drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 155 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 156 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 157 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 158 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 159 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 160 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 161 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 162 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 163 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 165 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 167                                 int wait_to_complete);
 168 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 169                                 struct rte_eth_stats *stats);
 170 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 171                                 struct rte_eth_xstats *xstats, unsigned n);
 172 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 173                                   struct rte_eth_xstats *xstats, unsigned n);
 174 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 177                                              uint16_t queue_id,
 178                                              uint8_t stat_idx,
 179                                              uint8_t is_rx);
 180 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 181                                struct rte_eth_dev_info *dev_info);
 182 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 183                                  struct rte_eth_dev_info *dev_info);
 184 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 185
 186 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 187                 uint16_t vlan_id, int on);
 188 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 189                                enum rte_vlan_type vlan_type,
 190                                uint16_t tpid_id);
 191 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 192                 uint16_t queue, bool on);
 193 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 194                 int on);
 195 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 220 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 221                 void *param);
 222 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 223 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 224                 uint32_t index, uint32_t pool);
 225 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 226 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 227                                            struct ether_addr *mac_addr);
 228 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 229
 230 /* For Virtual Function support */
 231 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 232 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 233 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 234 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 235 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 236 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 237 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 238 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 239 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 240                 struct rte_eth_stats *stats);
 241 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 242 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 243                 uint16_t vlan_id, int on);
 244 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 245                 uint16_t queue, int on);
 246 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 247 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 248 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                             uint16_t queue_id);
 250 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                              uint16_t queue_id);
 252 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 253                                  uint8_t queue, uint8_t msix_vector);
 254 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 255
 256 /* For Eth VMDQ APIs support */
 257 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 258                 ether_addr* mac_addr,uint8_t on);
 259 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 260 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 261                 uint16_t rx_mask, uint8_t on);
 262 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 263 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 264 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 265                 uint64_t pool_mask,uint8_t vlan_on);
 266 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 267                 struct rte_eth_mirror_conf *mirror_conf,
 268                 uint8_t rule_id, uint8_t on);
 269 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 270                 uint8_t rule_id);
 271 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                           uint16_t queue_id);
 273 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                            uint16_t queue_id);
 275 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 276                                uint8_t queue, uint8_t msix_vector);
 277 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 278
 279 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 280                 uint16_t queue_idx, uint16_t tx_rate);
 281 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 282                 uint16_t tx_rate, uint64_t q_msk);
 283
 284 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 285                                  struct ether_addr *mac_addr,
 286                                  uint32_t index, uint32_t pool);
 287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 289                                              struct ether_addr *mac_addr);
 290 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 291                         struct rte_eth_syn_filter *filter,
 292                         bool add);
 293 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 294                         struct rte_eth_syn_filter *filter);
 295 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 296                         enum rte_filter_op filter_op,
 297                         void *arg);
 298 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 299                         struct ixgbe_5tuple_filter *filter);
 300 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 301                         struct ixgbe_5tuple_filter *filter);
 302 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 303                         struct rte_eth_ntuple_filter *filter,
 304                         bool add);
 305 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 306                                 enum rte_filter_op filter_op,
 307                                 void *arg);
 308 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 309                         struct rte_eth_ntuple_filter *filter);
 310 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 311                         struct rte_eth_ethertype_filter *filter,
 312                         bool add);
 313 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 314                                 enum rte_filter_op filter_op,
 315                                 void *arg);
 316 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 317                         struct rte_eth_ethertype_filter *filter);
 318 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 319                      enum rte_filter_type filter_type,
 320                      enum rte_filter_op filter_op,
 321                      void *arg);
 322 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 323
 324 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 325                                       struct ether_addr *mc_addr_set,
 326                                       uint32_t nb_mc_addr);
 327 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                    struct rte_eth_dcb_info *dcb_info);
 329
 330 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 331 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 332                             struct rte_dev_reg_info *regs);
 333 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 334 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 335                                 struct rte_dev_eeprom_info *eeprom);
 336 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 337                                 struct rte_dev_eeprom_info *eeprom);
 338
 339 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 340 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 341                                 struct rte_dev_reg_info *regs);
 342
 343 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 344 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 345 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                             struct timespec *timestamp,
 347                                             uint32_t flags);
 348 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                             struct timespec *timestamp);
 350 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 351 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 352                                    struct timespec *timestamp);
 353 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 354                                    const struct timespec *timestamp);
 355
 356 static int ixgbe_dev_l2_tunnel_eth_type_conf
 357         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 358 static int ixgbe_dev_l2_tunnel_offload_set
 359         (struct rte_eth_dev *dev,
 360          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 361          uint32_t mask,
 362          uint8_t en);
 363 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 364                                              enum rte_filter_op filter_op,
 365                                              void *arg);
 366
 367 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 368                                          struct rte_eth_udp_tunnel *udp_tunnel);
 369 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 370                                          struct rte_eth_udp_tunnel *udp_tunnel);
 371
 372 /*
 373  * Define VF Stats MACRO for Non "cleared on read" register
 374  */
 375 #define UPDATE_VF_STAT(reg, last, cur)                          \
 376 {                                                               \
 377         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 378         cur += (latest - last) & UINT_MAX;                      \
 379         last = latest;                                          \
 380 }
 381
 382 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 383 {                                                                \
 384         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 385         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 386         u64 latest = ((new_msb << 32) | new_lsb);                \
 387         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 388         last = latest;                                           \
 389 }
 390
 391 #define IXGBE_SET_HWSTRIP(h, q) do{\
 392                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 393                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 394                 (h)->bitmap[idx] |= 1 << bit;\
 395         }while(0)
 396
 397 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 398                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 399                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 400                 (h)->bitmap[idx] &= ~(1 << bit);\
 401         }while(0)
 402
 403 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 404                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 405                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 406                 (r) = (h)->bitmap[idx] >> bit & 1;\
 407         }while(0)
 408
 409 /*
 410  * The set of PCI devices this driver supports
 411  */
 412 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 413
 414 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 415 #include "rte_pci_dev_ids.h"
 416
 417 { .vendor_id = 0, /* sentinel */ },
 418 };
 419
 420
 421 /*
 422  * The set of PCI devices this driver supports (for 82599 VF)
 423  */
 424 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 425
 426 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 427 #include "rte_pci_dev_ids.h"
 428 { .vendor_id = 0, /* sentinel */ },
 429
 430 };
 431
 432 static const struct rte_eth_desc_lim rx_desc_lim = {
 433         .nb_max = IXGBE_MAX_RING_DESC,
 434         .nb_min = IXGBE_MIN_RING_DESC,
 435         .nb_align = IXGBE_RXD_ALIGN,
 436 };
 437
 438 static const struct rte_eth_desc_lim tx_desc_lim = {
 439         .nb_max = IXGBE_MAX_RING_DESC,
 440         .nb_min = IXGBE_MIN_RING_DESC,
 441         .nb_align = IXGBE_TXD_ALIGN,
 442 };
 443
 444 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 445         .dev_configure        = ixgbe_dev_configure,
 446         .dev_start            = ixgbe_dev_start,
 447         .dev_stop             = ixgbe_dev_stop,
 448         .dev_set_link_up    = ixgbe_dev_set_link_up,
 449         .dev_set_link_down  = ixgbe_dev_set_link_down,
 450         .dev_close            = ixgbe_dev_close,
 451         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 452         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 453         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 454         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 455         .link_update          = ixgbe_dev_link_update,
 456         .stats_get            = ixgbe_dev_stats_get,
 457         .xstats_get           = ixgbe_dev_xstats_get,
 458         .stats_reset          = ixgbe_dev_stats_reset,
 459         .xstats_reset         = ixgbe_dev_xstats_reset,
 460         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 461         .dev_infos_get        = ixgbe_dev_info_get,
 462         .mtu_set              = ixgbe_dev_mtu_set,
 463         .vlan_filter_set      = ixgbe_vlan_filter_set,
 464         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 465         .vlan_offload_set     = ixgbe_vlan_offload_set,
 466         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 467         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 468         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 469         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 470         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 471         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 472         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 473         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 474         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 475         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 476         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 477         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 478         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 479         .dev_led_on           = ixgbe_dev_led_on,
 480         .dev_led_off          = ixgbe_dev_led_off,
 481         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 482         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 483         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 484         .mac_addr_add         = ixgbe_add_rar,
 485         .mac_addr_remove      = ixgbe_remove_rar,
 486         .mac_addr_set         = ixgbe_set_default_mac_addr,
 487         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 488         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 489         .mirror_rule_set      = ixgbe_mirror_rule_set,
 490         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 491         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 492         .set_vf_rx            = ixgbe_set_pool_rx,
 493         .set_vf_tx            = ixgbe_set_pool_tx,
 494         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 495         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 496         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 497         .reta_update          = ixgbe_dev_rss_reta_update,
 498         .reta_query           = ixgbe_dev_rss_reta_query,
 499 #ifdef RTE_NIC_BYPASS
 500         .bypass_init          = ixgbe_bypass_init,
 501         .bypass_state_set     = ixgbe_bypass_state_store,
 502         .bypass_state_show    = ixgbe_bypass_state_show,
 503         .bypass_event_set     = ixgbe_bypass_event_store,
 504         .bypass_event_show    = ixgbe_bypass_event_show,
 505         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 506         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 507         .bypass_ver_show      = ixgbe_bypass_ver_show,
 508         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 509 #endif /* RTE_NIC_BYPASS */
 510         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 511         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 512         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 513         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 514         .rxq_info_get         = ixgbe_rxq_info_get,
 515         .txq_info_get         = ixgbe_txq_info_get,
 516         .timesync_enable      = ixgbe_timesync_enable,
 517         .timesync_disable     = ixgbe_timesync_disable,
 518         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 519         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 520         .get_reg_length       = ixgbe_get_reg_length,
 521         .get_reg              = ixgbe_get_regs,
 522         .get_eeprom_length    = ixgbe_get_eeprom_length,
 523         .get_eeprom           = ixgbe_get_eeprom,
 524         .set_eeprom           = ixgbe_set_eeprom,
 525         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 526         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 527         .timesync_read_time   = ixgbe_timesync_read_time,
 528         .timesync_write_time  = ixgbe_timesync_write_time,
 529         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 530         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 531         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 532         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 533 };
 534
 535 /*
 536  * dev_ops for virtual function, bare necessities for basic vf
 537  * operation have been implemented
 538  */
 539 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 540         .dev_configure        = ixgbevf_dev_configure,
 541         .dev_start            = ixgbevf_dev_start,
 542         .dev_stop             = ixgbevf_dev_stop,
 543         .link_update          = ixgbe_dev_link_update,
 544         .stats_get            = ixgbevf_dev_stats_get,
 545         .xstats_get           = ixgbevf_dev_xstats_get,
 546         .stats_reset          = ixgbevf_dev_stats_reset,
 547         .xstats_reset         = ixgbevf_dev_stats_reset,
 548         .dev_close            = ixgbevf_dev_close,
 549         .dev_infos_get        = ixgbevf_dev_info_get,
 550         .mtu_set              = ixgbevf_dev_set_mtu,
 551         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 552         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 553         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 554         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 555         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 556         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 557         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 558         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 559         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 560         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 561         .mac_addr_add         = ixgbevf_add_mac_addr,
 562         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 563         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 564         .rxq_info_get         = ixgbe_rxq_info_get,
 565         .txq_info_get         = ixgbe_txq_info_get,
 566         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 567         .get_reg_length       = ixgbevf_get_reg_length,
 568         .get_reg              = ixgbevf_get_regs,
 569         .reta_update          = ixgbe_dev_rss_reta_update,
 570         .reta_query           = ixgbe_dev_rss_reta_query,
 571         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 572         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 573 };
 574
 575 /* store statistics names and its offset in stats structure */
 576 struct rte_ixgbe_xstats_name_off {
 577         char name[RTE_ETH_XSTATS_NAME_SIZE];
 578         unsigned offset;
 579 };
 580
 581 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 582         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 583         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 584         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 585         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 586         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 587         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 588         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 589         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 590         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 591         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 592         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 593         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 594         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 595         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 596         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 597                 prc1023)},
 598         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 599                 prc1522)},
 600         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 601         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 602         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 603         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 604         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 605         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 606         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 607         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 608         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 609         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 610         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 611         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 612         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 613         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 614         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 615         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 616         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 617                 ptc1023)},
 618         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 619                 ptc1522)},
 620         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 621         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 622         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 623         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 624
 625         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 626                 fdirustat_add)},
 627         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 628                 fdirustat_remove)},
 629         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 630                 fdirfstat_fadd)},
 631         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 632                 fdirfstat_fremove)},
 633         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 634                 fdirmatch)},
 635         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 636                 fdirmiss)},
 637
 638         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 639         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 640         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 641                 fclast)},
 642         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 643         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 644         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 645         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 646         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 647                 fcoe_noddp)},
 648         {"rx_fcoe_no_direct_data_placement_ext_buff",
 649                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 650
 651         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 652                 lxontxc)},
 653         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 654                 lxonrxc)},
 655         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 656                 lxofftxc)},
 657         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 658                 lxoffrxc)},
 659         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 660 };
 661
 662 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 663                            sizeof(rte_ixgbe_stats_strings[0]))
 664
 665 /* Per-queue statistics */
 666 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 667         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 668         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 669         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 670         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 671 };
 672
 673 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 674                            sizeof(rte_ixgbe_rxq_strings[0]))
 675
 676 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 677         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 678         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 679         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 680                 pxon2offc)},
 681 };
 682
 683 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 684                            sizeof(rte_ixgbe_txq_strings[0]))
 685
 686 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 687         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 688 };
 689
 690 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 691                 sizeof(rte_ixgbevf_stats_strings[0]))
 692
 693 /**
 694  * Atomically reads the link status information from global
 695  * structure rte_eth_dev.
 696  *
 697  * @param dev
 698  *   - Pointer to the structure rte_eth_dev to read from.
 699  *   - Pointer to the buffer to be saved with the link status.
 700  *
 701  * @return
 702  *   - On success, zero.
 703  *   - On failure, negative value.
 704  */
 705 static inline int
 706 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 707                                 struct rte_eth_link *link)
 708 {
 709         struct rte_eth_link *dst = link;
 710         struct rte_eth_link *src = &(dev->data->dev_link);
 711
 712         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 713                                         *(uint64_t *)src) == 0)
 714                 return -1;
 715
 716         return 0;
 717 }
 718
 719 /**
 720  * Atomically writes the link status information into global
 721  * structure rte_eth_dev.
 722  *
 723  * @param dev
 724  *   - Pointer to the structure rte_eth_dev to read from.
 725  *   - Pointer to the buffer to be saved with the link status.
 726  *
 727  * @return
 728  *   - On success, zero.
 729  *   - On failure, negative value.
 730  */
 731 static inline int
 732 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 733                                 struct rte_eth_link *link)
 734 {
 735         struct rte_eth_link *dst = &(dev->data->dev_link);
 736         struct rte_eth_link *src = link;
 737
 738         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 739                                         *(uint64_t *)src) == 0)
 740                 return -1;
 741
 742         return 0;
 743 }
 744
 745 /*
 746  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 747  */
 748 static inline int
 749 ixgbe_is_sfp(struct ixgbe_hw *hw)
 750 {
 751         switch (hw->phy.type) {
 752         case ixgbe_phy_sfp_avago:
 753         case ixgbe_phy_sfp_ftl:
 754         case ixgbe_phy_sfp_intel:
 755         case ixgbe_phy_sfp_unknown:
 756         case ixgbe_phy_sfp_passive_tyco:
 757         case ixgbe_phy_sfp_passive_unknown:
 758                 return 1;
 759         default:
 760                 return 0;
 761         }
 762 }
 763
 764 static inline int32_t
 765 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 766 {
 767         uint32_t ctrl_ext;
 768         int32_t status;
 769
 770         status = ixgbe_reset_hw(hw);
 771
 772         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 773         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 774         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 775         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 776         IXGBE_WRITE_FLUSH(hw);
 777
 778         return status;
 779 }
 780
 781 static inline void
 782 ixgbe_enable_intr(struct rte_eth_dev *dev)
 783 {
 784         struct ixgbe_interrupt *intr =
 785                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 786         struct ixgbe_hw *hw =
 787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 788
 789         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 790         IXGBE_WRITE_FLUSH(hw);
 791 }
 792
 793 /*
 794  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 795  */
 796 static void
 797 ixgbe_disable_intr(struct ixgbe_hw *hw)
 798 {
 799         PMD_INIT_FUNC_TRACE();
 800
 801         if (hw->mac.type == ixgbe_mac_82598EB) {
 802                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 803         } else {
 804                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 805                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 806                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 807         }
 808         IXGBE_WRITE_FLUSH(hw);
 809 }
 810
 811 /*
 812  * This function resets queue statistics mapping registers.
 813  * From Niantic datasheet, Initialization of Statistics section:
 814  * "...if software requires the queue counters, the RQSMR and TQSM registers
 815  * must be re-programmed following a device reset.
 816  */
 817 static void
 818 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 819 {
 820         uint32_t i;
 821
 822         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 823                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 824                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 825         }
 826 }
 827
 828
 829 static int
 830 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 831                                   uint16_t queue_id,
 832                                   uint8_t stat_idx,
 833                                   uint8_t is_rx)
 834 {
 835 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 836 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 837 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 838
 839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 840         struct ixgbe_stat_mapping_registers *stat_mappings =
 841                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 842         uint32_t qsmr_mask = 0;
 843         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 844         uint32_t q_map;
 845         uint8_t n, offset;
 846
 847         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 848                 (hw->mac.type != ixgbe_mac_X540) &&
 849                 (hw->mac.type != ixgbe_mac_X550) &&
 850                 (hw->mac.type != ixgbe_mac_X550EM_x))
 851                 return -ENOSYS;
 852
 853         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 854                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 855                      queue_id, stat_idx);
 856
 857         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 858         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 859                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 860                 return -EIO;
 861         }
 862         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 863
 864         /* Now clear any previous stat_idx set */
 865         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 866         if (!is_rx)
 867                 stat_mappings->tqsm[n] &= ~clearing_mask;
 868         else
 869                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 870
 871         q_map = (uint32_t)stat_idx;
 872         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 873         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 874         if (!is_rx)
 875                 stat_mappings->tqsm[n] |= qsmr_mask;
 876         else
 877                 stat_mappings->rqsmr[n] |= qsmr_mask;
 878
 879         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 880                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 881                      queue_id, stat_idx);
 882         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 883                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 884
 885         /* Now write the mapping in the appropriate register */
 886         if (is_rx) {
 887                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 888                              stat_mappings->rqsmr[n], n);
 889                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 890         }
 891         else {
 892                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 893                              stat_mappings->tqsm[n], n);
 894                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 895         }
 896         return 0;
 897 }
 898
 899 static void
 900 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 901 {
 902         struct ixgbe_stat_mapping_registers *stat_mappings =
 903                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 905         int i;
 906
 907         /* write whatever was in stat mapping table to the NIC */
 908         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 909                 /* rx */
 910                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 911
 912                 /* tx */
 913                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 914         }
 915 }
 916
 917 static void
 918 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 919 {
 920         uint8_t i;
 921         struct ixgbe_dcb_tc_config *tc;
 922         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 923
 924         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 925         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 926         for (i = 0; i < dcb_max_tc; i++) {
 927                 tc = &dcb_config->tc_config[i];
 928                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 929                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 930                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 931                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 932                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 933                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 934                 tc->pfc = ixgbe_dcb_pfc_disabled;
 935         }
 936
 937         /* Initialize default user to priority mapping, UPx->TC0 */
 938         tc = &dcb_config->tc_config[0];
 939         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 940         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 941         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 942                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 943                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 944         }
 945         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 946         dcb_config->pfc_mode_enable = false;
 947         dcb_config->vt_mode = true;
 948         dcb_config->round_robin_enable = false;
 949         /* support all DCB capabilities in 82599 */
 950         dcb_config->support.capabilities = 0xFF;
 951
 952         /*we only support 4 Tcs for X540, X550 */
 953         if (hw->mac.type == ixgbe_mac_X540 ||
 954                 hw->mac.type == ixgbe_mac_X550 ||
 955                 hw->mac.type == ixgbe_mac_X550EM_x) {
 956                 dcb_config->num_tcs.pg_tcs = 4;
 957                 dcb_config->num_tcs.pfc_tcs = 4;
 958         }
 959 }
 960
 961 /*
 962  * Ensure that all locks are released before first NVM or PHY access
 963  */
 964 static void
 965 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 966 {
 967         uint16_t mask;
 968
 969         /*
 970          * Phy lock should not fail in this early stage. If this is the case,
 971          * it is due to an improper exit of the application.
 972          * So force the release of the faulty lock. Release of common lock
 973          * is done automatically by swfw_sync function.
 974          */
 975         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 976         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 977                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 978         }
 979         ixgbe_release_swfw_semaphore(hw, mask);
 980
 981         /*
 982          * These ones are more tricky since they are common to all ports; but
 983          * swfw_sync retries last long enough (1s) to be almost sure that if
 984          * lock can not be taken it is due to an improper lock of the
 985          * semaphore.
 986          */
 987         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 988         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 989                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 990         }
 991         ixgbe_release_swfw_semaphore(hw, mask);
 992 }
 993
 994 /*
 995  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 996  * It returns 0 on success.
 997  */
 998 static int
 999 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1000 {
1001         struct rte_pci_device *pci_dev;
1002         struct ixgbe_hw *hw =
1003                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1004         struct ixgbe_vfta * shadow_vfta =
1005                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1006         struct ixgbe_hwstrip *hwstrip =
1007                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1008         struct ixgbe_dcb_config *dcb_config =
1009                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1010         struct ixgbe_filter_info *filter_info =
1011                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1012         uint32_t ctrl_ext;
1013         uint16_t csum;
1014         int diag, i;
1015
1016         PMD_INIT_FUNC_TRACE();
1017
1018         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1019         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1020         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1021
1022         /*
1023          * For secondary processes, we don't initialise any further as primary
1024          * has already done this work. Only check we don't need a different
1025          * RX and TX function.
1026          */
1027         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1028                 struct ixgbe_tx_queue *txq;
1029                 /* TX queue function in primary, set by last queue initialized
1030                  * Tx queue may not initialized by primary process */
1031                 if (eth_dev->data->tx_queues) {
1032                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1033                         ixgbe_set_tx_function(eth_dev, txq);
1034                 } else {
1035                         /* Use default TX function if we get here */
1036                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1037                                              "Using default TX function.");
1038                 }
1039
1040                 ixgbe_set_rx_function(eth_dev);
1041
1042                 return 0;
1043         }
1044         pci_dev = eth_dev->pci_dev;
1045
1046         rte_eth_copy_pci_info(eth_dev, pci_dev);
1047
1048         /* Vendor and Device ID need to be set before init of shared code */
1049         hw->device_id = pci_dev->id.device_id;
1050         hw->vendor_id = pci_dev->id.vendor_id;
1051         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1052         hw->allow_unsupported_sfp = 1;
1053
1054         /* Initialize the shared code (base driver) */
1055 #ifdef RTE_NIC_BYPASS
1056         diag = ixgbe_bypass_init_shared_code(hw);
1057 #else
1058         diag = ixgbe_init_shared_code(hw);
1059 #endif /* RTE_NIC_BYPASS */
1060
1061         if (diag != IXGBE_SUCCESS) {
1062                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1063                 return -EIO;
1064         }
1065
1066         /* pick up the PCI bus settings for reporting later */
1067         ixgbe_get_bus_info(hw);
1068
1069         /* Unlock any pending hardware semaphore */
1070         ixgbe_swfw_lock_reset(hw);
1071
1072         /* Initialize DCB configuration*/
1073         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1074         ixgbe_dcb_init(hw,dcb_config);
1075         /* Get Hardware Flow Control setting */
1076         hw->fc.requested_mode = ixgbe_fc_full;
1077         hw->fc.current_mode = ixgbe_fc_full;
1078         hw->fc.pause_time = IXGBE_FC_PAUSE;
1079         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1080                 hw->fc.low_water[i] = IXGBE_FC_LO;
1081                 hw->fc.high_water[i] = IXGBE_FC_HI;
1082         }
1083         hw->fc.send_xon = 1;
1084
1085         /* Make sure we have a good EEPROM before we read from it */
1086         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1087         if (diag != IXGBE_SUCCESS) {
1088                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1089                 return -EIO;
1090         }
1091
1092 #ifdef RTE_NIC_BYPASS
1093         diag = ixgbe_bypass_init_hw(hw);
1094 #else
1095         diag = ixgbe_init_hw(hw);
1096 #endif /* RTE_NIC_BYPASS */
1097
1098         /*
1099          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1100          * is called too soon after the kernel driver unbinding/binding occurs.
1101          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1102          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1103          * also called. See ixgbe_identify_phy_82599(). The reason for the
1104          * failure is not known, and only occuts when virtualisation features
1105          * are disabled in the bios. A delay of 100ms  was found to be enough by
1106          * trial-and-error, and is doubled to be safe.
1107          */
1108         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1109                 rte_delay_ms(200);
1110                 diag = ixgbe_init_hw(hw);
1111         }
1112
1113         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1114                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1115                     "LOM.  Please be aware there may be issues associated "
1116                     "with your hardware.");
1117                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1118                     "please contact your Intel or hardware representative "
1119                     "who provided you with this hardware.");
1120         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1121                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1122         if (diag) {
1123                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1124                 return -EIO;
1125         }
1126
1127         /* Reset the hw statistics */
1128         ixgbe_dev_stats_reset(eth_dev);
1129
1130         /* disable interrupt */
1131         ixgbe_disable_intr(hw);
1132
1133         /* reset mappings for queue statistics hw counters*/
1134         ixgbe_reset_qstat_mappings(hw);
1135
1136         /* Allocate memory for storing MAC addresses */
1137         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1138                         hw->mac.num_rar_entries, 0);
1139         if (eth_dev->data->mac_addrs == NULL) {
1140                 PMD_INIT_LOG(ERR,
1141                         "Failed to allocate %u bytes needed to store "
1142                         "MAC addresses",
1143                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1144                 return -ENOMEM;
1145         }
1146         /* Copy the permanent MAC address */
1147         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1148                         &eth_dev->data->mac_addrs[0]);
1149
1150         /* Allocate memory for storing hash filter MAC addresses */
1151         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1152                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1153         if (eth_dev->data->hash_mac_addrs == NULL) {
1154                 PMD_INIT_LOG(ERR,
1155                         "Failed to allocate %d bytes needed to store MAC addresses",
1156                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1157                 return -ENOMEM;
1158         }
1159
1160         /* initialize the vfta */
1161         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1162
1163         /* initialize the hw strip bitmap*/
1164         memset(hwstrip, 0, sizeof(*hwstrip));
1165
1166         /* initialize PF if max_vfs not zero */
1167         ixgbe_pf_host_init(eth_dev);
1168
1169         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1170         /* let hardware know driver is loaded */
1171         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1172         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1173         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1174         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1175         IXGBE_WRITE_FLUSH(hw);
1176
1177         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1178                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1179                              (int) hw->mac.type, (int) hw->phy.type,
1180                              (int) hw->phy.sfp_type);
1181         else
1182                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1183                              (int) hw->mac.type, (int) hw->phy.type);
1184
1185         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1186                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1187                         pci_dev->id.device_id);
1188
1189         rte_intr_callback_register(&pci_dev->intr_handle,
1190                                    ixgbe_dev_interrupt_handler,
1191                                    (void *)eth_dev);
1192
1193         /* enable uio/vfio intr/eventfd mapping */
1194         rte_intr_enable(&pci_dev->intr_handle);
1195
1196         /* enable support intr */
1197         ixgbe_enable_intr(eth_dev);
1198
1199         /* initialize 5tuple filter list */
1200         TAILQ_INIT(&filter_info->fivetuple_list);
1201         memset(filter_info->fivetuple_mask, 0,
1202                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1203
1204         return 0;
1205 }
1206
1207 static int
1208 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1209 {
1210         struct rte_pci_device *pci_dev;
1211         struct ixgbe_hw *hw;
1212
1213         PMD_INIT_FUNC_TRACE();
1214
1215         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1216                 return -EPERM;
1217
1218         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1219         pci_dev = eth_dev->pci_dev;
1220
1221         if (hw->adapter_stopped == 0)
1222                 ixgbe_dev_close(eth_dev);
1223
1224         eth_dev->dev_ops = NULL;
1225         eth_dev->rx_pkt_burst = NULL;
1226         eth_dev->tx_pkt_burst = NULL;
1227
1228         /* Unlock any pending hardware semaphore */
1229         ixgbe_swfw_lock_reset(hw);
1230
1231         /* disable uio intr before callback unregister */
1232         rte_intr_disable(&(pci_dev->intr_handle));
1233         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1234                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1235
1236         /* uninitialize PF if max_vfs not zero */
1237         ixgbe_pf_host_uninit(eth_dev);
1238
1239         rte_free(eth_dev->data->mac_addrs);
1240         eth_dev->data->mac_addrs = NULL;
1241
1242         rte_free(eth_dev->data->hash_mac_addrs);
1243         eth_dev->data->hash_mac_addrs = NULL;
1244
1245         return 0;
1246 }
1247
1248 /*
1249  * Negotiate mailbox API version with the PF.
1250  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1251  * Then we try to negotiate starting with the most recent one.
1252  * If all negotiation attempts fail, then we will proceed with
1253  * the default one (ixgbe_mbox_api_10).
1254  */
1255 static void
1256 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1257 {
1258         int32_t i;
1259
1260         /* start with highest supported, proceed down */
1261         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1262                 ixgbe_mbox_api_11,
1263                 ixgbe_mbox_api_10,
1264         };
1265
1266         for (i = 0;
1267                         i != RTE_DIM(sup_ver) &&
1268                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1269                         i++)
1270                 ;
1271 }
1272
1273 static void
1274 generate_random_mac_addr(struct ether_addr *mac_addr)
1275 {
1276         uint64_t random;
1277
1278         /* Set Organizationally Unique Identifier (OUI) prefix. */
1279         mac_addr->addr_bytes[0] = 0x00;
1280         mac_addr->addr_bytes[1] = 0x09;
1281         mac_addr->addr_bytes[2] = 0xC0;
1282         /* Force indication of locally assigned MAC address. */
1283         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1284         /* Generate the last 3 bytes of the MAC address with a random number. */
1285         random = rte_rand();
1286         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1287 }
1288
1289 /*
1290  * Virtual Function device init
1291  */
1292 static int
1293 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1294 {
1295         int diag;
1296         uint32_t tc, tcs;
1297         struct rte_pci_device *pci_dev;
1298         struct ixgbe_hw *hw =
1299                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1300         struct ixgbe_vfta * shadow_vfta =
1301                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1302         struct ixgbe_hwstrip *hwstrip =
1303                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1304         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1305
1306         PMD_INIT_FUNC_TRACE();
1307
1308         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1309         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1310         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1311
1312         /* for secondary processes, we don't initialise any further as primary
1313          * has already done this work. Only check we don't need a different
1314          * RX function */
1315         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1316                 if (eth_dev->data->scattered_rx)
1317                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1318                 return 0;
1319         }
1320
1321         pci_dev = eth_dev->pci_dev;
1322
1323         rte_eth_copy_pci_info(eth_dev, pci_dev);
1324
1325         hw->device_id = pci_dev->id.device_id;
1326         hw->vendor_id = pci_dev->id.vendor_id;
1327         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1328
1329         /* initialize the vfta */
1330         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1331
1332         /* initialize the hw strip bitmap*/
1333         memset(hwstrip, 0, sizeof(*hwstrip));
1334
1335         /* Initialize the shared code (base driver) */
1336         diag = ixgbe_init_shared_code(hw);
1337         if (diag != IXGBE_SUCCESS) {
1338                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1339                 return -EIO;
1340         }
1341
1342         /* init_mailbox_params */
1343         hw->mbx.ops.init_params(hw);
1344
1345         /* Reset the hw statistics */
1346         ixgbevf_dev_stats_reset(eth_dev);
1347
1348         /* Disable the interrupts for VF */
1349         ixgbevf_intr_disable(hw);
1350
1351         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1352         diag = hw->mac.ops.reset_hw(hw);
1353
1354         /*
1355          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1356          * the underlying PF driver has not assigned a MAC address to the VF.
1357          * In this case, assign a random MAC address.
1358          */
1359         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1360                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1361                 return diag;
1362         }
1363
1364         /* negotiate mailbox API version to use with the PF. */
1365         ixgbevf_negotiate_api(hw);
1366
1367         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1368         ixgbevf_get_queues(hw, &tcs, &tc);
1369
1370         /* Allocate memory for storing MAC addresses */
1371         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1372                         hw->mac.num_rar_entries, 0);
1373         if (eth_dev->data->mac_addrs == NULL) {
1374                 PMD_INIT_LOG(ERR,
1375                         "Failed to allocate %u bytes needed to store "
1376                         "MAC addresses",
1377                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1378                 return -ENOMEM;
1379         }
1380
1381         /* Generate a random MAC address, if none was assigned by PF. */
1382         if (is_zero_ether_addr(perm_addr)) {
1383                 generate_random_mac_addr(perm_addr);
1384                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1385                 if (diag) {
1386                         rte_free(eth_dev->data->mac_addrs);
1387                         eth_dev->data->mac_addrs = NULL;
1388                         return diag;
1389                 }
1390                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1391                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1392                              "%02x:%02x:%02x:%02x:%02x:%02x",
1393                              perm_addr->addr_bytes[0],
1394                              perm_addr->addr_bytes[1],
1395                              perm_addr->addr_bytes[2],
1396                              perm_addr->addr_bytes[3],
1397                              perm_addr->addr_bytes[4],
1398                              perm_addr->addr_bytes[5]);
1399         }
1400
1401         /* Copy the permanent MAC address */
1402         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1403
1404         /* reset the hardware with the new settings */
1405         diag = hw->mac.ops.start_hw(hw);
1406         switch (diag) {
1407                 case  0:
1408                         break;
1409
1410                 default:
1411                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1412                         return -EIO;
1413         }
1414
1415         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1416                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1417                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1418
1419         return 0;
1420 }
1421
1422 /* Virtual Function device uninit */
1423
1424 static int
1425 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1426 {
1427         struct ixgbe_hw *hw;
1428         unsigned i;
1429
1430         PMD_INIT_FUNC_TRACE();
1431
1432         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1433                 return -EPERM;
1434
1435         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1436
1437         if (hw->adapter_stopped == 0)
1438                 ixgbevf_dev_close(eth_dev);
1439
1440         eth_dev->dev_ops = NULL;
1441         eth_dev->rx_pkt_burst = NULL;
1442         eth_dev->tx_pkt_burst = NULL;
1443
1444         /* Disable the interrupts for VF */
1445         ixgbevf_intr_disable(hw);
1446
1447         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1448                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1449                 eth_dev->data->rx_queues[i] = NULL;
1450         }
1451         eth_dev->data->nb_rx_queues = 0;
1452
1453         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1454                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1455                 eth_dev->data->tx_queues[i] = NULL;
1456         }
1457         eth_dev->data->nb_tx_queues = 0;
1458
1459         rte_free(eth_dev->data->mac_addrs);
1460         eth_dev->data->mac_addrs = NULL;
1461
1462         return 0;
1463 }
1464
1465 static struct eth_driver rte_ixgbe_pmd = {
1466         .pci_drv = {
1467                 .name = "rte_ixgbe_pmd",
1468                 .id_table = pci_id_ixgbe_map,
1469                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1470                         RTE_PCI_DRV_DETACHABLE,
1471         },
1472         .eth_dev_init = eth_ixgbe_dev_init,
1473         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1474         .dev_private_size = sizeof(struct ixgbe_adapter),
1475 };
1476
1477 /*
1478  * virtual function driver struct
1479  */
1480 static struct eth_driver rte_ixgbevf_pmd = {
1481         .pci_drv = {
1482                 .name = "rte_ixgbevf_pmd",
1483                 .id_table = pci_id_ixgbevf_map,
1484                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1485         },
1486         .eth_dev_init = eth_ixgbevf_dev_init,
1487         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1488         .dev_private_size = sizeof(struct ixgbe_adapter),
1489 };
1490
1491 /*
1492  * Driver initialization routine.
1493  * Invoked once at EAL init time.
1494  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1495  */
1496 static int
1497 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1498 {
1499         PMD_INIT_FUNC_TRACE();
1500
1501         rte_eth_driver_register(&rte_ixgbe_pmd);
1502         return 0;
1503 }
1504
1505 /*
1506  * VF Driver initialization routine.
1507  * Invoked one at EAL init time.
1508  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1509  */
1510 static int
1511 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1512 {
1513         PMD_INIT_FUNC_TRACE();
1514
1515         rte_eth_driver_register(&rte_ixgbevf_pmd);
1516         return 0;
1517 }
1518
1519 static int
1520 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1521 {
1522         struct ixgbe_hw *hw =
1523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524         struct ixgbe_vfta * shadow_vfta =
1525                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1526         uint32_t vfta;
1527         uint32_t vid_idx;
1528         uint32_t vid_bit;
1529
1530         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1531         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1532         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1533         if (on)
1534                 vfta |= vid_bit;
1535         else
1536                 vfta &= ~vid_bit;
1537         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1538
1539         /* update local VFTA copy */
1540         shadow_vfta->vfta[vid_idx] = vfta;
1541
1542         return 0;
1543 }
1544
1545 static void
1546 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1547 {
1548         if (on)
1549                 ixgbe_vlan_hw_strip_enable(dev, queue);
1550         else
1551                 ixgbe_vlan_hw_strip_disable(dev, queue);
1552 }
1553
1554 static int
1555 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1556                     enum rte_vlan_type vlan_type,
1557                     uint16_t tpid)
1558 {
1559         struct ixgbe_hw *hw =
1560                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1561         int ret = 0;
1562
1563         switch (vlan_type) {
1564         case ETH_VLAN_TYPE_INNER:
1565                 /* Only the high 16-bits is valid */
1566                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1567                 break;
1568         default:
1569                 ret = -EINVAL;
1570                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1571                 break;
1572         }
1573
1574         return ret;
1575 }
1576
1577 void
1578 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1579 {
1580         struct ixgbe_hw *hw =
1581                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582         uint32_t vlnctrl;
1583
1584         PMD_INIT_FUNC_TRACE();
1585
1586         /* Filter Table Disable */
1587         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1588         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1589
1590         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1591 }
1592
1593 void
1594 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1595 {
1596         struct ixgbe_hw *hw =
1597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598         struct ixgbe_vfta * shadow_vfta =
1599                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1600         uint32_t vlnctrl;
1601         uint16_t i;
1602
1603         PMD_INIT_FUNC_TRACE();
1604
1605         /* Filter Table Enable */
1606         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1607         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1608         vlnctrl |= IXGBE_VLNCTRL_VFE;
1609
1610         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1611
1612         /* write whatever is in local vfta copy */
1613         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1614                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1615 }
1616
1617 static void
1618 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1619 {
1620         struct ixgbe_hwstrip *hwstrip =
1621                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1622
1623         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1624                 return;
1625
1626         if (on)
1627                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1628         else
1629                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1630 }
1631
1632 static void
1633 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1634 {
1635         struct ixgbe_hw *hw =
1636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637         uint32_t ctrl;
1638
1639         PMD_INIT_FUNC_TRACE();
1640
1641         if (hw->mac.type == ixgbe_mac_82598EB) {
1642                 /* No queue level support */
1643                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1644                 return;
1645         }
1646         else {
1647                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1648                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1649                 ctrl &= ~IXGBE_RXDCTL_VME;
1650                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1651         }
1652         /* record those setting for HW strip per queue */
1653         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1654 }
1655
1656 static void
1657 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1658 {
1659         struct ixgbe_hw *hw =
1660                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1661         uint32_t ctrl;
1662
1663         PMD_INIT_FUNC_TRACE();
1664
1665         if (hw->mac.type == ixgbe_mac_82598EB) {
1666                 /* No queue level supported */
1667                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1668                 return;
1669         }
1670         else {
1671                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1672                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1673                 ctrl |= IXGBE_RXDCTL_VME;
1674                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1675         }
1676         /* record those setting for HW strip per queue */
1677         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1678 }
1679
1680 void
1681 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1682 {
1683         struct ixgbe_hw *hw =
1684                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         uint32_t ctrl;
1686         uint16_t i;
1687
1688         PMD_INIT_FUNC_TRACE();
1689
1690         if (hw->mac.type == ixgbe_mac_82598EB) {
1691                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1692                 ctrl &= ~IXGBE_VLNCTRL_VME;
1693                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1694         }
1695         else {
1696                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1697                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1698                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1699                         ctrl &= ~IXGBE_RXDCTL_VME;
1700                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1701
1702                         /* record those setting for HW strip per queue */
1703                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1704                 }
1705         }
1706 }
1707
1708 void
1709 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1710 {
1711         struct ixgbe_hw *hw =
1712                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1713         uint32_t ctrl;
1714         uint16_t i;
1715
1716         PMD_INIT_FUNC_TRACE();
1717
1718         if (hw->mac.type == ixgbe_mac_82598EB) {
1719                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1720                 ctrl |= IXGBE_VLNCTRL_VME;
1721                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1722         }
1723         else {
1724                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1725                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1726                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1727                         ctrl |= IXGBE_RXDCTL_VME;
1728                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1729
1730                         /* record those setting for HW strip per queue */
1731                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1732                 }
1733         }
1734 }
1735
1736 static void
1737 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1738 {
1739         struct ixgbe_hw *hw =
1740                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1741         uint32_t ctrl;
1742
1743         PMD_INIT_FUNC_TRACE();
1744
1745         /* DMATXCTRL: Geric Double VLAN Disable */
1746         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1747         ctrl &= ~IXGBE_DMATXCTL_GDV;
1748         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1749
1750         /* CTRL_EXT: Global Double VLAN Disable */
1751         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1752         ctrl &= ~IXGBE_EXTENDED_VLAN;
1753         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1754
1755 }
1756
1757 static void
1758 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1759 {
1760         struct ixgbe_hw *hw =
1761                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1762         uint32_t ctrl;
1763
1764         PMD_INIT_FUNC_TRACE();
1765
1766         /* DMATXCTRL: Geric Double VLAN Enable */
1767         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1768         ctrl |= IXGBE_DMATXCTL_GDV;
1769         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1770
1771         /* CTRL_EXT: Global Double VLAN Enable */
1772         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1773         ctrl |= IXGBE_EXTENDED_VLAN;
1774         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1775
1776         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1777         if (hw->mac.type == ixgbe_mac_X550 ||
1778             hw->mac.type == ixgbe_mac_X550EM_x) {
1779                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1780                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1781                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1782         }
1783
1784         /*
1785          * VET EXT field in the EXVET register = 0x8100 by default
1786          * So no need to change. Same to VT field of DMATXCTL register
1787          */
1788 }
1789
1790 static void
1791 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1792 {
1793         if(mask & ETH_VLAN_STRIP_MASK){
1794                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1795                         ixgbe_vlan_hw_strip_enable_all(dev);
1796                 else
1797                         ixgbe_vlan_hw_strip_disable_all(dev);
1798         }
1799
1800         if(mask & ETH_VLAN_FILTER_MASK){
1801                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1802                         ixgbe_vlan_hw_filter_enable(dev);
1803                 else
1804                         ixgbe_vlan_hw_filter_disable(dev);
1805         }
1806
1807         if(mask & ETH_VLAN_EXTEND_MASK){
1808                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1809                         ixgbe_vlan_hw_extend_enable(dev);
1810                 else
1811                         ixgbe_vlan_hw_extend_disable(dev);
1812         }
1813 }
1814
1815 static void
1816 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1817 {
1818         struct ixgbe_hw *hw =
1819                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1820         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1821         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1822         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1823         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1824 }
1825
1826 static int
1827 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1828 {
1829         switch (nb_rx_q) {
1830         case 1:
1831         case 2:
1832                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1833                 break;
1834         case 4:
1835                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1836                 break;
1837         default:
1838                 return -EINVAL;
1839         }
1840
1841         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1842         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1843
1844         return 0;
1845 }
1846
1847 static int
1848 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1849 {
1850         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1851         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1852         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1853
1854         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1855                 /* check multi-queue mode */
1856                 switch (dev_conf->rxmode.mq_mode) {
1857                 case ETH_MQ_RX_VMDQ_DCB:
1858                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1859                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1860                         PMD_INIT_LOG(ERR, "SRIOV active,"
1861                                         " unsupported mq_mode rx %d.",
1862                                         dev_conf->rxmode.mq_mode);
1863                         return -EINVAL;
1864                 case ETH_MQ_RX_RSS:
1865                 case ETH_MQ_RX_VMDQ_RSS:
1866                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1867                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1868                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1869                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1870                                                 " invalid queue number"
1871                                                 " for VMDQ RSS, allowed"
1872                                                 " value are 1, 2 or 4.");
1873                                         return -EINVAL;
1874                                 }
1875                         break;
1876                 case ETH_MQ_RX_VMDQ_ONLY:
1877                 case ETH_MQ_RX_NONE:
1878                         /* if nothing mq mode configure, use default scheme */
1879                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1880                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1881                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1882                         break;
1883                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1884                         /* SRIOV only works in VMDq enable mode */
1885                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1886                                         " wrong mq_mode rx %d.",
1887                                         dev_conf->rxmode.mq_mode);
1888                         return -EINVAL;
1889                 }
1890
1891                 switch (dev_conf->txmode.mq_mode) {
1892                 case ETH_MQ_TX_VMDQ_DCB:
1893                         /* DCB VMDQ in SRIOV mode, not implement yet */
1894                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1895                                         " unsupported VMDQ mq_mode tx %d.",
1896                                         dev_conf->txmode.mq_mode);
1897                         return -EINVAL;
1898                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1899                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1900                         break;
1901                 }
1902
1903                 /* check valid queue number */
1904                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1905                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1906                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1907                                         " queue number must less equal to %d.",
1908                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1909                         return -EINVAL;
1910                 }
1911         } else {
1912                 /* check configuration for vmdb+dcb mode */
1913                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1914                         const struct rte_eth_vmdq_dcb_conf *conf;
1915
1916                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1917                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1918                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1919                                 return -EINVAL;
1920                         }
1921                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1922                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1923                                conf->nb_queue_pools == ETH_32_POOLS)) {
1924                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1925                                                 " nb_queue_pools must be %d or %d.",
1926                                                 ETH_16_POOLS, ETH_32_POOLS);
1927                                 return -EINVAL;
1928                         }
1929                 }
1930                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1931                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1932
1933                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1934                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1935                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1936                                 return -EINVAL;
1937                         }
1938                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1939                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1940                                conf->nb_queue_pools == ETH_32_POOLS)) {
1941                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1942                                                 " nb_queue_pools != %d and"
1943                                                 " nb_queue_pools != %d.",
1944                                                 ETH_16_POOLS, ETH_32_POOLS);
1945                                 return -EINVAL;
1946                         }
1947                 }
1948
1949                 /* For DCB mode check our configuration before we go further */
1950                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1951                         const struct rte_eth_dcb_rx_conf *conf;
1952
1953                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1954                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1955                                                  IXGBE_DCB_NB_QUEUES);
1956                                 return -EINVAL;
1957                         }
1958                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1959                         if (!(conf->nb_tcs == ETH_4_TCS ||
1960                                conf->nb_tcs == ETH_8_TCS)) {
1961                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1962                                                 " and nb_tcs != %d.",
1963                                                 ETH_4_TCS, ETH_8_TCS);
1964                                 return -EINVAL;
1965                         }
1966                 }
1967
1968                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1969                         const struct rte_eth_dcb_tx_conf *conf;
1970
1971                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1972                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1973                                                  IXGBE_DCB_NB_QUEUES);
1974                                 return -EINVAL;
1975                         }
1976                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1977                         if (!(conf->nb_tcs == ETH_4_TCS ||
1978                                conf->nb_tcs == ETH_8_TCS)) {
1979                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1980                                                 " and nb_tcs != %d.",
1981                                                 ETH_4_TCS, ETH_8_TCS);
1982                                 return -EINVAL;
1983                         }
1984                 }
1985         }
1986         return 0;
1987 }
1988
1989 static int
1990 ixgbe_dev_configure(struct rte_eth_dev *dev)
1991 {
1992         struct ixgbe_interrupt *intr =
1993                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1994         struct ixgbe_adapter *adapter =
1995                 (struct ixgbe_adapter *)dev->data->dev_private;
1996         int ret;
1997
1998         PMD_INIT_FUNC_TRACE();
1999         /* multipe queue mode checking */
2000         ret  = ixgbe_check_mq_mode(dev);
2001         if (ret != 0) {
2002                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2003                             ret);
2004                 return ret;
2005         }
2006
2007         /* set flag to update link status after init */
2008         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2009
2010         /*
2011          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2012          * allocation or vector Rx preconditions we will reset it.
2013          */
2014         adapter->rx_bulk_alloc_allowed = true;
2015         adapter->rx_vec_allowed = true;
2016
2017         return 0;
2018 }
2019
2020 /*
2021  * Configure device link speed and setup link.
2022  * It returns 0 on success.
2023  */
2024 static int
2025 ixgbe_dev_start(struct rte_eth_dev *dev)
2026 {
2027         struct ixgbe_hw *hw =
2028                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029         struct ixgbe_vf_info *vfinfo =
2030                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2031         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2032         uint32_t intr_vector = 0;
2033         int err, link_up = 0, negotiate = 0;
2034         uint32_t speed = 0;
2035         int mask = 0;
2036         int status;
2037         uint16_t vf, idx;
2038
2039         PMD_INIT_FUNC_TRACE();
2040
2041         /* IXGBE devices don't support half duplex */
2042         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2043                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2044                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2045                              dev->data->dev_conf.link_duplex,
2046                              dev->data->port_id);
2047                 return -EINVAL;
2048         }
2049
2050         /* disable uio/vfio intr/eventfd mapping */
2051         rte_intr_disable(intr_handle);
2052
2053         /* stop adapter */
2054         hw->adapter_stopped = 0;
2055         ixgbe_stop_adapter(hw);
2056
2057         /* reinitialize adapter
2058          * this calls reset and start */
2059         status = ixgbe_pf_reset_hw(hw);
2060         if (status != 0)
2061                 return -1;
2062         hw->mac.ops.start_hw(hw);
2063         hw->mac.get_link_status = true;
2064
2065         /* configure PF module if SRIOV enabled */
2066         ixgbe_pf_host_configure(dev);
2067
2068         /* check and configure queue intr-vector mapping */
2069         if ((rte_intr_cap_multiple(intr_handle) ||
2070              !RTE_ETH_DEV_SRIOV(dev).active) &&
2071             dev->data->dev_conf.intr_conf.rxq != 0) {
2072                 intr_vector = dev->data->nb_rx_queues;
2073                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2074                         return -1;
2075         }
2076
2077         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2078                 intr_handle->intr_vec =
2079                         rte_zmalloc("intr_vec",
2080                                     dev->data->nb_rx_queues * sizeof(int), 0);
2081                 if (intr_handle->intr_vec == NULL) {
2082                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2083                                      " intr_vec\n", dev->data->nb_rx_queues);
2084                         return -ENOMEM;
2085                 }
2086         }
2087
2088         /* confiugre msix for sleep until rx interrupt */
2089         ixgbe_configure_msix(dev);
2090
2091         /* initialize transmission unit */
2092         ixgbe_dev_tx_init(dev);
2093
2094         /* This can fail when allocating mbufs for descriptor rings */
2095         err = ixgbe_dev_rx_init(dev);
2096         if (err) {
2097                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2098                 goto error;
2099         }
2100
2101         err = ixgbe_dev_rxtx_start(dev);
2102         if (err < 0) {
2103                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2104                 goto error;
2105         }
2106
2107         /* Skip link setup if loopback mode is enabled for 82599. */
2108         if (hw->mac.type == ixgbe_mac_82599EB &&
2109                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2110                 goto skip_link_setup;
2111
2112         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2113                 err = hw->mac.ops.setup_sfp(hw);
2114                 if (err)
2115                         goto error;
2116         }
2117
2118         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2119                 /* Turn on the copper */
2120                 ixgbe_set_phy_power(hw, true);
2121         } else {
2122                 /* Turn on the laser */
2123                 ixgbe_enable_tx_laser(hw);
2124         }
2125
2126         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2127         if (err)
2128                 goto error;
2129         dev->data->dev_link.link_status = link_up;
2130
2131         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2132         if (err)
2133                 goto error;
2134
2135         switch(dev->data->dev_conf.link_speed) {
2136         case ETH_LINK_SPEED_AUTONEG:
2137                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2138                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2139                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2140                 break;
2141         case ETH_LINK_SPEED_100:
2142                 /*
2143                  * Invalid for 82598 but error will be detected by
2144                  * ixgbe_setup_link()
2145                  */
2146                 speed = IXGBE_LINK_SPEED_100_FULL;
2147                 break;
2148         case ETH_LINK_SPEED_1000:
2149                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2150                 break;
2151         case ETH_LINK_SPEED_10000:
2152                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2153                 break;
2154         default:
2155                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2156                              dev->data->dev_conf.link_speed,
2157                              dev->data->port_id);
2158                 goto error;
2159         }
2160
2161         err = ixgbe_setup_link(hw, speed, link_up);
2162         if (err)
2163                 goto error;
2164
2165 skip_link_setup:
2166
2167         if (rte_intr_allow_others(intr_handle)) {
2168                 /* check if lsc interrupt is enabled */
2169                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2170                         ixgbe_dev_lsc_interrupt_setup(dev);
2171         } else {
2172                 rte_intr_callback_unregister(intr_handle,
2173                                              ixgbe_dev_interrupt_handler,
2174                                              (void *)dev);
2175                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2176                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2177                                      " no intr multiplex\n");
2178         }
2179
2180         /* check if rxq interrupt is enabled */
2181         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2182             rte_intr_dp_is_en(intr_handle))
2183                 ixgbe_dev_rxq_interrupt_setup(dev);
2184
2185         /* enable uio/vfio intr/eventfd mapping */
2186         rte_intr_enable(intr_handle);
2187
2188         /* resume enabled intr since hw reset */
2189         ixgbe_enable_intr(dev);
2190
2191         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2192                 ETH_VLAN_EXTEND_MASK;
2193         ixgbe_vlan_offload_set(dev, mask);
2194
2195         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2196                 /* Enable vlan filtering for VMDq */
2197                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2198         }
2199
2200         /* Configure DCB hw */
2201         ixgbe_configure_dcb(dev);
2202
2203         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2204                 err = ixgbe_fdir_configure(dev);
2205                 if (err)
2206                         goto error;
2207         }
2208
2209         /* Restore vf rate limit */
2210         if (vfinfo != NULL) {
2211                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2212                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2213                                 if (vfinfo[vf].tx_rate[idx] != 0)
2214                                         ixgbe_set_vf_rate_limit(dev, vf,
2215                                                 vfinfo[vf].tx_rate[idx],
2216                                                 1 << idx);
2217         }
2218
2219         ixgbe_restore_statistics_mapping(dev);
2220
2221         return 0;
2222
2223 error:
2224         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2225         ixgbe_dev_clear_queues(dev);
2226         return -EIO;
2227 }
2228
2229 /*
2230  * Stop device: disable rx and tx functions to allow for reconfiguring.
2231  */
2232 static void
2233 ixgbe_dev_stop(struct rte_eth_dev *dev)
2234 {
2235         struct rte_eth_link link;
2236         struct ixgbe_hw *hw =
2237                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238         struct ixgbe_vf_info *vfinfo =
2239                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2240         struct ixgbe_filter_info *filter_info =
2241                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2242         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2243         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2244         int vf;
2245
2246         PMD_INIT_FUNC_TRACE();
2247
2248         /* disable interrupts */
2249         ixgbe_disable_intr(hw);
2250
2251         /* disable intr eventfd mapping */
2252         rte_intr_disable(intr_handle);
2253
2254         /* reset the NIC */
2255         ixgbe_pf_reset_hw(hw);
2256         hw->adapter_stopped = 0;
2257
2258         /* stop adapter */
2259         ixgbe_stop_adapter(hw);
2260
2261         for (vf = 0; vfinfo != NULL &&
2262                      vf < dev->pci_dev->max_vfs; vf++)
2263                 vfinfo[vf].clear_to_send = false;
2264
2265         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2266                 /* Turn off the copper */
2267                 ixgbe_set_phy_power(hw, false);
2268         } else {
2269                 /* Turn off the laser */
2270                 ixgbe_disable_tx_laser(hw);
2271         }
2272
2273         ixgbe_dev_clear_queues(dev);
2274
2275         /* Clear stored conf */
2276         dev->data->scattered_rx = 0;
2277         dev->data->lro = 0;
2278
2279         /* Clear recorded link status */
2280         memset(&link, 0, sizeof(link));
2281         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2282
2283         /* Remove all ntuple filters of the device */
2284         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2285              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2286                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2287                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2288                              p_5tuple, entries);
2289                 rte_free(p_5tuple);
2290         }
2291         memset(filter_info->fivetuple_mask, 0,
2292                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2293
2294         if (!rte_intr_allow_others(intr_handle))
2295                 /* resume to the default handler */
2296                 rte_intr_callback_register(intr_handle,
2297                                            ixgbe_dev_interrupt_handler,
2298                                            (void *)dev);
2299
2300         /* Clean datapath event and queue/vec mapping */
2301         rte_intr_efd_disable(intr_handle);
2302         if (intr_handle->intr_vec != NULL) {
2303                 rte_free(intr_handle->intr_vec);
2304                 intr_handle->intr_vec = NULL;
2305         }
2306 }
2307
2308 /*
2309  * Set device link up: enable tx.
2310  */
2311 static int
2312 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2313 {
2314         struct ixgbe_hw *hw =
2315                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316         if (hw->mac.type == ixgbe_mac_82599EB) {
2317 #ifdef RTE_NIC_BYPASS
2318                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2319                         /* Not suported in bypass mode */
2320                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2321                                      "by device id 0x%x", hw->device_id);
2322                         return -ENOTSUP;
2323                 }
2324 #endif
2325         }
2326
2327         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2328                 /* Turn on the copper */
2329                 ixgbe_set_phy_power(hw, true);
2330         } else {
2331                 /* Turn on the laser */
2332                 ixgbe_enable_tx_laser(hw);
2333         }
2334
2335         return 0;
2336 }
2337
2338 /*
2339  * Set device link down: disable tx.
2340  */
2341 static int
2342 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2343 {
2344         struct ixgbe_hw *hw =
2345                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2346         if (hw->mac.type == ixgbe_mac_82599EB) {
2347 #ifdef RTE_NIC_BYPASS
2348                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2349                         /* Not suported in bypass mode */
2350                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2351                                      "by device id 0x%x", hw->device_id);
2352                         return -ENOTSUP;
2353                 }
2354 #endif
2355         }
2356
2357         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2358                 /* Turn off the copper */
2359                 ixgbe_set_phy_power(hw, false);
2360         } else {
2361                 /* Turn off the laser */
2362                 ixgbe_disable_tx_laser(hw);
2363         }
2364
2365         return 0;
2366 }
2367
2368 /*
2369  * Reest and stop device.
2370  */
2371 static void
2372 ixgbe_dev_close(struct rte_eth_dev *dev)
2373 {
2374         struct ixgbe_hw *hw =
2375                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2376
2377         PMD_INIT_FUNC_TRACE();
2378
2379         ixgbe_pf_reset_hw(hw);
2380
2381         ixgbe_dev_stop(dev);
2382         hw->adapter_stopped = 1;
2383
2384         ixgbe_dev_free_queues(dev);
2385
2386         ixgbe_disable_pcie_master(hw);
2387
2388         /* reprogram the RAR[0] in case user changed it. */
2389         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2390 }
2391
2392 static void
2393 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2394                            struct ixgbe_hw_stats *hw_stats,
2395                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2396                            uint64_t *total_qprc, uint64_t *total_qprdc)
2397 {
2398         uint32_t bprc, lxon, lxoff, total;
2399         uint32_t delta_gprc = 0;
2400         unsigned i;
2401         /* Workaround for RX byte count not including CRC bytes when CRC
2402 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2403          * is disabled.
2404 +        */
2405         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2406                         IXGBE_HLREG0_RXCRCSTRP);
2407
2408         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2409         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2410         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2411         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2412
2413         for (i = 0; i < 8; i++) {
2414                 uint32_t mp;
2415                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2416                 /* global total per queue */
2417                 hw_stats->mpc[i] += mp;
2418                 /* Running comprehensive total for stats display */
2419                 *total_missed_rx += hw_stats->mpc[i];
2420                 if (hw->mac.type == ixgbe_mac_82598EB) {
2421                         hw_stats->rnbc[i] +=
2422                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2423                         hw_stats->pxonrxc[i] +=
2424                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2425                         hw_stats->pxoffrxc[i] +=
2426                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2427                 } else {
2428                         hw_stats->pxonrxc[i] +=
2429                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2430                         hw_stats->pxoffrxc[i] +=
2431                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2432                         hw_stats->pxon2offc[i] +=
2433                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2434                 }
2435                 hw_stats->pxontxc[i] +=
2436                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2437                 hw_stats->pxofftxc[i] +=
2438                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2439         }
2440         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2441                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2442                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2443                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2444
2445                 delta_gprc += delta_qprc;
2446
2447                 hw_stats->qprc[i] += delta_qprc;
2448                 hw_stats->qptc[i] += delta_qptc;
2449
2450                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2451                 hw_stats->qbrc[i] +=
2452                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2453                 if (crc_strip == 0)
2454                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2455
2456                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2457                 hw_stats->qbtc[i] +=
2458                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2459
2460                 hw_stats->qprdc[i] += delta_qprdc;
2461                 *total_qprdc += hw_stats->qprdc[i];
2462
2463                 *total_qprc += hw_stats->qprc[i];
2464                 *total_qbrc += hw_stats->qbrc[i];
2465         }
2466         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2467         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2468         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2469
2470         /*
2471          * An errata states that gprc actually counts good + missed packets:
2472          * Workaround to set gprc to summated queue packet receives
2473          */
2474         hw_stats->gprc = *total_qprc;
2475
2476         if (hw->mac.type != ixgbe_mac_82598EB) {
2477                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2478                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2479                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2480                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2481                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2482                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2483                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2484                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2485         } else {
2486                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2487                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2488                 /* 82598 only has a counter in the high register */
2489                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2490                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2491                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2492         }
2493         uint64_t old_tpr = hw_stats->tpr;
2494
2495         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2496         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2497
2498         if (crc_strip == 0)
2499                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2500
2501         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2502         hw_stats->gptc += delta_gptc;
2503         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2504         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2505
2506         /*
2507          * Workaround: mprc hardware is incorrectly counting
2508          * broadcasts, so for now we subtract those.
2509          */
2510         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2511         hw_stats->bprc += bprc;
2512         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2513         if (hw->mac.type == ixgbe_mac_82598EB)
2514                 hw_stats->mprc -= bprc;
2515
2516         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2517         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2518         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2519         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2520         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2521         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2522
2523         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2524         hw_stats->lxontxc += lxon;
2525         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2526         hw_stats->lxofftxc += lxoff;
2527         total = lxon + lxoff;
2528
2529         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2530         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2531         hw_stats->gptc -= total;
2532         hw_stats->mptc -= total;
2533         hw_stats->ptc64 -= total;
2534         hw_stats->gotc -= total * ETHER_MIN_LEN;
2535
2536         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2537         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2538         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2539         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2540         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2541         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2542         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2543         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2544         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2545         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2546         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2547         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2548         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2549         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2550         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2551         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2552         /* Only read FCOE on 82599 */
2553         if (hw->mac.type != ixgbe_mac_82598EB) {
2554                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2555                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2556                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2557                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2558                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2559         }
2560
2561         /* Flow Director Stats registers */
2562         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2563         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2564 }
2565
2566 /*
2567  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2568  */
2569 static void
2570 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2571 {
2572         struct ixgbe_hw *hw =
2573                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2574         struct ixgbe_hw_stats *hw_stats =
2575                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2576         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2577         unsigned i;
2578
2579         total_missed_rx = 0;
2580         total_qbrc = 0;
2581         total_qprc = 0;
2582         total_qprdc = 0;
2583
2584         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2585                         &total_qprc, &total_qprdc);
2586
2587         if (stats == NULL)
2588                 return;
2589
2590         /* Fill out the rte_eth_stats statistics structure */
2591         stats->ipackets = total_qprc;
2592         stats->ibytes = total_qbrc;
2593         stats->opackets = hw_stats->gptc;
2594         stats->obytes = hw_stats->gotc;
2595
2596         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2597                 stats->q_ipackets[i] = hw_stats->qprc[i];
2598                 stats->q_opackets[i] = hw_stats->qptc[i];
2599                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2600                 stats->q_obytes[i] = hw_stats->qbtc[i];
2601                 stats->q_errors[i] = hw_stats->qprdc[i];
2602         }
2603
2604         /* Rx Errors */
2605         stats->imissed  = total_missed_rx;
2606         stats->ierrors  = hw_stats->crcerrs +
2607                           hw_stats->mspdc +
2608                           hw_stats->rlec +
2609                           hw_stats->ruc +
2610                           hw_stats->roc +
2611                           total_missed_rx +
2612                           hw_stats->illerrc +
2613                           hw_stats->errbc +
2614                           hw_stats->rfc +
2615                           hw_stats->fccrc +
2616                           hw_stats->fclast;
2617
2618         /* Tx Errors */
2619         stats->oerrors  = 0;
2620 }
2621
2622 static void
2623 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2624 {
2625         struct ixgbe_hw_stats *stats =
2626                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2627
2628         /* HW registers are cleared on read */
2629         ixgbe_dev_stats_get(dev, NULL);
2630
2631         /* Reset software totals */
2632         memset(stats, 0, sizeof(*stats));
2633 }
2634
2635 /* This function calculates the number of xstats based on the current config */
2636 static unsigned
2637 ixgbe_xstats_calc_num(void) {
2638         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2639                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2640 }
2641
2642 static int
2643 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2644                                          unsigned n)
2645 {
2646         struct ixgbe_hw *hw =
2647                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2648         struct ixgbe_hw_stats *hw_stats =
2649                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2650         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2651         unsigned i, stat, count = 0;
2652
2653         count = ixgbe_xstats_calc_num();
2654
2655         if (n < count)
2656                 return count;
2657
2658         total_missed_rx = 0;
2659         total_qbrc = 0;
2660         total_qprc = 0;
2661         total_qprdc = 0;
2662
2663         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2664                                    &total_qprc, &total_qprdc);
2665
2666         /* If this is a reset xstats is NULL, and we have cleared the
2667          * registers by reading them.
2668          */
2669         if (!xstats)
2670                 return 0;
2671
2672         /* Extended stats from ixgbe_hw_stats */
2673         count = 0;
2674         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2675                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2676                          rte_ixgbe_stats_strings[i].name);
2677                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2678                                 rte_ixgbe_stats_strings[i].offset);
2679                 count++;
2680         }
2681
2682         /* RX Priority Stats */
2683         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2684                 for (i = 0; i < 8; i++) {
2685                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2686                                  "rx_priority%u_%s", i,
2687                                  rte_ixgbe_rxq_strings[stat].name);
2688                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2689                                         rte_ixgbe_rxq_strings[stat].offset +
2690                                         (sizeof(uint64_t) * i));
2691                         count++;
2692                 }
2693         }
2694
2695         /* TX Priority Stats */
2696         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2697                 for (i = 0; i < 8; i++) {
2698                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2699                                  "tx_priority%u_%s", i,
2700                                  rte_ixgbe_txq_strings[stat].name);
2701                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2702                                         rte_ixgbe_txq_strings[stat].offset +
2703                                         (sizeof(uint64_t) * i));
2704                         count++;
2705                 }
2706         }
2707
2708         return count;
2709 }
2710
2711 static void
2712 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2713 {
2714         struct ixgbe_hw_stats *stats =
2715                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2716
2717         unsigned count = ixgbe_xstats_calc_num();
2718
2719         /* HW registers are cleared on read */
2720         ixgbe_dev_xstats_get(dev, NULL, count);
2721
2722         /* Reset software totals */
2723         memset(stats, 0, sizeof(*stats));
2724 }
2725
2726 static void
2727 ixgbevf_update_stats(struct rte_eth_dev *dev)
2728 {
2729         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2730         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2731                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2732
2733         /* Good Rx packet, include VF loopback */
2734         UPDATE_VF_STAT(IXGBE_VFGPRC,
2735             hw_stats->last_vfgprc, hw_stats->vfgprc);
2736
2737         /* Good Rx octets, include VF loopback */
2738         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2739             hw_stats->last_vfgorc, hw_stats->vfgorc);
2740
2741         /* Good Tx packet, include VF loopback */
2742         UPDATE_VF_STAT(IXGBE_VFGPTC,
2743             hw_stats->last_vfgptc, hw_stats->vfgptc);
2744
2745         /* Good Tx octets, include VF loopback */
2746         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2747             hw_stats->last_vfgotc, hw_stats->vfgotc);
2748
2749         /* Rx Multicst Packet */
2750         UPDATE_VF_STAT(IXGBE_VFMPRC,
2751             hw_stats->last_vfmprc, hw_stats->vfmprc);
2752 }
2753
2754 static int
2755 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2756                        unsigned n)
2757 {
2758         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2759                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2760         unsigned i;
2761
2762         if (n < IXGBEVF_NB_XSTATS)
2763                 return IXGBEVF_NB_XSTATS;
2764
2765         ixgbevf_update_stats(dev);
2766
2767         if (!xstats)
2768                 return 0;
2769
2770         /* Extended stats */
2771         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2772                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2773                          "%s", rte_ixgbevf_stats_strings[i].name);
2774                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2775                         rte_ixgbevf_stats_strings[i].offset);
2776         }
2777
2778         return IXGBEVF_NB_XSTATS;
2779 }
2780
2781 static void
2782 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2783 {
2784         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2785                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2786
2787         ixgbevf_update_stats(dev);
2788
2789         if (stats == NULL)
2790                 return;
2791
2792         stats->ipackets = hw_stats->vfgprc;
2793         stats->ibytes = hw_stats->vfgorc;
2794         stats->opackets = hw_stats->vfgptc;
2795         stats->obytes = hw_stats->vfgotc;
2796         stats->imcasts = hw_stats->vfmprc;
2797         /* stats->imcasts should be removed as imcasts is deprecated */
2798 }
2799
2800 static void
2801 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2802 {
2803         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2804                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2805
2806         /* Sync HW register to the last stats */
2807         ixgbevf_dev_stats_get(dev, NULL);
2808
2809         /* reset HW current stats*/
2810         hw_stats->vfgprc = 0;
2811         hw_stats->vfgorc = 0;
2812         hw_stats->vfgptc = 0;
2813         hw_stats->vfgotc = 0;
2814         hw_stats->vfmprc = 0;
2815
2816 }
2817
2818 static void
2819 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2820 {
2821         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822
2823         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2824         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2825         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2826         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2827         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2828         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2829         dev_info->max_vfs = dev->pci_dev->max_vfs;
2830         if (hw->mac.type == ixgbe_mac_82598EB)
2831                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2832         else
2833                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2834         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2835         dev_info->rx_offload_capa =
2836                 DEV_RX_OFFLOAD_VLAN_STRIP |
2837                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2838                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2839                 DEV_RX_OFFLOAD_TCP_CKSUM;
2840
2841         /*
2842          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2843          * mode.
2844          */
2845         if ((hw->mac.type == ixgbe_mac_82599EB ||
2846              hw->mac.type == ixgbe_mac_X540) &&
2847             !RTE_ETH_DEV_SRIOV(dev).active)
2848                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2849
2850         if (hw->mac.type == ixgbe_mac_X550 ||
2851             hw->mac.type == ixgbe_mac_X550EM_x)
2852                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2853
2854         dev_info->tx_offload_capa =
2855                 DEV_TX_OFFLOAD_VLAN_INSERT |
2856                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2857                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2858                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2859                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2860                 DEV_TX_OFFLOAD_TCP_TSO;
2861
2862         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2863                 .rx_thresh = {
2864                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2865                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2866                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2867                 },
2868                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2869                 .rx_drop_en = 0,
2870         };
2871
2872         dev_info->default_txconf = (struct rte_eth_txconf) {
2873                 .tx_thresh = {
2874                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2875                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2876                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2877                 },
2878                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2879                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2880                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2881                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2882         };
2883
2884         dev_info->rx_desc_lim = rx_desc_lim;
2885         dev_info->tx_desc_lim = tx_desc_lim;
2886
2887         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2888         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2889         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2890 }
2891
2892 static void
2893 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2894                      struct rte_eth_dev_info *dev_info)
2895 {
2896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897
2898         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2899         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2900         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2901         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2902         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2903         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2904         dev_info->max_vfs = dev->pci_dev->max_vfs;
2905         if (hw->mac.type == ixgbe_mac_82598EB)
2906                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2907         else
2908                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2909         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2910                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2911                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2912                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2913         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2914                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2915                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2916                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2917                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2918                                 DEV_TX_OFFLOAD_TCP_TSO;
2919
2920         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2921                 .rx_thresh = {
2922                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2923                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2924                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2925                 },
2926                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2927                 .rx_drop_en = 0,
2928         };
2929
2930         dev_info->default_txconf = (struct rte_eth_txconf) {
2931                 .tx_thresh = {
2932                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2933                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2934                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2935                 },
2936                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2937                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2938                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2939                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2940         };
2941
2942         dev_info->rx_desc_lim = rx_desc_lim;
2943         dev_info->tx_desc_lim = tx_desc_lim;
2944 }
2945
2946 /* return 0 means link status changed, -1 means not changed */
2947 static int
2948 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2949 {
2950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2951         struct rte_eth_link link, old;
2952         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2953         int link_up;
2954         int diag;
2955
2956         link.link_status = 0;
2957         link.link_speed = 0;
2958         link.link_duplex = 0;
2959         memset(&old, 0, sizeof(old));
2960         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2961
2962         hw->mac.get_link_status = true;
2963
2964         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2965         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2966                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2967         else
2968                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2969
2970         if (diag != 0) {
2971                 link.link_speed = ETH_LINK_SPEED_100;
2972                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2973                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2974                 if (link.link_status == old.link_status)
2975                         return -1;
2976                 return 0;
2977         }
2978
2979         if (link_up == 0) {
2980                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2981                 if (link.link_status == old.link_status)
2982                         return -1;
2983                 return 0;
2984         }
2985         link.link_status = 1;
2986         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2987
2988         switch (link_speed) {
2989         default:
2990         case IXGBE_LINK_SPEED_UNKNOWN:
2991                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2992                 link.link_speed = ETH_LINK_SPEED_100;
2993                 break;
2994
2995         case IXGBE_LINK_SPEED_100_FULL:
2996                 link.link_speed = ETH_LINK_SPEED_100;
2997                 break;
2998
2999         case IXGBE_LINK_SPEED_1GB_FULL:
3000                 link.link_speed = ETH_LINK_SPEED_1000;
3001                 break;
3002
3003         case IXGBE_LINK_SPEED_10GB_FULL:
3004                 link.link_speed = ETH_LINK_SPEED_10000;
3005                 break;
3006         }
3007         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3008
3009         if (link.link_status == old.link_status)
3010                 return -1;
3011
3012         return 0;
3013 }
3014
3015 static void
3016 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3017 {
3018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019         uint32_t fctrl;
3020
3021         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3022         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3023         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3024 }
3025
3026 static void
3027 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3028 {
3029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030         uint32_t fctrl;
3031
3032         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3033         fctrl &= (~IXGBE_FCTRL_UPE);
3034         if (dev->data->all_multicast == 1)
3035                 fctrl |= IXGBE_FCTRL_MPE;
3036         else
3037                 fctrl &= (~IXGBE_FCTRL_MPE);
3038         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3039 }
3040
3041 static void
3042 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3043 {
3044         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3045         uint32_t fctrl;
3046
3047         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3048         fctrl |= IXGBE_FCTRL_MPE;
3049         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3050 }
3051
3052 static void
3053 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3054 {
3055         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3056         uint32_t fctrl;
3057
3058         if (dev->data->promiscuous == 1)
3059                 return; /* must remain in all_multicast mode */
3060
3061         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3062         fctrl &= (~IXGBE_FCTRL_MPE);
3063         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3064 }
3065
3066 /**
3067  * It clears the interrupt causes and enables the interrupt.
3068  * It will be called once only during nic initialized.
3069  *
3070  * @param dev
3071  *  Pointer to struct rte_eth_dev.
3072  *
3073  * @return
3074  *  - On success, zero.
3075  *  - On failure, a negative value.
3076  */
3077 static int
3078 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3079 {
3080         struct ixgbe_interrupt *intr =
3081                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3082
3083         ixgbe_dev_link_status_print(dev);
3084         intr->mask |= IXGBE_EICR_LSC;
3085
3086         return 0;
3087 }
3088
3089 /**
3090  * It clears the interrupt causes and enables the interrupt.
3091  * It will be called once only during nic initialized.
3092  *
3093  * @param dev
3094  *  Pointer to struct rte_eth_dev.
3095  *
3096  * @return
3097  *  - On success, zero.
3098  *  - On failure, a negative value.
3099  */
3100 static int
3101 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3102 {
3103         struct ixgbe_interrupt *intr =
3104                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3105
3106         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3107
3108         return 0;
3109 }
3110
3111 /*
3112  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3113  *
3114  * @param dev
3115  *  Pointer to struct rte_eth_dev.
3116  *
3117  * @return
3118  *  - On success, zero.
3119  *  - On failure, a negative value.
3120  */
3121 static int
3122 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3123 {
3124         uint32_t eicr;
3125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3126         struct ixgbe_interrupt *intr =
3127                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3128
3129         /* clear all cause mask */
3130         ixgbe_disable_intr(hw);
3131
3132         /* read-on-clear nic registers here */
3133         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3134         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3135
3136         intr->flags = 0;
3137
3138         /* set flag for async link update */
3139         if (eicr & IXGBE_EICR_LSC)
3140                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3141
3142         if (eicr & IXGBE_EICR_MAILBOX)
3143                 intr->flags |= IXGBE_FLAG_MAILBOX;
3144
3145         return 0;
3146 }
3147
3148 /**
3149  * It gets and then prints the link status.
3150  *
3151  * @param dev
3152  *  Pointer to struct rte_eth_dev.
3153  *
3154  * @return
3155  *  - On success, zero.
3156  *  - On failure, a negative value.
3157  */
3158 static void
3159 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3160 {
3161         struct rte_eth_link link;
3162
3163         memset(&link, 0, sizeof(link));
3164         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3165         if (link.link_status) {
3166                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3167                                         (int)(dev->data->port_id),
3168                                         (unsigned)link.link_speed,
3169                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3170                                         "full-duplex" : "half-duplex");
3171         } else {
3172                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3173                                 (int)(dev->data->port_id));
3174         }
3175         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3176                                 dev->pci_dev->addr.domain,
3177                                 dev->pci_dev->addr.bus,
3178                                 dev->pci_dev->addr.devid,
3179                                 dev->pci_dev->addr.function);
3180 }
3181
3182 /*
3183  * It executes link_update after knowing an interrupt occurred.
3184  *
3185  * @param dev
3186  *  Pointer to struct rte_eth_dev.
3187  *
3188  * @return
3189  *  - On success, zero.
3190  *  - On failure, a negative value.
3191  */
3192 static int
3193 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3194 {
3195         struct ixgbe_interrupt *intr =
3196                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3197         int64_t timeout;
3198         struct rte_eth_link link;
3199         int intr_enable_delay = false;
3200
3201         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3202
3203         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3204                 ixgbe_pf_mbx_process(dev);
3205                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3206         }
3207
3208         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3209                 /* get the link status before link update, for predicting later */
3210                 memset(&link, 0, sizeof(link));
3211                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3212
3213                 ixgbe_dev_link_update(dev, 0);
3214
3215                 /* likely to up */
3216                 if (!link.link_status)
3217                         /* handle it 1 sec later, wait it being stable */
3218                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3219                 /* likely to down */
3220                 else
3221                         /* handle it 4 sec later, wait it being stable */
3222                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3223
3224                 ixgbe_dev_link_status_print(dev);
3225
3226                 intr_enable_delay = true;
3227         }
3228
3229         if (intr_enable_delay) {
3230                 if (rte_eal_alarm_set(timeout * 1000,
3231                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3232                         PMD_DRV_LOG(ERR, "Error setting alarm");
3233         } else {
3234                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3235                 ixgbe_enable_intr(dev);
3236                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3237         }
3238
3239
3240         return 0;
3241 }
3242
3243 /**
3244  * Interrupt handler which shall be registered for alarm callback for delayed
3245  * handling specific interrupt to wait for the stable nic state. As the
3246  * NIC interrupt state is not stable for ixgbe after link is just down,
3247  * it needs to wait 4 seconds to get the stable status.
3248  *
3249  * @param handle
3250  *  Pointer to interrupt handle.
3251  * @param param
3252  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3253  *
3254  * @return
3255  *  void
3256  */
3257 static void
3258 ixgbe_dev_interrupt_delayed_handler(void *param)
3259 {
3260         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3261         struct ixgbe_interrupt *intr =
3262                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3263         struct ixgbe_hw *hw =
3264                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3265         uint32_t eicr;
3266
3267         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3268         if (eicr & IXGBE_EICR_MAILBOX)
3269                 ixgbe_pf_mbx_process(dev);
3270
3271         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3272                 ixgbe_dev_link_update(dev, 0);
3273                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3274                 ixgbe_dev_link_status_print(dev);
3275                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3276         }
3277
3278         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3279         ixgbe_enable_intr(dev);
3280         rte_intr_enable(&(dev->pci_dev->intr_handle));
3281 }
3282
3283 /**
3284  * Interrupt handler triggered by NIC  for handling
3285  * specific interrupt.
3286  *
3287  * @param handle
3288  *  Pointer to interrupt handle.
3289  * @param param
3290  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3291  *
3292  * @return
3293  *  void
3294  */
3295 static void
3296 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3297                             void *param)
3298 {
3299         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3300
3301         ixgbe_dev_interrupt_get_status(dev);
3302         ixgbe_dev_interrupt_action(dev);
3303 }
3304
3305 static int
3306 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3307 {
3308         struct ixgbe_hw *hw;
3309
3310         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3311         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3312 }
3313
3314 static int
3315 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3316 {
3317         struct ixgbe_hw *hw;
3318
3319         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3320         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3321 }
3322
3323 static int
3324 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3325 {
3326         struct ixgbe_hw *hw;
3327         uint32_t mflcn_reg;
3328         uint32_t fccfg_reg;
3329         int rx_pause;
3330         int tx_pause;
3331
3332         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3333
3334         fc_conf->pause_time = hw->fc.pause_time;
3335         fc_conf->high_water = hw->fc.high_water[0];
3336         fc_conf->low_water = hw->fc.low_water[0];
3337         fc_conf->send_xon = hw->fc.send_xon;
3338         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3339
3340         /*
3341          * Return rx_pause status according to actual setting of
3342          * MFLCN register.
3343          */
3344         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3345         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3346                 rx_pause = 1;
3347         else
3348                 rx_pause = 0;
3349
3350         /*
3351          * Return tx_pause status according to actual setting of
3352          * FCCFG register.
3353          */
3354         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3355         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3356                 tx_pause = 1;
3357         else
3358                 tx_pause = 0;
3359
3360         if (rx_pause && tx_pause)
3361                 fc_conf->mode = RTE_FC_FULL;
3362         else if (rx_pause)
3363                 fc_conf->mode = RTE_FC_RX_PAUSE;
3364         else if (tx_pause)
3365                 fc_conf->mode = RTE_FC_TX_PAUSE;
3366         else
3367                 fc_conf->mode = RTE_FC_NONE;
3368
3369         return 0;
3370 }
3371
3372 static int
3373 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3374 {
3375         struct ixgbe_hw *hw;
3376         int err;
3377         uint32_t rx_buf_size;
3378         uint32_t max_high_water;
3379         uint32_t mflcn;
3380         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3381                 ixgbe_fc_none,
3382                 ixgbe_fc_rx_pause,
3383                 ixgbe_fc_tx_pause,
3384                 ixgbe_fc_full
3385         };
3386
3387         PMD_INIT_FUNC_TRACE();
3388
3389         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3390         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3391         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3392
3393         /*
3394          * At least reserve one Ethernet frame for watermark
3395          * high_water/low_water in kilo bytes for ixgbe
3396          */
3397         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3398         if ((fc_conf->high_water > max_high_water) ||
3399                 (fc_conf->high_water < fc_conf->low_water)) {
3400                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3401                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3402                 return -EINVAL;
3403         }
3404
3405         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3406         hw->fc.pause_time     = fc_conf->pause_time;
3407         hw->fc.high_water[0]  = fc_conf->high_water;
3408         hw->fc.low_water[0]   = fc_conf->low_water;
3409         hw->fc.send_xon       = fc_conf->send_xon;
3410         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3411
3412         err = ixgbe_fc_enable(hw);
3413
3414         /* Not negotiated is not an error case */
3415         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3416
3417                 /* check if we want to forward MAC frames - driver doesn't have native
3418                  * capability to do that, so we'll write the registers ourselves */
3419
3420                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3421
3422                 /* set or clear MFLCN.PMCF bit depending on configuration */
3423                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3424                         mflcn |= IXGBE_MFLCN_PMCF;
3425                 else
3426                         mflcn &= ~IXGBE_MFLCN_PMCF;
3427
3428                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3429                 IXGBE_WRITE_FLUSH(hw);
3430
3431                 return 0;
3432         }
3433
3434         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3435         return -EIO;
3436 }
3437
3438 /**
3439  *  ixgbe_pfc_enable_generic - Enable flow control
3440  *  @hw: pointer to hardware structure
3441  *  @tc_num: traffic class number
3442  *  Enable flow control according to the current settings.
3443  */
3444 static int
3445 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3446 {
3447         int ret_val = 0;
3448         uint32_t mflcn_reg, fccfg_reg;
3449         uint32_t reg;
3450         uint32_t fcrtl, fcrth;
3451         uint8_t i;
3452         uint8_t nb_rx_en;
3453
3454         /* Validate the water mark configuration */
3455         if (!hw->fc.pause_time) {
3456                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3457                 goto out;
3458         }
3459
3460         /* Low water mark of zero causes XOFF floods */
3461         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3462                  /* High/Low water can not be 0 */
3463                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3464                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3465                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3466                         goto out;
3467                 }
3468
3469                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3470                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3471                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3472                         goto out;
3473                 }
3474         }
3475         /* Negotiate the fc mode to use */
3476         ixgbe_fc_autoneg(hw);
3477
3478         /* Disable any previous flow control settings */
3479         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3480         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3481
3482         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3483         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3484
3485         switch (hw->fc.current_mode) {
3486         case ixgbe_fc_none:
3487                 /*
3488                  * If the count of enabled RX Priority Flow control >1,
3489                  * and the TX pause can not be disabled
3490                  */
3491                 nb_rx_en = 0;
3492                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3493                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3494                         if (reg & IXGBE_FCRTH_FCEN)
3495                                 nb_rx_en++;
3496                 }
3497                 if (nb_rx_en > 1)
3498                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3499                 break;
3500         case ixgbe_fc_rx_pause:
3501                 /*
3502                  * Rx Flow control is enabled and Tx Flow control is
3503                  * disabled by software override. Since there really
3504                  * isn't a way to advertise that we are capable of RX
3505                  * Pause ONLY, we will advertise that we support both
3506                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3507                  * disable the adapter's ability to send PAUSE frames.
3508                  */
3509                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3510                 /*
3511                  * If the count of enabled RX Priority Flow control >1,
3512                  * and the TX pause can not be disabled
3513                  */
3514                 nb_rx_en = 0;
3515                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3516                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3517                         if (reg & IXGBE_FCRTH_FCEN)
3518                                 nb_rx_en++;
3519                 }
3520                 if (nb_rx_en > 1)
3521                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3522                 break;
3523         case ixgbe_fc_tx_pause:
3524                 /*
3525                  * Tx Flow control is enabled, and Rx Flow control is
3526                  * disabled by software override.
3527                  */
3528                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3529                 break;
3530         case ixgbe_fc_full:
3531                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3532                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3533                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3534                 break;
3535         default:
3536                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3537                 ret_val = IXGBE_ERR_CONFIG;
3538                 goto out;
3539                 break;
3540         }
3541
3542         /* Set 802.3x based flow control settings. */
3543         mflcn_reg |= IXGBE_MFLCN_DPF;
3544         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3545         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3546
3547         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3548         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3549                 hw->fc.high_water[tc_num]) {
3550                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3551                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3552                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3553         } else {
3554                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3555                 /*
3556                  * In order to prevent Tx hangs when the internal Tx
3557                  * switch is enabled we must set the high water mark
3558                  * to the maximum FCRTH value.  This allows the Tx
3559                  * switch to function even under heavy Rx workloads.
3560                  */
3561                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3562         }
3563         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3564
3565         /* Configure pause time (2 TCs per register) */
3566         reg = hw->fc.pause_time * 0x00010001;
3567         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3568                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3569
3570         /* Configure flow control refresh threshold value */
3571         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3572
3573 out:
3574         return ret_val;
3575 }
3576
3577 static int
3578 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3579 {
3580         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3581         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3582
3583         if(hw->mac.type != ixgbe_mac_82598EB) {
3584                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3585         }
3586         return ret_val;
3587 }
3588
3589 static int
3590 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3591 {
3592         int err;
3593         uint32_t rx_buf_size;
3594         uint32_t max_high_water;
3595         uint8_t tc_num;
3596         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3597         struct ixgbe_hw *hw =
3598                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3599         struct ixgbe_dcb_config *dcb_config =
3600                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3601
3602         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3603                 ixgbe_fc_none,
3604                 ixgbe_fc_rx_pause,
3605                 ixgbe_fc_tx_pause,
3606                 ixgbe_fc_full
3607         };
3608
3609         PMD_INIT_FUNC_TRACE();
3610
3611         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3612         tc_num = map[pfc_conf->priority];
3613         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3614         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3615         /*
3616          * At least reserve one Ethernet frame for watermark
3617          * high_water/low_water in kilo bytes for ixgbe
3618          */
3619         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3620         if ((pfc_conf->fc.high_water > max_high_water) ||
3621             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3622                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3623                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3624                 return -EINVAL;
3625         }
3626
3627         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3628         hw->fc.pause_time = pfc_conf->fc.pause_time;
3629         hw->fc.send_xon = pfc_conf->fc.send_xon;
3630         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3631         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3632
3633         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3634
3635         /* Not negotiated is not an error case */
3636         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3637                 return 0;
3638
3639         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3640         return -EIO;
3641 }
3642
3643 static int
3644 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3645                           struct rte_eth_rss_reta_entry64 *reta_conf,
3646                           uint16_t reta_size)
3647 {
3648         uint8_t i, j, mask;
3649         uint32_t reta, r;
3650         uint16_t idx, shift;
3651         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3652         uint16_t sp_reta_size;
3653         uint32_t reta_reg;
3654
3655         PMD_INIT_FUNC_TRACE();
3656
3657         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3658                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3659                         "NIC.");
3660                 return -ENOTSUP;
3661         }
3662
3663         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3664         if (reta_size != sp_reta_size) {
3665                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3666                         "(%d) doesn't match the number hardware can supported "
3667                         "(%d)\n", reta_size, sp_reta_size);
3668                 return -EINVAL;
3669         }
3670
3671         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3672                 idx = i / RTE_RETA_GROUP_SIZE;
3673                 shift = i % RTE_RETA_GROUP_SIZE;
3674                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3675                                                 IXGBE_4_BIT_MASK);
3676                 if (!mask)
3677                         continue;
3678                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3679                 if (mask == IXGBE_4_BIT_MASK)
3680                         r = 0;
3681                 else
3682                         r = IXGBE_READ_REG(hw, reta_reg);
3683                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3684                         if (mask & (0x1 << j))
3685                                 reta |= reta_conf[idx].reta[shift + j] <<
3686                                                         (CHAR_BIT * j);
3687                         else
3688                                 reta |= r & (IXGBE_8_BIT_MASK <<
3689                                                 (CHAR_BIT * j));
3690                 }
3691                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3692         }
3693
3694         return 0;
3695 }
3696
3697 static int
3698 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3699                          struct rte_eth_rss_reta_entry64 *reta_conf,
3700                          uint16_t reta_size)
3701 {
3702         uint8_t i, j, mask;
3703         uint32_t reta;
3704         uint16_t idx, shift;
3705         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3706         uint16_t sp_reta_size;
3707         uint32_t reta_reg;
3708
3709         PMD_INIT_FUNC_TRACE();
3710         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3711         if (reta_size != sp_reta_size) {
3712                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3713                         "(%d) doesn't match the number hardware can supported "
3714                         "(%d)\n", reta_size, sp_reta_size);
3715                 return -EINVAL;
3716         }
3717
3718         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3719                 idx = i / RTE_RETA_GROUP_SIZE;
3720                 shift = i % RTE_RETA_GROUP_SIZE;
3721                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3722                                                 IXGBE_4_BIT_MASK);
3723                 if (!mask)
3724                         continue;
3725
3726                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3727                 reta = IXGBE_READ_REG(hw, reta_reg);
3728                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3729                         if (mask & (0x1 << j))
3730                                 reta_conf[idx].reta[shift + j] =
3731                                         ((reta >> (CHAR_BIT * j)) &
3732                                                 IXGBE_8_BIT_MASK);
3733                 }
3734         }
3735
3736         return 0;
3737 }
3738
3739 static void
3740 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3741                                 uint32_t index, uint32_t pool)
3742 {
3743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3744         uint32_t enable_addr = 1;
3745
3746         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3747 }
3748
3749 static void
3750 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3751 {
3752         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3753
3754         ixgbe_clear_rar(hw, index);
3755 }
3756
3757 static void
3758 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3759 {
3760         ixgbe_remove_rar(dev, 0);
3761
3762         ixgbe_add_rar(dev, addr, 0, 0);
3763 }
3764
3765 static int
3766 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3767 {
3768         uint32_t hlreg0;
3769         uint32_t maxfrs;
3770         struct ixgbe_hw *hw;
3771         struct rte_eth_dev_info dev_info;
3772         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3773
3774         ixgbe_dev_info_get(dev, &dev_info);
3775
3776         /* check that mtu is within the allowed range */
3777         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3778                 return -EINVAL;
3779
3780         /* refuse mtu that requires the support of scattered packets when this
3781          * feature has not been enabled before. */
3782         if (!dev->data->scattered_rx &&
3783             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3784              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3785                 return -EINVAL;
3786
3787         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3788         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3789
3790         /* switch to jumbo mode if needed */
3791         if (frame_size > ETHER_MAX_LEN) {
3792                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3793                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3794         } else {
3795                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3796                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3797         }
3798         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3799
3800         /* update max frame size */
3801         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3802
3803         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3804         maxfrs &= 0x0000FFFF;
3805         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3806         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3807
3808         return 0;
3809 }
3810
3811 /*
3812  * Virtual Function operations
3813  */
3814 static void
3815 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3816 {
3817         PMD_INIT_FUNC_TRACE();
3818
3819         /* Clear interrupt mask to stop from interrupts being generated */
3820         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3821
3822         IXGBE_WRITE_FLUSH(hw);
3823 }
3824
3825 static void
3826 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3827 {
3828         PMD_INIT_FUNC_TRACE();
3829
3830         /* VF enable interrupt autoclean */
3831         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3832         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3833         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3834
3835         IXGBE_WRITE_FLUSH(hw);
3836 }
3837
3838 static int
3839 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3840 {
3841         struct rte_eth_conf* conf = &dev->data->dev_conf;
3842         struct ixgbe_adapter *adapter =
3843                         (struct ixgbe_adapter *)dev->data->dev_private;
3844
3845         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3846                      dev->data->port_id);
3847
3848         /*
3849          * VF has no ability to enable/disable HW CRC
3850          * Keep the persistent behavior the same as Host PF
3851          */
3852 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3853         if (!conf->rxmode.hw_strip_crc) {
3854                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3855                 conf->rxmode.hw_strip_crc = 1;
3856         }
3857 #else
3858         if (conf->rxmode.hw_strip_crc) {
3859                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3860                 conf->rxmode.hw_strip_crc = 0;
3861         }
3862 #endif
3863
3864         /*
3865          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3866          * allocation or vector Rx preconditions we will reset it.
3867          */
3868         adapter->rx_bulk_alloc_allowed = true;
3869         adapter->rx_vec_allowed = true;
3870
3871         return 0;
3872 }
3873
3874 static int
3875 ixgbevf_dev_start(struct rte_eth_dev *dev)
3876 {
3877         struct ixgbe_hw *hw =
3878                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3879         uint32_t intr_vector = 0;
3880         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3881
3882         int err, mask = 0;
3883
3884         PMD_INIT_FUNC_TRACE();
3885
3886         hw->mac.ops.reset_hw(hw);
3887         hw->mac.get_link_status = true;
3888
3889         /* negotiate mailbox API version to use with the PF. */
3890         ixgbevf_negotiate_api(hw);
3891
3892         ixgbevf_dev_tx_init(dev);
3893
3894         /* This can fail when allocating mbufs for descriptor rings */
3895         err = ixgbevf_dev_rx_init(dev);
3896         if (err) {
3897                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3898                 ixgbe_dev_clear_queues(dev);
3899                 return err;
3900         }
3901
3902         /* Set vfta */
3903         ixgbevf_set_vfta_all(dev,1);
3904
3905         /* Set HW strip */
3906         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3907                 ETH_VLAN_EXTEND_MASK;
3908         ixgbevf_vlan_offload_set(dev, mask);
3909
3910         ixgbevf_dev_rxtx_start(dev);
3911
3912         /* check and configure queue intr-vector mapping */
3913         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3914                 intr_vector = dev->data->nb_rx_queues;
3915                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3916                         return -1;
3917         }
3918
3919         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3920                 intr_handle->intr_vec =
3921                         rte_zmalloc("intr_vec",
3922                                     dev->data->nb_rx_queues * sizeof(int), 0);
3923                 if (intr_handle->intr_vec == NULL) {
3924                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3925                                      " intr_vec\n", dev->data->nb_rx_queues);
3926                         return -ENOMEM;
3927                 }
3928         }
3929         ixgbevf_configure_msix(dev);
3930
3931         rte_intr_enable(intr_handle);
3932
3933         /* Re-enable interrupt for VF */
3934         ixgbevf_intr_enable(hw);
3935
3936         return 0;
3937 }
3938
3939 static void
3940 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3941 {
3942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3943         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3944
3945         PMD_INIT_FUNC_TRACE();
3946
3947         hw->adapter_stopped = 1;
3948         ixgbe_stop_adapter(hw);
3949
3950         /*
3951           * Clear what we set, but we still keep shadow_vfta to
3952           * restore after device starts
3953           */
3954         ixgbevf_set_vfta_all(dev,0);
3955
3956         /* Clear stored conf */
3957         dev->data->scattered_rx = 0;
3958
3959         ixgbe_dev_clear_queues(dev);
3960
3961         /* disable intr eventfd mapping */
3962         rte_intr_disable(intr_handle);
3963
3964         /* Clean datapath event and queue/vec mapping */
3965         rte_intr_efd_disable(intr_handle);
3966         if (intr_handle->intr_vec != NULL) {
3967                 rte_free(intr_handle->intr_vec);
3968                 intr_handle->intr_vec = NULL;
3969         }
3970 }
3971
3972 static void
3973 ixgbevf_dev_close(struct rte_eth_dev *dev)
3974 {
3975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3976
3977         PMD_INIT_FUNC_TRACE();
3978
3979         ixgbe_reset_hw(hw);
3980
3981         ixgbevf_dev_stop(dev);
3982
3983         ixgbe_dev_free_queues(dev);
3984
3985         /* reprogram the RAR[0] in case user changed it. */
3986         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3987 }
3988
3989 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3990 {
3991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3992         struct ixgbe_vfta * shadow_vfta =
3993                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3994         int i = 0, j = 0, vfta = 0, mask = 1;
3995
3996         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3997                 vfta = shadow_vfta->vfta[i];
3998                 if(vfta){
3999                         mask = 1;
4000                         for (j = 0; j < 32; j++){
4001                                 if(vfta & mask)
4002                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4003                                 mask<<=1;
4004                         }
4005                 }
4006         }
4007
4008 }
4009
4010 static int
4011 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4012 {
4013         struct ixgbe_hw *hw =
4014                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4015         struct ixgbe_vfta * shadow_vfta =
4016                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4017         uint32_t vid_idx = 0;
4018         uint32_t vid_bit = 0;
4019         int ret = 0;
4020
4021         PMD_INIT_FUNC_TRACE();
4022
4023         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4024         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4025         if(ret){
4026                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4027                 return ret;
4028         }
4029         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4030         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4031
4032         /* Save what we set and retore it after device reset */
4033         if (on)
4034                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4035         else
4036                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4037
4038         return 0;
4039 }
4040
4041 static void
4042 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4043 {
4044         struct ixgbe_hw *hw =
4045                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4046         uint32_t ctrl;
4047
4048         PMD_INIT_FUNC_TRACE();
4049
4050         if(queue >= hw->mac.max_rx_queues)
4051                 return;
4052
4053         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4054         if(on)
4055                 ctrl |= IXGBE_RXDCTL_VME;
4056         else
4057                 ctrl &= ~IXGBE_RXDCTL_VME;
4058         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4059
4060         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4061 }
4062
4063 static void
4064 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4065 {
4066         struct ixgbe_hw *hw =
4067                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4068         uint16_t i;
4069         int on = 0;
4070
4071         /* VF function only support hw strip feature, others are not support */
4072         if(mask & ETH_VLAN_STRIP_MASK){
4073                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4074
4075                 for(i=0; i < hw->mac.max_rx_queues; i++)
4076                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4077         }
4078 }
4079
4080 static int
4081 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4082 {
4083         uint32_t reg_val;
4084
4085         /* we only need to do this if VMDq is enabled */
4086         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4087         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4088                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4089                 return -1;
4090         }
4091
4092         return 0;
4093 }
4094
4095 static uint32_t
4096 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4097 {
4098         uint32_t vector = 0;
4099         switch (hw->mac.mc_filter_type) {
4100         case 0:   /* use bits [47:36] of the address */
4101                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4102                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4103                 break;
4104         case 1:   /* use bits [46:35] of the address */
4105                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4106                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4107                 break;
4108         case 2:   /* use bits [45:34] of the address */
4109                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4110                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4111                 break;
4112         case 3:   /* use bits [43:32] of the address */
4113                 vector = ((uc_addr->addr_bytes[4]) |
4114                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4115                 break;
4116         default:  /* Invalid mc_filter_type */
4117                 break;
4118         }
4119
4120         /* vector can only be 12-bits or boundary will be exceeded */
4121         vector &= 0xFFF;
4122         return vector;
4123 }
4124
4125 static int
4126 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4127                                uint8_t on)
4128 {
4129         uint32_t vector;
4130         uint32_t uta_idx;
4131         uint32_t reg_val;
4132         uint32_t uta_shift;
4133         uint32_t rc;
4134         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4135         const uint32_t ixgbe_uta_bit_shift = 5;
4136         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4137         const uint32_t bit1 = 0x1;
4138
4139         struct ixgbe_hw *hw =
4140                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4141         struct ixgbe_uta_info *uta_info =
4142                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4143
4144         /* The UTA table only exists on 82599 hardware and newer */
4145         if (hw->mac.type < ixgbe_mac_82599EB)
4146                 return -ENOTSUP;
4147
4148         vector = ixgbe_uta_vector(hw,mac_addr);
4149         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4150         uta_shift = vector & ixgbe_uta_bit_mask;
4151
4152         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4153         if(rc == on)
4154                 return 0;
4155
4156         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4157         if (on) {
4158                 uta_info->uta_in_use++;
4159                 reg_val |= (bit1 << uta_shift);
4160                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4161         } else {
4162                 uta_info->uta_in_use--;
4163                 reg_val &= ~(bit1 << uta_shift);
4164                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4165         }
4166
4167         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4168
4169         if (uta_info->uta_in_use > 0)
4170                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4171                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4172         else
4173                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4174
4175         return 0;
4176 }
4177
4178 static int
4179 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4180 {
4181         int i;
4182         struct ixgbe_hw *hw =
4183                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4184         struct ixgbe_uta_info *uta_info =
4185                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4186
4187         /* The UTA table only exists on 82599 hardware and newer */
4188         if (hw->mac.type < ixgbe_mac_82599EB)
4189                 return -ENOTSUP;
4190
4191         if(on) {
4192                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4193                         uta_info->uta_shadow[i] = ~0;
4194                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4195                 }
4196         } else {
4197                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4198                         uta_info->uta_shadow[i] = 0;
4199                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4200                 }
4201         }
4202         return 0;
4203
4204 }
4205
4206 uint32_t
4207 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4208 {
4209         uint32_t new_val = orig_val;
4210
4211         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4212                 new_val |= IXGBE_VMOLR_AUPE;
4213         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4214                 new_val |= IXGBE_VMOLR_ROMPE;
4215         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4216                 new_val |= IXGBE_VMOLR_ROPE;
4217         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4218                 new_val |= IXGBE_VMOLR_BAM;
4219         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4220                 new_val |= IXGBE_VMOLR_MPE;
4221
4222         return new_val;
4223 }
4224
4225 static int
4226 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4227                                uint16_t rx_mask, uint8_t on)
4228 {
4229         int val = 0;
4230
4231         struct ixgbe_hw *hw =
4232                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4233         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4234
4235         if (hw->mac.type == ixgbe_mac_82598EB) {
4236                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4237                              " on 82599 hardware and newer");
4238                 return -ENOTSUP;
4239         }
4240         if (ixgbe_vmdq_mode_check(hw) < 0)
4241                 return -ENOTSUP;
4242
4243         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4244
4245         if (on)
4246                 vmolr |= val;
4247         else
4248                 vmolr &= ~val;
4249
4250         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4251
4252         return 0;
4253 }
4254
4255 static int
4256 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4257 {
4258         uint32_t reg,addr;
4259         uint32_t val;
4260         const uint8_t bit1 = 0x1;
4261
4262         struct ixgbe_hw *hw =
4263                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4264
4265         if (ixgbe_vmdq_mode_check(hw) < 0)
4266                 return -ENOTSUP;
4267
4268         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4269         reg = IXGBE_READ_REG(hw, addr);
4270         val = bit1 << pool;
4271
4272         if (on)
4273                 reg |= val;
4274         else
4275                 reg &= ~val;
4276
4277         IXGBE_WRITE_REG(hw, addr,reg);
4278
4279         return 0;
4280 }
4281
4282 static int
4283 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4284 {
4285         uint32_t reg,addr;
4286         uint32_t val;
4287         const uint8_t bit1 = 0x1;
4288
4289         struct ixgbe_hw *hw =
4290                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4291
4292         if (ixgbe_vmdq_mode_check(hw) < 0)
4293                 return -ENOTSUP;
4294
4295         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4296         reg = IXGBE_READ_REG(hw, addr);
4297         val = bit1 << pool;
4298
4299         if (on)
4300                 reg |= val;
4301         else
4302                 reg &= ~val;
4303
4304         IXGBE_WRITE_REG(hw, addr,reg);
4305
4306         return 0;
4307 }
4308
4309 static int
4310 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4311                         uint64_t pool_mask, uint8_t vlan_on)
4312 {
4313         int ret = 0;
4314         uint16_t pool_idx;
4315         struct ixgbe_hw *hw =
4316                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4317
4318         if (ixgbe_vmdq_mode_check(hw) < 0)
4319                 return -ENOTSUP;
4320         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4321                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4322                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4323                         if (ret < 0)
4324                                 return ret;
4325         }
4326
4327         return ret;
4328 }
4329
4330 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4331 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4332 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4333 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4334 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4335         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4336         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4337
4338 static int
4339 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4340                         struct rte_eth_mirror_conf *mirror_conf,
4341                         uint8_t rule_id, uint8_t on)
4342 {
4343         uint32_t mr_ctl,vlvf;
4344         uint32_t mp_lsb = 0;
4345         uint32_t mv_msb = 0;
4346         uint32_t mv_lsb = 0;
4347         uint32_t mp_msb = 0;
4348         uint8_t i = 0;
4349         int reg_index = 0;
4350         uint64_t vlan_mask = 0;
4351
4352         const uint8_t pool_mask_offset = 32;
4353         const uint8_t vlan_mask_offset = 32;
4354         const uint8_t dst_pool_offset = 8;
4355         const uint8_t rule_mr_offset  = 4;
4356         const uint8_t mirror_rule_mask= 0x0F;
4357
4358         struct ixgbe_mirror_info *mr_info =
4359                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4360         struct ixgbe_hw *hw =
4361                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362         uint8_t mirror_type = 0;
4363
4364         if (ixgbe_vmdq_mode_check(hw) < 0)
4365                 return -ENOTSUP;
4366
4367         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4368                 return -EINVAL;
4369
4370         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4371                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4372                         mirror_conf->rule_type);
4373                 return -EINVAL;
4374         }
4375
4376         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4377                 mirror_type |= IXGBE_MRCTL_VLME;
4378                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4379                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4380                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4381                                 /* search vlan id related pool vlan filter index */
4382                                 reg_index = ixgbe_find_vlvf_slot(hw,
4383                                                 mirror_conf->vlan.vlan_id[i]);
4384                                 if(reg_index < 0)
4385                                         return -EINVAL;
4386                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4387                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4388                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4389                                       mirror_conf->vlan.vlan_id[i]))
4390                                         vlan_mask |= (1ULL << reg_index);
4391                                 else
4392                                         return -EINVAL;
4393                         }
4394                 }
4395
4396                 if (on) {
4397                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4398                         mv_msb = vlan_mask >> vlan_mask_offset;
4399
4400                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4401                                                 mirror_conf->vlan.vlan_mask;
4402                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4403                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4404                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4405                                                 mirror_conf->vlan.vlan_id[i];
4406                         }
4407                 } else {
4408                         mv_lsb = 0;
4409                         mv_msb = 0;
4410                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4411                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4412                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4413                 }
4414         }
4415
4416         /*
4417          * if enable pool mirror, write related pool mask register,if disable
4418          * pool mirror, clear PFMRVM register
4419          */
4420         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4421                 mirror_type |= IXGBE_MRCTL_VPME;
4422                 if (on) {
4423                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4424                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4425                         mr_info->mr_conf[rule_id].pool_mask =
4426                                         mirror_conf->pool_mask;
4427
4428                 } else {
4429                         mp_lsb = 0;
4430                         mp_msb = 0;
4431                         mr_info->mr_conf[rule_id].pool_mask = 0;
4432                 }
4433         }
4434         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4435                 mirror_type |= IXGBE_MRCTL_UPME;
4436         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4437                 mirror_type |= IXGBE_MRCTL_DPME;
4438
4439         /* read  mirror control register and recalculate it */
4440         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4441
4442         if (on) {
4443                 mr_ctl |= mirror_type;
4444                 mr_ctl &= mirror_rule_mask;
4445                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4446         } else
4447                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4448
4449         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4450         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4451
4452         /* write mirrror control  register */
4453         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4454
4455         /* write pool mirrror control  register */
4456         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4457                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4458                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4459                                 mp_msb);
4460         }
4461         /* write VLAN mirrror control  register */
4462         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4463                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4464                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4465                                 mv_msb);
4466         }
4467
4468         return 0;
4469 }
4470
4471 static int
4472 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4473 {
4474         int mr_ctl = 0;
4475         uint32_t lsb_val = 0;
4476         uint32_t msb_val = 0;
4477         const uint8_t rule_mr_offset = 4;
4478
4479         struct ixgbe_hw *hw =
4480                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481         struct ixgbe_mirror_info *mr_info =
4482                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4483
4484         if (ixgbe_vmdq_mode_check(hw) < 0)
4485                 return -ENOTSUP;
4486
4487         memset(&mr_info->mr_conf[rule_id], 0,
4488                 sizeof(struct rte_eth_mirror_conf));
4489
4490         /* clear PFVMCTL register */
4491         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4492
4493         /* clear pool mask register */
4494         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4495         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4496
4497         /* clear vlan mask register */
4498         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4499         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4500
4501         return 0;
4502 }
4503
4504 static int
4505 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4506 {
4507         uint32_t mask;
4508         struct ixgbe_hw *hw =
4509                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4510
4511         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4512         mask |= (1 << IXGBE_MISC_VEC_ID);
4513         RTE_SET_USED(queue_id);
4514         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4515
4516         rte_intr_enable(&dev->pci_dev->intr_handle);
4517
4518         return 0;
4519 }
4520
4521 static int
4522 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4523 {
4524         uint32_t mask;
4525         struct ixgbe_hw *hw =
4526                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527
4528         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4529         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4530         RTE_SET_USED(queue_id);
4531         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4532
4533         return 0;
4534 }
4535
4536 static int
4537 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4538 {
4539         uint32_t mask;
4540         struct ixgbe_hw *hw =
4541                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4542         struct ixgbe_interrupt *intr =
4543                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4544
4545         if (queue_id < 16) {
4546                 ixgbe_disable_intr(hw);
4547                 intr->mask |= (1 << queue_id);
4548                 ixgbe_enable_intr(dev);
4549         } else if (queue_id < 32) {
4550                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4551                 mask &= (1 << queue_id);
4552                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4553         } else if (queue_id < 64) {
4554                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4555                 mask &= (1 << (queue_id - 32));
4556                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4557         }
4558         rte_intr_enable(&dev->pci_dev->intr_handle);
4559
4560         return 0;
4561 }
4562
4563 static int
4564 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4565 {
4566         uint32_t mask;
4567         struct ixgbe_hw *hw =
4568                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4569         struct ixgbe_interrupt *intr =
4570                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4571
4572         if (queue_id < 16) {
4573                 ixgbe_disable_intr(hw);
4574                 intr->mask &= ~(1 << queue_id);
4575                 ixgbe_enable_intr(dev);
4576         } else if (queue_id < 32) {
4577                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4578                 mask &= ~(1 << queue_id);
4579                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4580         } else if (queue_id < 64) {
4581                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4582                 mask &= ~(1 << (queue_id - 32));
4583                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4584         }
4585
4586         return 0;
4587 }
4588
4589 static void
4590 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4591                      uint8_t queue, uint8_t msix_vector)
4592 {
4593         uint32_t tmp, idx;
4594
4595         if (direction == -1) {
4596                 /* other causes */
4597                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4598                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4599                 tmp &= ~0xFF;
4600                 tmp |= msix_vector;
4601                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4602         } else {
4603                 /* rx or tx cause */
4604                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4605                 idx = ((16 * (queue & 1)) + (8 * direction));
4606                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4607                 tmp &= ~(0xFF << idx);
4608                 tmp |= (msix_vector << idx);
4609                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4610         }
4611 }
4612
4613 /**
4614  * set the IVAR registers, mapping interrupt causes to vectors
4615  * @param hw
4616  *  pointer to ixgbe_hw struct
4617  * @direction
4618  *  0 for Rx, 1 for Tx, -1 for other causes
4619  * @queue
4620  *  queue to map the corresponding interrupt to
4621  * @msix_vector
4622  *  the vector to map to the corresponding queue
4623  */
4624 static void
4625 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4626                    uint8_t queue, uint8_t msix_vector)
4627 {
4628         uint32_t tmp, idx;
4629
4630         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4631         if (hw->mac.type == ixgbe_mac_82598EB) {
4632                 if (direction == -1)
4633                         direction = 0;
4634                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4635                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4636                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4637                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4638                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4639         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4640                         (hw->mac.type == ixgbe_mac_X540)) {
4641                 if (direction == -1) {
4642                         /* other causes */
4643                         idx = ((queue & 1) * 8);
4644                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4645                         tmp &= ~(0xFF << idx);
4646                         tmp |= (msix_vector << idx);
4647                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4648                 } else {
4649                         /* rx or tx causes */
4650                         idx = ((16 * (queue & 1)) + (8 * direction));
4651                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4652                         tmp &= ~(0xFF << idx);
4653                         tmp |= (msix_vector << idx);
4654                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4655                 }
4656         }
4657 }
4658
4659 static void
4660 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4661 {
4662         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4663         struct ixgbe_hw *hw =
4664                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4665         uint32_t q_idx;
4666         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4667
4668         /* won't configure msix register if no mapping is done
4669          * between intr vector and event fd.
4670          */
4671         if (!rte_intr_dp_is_en(intr_handle))
4672                 return;
4673
4674         /* Configure all RX queues of VF */
4675         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4676                 /* Force all queue use vector 0,
4677                  * as IXGBE_VF_MAXMSIVECOTR = 1
4678                  */
4679                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4680                 intr_handle->intr_vec[q_idx] = vector_idx;
4681         }
4682
4683         /* Configure VF other cause ivar */
4684         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4685 }
4686
4687 /**
4688  * Sets up the hardware to properly generate MSI-X interrupts
4689  * @hw
4690  *  board private structure
4691  */
4692 static void
4693 ixgbe_configure_msix(struct rte_eth_dev *dev)
4694 {
4695         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4696         struct ixgbe_hw *hw =
4697                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4698         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4699         uint32_t vec = IXGBE_MISC_VEC_ID;
4700         uint32_t mask;
4701         uint32_t gpie;
4702
4703         /* won't configure msix register if no mapping is done
4704          * between intr vector and event fd
4705          */
4706         if (!rte_intr_dp_is_en(intr_handle))
4707                 return;
4708
4709         if (rte_intr_allow_others(intr_handle))
4710                 vec = base = IXGBE_RX_VEC_START;
4711
4712         /* setup GPIE for MSI-x mode */
4713         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4714         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4715                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4716         /* auto clearing and auto setting corresponding bits in EIMS
4717          * when MSI-X interrupt is triggered
4718          */
4719         if (hw->mac.type == ixgbe_mac_82598EB) {
4720                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4721         } else {
4722                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4723                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4724         }
4725         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4726
4727         /* Populate the IVAR table and set the ITR values to the
4728          * corresponding register.
4729          */
4730         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4731              queue_id++) {
4732                 /* by default, 1:1 mapping */
4733                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4734                 intr_handle->intr_vec[queue_id] = vec;
4735                 if (vec < base + intr_handle->nb_efd - 1)
4736                         vec++;
4737         }
4738
4739         switch (hw->mac.type) {
4740         case ixgbe_mac_82598EB:
4741                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4742                                    IXGBE_MISC_VEC_ID);
4743                 break;
4744         case ixgbe_mac_82599EB:
4745         case ixgbe_mac_X540:
4746                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4747                 break;
4748         default:
4749                 break;
4750         }
4751         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4752                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4753
4754         /* set up to autoclear timer, and the vectors */
4755         mask = IXGBE_EIMS_ENABLE_MASK;
4756         mask &= ~(IXGBE_EIMS_OTHER |
4757                   IXGBE_EIMS_MAILBOX |
4758                   IXGBE_EIMS_LSC);
4759
4760         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4761 }
4762
4763 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4764         uint16_t queue_idx, uint16_t tx_rate)
4765 {
4766         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4767         uint32_t rf_dec, rf_int;
4768         uint32_t bcnrc_val;
4769         uint16_t link_speed = dev->data->dev_link.link_speed;
4770
4771         if (queue_idx >= hw->mac.max_tx_queues)
4772                 return -EINVAL;
4773
4774         if (tx_rate != 0) {
4775                 /* Calculate the rate factor values to set */
4776                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4777                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4778                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4779
4780                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4781                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4782                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4783                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4784         } else {
4785                 bcnrc_val = 0;
4786         }
4787
4788         /*
4789          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4790          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4791          * set as 0x4.
4792          */
4793         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4794                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4795                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4796                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4797                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4798         else
4799                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4800                         IXGBE_MMW_SIZE_DEFAULT);
4801
4802         /* Set RTTBCNRC of queue X */
4803         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4804         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4805         IXGBE_WRITE_FLUSH(hw);
4806
4807         return 0;
4808 }
4809
4810 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4811         uint16_t tx_rate, uint64_t q_msk)
4812 {
4813         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4814         struct ixgbe_vf_info *vfinfo =
4815                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4816         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4817         uint32_t queue_stride =
4818                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4819         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4820         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4821         uint16_t total_rate = 0;
4822
4823         if (queue_end >= hw->mac.max_tx_queues)
4824                 return -EINVAL;
4825
4826         if (vfinfo != NULL) {
4827                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4828                         if (vf_idx == vf)
4829                                 continue;
4830                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4831                                 idx++)
4832                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4833                 }
4834         } else
4835                 return -EINVAL;
4836
4837         /* Store tx_rate for this vf. */
4838         for (idx = 0; idx < nb_q_per_pool; idx++) {
4839                 if (((uint64_t)0x1 << idx) & q_msk) {
4840                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4841                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4842                         total_rate += tx_rate;
4843                 }
4844         }
4845
4846         if (total_rate > dev->data->dev_link.link_speed) {
4847                 /*
4848                  * Reset stored TX rate of the VF if it causes exceed
4849                  * link speed.
4850                  */
4851                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4852                 return -EINVAL;
4853         }
4854
4855         /* Set RTTBCNRC of each queue/pool for vf X  */
4856         for (; queue_idx <= queue_end; queue_idx++) {
4857                 if (0x1 & q_msk)
4858                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4859                 q_msk = q_msk >> 1;
4860         }
4861
4862         return 0;
4863 }
4864
4865 static void
4866 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4867                      __attribute__((unused)) uint32_t index,
4868                      __attribute__((unused)) uint32_t pool)
4869 {
4870         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4871         int diag;
4872
4873         /*
4874          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4875          * operation. Trap this case to avoid exhausting the [very limited]
4876          * set of PF resources used to store VF MAC addresses.
4877          */
4878         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4879                 return;
4880         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4881         if (diag == 0)
4882                 return;
4883         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4884 }
4885
4886 static void
4887 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4888 {
4889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4890         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4891         struct ether_addr *mac_addr;
4892         uint32_t i;
4893         int diag;
4894
4895         /*
4896          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4897          * not support the deletion of a given MAC address.
4898          * Instead, it imposes to delete all MAC addresses, then to add again
4899          * all MAC addresses with the exception of the one to be deleted.
4900          */
4901         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4902
4903         /*
4904          * Add again all MAC addresses, with the exception of the deleted one
4905          * and of the permanent MAC address.
4906          */
4907         for (i = 0, mac_addr = dev->data->mac_addrs;
4908              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4909                 /* Skip the deleted MAC address */
4910                 if (i == index)
4911                         continue;
4912                 /* Skip NULL MAC addresses */
4913                 if (is_zero_ether_addr(mac_addr))
4914                         continue;
4915                 /* Skip the permanent MAC address */
4916                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4917                         continue;
4918                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4919                 if (diag != 0)
4920                         PMD_DRV_LOG(ERR,
4921                                     "Adding again MAC address "
4922                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4923                                     "diag=%d",
4924                                     mac_addr->addr_bytes[0],
4925                                     mac_addr->addr_bytes[1],
4926                                     mac_addr->addr_bytes[2],
4927                                     mac_addr->addr_bytes[3],
4928                                     mac_addr->addr_bytes[4],
4929                                     mac_addr->addr_bytes[5],
4930                                     diag);
4931         }
4932 }
4933
4934 static void
4935 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4936 {
4937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4938
4939         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4940 }
4941
4942 #define MAC_TYPE_FILTER_SUP(type)    do {\
4943         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4944                 (type) != ixgbe_mac_X550)\
4945                 return -ENOTSUP;\
4946 } while (0)
4947
4948 static int
4949 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4950                         struct rte_eth_syn_filter *filter,
4951                         bool add)
4952 {
4953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4954         uint32_t synqf;
4955
4956         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4957                 return -EINVAL;
4958
4959         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4960
4961         if (add) {
4962                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4963                         return -EINVAL;
4964                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4965                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4966
4967                 if (filter->hig_pri)
4968                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4969                 else
4970                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4971         } else {
4972                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4973                         return -ENOENT;
4974                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4975         }
4976         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4977         IXGBE_WRITE_FLUSH(hw);
4978         return 0;
4979 }
4980
4981 static int
4982 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4983                         struct rte_eth_syn_filter *filter)
4984 {
4985         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4986         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4987
4988         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4989                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4990                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4991                 return 0;
4992         }
4993         return -ENOENT;
4994 }
4995
4996 static int
4997 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4998                         enum rte_filter_op filter_op,
4999                         void *arg)
5000 {
5001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5002         int ret;
5003
5004         MAC_TYPE_FILTER_SUP(hw->mac.type);
5005
5006         if (filter_op == RTE_ETH_FILTER_NOP)
5007                 return 0;
5008
5009         if (arg == NULL) {
5010                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5011                             filter_op);
5012                 return -EINVAL;
5013         }
5014
5015         switch (filter_op) {
5016         case RTE_ETH_FILTER_ADD:
5017                 ret = ixgbe_syn_filter_set(dev,
5018                                 (struct rte_eth_syn_filter *)arg,
5019                                 TRUE);
5020                 break;
5021         case RTE_ETH_FILTER_DELETE:
5022                 ret = ixgbe_syn_filter_set(dev,
5023                                 (struct rte_eth_syn_filter *)arg,
5024                                 FALSE);
5025                 break;
5026         case RTE_ETH_FILTER_GET:
5027                 ret = ixgbe_syn_filter_get(dev,
5028                                 (struct rte_eth_syn_filter *)arg);
5029                 break;
5030         default:
5031                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5032                 ret = -EINVAL;
5033                 break;
5034         }
5035
5036         return ret;
5037 }
5038
5039
5040 static inline enum ixgbe_5tuple_protocol
5041 convert_protocol_type(uint8_t protocol_value)
5042 {
5043         if (protocol_value == IPPROTO_TCP)
5044                 return IXGBE_FILTER_PROTOCOL_TCP;
5045         else if (protocol_value == IPPROTO_UDP)
5046                 return IXGBE_FILTER_PROTOCOL_UDP;
5047         else if (protocol_value == IPPROTO_SCTP)
5048                 return IXGBE_FILTER_PROTOCOL_SCTP;
5049         else
5050                 return IXGBE_FILTER_PROTOCOL_NONE;
5051 }
5052
5053 /*
5054  * add a 5tuple filter
5055  *
5056  * @param
5057  * dev: Pointer to struct rte_eth_dev.
5058  * index: the index the filter allocates.
5059  * filter: ponter to the filter that will be added.
5060  * rx_queue: the queue id the filter assigned to.
5061  *
5062  * @return
5063  *    - On success, zero.
5064  *    - On failure, a negative value.
5065  */
5066 static int
5067 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5068                         struct ixgbe_5tuple_filter *filter)
5069 {
5070         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5071         struct ixgbe_filter_info *filter_info =
5072                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5073         int i, idx, shift;
5074         uint32_t ftqf, sdpqf;
5075         uint32_t l34timir = 0;
5076         uint8_t mask = 0xff;
5077
5078         /*
5079          * look for an unused 5tuple filter index,
5080          * and insert the filter to list.
5081          */
5082         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5083                 idx = i / (sizeof(uint32_t) * NBBY);
5084                 shift = i % (sizeof(uint32_t) * NBBY);
5085                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5086                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5087                         filter->index = i;
5088                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5089                                           filter,
5090                                           entries);
5091                         break;
5092                 }
5093         }
5094         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5095                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5096                 return -ENOSYS;
5097         }
5098
5099         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5100                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5101         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5102
5103         ftqf = (uint32_t)(filter->filter_info.proto &
5104                 IXGBE_FTQF_PROTOCOL_MASK);
5105         ftqf |= (uint32_t)((filter->filter_info.priority &
5106                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5107         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5108                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5109         if (filter->filter_info.dst_ip_mask == 0)
5110                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5111         if (filter->filter_info.src_port_mask == 0)
5112                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5113         if (filter->filter_info.dst_port_mask == 0)
5114                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5115         if (filter->filter_info.proto_mask == 0)
5116                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5117         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5118         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5119         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5120
5121         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5122         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5123         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5124         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5125
5126         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5127         l34timir |= (uint32_t)(filter->queue <<
5128                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5129         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5130         return 0;
5131 }
5132
5133 /*
5134  * remove a 5tuple filter
5135  *
5136  * @param
5137  * dev: Pointer to struct rte_eth_dev.
5138  * filter: the pointer of the filter will be removed.
5139  */
5140 static void
5141 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5142                         struct ixgbe_5tuple_filter *filter)
5143 {
5144         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5145         struct ixgbe_filter_info *filter_info =
5146                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5147         uint16_t index = filter->index;
5148
5149         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5150                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5151         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5152         rte_free(filter);
5153
5154         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5155         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5156         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5157         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5158         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5159 }
5160
5161 static int
5162 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5163 {
5164         struct ixgbe_hw *hw;
5165         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5166
5167         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5168
5169         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5170                 return -EINVAL;
5171
5172         /* refuse mtu that requires the support of scattered packets when this
5173          * feature has not been enabled before. */
5174         if (!dev->data->scattered_rx &&
5175             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5176              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5177                 return -EINVAL;
5178
5179         /*
5180          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5181          * request of the version 2.0 of the mailbox API.
5182          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5183          * of the mailbox API.
5184          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5185          * prior to 3.11.33 which contains the following change:
5186          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5187          */
5188         ixgbevf_rlpml_set_vf(hw, max_frame);
5189
5190         /* update max frame size */
5191         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5192         return 0;
5193 }
5194
5195 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5196         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5197                 return -ENOTSUP;\
5198 } while (0)
5199
5200 static inline struct ixgbe_5tuple_filter *
5201 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5202                         struct ixgbe_5tuple_filter_info *key)
5203 {
5204         struct ixgbe_5tuple_filter *it;
5205
5206         TAILQ_FOREACH(it, filter_list, entries) {
5207                 if (memcmp(key, &it->filter_info,
5208                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5209                         return it;
5210                 }
5211         }
5212         return NULL;
5213 }
5214
5215 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5216 static inline int
5217 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5218                         struct ixgbe_5tuple_filter_info *filter_info)
5219 {
5220         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5221                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5222                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5223                 return -EINVAL;
5224
5225         switch (filter->dst_ip_mask) {
5226         case UINT32_MAX:
5227                 filter_info->dst_ip_mask = 0;
5228                 filter_info->dst_ip = filter->dst_ip;
5229                 break;
5230         case 0:
5231                 filter_info->dst_ip_mask = 1;
5232                 break;
5233         default:
5234                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5235                 return -EINVAL;
5236         }
5237
5238         switch (filter->src_ip_mask) {
5239         case UINT32_MAX:
5240                 filter_info->src_ip_mask = 0;
5241                 filter_info->src_ip = filter->src_ip;
5242                 break;
5243         case 0:
5244                 filter_info->src_ip_mask = 1;
5245                 break;
5246         default:
5247                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5248                 return -EINVAL;
5249         }
5250
5251         switch (filter->dst_port_mask) {
5252         case UINT16_MAX:
5253                 filter_info->dst_port_mask = 0;
5254                 filter_info->dst_port = filter->dst_port;
5255                 break;
5256         case 0:
5257                 filter_info->dst_port_mask = 1;
5258                 break;
5259         default:
5260                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5261                 return -EINVAL;
5262         }
5263
5264         switch (filter->src_port_mask) {
5265         case UINT16_MAX:
5266                 filter_info->src_port_mask = 0;
5267                 filter_info->src_port = filter->src_port;
5268                 break;
5269         case 0:
5270                 filter_info->src_port_mask = 1;
5271                 break;
5272         default:
5273                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5274                 return -EINVAL;
5275         }
5276
5277         switch (filter->proto_mask) {
5278         case UINT8_MAX:
5279                 filter_info->proto_mask = 0;
5280                 filter_info->proto =
5281                         convert_protocol_type(filter->proto);
5282                 break;
5283         case 0:
5284                 filter_info->proto_mask = 1;
5285                 break;
5286         default:
5287                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5288                 return -EINVAL;
5289         }
5290
5291         filter_info->priority = (uint8_t)filter->priority;
5292         return 0;
5293 }
5294
5295 /*
5296  * add or delete a ntuple filter
5297  *
5298  * @param
5299  * dev: Pointer to struct rte_eth_dev.
5300  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5301  * add: if true, add filter, if false, remove filter
5302  *
5303  * @return
5304  *    - On success, zero.
5305  *    - On failure, a negative value.
5306  */
5307 static int
5308 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5309                         struct rte_eth_ntuple_filter *ntuple_filter,
5310                         bool add)
5311 {
5312         struct ixgbe_filter_info *filter_info =
5313                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5314         struct ixgbe_5tuple_filter_info filter_5tuple;
5315         struct ixgbe_5tuple_filter *filter;
5316         int ret;
5317
5318         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5319                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5320                 return -EINVAL;
5321         }
5322
5323         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5324         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5325         if (ret < 0)
5326                 return ret;
5327
5328         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5329                                          &filter_5tuple);
5330         if (filter != NULL && add) {
5331                 PMD_DRV_LOG(ERR, "filter exists.");
5332                 return -EEXIST;
5333         }
5334         if (filter == NULL && !add) {
5335                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5336                 return -ENOENT;
5337         }
5338
5339         if (add) {
5340                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5341                                 sizeof(struct ixgbe_5tuple_filter), 0);
5342                 if (filter == NULL)
5343                         return -ENOMEM;
5344                 (void)rte_memcpy(&filter->filter_info,
5345                                  &filter_5tuple,
5346                                  sizeof(struct ixgbe_5tuple_filter_info));
5347                 filter->queue = ntuple_filter->queue;
5348                 ret = ixgbe_add_5tuple_filter(dev, filter);
5349                 if (ret < 0) {
5350                         rte_free(filter);
5351                         return ret;
5352                 }
5353         } else
5354                 ixgbe_remove_5tuple_filter(dev, filter);
5355
5356         return 0;
5357 }
5358
5359 /*
5360  * get a ntuple filter
5361  *
5362  * @param
5363  * dev: Pointer to struct rte_eth_dev.
5364  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5365  *
5366  * @return
5367  *    - On success, zero.
5368  *    - On failure, a negative value.
5369  */
5370 static int
5371 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5372                         struct rte_eth_ntuple_filter *ntuple_filter)
5373 {
5374         struct ixgbe_filter_info *filter_info =
5375                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5376         struct ixgbe_5tuple_filter_info filter_5tuple;
5377         struct ixgbe_5tuple_filter *filter;
5378         int ret;
5379
5380         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5381                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5382                 return -EINVAL;
5383         }
5384
5385         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5386         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5387         if (ret < 0)
5388                 return ret;
5389
5390         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5391                                          &filter_5tuple);
5392         if (filter == NULL) {
5393                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5394                 return -ENOENT;
5395         }
5396         ntuple_filter->queue = filter->queue;
5397         return 0;
5398 }
5399
5400 /*
5401  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5402  * @dev: pointer to rte_eth_dev structure
5403  * @filter_op:operation will be taken.
5404  * @arg: a pointer to specific structure corresponding to the filter_op
5405  *
5406  * @return
5407  *    - On success, zero.
5408  *    - On failure, a negative value.
5409  */
5410 static int
5411 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5412                                 enum rte_filter_op filter_op,
5413                                 void *arg)
5414 {
5415         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5416         int ret;
5417
5418         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5419
5420         if (filter_op == RTE_ETH_FILTER_NOP)
5421                 return 0;
5422
5423         if (arg == NULL) {
5424                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5425                             filter_op);
5426                 return -EINVAL;
5427         }
5428
5429         switch (filter_op) {
5430         case RTE_ETH_FILTER_ADD:
5431                 ret = ixgbe_add_del_ntuple_filter(dev,
5432                         (struct rte_eth_ntuple_filter *)arg,
5433                         TRUE);
5434                 break;
5435         case RTE_ETH_FILTER_DELETE:
5436                 ret = ixgbe_add_del_ntuple_filter(dev,
5437                         (struct rte_eth_ntuple_filter *)arg,
5438                         FALSE);
5439                 break;
5440         case RTE_ETH_FILTER_GET:
5441                 ret = ixgbe_get_ntuple_filter(dev,
5442                         (struct rte_eth_ntuple_filter *)arg);
5443                 break;
5444         default:
5445                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5446                 ret = -EINVAL;
5447                 break;
5448         }
5449         return ret;
5450 }
5451
5452 static inline int
5453 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5454                         uint16_t ethertype)
5455 {
5456         int i;
5457
5458         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5459                 if (filter_info->ethertype_filters[i] == ethertype &&
5460                     (filter_info->ethertype_mask & (1 << i)))
5461                         return i;
5462         }
5463         return -1;
5464 }
5465
5466 static inline int
5467 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5468                         uint16_t ethertype)
5469 {
5470         int i;
5471
5472         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5473                 if (!(filter_info->ethertype_mask & (1 << i))) {
5474                         filter_info->ethertype_mask |= 1 << i;
5475                         filter_info->ethertype_filters[i] = ethertype;
5476                         return i;
5477                 }
5478         }
5479         return -1;
5480 }
5481
5482 static inline int
5483 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5484                         uint8_t idx)
5485 {
5486         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5487                 return -1;
5488         filter_info->ethertype_mask &= ~(1 << idx);
5489         filter_info->ethertype_filters[idx] = 0;
5490         return idx;
5491 }
5492
5493 static int
5494 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5495                         struct rte_eth_ethertype_filter *filter,
5496                         bool add)
5497 {
5498         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5499         struct ixgbe_filter_info *filter_info =
5500                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5501         uint32_t etqf = 0;
5502         uint32_t etqs = 0;
5503         int ret;
5504
5505         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5506                 return -EINVAL;
5507
5508         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5509                 filter->ether_type == ETHER_TYPE_IPv6) {
5510                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5511                         " ethertype filter.", filter->ether_type);
5512                 return -EINVAL;
5513         }
5514
5515         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5516                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5517                 return -EINVAL;
5518         }
5519         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5520                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5521                 return -EINVAL;
5522         }
5523
5524         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5525         if (ret >= 0 && add) {
5526                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5527                             filter->ether_type);
5528                 return -EEXIST;
5529         }
5530         if (ret < 0 && !add) {
5531                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5532                             filter->ether_type);
5533                 return -ENOENT;
5534         }
5535
5536         if (add) {
5537                 ret = ixgbe_ethertype_filter_insert(filter_info,
5538                         filter->ether_type);
5539                 if (ret < 0) {
5540                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5541                         return -ENOSYS;
5542                 }
5543                 etqf = IXGBE_ETQF_FILTER_EN;
5544                 etqf |= (uint32_t)filter->ether_type;
5545                 etqs |= (uint32_t)((filter->queue <<
5546                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5547                                     IXGBE_ETQS_RX_QUEUE);
5548                 etqs |= IXGBE_ETQS_QUEUE_EN;
5549         } else {
5550                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5551                 if (ret < 0)
5552                         return -ENOSYS;
5553         }
5554         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5555         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5556         IXGBE_WRITE_FLUSH(hw);
5557
5558         return 0;
5559 }
5560
5561 static int
5562 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5563                         struct rte_eth_ethertype_filter *filter)
5564 {
5565         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5566         struct ixgbe_filter_info *filter_info =
5567                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5568         uint32_t etqf, etqs;
5569         int ret;
5570
5571         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5572         if (ret < 0) {
5573                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5574                             filter->ether_type);
5575                 return -ENOENT;
5576         }
5577
5578         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5579         if (etqf & IXGBE_ETQF_FILTER_EN) {
5580                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5581                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5582                 filter->flags = 0;
5583                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5584                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5585                 return 0;
5586         }
5587         return -ENOENT;
5588 }
5589
5590 /*
5591  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5592  * @dev: pointer to rte_eth_dev structure
5593  * @filter_op:operation will be taken.
5594  * @arg: a pointer to specific structure corresponding to the filter_op
5595  */
5596 static int
5597 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5598                                 enum rte_filter_op filter_op,
5599                                 void *arg)
5600 {
5601         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5602         int ret;
5603
5604         MAC_TYPE_FILTER_SUP(hw->mac.type);
5605
5606         if (filter_op == RTE_ETH_FILTER_NOP)
5607                 return 0;
5608
5609         if (arg == NULL) {
5610                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5611                             filter_op);
5612                 return -EINVAL;
5613         }
5614
5615         switch (filter_op) {
5616         case RTE_ETH_FILTER_ADD:
5617                 ret = ixgbe_add_del_ethertype_filter(dev,
5618                         (struct rte_eth_ethertype_filter *)arg,
5619                         TRUE);
5620                 break;
5621         case RTE_ETH_FILTER_DELETE:
5622                 ret = ixgbe_add_del_ethertype_filter(dev,
5623                         (struct rte_eth_ethertype_filter *)arg,
5624                         FALSE);
5625                 break;
5626         case RTE_ETH_FILTER_GET:
5627                 ret = ixgbe_get_ethertype_filter(dev,
5628                         (struct rte_eth_ethertype_filter *)arg);
5629                 break;
5630         default:
5631                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5632                 ret = -EINVAL;
5633                 break;
5634         }
5635         return ret;
5636 }
5637
5638 static int
5639 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5640                      enum rte_filter_type filter_type,
5641                      enum rte_filter_op filter_op,
5642                      void *arg)
5643 {
5644         int ret = -EINVAL;
5645
5646         switch (filter_type) {
5647         case RTE_ETH_FILTER_NTUPLE:
5648                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5649                 break;
5650         case RTE_ETH_FILTER_ETHERTYPE:
5651                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5652                 break;
5653         case RTE_ETH_FILTER_SYN:
5654                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5655                 break;
5656         case RTE_ETH_FILTER_FDIR:
5657                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5658                 break;
5659         case RTE_ETH_FILTER_L2_TUNNEL:
5660                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5661                 break;
5662         default:
5663                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5664                                                         filter_type);
5665                 break;
5666         }
5667
5668         return ret;
5669 }
5670
5671 static u8 *
5672 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5673                         u8 **mc_addr_ptr, u32 *vmdq)
5674 {
5675         u8 *mc_addr;
5676
5677         *vmdq = 0;
5678         mc_addr = *mc_addr_ptr;
5679         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5680         return mc_addr;
5681 }
5682
5683 static int
5684 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5685                           struct ether_addr *mc_addr_set,
5686                           uint32_t nb_mc_addr)
5687 {
5688         struct ixgbe_hw *hw;
5689         u8 *mc_addr_list;
5690
5691         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5692         mc_addr_list = (u8 *)mc_addr_set;
5693         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5694                                          ixgbe_dev_addr_list_itr, TRUE);
5695 }
5696
5697 static uint64_t
5698 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5699 {
5700         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5701         uint64_t systime_cycles;
5702
5703         switch (hw->mac.type) {
5704         case ixgbe_mac_X550:
5705                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5706                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5707                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5708                                 * NSEC_PER_SEC;
5709                 break;
5710         default:
5711                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5712                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5713                                 << 32;
5714         }
5715
5716         return systime_cycles;
5717 }
5718
5719 static uint64_t
5720 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5721 {
5722         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5723         uint64_t rx_tstamp_cycles;
5724
5725         switch (hw->mac.type) {
5726         case ixgbe_mac_X550:
5727                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5728                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5729                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5730                                 * NSEC_PER_SEC;
5731                 break;
5732         default:
5733                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5734                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5735                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5736                                 << 32;
5737         }
5738
5739         return rx_tstamp_cycles;
5740 }
5741
5742 static uint64_t
5743 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5744 {
5745         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746         uint64_t tx_tstamp_cycles;
5747
5748         switch (hw->mac.type) {
5749         case ixgbe_mac_X550:
5750                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5751                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5752                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5753                                 * NSEC_PER_SEC;
5754                 break;
5755         default:
5756                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5757                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5758                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5759                                 << 32;
5760         }
5761
5762         return tx_tstamp_cycles;
5763 }
5764
5765 static void
5766 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5767 {
5768         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5769         struct ixgbe_adapter *adapter =
5770                 (struct ixgbe_adapter *)dev->data->dev_private;
5771         struct rte_eth_link link;
5772         uint32_t incval = 0;
5773         uint32_t shift = 0;
5774
5775         /* Get current link speed. */
5776         memset(&link, 0, sizeof(link));
5777         ixgbe_dev_link_update(dev, 1);
5778         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5779
5780         switch (link.link_speed) {
5781         case ETH_LINK_SPEED_100:
5782                 incval = IXGBE_INCVAL_100;
5783                 shift = IXGBE_INCVAL_SHIFT_100;
5784                 break;
5785         case ETH_LINK_SPEED_1000:
5786                 incval = IXGBE_INCVAL_1GB;
5787                 shift = IXGBE_INCVAL_SHIFT_1GB;
5788                 break;
5789         case ETH_LINK_SPEED_10000:
5790         default:
5791                 incval = IXGBE_INCVAL_10GB;
5792                 shift = IXGBE_INCVAL_SHIFT_10GB;
5793                 break;
5794         }
5795
5796         switch (hw->mac.type) {
5797         case ixgbe_mac_X550:
5798                 /* Independent of link speed. */
5799                 incval = 1;
5800                 /* Cycles read will be interpreted as ns. */
5801                 shift = 0;
5802                 /* Fall-through */
5803         case ixgbe_mac_X540:
5804                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5805                 break;
5806         case ixgbe_mac_82599EB:
5807                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5808                 shift -= IXGBE_INCVAL_SHIFT_82599;
5809                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5810                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5811                 break;
5812         default:
5813                 /* Not supported. */
5814                 return;
5815         }
5816
5817         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5818         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5819         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5820
5821         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5822         adapter->systime_tc.cc_shift = shift;
5823         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5824
5825         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5826         adapter->rx_tstamp_tc.cc_shift = shift;
5827         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5828
5829         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5830         adapter->tx_tstamp_tc.cc_shift = shift;
5831         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5832 }
5833
5834 static int
5835 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5836 {
5837         struct ixgbe_adapter *adapter =
5838                         (struct ixgbe_adapter *)dev->data->dev_private;
5839
5840         adapter->systime_tc.nsec += delta;
5841         adapter->rx_tstamp_tc.nsec += delta;
5842         adapter->tx_tstamp_tc.nsec += delta;
5843
5844         return 0;
5845 }
5846
5847 static int
5848 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5849 {
5850         uint64_t ns;
5851         struct ixgbe_adapter *adapter =
5852                         (struct ixgbe_adapter *)dev->data->dev_private;
5853
5854         ns = rte_timespec_to_ns(ts);
5855         /* Set the timecounters to a new value. */
5856         adapter->systime_tc.nsec = ns;
5857         adapter->rx_tstamp_tc.nsec = ns;
5858         adapter->tx_tstamp_tc.nsec = ns;
5859
5860         return 0;
5861 }
5862
5863 static int
5864 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5865 {
5866         uint64_t ns, systime_cycles;
5867         struct ixgbe_adapter *adapter =
5868                         (struct ixgbe_adapter *)dev->data->dev_private;
5869
5870         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5871         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5872         *ts = rte_ns_to_timespec(ns);
5873
5874         return 0;
5875 }
5876
5877 static int
5878 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5879 {
5880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5881         uint32_t tsync_ctl;
5882         uint32_t tsauxc;
5883
5884         /* Stop the timesync system time. */
5885         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5886         /* Reset the timesync system time value. */
5887         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5888         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5889
5890         /* Enable system time for platforms where it isn't on by default. */
5891         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5892         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5893         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5894
5895         ixgbe_start_timecounters(dev);
5896
5897         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5898         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5899                         (ETHER_TYPE_1588 |
5900                          IXGBE_ETQF_FILTER_EN |
5901                          IXGBE_ETQF_1588));
5902
5903         /* Enable timestamping of received PTP packets. */
5904         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5905         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5906         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5907
5908         /* Enable timestamping of transmitted PTP packets. */
5909         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5910         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5911         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5912
5913         IXGBE_WRITE_FLUSH(hw);
5914
5915         return 0;
5916 }
5917
5918 static int
5919 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5920 {
5921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5922         uint32_t tsync_ctl;
5923
5924         /* Disable timestamping of transmitted PTP packets. */
5925         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5926         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5927         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5928
5929         /* Disable timestamping of received PTP packets. */
5930         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5931         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5932         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5933
5934         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5935         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5936
5937         /* Stop incrementating the System Time registers. */
5938         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5939
5940         return 0;
5941 }
5942
5943 static int
5944 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5945                                  struct timespec *timestamp,
5946                                  uint32_t flags __rte_unused)
5947 {
5948         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5949         struct ixgbe_adapter *adapter =
5950                 (struct ixgbe_adapter *)dev->data->dev_private;
5951         uint32_t tsync_rxctl;
5952         uint64_t rx_tstamp_cycles;
5953         uint64_t ns;
5954
5955         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5956         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5957                 return -EINVAL;
5958
5959         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
5960         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5961         *timestamp = rte_ns_to_timespec(ns);
5962
5963         return  0;
5964 }
5965
5966 static int
5967 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5968                                  struct timespec *timestamp)
5969 {
5970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5971         struct ixgbe_adapter *adapter =
5972                 (struct ixgbe_adapter *)dev->data->dev_private;
5973         uint32_t tsync_txctl;
5974         uint64_t tx_tstamp_cycles;
5975         uint64_t ns;
5976
5977         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5978         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5979                 return -EINVAL;
5980
5981         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
5982         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5983         *timestamp = rte_ns_to_timespec(ns);
5984
5985         return 0;
5986 }
5987
5988 static int
5989 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5990 {
5991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5992         int count = 0;
5993         int g_ind = 0;
5994         const struct reg_info *reg_group;
5995         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5996                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5997
5998         while ((reg_group = reg_set[g_ind++]))
5999                 count += ixgbe_regs_group_count(reg_group);
6000
6001         return count;
6002 }
6003
6004 static int
6005 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6006 {
6007         int count = 0;
6008         int g_ind = 0;
6009         const struct reg_info *reg_group;
6010
6011         while ((reg_group = ixgbevf_regs[g_ind++]))
6012                 count += ixgbe_regs_group_count(reg_group);
6013
6014         return count;
6015 }
6016
6017 static int
6018 ixgbe_get_regs(struct rte_eth_dev *dev,
6019               struct rte_dev_reg_info *regs)
6020 {
6021         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6022         uint32_t *data = regs->data;
6023         int g_ind = 0;
6024         int count = 0;
6025         const struct reg_info *reg_group;
6026         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6027                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6028
6029         /* Support only full register dump */
6030         if ((regs->length == 0) ||
6031             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6032                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6033                         hw->device_id;
6034                 while ((reg_group = reg_set[g_ind++]))
6035                         count += ixgbe_read_regs_group(dev, &data[count],
6036                                 reg_group);
6037                 return 0;
6038         }
6039
6040         return -ENOTSUP;
6041 }
6042
6043 static int
6044 ixgbevf_get_regs(struct rte_eth_dev *dev,
6045                 struct rte_dev_reg_info *regs)
6046 {
6047         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6048         uint32_t *data = regs->data;
6049         int g_ind = 0;
6050         int count = 0;
6051         const struct reg_info *reg_group;
6052
6053         /* Support only full register dump */
6054         if ((regs->length == 0) ||
6055             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6056                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6057                         hw->device_id;
6058                 while ((reg_group = ixgbevf_regs[g_ind++]))
6059                         count += ixgbe_read_regs_group(dev, &data[count],
6060                                                       reg_group);
6061                 return 0;
6062         }
6063
6064         return -ENOTSUP;
6065 }
6066
6067 static int
6068 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6069 {
6070         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6071
6072         /* Return unit is byte count */
6073         return hw->eeprom.word_size * 2;
6074 }
6075
6076 static int
6077 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6078                 struct rte_dev_eeprom_info *in_eeprom)
6079 {
6080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6081         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6082         uint16_t *data = in_eeprom->data;
6083         int first, length;
6084
6085         first = in_eeprom->offset >> 1;
6086         length = in_eeprom->length >> 1;
6087         if ((first > hw->eeprom.word_size) ||
6088             ((first + length) > hw->eeprom.word_size))
6089                 return -EINVAL;
6090
6091         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6092
6093         return eeprom->ops.read_buffer(hw, first, length, data);
6094 }
6095
6096 static int
6097 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6098                 struct rte_dev_eeprom_info *in_eeprom)
6099 {
6100         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6101         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6102         uint16_t *data = in_eeprom->data;
6103         int first, length;
6104
6105         first = in_eeprom->offset >> 1;
6106         length = in_eeprom->length >> 1;
6107         if ((first > hw->eeprom.word_size) ||
6108             ((first + length) > hw->eeprom.word_size))
6109                 return -EINVAL;
6110
6111         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6112
6113         return eeprom->ops.write_buffer(hw,  first, length, data);
6114 }
6115
6116 uint16_t
6117 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6118         switch (mac_type) {
6119         case ixgbe_mac_X550:
6120         case ixgbe_mac_X550EM_x:
6121                 return ETH_RSS_RETA_SIZE_512;
6122         case ixgbe_mac_X550_vf:
6123         case ixgbe_mac_X550EM_x_vf:
6124                 return ETH_RSS_RETA_SIZE_64;
6125         default:
6126                 return ETH_RSS_RETA_SIZE_128;
6127         }
6128 }
6129
6130 uint32_t
6131 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6132         switch (mac_type) {
6133         case ixgbe_mac_X550:
6134         case ixgbe_mac_X550EM_x:
6135                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6136                         return IXGBE_RETA(reta_idx >> 2);
6137                 else
6138                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6139         case ixgbe_mac_X550_vf:
6140         case ixgbe_mac_X550EM_x_vf:
6141                 return IXGBE_VFRETA(reta_idx >> 2);
6142         default:
6143                 return IXGBE_RETA(reta_idx >> 2);
6144         }
6145 }
6146
6147 uint32_t
6148 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6149         switch (mac_type) {
6150         case ixgbe_mac_X550_vf:
6151         case ixgbe_mac_X550EM_x_vf:
6152                 return IXGBE_VFMRQC;
6153         default:
6154                 return IXGBE_MRQC;
6155         }
6156 }
6157
6158 uint32_t
6159 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6160         switch (mac_type) {
6161         case ixgbe_mac_X550_vf:
6162         case ixgbe_mac_X550EM_x_vf:
6163                 return IXGBE_VFRSSRK(i);
6164         default:
6165                 return IXGBE_RSSRK(i);
6166         }
6167 }
6168
6169 bool
6170 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6171         switch (mac_type) {
6172         case ixgbe_mac_82599_vf:
6173         case ixgbe_mac_X540_vf:
6174                 return 0;
6175         default:
6176                 return 1;
6177         }
6178 }
6179
6180 static int
6181 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6182                         struct rte_eth_dcb_info *dcb_info)
6183 {
6184         struct ixgbe_dcb_config *dcb_config =
6185                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6186         struct ixgbe_dcb_tc_config *tc;
6187         uint8_t i, j;
6188
6189         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6190                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6191         else
6192                 dcb_info->nb_tcs = 1;
6193
6194         if (dcb_config->vt_mode) { /* vt is enabled*/
6195                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6196                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6197                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6198                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6199                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6200                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6201                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6202                                                 i * dcb_info->nb_tcs + j;
6203                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6204                                 dcb_info->tc_queue.tc_txq[i][j].base =
6205                                                 i * dcb_info->nb_tcs + j;
6206                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6207                         }
6208                 }
6209         } else { /* vt is disabled*/
6210                 struct rte_eth_dcb_rx_conf *rx_conf =
6211                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6212                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6213                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6214                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6215                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6216                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6217                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6218                         }
6219                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6220                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6221                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6222                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6223                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6224                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6225                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6226                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6227                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6228                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6229                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6230                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6231                         }
6232                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6233                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6234                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6235                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6236                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6237                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6238                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6239                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6240                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6241                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6242                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6243                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6244                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6245                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6246                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6247                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6248                 }
6249         }
6250         for (i = 0; i < dcb_info->nb_tcs; i++) {
6251                 tc = &dcb_config->tc_config[i];
6252                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6253         }
6254         return 0;
6255 }
6256
6257 /* Update e-tag ether type */
6258 static int
6259 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6260                             uint16_t ether_type)
6261 {
6262         uint32_t etag_etype;
6263
6264         if (hw->mac.type != ixgbe_mac_X550 &&
6265             hw->mac.type != ixgbe_mac_X550EM_x) {
6266                 return -ENOTSUP;
6267         }
6268
6269         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6270         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6271         etag_etype |= ether_type;
6272         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6273         IXGBE_WRITE_FLUSH(hw);
6274
6275         return 0;
6276 }
6277
6278 /* Config l2 tunnel ether type */
6279 static int
6280 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6281                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6282 {
6283         int ret = 0;
6284         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6285
6286         if (l2_tunnel == NULL)
6287                 return -EINVAL;
6288
6289         switch (l2_tunnel->l2_tunnel_type) {
6290         case RTE_L2_TUNNEL_TYPE_E_TAG:
6291                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6292                 break;
6293         default:
6294                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6295                 ret = -EINVAL;
6296                 break;
6297         }
6298
6299         return ret;
6300 }
6301
6302 /* Enable e-tag tunnel */
6303 static int
6304 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6305 {
6306         uint32_t etag_etype;
6307
6308         if (hw->mac.type != ixgbe_mac_X550 &&
6309             hw->mac.type != ixgbe_mac_X550EM_x) {
6310                 return -ENOTSUP;
6311         }
6312
6313         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6314         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6315         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6316         IXGBE_WRITE_FLUSH(hw);
6317
6318         return 0;
6319 }
6320
6321 /* Enable l2 tunnel */
6322 static int
6323 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6324                            enum rte_eth_tunnel_type l2_tunnel_type)
6325 {
6326         int ret = 0;
6327         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6328
6329         switch (l2_tunnel_type) {
6330         case RTE_L2_TUNNEL_TYPE_E_TAG:
6331                 ret = ixgbe_e_tag_enable(hw);
6332                 break;
6333         default:
6334                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6335                 ret = -EINVAL;
6336                 break;
6337         }
6338
6339         return ret;
6340 }
6341
6342 /* Disable e-tag tunnel */
6343 static int
6344 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6345 {
6346         uint32_t etag_etype;
6347
6348         if (hw->mac.type != ixgbe_mac_X550 &&
6349             hw->mac.type != ixgbe_mac_X550EM_x) {
6350                 return -ENOTSUP;
6351         }
6352
6353         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6354         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6355         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6356         IXGBE_WRITE_FLUSH(hw);
6357
6358         return 0;
6359 }
6360
6361 /* Disable l2 tunnel */
6362 static int
6363 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6364                             enum rte_eth_tunnel_type l2_tunnel_type)
6365 {
6366         int ret = 0;
6367         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6368
6369         switch (l2_tunnel_type) {
6370         case RTE_L2_TUNNEL_TYPE_E_TAG:
6371                 ret = ixgbe_e_tag_disable(hw);
6372                 break;
6373         default:
6374                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6375                 ret = -EINVAL;
6376                 break;
6377         }
6378
6379         return ret;
6380 }
6381
6382 static int
6383 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6384                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6385 {
6386         int ret = 0;
6387         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6388         uint32_t i, rar_entries;
6389         uint32_t rar_low, rar_high;
6390
6391         if (hw->mac.type != ixgbe_mac_X550 &&
6392             hw->mac.type != ixgbe_mac_X550EM_x) {
6393                 return -ENOTSUP;
6394         }
6395
6396         rar_entries = ixgbe_get_num_rx_addrs(hw);
6397
6398         for (i = 1; i < rar_entries; i++) {
6399                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6400                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6401                 if ((rar_high & IXGBE_RAH_AV) &&
6402                     (rar_high & IXGBE_RAH_ADTYPE) &&
6403                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6404                      l2_tunnel->tunnel_id)) {
6405                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6406                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6407
6408                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6409
6410                         return ret;
6411                 }
6412         }
6413
6414         return ret;
6415 }
6416
6417 static int
6418 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6419                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6420 {
6421         int ret = 0;
6422         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6423         uint32_t i, rar_entries;
6424         uint32_t rar_low, rar_high;
6425
6426         if (hw->mac.type != ixgbe_mac_X550 &&
6427             hw->mac.type != ixgbe_mac_X550EM_x) {
6428                 return -ENOTSUP;
6429         }
6430
6431         /* One entry for one tunnel. Try to remove potential existing entry. */
6432         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6433
6434         rar_entries = ixgbe_get_num_rx_addrs(hw);
6435
6436         for (i = 1; i < rar_entries; i++) {
6437                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6438                 if (rar_high & IXGBE_RAH_AV) {
6439                         continue;
6440                 } else {
6441                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6442                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6443                         rar_low = l2_tunnel->tunnel_id;
6444
6445                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6446                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6447
6448                         return ret;
6449                 }
6450         }
6451
6452         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6453                      " Please remove a rule before adding a new one.");
6454         return -EINVAL;
6455 }
6456
6457 /* Add l2 tunnel filter */
6458 static int
6459 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6460                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6461 {
6462         int ret = 0;
6463
6464         switch (l2_tunnel->l2_tunnel_type) {
6465         case RTE_L2_TUNNEL_TYPE_E_TAG:
6466                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6467                 break;
6468         default:
6469                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6470                 ret = -EINVAL;
6471                 break;
6472         }
6473
6474         return ret;
6475 }
6476
6477 /* Delete l2 tunnel filter */
6478 static int
6479 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6480                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6481 {
6482         int ret = 0;
6483
6484         switch (l2_tunnel->l2_tunnel_type) {
6485         case RTE_L2_TUNNEL_TYPE_E_TAG:
6486                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6487                 break;
6488         default:
6489                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6490                 ret = -EINVAL;
6491                 break;
6492         }
6493
6494         return ret;
6495 }
6496
6497 /**
6498  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6499  * @dev: pointer to rte_eth_dev structure
6500  * @filter_op:operation will be taken.
6501  * @arg: a pointer to specific structure corresponding to the filter_op
6502  */
6503 static int
6504 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6505                                   enum rte_filter_op filter_op,
6506                                   void *arg)
6507 {
6508         int ret = 0;
6509
6510         if (filter_op == RTE_ETH_FILTER_NOP)
6511                 return 0;
6512
6513         if (arg == NULL) {
6514                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6515                             filter_op);
6516                 return -EINVAL;
6517         }
6518
6519         switch (filter_op) {
6520         case RTE_ETH_FILTER_ADD:
6521                 ret = ixgbe_dev_l2_tunnel_filter_add
6522                         (dev,
6523                          (struct rte_eth_l2_tunnel_conf *)arg);
6524                 break;
6525         case RTE_ETH_FILTER_DELETE:
6526                 ret = ixgbe_dev_l2_tunnel_filter_del
6527                         (dev,
6528                          (struct rte_eth_l2_tunnel_conf *)arg);
6529                 break;
6530         default:
6531                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6532                 ret = -EINVAL;
6533                 break;
6534         }
6535         return ret;
6536 }
6537
6538 static int
6539 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6540 {
6541         int ret = 0;
6542         uint32_t ctrl;
6543         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6544
6545         if (hw->mac.type != ixgbe_mac_X550 &&
6546             hw->mac.type != ixgbe_mac_X550EM_x) {
6547                 return -ENOTSUP;
6548         }
6549
6550         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6551         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6552         if (en)
6553                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6554         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6555
6556         return ret;
6557 }
6558
6559 /* Enable l2 tunnel forwarding */
6560 static int
6561 ixgbe_dev_l2_tunnel_forwarding_enable
6562         (struct rte_eth_dev *dev,
6563          enum rte_eth_tunnel_type l2_tunnel_type)
6564 {
6565         int ret = 0;
6566
6567         switch (l2_tunnel_type) {
6568         case RTE_L2_TUNNEL_TYPE_E_TAG:
6569                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6570                 break;
6571         default:
6572                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6573                 ret = -EINVAL;
6574                 break;
6575         }
6576
6577         return ret;
6578 }
6579
6580 /* Disable l2 tunnel forwarding */
6581 static int
6582 ixgbe_dev_l2_tunnel_forwarding_disable
6583         (struct rte_eth_dev *dev,
6584          enum rte_eth_tunnel_type l2_tunnel_type)
6585 {
6586         int ret = 0;
6587
6588         switch (l2_tunnel_type) {
6589         case RTE_L2_TUNNEL_TYPE_E_TAG:
6590                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6591                 break;
6592         default:
6593                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6594                 ret = -EINVAL;
6595                 break;
6596         }
6597
6598         return ret;
6599 }
6600
6601 static int
6602 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6603                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6604                              bool en)
6605 {
6606         int ret = 0;
6607         uint32_t vmtir, vmvir;
6608         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6609
6610         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6611                 PMD_DRV_LOG(ERR,
6612                             "VF id %u should be less than %u",
6613                             l2_tunnel->vf_id,
6614                             dev->pci_dev->max_vfs);
6615                 return -EINVAL;
6616         }
6617
6618         if (hw->mac.type != ixgbe_mac_X550 &&
6619             hw->mac.type != ixgbe_mac_X550EM_x) {
6620                 return -ENOTSUP;
6621         }
6622
6623         if (en)
6624                 vmtir = l2_tunnel->tunnel_id;
6625         else
6626                 vmtir = 0;
6627
6628         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6629
6630         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6631         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6632         if (en)
6633                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6634         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6635
6636         return ret;
6637 }
6638
6639 /* Enable l2 tunnel tag insertion */
6640 static int
6641 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6642                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6643 {
6644         int ret = 0;
6645
6646         switch (l2_tunnel->l2_tunnel_type) {
6647         case RTE_L2_TUNNEL_TYPE_E_TAG:
6648                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6649                 break;
6650         default:
6651                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6652                 ret = -EINVAL;
6653                 break;
6654         }
6655
6656         return ret;
6657 }
6658
6659 /* Disable l2 tunnel tag insertion */
6660 static int
6661 ixgbe_dev_l2_tunnel_insertion_disable
6662         (struct rte_eth_dev *dev,
6663          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6664 {
6665         int ret = 0;
6666
6667         switch (l2_tunnel->l2_tunnel_type) {
6668         case RTE_L2_TUNNEL_TYPE_E_TAG:
6669                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6670                 break;
6671         default:
6672                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6673                 ret = -EINVAL;
6674                 break;
6675         }
6676
6677         return ret;
6678 }
6679
6680 static int
6681 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6682                              bool en)
6683 {
6684         int ret = 0;
6685         uint32_t qde;
6686         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6687
6688         if (hw->mac.type != ixgbe_mac_X550 &&
6689             hw->mac.type != ixgbe_mac_X550EM_x) {
6690                 return -ENOTSUP;
6691         }
6692
6693         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6694         if (en)
6695                 qde |= IXGBE_QDE_STRIP_TAG;
6696         else
6697                 qde &= ~IXGBE_QDE_STRIP_TAG;
6698         qde &= ~IXGBE_QDE_READ;
6699         qde |= IXGBE_QDE_WRITE;
6700         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6701
6702         return ret;
6703 }
6704
6705 /* Enable l2 tunnel tag stripping */
6706 static int
6707 ixgbe_dev_l2_tunnel_stripping_enable
6708         (struct rte_eth_dev *dev,
6709          enum rte_eth_tunnel_type l2_tunnel_type)
6710 {
6711         int ret = 0;
6712
6713         switch (l2_tunnel_type) {
6714         case RTE_L2_TUNNEL_TYPE_E_TAG:
6715                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6716                 break;
6717         default:
6718                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6719                 ret = -EINVAL;
6720                 break;
6721         }
6722
6723         return ret;
6724 }
6725
6726 /* Disable l2 tunnel tag stripping */
6727 static int
6728 ixgbe_dev_l2_tunnel_stripping_disable
6729         (struct rte_eth_dev *dev,
6730          enum rte_eth_tunnel_type l2_tunnel_type)
6731 {
6732         int ret = 0;
6733
6734         switch (l2_tunnel_type) {
6735         case RTE_L2_TUNNEL_TYPE_E_TAG:
6736                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6737                 break;
6738         default:
6739                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6740                 ret = -EINVAL;
6741                 break;
6742         }
6743
6744         return ret;
6745 }
6746
6747 /* Enable/disable l2 tunnel offload functions */
6748 static int
6749 ixgbe_dev_l2_tunnel_offload_set
6750         (struct rte_eth_dev *dev,
6751          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6752          uint32_t mask,
6753          uint8_t en)
6754 {
6755         int ret = 0;
6756
6757         if (l2_tunnel == NULL)
6758                 return -EINVAL;
6759
6760         ret = -EINVAL;
6761         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6762                 if (en)
6763                         ret = ixgbe_dev_l2_tunnel_enable(
6764                                 dev,
6765                                 l2_tunnel->l2_tunnel_type);
6766                 else
6767                         ret = ixgbe_dev_l2_tunnel_disable(
6768                                 dev,
6769                                 l2_tunnel->l2_tunnel_type);
6770         }
6771
6772         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6773                 if (en)
6774                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6775                                 dev,
6776                                 l2_tunnel);
6777                 else
6778                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6779                                 dev,
6780                                 l2_tunnel);
6781         }
6782
6783         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6784                 if (en)
6785                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6786                                 dev,
6787                                 l2_tunnel->l2_tunnel_type);
6788                 else
6789                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6790                                 dev,
6791                                 l2_tunnel->l2_tunnel_type);
6792         }
6793
6794         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6795                 if (en)
6796                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6797                                 dev,
6798                                 l2_tunnel->l2_tunnel_type);
6799                 else
6800                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6801                                 dev,
6802                                 l2_tunnel->l2_tunnel_type);
6803         }
6804
6805         return ret;
6806 }
6807
6808 static int
6809 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6810                         uint16_t port)
6811 {
6812         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6813         IXGBE_WRITE_FLUSH(hw);
6814
6815         return 0;
6816 }
6817
6818 /* There's only one register for VxLAN UDP port.
6819  * So, we cannot add several ports. Will update it.
6820  */
6821 static int
6822 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6823                      uint16_t port)
6824 {
6825         if (port == 0) {
6826                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6827                 return -EINVAL;
6828         }
6829
6830         return ixgbe_update_vxlan_port(hw, port);
6831 }
6832
6833 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6834  * UDP port, it must have a value.
6835  * So, will reset it to the original value 0.
6836  */
6837 static int
6838 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6839                      uint16_t port)
6840 {
6841         uint16_t cur_port;
6842
6843         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6844
6845         if (cur_port != port) {
6846                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6847                 return -EINVAL;
6848         }
6849
6850         return ixgbe_update_vxlan_port(hw, 0);
6851 }
6852
6853 /* Add UDP tunneling port */
6854 static int
6855 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6856                               struct rte_eth_udp_tunnel *udp_tunnel)
6857 {
6858         int ret = 0;
6859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6860
6861         if (hw->mac.type != ixgbe_mac_X550 &&
6862             hw->mac.type != ixgbe_mac_X550EM_x) {
6863                 return -ENOTSUP;
6864         }
6865
6866         if (udp_tunnel == NULL)
6867                 return -EINVAL;
6868
6869         switch (udp_tunnel->prot_type) {
6870         case RTE_TUNNEL_TYPE_VXLAN:
6871                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6872                 break;
6873
6874         case RTE_TUNNEL_TYPE_GENEVE:
6875         case RTE_TUNNEL_TYPE_TEREDO:
6876                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6877                 ret = -EINVAL;
6878                 break;
6879
6880         default:
6881                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6882                 ret = -EINVAL;
6883                 break;
6884         }
6885
6886         return ret;
6887 }
6888
6889 /* Remove UDP tunneling port */
6890 static int
6891 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6892                               struct rte_eth_udp_tunnel *udp_tunnel)
6893 {
6894         int ret = 0;
6895         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6896
6897         if (hw->mac.type != ixgbe_mac_X550 &&
6898             hw->mac.type != ixgbe_mac_X550EM_x) {
6899                 return -ENOTSUP;
6900         }
6901
6902         if (udp_tunnel == NULL)
6903                 return -EINVAL;
6904
6905         switch (udp_tunnel->prot_type) {
6906         case RTE_TUNNEL_TYPE_VXLAN:
6907                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
6908                 break;
6909         case RTE_TUNNEL_TYPE_GENEVE:
6910         case RTE_TUNNEL_TYPE_TEREDO:
6911                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6912                 ret = -EINVAL;
6913                 break;
6914         default:
6915                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6916                 ret = -EINVAL;
6917                 break;
6918         }
6919
6920         return ret;
6921 }
6922
6923 static struct rte_driver rte_ixgbe_driver = {
6924         .type = PMD_PDEV,
6925         .init = rte_ixgbe_pmd_init,
6926 };
6927
6928 static struct rte_driver rte_ixgbevf_driver = {
6929         .type = PMD_PDEV,
6930         .init = rte_ixgbevf_pmd_init,
6931 };
6932
6933 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6934 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);