drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstats *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstats *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 183                                              uint16_t queue_id,
 184                                              uint8_t stat_idx,
 185                                              uint8_t is_rx);
 186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 187                                struct rte_eth_dev_info *dev_info);
 188 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 190                                  struct rte_eth_dev_info *dev_info);
 191 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 192
 193 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 194                 uint16_t vlan_id, int on);
 195 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 196                                enum rte_vlan_type vlan_type,
 197                                uint16_t tpid_id);
 198 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 199                 uint16_t queue, bool on);
 200 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 201                 int on);
 202 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 203 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 204 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 205 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 206 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 207
 208 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 209 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 210 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 211                                struct rte_eth_fc_conf *fc_conf);
 212 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_pfc_conf *pfc_conf);
 216 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 217                         struct rte_eth_rss_reta_entry64 *reta_conf,
 218                         uint16_t reta_size);
 219 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 220                         struct rte_eth_rss_reta_entry64 *reta_conf,
 221                         uint16_t reta_size);
 222 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 226 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 227 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 228                 void *param);
 229 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 230 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 231                 uint32_t index, uint32_t pool);
 232 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 233 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 234                                            struct ether_addr *mac_addr);
 235 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 236
 237 /* For Virtual Function support */
 238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 240 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 241 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 243 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 246 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 256                                             uint16_t queue_id);
 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 258                                              uint16_t queue_id);
 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 260                                  uint8_t queue, uint8_t msix_vector);
 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 264
 265 /* For Eth VMDQ APIs support */
 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 267                 ether_addr * mac_addr, uint8_t on);
 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 269 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 270                 uint16_t rx_mask, uint8_t on);
 271 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 272 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 273 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 274                 uint64_t pool_mask, uint8_t vlan_on);
 275 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 276                 struct rte_eth_mirror_conf *mirror_conf,
 277                 uint8_t rule_id, uint8_t on);
 278 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 279                 uint8_t rule_id);
 280 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 281                                           uint16_t queue_id);
 282 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 283                                            uint16_t queue_id);
 284 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 285                                uint8_t queue, uint8_t msix_vector);
 286 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 287
 288 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 289                 uint16_t queue_idx, uint16_t tx_rate);
 290 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 291                 uint16_t tx_rate, uint64_t q_msk);
 292
 293 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 294                                  struct ether_addr *mac_addr,
 295                                  uint32_t index, uint32_t pool);
 296 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 297 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 298                                              struct ether_addr *mac_addr);
 299 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 300                         struct rte_eth_syn_filter *filter,
 301                         bool add);
 302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 303                         struct rte_eth_syn_filter *filter);
 304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 305                         enum rte_filter_op filter_op,
 306                         void *arg);
 307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 308                         struct ixgbe_5tuple_filter *filter);
 309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 310                         struct ixgbe_5tuple_filter *filter);
 311 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 312                         struct rte_eth_ntuple_filter *filter,
 313                         bool add);
 314 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 315                                 enum rte_filter_op filter_op,
 316                                 void *arg);
 317 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 318                         struct rte_eth_ntuple_filter *filter);
 319 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ethertype_filter *filter,
 321                         bool add);
 322 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ethertype_filter *filter);
 327 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 328                      enum rte_filter_type filter_type,
 329                      enum rte_filter_op filter_op,
 330                      void *arg);
 331 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 332
 333 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 334                                       struct ether_addr *mc_addr_set,
 335                                       uint32_t nb_mc_addr);
 336 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 337                                    struct rte_eth_dcb_info *dcb_info);
 338
 339 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 340 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 341                             struct rte_dev_reg_info *regs);
 342 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 343 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 344                                 struct rte_dev_eeprom_info *eeprom);
 345 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 346                                 struct rte_dev_eeprom_info *eeprom);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364
 365 static int ixgbe_dev_l2_tunnel_eth_type_conf
 366         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 367 static int ixgbe_dev_l2_tunnel_offload_set
 368         (struct rte_eth_dev *dev,
 369          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 370          uint32_t mask,
 371          uint8_t en);
 372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 373                                              enum rte_filter_op filter_op,
 374                                              void *arg);
 375
 376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 377                                          struct rte_eth_udp_tunnel *udp_tunnel);
 378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 379                                          struct rte_eth_udp_tunnel *udp_tunnel);
 380
 381 /*
 382  * Define VF Stats MACRO for Non "cleared on read" register
 383  */
 384 #define UPDATE_VF_STAT(reg, last, cur)                          \
 385 {                                                               \
 386         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 387         cur += (latest - last) & UINT_MAX;                      \
 388         last = latest;                                          \
 389 }
 390
 391 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 392 {                                                                \
 393         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 394         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 395         u64 latest = ((new_msb << 32) | new_lsb);                \
 396         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 397         last = latest;                                           \
 398 }
 399
 400 #define IXGBE_SET_HWSTRIP(h, q) do {\
 401                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 402                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 403                 (h)->bitmap[idx] |= 1 << bit;\
 404         } while (0)
 405
 406 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 407                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 408                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 409                 (h)->bitmap[idx] &= ~(1 << bit);\
 410         } while (0)
 411
 412 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 413                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 414                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 415                 (r) = (h)->bitmap[idx] >> bit & 1;\
 416         } while (0)
 417
 418 /*
 419  * The set of PCI devices this driver supports
 420  */
 421 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 422
 423 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 424 #include "rte_pci_dev_ids.h"
 425
 426 { .vendor_id = 0, /* sentinel */ },
 427 };
 428
 429
 430 /*
 431  * The set of PCI devices this driver supports (for 82599 VF)
 432  */
 433 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 434
 435 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 436 #include "rte_pci_dev_ids.h"
 437 { .vendor_id = 0, /* sentinel */ },
 438
 439 };
 440
 441 static const struct rte_eth_desc_lim rx_desc_lim = {
 442         .nb_max = IXGBE_MAX_RING_DESC,
 443         .nb_min = IXGBE_MIN_RING_DESC,
 444         .nb_align = IXGBE_RXD_ALIGN,
 445 };
 446
 447 static const struct rte_eth_desc_lim tx_desc_lim = {
 448         .nb_max = IXGBE_MAX_RING_DESC,
 449         .nb_min = IXGBE_MIN_RING_DESC,
 450         .nb_align = IXGBE_TXD_ALIGN,
 451 };
 452
 453 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 454         .dev_configure        = ixgbe_dev_configure,
 455         .dev_start            = ixgbe_dev_start,
 456         .dev_stop             = ixgbe_dev_stop,
 457         .dev_set_link_up    = ixgbe_dev_set_link_up,
 458         .dev_set_link_down  = ixgbe_dev_set_link_down,
 459         .dev_close            = ixgbe_dev_close,
 460         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 461         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 462         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 463         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 464         .link_update          = ixgbe_dev_link_update,
 465         .stats_get            = ixgbe_dev_stats_get,
 466         .xstats_get           = ixgbe_dev_xstats_get,
 467         .stats_reset          = ixgbe_dev_stats_reset,
 468         .xstats_reset         = ixgbe_dev_xstats_reset,
 469         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 470         .dev_infos_get        = ixgbe_dev_info_get,
 471         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 472         .mtu_set              = ixgbe_dev_mtu_set,
 473         .vlan_filter_set      = ixgbe_vlan_filter_set,
 474         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 475         .vlan_offload_set     = ixgbe_vlan_offload_set,
 476         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 477         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 478         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 479         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 480         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 481         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 482         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 483         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 484         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 485         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 486         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 487         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 488         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 489         .dev_led_on           = ixgbe_dev_led_on,
 490         .dev_led_off          = ixgbe_dev_led_off,
 491         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 492         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 493         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 494         .mac_addr_add         = ixgbe_add_rar,
 495         .mac_addr_remove      = ixgbe_remove_rar,
 496         .mac_addr_set         = ixgbe_set_default_mac_addr,
 497         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 498         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 499         .mirror_rule_set      = ixgbe_mirror_rule_set,
 500         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 501         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 502         .set_vf_rx            = ixgbe_set_pool_rx,
 503         .set_vf_tx            = ixgbe_set_pool_tx,
 504         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 505         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 506         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 507         .reta_update          = ixgbe_dev_rss_reta_update,
 508         .reta_query           = ixgbe_dev_rss_reta_query,
 509 #ifdef RTE_NIC_BYPASS
 510         .bypass_init          = ixgbe_bypass_init,
 511         .bypass_state_set     = ixgbe_bypass_state_store,
 512         .bypass_state_show    = ixgbe_bypass_state_show,
 513         .bypass_event_set     = ixgbe_bypass_event_store,
 514         .bypass_event_show    = ixgbe_bypass_event_show,
 515         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 516         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 517         .bypass_ver_show      = ixgbe_bypass_ver_show,
 518         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 519 #endif /* RTE_NIC_BYPASS */
 520         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 521         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 522         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 523         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 524         .rxq_info_get         = ixgbe_rxq_info_get,
 525         .txq_info_get         = ixgbe_txq_info_get,
 526         .timesync_enable      = ixgbe_timesync_enable,
 527         .timesync_disable     = ixgbe_timesync_disable,
 528         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 529         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 530         .get_reg_length       = ixgbe_get_reg_length,
 531         .get_reg              = ixgbe_get_regs,
 532         .get_eeprom_length    = ixgbe_get_eeprom_length,
 533         .get_eeprom           = ixgbe_get_eeprom,
 534         .set_eeprom           = ixgbe_set_eeprom,
 535         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 536         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 537         .timesync_read_time   = ixgbe_timesync_read_time,
 538         .timesync_write_time  = ixgbe_timesync_write_time,
 539         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 540         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 541         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 542         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 543 };
 544
 545 /*
 546  * dev_ops for virtual function, bare necessities for basic vf
 547  * operation have been implemented
 548  */
 549 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 550         .dev_configure        = ixgbevf_dev_configure,
 551         .dev_start            = ixgbevf_dev_start,
 552         .dev_stop             = ixgbevf_dev_stop,
 553         .link_update          = ixgbe_dev_link_update,
 554         .stats_get            = ixgbevf_dev_stats_get,
 555         .xstats_get           = ixgbevf_dev_xstats_get,
 556         .stats_reset          = ixgbevf_dev_stats_reset,
 557         .xstats_reset         = ixgbevf_dev_stats_reset,
 558         .dev_close            = ixgbevf_dev_close,
 559         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 560         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 561         .dev_infos_get        = ixgbevf_dev_info_get,
 562         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 563         .mtu_set              = ixgbevf_dev_set_mtu,
 564         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 565         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 566         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 567         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 568         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 569         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 570         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 571         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 572         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 573         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 574         .mac_addr_add         = ixgbevf_add_mac_addr,
 575         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 576         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 577         .rxq_info_get         = ixgbe_rxq_info_get,
 578         .txq_info_get         = ixgbe_txq_info_get,
 579         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 580         .get_reg_length       = ixgbevf_get_reg_length,
 581         .get_reg              = ixgbevf_get_regs,
 582         .reta_update          = ixgbe_dev_rss_reta_update,
 583         .reta_query           = ixgbe_dev_rss_reta_query,
 584         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 585         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 586 };
 587
 588 /* store statistics names and its offset in stats structure */
 589 struct rte_ixgbe_xstats_name_off {
 590         char name[RTE_ETH_XSTATS_NAME_SIZE];
 591         unsigned offset;
 592 };
 593
 594 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 595         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 596         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 597         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 598         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 599         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 600         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 601         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 602         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 603         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 604         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 605         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 606         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 607         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 608         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 609         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 610                 prc1023)},
 611         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 612                 prc1522)},
 613         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 614         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 615         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 616         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 617         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 618         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 619         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 620         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 621         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 622         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 623         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 624         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 625         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 626         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 627         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 628         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 629         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 630                 ptc1023)},
 631         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 632                 ptc1522)},
 633         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 634         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 635         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 636         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 637
 638         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 639                 fdirustat_add)},
 640         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 641                 fdirustat_remove)},
 642         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 643                 fdirfstat_fadd)},
 644         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 645                 fdirfstat_fremove)},
 646         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 647                 fdirmatch)},
 648         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 649                 fdirmiss)},
 650
 651         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 652         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 653         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 654                 fclast)},
 655         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 656         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 657         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 658         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 659         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 660                 fcoe_noddp)},
 661         {"rx_fcoe_no_direct_data_placement_ext_buff",
 662                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 663
 664         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 665                 lxontxc)},
 666         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 667                 lxonrxc)},
 668         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 669                 lxofftxc)},
 670         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 671                 lxoffrxc)},
 672         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 673 };
 674
 675 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 676                            sizeof(rte_ixgbe_stats_strings[0]))
 677
 678 /* Per-queue statistics */
 679 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 680         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 681         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 682         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 683         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 684 };
 685
 686 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 687                            sizeof(rte_ixgbe_rxq_strings[0]))
 688
 689 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 690         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 691         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 692         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 693                 pxon2offc)},
 694 };
 695
 696 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 697                            sizeof(rte_ixgbe_txq_strings[0]))
 698
 699 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 700         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 701 };
 702
 703 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 704                 sizeof(rte_ixgbevf_stats_strings[0]))
 705
 706 /**
 707  * Atomically reads the link status information from global
 708  * structure rte_eth_dev.
 709  *
 710  * @param dev
 711  *   - Pointer to the structure rte_eth_dev to read from.
 712  *   - Pointer to the buffer to be saved with the link status.
 713  *
 714  * @return
 715  *   - On success, zero.
 716  *   - On failure, negative value.
 717  */
 718 static inline int
 719 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 720                                 struct rte_eth_link *link)
 721 {
 722         struct rte_eth_link *dst = link;
 723         struct rte_eth_link *src = &(dev->data->dev_link);
 724
 725         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 726                                         *(uint64_t *)src) == 0)
 727                 return -1;
 728
 729         return 0;
 730 }
 731
 732 /**
 733  * Atomically writes the link status information into global
 734  * structure rte_eth_dev.
 735  *
 736  * @param dev
 737  *   - Pointer to the structure rte_eth_dev to read from.
 738  *   - Pointer to the buffer to be saved with the link status.
 739  *
 740  * @return
 741  *   - On success, zero.
 742  *   - On failure, negative value.
 743  */
 744 static inline int
 745 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 746                                 struct rte_eth_link *link)
 747 {
 748         struct rte_eth_link *dst = &(dev->data->dev_link);
 749         struct rte_eth_link *src = link;
 750
 751         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 752                                         *(uint64_t *)src) == 0)
 753                 return -1;
 754
 755         return 0;
 756 }
 757
 758 /*
 759  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 760  */
 761 static inline int
 762 ixgbe_is_sfp(struct ixgbe_hw *hw)
 763 {
 764         switch (hw->phy.type) {
 765         case ixgbe_phy_sfp_avago:
 766         case ixgbe_phy_sfp_ftl:
 767         case ixgbe_phy_sfp_intel:
 768         case ixgbe_phy_sfp_unknown:
 769         case ixgbe_phy_sfp_passive_tyco:
 770         case ixgbe_phy_sfp_passive_unknown:
 771                 return 1;
 772         default:
 773                 return 0;
 774         }
 775 }
 776
 777 static inline int32_t
 778 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 779 {
 780         uint32_t ctrl_ext;
 781         int32_t status;
 782
 783         status = ixgbe_reset_hw(hw);
 784
 785         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 786         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 787         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 788         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 789         IXGBE_WRITE_FLUSH(hw);
 790
 791         return status;
 792 }
 793
 794 static inline void
 795 ixgbe_enable_intr(struct rte_eth_dev *dev)
 796 {
 797         struct ixgbe_interrupt *intr =
 798                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 799         struct ixgbe_hw *hw =
 800                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 801
 802         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 803         IXGBE_WRITE_FLUSH(hw);
 804 }
 805
 806 /*
 807  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 808  */
 809 static void
 810 ixgbe_disable_intr(struct ixgbe_hw *hw)
 811 {
 812         PMD_INIT_FUNC_TRACE();
 813
 814         if (hw->mac.type == ixgbe_mac_82598EB) {
 815                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 816         } else {
 817                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 818                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 819                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 820         }
 821         IXGBE_WRITE_FLUSH(hw);
 822 }
 823
 824 /*
 825  * This function resets queue statistics mapping registers.
 826  * From Niantic datasheet, Initialization of Statistics section:
 827  * "...if software requires the queue counters, the RQSMR and TQSM registers
 828  * must be re-programmed following a device reset.
 829  */
 830 static void
 831 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 832 {
 833         uint32_t i;
 834
 835         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 836                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 837                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 838         }
 839 }
 840
 841
 842 static int
 843 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 844                                   uint16_t queue_id,
 845                                   uint8_t stat_idx,
 846                                   uint8_t is_rx)
 847 {
 848 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 849 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 850 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 851
 852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 853         struct ixgbe_stat_mapping_registers *stat_mappings =
 854                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 855         uint32_t qsmr_mask = 0;
 856         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 857         uint32_t q_map;
 858         uint8_t n, offset;
 859
 860         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 861                 (hw->mac.type != ixgbe_mac_X540) &&
 862                 (hw->mac.type != ixgbe_mac_X550) &&
 863                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 864                 (hw->mac.type != ixgbe_mac_X550EM_a))
 865                 return -ENOSYS;
 866
 867         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 868                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 869                      queue_id, stat_idx);
 870
 871         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 872         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 873                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 874                 return -EIO;
 875         }
 876         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 877
 878         /* Now clear any previous stat_idx set */
 879         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 880         if (!is_rx)
 881                 stat_mappings->tqsm[n] &= ~clearing_mask;
 882         else
 883                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 884
 885         q_map = (uint32_t)stat_idx;
 886         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 887         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 888         if (!is_rx)
 889                 stat_mappings->tqsm[n] |= qsmr_mask;
 890         else
 891                 stat_mappings->rqsmr[n] |= qsmr_mask;
 892
 893         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 894                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 895                      queue_id, stat_idx);
 896         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 897                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 898
 899         /* Now write the mapping in the appropriate register */
 900         if (is_rx) {
 901                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 902                              stat_mappings->rqsmr[n], n);
 903                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 904         } else {
 905                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 906                              stat_mappings->tqsm[n], n);
 907                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 908         }
 909         return 0;
 910 }
 911
 912 static void
 913 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 914 {
 915         struct ixgbe_stat_mapping_registers *stat_mappings =
 916                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 918         int i;
 919
 920         /* write whatever was in stat mapping table to the NIC */
 921         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 922                 /* rx */
 923                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 924
 925                 /* tx */
 926                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 927         }
 928 }
 929
 930 static void
 931 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 932 {
 933         uint8_t i;
 934         struct ixgbe_dcb_tc_config *tc;
 935         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 936
 937         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 938         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 939         for (i = 0; i < dcb_max_tc; i++) {
 940                 tc = &dcb_config->tc_config[i];
 941                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 942                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 943                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 944                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 945                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 946                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 947                 tc->pfc = ixgbe_dcb_pfc_disabled;
 948         }
 949
 950         /* Initialize default user to priority mapping, UPx->TC0 */
 951         tc = &dcb_config->tc_config[0];
 952         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 953         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 954         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 955                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 956                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 957         }
 958         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 959         dcb_config->pfc_mode_enable = false;
 960         dcb_config->vt_mode = true;
 961         dcb_config->round_robin_enable = false;
 962         /* support all DCB capabilities in 82599 */
 963         dcb_config->support.capabilities = 0xFF;
 964
 965         /*we only support 4 Tcs for X540, X550 */
 966         if (hw->mac.type == ixgbe_mac_X540 ||
 967                 hw->mac.type == ixgbe_mac_X550 ||
 968                 hw->mac.type == ixgbe_mac_X550EM_x ||
 969                 hw->mac.type == ixgbe_mac_X550EM_a) {
 970                 dcb_config->num_tcs.pg_tcs = 4;
 971                 dcb_config->num_tcs.pfc_tcs = 4;
 972         }
 973 }
 974
 975 /*
 976  * Ensure that all locks are released before first NVM or PHY access
 977  */
 978 static void
 979 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 980 {
 981         uint16_t mask;
 982
 983         /*
 984          * Phy lock should not fail in this early stage. If this is the case,
 985          * it is due to an improper exit of the application.
 986          * So force the release of the faulty lock. Release of common lock
 987          * is done automatically by swfw_sync function.
 988          */
 989         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 990         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 991                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 992         }
 993         ixgbe_release_swfw_semaphore(hw, mask);
 994
 995         /*
 996          * These ones are more tricky since they are common to all ports; but
 997          * swfw_sync retries last long enough (1s) to be almost sure that if
 998          * lock can not be taken it is due to an improper lock of the
 999          * semaphore.
1000          */
1001         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1002         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1003                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1004         }
1005         ixgbe_release_swfw_semaphore(hw, mask);
1006 }
1007
1008 /*
1009  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1010  * It returns 0 on success.
1011  */
1012 static int
1013 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1014 {
1015         struct rte_pci_device *pci_dev;
1016         struct ixgbe_hw *hw =
1017                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1018         struct ixgbe_vfta *shadow_vfta =
1019                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1020         struct ixgbe_hwstrip *hwstrip =
1021                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1022         struct ixgbe_dcb_config *dcb_config =
1023                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1024         struct ixgbe_filter_info *filter_info =
1025                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1026         uint32_t ctrl_ext;
1027         uint16_t csum;
1028         int diag, i;
1029
1030         PMD_INIT_FUNC_TRACE();
1031
1032         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1033         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1034         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1035
1036         /*
1037          * For secondary processes, we don't initialise any further as primary
1038          * has already done this work. Only check we don't need a different
1039          * RX and TX function.
1040          */
1041         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1042                 struct ixgbe_tx_queue *txq;
1043                 /* TX queue function in primary, set by last queue initialized
1044                  * Tx queue may not initialized by primary process
1045                  */
1046                 if (eth_dev->data->tx_queues) {
1047                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1048                         ixgbe_set_tx_function(eth_dev, txq);
1049                 } else {
1050                         /* Use default TX function if we get here */
1051                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1052                                      "Using default TX function.");
1053                 }
1054
1055                 ixgbe_set_rx_function(eth_dev);
1056
1057                 return 0;
1058         }
1059         pci_dev = eth_dev->pci_dev;
1060
1061         rte_eth_copy_pci_info(eth_dev, pci_dev);
1062
1063         /* Vendor and Device ID need to be set before init of shared code */
1064         hw->device_id = pci_dev->id.device_id;
1065         hw->vendor_id = pci_dev->id.vendor_id;
1066         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1067         hw->allow_unsupported_sfp = 1;
1068
1069         /* Initialize the shared code (base driver) */
1070 #ifdef RTE_NIC_BYPASS
1071         diag = ixgbe_bypass_init_shared_code(hw);
1072 #else
1073         diag = ixgbe_init_shared_code(hw);
1074 #endif /* RTE_NIC_BYPASS */
1075
1076         if (diag != IXGBE_SUCCESS) {
1077                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1078                 return -EIO;
1079         }
1080
1081         /* pick up the PCI bus settings for reporting later */
1082         ixgbe_get_bus_info(hw);
1083
1084         /* Unlock any pending hardware semaphore */
1085         ixgbe_swfw_lock_reset(hw);
1086
1087         /* Initialize DCB configuration*/
1088         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1089         ixgbe_dcb_init(hw, dcb_config);
1090         /* Get Hardware Flow Control setting */
1091         hw->fc.requested_mode = ixgbe_fc_full;
1092         hw->fc.current_mode = ixgbe_fc_full;
1093         hw->fc.pause_time = IXGBE_FC_PAUSE;
1094         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1095                 hw->fc.low_water[i] = IXGBE_FC_LO;
1096                 hw->fc.high_water[i] = IXGBE_FC_HI;
1097         }
1098         hw->fc.send_xon = 1;
1099
1100         /* Make sure we have a good EEPROM before we read from it */
1101         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1102         if (diag != IXGBE_SUCCESS) {
1103                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1104                 return -EIO;
1105         }
1106
1107 #ifdef RTE_NIC_BYPASS
1108         diag = ixgbe_bypass_init_hw(hw);
1109 #else
1110         diag = ixgbe_init_hw(hw);
1111 #endif /* RTE_NIC_BYPASS */
1112
1113         /*
1114          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1115          * is called too soon after the kernel driver unbinding/binding occurs.
1116          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1117          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1118          * also called. See ixgbe_identify_phy_82599(). The reason for the
1119          * failure is not known, and only occuts when virtualisation features
1120          * are disabled in the bios. A delay of 100ms  was found to be enough by
1121          * trial-and-error, and is doubled to be safe.
1122          */
1123         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1124                 rte_delay_ms(200);
1125                 diag = ixgbe_init_hw(hw);
1126         }
1127
1128         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1129                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1130                              "LOM.  Please be aware there may be issues associated "
1131                              "with your hardware.");
1132                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1133                              "please contact your Intel or hardware representative "
1134                              "who provided you with this hardware.");
1135         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1136                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1137         if (diag) {
1138                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1139                 return -EIO;
1140         }
1141
1142         /* Reset the hw statistics */
1143         ixgbe_dev_stats_reset(eth_dev);
1144
1145         /* disable interrupt */
1146         ixgbe_disable_intr(hw);
1147
1148         /* reset mappings for queue statistics hw counters*/
1149         ixgbe_reset_qstat_mappings(hw);
1150
1151         /* Allocate memory for storing MAC addresses */
1152         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1153                                                hw->mac.num_rar_entries, 0);
1154         if (eth_dev->data->mac_addrs == NULL) {
1155                 PMD_INIT_LOG(ERR,
1156                              "Failed to allocate %u bytes needed to store "
1157                              "MAC addresses",
1158                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1159                 return -ENOMEM;
1160         }
1161         /* Copy the permanent MAC address */
1162         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1163                         &eth_dev->data->mac_addrs[0]);
1164
1165         /* Allocate memory for storing hash filter MAC addresses */
1166         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1168         if (eth_dev->data->hash_mac_addrs == NULL) {
1169                 PMD_INIT_LOG(ERR,
1170                              "Failed to allocate %d bytes needed to store MAC addresses",
1171                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1172                 return -ENOMEM;
1173         }
1174
1175         /* initialize the vfta */
1176         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1177
1178         /* initialize the hw strip bitmap*/
1179         memset(hwstrip, 0, sizeof(*hwstrip));
1180
1181         /* initialize PF if max_vfs not zero */
1182         ixgbe_pf_host_init(eth_dev);
1183
1184         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1185         /* let hardware know driver is loaded */
1186         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1187         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1188         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1189         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1190         IXGBE_WRITE_FLUSH(hw);
1191
1192         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1193                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1194                              (int) hw->mac.type, (int) hw->phy.type,
1195                              (int) hw->phy.sfp_type);
1196         else
1197                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1198                              (int) hw->mac.type, (int) hw->phy.type);
1199
1200         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1201                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1202                      pci_dev->id.device_id);
1203
1204         rte_intr_callback_register(&pci_dev->intr_handle,
1205                                    ixgbe_dev_interrupt_handler,
1206                                    (void *)eth_dev);
1207
1208         /* enable uio/vfio intr/eventfd mapping */
1209         rte_intr_enable(&pci_dev->intr_handle);
1210
1211         /* enable support intr */
1212         ixgbe_enable_intr(eth_dev);
1213
1214         /* initialize 5tuple filter list */
1215         TAILQ_INIT(&filter_info->fivetuple_list);
1216         memset(filter_info->fivetuple_mask, 0,
1217                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1218
1219         return 0;
1220 }
1221
1222 static int
1223 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1224 {
1225         struct rte_pci_device *pci_dev;
1226         struct ixgbe_hw *hw;
1227
1228         PMD_INIT_FUNC_TRACE();
1229
1230         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1231                 return -EPERM;
1232
1233         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1234         pci_dev = eth_dev->pci_dev;
1235
1236         if (hw->adapter_stopped == 0)
1237                 ixgbe_dev_close(eth_dev);
1238
1239         eth_dev->dev_ops = NULL;
1240         eth_dev->rx_pkt_burst = NULL;
1241         eth_dev->tx_pkt_burst = NULL;
1242
1243         /* Unlock any pending hardware semaphore */
1244         ixgbe_swfw_lock_reset(hw);
1245
1246         /* disable uio intr before callback unregister */
1247         rte_intr_disable(&(pci_dev->intr_handle));
1248         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1249                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1250
1251         /* uninitialize PF if max_vfs not zero */
1252         ixgbe_pf_host_uninit(eth_dev);
1253
1254         rte_free(eth_dev->data->mac_addrs);
1255         eth_dev->data->mac_addrs = NULL;
1256
1257         rte_free(eth_dev->data->hash_mac_addrs);
1258         eth_dev->data->hash_mac_addrs = NULL;
1259
1260         return 0;
1261 }
1262
1263 /*
1264  * Negotiate mailbox API version with the PF.
1265  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1266  * Then we try to negotiate starting with the most recent one.
1267  * If all negotiation attempts fail, then we will proceed with
1268  * the default one (ixgbe_mbox_api_10).
1269  */
1270 static void
1271 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1272 {
1273         int32_t i;
1274
1275         /* start with highest supported, proceed down */
1276         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1277                 ixgbe_mbox_api_12,
1278                 ixgbe_mbox_api_11,
1279                 ixgbe_mbox_api_10,
1280         };
1281
1282         for (i = 0;
1283                         i != RTE_DIM(sup_ver) &&
1284                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1285                         i++)
1286                 ;
1287 }
1288
1289 static void
1290 generate_random_mac_addr(struct ether_addr *mac_addr)
1291 {
1292         uint64_t random;
1293
1294         /* Set Organizationally Unique Identifier (OUI) prefix. */
1295         mac_addr->addr_bytes[0] = 0x00;
1296         mac_addr->addr_bytes[1] = 0x09;
1297         mac_addr->addr_bytes[2] = 0xC0;
1298         /* Force indication of locally assigned MAC address. */
1299         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1300         /* Generate the last 3 bytes of the MAC address with a random number. */
1301         random = rte_rand();
1302         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1303 }
1304
1305 /*
1306  * Virtual Function device init
1307  */
1308 static int
1309 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1310 {
1311         int diag;
1312         uint32_t tc, tcs;
1313         struct rte_pci_device *pci_dev;
1314         struct ixgbe_hw *hw =
1315                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1316         struct ixgbe_vfta *shadow_vfta =
1317                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1318         struct ixgbe_hwstrip *hwstrip =
1319                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1320         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1321
1322         PMD_INIT_FUNC_TRACE();
1323
1324         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1325         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1326         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1327
1328         /* for secondary processes, we don't initialise any further as primary
1329          * has already done this work. Only check we don't need a different
1330          * RX function
1331          */
1332         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1333                 struct ixgbe_tx_queue *txq;
1334                 /* TX queue function in primary, set by last queue initialized
1335                  * Tx queue may not initialized by primary process
1336                  */
1337                 if (eth_dev->data->tx_queues) {
1338                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1339                         ixgbe_set_tx_function(eth_dev, txq);
1340                 } else {
1341                         /* Use default TX function if we get here */
1342                         PMD_INIT_LOG(NOTICE,
1343                                      "No TX queues configured yet. Using default TX function.");
1344                 }
1345
1346                 ixgbe_set_rx_function(eth_dev);
1347
1348                 return 0;
1349         }
1350
1351         pci_dev = eth_dev->pci_dev;
1352
1353         rte_eth_copy_pci_info(eth_dev, pci_dev);
1354
1355         hw->device_id = pci_dev->id.device_id;
1356         hw->vendor_id = pci_dev->id.vendor_id;
1357         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1358
1359         /* initialize the vfta */
1360         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1361
1362         /* initialize the hw strip bitmap*/
1363         memset(hwstrip, 0, sizeof(*hwstrip));
1364
1365         /* Initialize the shared code (base driver) */
1366         diag = ixgbe_init_shared_code(hw);
1367         if (diag != IXGBE_SUCCESS) {
1368                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1369                 return -EIO;
1370         }
1371
1372         /* init_mailbox_params */
1373         hw->mbx.ops.init_params(hw);
1374
1375         /* Reset the hw statistics */
1376         ixgbevf_dev_stats_reset(eth_dev);
1377
1378         /* Disable the interrupts for VF */
1379         ixgbevf_intr_disable(hw);
1380
1381         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1382         diag = hw->mac.ops.reset_hw(hw);
1383
1384         /*
1385          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1386          * the underlying PF driver has not assigned a MAC address to the VF.
1387          * In this case, assign a random MAC address.
1388          */
1389         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1390                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1391                 return diag;
1392         }
1393
1394         /* negotiate mailbox API version to use with the PF. */
1395         ixgbevf_negotiate_api(hw);
1396
1397         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1398         ixgbevf_get_queues(hw, &tcs, &tc);
1399
1400         /* Allocate memory for storing MAC addresses */
1401         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1402                                                hw->mac.num_rar_entries, 0);
1403         if (eth_dev->data->mac_addrs == NULL) {
1404                 PMD_INIT_LOG(ERR,
1405                              "Failed to allocate %u bytes needed to store "
1406                              "MAC addresses",
1407                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1408                 return -ENOMEM;
1409         }
1410
1411         /* Generate a random MAC address, if none was assigned by PF. */
1412         if (is_zero_ether_addr(perm_addr)) {
1413                 generate_random_mac_addr(perm_addr);
1414                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1415                 if (diag) {
1416                         rte_free(eth_dev->data->mac_addrs);
1417                         eth_dev->data->mac_addrs = NULL;
1418                         return diag;
1419                 }
1420                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1421                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1422                              "%02x:%02x:%02x:%02x:%02x:%02x",
1423                              perm_addr->addr_bytes[0],
1424                              perm_addr->addr_bytes[1],
1425                              perm_addr->addr_bytes[2],
1426                              perm_addr->addr_bytes[3],
1427                              perm_addr->addr_bytes[4],
1428                              perm_addr->addr_bytes[5]);
1429         }
1430
1431         /* Copy the permanent MAC address */
1432         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1433
1434         /* reset the hardware with the new settings */
1435         diag = hw->mac.ops.start_hw(hw);
1436         switch (diag) {
1437         case  0:
1438                 break;
1439
1440         default:
1441                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1442                 return -EIO;
1443         }
1444
1445         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1446                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1447                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1448
1449         return 0;
1450 }
1451
1452 /* Virtual Function device uninit */
1453
1454 static int
1455 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1456 {
1457         struct ixgbe_hw *hw;
1458
1459         PMD_INIT_FUNC_TRACE();
1460
1461         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1462                 return -EPERM;
1463
1464         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1465
1466         if (hw->adapter_stopped == 0)
1467                 ixgbevf_dev_close(eth_dev);
1468
1469         eth_dev->dev_ops = NULL;
1470         eth_dev->rx_pkt_burst = NULL;
1471         eth_dev->tx_pkt_burst = NULL;
1472
1473         /* Disable the interrupts for VF */
1474         ixgbevf_intr_disable(hw);
1475
1476         rte_free(eth_dev->data->mac_addrs);
1477         eth_dev->data->mac_addrs = NULL;
1478
1479         return 0;
1480 }
1481
1482 static struct eth_driver rte_ixgbe_pmd = {
1483         .pci_drv = {
1484                 .name = "rte_ixgbe_pmd",
1485                 .id_table = pci_id_ixgbe_map,
1486                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1487                         RTE_PCI_DRV_DETACHABLE,
1488         },
1489         .eth_dev_init = eth_ixgbe_dev_init,
1490         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1491         .dev_private_size = sizeof(struct ixgbe_adapter),
1492 };
1493
1494 /*
1495  * virtual function driver struct
1496  */
1497 static struct eth_driver rte_ixgbevf_pmd = {
1498         .pci_drv = {
1499                 .name = "rte_ixgbevf_pmd",
1500                 .id_table = pci_id_ixgbevf_map,
1501                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1502         },
1503         .eth_dev_init = eth_ixgbevf_dev_init,
1504         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1505         .dev_private_size = sizeof(struct ixgbe_adapter),
1506 };
1507
1508 /*
1509  * Driver initialization routine.
1510  * Invoked once at EAL init time.
1511  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1512  */
1513 static int
1514 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1515 {
1516         PMD_INIT_FUNC_TRACE();
1517
1518         rte_eth_driver_register(&rte_ixgbe_pmd);
1519         return 0;
1520 }
1521
1522 /*
1523  * VF Driver initialization routine.
1524  * Invoked one at EAL init time.
1525  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1526  */
1527 static int
1528 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1529 {
1530         PMD_INIT_FUNC_TRACE();
1531
1532         rte_eth_driver_register(&rte_ixgbevf_pmd);
1533         return 0;
1534 }
1535
1536 static int
1537 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1538 {
1539         struct ixgbe_hw *hw =
1540                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1541         struct ixgbe_vfta *shadow_vfta =
1542                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1543         uint32_t vfta;
1544         uint32_t vid_idx;
1545         uint32_t vid_bit;
1546
1547         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1548         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1549         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1550         if (on)
1551                 vfta |= vid_bit;
1552         else
1553                 vfta &= ~vid_bit;
1554         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1555
1556         /* update local VFTA copy */
1557         shadow_vfta->vfta[vid_idx] = vfta;
1558
1559         return 0;
1560 }
1561
1562 static void
1563 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1564 {
1565         if (on)
1566                 ixgbe_vlan_hw_strip_enable(dev, queue);
1567         else
1568                 ixgbe_vlan_hw_strip_disable(dev, queue);
1569 }
1570
1571 static int
1572 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1573                     enum rte_vlan_type vlan_type,
1574                     uint16_t tpid)
1575 {
1576         struct ixgbe_hw *hw =
1577                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578         int ret = 0;
1579
1580         switch (vlan_type) {
1581         case ETH_VLAN_TYPE_INNER:
1582                 /* Only the high 16-bits is valid */
1583                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1584                 break;
1585         default:
1586                 ret = -EINVAL;
1587                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1588                 break;
1589         }
1590
1591         return ret;
1592 }
1593
1594 void
1595 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1596 {
1597         struct ixgbe_hw *hw =
1598                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599         uint32_t vlnctrl;
1600
1601         PMD_INIT_FUNC_TRACE();
1602
1603         /* Filter Table Disable */
1604         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1605         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1606
1607         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1608 }
1609
1610 void
1611 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1612 {
1613         struct ixgbe_hw *hw =
1614                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1615         struct ixgbe_vfta *shadow_vfta =
1616                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1617         uint32_t vlnctrl;
1618         uint16_t i;
1619
1620         PMD_INIT_FUNC_TRACE();
1621
1622         /* Filter Table Enable */
1623         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1624         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1625         vlnctrl |= IXGBE_VLNCTRL_VFE;
1626
1627         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1628
1629         /* write whatever is in local vfta copy */
1630         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1631                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1632 }
1633
1634 static void
1635 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1636 {
1637         struct ixgbe_hwstrip *hwstrip =
1638                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1639
1640         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1641                 return;
1642
1643         if (on)
1644                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1645         else
1646                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1647 }
1648
1649 static void
1650 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1651 {
1652         struct ixgbe_hw *hw =
1653                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         uint32_t ctrl;
1655
1656         PMD_INIT_FUNC_TRACE();
1657
1658         if (hw->mac.type == ixgbe_mac_82598EB) {
1659                 /* No queue level support */
1660                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1661                 return;
1662         }
1663
1664         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1665         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1666         ctrl &= ~IXGBE_RXDCTL_VME;
1667         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1668
1669         /* record those setting for HW strip per queue */
1670         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1671 }
1672
1673 static void
1674 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1675 {
1676         struct ixgbe_hw *hw =
1677                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1678         uint32_t ctrl;
1679
1680         PMD_INIT_FUNC_TRACE();
1681
1682         if (hw->mac.type == ixgbe_mac_82598EB) {
1683                 /* No queue level supported */
1684                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1685                 return;
1686         }
1687
1688         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1689         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1690         ctrl |= IXGBE_RXDCTL_VME;
1691         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1692
1693         /* record those setting for HW strip per queue */
1694         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1695 }
1696
1697 void
1698 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1699 {
1700         struct ixgbe_hw *hw =
1701                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1702         uint32_t ctrl;
1703         uint16_t i;
1704
1705         PMD_INIT_FUNC_TRACE();
1706
1707         if (hw->mac.type == ixgbe_mac_82598EB) {
1708                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1709                 ctrl &= ~IXGBE_VLNCTRL_VME;
1710                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1711         } else {
1712                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1713                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1714                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1715                         ctrl &= ~IXGBE_RXDCTL_VME;
1716                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1717
1718                         /* record those setting for HW strip per queue */
1719                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1720                 }
1721         }
1722 }
1723
1724 void
1725 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1726 {
1727         struct ixgbe_hw *hw =
1728                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729         uint32_t ctrl;
1730         uint16_t i;
1731
1732         PMD_INIT_FUNC_TRACE();
1733
1734         if (hw->mac.type == ixgbe_mac_82598EB) {
1735                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1736                 ctrl |= IXGBE_VLNCTRL_VME;
1737                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1738         } else {
1739                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1740                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1741                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1742                         ctrl |= IXGBE_RXDCTL_VME;
1743                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1744
1745                         /* record those setting for HW strip per queue */
1746                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1747                 }
1748         }
1749 }
1750
1751 static void
1752 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1753 {
1754         struct ixgbe_hw *hw =
1755                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1756         uint32_t ctrl;
1757
1758         PMD_INIT_FUNC_TRACE();
1759
1760         /* DMATXCTRL: Geric Double VLAN Disable */
1761         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1762         ctrl &= ~IXGBE_DMATXCTL_GDV;
1763         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1764
1765         /* CTRL_EXT: Global Double VLAN Disable */
1766         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1767         ctrl &= ~IXGBE_EXTENDED_VLAN;
1768         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1769
1770 }
1771
1772 static void
1773 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1774 {
1775         struct ixgbe_hw *hw =
1776                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1777         uint32_t ctrl;
1778
1779         PMD_INIT_FUNC_TRACE();
1780
1781         /* DMATXCTRL: Geric Double VLAN Enable */
1782         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1783         ctrl |= IXGBE_DMATXCTL_GDV;
1784         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1785
1786         /* CTRL_EXT: Global Double VLAN Enable */
1787         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1788         ctrl |= IXGBE_EXTENDED_VLAN;
1789         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1790
1791         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1792         if (hw->mac.type == ixgbe_mac_X550 ||
1793             hw->mac.type == ixgbe_mac_X550EM_x ||
1794             hw->mac.type == ixgbe_mac_X550EM_a) {
1795                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1796                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1797                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1798         }
1799
1800         /*
1801          * VET EXT field in the EXVET register = 0x8100 by default
1802          * So no need to change. Same to VT field of DMATXCTL register
1803          */
1804 }
1805
1806 static void
1807 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1808 {
1809         if (mask & ETH_VLAN_STRIP_MASK) {
1810                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1811                         ixgbe_vlan_hw_strip_enable_all(dev);
1812                 else
1813                         ixgbe_vlan_hw_strip_disable_all(dev);
1814         }
1815
1816         if (mask & ETH_VLAN_FILTER_MASK) {
1817                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1818                         ixgbe_vlan_hw_filter_enable(dev);
1819                 else
1820                         ixgbe_vlan_hw_filter_disable(dev);
1821         }
1822
1823         if (mask & ETH_VLAN_EXTEND_MASK) {
1824                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1825                         ixgbe_vlan_hw_extend_enable(dev);
1826                 else
1827                         ixgbe_vlan_hw_extend_disable(dev);
1828         }
1829 }
1830
1831 static void
1832 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1833 {
1834         struct ixgbe_hw *hw =
1835                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1837         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1838
1839         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1840         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1841 }
1842
1843 static int
1844 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1845 {
1846         switch (nb_rx_q) {
1847         case 1:
1848         case 2:
1849                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1850                 break;
1851         case 4:
1852                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1853                 break;
1854         default:
1855                 return -EINVAL;
1856         }
1857
1858         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1859         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1860
1861         return 0;
1862 }
1863
1864 static int
1865 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1866 {
1867         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1870         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1871
1872         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1873                 /* check multi-queue mode */
1874                 switch (dev_conf->rxmode.mq_mode) {
1875                 case ETH_MQ_RX_VMDQ_DCB:
1876                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1877                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1878                         PMD_INIT_LOG(ERR, "SRIOV active,"
1879                                         " unsupported mq_mode rx %d.",
1880                                         dev_conf->rxmode.mq_mode);
1881                         return -EINVAL;
1882                 case ETH_MQ_RX_RSS:
1883                 case ETH_MQ_RX_VMDQ_RSS:
1884                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1885                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1886                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1887                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1888                                                 " invalid queue number"
1889                                                 " for VMDQ RSS, allowed"
1890                                                 " value are 1, 2 or 4.");
1891                                         return -EINVAL;
1892                                 }
1893                         break;
1894                 case ETH_MQ_RX_VMDQ_ONLY:
1895                 case ETH_MQ_RX_NONE:
1896                         /* if nothing mq mode configure, use default scheme */
1897                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1898                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1899                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1900                         break;
1901                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1902                         /* SRIOV only works in VMDq enable mode */
1903                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1904                                         " wrong mq_mode rx %d.",
1905                                         dev_conf->rxmode.mq_mode);
1906                         return -EINVAL;
1907                 }
1908
1909                 switch (dev_conf->txmode.mq_mode) {
1910                 case ETH_MQ_TX_VMDQ_DCB:
1911                         /* DCB VMDQ in SRIOV mode, not implement yet */
1912                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1913                                         " unsupported VMDQ mq_mode tx %d.",
1914                                         dev_conf->txmode.mq_mode);
1915                         return -EINVAL;
1916                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1917                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1918                         break;
1919                 }
1920
1921                 /* check valid queue number */
1922                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1923                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1924                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1925                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1926                                         " must be less than or equal to %d.",
1927                                         nb_rx_q, nb_tx_q,
1928                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1929                         return -EINVAL;
1930                 }
1931         } else {
1932                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1933                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1934                                           " not supported.");
1935                         return -EINVAL;
1936                 }
1937                 /* check configuration for vmdb+dcb mode */
1938                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1939                         const struct rte_eth_vmdq_dcb_conf *conf;
1940
1941                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1942                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1943                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1944                                 return -EINVAL;
1945                         }
1946                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1947                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1948                                conf->nb_queue_pools == ETH_32_POOLS)) {
1949                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1950                                                 " nb_queue_pools must be %d or %d.",
1951                                                 ETH_16_POOLS, ETH_32_POOLS);
1952                                 return -EINVAL;
1953                         }
1954                 }
1955                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1956                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1957
1958                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1959                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1960                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1961                                 return -EINVAL;
1962                         }
1963                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1964                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1965                                conf->nb_queue_pools == ETH_32_POOLS)) {
1966                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1967                                                 " nb_queue_pools != %d and"
1968                                                 " nb_queue_pools != %d.",
1969                                                 ETH_16_POOLS, ETH_32_POOLS);
1970                                 return -EINVAL;
1971                         }
1972                 }
1973
1974                 /* For DCB mode check our configuration before we go further */
1975                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1976                         const struct rte_eth_dcb_rx_conf *conf;
1977
1978                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1979                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1980                                                  IXGBE_DCB_NB_QUEUES);
1981                                 return -EINVAL;
1982                         }
1983                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1984                         if (!(conf->nb_tcs == ETH_4_TCS ||
1985                                conf->nb_tcs == ETH_8_TCS)) {
1986                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1987                                                 " and nb_tcs != %d.",
1988                                                 ETH_4_TCS, ETH_8_TCS);
1989                                 return -EINVAL;
1990                         }
1991                 }
1992
1993                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1994                         const struct rte_eth_dcb_tx_conf *conf;
1995
1996                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1997                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1998                                                  IXGBE_DCB_NB_QUEUES);
1999                                 return -EINVAL;
2000                         }
2001                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2002                         if (!(conf->nb_tcs == ETH_4_TCS ||
2003                                conf->nb_tcs == ETH_8_TCS)) {
2004                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2005                                                 " and nb_tcs != %d.",
2006                                                 ETH_4_TCS, ETH_8_TCS);
2007                                 return -EINVAL;
2008                         }
2009                 }
2010
2011                 /*
2012                  * When DCB/VT is off, maximum number of queues changes,
2013                  * except for 82598EB, which remains constant.
2014                  */
2015                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2016                                 hw->mac.type != ixgbe_mac_82598EB) {
2017                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2018                                 PMD_INIT_LOG(ERR,
2019                                              "Neither VT nor DCB are enabled, "
2020                                              "nb_tx_q > %d.",
2021                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2022                                 return -EINVAL;
2023                         }
2024                 }
2025         }
2026         return 0;
2027 }
2028
2029 static int
2030 ixgbe_dev_configure(struct rte_eth_dev *dev)
2031 {
2032         struct ixgbe_interrupt *intr =
2033                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2034         struct ixgbe_adapter *adapter =
2035                 (struct ixgbe_adapter *)dev->data->dev_private;
2036         int ret;
2037
2038         PMD_INIT_FUNC_TRACE();
2039         /* multipe queue mode checking */
2040         ret  = ixgbe_check_mq_mode(dev);
2041         if (ret != 0) {
2042                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2043                             ret);
2044                 return ret;
2045         }
2046
2047         /* set flag to update link status after init */
2048         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2049
2050         /*
2051          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2052          * allocation or vector Rx preconditions we will reset it.
2053          */
2054         adapter->rx_bulk_alloc_allowed = true;
2055         adapter->rx_vec_allowed = true;
2056
2057         return 0;
2058 }
2059
2060 static void
2061 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2062 {
2063         struct ixgbe_hw *hw =
2064                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         struct ixgbe_interrupt *intr =
2066                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2067         uint32_t gpie;
2068
2069         /* only set up it on X550EM_X */
2070         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2071                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2072                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2073                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2074                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2075                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2076         }
2077 }
2078
2079 /*
2080  * Configure device link speed and setup link.
2081  * It returns 0 on success.
2082  */
2083 static int
2084 ixgbe_dev_start(struct rte_eth_dev *dev)
2085 {
2086         struct ixgbe_hw *hw =
2087                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088         struct ixgbe_vf_info *vfinfo =
2089                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2090         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2091         uint32_t intr_vector = 0;
2092         int err, link_up = 0, negotiate = 0;
2093         uint32_t speed = 0;
2094         int mask = 0;
2095         int status;
2096         uint16_t vf, idx;
2097         uint32_t *link_speeds;
2098
2099         PMD_INIT_FUNC_TRACE();
2100
2101         /* IXGBE devices don't support:
2102         *    - half duplex (checked afterwards for valid speeds)
2103         *    - fixed speed: TODO implement
2104         */
2105         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2106                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2107                              dev->data->port_id);
2108                 return -EINVAL;
2109         }
2110
2111         /* disable uio/vfio intr/eventfd mapping */
2112         rte_intr_disable(intr_handle);
2113
2114         /* stop adapter */
2115         hw->adapter_stopped = 0;
2116         ixgbe_stop_adapter(hw);
2117
2118         /* reinitialize adapter
2119          * this calls reset and start
2120          */
2121         status = ixgbe_pf_reset_hw(hw);
2122         if (status != 0)
2123                 return -1;
2124         hw->mac.ops.start_hw(hw);
2125         hw->mac.get_link_status = true;
2126
2127         /* configure PF module if SRIOV enabled */
2128         ixgbe_pf_host_configure(dev);
2129
2130         ixgbe_dev_phy_intr_setup(dev);
2131
2132         /* check and configure queue intr-vector mapping */
2133         if ((rte_intr_cap_multiple(intr_handle) ||
2134              !RTE_ETH_DEV_SRIOV(dev).active) &&
2135             dev->data->dev_conf.intr_conf.rxq != 0) {
2136                 intr_vector = dev->data->nb_rx_queues;
2137                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2138                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2139                                         IXGBE_MAX_INTR_QUEUE_NUM);
2140                         return -ENOTSUP;
2141                 }
2142                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2143                         return -1;
2144         }
2145
2146         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2147                 intr_handle->intr_vec =
2148                         rte_zmalloc("intr_vec",
2149                                     dev->data->nb_rx_queues * sizeof(int), 0);
2150                 if (intr_handle->intr_vec == NULL) {
2151                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2152                                      " intr_vec\n", dev->data->nb_rx_queues);
2153                         return -ENOMEM;
2154                 }
2155         }
2156
2157         /* confiugre msix for sleep until rx interrupt */
2158         ixgbe_configure_msix(dev);
2159
2160         /* initialize transmission unit */
2161         ixgbe_dev_tx_init(dev);
2162
2163         /* This can fail when allocating mbufs for descriptor rings */
2164         err = ixgbe_dev_rx_init(dev);
2165         if (err) {
2166                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2167                 goto error;
2168         }
2169
2170         err = ixgbe_dev_rxtx_start(dev);
2171         if (err < 0) {
2172                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2173                 goto error;
2174         }
2175
2176         /* Skip link setup if loopback mode is enabled for 82599. */
2177         if (hw->mac.type == ixgbe_mac_82599EB &&
2178                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2179                 goto skip_link_setup;
2180
2181         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2182                 err = hw->mac.ops.setup_sfp(hw);
2183                 if (err)
2184                         goto error;
2185         }
2186
2187         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2188                 /* Turn on the copper */
2189                 ixgbe_set_phy_power(hw, true);
2190         } else {
2191                 /* Turn on the laser */
2192                 ixgbe_enable_tx_laser(hw);
2193         }
2194
2195         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2196         if (err)
2197                 goto error;
2198         dev->data->dev_link.link_status = link_up;
2199
2200         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2201         if (err)
2202                 goto error;
2203
2204         link_speeds = &dev->data->dev_conf.link_speeds;
2205         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2206                         ETH_LINK_SPEED_10G)) {
2207                 PMD_INIT_LOG(ERR, "Invalid link setting");
2208                 goto error;
2209         }
2210
2211         speed = 0x0;
2212         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2213                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2214                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2215                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2216         } else {
2217                 if (*link_speeds & ETH_LINK_SPEED_10G)
2218                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2219                 if (*link_speeds & ETH_LINK_SPEED_1G)
2220                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2221                 if (*link_speeds & ETH_LINK_SPEED_100M)
2222                         speed |= IXGBE_LINK_SPEED_100_FULL;
2223         }
2224
2225         err = ixgbe_setup_link(hw, speed, link_up);
2226         if (err)
2227                 goto error;
2228
2229 skip_link_setup:
2230
2231         if (rte_intr_allow_others(intr_handle)) {
2232                 /* check if lsc interrupt is enabled */
2233                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2234                         ixgbe_dev_lsc_interrupt_setup(dev);
2235         } else {
2236                 rte_intr_callback_unregister(intr_handle,
2237                                              ixgbe_dev_interrupt_handler,
2238                                              (void *)dev);
2239                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2240                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2241                                      " no intr multiplex\n");
2242         }
2243
2244         /* check if rxq interrupt is enabled */
2245         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2246             rte_intr_dp_is_en(intr_handle))
2247                 ixgbe_dev_rxq_interrupt_setup(dev);
2248
2249         /* enable uio/vfio intr/eventfd mapping */
2250         rte_intr_enable(intr_handle);
2251
2252         /* resume enabled intr since hw reset */
2253         ixgbe_enable_intr(dev);
2254
2255         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2256                 ETH_VLAN_EXTEND_MASK;
2257         ixgbe_vlan_offload_set(dev, mask);
2258
2259         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2260                 /* Enable vlan filtering for VMDq */
2261                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2262         }
2263
2264         /* Configure DCB hw */
2265         ixgbe_configure_dcb(dev);
2266
2267         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2268                 err = ixgbe_fdir_configure(dev);
2269                 if (err)
2270                         goto error;
2271         }
2272
2273         /* Restore vf rate limit */
2274         if (vfinfo != NULL) {
2275                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2276                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2277                                 if (vfinfo[vf].tx_rate[idx] != 0)
2278                                         ixgbe_set_vf_rate_limit(dev, vf,
2279                                                 vfinfo[vf].tx_rate[idx],
2280                                                 1 << idx);
2281         }
2282
2283         ixgbe_restore_statistics_mapping(dev);
2284
2285         return 0;
2286
2287 error:
2288         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2289         ixgbe_dev_clear_queues(dev);
2290         return -EIO;
2291 }
2292
2293 /*
2294  * Stop device: disable rx and tx functions to allow for reconfiguring.
2295  */
2296 static void
2297 ixgbe_dev_stop(struct rte_eth_dev *dev)
2298 {
2299         struct rte_eth_link link;
2300         struct ixgbe_hw *hw =
2301                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302         struct ixgbe_vf_info *vfinfo =
2303                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2304         struct ixgbe_filter_info *filter_info =
2305                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2306         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2307         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2308         int vf;
2309
2310         PMD_INIT_FUNC_TRACE();
2311
2312         /* disable interrupts */
2313         ixgbe_disable_intr(hw);
2314
2315         /* reset the NIC */
2316         ixgbe_pf_reset_hw(hw);
2317         hw->adapter_stopped = 0;
2318
2319         /* stop adapter */
2320         ixgbe_stop_adapter(hw);
2321
2322         for (vf = 0; vfinfo != NULL &&
2323                      vf < dev->pci_dev->max_vfs; vf++)
2324                 vfinfo[vf].clear_to_send = false;
2325
2326         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2327                 /* Turn off the copper */
2328                 ixgbe_set_phy_power(hw, false);
2329         } else {
2330                 /* Turn off the laser */
2331                 ixgbe_disable_tx_laser(hw);
2332         }
2333
2334         ixgbe_dev_clear_queues(dev);
2335
2336         /* Clear stored conf */
2337         dev->data->scattered_rx = 0;
2338         dev->data->lro = 0;
2339
2340         /* Clear recorded link status */
2341         memset(&link, 0, sizeof(link));
2342         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2343
2344         /* Remove all ntuple filters of the device */
2345         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2346              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2347                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2348                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2349                              p_5tuple, entries);
2350                 rte_free(p_5tuple);
2351         }
2352         memset(filter_info->fivetuple_mask, 0,
2353                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2354
2355         if (!rte_intr_allow_others(intr_handle))
2356                 /* resume to the default handler */
2357                 rte_intr_callback_register(intr_handle,
2358                                            ixgbe_dev_interrupt_handler,
2359                                            (void *)dev);
2360
2361         /* Clean datapath event and queue/vec mapping */
2362         rte_intr_efd_disable(intr_handle);
2363         if (intr_handle->intr_vec != NULL) {
2364                 rte_free(intr_handle->intr_vec);
2365                 intr_handle->intr_vec = NULL;
2366         }
2367 }
2368
2369 /*
2370  * Set device link up: enable tx.
2371  */
2372 static int
2373 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2374 {
2375         struct ixgbe_hw *hw =
2376                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2377         if (hw->mac.type == ixgbe_mac_82599EB) {
2378 #ifdef RTE_NIC_BYPASS
2379                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2380                         /* Not suported in bypass mode */
2381                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2382                                      "by device id 0x%x", hw->device_id);
2383                         return -ENOTSUP;
2384                 }
2385 #endif
2386         }
2387
2388         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2389                 /* Turn on the copper */
2390                 ixgbe_set_phy_power(hw, true);
2391         } else {
2392                 /* Turn on the laser */
2393                 ixgbe_enable_tx_laser(hw);
2394         }
2395
2396         return 0;
2397 }
2398
2399 /*
2400  * Set device link down: disable tx.
2401  */
2402 static int
2403 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2404 {
2405         struct ixgbe_hw *hw =
2406                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2407         if (hw->mac.type == ixgbe_mac_82599EB) {
2408 #ifdef RTE_NIC_BYPASS
2409                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2410                         /* Not suported in bypass mode */
2411                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2412                                      "by device id 0x%x", hw->device_id);
2413                         return -ENOTSUP;
2414                 }
2415 #endif
2416         }
2417
2418         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2419                 /* Turn off the copper */
2420                 ixgbe_set_phy_power(hw, false);
2421         } else {
2422                 /* Turn off the laser */
2423                 ixgbe_disable_tx_laser(hw);
2424         }
2425
2426         return 0;
2427 }
2428
2429 /*
2430  * Reest and stop device.
2431  */
2432 static void
2433 ixgbe_dev_close(struct rte_eth_dev *dev)
2434 {
2435         struct ixgbe_hw *hw =
2436                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2437
2438         PMD_INIT_FUNC_TRACE();
2439
2440         ixgbe_pf_reset_hw(hw);
2441
2442         ixgbe_dev_stop(dev);
2443         hw->adapter_stopped = 1;
2444
2445         ixgbe_dev_free_queues(dev);
2446
2447         ixgbe_disable_pcie_master(hw);
2448
2449         /* reprogram the RAR[0] in case user changed it. */
2450         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2451 }
2452
2453 static void
2454 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2455                            struct ixgbe_hw_stats *hw_stats,
2456                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2457                            uint64_t *total_qprc, uint64_t *total_qprdc)
2458 {
2459         uint32_t bprc, lxon, lxoff, total;
2460         uint32_t delta_gprc = 0;
2461         unsigned i;
2462         /* Workaround for RX byte count not including CRC bytes when CRC
2463 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2464          * is disabled.
2465 +        */
2466         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2467                         IXGBE_HLREG0_RXCRCSTRP);
2468
2469         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2470         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2471         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2472         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2473
2474         for (i = 0; i < 8; i++) {
2475                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2476
2477                 /* global total per queue */
2478                 hw_stats->mpc[i] += mp;
2479                 /* Running comprehensive total for stats display */
2480                 *total_missed_rx += hw_stats->mpc[i];
2481                 if (hw->mac.type == ixgbe_mac_82598EB) {
2482                         hw_stats->rnbc[i] +=
2483                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2484                         hw_stats->pxonrxc[i] +=
2485                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2486                         hw_stats->pxoffrxc[i] +=
2487                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2488                 } else {
2489                         hw_stats->pxonrxc[i] +=
2490                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2491                         hw_stats->pxoffrxc[i] +=
2492                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2493                         hw_stats->pxon2offc[i] +=
2494                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2495                 }
2496                 hw_stats->pxontxc[i] +=
2497                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2498                 hw_stats->pxofftxc[i] +=
2499                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2500         }
2501         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2502                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2503                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2504                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2505
2506                 delta_gprc += delta_qprc;
2507
2508                 hw_stats->qprc[i] += delta_qprc;
2509                 hw_stats->qptc[i] += delta_qptc;
2510
2511                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2512                 hw_stats->qbrc[i] +=
2513                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2514                 if (crc_strip == 0)
2515                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2516
2517                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2518                 hw_stats->qbtc[i] +=
2519                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2520
2521                 hw_stats->qprdc[i] += delta_qprdc;
2522                 *total_qprdc += hw_stats->qprdc[i];
2523
2524                 *total_qprc += hw_stats->qprc[i];
2525                 *total_qbrc += hw_stats->qbrc[i];
2526         }
2527         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2528         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2529         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2530
2531         /*
2532          * An errata states that gprc actually counts good + missed packets:
2533          * Workaround to set gprc to summated queue packet receives
2534          */
2535         hw_stats->gprc = *total_qprc;
2536
2537         if (hw->mac.type != ixgbe_mac_82598EB) {
2538                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2539                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2540                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2541                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2542                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2543                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2544                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2545                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2546         } else {
2547                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2548                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2549                 /* 82598 only has a counter in the high register */
2550                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2551                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2552                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2553         }
2554         uint64_t old_tpr = hw_stats->tpr;
2555
2556         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2557         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2558
2559         if (crc_strip == 0)
2560                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2561
2562         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2563         hw_stats->gptc += delta_gptc;
2564         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2565         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2566
2567         /*
2568          * Workaround: mprc hardware is incorrectly counting
2569          * broadcasts, so for now we subtract those.
2570          */
2571         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2572         hw_stats->bprc += bprc;
2573         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2574         if (hw->mac.type == ixgbe_mac_82598EB)
2575                 hw_stats->mprc -= bprc;
2576
2577         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2578         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2579         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2580         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2581         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2582         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2583
2584         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2585         hw_stats->lxontxc += lxon;
2586         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2587         hw_stats->lxofftxc += lxoff;
2588         total = lxon + lxoff;
2589
2590         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2591         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2592         hw_stats->gptc -= total;
2593         hw_stats->mptc -= total;
2594         hw_stats->ptc64 -= total;
2595         hw_stats->gotc -= total * ETHER_MIN_LEN;
2596
2597         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2598         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2599         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2600         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2601         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2602         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2603         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2604         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2605         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2606         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2607         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2608         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2609         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2610         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2611         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2612         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2613         /* Only read FCOE on 82599 */
2614         if (hw->mac.type != ixgbe_mac_82598EB) {
2615                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2616                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2617                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2618                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2619                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2620         }
2621
2622         /* Flow Director Stats registers */
2623         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2624         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2625 }
2626
2627 /*
2628  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2629  */
2630 static void
2631 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2632 {
2633         struct ixgbe_hw *hw =
2634                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2635         struct ixgbe_hw_stats *hw_stats =
2636                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2637         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2638         unsigned i;
2639
2640         total_missed_rx = 0;
2641         total_qbrc = 0;
2642         total_qprc = 0;
2643         total_qprdc = 0;
2644
2645         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2646                         &total_qprc, &total_qprdc);
2647
2648         if (stats == NULL)
2649                 return;
2650
2651         /* Fill out the rte_eth_stats statistics structure */
2652         stats->ipackets = total_qprc;
2653         stats->ibytes = total_qbrc;
2654         stats->opackets = hw_stats->gptc;
2655         stats->obytes = hw_stats->gotc;
2656
2657         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2658                 stats->q_ipackets[i] = hw_stats->qprc[i];
2659                 stats->q_opackets[i] = hw_stats->qptc[i];
2660                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2661                 stats->q_obytes[i] = hw_stats->qbtc[i];
2662                 stats->q_errors[i] = hw_stats->qprdc[i];
2663         }
2664
2665         /* Rx Errors */
2666         stats->imissed  = total_missed_rx;
2667         stats->ierrors  = hw_stats->crcerrs +
2668                           hw_stats->mspdc +
2669                           hw_stats->rlec +
2670                           hw_stats->ruc +
2671                           hw_stats->roc +
2672                           hw_stats->illerrc +
2673                           hw_stats->errbc +
2674                           hw_stats->rfc +
2675                           hw_stats->fccrc +
2676                           hw_stats->fclast;
2677
2678         /* Tx Errors */
2679         stats->oerrors  = 0;
2680 }
2681
2682 static void
2683 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2684 {
2685         struct ixgbe_hw_stats *stats =
2686                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2687
2688         /* HW registers are cleared on read */
2689         ixgbe_dev_stats_get(dev, NULL);
2690
2691         /* Reset software totals */
2692         memset(stats, 0, sizeof(*stats));
2693 }
2694
2695 /* This function calculates the number of xstats based on the current config */
2696 static unsigned
2697 ixgbe_xstats_calc_num(void) {
2698         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2699                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2700 }
2701
2702 static int
2703 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2704                                          unsigned n)
2705 {
2706         struct ixgbe_hw *hw =
2707                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2708         struct ixgbe_hw_stats *hw_stats =
2709                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2710         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2711         unsigned i, stat, count = 0;
2712
2713         count = ixgbe_xstats_calc_num();
2714
2715         if (n < count)
2716                 return count;
2717
2718         total_missed_rx = 0;
2719         total_qbrc = 0;
2720         total_qprc = 0;
2721         total_qprdc = 0;
2722
2723         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2724                                    &total_qprc, &total_qprdc);
2725
2726         /* If this is a reset xstats is NULL, and we have cleared the
2727          * registers by reading them.
2728          */
2729         if (!xstats)
2730                 return 0;
2731
2732         /* Extended stats from ixgbe_hw_stats */
2733         count = 0;
2734         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2735                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2736                          rte_ixgbe_stats_strings[i].name);
2737                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2738                                 rte_ixgbe_stats_strings[i].offset);
2739                 count++;
2740         }
2741
2742         /* RX Priority Stats */
2743         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2744                 for (i = 0; i < 8; i++) {
2745                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2746                                  "rx_priority%u_%s", i,
2747                                  rte_ixgbe_rxq_strings[stat].name);
2748                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2749                                         rte_ixgbe_rxq_strings[stat].offset +
2750                                         (sizeof(uint64_t) * i));
2751                         count++;
2752                 }
2753         }
2754
2755         /* TX Priority Stats */
2756         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2757                 for (i = 0; i < 8; i++) {
2758                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2759                                  "tx_priority%u_%s", i,
2760                                  rte_ixgbe_txq_strings[stat].name);
2761                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2762                                         rte_ixgbe_txq_strings[stat].offset +
2763                                         (sizeof(uint64_t) * i));
2764                         count++;
2765                 }
2766         }
2767
2768         return count;
2769 }
2770
2771 static void
2772 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2773 {
2774         struct ixgbe_hw_stats *stats =
2775                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2776
2777         unsigned count = ixgbe_xstats_calc_num();
2778
2779         /* HW registers are cleared on read */
2780         ixgbe_dev_xstats_get(dev, NULL, count);
2781
2782         /* Reset software totals */
2783         memset(stats, 0, sizeof(*stats));
2784 }
2785
2786 static void
2787 ixgbevf_update_stats(struct rte_eth_dev *dev)
2788 {
2789         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2790         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2791                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2792
2793         /* Good Rx packet, include VF loopback */
2794         UPDATE_VF_STAT(IXGBE_VFGPRC,
2795             hw_stats->last_vfgprc, hw_stats->vfgprc);
2796
2797         /* Good Rx octets, include VF loopback */
2798         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2799             hw_stats->last_vfgorc, hw_stats->vfgorc);
2800
2801         /* Good Tx packet, include VF loopback */
2802         UPDATE_VF_STAT(IXGBE_VFGPTC,
2803             hw_stats->last_vfgptc, hw_stats->vfgptc);
2804
2805         /* Good Tx octets, include VF loopback */
2806         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2807             hw_stats->last_vfgotc, hw_stats->vfgotc);
2808
2809         /* Rx Multicst Packet */
2810         UPDATE_VF_STAT(IXGBE_VFMPRC,
2811             hw_stats->last_vfmprc, hw_stats->vfmprc);
2812 }
2813
2814 static int
2815 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2816                        unsigned n)
2817 {
2818         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2819                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2820         unsigned i;
2821
2822         if (n < IXGBEVF_NB_XSTATS)
2823                 return IXGBEVF_NB_XSTATS;
2824
2825         ixgbevf_update_stats(dev);
2826
2827         if (!xstats)
2828                 return 0;
2829
2830         /* Extended stats */
2831         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2832                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2833                          "%s", rte_ixgbevf_stats_strings[i].name);
2834                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2835                         rte_ixgbevf_stats_strings[i].offset);
2836         }
2837
2838         return IXGBEVF_NB_XSTATS;
2839 }
2840
2841 static void
2842 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2843 {
2844         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2845                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2846
2847         ixgbevf_update_stats(dev);
2848
2849         if (stats == NULL)
2850                 return;
2851
2852         stats->ipackets = hw_stats->vfgprc;
2853         stats->ibytes = hw_stats->vfgorc;
2854         stats->opackets = hw_stats->vfgptc;
2855         stats->obytes = hw_stats->vfgotc;
2856 }
2857
2858 static void
2859 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2860 {
2861         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2862                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2863
2864         /* Sync HW register to the last stats */
2865         ixgbevf_dev_stats_get(dev, NULL);
2866
2867         /* reset HW current stats*/
2868         hw_stats->vfgprc = 0;
2869         hw_stats->vfgorc = 0;
2870         hw_stats->vfgptc = 0;
2871         hw_stats->vfgotc = 0;
2872 }
2873
2874 static void
2875 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2876 {
2877         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2878         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2879
2880         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2881         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2882         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
2883                 /*
2884                  * When DCB/VT is off, maximum number of queues changes,
2885                  * except for 82598EB, which remains constant.
2886                  */
2887                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2888                                 hw->mac.type != ixgbe_mac_82598EB)
2889                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
2890         }
2891         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2892         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2893         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2894         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2895         dev_info->max_vfs = dev->pci_dev->max_vfs;
2896         if (hw->mac.type == ixgbe_mac_82598EB)
2897                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2898         else
2899                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2900         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2901         dev_info->rx_offload_capa =
2902                 DEV_RX_OFFLOAD_VLAN_STRIP |
2903                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2904                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2905                 DEV_RX_OFFLOAD_TCP_CKSUM;
2906
2907         /*
2908          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2909          * mode.
2910          */
2911         if ((hw->mac.type == ixgbe_mac_82599EB ||
2912              hw->mac.type == ixgbe_mac_X540) &&
2913             !RTE_ETH_DEV_SRIOV(dev).active)
2914                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2915
2916         if (hw->mac.type == ixgbe_mac_X550 ||
2917             hw->mac.type == ixgbe_mac_X550EM_x ||
2918             hw->mac.type == ixgbe_mac_X550EM_a)
2919                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2920
2921         dev_info->tx_offload_capa =
2922                 DEV_TX_OFFLOAD_VLAN_INSERT |
2923                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2924                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2925                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2926                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2927                 DEV_TX_OFFLOAD_TCP_TSO;
2928
2929         if (hw->mac.type == ixgbe_mac_X550 ||
2930             hw->mac.type == ixgbe_mac_X550EM_x ||
2931             hw->mac.type == ixgbe_mac_X550EM_a)
2932                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2933
2934         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2935                 .rx_thresh = {
2936                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2937                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2938                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2939                 },
2940                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2941                 .rx_drop_en = 0,
2942         };
2943
2944         dev_info->default_txconf = (struct rte_eth_txconf) {
2945                 .tx_thresh = {
2946                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2947                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2948                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2949                 },
2950                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2951                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2952                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2953                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2954         };
2955
2956         dev_info->rx_desc_lim = rx_desc_lim;
2957         dev_info->tx_desc_lim = tx_desc_lim;
2958
2959         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2960         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2961         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2962
2963         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2964         if (hw->mac.type == ixgbe_mac_X540 ||
2965             hw->mac.type == ixgbe_mac_X540_vf ||
2966             hw->mac.type == ixgbe_mac_X550 ||
2967             hw->mac.type == ixgbe_mac_X550_vf) {
2968                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2969         }
2970 }
2971
2972 static const uint32_t *
2973 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2974 {
2975         static const uint32_t ptypes[] = {
2976                 /* For non-vec functions,
2977                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
2978                  * for vec functions,
2979                  * refers to _recv_raw_pkts_vec().
2980                  */
2981                 RTE_PTYPE_L2_ETHER,
2982                 RTE_PTYPE_L3_IPV4,
2983                 RTE_PTYPE_L3_IPV4_EXT,
2984                 RTE_PTYPE_L3_IPV6,
2985                 RTE_PTYPE_L3_IPV6_EXT,
2986                 RTE_PTYPE_L4_SCTP,
2987                 RTE_PTYPE_L4_TCP,
2988                 RTE_PTYPE_L4_UDP,
2989                 RTE_PTYPE_TUNNEL_IP,
2990                 RTE_PTYPE_INNER_L3_IPV6,
2991                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2992                 RTE_PTYPE_INNER_L4_TCP,
2993                 RTE_PTYPE_INNER_L4_UDP,
2994                 RTE_PTYPE_UNKNOWN
2995         };
2996
2997         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
2998             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
2999             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3000             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3001                 return ptypes;
3002         return NULL;
3003 }
3004
3005 static void
3006 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3007                      struct rte_eth_dev_info *dev_info)
3008 {
3009         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3010
3011         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3012         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3013         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3014         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3015         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3016         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3017         dev_info->max_vfs = dev->pci_dev->max_vfs;
3018         if (hw->mac.type == ixgbe_mac_82598EB)
3019                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3020         else
3021                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3022         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3023                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3024                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3025                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3026         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3027                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3028                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3029                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3030                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3031                                 DEV_TX_OFFLOAD_TCP_TSO;
3032
3033         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3034                 .rx_thresh = {
3035                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3036                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3037                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3038                 },
3039                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3040                 .rx_drop_en = 0,
3041         };
3042
3043         dev_info->default_txconf = (struct rte_eth_txconf) {
3044                 .tx_thresh = {
3045                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3046                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3047                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3048                 },
3049                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3050                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3051                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3052                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3053         };
3054
3055         dev_info->rx_desc_lim = rx_desc_lim;
3056         dev_info->tx_desc_lim = tx_desc_lim;
3057 }
3058
3059 /* return 0 means link status changed, -1 means not changed */
3060 static int
3061 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3062 {
3063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3064         struct rte_eth_link link, old;
3065         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3066         int link_up;
3067         int diag;
3068
3069         link.link_status = ETH_LINK_DOWN;
3070         link.link_speed = 0;
3071         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3072         memset(&old, 0, sizeof(old));
3073         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3074
3075         hw->mac.get_link_status = true;
3076
3077         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3078         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3079                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3080         else
3081                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3082
3083         if (diag != 0) {
3084                 link.link_speed = ETH_SPEED_NUM_100M;
3085                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3086                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3087                 if (link.link_status == old.link_status)
3088                         return -1;
3089                 return 0;
3090         }
3091
3092         if (link_up == 0) {
3093                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3094                 if (link.link_status == old.link_status)
3095                         return -1;
3096                 return 0;
3097         }
3098         link.link_status = ETH_LINK_UP;
3099         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3100
3101         switch (link_speed) {
3102         default:
3103         case IXGBE_LINK_SPEED_UNKNOWN:
3104                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3105                 link.link_speed = ETH_SPEED_NUM_100M;
3106                 break;
3107
3108         case IXGBE_LINK_SPEED_100_FULL:
3109                 link.link_speed = ETH_SPEED_NUM_100M;
3110                 break;
3111
3112         case IXGBE_LINK_SPEED_1GB_FULL:
3113                 link.link_speed = ETH_SPEED_NUM_1G;
3114                 break;
3115
3116         case IXGBE_LINK_SPEED_10GB_FULL:
3117                 link.link_speed = ETH_SPEED_NUM_10G;
3118                 break;
3119         }
3120         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3121
3122         if (link.link_status == old.link_status)
3123                 return -1;
3124
3125         return 0;
3126 }
3127
3128 static void
3129 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3130 {
3131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3132         uint32_t fctrl;
3133
3134         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3135         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3136         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3137 }
3138
3139 static void
3140 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3141 {
3142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3143         uint32_t fctrl;
3144
3145         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3146         fctrl &= (~IXGBE_FCTRL_UPE);
3147         if (dev->data->all_multicast == 1)
3148                 fctrl |= IXGBE_FCTRL_MPE;
3149         else
3150                 fctrl &= (~IXGBE_FCTRL_MPE);
3151         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3152 }
3153
3154 static void
3155 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3156 {
3157         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3158         uint32_t fctrl;
3159
3160         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3161         fctrl |= IXGBE_FCTRL_MPE;
3162         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3163 }
3164
3165 static void
3166 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3167 {
3168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3169         uint32_t fctrl;
3170
3171         if (dev->data->promiscuous == 1)
3172                 return; /* must remain in all_multicast mode */
3173
3174         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3175         fctrl &= (~IXGBE_FCTRL_MPE);
3176         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3177 }
3178
3179 /**
3180  * It clears the interrupt causes and enables the interrupt.
3181  * It will be called once only during nic initialized.
3182  *
3183  * @param dev
3184  *  Pointer to struct rte_eth_dev.
3185  *
3186  * @return
3187  *  - On success, zero.
3188  *  - On failure, a negative value.
3189  */
3190 static int
3191 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3192 {
3193         struct ixgbe_interrupt *intr =
3194                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3195
3196         ixgbe_dev_link_status_print(dev);
3197         intr->mask |= IXGBE_EICR_LSC;
3198
3199         return 0;
3200 }
3201
3202 /**
3203  * It clears the interrupt causes and enables the interrupt.
3204  * It will be called once only during nic initialized.
3205  *
3206  * @param dev
3207  *  Pointer to struct rte_eth_dev.
3208  *
3209  * @return
3210  *  - On success, zero.
3211  *  - On failure, a negative value.
3212  */
3213 static int
3214 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3215 {
3216         struct ixgbe_interrupt *intr =
3217                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3218
3219         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3220
3221         return 0;
3222 }
3223
3224 /*
3225  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3226  *
3227  * @param dev
3228  *  Pointer to struct rte_eth_dev.
3229  *
3230  * @return
3231  *  - On success, zero.
3232  *  - On failure, a negative value.
3233  */
3234 static int
3235 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3236 {
3237         uint32_t eicr;
3238         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3239         struct ixgbe_interrupt *intr =
3240                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3241
3242         /* clear all cause mask */
3243         ixgbe_disable_intr(hw);
3244
3245         /* read-on-clear nic registers here */
3246         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3247         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3248
3249         intr->flags = 0;
3250
3251         /* set flag for async link update */
3252         if (eicr & IXGBE_EICR_LSC)
3253                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3254
3255         if (eicr & IXGBE_EICR_MAILBOX)
3256                 intr->flags |= IXGBE_FLAG_MAILBOX;
3257
3258         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3259             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3260             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3261                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3262
3263         return 0;
3264 }
3265
3266 /**
3267  * It gets and then prints the link status.
3268  *
3269  * @param dev
3270  *  Pointer to struct rte_eth_dev.
3271  *
3272  * @return
3273  *  - On success, zero.
3274  *  - On failure, a negative value.
3275  */
3276 static void
3277 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3278 {
3279         struct rte_eth_link link;
3280
3281         memset(&link, 0, sizeof(link));
3282         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3283         if (link.link_status) {
3284                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3285                                         (int)(dev->data->port_id),
3286                                         (unsigned)link.link_speed,
3287                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3288                                         "full-duplex" : "half-duplex");
3289         } else {
3290                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3291                                 (int)(dev->data->port_id));
3292         }
3293         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3294                                 dev->pci_dev->addr.domain,
3295                                 dev->pci_dev->addr.bus,
3296                                 dev->pci_dev->addr.devid,
3297                                 dev->pci_dev->addr.function);
3298 }
3299
3300 /*
3301  * It executes link_update after knowing an interrupt occurred.
3302  *
3303  * @param dev
3304  *  Pointer to struct rte_eth_dev.
3305  *
3306  * @return
3307  *  - On success, zero.
3308  *  - On failure, a negative value.
3309  */
3310 static int
3311 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3312 {
3313         struct ixgbe_interrupt *intr =
3314                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3315         int64_t timeout;
3316         struct rte_eth_link link;
3317         int intr_enable_delay = false;
3318         struct ixgbe_hw *hw =
3319                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3320
3321         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3322
3323         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3324                 ixgbe_pf_mbx_process(dev);
3325                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3326         }
3327
3328         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3329                 ixgbe_handle_lasi(hw);
3330                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3331         }
3332
3333         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3334                 /* get the link status before link update, for predicting later */
3335                 memset(&link, 0, sizeof(link));
3336                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3337
3338                 ixgbe_dev_link_update(dev, 0);
3339
3340                 /* likely to up */
3341                 if (!link.link_status)
3342                         /* handle it 1 sec later, wait it being stable */
3343                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3344                 /* likely to down */
3345                 else
3346                         /* handle it 4 sec later, wait it being stable */
3347                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3348
3349                 ixgbe_dev_link_status_print(dev);
3350
3351                 intr_enable_delay = true;
3352         }
3353
3354         if (intr_enable_delay) {
3355                 if (rte_eal_alarm_set(timeout * 1000,
3356                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3357                         PMD_DRV_LOG(ERR, "Error setting alarm");
3358         } else {
3359                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3360                 ixgbe_enable_intr(dev);
3361                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3362         }
3363
3364
3365         return 0;
3366 }
3367
3368 /**
3369  * Interrupt handler which shall be registered for alarm callback for delayed
3370  * handling specific interrupt to wait for the stable nic state. As the
3371  * NIC interrupt state is not stable for ixgbe after link is just down,
3372  * it needs to wait 4 seconds to get the stable status.
3373  *
3374  * @param handle
3375  *  Pointer to interrupt handle.
3376  * @param param
3377  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3378  *
3379  * @return
3380  *  void
3381  */
3382 static void
3383 ixgbe_dev_interrupt_delayed_handler(void *param)
3384 {
3385         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3386         struct ixgbe_interrupt *intr =
3387                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3388         struct ixgbe_hw *hw =
3389                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3390         uint32_t eicr;
3391
3392         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3393         if (eicr & IXGBE_EICR_MAILBOX)
3394                 ixgbe_pf_mbx_process(dev);
3395
3396         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3397                 ixgbe_handle_lasi(hw);
3398                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3399         }
3400
3401         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3402                 ixgbe_dev_link_update(dev, 0);
3403                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3404                 ixgbe_dev_link_status_print(dev);
3405                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3406         }
3407
3408         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3409         ixgbe_enable_intr(dev);
3410         rte_intr_enable(&(dev->pci_dev->intr_handle));
3411 }
3412
3413 /**
3414  * Interrupt handler triggered by NIC  for handling
3415  * specific interrupt.
3416  *
3417  * @param handle
3418  *  Pointer to interrupt handle.
3419  * @param param
3420  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3421  *
3422  * @return
3423  *  void
3424  */
3425 static void
3426 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3427                             void *param)
3428 {
3429         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3430
3431         ixgbe_dev_interrupt_get_status(dev);
3432         ixgbe_dev_interrupt_action(dev);
3433 }
3434
3435 static int
3436 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3437 {
3438         struct ixgbe_hw *hw;
3439
3440         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3441         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3442 }
3443
3444 static int
3445 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3446 {
3447         struct ixgbe_hw *hw;
3448
3449         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3450         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3451 }
3452
3453 static int
3454 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3455 {
3456         struct ixgbe_hw *hw;
3457         uint32_t mflcn_reg;
3458         uint32_t fccfg_reg;
3459         int rx_pause;
3460         int tx_pause;
3461
3462         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3463
3464         fc_conf->pause_time = hw->fc.pause_time;
3465         fc_conf->high_water = hw->fc.high_water[0];
3466         fc_conf->low_water = hw->fc.low_water[0];
3467         fc_conf->send_xon = hw->fc.send_xon;
3468         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3469
3470         /*
3471          * Return rx_pause status according to actual setting of
3472          * MFLCN register.
3473          */
3474         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3475         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3476                 rx_pause = 1;
3477         else
3478                 rx_pause = 0;
3479
3480         /*
3481          * Return tx_pause status according to actual setting of
3482          * FCCFG register.
3483          */
3484         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3485         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3486                 tx_pause = 1;
3487         else
3488                 tx_pause = 0;
3489
3490         if (rx_pause && tx_pause)
3491                 fc_conf->mode = RTE_FC_FULL;
3492         else if (rx_pause)
3493                 fc_conf->mode = RTE_FC_RX_PAUSE;
3494         else if (tx_pause)
3495                 fc_conf->mode = RTE_FC_TX_PAUSE;
3496         else
3497                 fc_conf->mode = RTE_FC_NONE;
3498
3499         return 0;
3500 }
3501
3502 static int
3503 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3504 {
3505         struct ixgbe_hw *hw;
3506         int err;
3507         uint32_t rx_buf_size;
3508         uint32_t max_high_water;
3509         uint32_t mflcn;
3510         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3511                 ixgbe_fc_none,
3512                 ixgbe_fc_rx_pause,
3513                 ixgbe_fc_tx_pause,
3514                 ixgbe_fc_full
3515         };
3516
3517         PMD_INIT_FUNC_TRACE();
3518
3519         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3520         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3521         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3522
3523         /*
3524          * At least reserve one Ethernet frame for watermark
3525          * high_water/low_water in kilo bytes for ixgbe
3526          */
3527         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3528         if ((fc_conf->high_water > max_high_water) ||
3529                 (fc_conf->high_water < fc_conf->low_water)) {
3530                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3531                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3532                 return -EINVAL;
3533         }
3534
3535         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3536         hw->fc.pause_time     = fc_conf->pause_time;
3537         hw->fc.high_water[0]  = fc_conf->high_water;
3538         hw->fc.low_water[0]   = fc_conf->low_water;
3539         hw->fc.send_xon       = fc_conf->send_xon;
3540         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3541
3542         err = ixgbe_fc_enable(hw);
3543
3544         /* Not negotiated is not an error case */
3545         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3546
3547                 /* check if we want to forward MAC frames - driver doesn't have native
3548                  * capability to do that, so we'll write the registers ourselves */
3549
3550                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3551
3552                 /* set or clear MFLCN.PMCF bit depending on configuration */
3553                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3554                         mflcn |= IXGBE_MFLCN_PMCF;
3555                 else
3556                         mflcn &= ~IXGBE_MFLCN_PMCF;
3557
3558                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3559                 IXGBE_WRITE_FLUSH(hw);
3560
3561                 return 0;
3562         }
3563
3564         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3565         return -EIO;
3566 }
3567
3568 /**
3569  *  ixgbe_pfc_enable_generic - Enable flow control
3570  *  @hw: pointer to hardware structure
3571  *  @tc_num: traffic class number
3572  *  Enable flow control according to the current settings.
3573  */
3574 static int
3575 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3576 {
3577         int ret_val = 0;
3578         uint32_t mflcn_reg, fccfg_reg;
3579         uint32_t reg;
3580         uint32_t fcrtl, fcrth;
3581         uint8_t i;
3582         uint8_t nb_rx_en;
3583
3584         /* Validate the water mark configuration */
3585         if (!hw->fc.pause_time) {
3586                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3587                 goto out;
3588         }
3589
3590         /* Low water mark of zero causes XOFF floods */
3591         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3592                  /* High/Low water can not be 0 */
3593                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3594                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3595                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3596                         goto out;
3597                 }
3598
3599                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3600                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3601                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3602                         goto out;
3603                 }
3604         }
3605         /* Negotiate the fc mode to use */
3606         ixgbe_fc_autoneg(hw);
3607
3608         /* Disable any previous flow control settings */
3609         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3610         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3611
3612         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3613         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3614
3615         switch (hw->fc.current_mode) {
3616         case ixgbe_fc_none:
3617                 /*
3618                  * If the count of enabled RX Priority Flow control >1,
3619                  * and the TX pause can not be disabled
3620                  */
3621                 nb_rx_en = 0;
3622                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3623                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3624                         if (reg & IXGBE_FCRTH_FCEN)
3625                                 nb_rx_en++;
3626                 }
3627                 if (nb_rx_en > 1)
3628                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3629                 break;
3630         case ixgbe_fc_rx_pause:
3631                 /*
3632                  * Rx Flow control is enabled and Tx Flow control is
3633                  * disabled by software override. Since there really
3634                  * isn't a way to advertise that we are capable of RX
3635                  * Pause ONLY, we will advertise that we support both
3636                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3637                  * disable the adapter's ability to send PAUSE frames.
3638                  */
3639                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3640                 /*
3641                  * If the count of enabled RX Priority Flow control >1,
3642                  * and the TX pause can not be disabled
3643                  */
3644                 nb_rx_en = 0;
3645                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3646                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3647                         if (reg & IXGBE_FCRTH_FCEN)
3648                                 nb_rx_en++;
3649                 }
3650                 if (nb_rx_en > 1)
3651                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3652                 break;
3653         case ixgbe_fc_tx_pause:
3654                 /*
3655                  * Tx Flow control is enabled, and Rx Flow control is
3656                  * disabled by software override.
3657                  */
3658                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3659                 break;
3660         case ixgbe_fc_full:
3661                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3662                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3663                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3664                 break;
3665         default:
3666                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3667                 ret_val = IXGBE_ERR_CONFIG;
3668                 goto out;
3669         }
3670
3671         /* Set 802.3x based flow control settings. */
3672         mflcn_reg |= IXGBE_MFLCN_DPF;
3673         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3674         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3675
3676         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3677         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3678                 hw->fc.high_water[tc_num]) {
3679                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3680                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3681                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3682         } else {
3683                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3684                 /*
3685                  * In order to prevent Tx hangs when the internal Tx
3686                  * switch is enabled we must set the high water mark
3687                  * to the maximum FCRTH value.  This allows the Tx
3688                  * switch to function even under heavy Rx workloads.
3689                  */
3690                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3691         }
3692         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3693
3694         /* Configure pause time (2 TCs per register) */
3695         reg = hw->fc.pause_time * 0x00010001;
3696         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3697                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3698
3699         /* Configure flow control refresh threshold value */
3700         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3701
3702 out:
3703         return ret_val;
3704 }
3705
3706 static int
3707 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3708 {
3709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3711
3712         if (hw->mac.type != ixgbe_mac_82598EB) {
3713                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3714         }
3715         return ret_val;
3716 }
3717
3718 static int
3719 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3720 {
3721         int err;
3722         uint32_t rx_buf_size;
3723         uint32_t max_high_water;
3724         uint8_t tc_num;
3725         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3726         struct ixgbe_hw *hw =
3727                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3728         struct ixgbe_dcb_config *dcb_config =
3729                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3730
3731         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3732                 ixgbe_fc_none,
3733                 ixgbe_fc_rx_pause,
3734                 ixgbe_fc_tx_pause,
3735                 ixgbe_fc_full
3736         };
3737
3738         PMD_INIT_FUNC_TRACE();
3739
3740         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3741         tc_num = map[pfc_conf->priority];
3742         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3743         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3744         /*
3745          * At least reserve one Ethernet frame for watermark
3746          * high_water/low_water in kilo bytes for ixgbe
3747          */
3748         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3749         if ((pfc_conf->fc.high_water > max_high_water) ||
3750             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3751                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3752                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3753                 return -EINVAL;
3754         }
3755
3756         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3757         hw->fc.pause_time = pfc_conf->fc.pause_time;
3758         hw->fc.send_xon = pfc_conf->fc.send_xon;
3759         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3760         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3761
3762         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3763
3764         /* Not negotiated is not an error case */
3765         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3766                 return 0;
3767
3768         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3769         return -EIO;
3770 }
3771
3772 static int
3773 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3774                           struct rte_eth_rss_reta_entry64 *reta_conf,
3775                           uint16_t reta_size)
3776 {
3777         uint16_t i, sp_reta_size;
3778         uint8_t j, mask;
3779         uint32_t reta, r;
3780         uint16_t idx, shift;
3781         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3782         uint32_t reta_reg;
3783
3784         PMD_INIT_FUNC_TRACE();
3785
3786         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3787                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3788                         "NIC.");
3789                 return -ENOTSUP;
3790         }
3791
3792         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3793         if (reta_size != sp_reta_size) {
3794                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3795                         "(%d) doesn't match the number hardware can supported "
3796                         "(%d)\n", reta_size, sp_reta_size);
3797                 return -EINVAL;
3798         }
3799
3800         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3801                 idx = i / RTE_RETA_GROUP_SIZE;
3802                 shift = i % RTE_RETA_GROUP_SIZE;
3803                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3804                                                 IXGBE_4_BIT_MASK);
3805                 if (!mask)
3806                         continue;
3807                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3808                 if (mask == IXGBE_4_BIT_MASK)
3809                         r = 0;
3810                 else
3811                         r = IXGBE_READ_REG(hw, reta_reg);
3812                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3813                         if (mask & (0x1 << j))
3814                                 reta |= reta_conf[idx].reta[shift + j] <<
3815                                                         (CHAR_BIT * j);
3816                         else
3817                                 reta |= r & (IXGBE_8_BIT_MASK <<
3818                                                 (CHAR_BIT * j));
3819                 }
3820                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3821         }
3822
3823         return 0;
3824 }
3825
3826 static int
3827 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3828                          struct rte_eth_rss_reta_entry64 *reta_conf,
3829                          uint16_t reta_size)
3830 {
3831         uint16_t i, sp_reta_size;
3832         uint8_t j, mask;
3833         uint32_t reta;
3834         uint16_t idx, shift;
3835         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3836         uint32_t reta_reg;
3837
3838         PMD_INIT_FUNC_TRACE();
3839         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3840         if (reta_size != sp_reta_size) {
3841                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3842                         "(%d) doesn't match the number hardware can supported "
3843                         "(%d)\n", reta_size, sp_reta_size);
3844                 return -EINVAL;
3845         }
3846
3847         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3848                 idx = i / RTE_RETA_GROUP_SIZE;
3849                 shift = i % RTE_RETA_GROUP_SIZE;
3850                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3851                                                 IXGBE_4_BIT_MASK);
3852                 if (!mask)
3853                         continue;
3854
3855                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3856                 reta = IXGBE_READ_REG(hw, reta_reg);
3857                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3858                         if (mask & (0x1 << j))
3859                                 reta_conf[idx].reta[shift + j] =
3860                                         ((reta >> (CHAR_BIT * j)) &
3861                                                 IXGBE_8_BIT_MASK);
3862                 }
3863         }
3864
3865         return 0;
3866 }
3867
3868 static void
3869 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3870                                 uint32_t index, uint32_t pool)
3871 {
3872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3873         uint32_t enable_addr = 1;
3874
3875         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3876 }
3877
3878 static void
3879 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3880 {
3881         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3882
3883         ixgbe_clear_rar(hw, index);
3884 }
3885
3886 static void
3887 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3888 {
3889         ixgbe_remove_rar(dev, 0);
3890
3891         ixgbe_add_rar(dev, addr, 0, 0);
3892 }
3893
3894 static int
3895 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3896 {
3897         uint32_t hlreg0;
3898         uint32_t maxfrs;
3899         struct ixgbe_hw *hw;
3900         struct rte_eth_dev_info dev_info;
3901         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3902
3903         ixgbe_dev_info_get(dev, &dev_info);
3904
3905         /* check that mtu is within the allowed range */
3906         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3907                 return -EINVAL;
3908
3909         /* refuse mtu that requires the support of scattered packets when this
3910          * feature has not been enabled before.
3911          */
3912         if (!dev->data->scattered_rx &&
3913             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3914              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3915                 return -EINVAL;
3916
3917         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3918         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3919
3920         /* switch to jumbo mode if needed */
3921         if (frame_size > ETHER_MAX_LEN) {
3922                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3923                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3924         } else {
3925                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3926                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3927         }
3928         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3929
3930         /* update max frame size */
3931         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3932
3933         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3934         maxfrs &= 0x0000FFFF;
3935         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3936         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3937
3938         return 0;
3939 }
3940
3941 /*
3942  * Virtual Function operations
3943  */
3944 static void
3945 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3946 {
3947         PMD_INIT_FUNC_TRACE();
3948
3949         /* Clear interrupt mask to stop from interrupts being generated */
3950         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3951
3952         IXGBE_WRITE_FLUSH(hw);
3953 }
3954
3955 static void
3956 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3957 {
3958         PMD_INIT_FUNC_TRACE();
3959
3960         /* VF enable interrupt autoclean */
3961         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3962         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3963         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3964
3965         IXGBE_WRITE_FLUSH(hw);
3966 }
3967
3968 static int
3969 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3970 {
3971         struct rte_eth_conf *conf = &dev->data->dev_conf;
3972         struct ixgbe_adapter *adapter =
3973                         (struct ixgbe_adapter *)dev->data->dev_private;
3974
3975         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3976                      dev->data->port_id);
3977
3978         /*
3979          * VF has no ability to enable/disable HW CRC
3980          * Keep the persistent behavior the same as Host PF
3981          */
3982 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3983         if (!conf->rxmode.hw_strip_crc) {
3984                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3985                 conf->rxmode.hw_strip_crc = 1;
3986         }
3987 #else
3988         if (conf->rxmode.hw_strip_crc) {
3989                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3990                 conf->rxmode.hw_strip_crc = 0;
3991         }
3992 #endif
3993
3994         /*
3995          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3996          * allocation or vector Rx preconditions we will reset it.
3997          */
3998         adapter->rx_bulk_alloc_allowed = true;
3999         adapter->rx_vec_allowed = true;
4000
4001         return 0;
4002 }
4003
4004 static int
4005 ixgbevf_dev_start(struct rte_eth_dev *dev)
4006 {
4007         struct ixgbe_hw *hw =
4008                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4009         uint32_t intr_vector = 0;
4010         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4011
4012         int err, mask = 0;
4013
4014         PMD_INIT_FUNC_TRACE();
4015
4016         hw->mac.ops.reset_hw(hw);
4017         hw->mac.get_link_status = true;
4018
4019         /* negotiate mailbox API version to use with the PF. */
4020         ixgbevf_negotiate_api(hw);
4021
4022         ixgbevf_dev_tx_init(dev);
4023
4024         /* This can fail when allocating mbufs for descriptor rings */
4025         err = ixgbevf_dev_rx_init(dev);
4026         if (err) {
4027                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4028                 ixgbe_dev_clear_queues(dev);
4029                 return err;
4030         }
4031
4032         /* Set vfta */
4033         ixgbevf_set_vfta_all(dev, 1);
4034
4035         /* Set HW strip */
4036         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4037                 ETH_VLAN_EXTEND_MASK;
4038         ixgbevf_vlan_offload_set(dev, mask);
4039
4040         ixgbevf_dev_rxtx_start(dev);
4041
4042         /* check and configure queue intr-vector mapping */
4043         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4044                 intr_vector = dev->data->nb_rx_queues;
4045                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4046                         return -1;
4047         }
4048
4049         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4050                 intr_handle->intr_vec =
4051                         rte_zmalloc("intr_vec",
4052                                     dev->data->nb_rx_queues * sizeof(int), 0);
4053                 if (intr_handle->intr_vec == NULL) {
4054                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4055                                      " intr_vec\n", dev->data->nb_rx_queues);
4056                         return -ENOMEM;
4057                 }
4058         }
4059         ixgbevf_configure_msix(dev);
4060
4061         rte_intr_enable(intr_handle);
4062
4063         /* Re-enable interrupt for VF */
4064         ixgbevf_intr_enable(hw);
4065
4066         return 0;
4067 }
4068
4069 static void
4070 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4071 {
4072         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4073         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4074
4075         PMD_INIT_FUNC_TRACE();
4076
4077         hw->adapter_stopped = 1;
4078         ixgbe_stop_adapter(hw);
4079
4080         /*
4081           * Clear what we set, but we still keep shadow_vfta to
4082           * restore after device starts
4083           */
4084         ixgbevf_set_vfta_all(dev, 0);
4085
4086         /* Clear stored conf */
4087         dev->data->scattered_rx = 0;
4088
4089         ixgbe_dev_clear_queues(dev);
4090
4091         /* Clean datapath event and queue/vec mapping */
4092         rte_intr_efd_disable(intr_handle);
4093         if (intr_handle->intr_vec != NULL) {
4094                 rte_free(intr_handle->intr_vec);
4095                 intr_handle->intr_vec = NULL;
4096         }
4097 }
4098
4099 static void
4100 ixgbevf_dev_close(struct rte_eth_dev *dev)
4101 {
4102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4103
4104         PMD_INIT_FUNC_TRACE();
4105
4106         ixgbe_reset_hw(hw);
4107
4108         ixgbevf_dev_stop(dev);
4109
4110         ixgbe_dev_free_queues(dev);
4111
4112         /**
4113          * Remove the VF MAC address ro ensure
4114          * that the VF traffic goes to the PF
4115          * after stop, close and detach of the VF
4116          **/
4117         ixgbevf_remove_mac_addr(dev, 0);
4118 }
4119
4120 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4121 {
4122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4123         struct ixgbe_vfta *shadow_vfta =
4124                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4125         int i = 0, j = 0, vfta = 0, mask = 1;
4126
4127         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4128                 vfta = shadow_vfta->vfta[i];
4129                 if (vfta) {
4130                         mask = 1;
4131                         for (j = 0; j < 32; j++) {
4132                                 if (vfta & mask)
4133                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4134                                 mask <<= 1;
4135                         }
4136                 }
4137         }
4138
4139 }
4140
4141 static int
4142 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4143 {
4144         struct ixgbe_hw *hw =
4145                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4146         struct ixgbe_vfta *shadow_vfta =
4147                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4148         uint32_t vid_idx = 0;
4149         uint32_t vid_bit = 0;
4150         int ret = 0;
4151
4152         PMD_INIT_FUNC_TRACE();
4153
4154         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4155         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4156         if (ret) {
4157                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4158                 return ret;
4159         }
4160         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4161         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4162
4163         /* Save what we set and retore it after device reset */
4164         if (on)
4165                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4166         else
4167                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4168
4169         return 0;
4170 }
4171
4172 static void
4173 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4174 {
4175         struct ixgbe_hw *hw =
4176                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4177         uint32_t ctrl;
4178
4179         PMD_INIT_FUNC_TRACE();
4180
4181         if (queue >= hw->mac.max_rx_queues)
4182                 return;
4183
4184         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4185         if (on)
4186                 ctrl |= IXGBE_RXDCTL_VME;
4187         else
4188                 ctrl &= ~IXGBE_RXDCTL_VME;
4189         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4190
4191         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4192 }
4193
4194 static void
4195 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4196 {
4197         struct ixgbe_hw *hw =
4198                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199         uint16_t i;
4200         int on = 0;
4201
4202         /* VF function only support hw strip feature, others are not support */
4203         if (mask & ETH_VLAN_STRIP_MASK) {
4204                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4205
4206                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4207                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4208         }
4209 }
4210
4211 static int
4212 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4213 {
4214         uint32_t reg_val;
4215
4216         /* we only need to do this if VMDq is enabled */
4217         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4218         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4219                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4220                 return -1;
4221         }
4222
4223         return 0;
4224 }
4225
4226 static uint32_t
4227 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4228 {
4229         uint32_t vector = 0;
4230
4231         switch (hw->mac.mc_filter_type) {
4232         case 0:   /* use bits [47:36] of the address */
4233                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4234                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4235                 break;
4236         case 1:   /* use bits [46:35] of the address */
4237                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4238                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4239                 break;
4240         case 2:   /* use bits [45:34] of the address */
4241                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4242                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4243                 break;
4244         case 3:   /* use bits [43:32] of the address */
4245                 vector = ((uc_addr->addr_bytes[4]) |
4246                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4247                 break;
4248         default:  /* Invalid mc_filter_type */
4249                 break;
4250         }
4251
4252         /* vector can only be 12-bits or boundary will be exceeded */
4253         vector &= 0xFFF;
4254         return vector;
4255 }
4256
4257 static int
4258 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4259                         uint8_t on)
4260 {
4261         uint32_t vector;
4262         uint32_t uta_idx;
4263         uint32_t reg_val;
4264         uint32_t uta_shift;
4265         uint32_t rc;
4266         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4267         const uint32_t ixgbe_uta_bit_shift = 5;
4268         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4269         const uint32_t bit1 = 0x1;
4270
4271         struct ixgbe_hw *hw =
4272                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4273         struct ixgbe_uta_info *uta_info =
4274                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4275
4276         /* The UTA table only exists on 82599 hardware and newer */
4277         if (hw->mac.type < ixgbe_mac_82599EB)
4278                 return -ENOTSUP;
4279
4280         vector = ixgbe_uta_vector(hw, mac_addr);
4281         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4282         uta_shift = vector & ixgbe_uta_bit_mask;
4283
4284         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4285         if (rc == on)
4286                 return 0;
4287
4288         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4289         if (on) {
4290                 uta_info->uta_in_use++;
4291                 reg_val |= (bit1 << uta_shift);
4292                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4293         } else {
4294                 uta_info->uta_in_use--;
4295                 reg_val &= ~(bit1 << uta_shift);
4296                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4297         }
4298
4299         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4300
4301         if (uta_info->uta_in_use > 0)
4302                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4303                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4304         else
4305                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4306
4307         return 0;
4308 }
4309
4310 static int
4311 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4312 {
4313         int i;
4314         struct ixgbe_hw *hw =
4315                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4316         struct ixgbe_uta_info *uta_info =
4317                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4318
4319         /* The UTA table only exists on 82599 hardware and newer */
4320         if (hw->mac.type < ixgbe_mac_82599EB)
4321                 return -ENOTSUP;
4322
4323         if (on) {
4324                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4325                         uta_info->uta_shadow[i] = ~0;
4326                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4327                 }
4328         } else {
4329                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4330                         uta_info->uta_shadow[i] = 0;
4331                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4332                 }
4333         }
4334         return 0;
4335
4336 }
4337
4338 uint32_t
4339 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4340 {
4341         uint32_t new_val = orig_val;
4342
4343         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4344                 new_val |= IXGBE_VMOLR_AUPE;
4345         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4346                 new_val |= IXGBE_VMOLR_ROMPE;
4347         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4348                 new_val |= IXGBE_VMOLR_ROPE;
4349         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4350                 new_val |= IXGBE_VMOLR_BAM;
4351         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4352                 new_val |= IXGBE_VMOLR_MPE;
4353
4354         return new_val;
4355 }
4356
4357 static int
4358 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4359                                uint16_t rx_mask, uint8_t on)
4360 {
4361         int val = 0;
4362
4363         struct ixgbe_hw *hw =
4364                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4365         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4366
4367         if (hw->mac.type == ixgbe_mac_82598EB) {
4368                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4369                              " on 82599 hardware and newer");
4370                 return -ENOTSUP;
4371         }
4372         if (ixgbe_vmdq_mode_check(hw) < 0)
4373                 return -ENOTSUP;
4374
4375         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4376
4377         if (on)
4378                 vmolr |= val;
4379         else
4380                 vmolr &= ~val;
4381
4382         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4383
4384         return 0;
4385 }
4386
4387 static int
4388 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4389 {
4390         uint32_t reg, addr;
4391         uint32_t val;
4392         const uint8_t bit1 = 0x1;
4393
4394         struct ixgbe_hw *hw =
4395                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4396
4397         if (ixgbe_vmdq_mode_check(hw) < 0)
4398                 return -ENOTSUP;
4399
4400         if (pool >= ETH_64_POOLS)
4401                 return -EINVAL;
4402
4403         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4404         if (pool >= 32) {
4405                 addr = IXGBE_VFRE(1);
4406                 val = bit1 << (pool - 32);
4407         } else {
4408                 addr = IXGBE_VFRE(0);
4409                 val = bit1 << pool;
4410         }
4411
4412         reg = IXGBE_READ_REG(hw, addr);
4413
4414         if (on)
4415                 reg |= val;
4416         else
4417                 reg &= ~val;
4418
4419         IXGBE_WRITE_REG(hw, addr, reg);
4420
4421         return 0;
4422 }
4423
4424 static int
4425 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4426 {
4427         uint32_t reg, addr;
4428         uint32_t val;
4429         const uint8_t bit1 = 0x1;
4430
4431         struct ixgbe_hw *hw =
4432                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4433
4434         if (ixgbe_vmdq_mode_check(hw) < 0)
4435                 return -ENOTSUP;
4436
4437         if (pool >= ETH_64_POOLS)
4438                 return -EINVAL;
4439
4440         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4441         if (pool >= 32) {
4442                 addr = IXGBE_VFTE(1);
4443                 val = bit1 << (pool - 32);
4444         } else {
4445                 addr = IXGBE_VFTE(0);
4446                 val = bit1 << pool;
4447         }
4448
4449         reg = IXGBE_READ_REG(hw, addr);
4450
4451         if (on)
4452                 reg |= val;
4453         else
4454                 reg &= ~val;
4455
4456         IXGBE_WRITE_REG(hw, addr, reg);
4457
4458         return 0;
4459 }
4460
4461 static int
4462 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4463                         uint64_t pool_mask, uint8_t vlan_on)
4464 {
4465         int ret = 0;
4466         uint16_t pool_idx;
4467         struct ixgbe_hw *hw =
4468                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4469
4470         if (ixgbe_vmdq_mode_check(hw) < 0)
4471                 return -ENOTSUP;
4472         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4473                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4474                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx, vlan_on);
4475                         if (ret < 0)
4476                                 return ret;
4477                 }
4478         }
4479
4480         return ret;
4481 }
4482
4483 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4484 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4485 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4486 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4487 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4488         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4489         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4490
4491 static int
4492 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4493                         struct rte_eth_mirror_conf *mirror_conf,
4494                         uint8_t rule_id, uint8_t on)
4495 {
4496         uint32_t mr_ctl, vlvf;
4497         uint32_t mp_lsb = 0;
4498         uint32_t mv_msb = 0;
4499         uint32_t mv_lsb = 0;
4500         uint32_t mp_msb = 0;
4501         uint8_t i = 0;
4502         int reg_index = 0;
4503         uint64_t vlan_mask = 0;
4504
4505         const uint8_t pool_mask_offset = 32;
4506         const uint8_t vlan_mask_offset = 32;
4507         const uint8_t dst_pool_offset = 8;
4508         const uint8_t rule_mr_offset  = 4;
4509         const uint8_t mirror_rule_mask = 0x0F;
4510
4511         struct ixgbe_mirror_info *mr_info =
4512                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4513         struct ixgbe_hw *hw =
4514                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4515         uint8_t mirror_type = 0;
4516
4517         if (ixgbe_vmdq_mode_check(hw) < 0)
4518                 return -ENOTSUP;
4519
4520         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4521                 return -EINVAL;
4522
4523         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4524                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4525                         mirror_conf->rule_type);
4526                 return -EINVAL;
4527         }
4528
4529         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4530                 mirror_type |= IXGBE_MRCTL_VLME;
4531                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4532                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4533                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4534                                 /* search vlan id related pool vlan filter index */
4535                                 reg_index = ixgbe_find_vlvf_slot(hw,
4536                                                 mirror_conf->vlan.vlan_id[i]);
4537                                 if (reg_index < 0)
4538                                         return -EINVAL;
4539                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4540                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4541                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4542                                       mirror_conf->vlan.vlan_id[i]))
4543                                         vlan_mask |= (1ULL << reg_index);
4544                                 else
4545                                         return -EINVAL;
4546                         }
4547                 }
4548
4549                 if (on) {
4550                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4551                         mv_msb = vlan_mask >> vlan_mask_offset;
4552
4553                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4554                                                 mirror_conf->vlan.vlan_mask;
4555                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4556                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4557                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4558                                                 mirror_conf->vlan.vlan_id[i];
4559                         }
4560                 } else {
4561                         mv_lsb = 0;
4562                         mv_msb = 0;
4563                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4564                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4565                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4566                 }
4567         }
4568
4569         /*
4570          * if enable pool mirror, write related pool mask register,if disable
4571          * pool mirror, clear PFMRVM register
4572          */
4573         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4574                 mirror_type |= IXGBE_MRCTL_VPME;
4575                 if (on) {
4576                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4577                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4578                         mr_info->mr_conf[rule_id].pool_mask =
4579                                         mirror_conf->pool_mask;
4580
4581                 } else {
4582                         mp_lsb = 0;
4583                         mp_msb = 0;
4584                         mr_info->mr_conf[rule_id].pool_mask = 0;
4585                 }
4586         }
4587         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4588                 mirror_type |= IXGBE_MRCTL_UPME;
4589         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4590                 mirror_type |= IXGBE_MRCTL_DPME;
4591
4592         /* read  mirror control register and recalculate it */
4593         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4594
4595         if (on) {
4596                 mr_ctl |= mirror_type;
4597                 mr_ctl &= mirror_rule_mask;
4598                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4599         } else
4600                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4601
4602         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4603         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4604
4605         /* write mirrror control  register */
4606         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4607
4608         /* write pool mirrror control  register */
4609         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4610                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4611                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4612                                 mp_msb);
4613         }
4614         /* write VLAN mirrror control  register */
4615         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4616                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4617                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4618                                 mv_msb);
4619         }
4620
4621         return 0;
4622 }
4623
4624 static int
4625 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4626 {
4627         int mr_ctl = 0;
4628         uint32_t lsb_val = 0;
4629         uint32_t msb_val = 0;
4630         const uint8_t rule_mr_offset = 4;
4631
4632         struct ixgbe_hw *hw =
4633                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4634         struct ixgbe_mirror_info *mr_info =
4635                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4636
4637         if (ixgbe_vmdq_mode_check(hw) < 0)
4638                 return -ENOTSUP;
4639
4640         memset(&mr_info->mr_conf[rule_id], 0,
4641                 sizeof(struct rte_eth_mirror_conf));
4642
4643         /* clear PFVMCTL register */
4644         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4645
4646         /* clear pool mask register */
4647         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4648         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4649
4650         /* clear vlan mask register */
4651         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4652         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4653
4654         return 0;
4655 }
4656
4657 static int
4658 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4659 {
4660         uint32_t mask;
4661         struct ixgbe_hw *hw =
4662                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4663
4664         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4665         mask |= (1 << IXGBE_MISC_VEC_ID);
4666         RTE_SET_USED(queue_id);
4667         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4668
4669         rte_intr_enable(&dev->pci_dev->intr_handle);
4670
4671         return 0;
4672 }
4673
4674 static int
4675 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4676 {
4677         uint32_t mask;
4678         struct ixgbe_hw *hw =
4679                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4680
4681         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4682         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4683         RTE_SET_USED(queue_id);
4684         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4685
4686         return 0;
4687 }
4688
4689 static int
4690 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4691 {
4692         uint32_t mask;
4693         struct ixgbe_hw *hw =
4694                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695         struct ixgbe_interrupt *intr =
4696                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4697
4698         if (queue_id < 16) {
4699                 ixgbe_disable_intr(hw);
4700                 intr->mask |= (1 << queue_id);
4701                 ixgbe_enable_intr(dev);
4702         } else if (queue_id < 32) {
4703                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4704                 mask &= (1 << queue_id);
4705                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4706         } else if (queue_id < 64) {
4707                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4708                 mask &= (1 << (queue_id - 32));
4709                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4710         }
4711         rte_intr_enable(&dev->pci_dev->intr_handle);
4712
4713         return 0;
4714 }
4715
4716 static int
4717 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4718 {
4719         uint32_t mask;
4720         struct ixgbe_hw *hw =
4721                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4722         struct ixgbe_interrupt *intr =
4723                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4724
4725         if (queue_id < 16) {
4726                 ixgbe_disable_intr(hw);
4727                 intr->mask &= ~(1 << queue_id);
4728                 ixgbe_enable_intr(dev);
4729         } else if (queue_id < 32) {
4730                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4731                 mask &= ~(1 << queue_id);
4732                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4733         } else if (queue_id < 64) {
4734                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4735                 mask &= ~(1 << (queue_id - 32));
4736                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4737         }
4738
4739         return 0;
4740 }
4741
4742 static void
4743 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4744                      uint8_t queue, uint8_t msix_vector)
4745 {
4746         uint32_t tmp, idx;
4747
4748         if (direction == -1) {
4749                 /* other causes */
4750                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4751                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4752                 tmp &= ~0xFF;
4753                 tmp |= msix_vector;
4754                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4755         } else {
4756                 /* rx or tx cause */
4757                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4758                 idx = ((16 * (queue & 1)) + (8 * direction));
4759                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4760                 tmp &= ~(0xFF << idx);
4761                 tmp |= (msix_vector << idx);
4762                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4763         }
4764 }
4765
4766 /**
4767  * set the IVAR registers, mapping interrupt causes to vectors
4768  * @param hw
4769  *  pointer to ixgbe_hw struct
4770  * @direction
4771  *  0 for Rx, 1 for Tx, -1 for other causes
4772  * @queue
4773  *  queue to map the corresponding interrupt to
4774  * @msix_vector
4775  *  the vector to map to the corresponding queue
4776  */
4777 static void
4778 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4779                    uint8_t queue, uint8_t msix_vector)
4780 {
4781         uint32_t tmp, idx;
4782
4783         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4784         if (hw->mac.type == ixgbe_mac_82598EB) {
4785                 if (direction == -1)
4786                         direction = 0;
4787                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4788                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4789                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4790                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4791                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4792         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4793                         (hw->mac.type == ixgbe_mac_X540)) {
4794                 if (direction == -1) {
4795                         /* other causes */
4796                         idx = ((queue & 1) * 8);
4797                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4798                         tmp &= ~(0xFF << idx);
4799                         tmp |= (msix_vector << idx);
4800                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4801                 } else {
4802                         /* rx or tx causes */
4803                         idx = ((16 * (queue & 1)) + (8 * direction));
4804                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4805                         tmp &= ~(0xFF << idx);
4806                         tmp |= (msix_vector << idx);
4807                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4808                 }
4809         }
4810 }
4811
4812 static void
4813 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4814 {
4815         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4816         struct ixgbe_hw *hw =
4817                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4818         uint32_t q_idx;
4819         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4820
4821         /* won't configure msix register if no mapping is done
4822          * between intr vector and event fd.
4823          */
4824         if (!rte_intr_dp_is_en(intr_handle))
4825                 return;
4826
4827         /* Configure all RX queues of VF */
4828         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4829                 /* Force all queue use vector 0,
4830                  * as IXGBE_VF_MAXMSIVECOTR = 1
4831                  */
4832                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4833                 intr_handle->intr_vec[q_idx] = vector_idx;
4834         }
4835
4836         /* Configure VF other cause ivar */
4837         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4838 }
4839
4840 /**
4841  * Sets up the hardware to properly generate MSI-X interrupts
4842  * @hw
4843  *  board private structure
4844  */
4845 static void
4846 ixgbe_configure_msix(struct rte_eth_dev *dev)
4847 {
4848         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4849         struct ixgbe_hw *hw =
4850                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4851         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4852         uint32_t vec = IXGBE_MISC_VEC_ID;
4853         uint32_t mask;
4854         uint32_t gpie;
4855
4856         /* won't configure msix register if no mapping is done
4857          * between intr vector and event fd
4858          */
4859         if (!rte_intr_dp_is_en(intr_handle))
4860                 return;
4861
4862         if (rte_intr_allow_others(intr_handle))
4863                 vec = base = IXGBE_RX_VEC_START;
4864
4865         /* setup GPIE for MSI-x mode */
4866         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4867         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4868                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4869         /* auto clearing and auto setting corresponding bits in EIMS
4870          * when MSI-X interrupt is triggered
4871          */
4872         if (hw->mac.type == ixgbe_mac_82598EB) {
4873                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4874         } else {
4875                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4876                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4877         }
4878         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4879
4880         /* Populate the IVAR table and set the ITR values to the
4881          * corresponding register.
4882          */
4883         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4884              queue_id++) {
4885                 /* by default, 1:1 mapping */
4886                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4887                 intr_handle->intr_vec[queue_id] = vec;
4888                 if (vec < base + intr_handle->nb_efd - 1)
4889                         vec++;
4890         }
4891
4892         switch (hw->mac.type) {
4893         case ixgbe_mac_82598EB:
4894                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4895                                    IXGBE_MISC_VEC_ID);
4896                 break;
4897         case ixgbe_mac_82599EB:
4898         case ixgbe_mac_X540:
4899                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4900                 break;
4901         default:
4902                 break;
4903         }
4904         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4905                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4906
4907         /* set up to autoclear timer, and the vectors */
4908         mask = IXGBE_EIMS_ENABLE_MASK;
4909         mask &= ~(IXGBE_EIMS_OTHER |
4910                   IXGBE_EIMS_MAILBOX |
4911                   IXGBE_EIMS_LSC);
4912
4913         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4914 }
4915
4916 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4917         uint16_t queue_idx, uint16_t tx_rate)
4918 {
4919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4920         uint32_t rf_dec, rf_int;
4921         uint32_t bcnrc_val;
4922         uint16_t link_speed = dev->data->dev_link.link_speed;
4923
4924         if (queue_idx >= hw->mac.max_tx_queues)
4925                 return -EINVAL;
4926
4927         if (tx_rate != 0) {
4928                 /* Calculate the rate factor values to set */
4929                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4930                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4931                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4932
4933                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4934                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4935                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4936                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4937         } else {
4938                 bcnrc_val = 0;
4939         }
4940
4941         /*
4942          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4943          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4944          * set as 0x4.
4945          */
4946         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4947                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4948                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4949                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4950                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4951         else
4952                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4953                         IXGBE_MMW_SIZE_DEFAULT);
4954
4955         /* Set RTTBCNRC of queue X */
4956         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4957         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4958         IXGBE_WRITE_FLUSH(hw);
4959
4960         return 0;
4961 }
4962
4963 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4964         uint16_t tx_rate, uint64_t q_msk)
4965 {
4966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4967         struct ixgbe_vf_info *vfinfo =
4968                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4969         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4970         uint32_t queue_stride =
4971                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4972         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4973         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4974         uint16_t total_rate = 0;
4975
4976         if (queue_end >= hw->mac.max_tx_queues)
4977                 return -EINVAL;
4978
4979         if (vfinfo != NULL) {
4980                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4981                         if (vf_idx == vf)
4982                                 continue;
4983                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4984                                 idx++)
4985                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4986                 }
4987         } else
4988                 return -EINVAL;
4989
4990         /* Store tx_rate for this vf. */
4991         for (idx = 0; idx < nb_q_per_pool; idx++) {
4992                 if (((uint64_t)0x1 << idx) & q_msk) {
4993                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4994                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4995                         total_rate += tx_rate;
4996                 }
4997         }
4998
4999         if (total_rate > dev->data->dev_link.link_speed) {
5000                 /*
5001                  * Reset stored TX rate of the VF if it causes exceed
5002                  * link speed.
5003                  */
5004                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5005                 return -EINVAL;
5006         }
5007
5008         /* Set RTTBCNRC of each queue/pool for vf X  */
5009         for (; queue_idx <= queue_end; queue_idx++) {
5010                 if (0x1 & q_msk)
5011                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5012                 q_msk = q_msk >> 1;
5013         }
5014
5015         return 0;
5016 }
5017
5018 static void
5019 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5020                      __attribute__((unused)) uint32_t index,
5021                      __attribute__((unused)) uint32_t pool)
5022 {
5023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5024         int diag;
5025
5026         /*
5027          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5028          * operation. Trap this case to avoid exhausting the [very limited]
5029          * set of PF resources used to store VF MAC addresses.
5030          */
5031         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5032                 return;
5033         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5034         if (diag == 0)
5035                 return;
5036         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5037 }
5038
5039 static void
5040 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5041 {
5042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5043         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5044         struct ether_addr *mac_addr;
5045         uint32_t i;
5046         int diag;
5047
5048         /*
5049          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5050          * not support the deletion of a given MAC address.
5051          * Instead, it imposes to delete all MAC addresses, then to add again
5052          * all MAC addresses with the exception of the one to be deleted.
5053          */
5054         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5055
5056         /*
5057          * Add again all MAC addresses, with the exception of the deleted one
5058          * and of the permanent MAC address.
5059          */
5060         for (i = 0, mac_addr = dev->data->mac_addrs;
5061              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5062                 /* Skip the deleted MAC address */
5063                 if (i == index)
5064                         continue;
5065                 /* Skip NULL MAC addresses */
5066                 if (is_zero_ether_addr(mac_addr))
5067                         continue;
5068                 /* Skip the permanent MAC address */
5069                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5070                         continue;
5071                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5072                 if (diag != 0)
5073                         PMD_DRV_LOG(ERR,
5074                                     "Adding again MAC address "
5075                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5076                                     "diag=%d",
5077                                     mac_addr->addr_bytes[0],
5078                                     mac_addr->addr_bytes[1],
5079                                     mac_addr->addr_bytes[2],
5080                                     mac_addr->addr_bytes[3],
5081                                     mac_addr->addr_bytes[4],
5082                                     mac_addr->addr_bytes[5],
5083                                     diag);
5084         }
5085 }
5086
5087 static void
5088 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5089 {
5090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5091
5092         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5093 }
5094
5095 #define MAC_TYPE_FILTER_SUP(type)    do {\
5096         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5097                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5098                 (type) != ixgbe_mac_X550EM_a)\
5099                 return -ENOTSUP;\
5100 } while (0)
5101
5102 static int
5103 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5104                         struct rte_eth_syn_filter *filter,
5105                         bool add)
5106 {
5107         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5108         uint32_t synqf;
5109
5110         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5111                 return -EINVAL;
5112
5113         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5114
5115         if (add) {
5116                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5117                         return -EINVAL;
5118                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5119                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5120
5121                 if (filter->hig_pri)
5122                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5123                 else
5124                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5125         } else {
5126                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5127                         return -ENOENT;
5128                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5129         }
5130         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5131         IXGBE_WRITE_FLUSH(hw);
5132         return 0;
5133 }
5134
5135 static int
5136 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5137                         struct rte_eth_syn_filter *filter)
5138 {
5139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5140         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5141
5142         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5143                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5144                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5145                 return 0;
5146         }
5147         return -ENOENT;
5148 }
5149
5150 static int
5151 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5152                         enum rte_filter_op filter_op,
5153                         void *arg)
5154 {
5155         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5156         int ret;
5157
5158         MAC_TYPE_FILTER_SUP(hw->mac.type);
5159
5160         if (filter_op == RTE_ETH_FILTER_NOP)
5161                 return 0;
5162
5163         if (arg == NULL) {
5164                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5165                             filter_op);
5166                 return -EINVAL;
5167         }
5168
5169         switch (filter_op) {
5170         case RTE_ETH_FILTER_ADD:
5171                 ret = ixgbe_syn_filter_set(dev,
5172                                 (struct rte_eth_syn_filter *)arg,
5173                                 TRUE);
5174                 break;
5175         case RTE_ETH_FILTER_DELETE:
5176                 ret = ixgbe_syn_filter_set(dev,
5177                                 (struct rte_eth_syn_filter *)arg,
5178                                 FALSE);
5179                 break;
5180         case RTE_ETH_FILTER_GET:
5181                 ret = ixgbe_syn_filter_get(dev,
5182                                 (struct rte_eth_syn_filter *)arg);
5183                 break;
5184         default:
5185                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5186                 ret = -EINVAL;
5187                 break;
5188         }
5189
5190         return ret;
5191 }
5192
5193
5194 static inline enum ixgbe_5tuple_protocol
5195 convert_protocol_type(uint8_t protocol_value)
5196 {
5197         if (protocol_value == IPPROTO_TCP)
5198                 return IXGBE_FILTER_PROTOCOL_TCP;
5199         else if (protocol_value == IPPROTO_UDP)
5200                 return IXGBE_FILTER_PROTOCOL_UDP;
5201         else if (protocol_value == IPPROTO_SCTP)
5202                 return IXGBE_FILTER_PROTOCOL_SCTP;
5203         else
5204                 return IXGBE_FILTER_PROTOCOL_NONE;
5205 }
5206
5207 /*
5208  * add a 5tuple filter
5209  *
5210  * @param
5211  * dev: Pointer to struct rte_eth_dev.
5212  * index: the index the filter allocates.
5213  * filter: ponter to the filter that will be added.
5214  * rx_queue: the queue id the filter assigned to.
5215  *
5216  * @return
5217  *    - On success, zero.
5218  *    - On failure, a negative value.
5219  */
5220 static int
5221 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5222                         struct ixgbe_5tuple_filter *filter)
5223 {
5224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225         struct ixgbe_filter_info *filter_info =
5226                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5227         int i, idx, shift;
5228         uint32_t ftqf, sdpqf;
5229         uint32_t l34timir = 0;
5230         uint8_t mask = 0xff;
5231
5232         /*
5233          * look for an unused 5tuple filter index,
5234          * and insert the filter to list.
5235          */
5236         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5237                 idx = i / (sizeof(uint32_t) * NBBY);
5238                 shift = i % (sizeof(uint32_t) * NBBY);
5239                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5240                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5241                         filter->index = i;
5242                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5243                                           filter,
5244                                           entries);
5245                         break;
5246                 }
5247         }
5248         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5249                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5250                 return -ENOSYS;
5251         }
5252
5253         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5254                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5255         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5256
5257         ftqf = (uint32_t)(filter->filter_info.proto &
5258                 IXGBE_FTQF_PROTOCOL_MASK);
5259         ftqf |= (uint32_t)((filter->filter_info.priority &
5260                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5261         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5262                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5263         if (filter->filter_info.dst_ip_mask == 0)
5264                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5265         if (filter->filter_info.src_port_mask == 0)
5266                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5267         if (filter->filter_info.dst_port_mask == 0)
5268                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5269         if (filter->filter_info.proto_mask == 0)
5270                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5271         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5272         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5273         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5274
5275         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5276         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5277         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5278         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5279
5280         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5281         l34timir |= (uint32_t)(filter->queue <<
5282                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5283         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5284         return 0;
5285 }
5286
5287 /*
5288  * remove a 5tuple filter
5289  *
5290  * @param
5291  * dev: Pointer to struct rte_eth_dev.
5292  * filter: the pointer of the filter will be removed.
5293  */
5294 static void
5295 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5296                         struct ixgbe_5tuple_filter *filter)
5297 {
5298         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5299         struct ixgbe_filter_info *filter_info =
5300                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5301         uint16_t index = filter->index;
5302
5303         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5304                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5305         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5306         rte_free(filter);
5307
5308         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5309         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5310         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5311         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5312         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5313 }
5314
5315 static int
5316 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5317 {
5318         struct ixgbe_hw *hw;
5319         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5320
5321         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5322
5323         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5324                 return -EINVAL;
5325
5326         /* refuse mtu that requires the support of scattered packets when this
5327          * feature has not been enabled before.
5328          */
5329         if (!dev->data->scattered_rx &&
5330             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5331              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5332                 return -EINVAL;
5333
5334         /*
5335          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5336          * request of the version 2.0 of the mailbox API.
5337          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5338          * of the mailbox API.
5339          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5340          * prior to 3.11.33 which contains the following change:
5341          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5342          */
5343         ixgbevf_rlpml_set_vf(hw, max_frame);
5344
5345         /* update max frame size */
5346         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5347         return 0;
5348 }
5349
5350 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5351         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5352                 return -ENOTSUP;\
5353 } while (0)
5354
5355 static inline struct ixgbe_5tuple_filter *
5356 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5357                         struct ixgbe_5tuple_filter_info *key)
5358 {
5359         struct ixgbe_5tuple_filter *it;
5360
5361         TAILQ_FOREACH(it, filter_list, entries) {
5362                 if (memcmp(key, &it->filter_info,
5363                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5364                         return it;
5365                 }
5366         }
5367         return NULL;
5368 }
5369
5370 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5371 static inline int
5372 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5373                         struct ixgbe_5tuple_filter_info *filter_info)
5374 {
5375         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5376                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5377                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5378                 return -EINVAL;
5379
5380         switch (filter->dst_ip_mask) {
5381         case UINT32_MAX:
5382                 filter_info->dst_ip_mask = 0;
5383                 filter_info->dst_ip = filter->dst_ip;
5384                 break;
5385         case 0:
5386                 filter_info->dst_ip_mask = 1;
5387                 break;
5388         default:
5389                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5390                 return -EINVAL;
5391         }
5392
5393         switch (filter->src_ip_mask) {
5394         case UINT32_MAX:
5395                 filter_info->src_ip_mask = 0;
5396                 filter_info->src_ip = filter->src_ip;
5397                 break;
5398         case 0:
5399                 filter_info->src_ip_mask = 1;
5400                 break;
5401         default:
5402                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5403                 return -EINVAL;
5404         }
5405
5406         switch (filter->dst_port_mask) {
5407         case UINT16_MAX:
5408                 filter_info->dst_port_mask = 0;
5409                 filter_info->dst_port = filter->dst_port;
5410                 break;
5411         case 0:
5412                 filter_info->dst_port_mask = 1;
5413                 break;
5414         default:
5415                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5416                 return -EINVAL;
5417         }
5418
5419         switch (filter->src_port_mask) {
5420         case UINT16_MAX:
5421                 filter_info->src_port_mask = 0;
5422                 filter_info->src_port = filter->src_port;
5423                 break;
5424         case 0:
5425                 filter_info->src_port_mask = 1;
5426                 break;
5427         default:
5428                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5429                 return -EINVAL;
5430         }
5431
5432         switch (filter->proto_mask) {
5433         case UINT8_MAX:
5434                 filter_info->proto_mask = 0;
5435                 filter_info->proto =
5436                         convert_protocol_type(filter->proto);
5437                 break;
5438         case 0:
5439                 filter_info->proto_mask = 1;
5440                 break;
5441         default:
5442                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5443                 return -EINVAL;
5444         }
5445
5446         filter_info->priority = (uint8_t)filter->priority;
5447         return 0;
5448 }
5449
5450 /*
5451  * add or delete a ntuple filter
5452  *
5453  * @param
5454  * dev: Pointer to struct rte_eth_dev.
5455  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5456  * add: if true, add filter, if false, remove filter
5457  *
5458  * @return
5459  *    - On success, zero.
5460  *    - On failure, a negative value.
5461  */
5462 static int
5463 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5464                         struct rte_eth_ntuple_filter *ntuple_filter,
5465                         bool add)
5466 {
5467         struct ixgbe_filter_info *filter_info =
5468                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5469         struct ixgbe_5tuple_filter_info filter_5tuple;
5470         struct ixgbe_5tuple_filter *filter;
5471         int ret;
5472
5473         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5474                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5475                 return -EINVAL;
5476         }
5477
5478         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5479         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5480         if (ret < 0)
5481                 return ret;
5482
5483         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5484                                          &filter_5tuple);
5485         if (filter != NULL && add) {
5486                 PMD_DRV_LOG(ERR, "filter exists.");
5487                 return -EEXIST;
5488         }
5489         if (filter == NULL && !add) {
5490                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5491                 return -ENOENT;
5492         }
5493
5494         if (add) {
5495                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5496                                 sizeof(struct ixgbe_5tuple_filter), 0);
5497                 if (filter == NULL)
5498                         return -ENOMEM;
5499                 (void)rte_memcpy(&filter->filter_info,
5500                                  &filter_5tuple,
5501                                  sizeof(struct ixgbe_5tuple_filter_info));
5502                 filter->queue = ntuple_filter->queue;
5503                 ret = ixgbe_add_5tuple_filter(dev, filter);
5504                 if (ret < 0) {
5505                         rte_free(filter);
5506                         return ret;
5507                 }
5508         } else
5509                 ixgbe_remove_5tuple_filter(dev, filter);
5510
5511         return 0;
5512 }
5513
5514 /*
5515  * get a ntuple filter
5516  *
5517  * @param
5518  * dev: Pointer to struct rte_eth_dev.
5519  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5520  *
5521  * @return
5522  *    - On success, zero.
5523  *    - On failure, a negative value.
5524  */
5525 static int
5526 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5527                         struct rte_eth_ntuple_filter *ntuple_filter)
5528 {
5529         struct ixgbe_filter_info *filter_info =
5530                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5531         struct ixgbe_5tuple_filter_info filter_5tuple;
5532         struct ixgbe_5tuple_filter *filter;
5533         int ret;
5534
5535         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5536                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5537                 return -EINVAL;
5538         }
5539
5540         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5541         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5542         if (ret < 0)
5543                 return ret;
5544
5545         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5546                                          &filter_5tuple);
5547         if (filter == NULL) {
5548                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5549                 return -ENOENT;
5550         }
5551         ntuple_filter->queue = filter->queue;
5552         return 0;
5553 }
5554
5555 /*
5556  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5557  * @dev: pointer to rte_eth_dev structure
5558  * @filter_op:operation will be taken.
5559  * @arg: a pointer to specific structure corresponding to the filter_op
5560  *
5561  * @return
5562  *    - On success, zero.
5563  *    - On failure, a negative value.
5564  */
5565 static int
5566 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5567                                 enum rte_filter_op filter_op,
5568                                 void *arg)
5569 {
5570         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5571         int ret;
5572
5573         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5574
5575         if (filter_op == RTE_ETH_FILTER_NOP)
5576                 return 0;
5577
5578         if (arg == NULL) {
5579                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5580                             filter_op);
5581                 return -EINVAL;
5582         }
5583
5584         switch (filter_op) {
5585         case RTE_ETH_FILTER_ADD:
5586                 ret = ixgbe_add_del_ntuple_filter(dev,
5587                         (struct rte_eth_ntuple_filter *)arg,
5588                         TRUE);
5589                 break;
5590         case RTE_ETH_FILTER_DELETE:
5591                 ret = ixgbe_add_del_ntuple_filter(dev,
5592                         (struct rte_eth_ntuple_filter *)arg,
5593                         FALSE);
5594                 break;
5595         case RTE_ETH_FILTER_GET:
5596                 ret = ixgbe_get_ntuple_filter(dev,
5597                         (struct rte_eth_ntuple_filter *)arg);
5598                 break;
5599         default:
5600                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5601                 ret = -EINVAL;
5602                 break;
5603         }
5604         return ret;
5605 }
5606
5607 static inline int
5608 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5609                         uint16_t ethertype)
5610 {
5611         int i;
5612
5613         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5614                 if (filter_info->ethertype_filters[i] == ethertype &&
5615                     (filter_info->ethertype_mask & (1 << i)))
5616                         return i;
5617         }
5618         return -1;
5619 }
5620
5621 static inline int
5622 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5623                         uint16_t ethertype)
5624 {
5625         int i;
5626
5627         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5628                 if (!(filter_info->ethertype_mask & (1 << i))) {
5629                         filter_info->ethertype_mask |= 1 << i;
5630                         filter_info->ethertype_filters[i] = ethertype;
5631                         return i;
5632                 }
5633         }
5634         return -1;
5635 }
5636
5637 static inline int
5638 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5639                         uint8_t idx)
5640 {
5641         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5642                 return -1;
5643         filter_info->ethertype_mask &= ~(1 << idx);
5644         filter_info->ethertype_filters[idx] = 0;
5645         return idx;
5646 }
5647
5648 static int
5649 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5650                         struct rte_eth_ethertype_filter *filter,
5651                         bool add)
5652 {
5653         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5654         struct ixgbe_filter_info *filter_info =
5655                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5656         uint32_t etqf = 0;
5657         uint32_t etqs = 0;
5658         int ret;
5659
5660         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5661                 return -EINVAL;
5662
5663         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5664                 filter->ether_type == ETHER_TYPE_IPv6) {
5665                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5666                         " ethertype filter.", filter->ether_type);
5667                 return -EINVAL;
5668         }
5669
5670         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5671                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5672                 return -EINVAL;
5673         }
5674         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5675                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5676                 return -EINVAL;
5677         }
5678
5679         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5680         if (ret >= 0 && add) {
5681                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5682                             filter->ether_type);
5683                 return -EEXIST;
5684         }
5685         if (ret < 0 && !add) {
5686                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5687                             filter->ether_type);
5688                 return -ENOENT;
5689         }
5690
5691         if (add) {
5692                 ret = ixgbe_ethertype_filter_insert(filter_info,
5693                         filter->ether_type);
5694                 if (ret < 0) {
5695                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5696                         return -ENOSYS;
5697                 }
5698                 etqf = IXGBE_ETQF_FILTER_EN;
5699                 etqf |= (uint32_t)filter->ether_type;
5700                 etqs |= (uint32_t)((filter->queue <<
5701                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5702                                     IXGBE_ETQS_RX_QUEUE);
5703                 etqs |= IXGBE_ETQS_QUEUE_EN;
5704         } else {
5705                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5706                 if (ret < 0)
5707                         return -ENOSYS;
5708         }
5709         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5710         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5711         IXGBE_WRITE_FLUSH(hw);
5712
5713         return 0;
5714 }
5715
5716 static int
5717 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5718                         struct rte_eth_ethertype_filter *filter)
5719 {
5720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5721         struct ixgbe_filter_info *filter_info =
5722                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5723         uint32_t etqf, etqs;
5724         int ret;
5725
5726         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5727         if (ret < 0) {
5728                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5729                             filter->ether_type);
5730                 return -ENOENT;
5731         }
5732
5733         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5734         if (etqf & IXGBE_ETQF_FILTER_EN) {
5735                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5736                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5737                 filter->flags = 0;
5738                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5739                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5740                 return 0;
5741         }
5742         return -ENOENT;
5743 }
5744
5745 /*
5746  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5747  * @dev: pointer to rte_eth_dev structure
5748  * @filter_op:operation will be taken.
5749  * @arg: a pointer to specific structure corresponding to the filter_op
5750  */
5751 static int
5752 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5753                                 enum rte_filter_op filter_op,
5754                                 void *arg)
5755 {
5756         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5757         int ret;
5758
5759         MAC_TYPE_FILTER_SUP(hw->mac.type);
5760
5761         if (filter_op == RTE_ETH_FILTER_NOP)
5762                 return 0;
5763
5764         if (arg == NULL) {
5765                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5766                             filter_op);
5767                 return -EINVAL;
5768         }
5769
5770         switch (filter_op) {
5771         case RTE_ETH_FILTER_ADD:
5772                 ret = ixgbe_add_del_ethertype_filter(dev,
5773                         (struct rte_eth_ethertype_filter *)arg,
5774                         TRUE);
5775                 break;
5776         case RTE_ETH_FILTER_DELETE:
5777                 ret = ixgbe_add_del_ethertype_filter(dev,
5778                         (struct rte_eth_ethertype_filter *)arg,
5779                         FALSE);
5780                 break;
5781         case RTE_ETH_FILTER_GET:
5782                 ret = ixgbe_get_ethertype_filter(dev,
5783                         (struct rte_eth_ethertype_filter *)arg);
5784                 break;
5785         default:
5786                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5787                 ret = -EINVAL;
5788                 break;
5789         }
5790         return ret;
5791 }
5792
5793 static int
5794 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5795                      enum rte_filter_type filter_type,
5796                      enum rte_filter_op filter_op,
5797                      void *arg)
5798 {
5799         int ret = -EINVAL;
5800
5801         switch (filter_type) {
5802         case RTE_ETH_FILTER_NTUPLE:
5803                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5804                 break;
5805         case RTE_ETH_FILTER_ETHERTYPE:
5806                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5807                 break;
5808         case RTE_ETH_FILTER_SYN:
5809                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5810                 break;
5811         case RTE_ETH_FILTER_FDIR:
5812                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5813                 break;
5814         case RTE_ETH_FILTER_L2_TUNNEL:
5815                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5816                 break;
5817         default:
5818                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5819                                                         filter_type);
5820                 break;
5821         }
5822
5823         return ret;
5824 }
5825
5826 static u8 *
5827 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5828                         u8 **mc_addr_ptr, u32 *vmdq)
5829 {
5830         u8 *mc_addr;
5831
5832         *vmdq = 0;
5833         mc_addr = *mc_addr_ptr;
5834         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5835         return mc_addr;
5836 }
5837
5838 static int
5839 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5840                           struct ether_addr *mc_addr_set,
5841                           uint32_t nb_mc_addr)
5842 {
5843         struct ixgbe_hw *hw;
5844         u8 *mc_addr_list;
5845
5846         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5847         mc_addr_list = (u8 *)mc_addr_set;
5848         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5849                                          ixgbe_dev_addr_list_itr, TRUE);
5850 }
5851
5852 static uint64_t
5853 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5854 {
5855         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5856         uint64_t systime_cycles;
5857
5858         switch (hw->mac.type) {
5859         case ixgbe_mac_X550:
5860         case ixgbe_mac_X550EM_x:
5861         case ixgbe_mac_X550EM_a:
5862                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5863                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5864                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5865                                 * NSEC_PER_SEC;
5866                 break;
5867         default:
5868                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5869                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5870                                 << 32;
5871         }
5872
5873         return systime_cycles;
5874 }
5875
5876 static uint64_t
5877 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5878 {
5879         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5880         uint64_t rx_tstamp_cycles;
5881
5882         switch (hw->mac.type) {
5883         case ixgbe_mac_X550:
5884         case ixgbe_mac_X550EM_x:
5885         case ixgbe_mac_X550EM_a:
5886                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5887                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5888                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5889                                 * NSEC_PER_SEC;
5890                 break;
5891         default:
5892                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5893                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5894                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5895                                 << 32;
5896         }
5897
5898         return rx_tstamp_cycles;
5899 }
5900
5901 static uint64_t
5902 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5903 {
5904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5905         uint64_t tx_tstamp_cycles;
5906
5907         switch (hw->mac.type) {
5908         case ixgbe_mac_X550:
5909         case ixgbe_mac_X550EM_x:
5910         case ixgbe_mac_X550EM_a:
5911                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5912                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5913                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5914                                 * NSEC_PER_SEC;
5915                 break;
5916         default:
5917                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5918                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5919                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5920                                 << 32;
5921         }
5922
5923         return tx_tstamp_cycles;
5924 }
5925
5926 static void
5927 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5928 {
5929         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5930         struct ixgbe_adapter *adapter =
5931                 (struct ixgbe_adapter *)dev->data->dev_private;
5932         struct rte_eth_link link;
5933         uint32_t incval = 0;
5934         uint32_t shift = 0;
5935
5936         /* Get current link speed. */
5937         memset(&link, 0, sizeof(link));
5938         ixgbe_dev_link_update(dev, 1);
5939         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5940
5941         switch (link.link_speed) {
5942         case ETH_SPEED_NUM_100M:
5943                 incval = IXGBE_INCVAL_100;
5944                 shift = IXGBE_INCVAL_SHIFT_100;
5945                 break;
5946         case ETH_SPEED_NUM_1G:
5947                 incval = IXGBE_INCVAL_1GB;
5948                 shift = IXGBE_INCVAL_SHIFT_1GB;
5949                 break;
5950         case ETH_SPEED_NUM_10G:
5951         default:
5952                 incval = IXGBE_INCVAL_10GB;
5953                 shift = IXGBE_INCVAL_SHIFT_10GB;
5954                 break;
5955         }
5956
5957         switch (hw->mac.type) {
5958         case ixgbe_mac_X550:
5959         case ixgbe_mac_X550EM_x:
5960         case ixgbe_mac_X550EM_a:
5961                 /* Independent of link speed. */
5962                 incval = 1;
5963                 /* Cycles read will be interpreted as ns. */
5964                 shift = 0;
5965                 /* Fall-through */
5966         case ixgbe_mac_X540:
5967                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5968                 break;
5969         case ixgbe_mac_82599EB:
5970                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5971                 shift -= IXGBE_INCVAL_SHIFT_82599;
5972                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5973                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5974                 break;
5975         default:
5976                 /* Not supported. */
5977                 return;
5978         }
5979
5980         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5981         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5982         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5983
5984         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5985         adapter->systime_tc.cc_shift = shift;
5986         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5987
5988         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5989         adapter->rx_tstamp_tc.cc_shift = shift;
5990         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5991
5992         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5993         adapter->tx_tstamp_tc.cc_shift = shift;
5994         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5995 }
5996
5997 static int
5998 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5999 {
6000         struct ixgbe_adapter *adapter =
6001                         (struct ixgbe_adapter *)dev->data->dev_private;
6002
6003         adapter->systime_tc.nsec += delta;
6004         adapter->rx_tstamp_tc.nsec += delta;
6005         adapter->tx_tstamp_tc.nsec += delta;
6006
6007         return 0;
6008 }
6009
6010 static int
6011 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6012 {
6013         uint64_t ns;
6014         struct ixgbe_adapter *adapter =
6015                         (struct ixgbe_adapter *)dev->data->dev_private;
6016
6017         ns = rte_timespec_to_ns(ts);
6018         /* Set the timecounters to a new value. */
6019         adapter->systime_tc.nsec = ns;
6020         adapter->rx_tstamp_tc.nsec = ns;
6021         adapter->tx_tstamp_tc.nsec = ns;
6022
6023         return 0;
6024 }
6025
6026 static int
6027 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6028 {
6029         uint64_t ns, systime_cycles;
6030         struct ixgbe_adapter *adapter =
6031                         (struct ixgbe_adapter *)dev->data->dev_private;
6032
6033         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6034         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6035         *ts = rte_ns_to_timespec(ns);
6036
6037         return 0;
6038 }
6039
6040 static int
6041 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6042 {
6043         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6044         uint32_t tsync_ctl;
6045         uint32_t tsauxc;
6046
6047         /* Stop the timesync system time. */
6048         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6049         /* Reset the timesync system time value. */
6050         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6051         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6052
6053         /* Enable system time for platforms where it isn't on by default. */
6054         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6055         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6056         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6057
6058         ixgbe_start_timecounters(dev);
6059
6060         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6061         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6062                         (ETHER_TYPE_1588 |
6063                          IXGBE_ETQF_FILTER_EN |
6064                          IXGBE_ETQF_1588));
6065
6066         /* Enable timestamping of received PTP packets. */
6067         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6068         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6069         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6070
6071         /* Enable timestamping of transmitted PTP packets. */
6072         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6073         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6074         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6075
6076         IXGBE_WRITE_FLUSH(hw);
6077
6078         return 0;
6079 }
6080
6081 static int
6082 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6083 {
6084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6085         uint32_t tsync_ctl;
6086
6087         /* Disable timestamping of transmitted PTP packets. */
6088         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6089         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6090         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6091
6092         /* Disable timestamping of received PTP packets. */
6093         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6094         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6095         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6096
6097         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6098         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6099
6100         /* Stop incrementating the System Time registers. */
6101         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6102
6103         return 0;
6104 }
6105
6106 static int
6107 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6108                                  struct timespec *timestamp,
6109                                  uint32_t flags __rte_unused)
6110 {
6111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6112         struct ixgbe_adapter *adapter =
6113                 (struct ixgbe_adapter *)dev->data->dev_private;
6114         uint32_t tsync_rxctl;
6115         uint64_t rx_tstamp_cycles;
6116         uint64_t ns;
6117
6118         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6119         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6120                 return -EINVAL;
6121
6122         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6123         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6124         *timestamp = rte_ns_to_timespec(ns);
6125
6126         return  0;
6127 }
6128
6129 static int
6130 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6131                                  struct timespec *timestamp)
6132 {
6133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6134         struct ixgbe_adapter *adapter =
6135                 (struct ixgbe_adapter *)dev->data->dev_private;
6136         uint32_t tsync_txctl;
6137         uint64_t tx_tstamp_cycles;
6138         uint64_t ns;
6139
6140         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6141         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6142                 return -EINVAL;
6143
6144         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6145         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6146         *timestamp = rte_ns_to_timespec(ns);
6147
6148         return 0;
6149 }
6150
6151 static int
6152 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6153 {
6154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6155         int count = 0;
6156         int g_ind = 0;
6157         const struct reg_info *reg_group;
6158         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6159                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6160
6161         while ((reg_group = reg_set[g_ind++]))
6162                 count += ixgbe_regs_group_count(reg_group);
6163
6164         return count;
6165 }
6166
6167 static int
6168 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6169 {
6170         int count = 0;
6171         int g_ind = 0;
6172         const struct reg_info *reg_group;
6173
6174         while ((reg_group = ixgbevf_regs[g_ind++]))
6175                 count += ixgbe_regs_group_count(reg_group);
6176
6177         return count;
6178 }
6179
6180 static int
6181 ixgbe_get_regs(struct rte_eth_dev *dev,
6182               struct rte_dev_reg_info *regs)
6183 {
6184         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6185         uint32_t *data = regs->data;
6186         int g_ind = 0;
6187         int count = 0;
6188         const struct reg_info *reg_group;
6189         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6190                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6191
6192         /* Support only full register dump */
6193         if ((regs->length == 0) ||
6194             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6195                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6196                         hw->device_id;
6197                 while ((reg_group = reg_set[g_ind++]))
6198                         count += ixgbe_read_regs_group(dev, &data[count],
6199                                 reg_group);
6200                 return 0;
6201         }
6202
6203         return -ENOTSUP;
6204 }
6205
6206 static int
6207 ixgbevf_get_regs(struct rte_eth_dev *dev,
6208                 struct rte_dev_reg_info *regs)
6209 {
6210         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6211         uint32_t *data = regs->data;
6212         int g_ind = 0;
6213         int count = 0;
6214         const struct reg_info *reg_group;
6215
6216         /* Support only full register dump */
6217         if ((regs->length == 0) ||
6218             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6219                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6220                         hw->device_id;
6221                 while ((reg_group = ixgbevf_regs[g_ind++]))
6222                         count += ixgbe_read_regs_group(dev, &data[count],
6223                                                       reg_group);
6224                 return 0;
6225         }
6226
6227         return -ENOTSUP;
6228 }
6229
6230 static int
6231 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6232 {
6233         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6234
6235         /* Return unit is byte count */
6236         return hw->eeprom.word_size * 2;
6237 }
6238
6239 static int
6240 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6241                 struct rte_dev_eeprom_info *in_eeprom)
6242 {
6243         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6244         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6245         uint16_t *data = in_eeprom->data;
6246         int first, length;
6247
6248         first = in_eeprom->offset >> 1;
6249         length = in_eeprom->length >> 1;
6250         if ((first > hw->eeprom.word_size) ||
6251             ((first + length) > hw->eeprom.word_size))
6252                 return -EINVAL;
6253
6254         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6255
6256         return eeprom->ops.read_buffer(hw, first, length, data);
6257 }
6258
6259 static int
6260 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6261                 struct rte_dev_eeprom_info *in_eeprom)
6262 {
6263         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6264         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6265         uint16_t *data = in_eeprom->data;
6266         int first, length;
6267
6268         first = in_eeprom->offset >> 1;
6269         length = in_eeprom->length >> 1;
6270         if ((first > hw->eeprom.word_size) ||
6271             ((first + length) > hw->eeprom.word_size))
6272                 return -EINVAL;
6273
6274         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6275
6276         return eeprom->ops.write_buffer(hw,  first, length, data);
6277 }
6278
6279 uint16_t
6280 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6281         switch (mac_type) {
6282         case ixgbe_mac_X550:
6283         case ixgbe_mac_X550EM_x:
6284         case ixgbe_mac_X550EM_a:
6285                 return ETH_RSS_RETA_SIZE_512;
6286         case ixgbe_mac_X550_vf:
6287         case ixgbe_mac_X550EM_x_vf:
6288         case ixgbe_mac_X550EM_a_vf:
6289                 return ETH_RSS_RETA_SIZE_64;
6290         default:
6291                 return ETH_RSS_RETA_SIZE_128;
6292         }
6293 }
6294
6295 uint32_t
6296 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6297         switch (mac_type) {
6298         case ixgbe_mac_X550:
6299         case ixgbe_mac_X550EM_x:
6300         case ixgbe_mac_X550EM_a:
6301                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6302                         return IXGBE_RETA(reta_idx >> 2);
6303                 else
6304                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6305         case ixgbe_mac_X550_vf:
6306         case ixgbe_mac_X550EM_x_vf:
6307         case ixgbe_mac_X550EM_a_vf:
6308                 return IXGBE_VFRETA(reta_idx >> 2);
6309         default:
6310                 return IXGBE_RETA(reta_idx >> 2);
6311         }
6312 }
6313
6314 uint32_t
6315 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6316         switch (mac_type) {
6317         case ixgbe_mac_X550_vf:
6318         case ixgbe_mac_X550EM_x_vf:
6319         case ixgbe_mac_X550EM_a_vf:
6320                 return IXGBE_VFMRQC;
6321         default:
6322                 return IXGBE_MRQC;
6323         }
6324 }
6325
6326 uint32_t
6327 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6328         switch (mac_type) {
6329         case ixgbe_mac_X550_vf:
6330         case ixgbe_mac_X550EM_x_vf:
6331         case ixgbe_mac_X550EM_a_vf:
6332                 return IXGBE_VFRSSRK(i);
6333         default:
6334                 return IXGBE_RSSRK(i);
6335         }
6336 }
6337
6338 bool
6339 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6340         switch (mac_type) {
6341         case ixgbe_mac_82599_vf:
6342         case ixgbe_mac_X540_vf:
6343                 return 0;
6344         default:
6345                 return 1;
6346         }
6347 }
6348
6349 static int
6350 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6351                         struct rte_eth_dcb_info *dcb_info)
6352 {
6353         struct ixgbe_dcb_config *dcb_config =
6354                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6355         struct ixgbe_dcb_tc_config *tc;
6356         uint8_t i, j;
6357
6358         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6359                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6360         else
6361                 dcb_info->nb_tcs = 1;
6362
6363         if (dcb_config->vt_mode) { /* vt is enabled*/
6364                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6365                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6366                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6367                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6368                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6369                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6370                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6371                                                 i * dcb_info->nb_tcs + j;
6372                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6373                                 dcb_info->tc_queue.tc_txq[i][j].base =
6374                                                 i * dcb_info->nb_tcs + j;
6375                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6376                         }
6377                 }
6378         } else { /* vt is disabled*/
6379                 struct rte_eth_dcb_rx_conf *rx_conf =
6380                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6381                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6382                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6383                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6384                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6385                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6386                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6387                         }
6388                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6389                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6390                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6391                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6392                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6393                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6394                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6395                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6396                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6397                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6398                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6399                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6400                         }
6401                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6402                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6403                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6404                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6405                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6406                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6407                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6408                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6409                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6410                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6411                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6412                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6413                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6414                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6415                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6416                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6417                 }
6418         }
6419         for (i = 0; i < dcb_info->nb_tcs; i++) {
6420                 tc = &dcb_config->tc_config[i];
6421                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6422         }
6423         return 0;
6424 }
6425
6426 /* Update e-tag ether type */
6427 static int
6428 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6429                             uint16_t ether_type)
6430 {
6431         uint32_t etag_etype;
6432
6433         if (hw->mac.type != ixgbe_mac_X550 &&
6434             hw->mac.type != ixgbe_mac_X550EM_x &&
6435             hw->mac.type != ixgbe_mac_X550EM_a) {
6436                 return -ENOTSUP;
6437         }
6438
6439         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6440         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6441         etag_etype |= ether_type;
6442         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6443         IXGBE_WRITE_FLUSH(hw);
6444
6445         return 0;
6446 }
6447
6448 /* Config l2 tunnel ether type */
6449 static int
6450 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6451                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6452 {
6453         int ret = 0;
6454         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6455
6456         if (l2_tunnel == NULL)
6457                 return -EINVAL;
6458
6459         switch (l2_tunnel->l2_tunnel_type) {
6460         case RTE_L2_TUNNEL_TYPE_E_TAG:
6461                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6462                 break;
6463         default:
6464                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6465                 ret = -EINVAL;
6466                 break;
6467         }
6468
6469         return ret;
6470 }
6471
6472 /* Enable e-tag tunnel */
6473 static int
6474 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6475 {
6476         uint32_t etag_etype;
6477
6478         if (hw->mac.type != ixgbe_mac_X550 &&
6479             hw->mac.type != ixgbe_mac_X550EM_x &&
6480             hw->mac.type != ixgbe_mac_X550EM_a) {
6481                 return -ENOTSUP;
6482         }
6483
6484         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6485         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6486         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6487         IXGBE_WRITE_FLUSH(hw);
6488
6489         return 0;
6490 }
6491
6492 /* Enable l2 tunnel */
6493 static int
6494 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6495                            enum rte_eth_tunnel_type l2_tunnel_type)
6496 {
6497         int ret = 0;
6498         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6499
6500         switch (l2_tunnel_type) {
6501         case RTE_L2_TUNNEL_TYPE_E_TAG:
6502                 ret = ixgbe_e_tag_enable(hw);
6503                 break;
6504         default:
6505                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6506                 ret = -EINVAL;
6507                 break;
6508         }
6509
6510         return ret;
6511 }
6512
6513 /* Disable e-tag tunnel */
6514 static int
6515 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6516 {
6517         uint32_t etag_etype;
6518
6519         if (hw->mac.type != ixgbe_mac_X550 &&
6520             hw->mac.type != ixgbe_mac_X550EM_x &&
6521             hw->mac.type != ixgbe_mac_X550EM_a) {
6522                 return -ENOTSUP;
6523         }
6524
6525         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6526         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6527         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6528         IXGBE_WRITE_FLUSH(hw);
6529
6530         return 0;
6531 }
6532
6533 /* Disable l2 tunnel */
6534 static int
6535 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6536                             enum rte_eth_tunnel_type l2_tunnel_type)
6537 {
6538         int ret = 0;
6539         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6540
6541         switch (l2_tunnel_type) {
6542         case RTE_L2_TUNNEL_TYPE_E_TAG:
6543                 ret = ixgbe_e_tag_disable(hw);
6544                 break;
6545         default:
6546                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6547                 ret = -EINVAL;
6548                 break;
6549         }
6550
6551         return ret;
6552 }
6553
6554 static int
6555 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6556                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6557 {
6558         int ret = 0;
6559         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6560         uint32_t i, rar_entries;
6561         uint32_t rar_low, rar_high;
6562
6563         if (hw->mac.type != ixgbe_mac_X550 &&
6564             hw->mac.type != ixgbe_mac_X550EM_x &&
6565             hw->mac.type != ixgbe_mac_X550EM_a) {
6566                 return -ENOTSUP;
6567         }
6568
6569         rar_entries = ixgbe_get_num_rx_addrs(hw);
6570
6571         for (i = 1; i < rar_entries; i++) {
6572                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6573                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6574                 if ((rar_high & IXGBE_RAH_AV) &&
6575                     (rar_high & IXGBE_RAH_ADTYPE) &&
6576                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6577                      l2_tunnel->tunnel_id)) {
6578                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6579                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6580
6581                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6582
6583                         return ret;
6584                 }
6585         }
6586
6587         return ret;
6588 }
6589
6590 static int
6591 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6592                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6593 {
6594         int ret = 0;
6595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6596         uint32_t i, rar_entries;
6597         uint32_t rar_low, rar_high;
6598
6599         if (hw->mac.type != ixgbe_mac_X550 &&
6600             hw->mac.type != ixgbe_mac_X550EM_x &&
6601             hw->mac.type != ixgbe_mac_X550EM_a) {
6602                 return -ENOTSUP;
6603         }
6604
6605         /* One entry for one tunnel. Try to remove potential existing entry. */
6606         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6607
6608         rar_entries = ixgbe_get_num_rx_addrs(hw);
6609
6610         for (i = 1; i < rar_entries; i++) {
6611                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6612                 if (rar_high & IXGBE_RAH_AV) {
6613                         continue;
6614                 } else {
6615                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6616                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6617                         rar_low = l2_tunnel->tunnel_id;
6618
6619                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6620                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6621
6622                         return ret;
6623                 }
6624         }
6625
6626         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6627                      " Please remove a rule before adding a new one.");
6628         return -EINVAL;
6629 }
6630
6631 /* Add l2 tunnel filter */
6632 static int
6633 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6634                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6635 {
6636         int ret = 0;
6637
6638         switch (l2_tunnel->l2_tunnel_type) {
6639         case RTE_L2_TUNNEL_TYPE_E_TAG:
6640                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6641                 break;
6642         default:
6643                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6644                 ret = -EINVAL;
6645                 break;
6646         }
6647
6648         return ret;
6649 }
6650
6651 /* Delete l2 tunnel filter */
6652 static int
6653 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6654                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6655 {
6656         int ret = 0;
6657
6658         switch (l2_tunnel->l2_tunnel_type) {
6659         case RTE_L2_TUNNEL_TYPE_E_TAG:
6660                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6661                 break;
6662         default:
6663                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6664                 ret = -EINVAL;
6665                 break;
6666         }
6667
6668         return ret;
6669 }
6670
6671 /**
6672  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6673  * @dev: pointer to rte_eth_dev structure
6674  * @filter_op:operation will be taken.
6675  * @arg: a pointer to specific structure corresponding to the filter_op
6676  */
6677 static int
6678 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6679                                   enum rte_filter_op filter_op,
6680                                   void *arg)
6681 {
6682         int ret = 0;
6683
6684         if (filter_op == RTE_ETH_FILTER_NOP)
6685                 return 0;
6686
6687         if (arg == NULL) {
6688                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6689                             filter_op);
6690                 return -EINVAL;
6691         }
6692
6693         switch (filter_op) {
6694         case RTE_ETH_FILTER_ADD:
6695                 ret = ixgbe_dev_l2_tunnel_filter_add
6696                         (dev,
6697                          (struct rte_eth_l2_tunnel_conf *)arg);
6698                 break;
6699         case RTE_ETH_FILTER_DELETE:
6700                 ret = ixgbe_dev_l2_tunnel_filter_del
6701                         (dev,
6702                          (struct rte_eth_l2_tunnel_conf *)arg);
6703                 break;
6704         default:
6705                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6706                 ret = -EINVAL;
6707                 break;
6708         }
6709         return ret;
6710 }
6711
6712 static int
6713 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6714 {
6715         int ret = 0;
6716         uint32_t ctrl;
6717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6718
6719         if (hw->mac.type != ixgbe_mac_X550 &&
6720             hw->mac.type != ixgbe_mac_X550EM_x &&
6721             hw->mac.type != ixgbe_mac_X550EM_a) {
6722                 return -ENOTSUP;
6723         }
6724
6725         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6726         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6727         if (en)
6728                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6729         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6730
6731         return ret;
6732 }
6733
6734 /* Enable l2 tunnel forwarding */
6735 static int
6736 ixgbe_dev_l2_tunnel_forwarding_enable
6737         (struct rte_eth_dev *dev,
6738          enum rte_eth_tunnel_type l2_tunnel_type)
6739 {
6740         int ret = 0;
6741
6742         switch (l2_tunnel_type) {
6743         case RTE_L2_TUNNEL_TYPE_E_TAG:
6744                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6745                 break;
6746         default:
6747                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6748                 ret = -EINVAL;
6749                 break;
6750         }
6751
6752         return ret;
6753 }
6754
6755 /* Disable l2 tunnel forwarding */
6756 static int
6757 ixgbe_dev_l2_tunnel_forwarding_disable
6758         (struct rte_eth_dev *dev,
6759          enum rte_eth_tunnel_type l2_tunnel_type)
6760 {
6761         int ret = 0;
6762
6763         switch (l2_tunnel_type) {
6764         case RTE_L2_TUNNEL_TYPE_E_TAG:
6765                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6766                 break;
6767         default:
6768                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6769                 ret = -EINVAL;
6770                 break;
6771         }
6772
6773         return ret;
6774 }
6775
6776 static int
6777 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6778                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6779                              bool en)
6780 {
6781         int ret = 0;
6782         uint32_t vmtir, vmvir;
6783         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6784
6785         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6786                 PMD_DRV_LOG(ERR,
6787                             "VF id %u should be less than %u",
6788                             l2_tunnel->vf_id,
6789                             dev->pci_dev->max_vfs);
6790                 return -EINVAL;
6791         }
6792
6793         if (hw->mac.type != ixgbe_mac_X550 &&
6794             hw->mac.type != ixgbe_mac_X550EM_x &&
6795             hw->mac.type != ixgbe_mac_X550EM_a) {
6796                 return -ENOTSUP;
6797         }
6798
6799         if (en)
6800                 vmtir = l2_tunnel->tunnel_id;
6801         else
6802                 vmtir = 0;
6803
6804         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6805
6806         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6807         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6808         if (en)
6809                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6810         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6811
6812         return ret;
6813 }
6814
6815 /* Enable l2 tunnel tag insertion */
6816 static int
6817 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6818                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6819 {
6820         int ret = 0;
6821
6822         switch (l2_tunnel->l2_tunnel_type) {
6823         case RTE_L2_TUNNEL_TYPE_E_TAG:
6824                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6825                 break;
6826         default:
6827                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6828                 ret = -EINVAL;
6829                 break;
6830         }
6831
6832         return ret;
6833 }
6834
6835 /* Disable l2 tunnel tag insertion */
6836 static int
6837 ixgbe_dev_l2_tunnel_insertion_disable
6838         (struct rte_eth_dev *dev,
6839          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6840 {
6841         int ret = 0;
6842
6843         switch (l2_tunnel->l2_tunnel_type) {
6844         case RTE_L2_TUNNEL_TYPE_E_TAG:
6845                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6846                 break;
6847         default:
6848                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6849                 ret = -EINVAL;
6850                 break;
6851         }
6852
6853         return ret;
6854 }
6855
6856 static int
6857 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6858                              bool en)
6859 {
6860         int ret = 0;
6861         uint32_t qde;
6862         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6863
6864         if (hw->mac.type != ixgbe_mac_X550 &&
6865             hw->mac.type != ixgbe_mac_X550EM_x &&
6866             hw->mac.type != ixgbe_mac_X550EM_a) {
6867                 return -ENOTSUP;
6868         }
6869
6870         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6871         if (en)
6872                 qde |= IXGBE_QDE_STRIP_TAG;
6873         else
6874                 qde &= ~IXGBE_QDE_STRIP_TAG;
6875         qde &= ~IXGBE_QDE_READ;
6876         qde |= IXGBE_QDE_WRITE;
6877         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6878
6879         return ret;
6880 }
6881
6882 /* Enable l2 tunnel tag stripping */
6883 static int
6884 ixgbe_dev_l2_tunnel_stripping_enable
6885         (struct rte_eth_dev *dev,
6886          enum rte_eth_tunnel_type l2_tunnel_type)
6887 {
6888         int ret = 0;
6889
6890         switch (l2_tunnel_type) {
6891         case RTE_L2_TUNNEL_TYPE_E_TAG:
6892                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6893                 break;
6894         default:
6895                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6896                 ret = -EINVAL;
6897                 break;
6898         }
6899
6900         return ret;
6901 }
6902
6903 /* Disable l2 tunnel tag stripping */
6904 static int
6905 ixgbe_dev_l2_tunnel_stripping_disable
6906         (struct rte_eth_dev *dev,
6907          enum rte_eth_tunnel_type l2_tunnel_type)
6908 {
6909         int ret = 0;
6910
6911         switch (l2_tunnel_type) {
6912         case RTE_L2_TUNNEL_TYPE_E_TAG:
6913                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6914                 break;
6915         default:
6916                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6917                 ret = -EINVAL;
6918                 break;
6919         }
6920
6921         return ret;
6922 }
6923
6924 /* Enable/disable l2 tunnel offload functions */
6925 static int
6926 ixgbe_dev_l2_tunnel_offload_set
6927         (struct rte_eth_dev *dev,
6928          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6929          uint32_t mask,
6930          uint8_t en)
6931 {
6932         int ret = 0;
6933
6934         if (l2_tunnel == NULL)
6935                 return -EINVAL;
6936
6937         ret = -EINVAL;
6938         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6939                 if (en)
6940                         ret = ixgbe_dev_l2_tunnel_enable(
6941                                 dev,
6942                                 l2_tunnel->l2_tunnel_type);
6943                 else
6944                         ret = ixgbe_dev_l2_tunnel_disable(
6945                                 dev,
6946                                 l2_tunnel->l2_tunnel_type);
6947         }
6948
6949         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6950                 if (en)
6951                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6952                                 dev,
6953                                 l2_tunnel);
6954                 else
6955                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6956                                 dev,
6957                                 l2_tunnel);
6958         }
6959
6960         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6961                 if (en)
6962                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6963                                 dev,
6964                                 l2_tunnel->l2_tunnel_type);
6965                 else
6966                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6967                                 dev,
6968                                 l2_tunnel->l2_tunnel_type);
6969         }
6970
6971         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6972                 if (en)
6973                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6974                                 dev,
6975                                 l2_tunnel->l2_tunnel_type);
6976                 else
6977                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6978                                 dev,
6979                                 l2_tunnel->l2_tunnel_type);
6980         }
6981
6982         return ret;
6983 }
6984
6985 static int
6986 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6987                         uint16_t port)
6988 {
6989         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6990         IXGBE_WRITE_FLUSH(hw);
6991
6992         return 0;
6993 }
6994
6995 /* There's only one register for VxLAN UDP port.
6996  * So, we cannot add several ports. Will update it.
6997  */
6998 static int
6999 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7000                      uint16_t port)
7001 {
7002         if (port == 0) {
7003                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7004                 return -EINVAL;
7005         }
7006
7007         return ixgbe_update_vxlan_port(hw, port);
7008 }
7009
7010 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7011  * UDP port, it must have a value.
7012  * So, will reset it to the original value 0.
7013  */
7014 static int
7015 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7016                      uint16_t port)
7017 {
7018         uint16_t cur_port;
7019
7020         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7021
7022         if (cur_port != port) {
7023                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7024                 return -EINVAL;
7025         }
7026
7027         return ixgbe_update_vxlan_port(hw, 0);
7028 }
7029
7030 /* Add UDP tunneling port */
7031 static int
7032 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7033                               struct rte_eth_udp_tunnel *udp_tunnel)
7034 {
7035         int ret = 0;
7036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7037
7038         if (hw->mac.type != ixgbe_mac_X550 &&
7039             hw->mac.type != ixgbe_mac_X550EM_x &&
7040             hw->mac.type != ixgbe_mac_X550EM_a) {
7041                 return -ENOTSUP;
7042         }
7043
7044         if (udp_tunnel == NULL)
7045                 return -EINVAL;
7046
7047         switch (udp_tunnel->prot_type) {
7048         case RTE_TUNNEL_TYPE_VXLAN:
7049                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7050                 break;
7051
7052         case RTE_TUNNEL_TYPE_GENEVE:
7053         case RTE_TUNNEL_TYPE_TEREDO:
7054                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7055                 ret = -EINVAL;
7056                 break;
7057
7058         default:
7059                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7060                 ret = -EINVAL;
7061                 break;
7062         }
7063
7064         return ret;
7065 }
7066
7067 /* Remove UDP tunneling port */
7068 static int
7069 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7070                               struct rte_eth_udp_tunnel *udp_tunnel)
7071 {
7072         int ret = 0;
7073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7074
7075         if (hw->mac.type != ixgbe_mac_X550 &&
7076             hw->mac.type != ixgbe_mac_X550EM_x &&
7077             hw->mac.type != ixgbe_mac_X550EM_a) {
7078                 return -ENOTSUP;
7079         }
7080
7081         if (udp_tunnel == NULL)
7082                 return -EINVAL;
7083
7084         switch (udp_tunnel->prot_type) {
7085         case RTE_TUNNEL_TYPE_VXLAN:
7086                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7087                 break;
7088         case RTE_TUNNEL_TYPE_GENEVE:
7089         case RTE_TUNNEL_TYPE_TEREDO:
7090                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7091                 ret = -EINVAL;
7092                 break;
7093         default:
7094                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7095                 ret = -EINVAL;
7096                 break;
7097         }
7098
7099         return ret;
7100 }
7101
7102 /* ixgbevf_update_xcast_mode - Update Multicast mode
7103  * @hw: pointer to the HW structure
7104  * @netdev: pointer to net device structure
7105  * @xcast_mode: new multicast mode
7106  *
7107  * Updates the Multicast Mode of VF.
7108  */
7109 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7110                                      int xcast_mode)
7111 {
7112         struct ixgbe_mbx_info *mbx = &hw->mbx;
7113         u32 msgbuf[2];
7114         s32 err;
7115
7116         switch (hw->api_version) {
7117         case ixgbe_mbox_api_12:
7118                 break;
7119         default:
7120                 return -EOPNOTSUPP;
7121         }
7122
7123         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7124         msgbuf[1] = xcast_mode;
7125
7126         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7127         if (err)
7128                 return err;
7129
7130         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7131         if (err)
7132                 return err;
7133
7134         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7135         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7136                 return -EPERM;
7137
7138         return 0;
7139 }
7140
7141 static void
7142 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7143 {
7144         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7145
7146         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7147 }
7148
7149 static void
7150 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7151 {
7152         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7153
7154         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7155 }
7156
7157 static struct rte_driver rte_ixgbe_driver = {
7158         .type = PMD_PDEV,
7159         .init = rte_ixgbe_pmd_init,
7160 };
7161
7162 static struct rte_driver rte_ixgbevf_driver = {
7163         .type = PMD_PDEV,
7164         .init = rte_ixgbevf_pmd_init,
7165 };
7166
7167 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7168 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);