drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64 #include <rte_security_driver.h>
  65
  66 #include "ixgbe_logs.h"
  67 #include "base/ixgbe_api.h"
  68 #include "base/ixgbe_vf.h"
  69 #include "base/ixgbe_common.h"
  70 #include "ixgbe_ethdev.h"
  71 #include "ixgbe_bypass.h"
  72 #include "ixgbe_rxtx.h"
  73 #include "base/ixgbe_type.h"
  74 #include "base/ixgbe_phy.h"
  75 #include "ixgbe_regs.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 158 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 168 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 173 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static int
 187 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 188                 uint64_t *values, unsigned int n);
 189 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 190 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 191 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 192         struct rte_eth_xstat_name *xstats_names,
 193         unsigned int size);
 194 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 195         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 196 static int ixgbe_dev_xstats_get_names_by_id(
 197         struct rte_eth_dev *dev,
 198         struct rte_eth_xstat_name *xstats_names,
 199         const uint64_t *ids,
 200         unsigned int limit);
 201 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 202                                              uint16_t queue_id,
 203                                              uint8_t stat_idx,
 204                                              uint8_t is_rx);
 205 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 206                                  size_t fw_size);
 207 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 208                                struct rte_eth_dev_info *dev_info);
 209 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 210 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 211                                  struct rte_eth_dev_info *dev_info);
 212 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 213
 214 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 215                 uint16_t vlan_id, int on);
 216 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 217                                enum rte_vlan_type vlan_type,
 218                                uint16_t tpid_id);
 219 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 220                 uint16_t queue, bool on);
 221 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 222                 int on);
 223 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 224 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 225 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 226 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 227 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 228
 229 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 230 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 231 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 232                                struct rte_eth_fc_conf *fc_conf);
 233 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 234                                struct rte_eth_fc_conf *fc_conf);
 235 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 236                 struct rte_eth_pfc_conf *pfc_conf);
 237 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 238                         struct rte_eth_rss_reta_entry64 *reta_conf,
 239                         uint16_t reta_size);
 240 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 241                         struct rte_eth_rss_reta_entry64 *reta_conf,
 242                         uint16_t reta_size);
 243 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 245 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 247 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 248 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 249                                       struct rte_intr_handle *handle);
 250 static void ixgbe_dev_interrupt_handler(void *param);
 251 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 252 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 253                          uint32_t index, uint32_t pool);
 254 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 255 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 256                                            struct ether_addr *mac_addr);
 257 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 258 static bool is_device_supported(struct rte_eth_dev *dev,
 259                                 struct rte_pci_driver *drv);
 260
 261 /* For Virtual Function support */
 262 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 263 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 264 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 265 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 266 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 267                                    int wait_to_complete);
 268 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 269 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 270 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 271 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 272 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 273 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 274                 struct rte_eth_stats *stats);
 275 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 276 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 277                 uint16_t vlan_id, int on);
 278 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 279                 uint16_t queue, int on);
 280 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 281 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 282 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 283                                             uint16_t queue_id);
 284 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 285                                              uint16_t queue_id);
 286 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 287                                  uint8_t queue, uint8_t msix_vector);
 288 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 289 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 290 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 291
 292 /* For Eth VMDQ APIs support */
 293 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 294                 ether_addr * mac_addr, uint8_t on);
 295 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 296 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 297                 struct rte_eth_mirror_conf *mirror_conf,
 298                 uint8_t rule_id, uint8_t on);
 299 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 300                 uint8_t rule_id);
 301 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 302                                           uint16_t queue_id);
 303 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 304                                            uint16_t queue_id);
 305 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 306                                uint8_t queue, uint8_t msix_vector);
 307 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 308
 309 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 310                                 struct ether_addr *mac_addr,
 311                                 uint32_t index, uint32_t pool);
 312 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 313 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 314                                              struct ether_addr *mac_addr);
 315 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 316                         struct rte_eth_syn_filter *filter);
 317 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 318                         enum rte_filter_op filter_op,
 319                         void *arg);
 320 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 321                         struct ixgbe_5tuple_filter *filter);
 322 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 323                         struct ixgbe_5tuple_filter *filter);
 324 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 328                         struct rte_eth_ntuple_filter *filter);
 329 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 330                                 enum rte_filter_op filter_op,
 331                                 void *arg);
 332 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 333                         struct rte_eth_ethertype_filter *filter);
 334 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 335                      enum rte_filter_type filter_type,
 336                      enum rte_filter_op filter_op,
 337                      void *arg);
 338 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 339
 340 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 341                                       struct ether_addr *mc_addr_set,
 342                                       uint32_t nb_mc_addr);
 343 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 344                                    struct rte_eth_dcb_info *dcb_info);
 345
 346 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 347 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 348                             struct rte_dev_reg_info *regs);
 349 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 350 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 351                                 struct rte_dev_eeprom_info *eeprom);
 352 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 353                                 struct rte_dev_eeprom_info *eeprom);
 354
 355 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 356 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 357                                 struct rte_dev_reg_info *regs);
 358
 359 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 360 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 361 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 362                                             struct timespec *timestamp,
 363                                             uint32_t flags);
 364 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 365                                             struct timespec *timestamp);
 366 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 367 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 368                                    struct timespec *timestamp);
 369 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 370                                    const struct timespec *timestamp);
 371 static void ixgbevf_dev_interrupt_handler(void *param);
 372
 373 static int ixgbe_dev_l2_tunnel_eth_type_conf
 374         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 375 static int ixgbe_dev_l2_tunnel_offload_set
 376         (struct rte_eth_dev *dev,
 377          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 378          uint32_t mask,
 379          uint8_t en);
 380 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 381                                              enum rte_filter_op filter_op,
 382                                              void *arg);
 383
 384 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 385                                          struct rte_eth_udp_tunnel *udp_tunnel);
 386 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 387                                          struct rte_eth_udp_tunnel *udp_tunnel);
 388 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 389 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 390
 391 /*
 392  * Define VF Stats MACRO for Non "cleared on read" register
 393  */
 394 #define UPDATE_VF_STAT(reg, last, cur)                          \
 395 {                                                               \
 396         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 397         cur += (latest - last) & UINT_MAX;                      \
 398         last = latest;                                          \
 399 }
 400
 401 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 402 {                                                                \
 403         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 404         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 405         u64 latest = ((new_msb << 32) | new_lsb);                \
 406         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 407         last = latest;                                           \
 408 }
 409
 410 #define IXGBE_SET_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] |= 1 << bit;\
 414         } while (0)
 415
 416 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (h)->bitmap[idx] &= ~(1 << bit);\
 420         } while (0)
 421
 422 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 423                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 424                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 425                 (r) = (h)->bitmap[idx] >> bit & 1;\
 426         } while (0)
 427
 428 /*
 429  * The set of PCI devices this driver supports
 430  */
 431 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 480 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 482 #endif
 483         { .vendor_id = 0, /* sentinel */ },
 484 };
 485
 486 /*
 487  * The set of PCI devices this driver supports (for 82599 VF)
 488  */
 489 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 500         { .vendor_id = 0, /* sentinel */ },
 501 };
 502
 503 static const struct rte_eth_desc_lim rx_desc_lim = {
 504         .nb_max = IXGBE_MAX_RING_DESC,
 505         .nb_min = IXGBE_MIN_RING_DESC,
 506         .nb_align = IXGBE_RXD_ALIGN,
 507 };
 508
 509 static const struct rte_eth_desc_lim tx_desc_lim = {
 510         .nb_max = IXGBE_MAX_RING_DESC,
 511         .nb_min = IXGBE_MIN_RING_DESC,
 512         .nb_align = IXGBE_TXD_ALIGN,
 513         .nb_seg_max = IXGBE_TX_MAX_SEG,
 514         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 515 };
 516
 517 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 518         .dev_configure        = ixgbe_dev_configure,
 519         .dev_start            = ixgbe_dev_start,
 520         .dev_stop             = ixgbe_dev_stop,
 521         .dev_set_link_up    = ixgbe_dev_set_link_up,
 522         .dev_set_link_down  = ixgbe_dev_set_link_down,
 523         .dev_close            = ixgbe_dev_close,
 524         .dev_reset            = ixgbe_dev_reset,
 525         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 526         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 527         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 528         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 529         .link_update          = ixgbe_dev_link_update,
 530         .stats_get            = ixgbe_dev_stats_get,
 531         .xstats_get           = ixgbe_dev_xstats_get,
 532         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 533         .stats_reset          = ixgbe_dev_stats_reset,
 534         .xstats_reset         = ixgbe_dev_xstats_reset,
 535         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 536         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 537         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 538         .fw_version_get       = ixgbe_fw_version_get,
 539         .dev_infos_get        = ixgbe_dev_info_get,
 540         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 541         .mtu_set              = ixgbe_dev_mtu_set,
 542         .vlan_filter_set      = ixgbe_vlan_filter_set,
 543         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 544         .vlan_offload_set     = ixgbe_vlan_offload_set,
 545         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 546         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 547         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 548         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 549         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 550         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 551         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 552         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 553         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 554         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 555         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 556         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 557         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 558         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 559         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 560         .dev_led_on           = ixgbe_dev_led_on,
 561         .dev_led_off          = ixgbe_dev_led_off,
 562         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 563         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 564         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 565         .mac_addr_add         = ixgbe_add_rar,
 566         .mac_addr_remove      = ixgbe_remove_rar,
 567         .mac_addr_set         = ixgbe_set_default_mac_addr,
 568         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 569         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 570         .mirror_rule_set      = ixgbe_mirror_rule_set,
 571         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 572         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 573         .reta_update          = ixgbe_dev_rss_reta_update,
 574         .reta_query           = ixgbe_dev_rss_reta_query,
 575         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 576         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 577         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 578         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 579         .rxq_info_get         = ixgbe_rxq_info_get,
 580         .txq_info_get         = ixgbe_txq_info_get,
 581         .timesync_enable      = ixgbe_timesync_enable,
 582         .timesync_disable     = ixgbe_timesync_disable,
 583         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 584         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 585         .get_reg              = ixgbe_get_regs,
 586         .get_eeprom_length    = ixgbe_get_eeprom_length,
 587         .get_eeprom           = ixgbe_get_eeprom,
 588         .set_eeprom           = ixgbe_set_eeprom,
 589         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 590         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 591         .timesync_read_time   = ixgbe_timesync_read_time,
 592         .timesync_write_time  = ixgbe_timesync_write_time,
 593         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 594         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 595         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 596         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 597         .tm_ops_get           = ixgbe_tm_ops_get,
 598 };
 599
 600 /*
 601  * dev_ops for virtual function, bare necessities for basic vf
 602  * operation have been implemented
 603  */
 604 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 605         .dev_configure        = ixgbevf_dev_configure,
 606         .dev_start            = ixgbevf_dev_start,
 607         .dev_stop             = ixgbevf_dev_stop,
 608         .link_update          = ixgbevf_dev_link_update,
 609         .stats_get            = ixgbevf_dev_stats_get,
 610         .xstats_get           = ixgbevf_dev_xstats_get,
 611         .stats_reset          = ixgbevf_dev_stats_reset,
 612         .xstats_reset         = ixgbevf_dev_stats_reset,
 613         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 614         .dev_close            = ixgbevf_dev_close,
 615         .dev_reset            = ixgbevf_dev_reset,
 616         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 617         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 618         .dev_infos_get        = ixgbevf_dev_info_get,
 619         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 620         .mtu_set              = ixgbevf_dev_set_mtu,
 621         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 622         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 623         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 624         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 625         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 626         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 627         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 628         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 629         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 630         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 631         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 632         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 633         .mac_addr_add         = ixgbevf_add_mac_addr,
 634         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 635         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 636         .rxq_info_get         = ixgbe_rxq_info_get,
 637         .txq_info_get         = ixgbe_txq_info_get,
 638         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 639         .get_reg              = ixgbevf_get_regs,
 640         .reta_update          = ixgbe_dev_rss_reta_update,
 641         .reta_query           = ixgbe_dev_rss_reta_query,
 642         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 643         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 644 };
 645
 646 /* store statistics names and its offset in stats structure */
 647 struct rte_ixgbe_xstats_name_off {
 648         char name[RTE_ETH_XSTATS_NAME_SIZE];
 649         unsigned offset;
 650 };
 651
 652 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 653         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 654         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 655         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 656         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 657         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 658         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 659         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 660         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 661         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 662         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 663         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 664         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 665         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 666         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 667         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 668                 prc1023)},
 669         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 670                 prc1522)},
 671         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 672         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 673         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 674         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 675         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 676         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 677         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 678         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 679         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 680         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 681         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 682         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 683         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 684         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 685         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 686         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 687         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 688                 ptc1023)},
 689         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 690                 ptc1522)},
 691         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 692         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 693         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 694         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 695
 696         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 697                 fdirustat_add)},
 698         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 699                 fdirustat_remove)},
 700         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 701                 fdirfstat_fadd)},
 702         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 703                 fdirfstat_fremove)},
 704         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 705                 fdirmatch)},
 706         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 707                 fdirmiss)},
 708
 709         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 710         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 711         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 712                 fclast)},
 713         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 714         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 715         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 716         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 717         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 718                 fcoe_noddp)},
 719         {"rx_fcoe_no_direct_data_placement_ext_buff",
 720                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 721
 722         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 723                 lxontxc)},
 724         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 725                 lxonrxc)},
 726         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 727                 lxofftxc)},
 728         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 729                 lxoffrxc)},
 730         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 731 };
 732
 733 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 734                            sizeof(rte_ixgbe_stats_strings[0]))
 735
 736 /* MACsec statistics */
 737 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 738         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 739                 out_pkts_untagged)},
 740         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 741                 out_pkts_encrypted)},
 742         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 743                 out_pkts_protected)},
 744         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 745                 out_octets_encrypted)},
 746         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 747                 out_octets_protected)},
 748         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_untagged)},
 750         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_badtag)},
 752         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_nosci)},
 754         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_unknownsci)},
 756         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 757                 in_octets_decrypted)},
 758         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 759                 in_octets_validated)},
 760         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_unchecked)},
 762         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_delayed)},
 764         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_late)},
 766         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_ok)},
 768         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_invalid)},
 770         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_notvalid)},
 772         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_unusedsa)},
 774         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_notusingsa)},
 776 };
 777
 778 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 779                            sizeof(rte_ixgbe_macsec_strings[0]))
 780
 781 /* Per-queue statistics */
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 783         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 784         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 785         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 786         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 787 };
 788
 789 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 790                            sizeof(rte_ixgbe_rxq_strings[0]))
 791 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 792
 793 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 794         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 795         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 796         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 797                 pxon2offc)},
 798 };
 799
 800 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 801                            sizeof(rte_ixgbe_txq_strings[0]))
 802 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 803
 804 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 805         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 806 };
 807
 808 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 809                 sizeof(rte_ixgbevf_stats_strings[0]))
 810
 811 /**
 812  * Atomically reads the link status information from global
 813  * structure rte_eth_dev.
 814  *
 815  * @param dev
 816  *   - Pointer to the structure rte_eth_dev to read from.
 817  *   - Pointer to the buffer to be saved with the link status.
 818  *
 819  * @return
 820  *   - On success, zero.
 821  *   - On failure, negative value.
 822  */
 823 static inline int
 824 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 825                                 struct rte_eth_link *link)
 826 {
 827         struct rte_eth_link *dst = link;
 828         struct rte_eth_link *src = &(dev->data->dev_link);
 829
 830         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 831                                         *(uint64_t *)src) == 0)
 832                 return -1;
 833
 834         return 0;
 835 }
 836
 837 /**
 838  * Atomically writes the link status information into global
 839  * structure rte_eth_dev.
 840  *
 841  * @param dev
 842  *   - Pointer to the structure rte_eth_dev to read from.
 843  *   - Pointer to the buffer to be saved with the link status.
 844  *
 845  * @return
 846  *   - On success, zero.
 847  *   - On failure, negative value.
 848  */
 849 static inline int
 850 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 851                                 struct rte_eth_link *link)
 852 {
 853         struct rte_eth_link *dst = &(dev->data->dev_link);
 854         struct rte_eth_link *src = link;
 855
 856         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 857                                         *(uint64_t *)src) == 0)
 858                 return -1;
 859
 860         return 0;
 861 }
 862
 863 /*
 864  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 865  */
 866 static inline int
 867 ixgbe_is_sfp(struct ixgbe_hw *hw)
 868 {
 869         switch (hw->phy.type) {
 870         case ixgbe_phy_sfp_avago:
 871         case ixgbe_phy_sfp_ftl:
 872         case ixgbe_phy_sfp_intel:
 873         case ixgbe_phy_sfp_unknown:
 874         case ixgbe_phy_sfp_passive_tyco:
 875         case ixgbe_phy_sfp_passive_unknown:
 876                 return 1;
 877         default:
 878                 return 0;
 879         }
 880 }
 881
 882 static inline int32_t
 883 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 884 {
 885         uint32_t ctrl_ext;
 886         int32_t status;
 887
 888         status = ixgbe_reset_hw(hw);
 889
 890         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 891         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 892         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 893         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 894         IXGBE_WRITE_FLUSH(hw);
 895
 896         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 897                 status = IXGBE_SUCCESS;
 898         return status;
 899 }
 900
 901 static inline void
 902 ixgbe_enable_intr(struct rte_eth_dev *dev)
 903 {
 904         struct ixgbe_interrupt *intr =
 905                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 906         struct ixgbe_hw *hw =
 907                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 908
 909         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 910         IXGBE_WRITE_FLUSH(hw);
 911 }
 912
 913 /*
 914  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 915  */
 916 static void
 917 ixgbe_disable_intr(struct ixgbe_hw *hw)
 918 {
 919         PMD_INIT_FUNC_TRACE();
 920
 921         if (hw->mac.type == ixgbe_mac_82598EB) {
 922                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 923         } else {
 924                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 925                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 927         }
 928         IXGBE_WRITE_FLUSH(hw);
 929 }
 930
 931 /*
 932  * This function resets queue statistics mapping registers.
 933  * From Niantic datasheet, Initialization of Statistics section:
 934  * "...if software requires the queue counters, the RQSMR and TQSM registers
 935  * must be re-programmed following a device reset.
 936  */
 937 static void
 938 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 939 {
 940         uint32_t i;
 941
 942         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 943                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 944                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 945         }
 946 }
 947
 948
 949 static int
 950 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 951                                   uint16_t queue_id,
 952                                   uint8_t stat_idx,
 953                                   uint8_t is_rx)
 954 {
 955 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 956 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 957 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 958
 959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 960         struct ixgbe_stat_mapping_registers *stat_mappings =
 961                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 962         uint32_t qsmr_mask = 0;
 963         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 964         uint32_t q_map;
 965         uint8_t n, offset;
 966
 967         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 968                 (hw->mac.type != ixgbe_mac_X540) &&
 969                 (hw->mac.type != ixgbe_mac_X550) &&
 970                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 971                 (hw->mac.type != ixgbe_mac_X550EM_a))
 972                 return -ENOSYS;
 973
 974         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 975                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 976                      queue_id, stat_idx);
 977
 978         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 979         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 980                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 981                 return -EIO;
 982         }
 983         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 984
 985         /* Now clear any previous stat_idx set */
 986         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 987         if (!is_rx)
 988                 stat_mappings->tqsm[n] &= ~clearing_mask;
 989         else
 990                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 991
 992         q_map = (uint32_t)stat_idx;
 993         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 994         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 995         if (!is_rx)
 996                 stat_mappings->tqsm[n] |= qsmr_mask;
 997         else
 998                 stat_mappings->rqsmr[n] |= qsmr_mask;
 999
1000         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1001                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1002                      queue_id, stat_idx);
1003         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1004                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1005
1006         /* Now write the mapping in the appropriate register */
1007         if (is_rx) {
1008                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1009                              stat_mappings->rqsmr[n], n);
1010                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1011         } else {
1012                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1013                              stat_mappings->tqsm[n], n);
1014                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1015         }
1016         return 0;
1017 }
1018
1019 static void
1020 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1021 {
1022         struct ixgbe_stat_mapping_registers *stat_mappings =
1023                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1025         int i;
1026
1027         /* write whatever was in stat mapping table to the NIC */
1028         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1029                 /* rx */
1030                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1031
1032                 /* tx */
1033                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1034         }
1035 }
1036
1037 static void
1038 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1039 {
1040         uint8_t i;
1041         struct ixgbe_dcb_tc_config *tc;
1042         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1043
1044         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1045         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1046         for (i = 0; i < dcb_max_tc; i++) {
1047                 tc = &dcb_config->tc_config[i];
1048                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1049                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1050                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1051                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1052                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1053                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1054                 tc->pfc = ixgbe_dcb_pfc_disabled;
1055         }
1056
1057         /* Initialize default user to priority mapping, UPx->TC0 */
1058         tc = &dcb_config->tc_config[0];
1059         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1060         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1061         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1062                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1063                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1064         }
1065         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1066         dcb_config->pfc_mode_enable = false;
1067         dcb_config->vt_mode = true;
1068         dcb_config->round_robin_enable = false;
1069         /* support all DCB capabilities in 82599 */
1070         dcb_config->support.capabilities = 0xFF;
1071
1072         /*we only support 4 Tcs for X540, X550 */
1073         if (hw->mac.type == ixgbe_mac_X540 ||
1074                 hw->mac.type == ixgbe_mac_X550 ||
1075                 hw->mac.type == ixgbe_mac_X550EM_x ||
1076                 hw->mac.type == ixgbe_mac_X550EM_a) {
1077                 dcb_config->num_tcs.pg_tcs = 4;
1078                 dcb_config->num_tcs.pfc_tcs = 4;
1079         }
1080 }
1081
1082 /*
1083  * Ensure that all locks are released before first NVM or PHY access
1084  */
1085 static void
1086 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1087 {
1088         uint16_t mask;
1089
1090         /*
1091          * Phy lock should not fail in this early stage. If this is the case,
1092          * it is due to an improper exit of the application.
1093          * So force the release of the faulty lock. Release of common lock
1094          * is done automatically by swfw_sync function.
1095          */
1096         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1097         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1098                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1099         }
1100         ixgbe_release_swfw_semaphore(hw, mask);
1101
1102         /*
1103          * These ones are more tricky since they are common to all ports; but
1104          * swfw_sync retries last long enough (1s) to be almost sure that if
1105          * lock can not be taken it is due to an improper lock of the
1106          * semaphore.
1107          */
1108         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1109         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1111         }
1112         ixgbe_release_swfw_semaphore(hw, mask);
1113 }
1114
1115 /*
1116  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1117  * It returns 0 on success.
1118  */
1119 static int
1120 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1121 {
1122         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1123         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1124         struct ixgbe_hw *hw =
1125                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1126         struct ixgbe_vfta *shadow_vfta =
1127                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1128         struct ixgbe_hwstrip *hwstrip =
1129                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1130         struct ixgbe_dcb_config *dcb_config =
1131                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1132         struct ixgbe_filter_info *filter_info =
1133                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1134         struct ixgbe_bw_conf *bw_conf =
1135                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1136         uint32_t ctrl_ext;
1137         uint16_t csum;
1138         int diag, i;
1139
1140         PMD_INIT_FUNC_TRACE();
1141
1142         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1143         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1144         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1145         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1146
1147         /*
1148          * For secondary processes, we don't initialise any further as primary
1149          * has already done this work. Only check we don't need a different
1150          * RX and TX function.
1151          */
1152         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1153                 struct ixgbe_tx_queue *txq;
1154                 /* TX queue function in primary, set by last queue initialized
1155                  * Tx queue may not initialized by primary process
1156                  */
1157                 if (eth_dev->data->tx_queues) {
1158                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1159                         ixgbe_set_tx_function(eth_dev, txq);
1160                 } else {
1161                         /* Use default TX function if we get here */
1162                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1163                                      "Using default TX function.");
1164                 }
1165
1166                 ixgbe_set_rx_function(eth_dev);
1167
1168                 return 0;
1169         }
1170
1171         /* Initialize security_ctx only for primary process*/
1172         eth_dev->security_ctx = ixgbe_ipsec_ctx_create(eth_dev);
1173         if (eth_dev->security_ctx == NULL)
1174                 return -ENOMEM;
1175
1176         rte_eth_copy_pci_info(eth_dev, pci_dev);
1177         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1178
1179         /* Vendor and Device ID need to be set before init of shared code */
1180         hw->device_id = pci_dev->id.device_id;
1181         hw->vendor_id = pci_dev->id.vendor_id;
1182         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1183         hw->allow_unsupported_sfp = 1;
1184
1185         /* Initialize the shared code (base driver) */
1186 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1187         diag = ixgbe_bypass_init_shared_code(hw);
1188 #else
1189         diag = ixgbe_init_shared_code(hw);
1190 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1191
1192         if (diag != IXGBE_SUCCESS) {
1193                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1194                 return -EIO;
1195         }
1196
1197         /* pick up the PCI bus settings for reporting later */
1198         ixgbe_get_bus_info(hw);
1199
1200         /* Unlock any pending hardware semaphore */
1201         ixgbe_swfw_lock_reset(hw);
1202
1203         /* Initialize DCB configuration*/
1204         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1205         ixgbe_dcb_init(hw, dcb_config);
1206         /* Get Hardware Flow Control setting */
1207         hw->fc.requested_mode = ixgbe_fc_full;
1208         hw->fc.current_mode = ixgbe_fc_full;
1209         hw->fc.pause_time = IXGBE_FC_PAUSE;
1210         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1211                 hw->fc.low_water[i] = IXGBE_FC_LO;
1212                 hw->fc.high_water[i] = IXGBE_FC_HI;
1213         }
1214         hw->fc.send_xon = 1;
1215
1216         /* Make sure we have a good EEPROM before we read from it */
1217         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1218         if (diag != IXGBE_SUCCESS) {
1219                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1220                 return -EIO;
1221         }
1222
1223 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1224         diag = ixgbe_bypass_init_hw(hw);
1225 #else
1226         diag = ixgbe_init_hw(hw);
1227 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1228
1229         /*
1230          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1231          * is called too soon after the kernel driver unbinding/binding occurs.
1232          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1233          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1234          * also called. See ixgbe_identify_phy_82599(). The reason for the
1235          * failure is not known, and only occuts when virtualisation features
1236          * are disabled in the bios. A delay of 100ms  was found to be enough by
1237          * trial-and-error, and is doubled to be safe.
1238          */
1239         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1240                 rte_delay_ms(200);
1241                 diag = ixgbe_init_hw(hw);
1242         }
1243
1244         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1245                 diag = IXGBE_SUCCESS;
1246
1247         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1248                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1249                              "LOM.  Please be aware there may be issues associated "
1250                              "with your hardware.");
1251                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1252                              "please contact your Intel or hardware representative "
1253                              "who provided you with this hardware.");
1254         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1255                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1256         if (diag) {
1257                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1258                 return -EIO;
1259         }
1260
1261         /* Reset the hw statistics */
1262         ixgbe_dev_stats_reset(eth_dev);
1263
1264         /* disable interrupt */
1265         ixgbe_disable_intr(hw);
1266
1267         /* reset mappings for queue statistics hw counters*/
1268         ixgbe_reset_qstat_mappings(hw);
1269
1270         /* Allocate memory for storing MAC addresses */
1271         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1272                                                hw->mac.num_rar_entries, 0);
1273         if (eth_dev->data->mac_addrs == NULL) {
1274                 PMD_INIT_LOG(ERR,
1275                              "Failed to allocate %u bytes needed to store "
1276                              "MAC addresses",
1277                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1278                 return -ENOMEM;
1279         }
1280         /* Copy the permanent MAC address */
1281         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1282                         &eth_dev->data->mac_addrs[0]);
1283
1284         /* Allocate memory for storing hash filter MAC addresses */
1285         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1286                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1287         if (eth_dev->data->hash_mac_addrs == NULL) {
1288                 PMD_INIT_LOG(ERR,
1289                              "Failed to allocate %d bytes needed to store MAC addresses",
1290                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1291                 return -ENOMEM;
1292         }
1293
1294         /* initialize the vfta */
1295         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1296
1297         /* initialize the hw strip bitmap*/
1298         memset(hwstrip, 0, sizeof(*hwstrip));
1299
1300         /* initialize PF if max_vfs not zero */
1301         ixgbe_pf_host_init(eth_dev);
1302
1303         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1304         /* let hardware know driver is loaded */
1305         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1306         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1307         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1308         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1309         IXGBE_WRITE_FLUSH(hw);
1310
1311         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1312                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1313                              (int) hw->mac.type, (int) hw->phy.type,
1314                              (int) hw->phy.sfp_type);
1315         else
1316                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1317                              (int) hw->mac.type, (int) hw->phy.type);
1318
1319         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1320                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1321                      pci_dev->id.device_id);
1322
1323         rte_intr_callback_register(intr_handle,
1324                                    ixgbe_dev_interrupt_handler, eth_dev);
1325
1326         /* enable uio/vfio intr/eventfd mapping */
1327         rte_intr_enable(intr_handle);
1328
1329         /* enable support intr */
1330         ixgbe_enable_intr(eth_dev);
1331
1332         /* initialize filter info */
1333         memset(filter_info, 0,
1334                sizeof(struct ixgbe_filter_info));
1335
1336         /* initialize 5tuple filter list */
1337         TAILQ_INIT(&filter_info->fivetuple_list);
1338
1339         /* initialize flow director filter list & hash */
1340         ixgbe_fdir_filter_init(eth_dev);
1341
1342         /* initialize l2 tunnel filter list & hash */
1343         ixgbe_l2_tn_filter_init(eth_dev);
1344
1345         /* initialize flow filter lists */
1346         ixgbe_filterlist_init();
1347
1348         /* initialize bandwidth configuration info */
1349         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1350
1351         /* initialize Traffic Manager configuration */
1352         ixgbe_tm_conf_init(eth_dev);
1353
1354         return 0;
1355 }
1356
1357 static int
1358 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1359 {
1360         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1361         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1362         struct ixgbe_hw *hw;
1363
1364         PMD_INIT_FUNC_TRACE();
1365
1366         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1367                 return -EPERM;
1368
1369         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1370
1371         if (hw->adapter_stopped == 0)
1372                 ixgbe_dev_close(eth_dev);
1373
1374         eth_dev->dev_ops = NULL;
1375         eth_dev->rx_pkt_burst = NULL;
1376         eth_dev->tx_pkt_burst = NULL;
1377
1378         /* Unlock any pending hardware semaphore */
1379         ixgbe_swfw_lock_reset(hw);
1380
1381         /* disable uio intr before callback unregister */
1382         rte_intr_disable(intr_handle);
1383         rte_intr_callback_unregister(intr_handle,
1384                                      ixgbe_dev_interrupt_handler, eth_dev);
1385
1386         /* uninitialize PF if max_vfs not zero */
1387         ixgbe_pf_host_uninit(eth_dev);
1388
1389         rte_free(eth_dev->data->mac_addrs);
1390         eth_dev->data->mac_addrs = NULL;
1391
1392         rte_free(eth_dev->data->hash_mac_addrs);
1393         eth_dev->data->hash_mac_addrs = NULL;
1394
1395         /* remove all the fdir filters & hash */
1396         ixgbe_fdir_filter_uninit(eth_dev);
1397
1398         /* remove all the L2 tunnel filters & hash */
1399         ixgbe_l2_tn_filter_uninit(eth_dev);
1400
1401         /* Remove all ntuple filters of the device */
1402         ixgbe_ntuple_filter_uninit(eth_dev);
1403
1404         /* clear all the filters list */
1405         ixgbe_filterlist_flush();
1406
1407         /* Remove all Traffic Manager configuration */
1408         ixgbe_tm_conf_uninit(eth_dev);
1409
1410         rte_free(eth_dev->security_ctx);
1411
1412         return 0;
1413 }
1414
1415 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1416 {
1417         struct ixgbe_filter_info *filter_info =
1418                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1419         struct ixgbe_5tuple_filter *p_5tuple;
1420
1421         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1422                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1423                              p_5tuple,
1424                              entries);
1425                 rte_free(p_5tuple);
1426         }
1427         memset(filter_info->fivetuple_mask, 0,
1428                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1429
1430         return 0;
1431 }
1432
1433 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1434 {
1435         struct ixgbe_hw_fdir_info *fdir_info =
1436                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1437         struct ixgbe_fdir_filter *fdir_filter;
1438
1439                 if (fdir_info->hash_map)
1440                 rte_free(fdir_info->hash_map);
1441         if (fdir_info->hash_handle)
1442                 rte_hash_free(fdir_info->hash_handle);
1443
1444         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1445                 TAILQ_REMOVE(&fdir_info->fdir_list,
1446                              fdir_filter,
1447                              entries);
1448                 rte_free(fdir_filter);
1449         }
1450
1451         return 0;
1452 }
1453
1454 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1455 {
1456         struct ixgbe_l2_tn_info *l2_tn_info =
1457                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1458         struct ixgbe_l2_tn_filter *l2_tn_filter;
1459
1460         if (l2_tn_info->hash_map)
1461                 rte_free(l2_tn_info->hash_map);
1462         if (l2_tn_info->hash_handle)
1463                 rte_hash_free(l2_tn_info->hash_handle);
1464
1465         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1466                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1467                              l2_tn_filter,
1468                              entries);
1469                 rte_free(l2_tn_filter);
1470         }
1471
1472         return 0;
1473 }
1474
1475 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1476 {
1477         struct ixgbe_hw_fdir_info *fdir_info =
1478                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1479         char fdir_hash_name[RTE_HASH_NAMESIZE];
1480         struct rte_hash_parameters fdir_hash_params = {
1481                 .name = fdir_hash_name,
1482                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1483                 .key_len = sizeof(union ixgbe_atr_input),
1484                 .hash_func = rte_hash_crc,
1485                 .hash_func_init_val = 0,
1486                 .socket_id = rte_socket_id(),
1487         };
1488
1489         TAILQ_INIT(&fdir_info->fdir_list);
1490         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1491                  "fdir_%s", eth_dev->device->name);
1492         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1493         if (!fdir_info->hash_handle) {
1494                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1495                 return -EINVAL;
1496         }
1497         fdir_info->hash_map = rte_zmalloc("ixgbe",
1498                                           sizeof(struct ixgbe_fdir_filter *) *
1499                                           IXGBE_MAX_FDIR_FILTER_NUM,
1500                                           0);
1501         if (!fdir_info->hash_map) {
1502                 PMD_INIT_LOG(ERR,
1503                              "Failed to allocate memory for fdir hash map!");
1504                 return -ENOMEM;
1505         }
1506         fdir_info->mask_added = FALSE;
1507
1508         return 0;
1509 }
1510
1511 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1512 {
1513         struct ixgbe_l2_tn_info *l2_tn_info =
1514                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1515         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1516         struct rte_hash_parameters l2_tn_hash_params = {
1517                 .name = l2_tn_hash_name,
1518                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1519                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1520                 .hash_func = rte_hash_crc,
1521                 .hash_func_init_val = 0,
1522                 .socket_id = rte_socket_id(),
1523         };
1524
1525         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1526         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1527                  "l2_tn_%s", eth_dev->device->name);
1528         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1529         if (!l2_tn_info->hash_handle) {
1530                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1531                 return -EINVAL;
1532         }
1533         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1534                                    sizeof(struct ixgbe_l2_tn_filter *) *
1535                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1536                                    0);
1537         if (!l2_tn_info->hash_map) {
1538                 PMD_INIT_LOG(ERR,
1539                         "Failed to allocate memory for L2 TN hash map!");
1540                 return -ENOMEM;
1541         }
1542         l2_tn_info->e_tag_en = FALSE;
1543         l2_tn_info->e_tag_fwd_en = FALSE;
1544         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1545
1546         return 0;
1547 }
1548 /*
1549  * Negotiate mailbox API version with the PF.
1550  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1551  * Then we try to negotiate starting with the most recent one.
1552  * If all negotiation attempts fail, then we will proceed with
1553  * the default one (ixgbe_mbox_api_10).
1554  */
1555 static void
1556 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1557 {
1558         int32_t i;
1559
1560         /* start with highest supported, proceed down */
1561         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1562                 ixgbe_mbox_api_12,
1563                 ixgbe_mbox_api_11,
1564                 ixgbe_mbox_api_10,
1565         };
1566
1567         for (i = 0;
1568                         i != RTE_DIM(sup_ver) &&
1569                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1570                         i++)
1571                 ;
1572 }
1573
1574 static void
1575 generate_random_mac_addr(struct ether_addr *mac_addr)
1576 {
1577         uint64_t random;
1578
1579         /* Set Organizationally Unique Identifier (OUI) prefix. */
1580         mac_addr->addr_bytes[0] = 0x00;
1581         mac_addr->addr_bytes[1] = 0x09;
1582         mac_addr->addr_bytes[2] = 0xC0;
1583         /* Force indication of locally assigned MAC address. */
1584         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1585         /* Generate the last 3 bytes of the MAC address with a random number. */
1586         random = rte_rand();
1587         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1588 }
1589
1590 /*
1591  * Virtual Function device init
1592  */
1593 static int
1594 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1595 {
1596         int diag;
1597         uint32_t tc, tcs;
1598         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1599         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1600         struct ixgbe_hw *hw =
1601                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1602         struct ixgbe_vfta *shadow_vfta =
1603                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1604         struct ixgbe_hwstrip *hwstrip =
1605                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1606         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1607
1608         PMD_INIT_FUNC_TRACE();
1609
1610         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1611         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1612         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1613
1614         /* for secondary processes, we don't initialise any further as primary
1615          * has already done this work. Only check we don't need a different
1616          * RX function
1617          */
1618         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1619                 struct ixgbe_tx_queue *txq;
1620                 /* TX queue function in primary, set by last queue initialized
1621                  * Tx queue may not initialized by primary process
1622                  */
1623                 if (eth_dev->data->tx_queues) {
1624                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1625                         ixgbe_set_tx_function(eth_dev, txq);
1626                 } else {
1627                         /* Use default TX function if we get here */
1628                         PMD_INIT_LOG(NOTICE,
1629                                      "No TX queues configured yet. Using default TX function.");
1630                 }
1631
1632                 ixgbe_set_rx_function(eth_dev);
1633
1634                 return 0;
1635         }
1636
1637         rte_eth_copy_pci_info(eth_dev, pci_dev);
1638         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1639
1640         hw->device_id = pci_dev->id.device_id;
1641         hw->vendor_id = pci_dev->id.vendor_id;
1642         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1643
1644         /* initialize the vfta */
1645         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1646
1647         /* initialize the hw strip bitmap*/
1648         memset(hwstrip, 0, sizeof(*hwstrip));
1649
1650         /* Initialize the shared code (base driver) */
1651         diag = ixgbe_init_shared_code(hw);
1652         if (diag != IXGBE_SUCCESS) {
1653                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1654                 return -EIO;
1655         }
1656
1657         /* init_mailbox_params */
1658         hw->mbx.ops.init_params(hw);
1659
1660         /* Reset the hw statistics */
1661         ixgbevf_dev_stats_reset(eth_dev);
1662
1663         /* Disable the interrupts for VF */
1664         ixgbevf_intr_disable(hw);
1665
1666         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1667         diag = hw->mac.ops.reset_hw(hw);
1668
1669         /*
1670          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1671          * the underlying PF driver has not assigned a MAC address to the VF.
1672          * In this case, assign a random MAC address.
1673          */
1674         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1675                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1676                 return diag;
1677         }
1678
1679         /* negotiate mailbox API version to use with the PF. */
1680         ixgbevf_negotiate_api(hw);
1681
1682         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1683         ixgbevf_get_queues(hw, &tcs, &tc);
1684
1685         /* Allocate memory for storing MAC addresses */
1686         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1687                                                hw->mac.num_rar_entries, 0);
1688         if (eth_dev->data->mac_addrs == NULL) {
1689                 PMD_INIT_LOG(ERR,
1690                              "Failed to allocate %u bytes needed to store "
1691                              "MAC addresses",
1692                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1693                 return -ENOMEM;
1694         }
1695
1696         /* Generate a random MAC address, if none was assigned by PF. */
1697         if (is_zero_ether_addr(perm_addr)) {
1698                 generate_random_mac_addr(perm_addr);
1699                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1700                 if (diag) {
1701                         rte_free(eth_dev->data->mac_addrs);
1702                         eth_dev->data->mac_addrs = NULL;
1703                         return diag;
1704                 }
1705                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1706                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1707                              "%02x:%02x:%02x:%02x:%02x:%02x",
1708                              perm_addr->addr_bytes[0],
1709                              perm_addr->addr_bytes[1],
1710                              perm_addr->addr_bytes[2],
1711                              perm_addr->addr_bytes[3],
1712                              perm_addr->addr_bytes[4],
1713                              perm_addr->addr_bytes[5]);
1714         }
1715
1716         /* Copy the permanent MAC address */
1717         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1718
1719         /* reset the hardware with the new settings */
1720         diag = hw->mac.ops.start_hw(hw);
1721         switch (diag) {
1722         case  0:
1723                 break;
1724
1725         default:
1726                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1727                 return -EIO;
1728         }
1729
1730         rte_intr_callback_register(intr_handle,
1731                                    ixgbevf_dev_interrupt_handler, eth_dev);
1732         rte_intr_enable(intr_handle);
1733         ixgbevf_intr_enable(hw);
1734
1735         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1736                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1737                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1738
1739         return 0;
1740 }
1741
1742 /* Virtual Function device uninit */
1743
1744 static int
1745 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1746 {
1747         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1748         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1749         struct ixgbe_hw *hw;
1750
1751         PMD_INIT_FUNC_TRACE();
1752
1753         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1754                 return -EPERM;
1755
1756         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1757
1758         if (hw->adapter_stopped == 0)
1759                 ixgbevf_dev_close(eth_dev);
1760
1761         eth_dev->dev_ops = NULL;
1762         eth_dev->rx_pkt_burst = NULL;
1763         eth_dev->tx_pkt_burst = NULL;
1764
1765         /* Disable the interrupts for VF */
1766         ixgbevf_intr_disable(hw);
1767
1768         rte_free(eth_dev->data->mac_addrs);
1769         eth_dev->data->mac_addrs = NULL;
1770
1771         rte_intr_disable(intr_handle);
1772         rte_intr_callback_unregister(intr_handle,
1773                                      ixgbevf_dev_interrupt_handler, eth_dev);
1774
1775         return 0;
1776 }
1777
1778 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1779         struct rte_pci_device *pci_dev)
1780 {
1781         return rte_eth_dev_pci_generic_probe(pci_dev,
1782                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1783 }
1784
1785 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1786 {
1787         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1788 }
1789
1790 static struct rte_pci_driver rte_ixgbe_pmd = {
1791         .id_table = pci_id_ixgbe_map,
1792         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1793                      RTE_PCI_DRV_IOVA_AS_VA,
1794         .probe = eth_ixgbe_pci_probe,
1795         .remove = eth_ixgbe_pci_remove,
1796 };
1797
1798 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1799         struct rte_pci_device *pci_dev)
1800 {
1801         return rte_eth_dev_pci_generic_probe(pci_dev,
1802                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1803 }
1804
1805 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1806 {
1807         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1808 }
1809
1810 /*
1811  * virtual function driver struct
1812  */
1813 static struct rte_pci_driver rte_ixgbevf_pmd = {
1814         .id_table = pci_id_ixgbevf_map,
1815         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1816         .probe = eth_ixgbevf_pci_probe,
1817         .remove = eth_ixgbevf_pci_remove,
1818 };
1819
1820 static int
1821 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1822 {
1823         struct ixgbe_hw *hw =
1824                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825         struct ixgbe_vfta *shadow_vfta =
1826                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1827         uint32_t vfta;
1828         uint32_t vid_idx;
1829         uint32_t vid_bit;
1830
1831         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1832         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1833         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1834         if (on)
1835                 vfta |= vid_bit;
1836         else
1837                 vfta &= ~vid_bit;
1838         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1839
1840         /* update local VFTA copy */
1841         shadow_vfta->vfta[vid_idx] = vfta;
1842
1843         return 0;
1844 }
1845
1846 static void
1847 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1848 {
1849         if (on)
1850                 ixgbe_vlan_hw_strip_enable(dev, queue);
1851         else
1852                 ixgbe_vlan_hw_strip_disable(dev, queue);
1853 }
1854
1855 static int
1856 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1857                     enum rte_vlan_type vlan_type,
1858                     uint16_t tpid)
1859 {
1860         struct ixgbe_hw *hw =
1861                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862         int ret = 0;
1863         uint32_t reg;
1864         uint32_t qinq;
1865
1866         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867         qinq &= IXGBE_DMATXCTL_GDV;
1868
1869         switch (vlan_type) {
1870         case ETH_VLAN_TYPE_INNER:
1871                 if (qinq) {
1872                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1873                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1874                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1875                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1876                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1877                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1878                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1879                 } else {
1880                         ret = -ENOTSUP;
1881                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1882                                     " by single VLAN");
1883                 }
1884                 break;
1885         case ETH_VLAN_TYPE_OUTER:
1886                 if (qinq) {
1887                         /* Only the high 16-bits is valid */
1888                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1889                                         IXGBE_EXVET_VET_EXT_SHIFT);
1890                 } else {
1891                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1892                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1893                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1894                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1895                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1896                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1897                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1898                 }
1899
1900                 break;
1901         default:
1902                 ret = -EINVAL;
1903                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1904                 break;
1905         }
1906
1907         return ret;
1908 }
1909
1910 void
1911 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1912 {
1913         struct ixgbe_hw *hw =
1914                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1915         uint32_t vlnctrl;
1916
1917         PMD_INIT_FUNC_TRACE();
1918
1919         /* Filter Table Disable */
1920         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1921         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1922
1923         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1924 }
1925
1926 void
1927 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1928 {
1929         struct ixgbe_hw *hw =
1930                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1931         struct ixgbe_vfta *shadow_vfta =
1932                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1933         uint32_t vlnctrl;
1934         uint16_t i;
1935
1936         PMD_INIT_FUNC_TRACE();
1937
1938         /* Filter Table Enable */
1939         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1940         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1941         vlnctrl |= IXGBE_VLNCTRL_VFE;
1942
1943         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1944
1945         /* write whatever is in local vfta copy */
1946         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1947                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1948 }
1949
1950 static void
1951 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1952 {
1953         struct ixgbe_hwstrip *hwstrip =
1954                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1955         struct ixgbe_rx_queue *rxq;
1956
1957         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1958                 return;
1959
1960         if (on)
1961                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1962         else
1963                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1964
1965         if (queue >= dev->data->nb_rx_queues)
1966                 return;
1967
1968         rxq = dev->data->rx_queues[queue];
1969
1970         if (on)
1971                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1972         else
1973                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1974 }
1975
1976 static void
1977 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1978 {
1979         struct ixgbe_hw *hw =
1980                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1981         uint32_t ctrl;
1982
1983         PMD_INIT_FUNC_TRACE();
1984
1985         if (hw->mac.type == ixgbe_mac_82598EB) {
1986                 /* No queue level support */
1987                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1988                 return;
1989         }
1990
1991         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1992         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1993         ctrl &= ~IXGBE_RXDCTL_VME;
1994         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1995
1996         /* record those setting for HW strip per queue */
1997         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1998 }
1999
2000 static void
2001 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2002 {
2003         struct ixgbe_hw *hw =
2004                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005         uint32_t ctrl;
2006
2007         PMD_INIT_FUNC_TRACE();
2008
2009         if (hw->mac.type == ixgbe_mac_82598EB) {
2010                 /* No queue level supported */
2011                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2012                 return;
2013         }
2014
2015         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2016         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2017         ctrl |= IXGBE_RXDCTL_VME;
2018         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2019
2020         /* record those setting for HW strip per queue */
2021         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2022 }
2023
2024 void
2025 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2026 {
2027         struct ixgbe_hw *hw =
2028                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029         uint32_t ctrl;
2030         uint16_t i;
2031         struct ixgbe_rx_queue *rxq;
2032
2033         PMD_INIT_FUNC_TRACE();
2034
2035         if (hw->mac.type == ixgbe_mac_82598EB) {
2036                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2037                 ctrl &= ~IXGBE_VLNCTRL_VME;
2038                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2039         } else {
2040                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2041                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2042                         rxq = dev->data->rx_queues[i];
2043                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2044                         ctrl &= ~IXGBE_RXDCTL_VME;
2045                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2046
2047                         /* record those setting for HW strip per queue */
2048                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2049                 }
2050         }
2051 }
2052
2053 void
2054 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2055 {
2056         struct ixgbe_hw *hw =
2057                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2058         uint32_t ctrl;
2059         uint16_t i;
2060         struct ixgbe_rx_queue *rxq;
2061
2062         PMD_INIT_FUNC_TRACE();
2063
2064         if (hw->mac.type == ixgbe_mac_82598EB) {
2065                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2066                 ctrl |= IXGBE_VLNCTRL_VME;
2067                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2068         } else {
2069                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2070                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2071                         rxq = dev->data->rx_queues[i];
2072                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2073                         ctrl |= IXGBE_RXDCTL_VME;
2074                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2075
2076                         /* record those setting for HW strip per queue */
2077                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2078                 }
2079         }
2080 }
2081
2082 static void
2083 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2084 {
2085         struct ixgbe_hw *hw =
2086                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087         uint32_t ctrl;
2088
2089         PMD_INIT_FUNC_TRACE();
2090
2091         /* DMATXCTRL: Geric Double VLAN Disable */
2092         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2093         ctrl &= ~IXGBE_DMATXCTL_GDV;
2094         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2095
2096         /* CTRL_EXT: Global Double VLAN Disable */
2097         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2098         ctrl &= ~IXGBE_EXTENDED_VLAN;
2099         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2100
2101 }
2102
2103 static void
2104 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2105 {
2106         struct ixgbe_hw *hw =
2107                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2108         uint32_t ctrl;
2109
2110         PMD_INIT_FUNC_TRACE();
2111
2112         /* DMATXCTRL: Geric Double VLAN Enable */
2113         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2114         ctrl |= IXGBE_DMATXCTL_GDV;
2115         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2116
2117         /* CTRL_EXT: Global Double VLAN Enable */
2118         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2119         ctrl |= IXGBE_EXTENDED_VLAN;
2120         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2121
2122         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2123         if (hw->mac.type == ixgbe_mac_X550 ||
2124             hw->mac.type == ixgbe_mac_X550EM_x ||
2125             hw->mac.type == ixgbe_mac_X550EM_a) {
2126                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2127                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2128                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2129         }
2130
2131         /*
2132          * VET EXT field in the EXVET register = 0x8100 by default
2133          * So no need to change. Same to VT field of DMATXCTL register
2134          */
2135 }
2136
2137 static void
2138 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2139 {
2140         if (mask & ETH_VLAN_STRIP_MASK) {
2141                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2142                         ixgbe_vlan_hw_strip_enable_all(dev);
2143                 else
2144                         ixgbe_vlan_hw_strip_disable_all(dev);
2145         }
2146
2147         if (mask & ETH_VLAN_FILTER_MASK) {
2148                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2149                         ixgbe_vlan_hw_filter_enable(dev);
2150                 else
2151                         ixgbe_vlan_hw_filter_disable(dev);
2152         }
2153
2154         if (mask & ETH_VLAN_EXTEND_MASK) {
2155                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2156                         ixgbe_vlan_hw_extend_enable(dev);
2157                 else
2158                         ixgbe_vlan_hw_extend_disable(dev);
2159         }
2160 }
2161
2162 static void
2163 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2164 {
2165         struct ixgbe_hw *hw =
2166                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2168         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2169
2170         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2171         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2172 }
2173
2174 static int
2175 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2176 {
2177         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2178
2179         switch (nb_rx_q) {
2180         case 1:
2181         case 2:
2182                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2183                 break;
2184         case 4:
2185                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2186                 break;
2187         default:
2188                 return -EINVAL;
2189         }
2190
2191         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2192         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2193
2194         return 0;
2195 }
2196
2197 static int
2198 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2199 {
2200         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2201         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2203         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2204
2205         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2206                 /* check multi-queue mode */
2207                 switch (dev_conf->rxmode.mq_mode) {
2208                 case ETH_MQ_RX_VMDQ_DCB:
2209                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2210                         break;
2211                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2212                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2213                         PMD_INIT_LOG(ERR, "SRIOV active,"
2214                                         " unsupported mq_mode rx %d.",
2215                                         dev_conf->rxmode.mq_mode);
2216                         return -EINVAL;
2217                 case ETH_MQ_RX_RSS:
2218                 case ETH_MQ_RX_VMDQ_RSS:
2219                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2220                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2221                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2222                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2223                                                 " invalid queue number"
2224                                                 " for VMDQ RSS, allowed"
2225                                                 " value are 1, 2 or 4.");
2226                                         return -EINVAL;
2227                                 }
2228                         break;
2229                 case ETH_MQ_RX_VMDQ_ONLY:
2230                 case ETH_MQ_RX_NONE:
2231                         /* if nothing mq mode configure, use default scheme */
2232                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2233                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2234                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2235                         break;
2236                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2237                         /* SRIOV only works in VMDq enable mode */
2238                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2239                                         " wrong mq_mode rx %d.",
2240                                         dev_conf->rxmode.mq_mode);
2241                         return -EINVAL;
2242                 }
2243
2244                 switch (dev_conf->txmode.mq_mode) {
2245                 case ETH_MQ_TX_VMDQ_DCB:
2246                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2247                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2248                         break;
2249                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2250                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2251                         break;
2252                 }
2253
2254                 /* check valid queue number */
2255                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2256                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2257                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2258                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2259                                         " must be less than or equal to %d.",
2260                                         nb_rx_q, nb_tx_q,
2261                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2262                         return -EINVAL;
2263                 }
2264         } else {
2265                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2266                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2267                                           " not supported.");
2268                         return -EINVAL;
2269                 }
2270                 /* check configuration for vmdb+dcb mode */
2271                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2272                         const struct rte_eth_vmdq_dcb_conf *conf;
2273
2274                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2275                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2276                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2277                                 return -EINVAL;
2278                         }
2279                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2280                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2281                                conf->nb_queue_pools == ETH_32_POOLS)) {
2282                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2283                                                 " nb_queue_pools must be %d or %d.",
2284                                                 ETH_16_POOLS, ETH_32_POOLS);
2285                                 return -EINVAL;
2286                         }
2287                 }
2288                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2289                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2290
2291                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2292                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2293                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2294                                 return -EINVAL;
2295                         }
2296                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2297                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2298                                conf->nb_queue_pools == ETH_32_POOLS)) {
2299                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2300                                                 " nb_queue_pools != %d and"
2301                                                 " nb_queue_pools != %d.",
2302                                                 ETH_16_POOLS, ETH_32_POOLS);
2303                                 return -EINVAL;
2304                         }
2305                 }
2306
2307                 /* For DCB mode check our configuration before we go further */
2308                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2309                         const struct rte_eth_dcb_rx_conf *conf;
2310
2311                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2312                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2313                                                  IXGBE_DCB_NB_QUEUES);
2314                                 return -EINVAL;
2315                         }
2316                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2317                         if (!(conf->nb_tcs == ETH_4_TCS ||
2318                                conf->nb_tcs == ETH_8_TCS)) {
2319                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2320                                                 " and nb_tcs != %d.",
2321                                                 ETH_4_TCS, ETH_8_TCS);
2322                                 return -EINVAL;
2323                         }
2324                 }
2325
2326                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2327                         const struct rte_eth_dcb_tx_conf *conf;
2328
2329                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2330                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2331                                                  IXGBE_DCB_NB_QUEUES);
2332                                 return -EINVAL;
2333                         }
2334                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2335                         if (!(conf->nb_tcs == ETH_4_TCS ||
2336                                conf->nb_tcs == ETH_8_TCS)) {
2337                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2338                                                 " and nb_tcs != %d.",
2339                                                 ETH_4_TCS, ETH_8_TCS);
2340                                 return -EINVAL;
2341                         }
2342                 }
2343
2344                 /*
2345                  * When DCB/VT is off, maximum number of queues changes,
2346                  * except for 82598EB, which remains constant.
2347                  */
2348                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2349                                 hw->mac.type != ixgbe_mac_82598EB) {
2350                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2351                                 PMD_INIT_LOG(ERR,
2352                                              "Neither VT nor DCB are enabled, "
2353                                              "nb_tx_q > %d.",
2354                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2355                                 return -EINVAL;
2356                         }
2357                 }
2358         }
2359         return 0;
2360 }
2361
2362 static int
2363 ixgbe_dev_configure(struct rte_eth_dev *dev)
2364 {
2365         struct ixgbe_interrupt *intr =
2366                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2367         struct ixgbe_adapter *adapter =
2368                 (struct ixgbe_adapter *)dev->data->dev_private;
2369         int ret;
2370
2371         PMD_INIT_FUNC_TRACE();
2372         /* multipe queue mode checking */
2373         ret  = ixgbe_check_mq_mode(dev);
2374         if (ret != 0) {
2375                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2376                             ret);
2377                 return ret;
2378         }
2379
2380         /* set flag to update link status after init */
2381         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2382
2383         /*
2384          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2385          * allocation or vector Rx preconditions we will reset it.
2386          */
2387         adapter->rx_bulk_alloc_allowed = true;
2388         adapter->rx_vec_allowed = true;
2389
2390         return 0;
2391 }
2392
2393 static void
2394 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2395 {
2396         struct ixgbe_hw *hw =
2397                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398         struct ixgbe_interrupt *intr =
2399                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2400         uint32_t gpie;
2401
2402         /* only set up it on X550EM_X */
2403         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2404                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2405                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2406                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2407                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2408                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2409         }
2410 }
2411
2412 int
2413 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2414                         uint16_t tx_rate, uint64_t q_msk)
2415 {
2416         struct ixgbe_hw *hw;
2417         struct ixgbe_vf_info *vfinfo;
2418         struct rte_eth_link link;
2419         uint8_t  nb_q_per_pool;
2420         uint32_t queue_stride;
2421         uint32_t queue_idx, idx = 0, vf_idx;
2422         uint32_t queue_end;
2423         uint16_t total_rate = 0;
2424         struct rte_pci_device *pci_dev;
2425
2426         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2427         rte_eth_link_get_nowait(dev->data->port_id, &link);
2428
2429         if (vf >= pci_dev->max_vfs)
2430                 return -EINVAL;
2431
2432         if (tx_rate > link.link_speed)
2433                 return -EINVAL;
2434
2435         if (q_msk == 0)
2436                 return 0;
2437
2438         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2439         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2440         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2441         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2442         queue_idx = vf * queue_stride;
2443         queue_end = queue_idx + nb_q_per_pool - 1;
2444         if (queue_end >= hw->mac.max_tx_queues)
2445                 return -EINVAL;
2446
2447         if (vfinfo) {
2448                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2449                         if (vf_idx == vf)
2450                                 continue;
2451                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2452                                 idx++)
2453                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2454                 }
2455         } else {
2456                 return -EINVAL;
2457         }
2458
2459         /* Store tx_rate for this vf. */
2460         for (idx = 0; idx < nb_q_per_pool; idx++) {
2461                 if (((uint64_t)0x1 << idx) & q_msk) {
2462                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2463                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2464                         total_rate += tx_rate;
2465                 }
2466         }
2467
2468         if (total_rate > dev->data->dev_link.link_speed) {
2469                 /* Reset stored TX rate of the VF if it causes exceed
2470                  * link speed.
2471                  */
2472                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2473                 return -EINVAL;
2474         }
2475
2476         /* Set RTTBCNRC of each queue/pool for vf X  */
2477         for (; queue_idx <= queue_end; queue_idx++) {
2478                 if (0x1 & q_msk)
2479                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2480                 q_msk = q_msk >> 1;
2481         }
2482
2483         return 0;
2484 }
2485
2486 /*
2487  * Configure device link speed and setup link.
2488  * It returns 0 on success.
2489  */
2490 static int
2491 ixgbe_dev_start(struct rte_eth_dev *dev)
2492 {
2493         struct ixgbe_hw *hw =
2494                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2495         struct ixgbe_vf_info *vfinfo =
2496                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2497         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2498         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2499         uint32_t intr_vector = 0;
2500         int err, link_up = 0, negotiate = 0;
2501         uint32_t speed = 0;
2502         int mask = 0;
2503         int status;
2504         uint16_t vf, idx;
2505         uint32_t *link_speeds;
2506         struct ixgbe_tm_conf *tm_conf =
2507                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2508
2509         PMD_INIT_FUNC_TRACE();
2510
2511         /* IXGBE devices don't support:
2512         *    - half duplex (checked afterwards for valid speeds)
2513         *    - fixed speed: TODO implement
2514         */
2515         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2516                 PMD_INIT_LOG(ERR,
2517                 "Invalid link_speeds for port %u, fix speed not supported",
2518                                 dev->data->port_id);
2519                 return -EINVAL;
2520         }
2521
2522         /* disable uio/vfio intr/eventfd mapping */
2523         rte_intr_disable(intr_handle);
2524
2525         /* stop adapter */
2526         hw->adapter_stopped = 0;
2527         ixgbe_stop_adapter(hw);
2528
2529         /* reinitialize adapter
2530          * this calls reset and start
2531          */
2532         status = ixgbe_pf_reset_hw(hw);
2533         if (status != 0)
2534                 return -1;
2535         hw->mac.ops.start_hw(hw);
2536         hw->mac.get_link_status = true;
2537
2538         /* configure PF module if SRIOV enabled */
2539         ixgbe_pf_host_configure(dev);
2540
2541         ixgbe_dev_phy_intr_setup(dev);
2542
2543         /* check and configure queue intr-vector mapping */
2544         if ((rte_intr_cap_multiple(intr_handle) ||
2545              !RTE_ETH_DEV_SRIOV(dev).active) &&
2546             dev->data->dev_conf.intr_conf.rxq != 0) {
2547                 intr_vector = dev->data->nb_rx_queues;
2548                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2549                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2550                                         IXGBE_MAX_INTR_QUEUE_NUM);
2551                         return -ENOTSUP;
2552                 }
2553                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2554                         return -1;
2555         }
2556
2557         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2558                 intr_handle->intr_vec =
2559                         rte_zmalloc("intr_vec",
2560                                     dev->data->nb_rx_queues * sizeof(int), 0);
2561                 if (intr_handle->intr_vec == NULL) {
2562                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2563                                      " intr_vec", dev->data->nb_rx_queues);
2564                         return -ENOMEM;
2565                 }
2566         }
2567
2568         /* confiugre msix for sleep until rx interrupt */
2569         ixgbe_configure_msix(dev);
2570
2571         /* initialize transmission unit */
2572         ixgbe_dev_tx_init(dev);
2573
2574         /* This can fail when allocating mbufs for descriptor rings */
2575         err = ixgbe_dev_rx_init(dev);
2576         if (err) {
2577                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2578                 goto error;
2579         }
2580
2581     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2582                 ETH_VLAN_EXTEND_MASK;
2583         ixgbe_vlan_offload_set(dev, mask);
2584
2585         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2586                 /* Enable vlan filtering for VMDq */
2587                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2588         }
2589
2590         /* Configure DCB hw */
2591         ixgbe_configure_dcb(dev);
2592
2593         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2594                 err = ixgbe_fdir_configure(dev);
2595                 if (err)
2596                         goto error;
2597         }
2598
2599         /* Restore vf rate limit */
2600         if (vfinfo != NULL) {
2601                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2602                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2603                                 if (vfinfo[vf].tx_rate[idx] != 0)
2604                                         ixgbe_set_vf_rate_limit(
2605                                                 dev, vf,
2606                                                 vfinfo[vf].tx_rate[idx],
2607                                                 1 << idx);
2608         }
2609
2610         ixgbe_restore_statistics_mapping(dev);
2611
2612         err = ixgbe_dev_rxtx_start(dev);
2613         if (err < 0) {
2614                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2615                 goto error;
2616         }
2617
2618         /* Skip link setup if loopback mode is enabled for 82599. */
2619         if (hw->mac.type == ixgbe_mac_82599EB &&
2620                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2621                 goto skip_link_setup;
2622
2623         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2624                 err = hw->mac.ops.setup_sfp(hw);
2625                 if (err)
2626                         goto error;
2627         }
2628
2629         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2630                 /* Turn on the copper */
2631                 ixgbe_set_phy_power(hw, true);
2632         } else {
2633                 /* Turn on the laser */
2634                 ixgbe_enable_tx_laser(hw);
2635         }
2636
2637         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2638         if (err)
2639                 goto error;
2640         dev->data->dev_link.link_status = link_up;
2641
2642         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2643         if (err)
2644                 goto error;
2645
2646         link_speeds = &dev->data->dev_conf.link_speeds;
2647         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2648                         ETH_LINK_SPEED_10G)) {
2649                 PMD_INIT_LOG(ERR, "Invalid link setting");
2650                 goto error;
2651         }
2652
2653         speed = 0x0;
2654         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2655                 switch (hw->mac.type) {
2656                 case ixgbe_mac_82598EB:
2657                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2658                         break;
2659                 case ixgbe_mac_82599EB:
2660                 case ixgbe_mac_X540:
2661                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2662                         break;
2663                 case ixgbe_mac_X550:
2664                 case ixgbe_mac_X550EM_x:
2665                 case ixgbe_mac_X550EM_a:
2666                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2667                         break;
2668                 default:
2669                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2670                 }
2671         } else {
2672                 if (*link_speeds & ETH_LINK_SPEED_10G)
2673                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2674                 if (*link_speeds & ETH_LINK_SPEED_1G)
2675                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2676                 if (*link_speeds & ETH_LINK_SPEED_100M)
2677                         speed |= IXGBE_LINK_SPEED_100_FULL;
2678         }
2679
2680         err = ixgbe_setup_link(hw, speed, link_up);
2681         if (err)
2682                 goto error;
2683
2684 skip_link_setup:
2685
2686         if (rte_intr_allow_others(intr_handle)) {
2687                 /* check if lsc interrupt is enabled */
2688                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2689                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2690                 else
2691                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2692                 ixgbe_dev_macsec_interrupt_setup(dev);
2693         } else {
2694                 rte_intr_callback_unregister(intr_handle,
2695                                              ixgbe_dev_interrupt_handler, dev);
2696                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2697                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2698                                      " no intr multiplex");
2699         }
2700
2701         /* check if rxq interrupt is enabled */
2702         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2703             rte_intr_dp_is_en(intr_handle))
2704                 ixgbe_dev_rxq_interrupt_setup(dev);
2705
2706         /* enable uio/vfio intr/eventfd mapping */
2707         rte_intr_enable(intr_handle);
2708
2709         /* resume enabled intr since hw reset */
2710         ixgbe_enable_intr(dev);
2711         ixgbe_l2_tunnel_conf(dev);
2712         ixgbe_filter_restore(dev);
2713
2714         if (tm_conf->root && !tm_conf->committed)
2715                 PMD_DRV_LOG(WARNING,
2716                             "please call hierarchy_commit() "
2717                             "before starting the port");
2718
2719         return 0;
2720
2721 error:
2722         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2723         ixgbe_dev_clear_queues(dev);
2724         return -EIO;
2725 }
2726
2727 /*
2728  * Stop device: disable rx and tx functions to allow for reconfiguring.
2729  */
2730 static void
2731 ixgbe_dev_stop(struct rte_eth_dev *dev)
2732 {
2733         struct rte_eth_link link;
2734         struct ixgbe_hw *hw =
2735                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2736         struct ixgbe_vf_info *vfinfo =
2737                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2738         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2739         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2740         int vf;
2741         struct ixgbe_tm_conf *tm_conf =
2742                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2743
2744         PMD_INIT_FUNC_TRACE();
2745
2746         /* disable interrupts */
2747         ixgbe_disable_intr(hw);
2748
2749         /* reset the NIC */
2750         ixgbe_pf_reset_hw(hw);
2751         hw->adapter_stopped = 0;
2752
2753         /* stop adapter */
2754         ixgbe_stop_adapter(hw);
2755
2756         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2757                 vfinfo[vf].clear_to_send = false;
2758
2759         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2760                 /* Turn off the copper */
2761                 ixgbe_set_phy_power(hw, false);
2762         } else {
2763                 /* Turn off the laser */
2764                 ixgbe_disable_tx_laser(hw);
2765         }
2766
2767         ixgbe_dev_clear_queues(dev);
2768
2769         /* Clear stored conf */
2770         dev->data->scattered_rx = 0;
2771         dev->data->lro = 0;
2772
2773         /* Clear recorded link status */
2774         memset(&link, 0, sizeof(link));
2775         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2776
2777         if (!rte_intr_allow_others(intr_handle))
2778                 /* resume to the default handler */
2779                 rte_intr_callback_register(intr_handle,
2780                                            ixgbe_dev_interrupt_handler,
2781                                            (void *)dev);
2782
2783         /* Clean datapath event and queue/vec mapping */
2784         rte_intr_efd_disable(intr_handle);
2785         if (intr_handle->intr_vec != NULL) {
2786                 rte_free(intr_handle->intr_vec);
2787                 intr_handle->intr_vec = NULL;
2788         }
2789
2790         /* reset hierarchy commit */
2791         tm_conf->committed = false;
2792 }
2793
2794 /*
2795  * Set device link up: enable tx.
2796  */
2797 static int
2798 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2799 {
2800         struct ixgbe_hw *hw =
2801                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2802         if (hw->mac.type == ixgbe_mac_82599EB) {
2803 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2804                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2805                         /* Not suported in bypass mode */
2806                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2807                                      "by device id 0x%x", hw->device_id);
2808                         return -ENOTSUP;
2809                 }
2810 #endif
2811         }
2812
2813         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2814                 /* Turn on the copper */
2815                 ixgbe_set_phy_power(hw, true);
2816         } else {
2817                 /* Turn on the laser */
2818                 ixgbe_enable_tx_laser(hw);
2819         }
2820
2821         return 0;
2822 }
2823
2824 /*
2825  * Set device link down: disable tx.
2826  */
2827 static int
2828 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2829 {
2830         struct ixgbe_hw *hw =
2831                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832         if (hw->mac.type == ixgbe_mac_82599EB) {
2833 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2834                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2835                         /* Not suported in bypass mode */
2836                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2837                                      "by device id 0x%x", hw->device_id);
2838                         return -ENOTSUP;
2839                 }
2840 #endif
2841         }
2842
2843         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2844                 /* Turn off the copper */
2845                 ixgbe_set_phy_power(hw, false);
2846         } else {
2847                 /* Turn off the laser */
2848                 ixgbe_disable_tx_laser(hw);
2849         }
2850
2851         return 0;
2852 }
2853
2854 /*
2855  * Reset and stop device.
2856  */
2857 static void
2858 ixgbe_dev_close(struct rte_eth_dev *dev)
2859 {
2860         struct ixgbe_hw *hw =
2861                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862
2863         PMD_INIT_FUNC_TRACE();
2864
2865         ixgbe_pf_reset_hw(hw);
2866
2867         ixgbe_dev_stop(dev);
2868         hw->adapter_stopped = 1;
2869
2870         ixgbe_dev_free_queues(dev);
2871
2872         ixgbe_disable_pcie_master(hw);
2873
2874         /* reprogram the RAR[0] in case user changed it. */
2875         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2876 }
2877
2878 /*
2879  * Reset PF device.
2880  */
2881 static int
2882 ixgbe_dev_reset(struct rte_eth_dev *dev)
2883 {
2884         int ret;
2885
2886         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2887          * its VF to make them align with it. The detailed notification
2888          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2889          * To avoid unexpected behavior in VF, currently reset of PF with
2890          * SR-IOV activation is not supported. It might be supported later.
2891          */
2892         if (dev->data->sriov.active)
2893                 return -ENOTSUP;
2894
2895         ret = eth_ixgbe_dev_uninit(dev);
2896         if (ret)
2897                 return ret;
2898
2899         ret = eth_ixgbe_dev_init(dev);
2900
2901         return ret;
2902 }
2903
2904 static void
2905 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2906                            struct ixgbe_hw_stats *hw_stats,
2907                            struct ixgbe_macsec_stats *macsec_stats,
2908                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2909                            uint64_t *total_qprc, uint64_t *total_qprdc)
2910 {
2911         uint32_t bprc, lxon, lxoff, total;
2912         uint32_t delta_gprc = 0;
2913         unsigned i;
2914         /* Workaround for RX byte count not including CRC bytes when CRC
2915          * strip is enabled. CRC bytes are removed from counters when crc_strip
2916          * is disabled.
2917          */
2918         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2919                         IXGBE_HLREG0_RXCRCSTRP);
2920
2921         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2922         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2923         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2924         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2925
2926         for (i = 0; i < 8; i++) {
2927                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2928
2929                 /* global total per queue */
2930                 hw_stats->mpc[i] += mp;
2931                 /* Running comprehensive total for stats display */
2932                 *total_missed_rx += hw_stats->mpc[i];
2933                 if (hw->mac.type == ixgbe_mac_82598EB) {
2934                         hw_stats->rnbc[i] +=
2935                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2936                         hw_stats->pxonrxc[i] +=
2937                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2938                         hw_stats->pxoffrxc[i] +=
2939                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2940                 } else {
2941                         hw_stats->pxonrxc[i] +=
2942                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2943                         hw_stats->pxoffrxc[i] +=
2944                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2945                         hw_stats->pxon2offc[i] +=
2946                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2947                 }
2948                 hw_stats->pxontxc[i] +=
2949                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2950                 hw_stats->pxofftxc[i] +=
2951                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2952         }
2953         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2954                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2955                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2956                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2957
2958                 delta_gprc += delta_qprc;
2959
2960                 hw_stats->qprc[i] += delta_qprc;
2961                 hw_stats->qptc[i] += delta_qptc;
2962
2963                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2964                 hw_stats->qbrc[i] +=
2965                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2966                 if (crc_strip == 0)
2967                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2968
2969                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2970                 hw_stats->qbtc[i] +=
2971                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2972
2973                 hw_stats->qprdc[i] += delta_qprdc;
2974                 *total_qprdc += hw_stats->qprdc[i];
2975
2976                 *total_qprc += hw_stats->qprc[i];
2977                 *total_qbrc += hw_stats->qbrc[i];
2978         }
2979         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2980         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2981         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2982
2983         /*
2984          * An errata states that gprc actually counts good + missed packets:
2985          * Workaround to set gprc to summated queue packet receives
2986          */
2987         hw_stats->gprc = *total_qprc;
2988
2989         if (hw->mac.type != ixgbe_mac_82598EB) {
2990                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2991                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2992                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2993                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2994                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2995                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2996                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2997                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2998         } else {
2999                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3000                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3001                 /* 82598 only has a counter in the high register */
3002                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3003                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3004                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3005         }
3006         uint64_t old_tpr = hw_stats->tpr;
3007
3008         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3009         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3010
3011         if (crc_strip == 0)
3012                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3013
3014         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3015         hw_stats->gptc += delta_gptc;
3016         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3017         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3018
3019         /*
3020          * Workaround: mprc hardware is incorrectly counting
3021          * broadcasts, so for now we subtract those.
3022          */
3023         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3024         hw_stats->bprc += bprc;
3025         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3026         if (hw->mac.type == ixgbe_mac_82598EB)
3027                 hw_stats->mprc -= bprc;
3028
3029         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3030         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3031         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3032         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3033         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3034         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3035
3036         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3037         hw_stats->lxontxc += lxon;
3038         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3039         hw_stats->lxofftxc += lxoff;
3040         total = lxon + lxoff;
3041
3042         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3043         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3044         hw_stats->gptc -= total;
3045         hw_stats->mptc -= total;
3046         hw_stats->ptc64 -= total;
3047         hw_stats->gotc -= total * ETHER_MIN_LEN;
3048
3049         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3050         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3051         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3052         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3053         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3054         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3055         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3056         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3057         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3058         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3059         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3060         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3061         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3062         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3063         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3064         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3065         /* Only read FCOE on 82599 */
3066         if (hw->mac.type != ixgbe_mac_82598EB) {
3067                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3068                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3069                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3070                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3071                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3072         }
3073
3074         /* Flow Director Stats registers */
3075         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3076         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3077
3078         /* MACsec Stats registers */
3079         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3080         macsec_stats->out_pkts_encrypted +=
3081                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3082         macsec_stats->out_pkts_protected +=
3083                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3084         macsec_stats->out_octets_encrypted +=
3085                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3086         macsec_stats->out_octets_protected +=
3087                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3088         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3089         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3090         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3091         macsec_stats->in_pkts_unknownsci +=
3092                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3093         macsec_stats->in_octets_decrypted +=
3094                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3095         macsec_stats->in_octets_validated +=
3096                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3097         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3098         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3099         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3100         for (i = 0; i < 2; i++) {
3101                 macsec_stats->in_pkts_ok +=
3102                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3103                 macsec_stats->in_pkts_invalid +=
3104                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3105                 macsec_stats->in_pkts_notvalid +=
3106                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3107         }
3108         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3109         macsec_stats->in_pkts_notusingsa +=
3110                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3111 }
3112
3113 /*
3114  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3115  */
3116 static int
3117 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3118 {
3119         struct ixgbe_hw *hw =
3120                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3121         struct ixgbe_hw_stats *hw_stats =
3122                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3123         struct ixgbe_macsec_stats *macsec_stats =
3124                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3125                                 dev->data->dev_private);
3126         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3127         unsigned i;
3128
3129         total_missed_rx = 0;
3130         total_qbrc = 0;
3131         total_qprc = 0;
3132         total_qprdc = 0;
3133
3134         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3135                         &total_qbrc, &total_qprc, &total_qprdc);
3136
3137         if (stats == NULL)
3138                 return -EINVAL;
3139
3140         /* Fill out the rte_eth_stats statistics structure */
3141         stats->ipackets = total_qprc;
3142         stats->ibytes = total_qbrc;
3143         stats->opackets = hw_stats->gptc;
3144         stats->obytes = hw_stats->gotc;
3145
3146         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3147                 stats->q_ipackets[i] = hw_stats->qprc[i];
3148                 stats->q_opackets[i] = hw_stats->qptc[i];
3149                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3150                 stats->q_obytes[i] = hw_stats->qbtc[i];
3151                 stats->q_errors[i] = hw_stats->qprdc[i];
3152         }
3153
3154         /* Rx Errors */
3155         stats->imissed  = total_missed_rx;
3156         stats->ierrors  = hw_stats->crcerrs +
3157                           hw_stats->mspdc +
3158                           hw_stats->rlec +
3159                           hw_stats->ruc +
3160                           hw_stats->roc +
3161                           hw_stats->illerrc +
3162                           hw_stats->errbc +
3163                           hw_stats->rfc +
3164                           hw_stats->fccrc +
3165                           hw_stats->fclast;
3166
3167         /* Tx Errors */
3168         stats->oerrors  = 0;
3169         return 0;
3170 }
3171
3172 static void
3173 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3174 {
3175         struct ixgbe_hw_stats *stats =
3176                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3177
3178         /* HW registers are cleared on read */
3179         ixgbe_dev_stats_get(dev, NULL);
3180
3181         /* Reset software totals */
3182         memset(stats, 0, sizeof(*stats));
3183 }
3184
3185 /* This function calculates the number of xstats based on the current config */
3186 static unsigned
3187 ixgbe_xstats_calc_num(void) {
3188         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3189                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3190                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3191 }
3192
3193 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3194         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3195 {
3196         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3197         unsigned stat, i, count;
3198
3199         if (xstats_names != NULL) {
3200                 count = 0;
3201
3202                 /* Note: limit >= cnt_stats checked upstream
3203                  * in rte_eth_xstats_names()
3204                  */
3205
3206                 /* Extended stats from ixgbe_hw_stats */
3207                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3208                         snprintf(xstats_names[count].name,
3209                                 sizeof(xstats_names[count].name),
3210                                 "%s",
3211                                 rte_ixgbe_stats_strings[i].name);
3212                         count++;
3213                 }
3214
3215                 /* MACsec Stats */
3216                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3217                         snprintf(xstats_names[count].name,
3218                                 sizeof(xstats_names[count].name),
3219                                 "%s",
3220                                 rte_ixgbe_macsec_strings[i].name);
3221                         count++;
3222                 }
3223
3224                 /* RX Priority Stats */
3225                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3226                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3227                                 snprintf(xstats_names[count].name,
3228                                         sizeof(xstats_names[count].name),
3229                                         "rx_priority%u_%s", i,
3230                                         rte_ixgbe_rxq_strings[stat].name);
3231                                 count++;
3232                         }
3233                 }
3234
3235                 /* TX Priority Stats */
3236                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3237                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3238                                 snprintf(xstats_names[count].name,
3239                                         sizeof(xstats_names[count].name),
3240                                         "tx_priority%u_%s", i,
3241                                         rte_ixgbe_txq_strings[stat].name);
3242                                 count++;
3243                         }
3244                 }
3245         }
3246         return cnt_stats;
3247 }
3248
3249 static int ixgbe_dev_xstats_get_names_by_id(
3250         struct rte_eth_dev *dev,
3251         struct rte_eth_xstat_name *xstats_names,
3252         const uint64_t *ids,
3253         unsigned int limit)
3254 {
3255         if (!ids) {
3256                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3257                 unsigned int stat, i, count;
3258
3259                 if (xstats_names != NULL) {
3260                         count = 0;
3261
3262                         /* Note: limit >= cnt_stats checked upstream
3263                          * in rte_eth_xstats_names()
3264                          */
3265
3266                         /* Extended stats from ixgbe_hw_stats */
3267                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3268                                 snprintf(xstats_names[count].name,
3269                                         sizeof(xstats_names[count].name),
3270                                         "%s",
3271                                         rte_ixgbe_stats_strings[i].name);
3272                                 count++;
3273                         }
3274
3275                         /* MACsec Stats */
3276                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3277                                 snprintf(xstats_names[count].name,
3278                                         sizeof(xstats_names[count].name),
3279                                         "%s",
3280                                         rte_ixgbe_macsec_strings[i].name);
3281                                 count++;
3282                         }
3283
3284                         /* RX Priority Stats */
3285                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3286                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3287                                         snprintf(xstats_names[count].name,
3288                                             sizeof(xstats_names[count].name),
3289                                             "rx_priority%u_%s", i,
3290                                             rte_ixgbe_rxq_strings[stat].name);
3291                                         count++;
3292                                 }
3293                         }
3294
3295                         /* TX Priority Stats */
3296                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3297                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3298                                         snprintf(xstats_names[count].name,
3299                                             sizeof(xstats_names[count].name),
3300                                             "tx_priority%u_%s", i,
3301                                             rte_ixgbe_txq_strings[stat].name);
3302                                         count++;
3303                                 }
3304                         }
3305                 }
3306                 return cnt_stats;
3307         }
3308
3309         uint16_t i;
3310         uint16_t size = ixgbe_xstats_calc_num();
3311         struct rte_eth_xstat_name xstats_names_copy[size];
3312
3313         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3314                         size);
3315
3316         for (i = 0; i < limit; i++) {
3317                 if (ids[i] >= size) {
3318                         PMD_INIT_LOG(ERR, "id value isn't valid");
3319                         return -1;
3320                 }
3321                 strcpy(xstats_names[i].name,
3322                                 xstats_names_copy[ids[i]].name);
3323         }
3324         return limit;
3325 }
3326
3327 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3328         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3329 {
3330         unsigned i;
3331
3332         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3333                 return -ENOMEM;
3334
3335         if (xstats_names != NULL)
3336                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3337                         snprintf(xstats_names[i].name,
3338                                 sizeof(xstats_names[i].name),
3339                                 "%s", rte_ixgbevf_stats_strings[i].name);
3340         return IXGBEVF_NB_XSTATS;
3341 }
3342
3343 static int
3344 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3345                                          unsigned n)
3346 {
3347         struct ixgbe_hw *hw =
3348                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3349         struct ixgbe_hw_stats *hw_stats =
3350                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3351         struct ixgbe_macsec_stats *macsec_stats =
3352                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3353                                 dev->data->dev_private);
3354         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3355         unsigned i, stat, count = 0;
3356
3357         count = ixgbe_xstats_calc_num();
3358
3359         if (n < count)
3360                 return count;
3361
3362         total_missed_rx = 0;
3363         total_qbrc = 0;
3364         total_qprc = 0;
3365         total_qprdc = 0;
3366
3367         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3368                         &total_qbrc, &total_qprc, &total_qprdc);
3369
3370         /* If this is a reset xstats is NULL, and we have cleared the
3371          * registers by reading them.
3372          */
3373         if (!xstats)
3374                 return 0;
3375
3376         /* Extended stats from ixgbe_hw_stats */
3377         count = 0;
3378         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3379                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3380                                 rte_ixgbe_stats_strings[i].offset);
3381                 xstats[count].id = count;
3382                 count++;
3383         }
3384
3385         /* MACsec Stats */
3386         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3387                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3388                                 rte_ixgbe_macsec_strings[i].offset);
3389                 xstats[count].id = count;
3390                 count++;
3391         }
3392
3393         /* RX Priority Stats */
3394         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3395                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3396                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3397                                         rte_ixgbe_rxq_strings[stat].offset +
3398                                         (sizeof(uint64_t) * i));
3399                         xstats[count].id = count;
3400                         count++;
3401                 }
3402         }
3403
3404         /* TX Priority Stats */
3405         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3406                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3407                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3408                                         rte_ixgbe_txq_strings[stat].offset +
3409                                         (sizeof(uint64_t) * i));
3410                         xstats[count].id = count;
3411                         count++;
3412                 }
3413         }
3414         return count;
3415 }
3416
3417 static int
3418 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3419                 uint64_t *values, unsigned int n)
3420 {
3421         if (!ids) {
3422                 struct ixgbe_hw *hw =
3423                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3424                 struct ixgbe_hw_stats *hw_stats =
3425                                 IXGBE_DEV_PRIVATE_TO_STATS(
3426                                                 dev->data->dev_private);
3427                 struct ixgbe_macsec_stats *macsec_stats =
3428                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3429                                         dev->data->dev_private);
3430                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3431                 unsigned int i, stat, count = 0;
3432
3433                 count = ixgbe_xstats_calc_num();
3434
3435                 if (!ids && n < count)
3436                         return count;
3437
3438                 total_missed_rx = 0;
3439                 total_qbrc = 0;
3440                 total_qprc = 0;
3441                 total_qprdc = 0;
3442
3443                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3444                                 &total_missed_rx, &total_qbrc, &total_qprc,
3445                                 &total_qprdc);
3446
3447                 /* If this is a reset xstats is NULL, and we have cleared the
3448                  * registers by reading them.
3449                  */
3450                 if (!ids && !values)
3451                         return 0;
3452
3453                 /* Extended stats from ixgbe_hw_stats */
3454                 count = 0;
3455                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3456                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3457                                         rte_ixgbe_stats_strings[i].offset);
3458                         count++;
3459                 }
3460
3461                 /* MACsec Stats */
3462                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3463                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3464                                         rte_ixgbe_macsec_strings[i].offset);
3465                         count++;
3466                 }
3467
3468                 /* RX Priority Stats */
3469                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3470                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3471                                 values[count] =
3472                                         *(uint64_t *)(((char *)hw_stats) +
3473                                         rte_ixgbe_rxq_strings[stat].offset +
3474                                         (sizeof(uint64_t) * i));
3475                                 count++;
3476                         }
3477                 }
3478
3479                 /* TX Priority Stats */
3480                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3481                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3482                                 values[count] =
3483                                         *(uint64_t *)(((char *)hw_stats) +
3484                                         rte_ixgbe_txq_strings[stat].offset +
3485                                         (sizeof(uint64_t) * i));
3486                                 count++;
3487                         }
3488                 }
3489                 return count;
3490         }
3491
3492         uint16_t i;
3493         uint16_t size = ixgbe_xstats_calc_num();
3494         uint64_t values_copy[size];
3495
3496         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3497
3498         for (i = 0; i < n; i++) {
3499                 if (ids[i] >= size) {
3500                         PMD_INIT_LOG(ERR, "id value isn't valid");
3501                         return -1;
3502                 }
3503                 values[i] = values_copy[ids[i]];
3504         }
3505         return n;
3506 }
3507
3508 static void
3509 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3510 {
3511         struct ixgbe_hw_stats *stats =
3512                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3513         struct ixgbe_macsec_stats *macsec_stats =
3514                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3515                                 dev->data->dev_private);
3516
3517         unsigned count = ixgbe_xstats_calc_num();
3518
3519         /* HW registers are cleared on read */
3520         ixgbe_dev_xstats_get(dev, NULL, count);
3521
3522         /* Reset software totals */
3523         memset(stats, 0, sizeof(*stats));
3524         memset(macsec_stats, 0, sizeof(*macsec_stats));
3525 }
3526
3527 static void
3528 ixgbevf_update_stats(struct rte_eth_dev *dev)
3529 {
3530         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3531         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3532                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3533
3534         /* Good Rx packet, include VF loopback */
3535         UPDATE_VF_STAT(IXGBE_VFGPRC,
3536             hw_stats->last_vfgprc, hw_stats->vfgprc);
3537
3538         /* Good Rx octets, include VF loopback */
3539         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3540             hw_stats->last_vfgorc, hw_stats->vfgorc);
3541
3542         /* Good Tx packet, include VF loopback */
3543         UPDATE_VF_STAT(IXGBE_VFGPTC,
3544             hw_stats->last_vfgptc, hw_stats->vfgptc);
3545
3546         /* Good Tx octets, include VF loopback */
3547         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3548             hw_stats->last_vfgotc, hw_stats->vfgotc);
3549
3550         /* Rx Multicst Packet */
3551         UPDATE_VF_STAT(IXGBE_VFMPRC,
3552             hw_stats->last_vfmprc, hw_stats->vfmprc);
3553 }
3554
3555 static int
3556 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3557                        unsigned n)
3558 {
3559         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3560                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3561         unsigned i;
3562
3563         if (n < IXGBEVF_NB_XSTATS)
3564                 return IXGBEVF_NB_XSTATS;
3565
3566         ixgbevf_update_stats(dev);
3567
3568         if (!xstats)
3569                 return 0;
3570
3571         /* Extended stats */
3572         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3573                 xstats[i].id = i;
3574                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3575                         rte_ixgbevf_stats_strings[i].offset);
3576         }
3577
3578         return IXGBEVF_NB_XSTATS;
3579 }
3580
3581 static int
3582 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3583 {
3584         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3585                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3586
3587         ixgbevf_update_stats(dev);
3588
3589         if (stats == NULL)
3590                 return -EINVAL;
3591
3592         stats->ipackets = hw_stats->vfgprc;
3593         stats->ibytes = hw_stats->vfgorc;
3594         stats->opackets = hw_stats->vfgptc;
3595         stats->obytes = hw_stats->vfgotc;
3596         return 0;
3597 }
3598
3599 static void
3600 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3601 {
3602         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3603                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3604
3605         /* Sync HW register to the last stats */
3606         ixgbevf_dev_stats_get(dev, NULL);
3607
3608         /* reset HW current stats*/
3609         hw_stats->vfgprc = 0;
3610         hw_stats->vfgorc = 0;
3611         hw_stats->vfgptc = 0;
3612         hw_stats->vfgotc = 0;
3613 }
3614
3615 static int
3616 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3617 {
3618         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619         u16 eeprom_verh, eeprom_verl;
3620         u32 etrack_id;
3621         int ret;
3622
3623         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3624         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3625
3626         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3627         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3628
3629         ret += 1; /* add the size of '\0' */
3630         if (fw_size < (u32)ret)
3631                 return ret;
3632         else
3633                 return 0;
3634 }
3635
3636 static void
3637 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3638 {
3639         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3640         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3641         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3642
3643         dev_info->pci_dev = pci_dev;
3644         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3645         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3646         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3647                 /*
3648                  * When DCB/VT is off, maximum number of queues changes,
3649                  * except for 82598EB, which remains constant.
3650                  */
3651                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3652                                 hw->mac.type != ixgbe_mac_82598EB)
3653                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3654         }
3655         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3656         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3657         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3658         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3659         dev_info->max_vfs = pci_dev->max_vfs;
3660         if (hw->mac.type == ixgbe_mac_82598EB)
3661                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3662         else
3663                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3664         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3665         dev_info->rx_offload_capa =
3666                 DEV_RX_OFFLOAD_VLAN_STRIP |
3667                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3668                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3669                 DEV_RX_OFFLOAD_TCP_CKSUM;
3670
3671         /*
3672          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3673          * mode.
3674          */
3675         if ((hw->mac.type == ixgbe_mac_82599EB ||
3676              hw->mac.type == ixgbe_mac_X540) &&
3677             !RTE_ETH_DEV_SRIOV(dev).active)
3678                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3679
3680         if (hw->mac.type == ixgbe_mac_82599EB ||
3681             hw->mac.type == ixgbe_mac_X540)
3682                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3683
3684         if (hw->mac.type == ixgbe_mac_X550 ||
3685             hw->mac.type == ixgbe_mac_X550EM_x ||
3686             hw->mac.type == ixgbe_mac_X550EM_a)
3687                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3688
3689         dev_info->tx_offload_capa =
3690                 DEV_TX_OFFLOAD_VLAN_INSERT |
3691                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3692                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3693                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3694                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3695                 DEV_TX_OFFLOAD_TCP_TSO;
3696
3697         if (hw->mac.type == ixgbe_mac_82599EB ||
3698             hw->mac.type == ixgbe_mac_X540)
3699                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3700
3701         if (hw->mac.type == ixgbe_mac_X550 ||
3702             hw->mac.type == ixgbe_mac_X550EM_x ||
3703             hw->mac.type == ixgbe_mac_X550EM_a)
3704                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3705
3706         dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3707         dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3708
3709         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3710                 .rx_thresh = {
3711                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3712                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3713                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3714                 },
3715                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3716                 .rx_drop_en = 0,
3717         };
3718
3719         dev_info->default_txconf = (struct rte_eth_txconf) {
3720                 .tx_thresh = {
3721                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3722                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3723                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3724                 },
3725                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3726                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3727                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3728                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3729         };
3730
3731         dev_info->rx_desc_lim = rx_desc_lim;
3732         dev_info->tx_desc_lim = tx_desc_lim;
3733
3734         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3735         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3736         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3737
3738         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3739         if (hw->mac.type == ixgbe_mac_X540 ||
3740             hw->mac.type == ixgbe_mac_X540_vf ||
3741             hw->mac.type == ixgbe_mac_X550 ||
3742             hw->mac.type == ixgbe_mac_X550_vf) {
3743                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3744         }
3745         if (hw->mac.type == ixgbe_mac_X550) {
3746                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3747                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3748         }
3749 }
3750
3751 static const uint32_t *
3752 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3753 {
3754         static const uint32_t ptypes[] = {
3755                 /* For non-vec functions,
3756                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3757                  * for vec functions,
3758                  * refers to _recv_raw_pkts_vec().
3759                  */
3760                 RTE_PTYPE_L2_ETHER,
3761                 RTE_PTYPE_L3_IPV4,
3762                 RTE_PTYPE_L3_IPV4_EXT,
3763                 RTE_PTYPE_L3_IPV6,
3764                 RTE_PTYPE_L3_IPV6_EXT,
3765                 RTE_PTYPE_L4_SCTP,
3766                 RTE_PTYPE_L4_TCP,
3767                 RTE_PTYPE_L4_UDP,
3768                 RTE_PTYPE_TUNNEL_IP,
3769                 RTE_PTYPE_INNER_L3_IPV6,
3770                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3771                 RTE_PTYPE_INNER_L4_TCP,
3772                 RTE_PTYPE_INNER_L4_UDP,
3773                 RTE_PTYPE_UNKNOWN
3774         };
3775
3776         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3777             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3778             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3779             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3780                 return ptypes;
3781
3782 #if defined(RTE_ARCH_X86)
3783         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3784             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3785                 return ptypes;
3786 #endif
3787         return NULL;
3788 }
3789
3790 static void
3791 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3792                      struct rte_eth_dev_info *dev_info)
3793 {
3794         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3795         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796
3797         dev_info->pci_dev = pci_dev;
3798         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3799         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3800         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3801         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3802         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3803         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3804         dev_info->max_vfs = pci_dev->max_vfs;
3805         if (hw->mac.type == ixgbe_mac_82598EB)
3806                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3807         else
3808                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3809         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3810                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3811                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3812                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3813         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3814                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3815                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3816                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3817                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3818                                 DEV_TX_OFFLOAD_TCP_TSO;
3819
3820         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3821                 .rx_thresh = {
3822                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3823                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3824                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3825                 },
3826                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3827                 .rx_drop_en = 0,
3828         };
3829
3830         dev_info->default_txconf = (struct rte_eth_txconf) {
3831                 .tx_thresh = {
3832                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3833                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3834                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3835                 },
3836                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3837                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3838                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3839                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3840         };
3841
3842         dev_info->rx_desc_lim = rx_desc_lim;
3843         dev_info->tx_desc_lim = tx_desc_lim;
3844 }
3845
3846 static int
3847 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3848                    int *link_up, int wait_to_complete)
3849 {
3850         /**
3851          * for a quick link status checking, wait_to_compelet == 0,
3852          * skip PF link status checking
3853          */
3854         bool no_pflink_check = wait_to_complete == 0;
3855         struct ixgbe_mbx_info *mbx = &hw->mbx;
3856         struct ixgbe_mac_info *mac = &hw->mac;
3857         uint32_t links_reg, in_msg;
3858         int ret_val = 0;
3859
3860         /* If we were hit with a reset drop the link */
3861         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3862                 mac->get_link_status = true;
3863
3864         if (!mac->get_link_status)
3865                 goto out;
3866
3867         /* if link status is down no point in checking to see if pf is up */
3868         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3869         if (!(links_reg & IXGBE_LINKS_UP))
3870                 goto out;
3871
3872         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3873          * before the link status is correct
3874          */
3875         if (mac->type == ixgbe_mac_82599_vf) {
3876                 int i;
3877
3878                 for (i = 0; i < 5; i++) {
3879                         rte_delay_us(100);
3880                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3881
3882                         if (!(links_reg & IXGBE_LINKS_UP))
3883                                 goto out;
3884                 }
3885         }
3886
3887         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3888         case IXGBE_LINKS_SPEED_10G_82599:
3889                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3890                 if (hw->mac.type >= ixgbe_mac_X550) {
3891                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3892                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3893                 }
3894                 break;
3895         case IXGBE_LINKS_SPEED_1G_82599:
3896                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3897                 break;
3898         case IXGBE_LINKS_SPEED_100_82599:
3899                 *speed = IXGBE_LINK_SPEED_100_FULL;
3900                 if (hw->mac.type == ixgbe_mac_X550) {
3901                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3902                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3903                 }
3904                 break;
3905         case IXGBE_LINKS_SPEED_10_X550EM_A:
3906                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3907                 /* Since Reserved in older MAC's */
3908                 if (hw->mac.type >= ixgbe_mac_X550)
3909                         *speed = IXGBE_LINK_SPEED_10_FULL;
3910                 break;
3911         default:
3912                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3913         }
3914
3915         if (no_pflink_check) {
3916                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3917                         mac->get_link_status = true;
3918                 else
3919                         mac->get_link_status = false;
3920
3921                 goto out;
3922         }
3923         /* if the read failed it could just be a mailbox collision, best wait
3924          * until we are called again and don't report an error
3925          */
3926         if (mbx->ops.read(hw, &in_msg, 1, 0))
3927                 goto out;
3928
3929         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3930                 /* msg is not CTS and is NACK we must have lost CTS status */
3931                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3932                         ret_val = -1;
3933                 goto out;
3934         }
3935
3936         /* the pf is talking, if we timed out in the past we reinit */
3937         if (!mbx->timeout) {
3938                 ret_val = -1;
3939                 goto out;
3940         }
3941
3942         /* if we passed all the tests above then the link is up and we no
3943          * longer need to check for link
3944          */
3945         mac->get_link_status = false;
3946
3947 out:
3948         *link_up = !mac->get_link_status;
3949         return ret_val;
3950 }
3951
3952 /* return 0 means link status changed, -1 means not changed */
3953 static int
3954 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3955                             int wait_to_complete, int vf)
3956 {
3957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3958         struct rte_eth_link link, old;
3959         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3960         struct ixgbe_interrupt *intr =
3961                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3962         int link_up;
3963         int diag;
3964         u32 speed = 0;
3965         int wait = 1;
3966         bool autoneg = false;
3967
3968         link.link_status = ETH_LINK_DOWN;
3969         link.link_speed = 0;
3970         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3971         link.link_autoneg = ETH_LINK_AUTONEG;
3972         memset(&old, 0, sizeof(old));
3973         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3974
3975         hw->mac.get_link_status = true;
3976
3977         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3978                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3979                 speed = hw->phy.autoneg_advertised;
3980                 if (!speed)
3981                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3982                 ixgbe_setup_link(hw, speed, true);
3983         }
3984
3985         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3986         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3987                 wait = 0;
3988
3989         if (vf)
3990                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3991         else
3992                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3993
3994         if (diag != 0) {
3995                 link.link_speed = ETH_SPEED_NUM_100M;
3996                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3997                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3998                 if (link.link_status == old.link_status)
3999                         return -1;
4000                 return 0;
4001         }
4002
4003         if (link_up == 0) {
4004                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4005                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4006                 if (link.link_status == old.link_status)
4007                         return -1;
4008                 return 0;
4009         }
4010         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4011         link.link_status = ETH_LINK_UP;
4012         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4013
4014         switch (link_speed) {
4015         default:
4016         case IXGBE_LINK_SPEED_UNKNOWN:
4017                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4018                 link.link_speed = ETH_SPEED_NUM_100M;
4019                 break;
4020
4021         case IXGBE_LINK_SPEED_100_FULL:
4022                 link.link_speed = ETH_SPEED_NUM_100M;
4023                 break;
4024
4025         case IXGBE_LINK_SPEED_1GB_FULL:
4026                 link.link_speed = ETH_SPEED_NUM_1G;
4027                 break;
4028
4029         case IXGBE_LINK_SPEED_2_5GB_FULL:
4030                 link.link_speed = ETH_SPEED_NUM_2_5G;
4031                 break;
4032
4033         case IXGBE_LINK_SPEED_5GB_FULL:
4034                 link.link_speed = ETH_SPEED_NUM_5G;
4035                 break;
4036
4037         case IXGBE_LINK_SPEED_10GB_FULL:
4038                 link.link_speed = ETH_SPEED_NUM_10G;
4039                 break;
4040         }
4041         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4042
4043         if (link.link_status == old.link_status)
4044                 return -1;
4045
4046         return 0;
4047 }
4048
4049 static int
4050 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4051 {
4052         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4053 }
4054
4055 static int
4056 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4057 {
4058         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4059 }
4060
4061 static void
4062 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4063 {
4064         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4065         uint32_t fctrl;
4066
4067         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4068         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4069         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4070 }
4071
4072 static void
4073 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4074 {
4075         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4076         uint32_t fctrl;
4077
4078         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4079         fctrl &= (~IXGBE_FCTRL_UPE);
4080         if (dev->data->all_multicast == 1)
4081                 fctrl |= IXGBE_FCTRL_MPE;
4082         else
4083                 fctrl &= (~IXGBE_FCTRL_MPE);
4084         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4085 }
4086
4087 static void
4088 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4089 {
4090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4091         uint32_t fctrl;
4092
4093         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4094         fctrl |= IXGBE_FCTRL_MPE;
4095         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4096 }
4097
4098 static void
4099 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4100 {
4101         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4102         uint32_t fctrl;
4103
4104         if (dev->data->promiscuous == 1)
4105                 return; /* must remain in all_multicast mode */
4106
4107         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4108         fctrl &= (~IXGBE_FCTRL_MPE);
4109         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4110 }
4111
4112 /**
4113  * It clears the interrupt causes and enables the interrupt.
4114  * It will be called once only during nic initialized.
4115  *
4116  * @param dev
4117  *  Pointer to struct rte_eth_dev.
4118  * @param on
4119  *  Enable or Disable.
4120  *
4121  * @return
4122  *  - On success, zero.
4123  *  - On failure, a negative value.
4124  */
4125 static int
4126 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4127 {
4128         struct ixgbe_interrupt *intr =
4129                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4130
4131         ixgbe_dev_link_status_print(dev);
4132         if (on)
4133                 intr->mask |= IXGBE_EICR_LSC;
4134         else
4135                 intr->mask &= ~IXGBE_EICR_LSC;
4136
4137         return 0;
4138 }
4139
4140 /**
4141  * It clears the interrupt causes and enables the interrupt.
4142  * It will be called once only during nic initialized.
4143  *
4144  * @param dev
4145  *  Pointer to struct rte_eth_dev.
4146  *
4147  * @return
4148  *  - On success, zero.
4149  *  - On failure, a negative value.
4150  */
4151 static int
4152 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4153 {
4154         struct ixgbe_interrupt *intr =
4155                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4156
4157         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4158
4159         return 0;
4160 }
4161
4162 /**
4163  * It clears the interrupt causes and enables the interrupt.
4164  * It will be called once only during nic initialized.
4165  *
4166  * @param dev
4167  *  Pointer to struct rte_eth_dev.
4168  *
4169  * @return
4170  *  - On success, zero.
4171  *  - On failure, a negative value.
4172  */
4173 static int
4174 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4175 {
4176         struct ixgbe_interrupt *intr =
4177                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4178
4179         intr->mask |= IXGBE_EICR_LINKSEC;
4180
4181         return 0;
4182 }
4183
4184 /*
4185  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4186  *
4187  * @param dev
4188  *  Pointer to struct rte_eth_dev.
4189  *
4190  * @return
4191  *  - On success, zero.
4192  *  - On failure, a negative value.
4193  */
4194 static int
4195 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4196 {
4197         uint32_t eicr;
4198         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199         struct ixgbe_interrupt *intr =
4200                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4201
4202         /* clear all cause mask */
4203         ixgbe_disable_intr(hw);
4204
4205         /* read-on-clear nic registers here */
4206         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4207         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4208
4209         intr->flags = 0;
4210
4211         /* set flag for async link update */
4212         if (eicr & IXGBE_EICR_LSC)
4213                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4214
4215         if (eicr & IXGBE_EICR_MAILBOX)
4216                 intr->flags |= IXGBE_FLAG_MAILBOX;
4217
4218         if (eicr & IXGBE_EICR_LINKSEC)
4219                 intr->flags |= IXGBE_FLAG_MACSEC;
4220
4221         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4222             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4223             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4224                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4225
4226         return 0;
4227 }
4228
4229 /**
4230  * It gets and then prints the link status.
4231  *
4232  * @param dev
4233  *  Pointer to struct rte_eth_dev.
4234  *
4235  * @return
4236  *  - On success, zero.
4237  *  - On failure, a negative value.
4238  */
4239 static void
4240 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4241 {
4242         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4243         struct rte_eth_link link;
4244
4245         memset(&link, 0, sizeof(link));
4246         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4247         if (link.link_status) {
4248                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4249                                         (int)(dev->data->port_id),
4250                                         (unsigned)link.link_speed,
4251                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4252                                         "full-duplex" : "half-duplex");
4253         } else {
4254                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4255                                 (int)(dev->data->port_id));
4256         }
4257         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4258                                 pci_dev->addr.domain,
4259                                 pci_dev->addr.bus,
4260                                 pci_dev->addr.devid,
4261                                 pci_dev->addr.function);
4262 }
4263
4264 /*
4265  * It executes link_update after knowing an interrupt occurred.
4266  *
4267  * @param dev
4268  *  Pointer to struct rte_eth_dev.
4269  *
4270  * @return
4271  *  - On success, zero.
4272  *  - On failure, a negative value.
4273  */
4274 static int
4275 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4276                            struct rte_intr_handle *intr_handle)
4277 {
4278         struct ixgbe_interrupt *intr =
4279                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4280         int64_t timeout;
4281         struct rte_eth_link link;
4282         struct ixgbe_hw *hw =
4283                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4284
4285         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4286
4287         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4288                 ixgbe_pf_mbx_process(dev);
4289                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4290         }
4291
4292         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4293                 ixgbe_handle_lasi(hw);
4294                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4295         }
4296
4297         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4298                 /* get the link status before link update, for predicting later */
4299                 memset(&link, 0, sizeof(link));
4300                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4301
4302                 ixgbe_dev_link_update(dev, 0);
4303
4304                 /* likely to up */
4305                 if (!link.link_status)
4306                         /* handle it 1 sec later, wait it being stable */
4307                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4308                 /* likely to down */
4309                 else
4310                         /* handle it 4 sec later, wait it being stable */
4311                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4312
4313                 ixgbe_dev_link_status_print(dev);
4314                 if (rte_eal_alarm_set(timeout * 1000,
4315                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4316                         PMD_DRV_LOG(ERR, "Error setting alarm");
4317                 else {
4318                         /* remember original mask */
4319                         intr->mask_original = intr->mask;
4320                         /* only disable lsc interrupt */
4321                         intr->mask &= ~IXGBE_EIMS_LSC;
4322                 }
4323         }
4324
4325         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4326         ixgbe_enable_intr(dev);
4327         rte_intr_enable(intr_handle);
4328
4329         return 0;
4330 }
4331
4332 /**
4333  * Interrupt handler which shall be registered for alarm callback for delayed
4334  * handling specific interrupt to wait for the stable nic state. As the
4335  * NIC interrupt state is not stable for ixgbe after link is just down,
4336  * it needs to wait 4 seconds to get the stable status.
4337  *
4338  * @param handle
4339  *  Pointer to interrupt handle.
4340  * @param param
4341  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4342  *
4343  * @return
4344  *  void
4345  */
4346 static void
4347 ixgbe_dev_interrupt_delayed_handler(void *param)
4348 {
4349         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4350         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4351         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4352         struct ixgbe_interrupt *intr =
4353                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4354         struct ixgbe_hw *hw =
4355                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4356         uint32_t eicr;
4357
4358         ixgbe_disable_intr(hw);
4359
4360         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4361         if (eicr & IXGBE_EICR_MAILBOX)
4362                 ixgbe_pf_mbx_process(dev);
4363
4364         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4365                 ixgbe_handle_lasi(hw);
4366                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4367         }
4368
4369         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4370                 ixgbe_dev_link_update(dev, 0);
4371                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4372                 ixgbe_dev_link_status_print(dev);
4373                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4374                                               NULL, NULL);
4375         }
4376
4377         if (intr->flags & IXGBE_FLAG_MACSEC) {
4378                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4379                                               NULL, NULL);
4380                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4381         }
4382
4383         /* restore original mask */
4384         intr->mask = intr->mask_original;
4385         intr->mask_original = 0;
4386
4387         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4388         ixgbe_enable_intr(dev);
4389         rte_intr_enable(intr_handle);
4390 }
4391
4392 /**
4393  * Interrupt handler triggered by NIC  for handling
4394  * specific interrupt.
4395  *
4396  * @param handle
4397  *  Pointer to interrupt handle.
4398  * @param param
4399  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4400  *
4401  * @return
4402  *  void
4403  */
4404 static void
4405 ixgbe_dev_interrupt_handler(void *param)
4406 {
4407         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4408
4409         ixgbe_dev_interrupt_get_status(dev);
4410         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4411 }
4412
4413 static int
4414 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4415 {
4416         struct ixgbe_hw *hw;
4417
4418         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4419         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4420 }
4421
4422 static int
4423 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4424 {
4425         struct ixgbe_hw *hw;
4426
4427         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4428         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4429 }
4430
4431 static int
4432 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4433 {
4434         struct ixgbe_hw *hw;
4435         uint32_t mflcn_reg;
4436         uint32_t fccfg_reg;
4437         int rx_pause;
4438         int tx_pause;
4439
4440         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4441
4442         fc_conf->pause_time = hw->fc.pause_time;
4443         fc_conf->high_water = hw->fc.high_water[0];
4444         fc_conf->low_water = hw->fc.low_water[0];
4445         fc_conf->send_xon = hw->fc.send_xon;
4446         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4447
4448         /*
4449          * Return rx_pause status according to actual setting of
4450          * MFLCN register.
4451          */
4452         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4453         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4454                 rx_pause = 1;
4455         else
4456                 rx_pause = 0;
4457
4458         /*
4459          * Return tx_pause status according to actual setting of
4460          * FCCFG register.
4461          */
4462         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4463         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4464                 tx_pause = 1;
4465         else
4466                 tx_pause = 0;
4467
4468         if (rx_pause && tx_pause)
4469                 fc_conf->mode = RTE_FC_FULL;
4470         else if (rx_pause)
4471                 fc_conf->mode = RTE_FC_RX_PAUSE;
4472         else if (tx_pause)
4473                 fc_conf->mode = RTE_FC_TX_PAUSE;
4474         else
4475                 fc_conf->mode = RTE_FC_NONE;
4476
4477         return 0;
4478 }
4479
4480 static int
4481 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4482 {
4483         struct ixgbe_hw *hw;
4484         int err;
4485         uint32_t rx_buf_size;
4486         uint32_t max_high_water;
4487         uint32_t mflcn;
4488         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4489                 ixgbe_fc_none,
4490                 ixgbe_fc_rx_pause,
4491                 ixgbe_fc_tx_pause,
4492                 ixgbe_fc_full
4493         };
4494
4495         PMD_INIT_FUNC_TRACE();
4496
4497         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4498         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4499         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4500
4501         /*
4502          * At least reserve one Ethernet frame for watermark
4503          * high_water/low_water in kilo bytes for ixgbe
4504          */
4505         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4506         if ((fc_conf->high_water > max_high_water) ||
4507                 (fc_conf->high_water < fc_conf->low_water)) {
4508                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4509                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4510                 return -EINVAL;
4511         }
4512
4513         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4514         hw->fc.pause_time     = fc_conf->pause_time;
4515         hw->fc.high_water[0]  = fc_conf->high_water;
4516         hw->fc.low_water[0]   = fc_conf->low_water;
4517         hw->fc.send_xon       = fc_conf->send_xon;
4518         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4519
4520         err = ixgbe_fc_enable(hw);
4521
4522         /* Not negotiated is not an error case */
4523         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4524
4525                 /* check if we want to forward MAC frames - driver doesn't have native
4526                  * capability to do that, so we'll write the registers ourselves */
4527
4528                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4529
4530                 /* set or clear MFLCN.PMCF bit depending on configuration */
4531                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4532                         mflcn |= IXGBE_MFLCN_PMCF;
4533                 else
4534                         mflcn &= ~IXGBE_MFLCN_PMCF;
4535
4536                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4537                 IXGBE_WRITE_FLUSH(hw);
4538
4539                 return 0;
4540         }
4541
4542         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4543         return -EIO;
4544 }
4545
4546 /**
4547  *  ixgbe_pfc_enable_generic - Enable flow control
4548  *  @hw: pointer to hardware structure
4549  *  @tc_num: traffic class number
4550  *  Enable flow control according to the current settings.
4551  */
4552 static int
4553 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4554 {
4555         int ret_val = 0;
4556         uint32_t mflcn_reg, fccfg_reg;
4557         uint32_t reg;
4558         uint32_t fcrtl, fcrth;
4559         uint8_t i;
4560         uint8_t nb_rx_en;
4561
4562         /* Validate the water mark configuration */
4563         if (!hw->fc.pause_time) {
4564                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4565                 goto out;
4566         }
4567
4568         /* Low water mark of zero causes XOFF floods */
4569         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4570                  /* High/Low water can not be 0 */
4571                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4572                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4573                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4574                         goto out;
4575                 }
4576
4577                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4578                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4579                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4580                         goto out;
4581                 }
4582         }
4583         /* Negotiate the fc mode to use */
4584         ixgbe_fc_autoneg(hw);
4585
4586         /* Disable any previous flow control settings */
4587         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4588         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4589
4590         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4591         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4592
4593         switch (hw->fc.current_mode) {
4594         case ixgbe_fc_none:
4595                 /*
4596                  * If the count of enabled RX Priority Flow control >1,
4597                  * and the TX pause can not be disabled
4598                  */
4599                 nb_rx_en = 0;
4600                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4601                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4602                         if (reg & IXGBE_FCRTH_FCEN)
4603                                 nb_rx_en++;
4604                 }
4605                 if (nb_rx_en > 1)
4606                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4607                 break;
4608         case ixgbe_fc_rx_pause:
4609                 /*
4610                  * Rx Flow control is enabled and Tx Flow control is
4611                  * disabled by software override. Since there really
4612                  * isn't a way to advertise that we are capable of RX
4613                  * Pause ONLY, we will advertise that we support both
4614                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4615                  * disable the adapter's ability to send PAUSE frames.
4616                  */
4617                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4618                 /*
4619                  * If the count of enabled RX Priority Flow control >1,
4620                  * and the TX pause can not be disabled
4621                  */
4622                 nb_rx_en = 0;
4623                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4624                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4625                         if (reg & IXGBE_FCRTH_FCEN)
4626                                 nb_rx_en++;
4627                 }
4628                 if (nb_rx_en > 1)
4629                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4630                 break;
4631         case ixgbe_fc_tx_pause:
4632                 /*
4633                  * Tx Flow control is enabled, and Rx Flow control is
4634                  * disabled by software override.
4635                  */
4636                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4637                 break;
4638         case ixgbe_fc_full:
4639                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4640                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4641                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4642                 break;
4643         default:
4644                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4645                 ret_val = IXGBE_ERR_CONFIG;
4646                 goto out;
4647         }
4648
4649         /* Set 802.3x based flow control settings. */
4650         mflcn_reg |= IXGBE_MFLCN_DPF;
4651         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4652         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4653
4654         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4655         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4656                 hw->fc.high_water[tc_num]) {
4657                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4658                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4659                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4660         } else {
4661                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4662                 /*
4663                  * In order to prevent Tx hangs when the internal Tx
4664                  * switch is enabled we must set the high water mark
4665                  * to the maximum FCRTH value.  This allows the Tx
4666                  * switch to function even under heavy Rx workloads.
4667                  */
4668                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4669         }
4670         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4671
4672         /* Configure pause time (2 TCs per register) */
4673         reg = hw->fc.pause_time * 0x00010001;
4674         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4675                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4676
4677         /* Configure flow control refresh threshold value */
4678         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4679
4680 out:
4681         return ret_val;
4682 }
4683
4684 static int
4685 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4686 {
4687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4688         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4689
4690         if (hw->mac.type != ixgbe_mac_82598EB) {
4691                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4692         }
4693         return ret_val;
4694 }
4695
4696 static int
4697 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4698 {
4699         int err;
4700         uint32_t rx_buf_size;
4701         uint32_t max_high_water;
4702         uint8_t tc_num;
4703         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4704         struct ixgbe_hw *hw =
4705                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4706         struct ixgbe_dcb_config *dcb_config =
4707                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4708
4709         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4710                 ixgbe_fc_none,
4711                 ixgbe_fc_rx_pause,
4712                 ixgbe_fc_tx_pause,
4713                 ixgbe_fc_full
4714         };
4715
4716         PMD_INIT_FUNC_TRACE();
4717
4718         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4719         tc_num = map[pfc_conf->priority];
4720         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4721         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4722         /*
4723          * At least reserve one Ethernet frame for watermark
4724          * high_water/low_water in kilo bytes for ixgbe
4725          */
4726         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4727         if ((pfc_conf->fc.high_water > max_high_water) ||
4728             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4729                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4730                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4731                 return -EINVAL;
4732         }
4733
4734         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4735         hw->fc.pause_time = pfc_conf->fc.pause_time;
4736         hw->fc.send_xon = pfc_conf->fc.send_xon;
4737         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4738         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4739
4740         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4741
4742         /* Not negotiated is not an error case */
4743         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4744                 return 0;
4745
4746         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4747         return -EIO;
4748 }
4749
4750 static int
4751 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4752                           struct rte_eth_rss_reta_entry64 *reta_conf,
4753                           uint16_t reta_size)
4754 {
4755         uint16_t i, sp_reta_size;
4756         uint8_t j, mask;
4757         uint32_t reta, r;
4758         uint16_t idx, shift;
4759         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4760         uint32_t reta_reg;
4761
4762         PMD_INIT_FUNC_TRACE();
4763
4764         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4765                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4766                         "NIC.");
4767                 return -ENOTSUP;
4768         }
4769
4770         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4771         if (reta_size != sp_reta_size) {
4772                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4773                         "(%d) doesn't match the number hardware can supported "
4774                         "(%d)", reta_size, sp_reta_size);
4775                 return -EINVAL;
4776         }
4777
4778         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4779                 idx = i / RTE_RETA_GROUP_SIZE;
4780                 shift = i % RTE_RETA_GROUP_SIZE;
4781                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4782                                                 IXGBE_4_BIT_MASK);
4783                 if (!mask)
4784                         continue;
4785                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4786                 if (mask == IXGBE_4_BIT_MASK)
4787                         r = 0;
4788                 else
4789                         r = IXGBE_READ_REG(hw, reta_reg);
4790                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4791                         if (mask & (0x1 << j))
4792                                 reta |= reta_conf[idx].reta[shift + j] <<
4793                                                         (CHAR_BIT * j);
4794                         else
4795                                 reta |= r & (IXGBE_8_BIT_MASK <<
4796                                                 (CHAR_BIT * j));
4797                 }
4798                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4799         }
4800
4801         return 0;
4802 }
4803
4804 static int
4805 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4806                          struct rte_eth_rss_reta_entry64 *reta_conf,
4807                          uint16_t reta_size)
4808 {
4809         uint16_t i, sp_reta_size;
4810         uint8_t j, mask;
4811         uint32_t reta;
4812         uint16_t idx, shift;
4813         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4814         uint32_t reta_reg;
4815
4816         PMD_INIT_FUNC_TRACE();
4817         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4818         if (reta_size != sp_reta_size) {
4819                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4820                         "(%d) doesn't match the number hardware can supported "
4821                         "(%d)", reta_size, sp_reta_size);
4822                 return -EINVAL;
4823         }
4824
4825         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4826                 idx = i / RTE_RETA_GROUP_SIZE;
4827                 shift = i % RTE_RETA_GROUP_SIZE;
4828                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4829                                                 IXGBE_4_BIT_MASK);
4830                 if (!mask)
4831                         continue;
4832
4833                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4834                 reta = IXGBE_READ_REG(hw, reta_reg);
4835                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4836                         if (mask & (0x1 << j))
4837                                 reta_conf[idx].reta[shift + j] =
4838                                         ((reta >> (CHAR_BIT * j)) &
4839                                                 IXGBE_8_BIT_MASK);
4840                 }
4841         }
4842
4843         return 0;
4844 }
4845
4846 static int
4847 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4848                                 uint32_t index, uint32_t pool)
4849 {
4850         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4851         uint32_t enable_addr = 1;
4852
4853         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4854                              pool, enable_addr);
4855 }
4856
4857 static void
4858 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4859 {
4860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4861
4862         ixgbe_clear_rar(hw, index);
4863 }
4864
4865 static void
4866 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4867 {
4868         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4869
4870         ixgbe_remove_rar(dev, 0);
4871
4872         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4873 }
4874
4875 static bool
4876 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4877 {
4878         if (strcmp(dev->device->driver->name, drv->driver.name))
4879                 return false;
4880
4881         return true;
4882 }
4883
4884 bool
4885 is_ixgbe_supported(struct rte_eth_dev *dev)
4886 {
4887         return is_device_supported(dev, &rte_ixgbe_pmd);
4888 }
4889
4890 static int
4891 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4892 {
4893         uint32_t hlreg0;
4894         uint32_t maxfrs;
4895         struct ixgbe_hw *hw;
4896         struct rte_eth_dev_info dev_info;
4897         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4898         struct rte_eth_dev_data *dev_data = dev->data;
4899
4900         ixgbe_dev_info_get(dev, &dev_info);
4901
4902         /* check that mtu is within the allowed range */
4903         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4904                 return -EINVAL;
4905
4906         /* If device is started, refuse mtu that requires the support of
4907          * scattered packets when this feature has not been enabled before.
4908          */
4909         if (dev_data->dev_started && !dev_data->scattered_rx &&
4910             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4911              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4912                 PMD_INIT_LOG(ERR, "Stop port first.");
4913                 return -EINVAL;
4914         }
4915
4916         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4917         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4918
4919         /* switch to jumbo mode if needed */
4920         if (frame_size > ETHER_MAX_LEN) {
4921                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4922                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4923         } else {
4924                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4925                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4926         }
4927         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4928
4929         /* update max frame size */
4930         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4931
4932         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4933         maxfrs &= 0x0000FFFF;
4934         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4935         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4936
4937         return 0;
4938 }
4939
4940 /*
4941  * Virtual Function operations
4942  */
4943 static void
4944 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4945 {
4946         PMD_INIT_FUNC_TRACE();
4947
4948         /* Clear interrupt mask to stop from interrupts being generated */
4949         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4950
4951         IXGBE_WRITE_FLUSH(hw);
4952 }
4953
4954 static void
4955 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4956 {
4957         PMD_INIT_FUNC_TRACE();
4958
4959         /* VF enable interrupt autoclean */
4960         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4961         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4962         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4963
4964         IXGBE_WRITE_FLUSH(hw);
4965 }
4966
4967 static int
4968 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4969 {
4970         struct rte_eth_conf *conf = &dev->data->dev_conf;
4971         struct ixgbe_adapter *adapter =
4972                         (struct ixgbe_adapter *)dev->data->dev_private;
4973
4974         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4975                      dev->data->port_id);
4976
4977         /*
4978          * VF has no ability to enable/disable HW CRC
4979          * Keep the persistent behavior the same as Host PF
4980          */
4981 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4982         if (!conf->rxmode.hw_strip_crc) {
4983                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4984                 conf->rxmode.hw_strip_crc = 1;
4985         }
4986 #else
4987         if (conf->rxmode.hw_strip_crc) {
4988                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4989                 conf->rxmode.hw_strip_crc = 0;
4990         }
4991 #endif
4992
4993         /*
4994          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4995          * allocation or vector Rx preconditions we will reset it.
4996          */
4997         adapter->rx_bulk_alloc_allowed = true;
4998         adapter->rx_vec_allowed = true;
4999
5000         return 0;
5001 }
5002
5003 static int
5004 ixgbevf_dev_start(struct rte_eth_dev *dev)
5005 {
5006         struct ixgbe_hw *hw =
5007                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5008         uint32_t intr_vector = 0;
5009         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5010         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5011
5012         int err, mask = 0;
5013
5014         PMD_INIT_FUNC_TRACE();
5015
5016         hw->mac.ops.reset_hw(hw);
5017         hw->mac.get_link_status = true;
5018
5019         /* negotiate mailbox API version to use with the PF. */
5020         ixgbevf_negotiate_api(hw);
5021
5022         ixgbevf_dev_tx_init(dev);
5023
5024         /* This can fail when allocating mbufs for descriptor rings */
5025         err = ixgbevf_dev_rx_init(dev);
5026         if (err) {
5027                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5028                 ixgbe_dev_clear_queues(dev);
5029                 return err;
5030         }
5031
5032         /* Set vfta */
5033         ixgbevf_set_vfta_all(dev, 1);
5034
5035         /* Set HW strip */
5036         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5037                 ETH_VLAN_EXTEND_MASK;
5038         ixgbevf_vlan_offload_set(dev, mask);
5039
5040         ixgbevf_dev_rxtx_start(dev);
5041
5042         /* check and configure queue intr-vector mapping */
5043         if (dev->data->dev_conf.intr_conf.rxq != 0) {
5044                 /* According to datasheet, only vector 0/1/2 can be used,
5045                  * now only one vector is used for Rx queue
5046                  */
5047                 intr_vector = 1;
5048                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5049                         return -1;
5050         }
5051
5052         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5053                 intr_handle->intr_vec =
5054                         rte_zmalloc("intr_vec",
5055                                     dev->data->nb_rx_queues * sizeof(int), 0);
5056                 if (intr_handle->intr_vec == NULL) {
5057                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5058                                      " intr_vec", dev->data->nb_rx_queues);
5059                         return -ENOMEM;
5060                 }
5061         }
5062         ixgbevf_configure_msix(dev);
5063
5064         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5065          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5066          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5067          * is not cleared, it will fail when following rte_intr_enable( ) tries
5068          * to map Rx queue interrupt to other VFIO vectors.
5069          * So clear uio/vfio intr/evevnfd first to avoid failure.
5070          */
5071         rte_intr_disable(intr_handle);
5072
5073         rte_intr_enable(intr_handle);
5074
5075         /* Re-enable interrupt for VF */
5076         ixgbevf_intr_enable(hw);
5077
5078         return 0;
5079 }
5080
5081 static void
5082 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5083 {
5084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5085         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5086         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5087
5088         PMD_INIT_FUNC_TRACE();
5089
5090         ixgbevf_intr_disable(hw);
5091
5092         hw->adapter_stopped = 1;
5093         ixgbe_stop_adapter(hw);
5094
5095         /*
5096           * Clear what we set, but we still keep shadow_vfta to
5097           * restore after device starts
5098           */
5099         ixgbevf_set_vfta_all(dev, 0);
5100
5101         /* Clear stored conf */
5102         dev->data->scattered_rx = 0;
5103
5104         ixgbe_dev_clear_queues(dev);
5105
5106         /* Clean datapath event and queue/vec mapping */
5107         rte_intr_efd_disable(intr_handle);
5108         if (intr_handle->intr_vec != NULL) {
5109                 rte_free(intr_handle->intr_vec);
5110                 intr_handle->intr_vec = NULL;
5111         }
5112 }
5113
5114 static void
5115 ixgbevf_dev_close(struct rte_eth_dev *dev)
5116 {
5117         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5118
5119         PMD_INIT_FUNC_TRACE();
5120
5121         ixgbe_reset_hw(hw);
5122
5123         ixgbevf_dev_stop(dev);
5124
5125         ixgbe_dev_free_queues(dev);
5126
5127         /**
5128          * Remove the VF MAC address ro ensure
5129          * that the VF traffic goes to the PF
5130          * after stop, close and detach of the VF
5131          **/
5132         ixgbevf_remove_mac_addr(dev, 0);
5133 }
5134
5135 /*
5136  * Reset VF device
5137  */
5138 static int
5139 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5140 {
5141         int ret;
5142
5143         ret = eth_ixgbevf_dev_uninit(dev);
5144         if (ret)
5145                 return ret;
5146
5147         ret = eth_ixgbevf_dev_init(dev);
5148
5149         return ret;
5150 }
5151
5152 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5153 {
5154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5155         struct ixgbe_vfta *shadow_vfta =
5156                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5157         int i = 0, j = 0, vfta = 0, mask = 1;
5158
5159         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5160                 vfta = shadow_vfta->vfta[i];
5161                 if (vfta) {
5162                         mask = 1;
5163                         for (j = 0; j < 32; j++) {
5164                                 if (vfta & mask)
5165                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5166                                                        on, false);
5167                                 mask <<= 1;
5168                         }
5169                 }
5170         }
5171
5172 }
5173
5174 static int
5175 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5176 {
5177         struct ixgbe_hw *hw =
5178                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5179         struct ixgbe_vfta *shadow_vfta =
5180                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5181         uint32_t vid_idx = 0;
5182         uint32_t vid_bit = 0;
5183         int ret = 0;
5184
5185         PMD_INIT_FUNC_TRACE();
5186
5187         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5188         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5189         if (ret) {
5190                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5191                 return ret;
5192         }
5193         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5194         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5195
5196         /* Save what we set and retore it after device reset */
5197         if (on)
5198                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5199         else
5200                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5201
5202         return 0;
5203 }
5204
5205 static void
5206 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5207 {
5208         struct ixgbe_hw *hw =
5209                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5210         uint32_t ctrl;
5211
5212         PMD_INIT_FUNC_TRACE();
5213
5214         if (queue >= hw->mac.max_rx_queues)
5215                 return;
5216
5217         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5218         if (on)
5219                 ctrl |= IXGBE_RXDCTL_VME;
5220         else
5221                 ctrl &= ~IXGBE_RXDCTL_VME;
5222         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5223
5224         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5225 }
5226
5227 static void
5228 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5229 {
5230         struct ixgbe_hw *hw =
5231                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5232         uint16_t i;
5233         int on = 0;
5234
5235         /* VF function only support hw strip feature, others are not support */
5236         if (mask & ETH_VLAN_STRIP_MASK) {
5237                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5238
5239                 for (i = 0; i < hw->mac.max_rx_queues; i++)
5240                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5241         }
5242 }
5243
5244 int
5245 ixgbe_vt_check(struct ixgbe_hw *hw)
5246 {
5247         uint32_t reg_val;
5248
5249         /* if Virtualization Technology is enabled */
5250         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5251         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5252                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5253                 return -1;
5254         }
5255
5256         return 0;
5257 }
5258
5259 static uint32_t
5260 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5261 {
5262         uint32_t vector = 0;
5263
5264         switch (hw->mac.mc_filter_type) {
5265         case 0:   /* use bits [47:36] of the address */
5266                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5267                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5268                 break;
5269         case 1:   /* use bits [46:35] of the address */
5270                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5271                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5272                 break;
5273         case 2:   /* use bits [45:34] of the address */
5274                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5275                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5276                 break;
5277         case 3:   /* use bits [43:32] of the address */
5278                 vector = ((uc_addr->addr_bytes[4]) |
5279                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5280                 break;
5281         default:  /* Invalid mc_filter_type */
5282                 break;
5283         }
5284
5285         /* vector can only be 12-bits or boundary will be exceeded */
5286         vector &= 0xFFF;
5287         return vector;
5288 }
5289
5290 static int
5291 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5292                         uint8_t on)
5293 {
5294         uint32_t vector;
5295         uint32_t uta_idx;
5296         uint32_t reg_val;
5297         uint32_t uta_shift;
5298         uint32_t rc;
5299         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5300         const uint32_t ixgbe_uta_bit_shift = 5;
5301         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5302         const uint32_t bit1 = 0x1;
5303
5304         struct ixgbe_hw *hw =
5305                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5306         struct ixgbe_uta_info *uta_info =
5307                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5308
5309         /* The UTA table only exists on 82599 hardware and newer */
5310         if (hw->mac.type < ixgbe_mac_82599EB)
5311                 return -ENOTSUP;
5312
5313         vector = ixgbe_uta_vector(hw, mac_addr);
5314         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5315         uta_shift = vector & ixgbe_uta_bit_mask;
5316
5317         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5318         if (rc == on)
5319                 return 0;
5320
5321         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5322         if (on) {
5323                 uta_info->uta_in_use++;
5324                 reg_val |= (bit1 << uta_shift);
5325                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5326         } else {
5327                 uta_info->uta_in_use--;
5328                 reg_val &= ~(bit1 << uta_shift);
5329                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5330         }
5331
5332         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5333
5334         if (uta_info->uta_in_use > 0)
5335                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5336                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5337         else
5338                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5339
5340         return 0;
5341 }
5342
5343 static int
5344 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5345 {
5346         int i;
5347         struct ixgbe_hw *hw =
5348                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5349         struct ixgbe_uta_info *uta_info =
5350                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5351
5352         /* The UTA table only exists on 82599 hardware and newer */
5353         if (hw->mac.type < ixgbe_mac_82599EB)
5354                 return -ENOTSUP;
5355
5356         if (on) {
5357                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5358                         uta_info->uta_shadow[i] = ~0;
5359                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5360                 }
5361         } else {
5362                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5363                         uta_info->uta_shadow[i] = 0;
5364                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5365                 }
5366         }
5367         return 0;
5368
5369 }
5370
5371 uint32_t
5372 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5373 {
5374         uint32_t new_val = orig_val;
5375
5376         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5377                 new_val |= IXGBE_VMOLR_AUPE;
5378         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5379                 new_val |= IXGBE_VMOLR_ROMPE;
5380         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5381                 new_val |= IXGBE_VMOLR_ROPE;
5382         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5383                 new_val |= IXGBE_VMOLR_BAM;
5384         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5385                 new_val |= IXGBE_VMOLR_MPE;
5386
5387         return new_val;
5388 }
5389
5390 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5391 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5392 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5393 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5394 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5395         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5396         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5397
5398 static int
5399 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5400                       struct rte_eth_mirror_conf *mirror_conf,
5401                       uint8_t rule_id, uint8_t on)
5402 {
5403         uint32_t mr_ctl, vlvf;
5404         uint32_t mp_lsb = 0;
5405         uint32_t mv_msb = 0;
5406         uint32_t mv_lsb = 0;
5407         uint32_t mp_msb = 0;
5408         uint8_t i = 0;
5409         int reg_index = 0;
5410         uint64_t vlan_mask = 0;
5411
5412         const uint8_t pool_mask_offset = 32;
5413         const uint8_t vlan_mask_offset = 32;
5414         const uint8_t dst_pool_offset = 8;
5415         const uint8_t rule_mr_offset  = 4;
5416         const uint8_t mirror_rule_mask = 0x0F;
5417
5418         struct ixgbe_mirror_info *mr_info =
5419                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5420         struct ixgbe_hw *hw =
5421                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5422         uint8_t mirror_type = 0;
5423
5424         if (ixgbe_vt_check(hw) < 0)
5425                 return -ENOTSUP;
5426
5427         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5428                 return -EINVAL;
5429
5430         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5431                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5432                             mirror_conf->rule_type);
5433                 return -EINVAL;
5434         }
5435
5436         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5437                 mirror_type |= IXGBE_MRCTL_VLME;
5438                 /* Check if vlan id is valid and find conresponding VLAN ID
5439                  * index in VLVF
5440                  */
5441                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5442                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5443                                 /* search vlan id related pool vlan filter
5444                                  * index
5445                                  */
5446                                 reg_index = ixgbe_find_vlvf_slot(
5447                                                 hw,
5448                                                 mirror_conf->vlan.vlan_id[i],
5449                                                 false);
5450                                 if (reg_index < 0)
5451                                         return -EINVAL;
5452                                 vlvf = IXGBE_READ_REG(hw,
5453                                                       IXGBE_VLVF(reg_index));
5454                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5455                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5456                                       mirror_conf->vlan.vlan_id[i]))
5457                                         vlan_mask |= (1ULL << reg_index);
5458                                 else
5459                                         return -EINVAL;
5460                         }
5461                 }
5462
5463                 if (on) {
5464                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5465                         mv_msb = vlan_mask >> vlan_mask_offset;
5466
5467                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5468                                                 mirror_conf->vlan.vlan_mask;
5469                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5470                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5471                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5472                                                 mirror_conf->vlan.vlan_id[i];
5473                         }
5474                 } else {
5475                         mv_lsb = 0;
5476                         mv_msb = 0;
5477                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5478                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5479                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5480                 }
5481         }
5482
5483         /**
5484          * if enable pool mirror, write related pool mask register,if disable
5485          * pool mirror, clear PFMRVM register
5486          */
5487         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5488                 mirror_type |= IXGBE_MRCTL_VPME;
5489                 if (on) {
5490                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5491                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5492                         mr_info->mr_conf[rule_id].pool_mask =
5493                                         mirror_conf->pool_mask;
5494
5495                 } else {
5496                         mp_lsb = 0;
5497                         mp_msb = 0;
5498                         mr_info->mr_conf[rule_id].pool_mask = 0;
5499                 }
5500         }
5501         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5502                 mirror_type |= IXGBE_MRCTL_UPME;
5503         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5504                 mirror_type |= IXGBE_MRCTL_DPME;
5505
5506         /* read  mirror control register and recalculate it */
5507         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5508
5509         if (on) {
5510                 mr_ctl |= mirror_type;
5511                 mr_ctl &= mirror_rule_mask;
5512                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5513         } else {
5514                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5515         }
5516
5517         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5518         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5519
5520         /* write mirrror control  register */
5521         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5522
5523         /* write pool mirrror control  register */
5524         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5525                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5526                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5527                                 mp_msb);
5528         }
5529         /* write VLAN mirrror control  register */
5530         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5531                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5532                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5533                                 mv_msb);
5534         }
5535
5536         return 0;
5537 }
5538
5539 static int
5540 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5541 {
5542         int mr_ctl = 0;
5543         uint32_t lsb_val = 0;
5544         uint32_t msb_val = 0;
5545         const uint8_t rule_mr_offset = 4;
5546
5547         struct ixgbe_hw *hw =
5548                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5549         struct ixgbe_mirror_info *mr_info =
5550                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5551
5552         if (ixgbe_vt_check(hw) < 0)
5553                 return -ENOTSUP;
5554
5555         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5556                 return -EINVAL;
5557
5558         memset(&mr_info->mr_conf[rule_id], 0,
5559                sizeof(struct rte_eth_mirror_conf));
5560
5561         /* clear PFVMCTL register */
5562         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5563
5564         /* clear pool mask register */
5565         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5566         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5567
5568         /* clear vlan mask register */
5569         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5570         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5571
5572         return 0;
5573 }
5574
5575 static int
5576 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5577 {
5578         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5579         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5580         uint32_t mask;
5581         struct ixgbe_hw *hw =
5582                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5583         uint32_t vec = IXGBE_MISC_VEC_ID;
5584
5585         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5586         if (rte_intr_allow_others(intr_handle))
5587                 vec = IXGBE_RX_VEC_START;
5588         mask |= (1 << vec);
5589         RTE_SET_USED(queue_id);
5590         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5591
5592         rte_intr_enable(intr_handle);
5593
5594         return 0;
5595 }
5596
5597 static int
5598 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5599 {
5600         uint32_t mask;
5601         struct ixgbe_hw *hw =
5602                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5603         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5604         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5605         uint32_t vec = IXGBE_MISC_VEC_ID;
5606
5607         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5608         if (rte_intr_allow_others(intr_handle))
5609                 vec = IXGBE_RX_VEC_START;
5610         mask &= ~(1 << vec);
5611         RTE_SET_USED(queue_id);
5612         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5613
5614         return 0;
5615 }
5616
5617 static int
5618 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5619 {
5620         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5621         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5622         uint32_t mask;
5623         struct ixgbe_hw *hw =
5624                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5625         struct ixgbe_interrupt *intr =
5626                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5627
5628         if (queue_id < 16) {
5629                 ixgbe_disable_intr(hw);
5630                 intr->mask |= (1 << queue_id);
5631                 ixgbe_enable_intr(dev);
5632         } else if (queue_id < 32) {
5633                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5634                 mask &= (1 << queue_id);
5635                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5636         } else if (queue_id < 64) {
5637                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5638                 mask &= (1 << (queue_id - 32));
5639                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5640         }
5641         rte_intr_enable(intr_handle);
5642
5643         return 0;
5644 }
5645
5646 static int
5647 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5648 {
5649         uint32_t mask;
5650         struct ixgbe_hw *hw =
5651                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5652         struct ixgbe_interrupt *intr =
5653                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5654
5655         if (queue_id < 16) {
5656                 ixgbe_disable_intr(hw);
5657                 intr->mask &= ~(1 << queue_id);
5658                 ixgbe_enable_intr(dev);
5659         } else if (queue_id < 32) {
5660                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5661                 mask &= ~(1 << queue_id);
5662                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5663         } else if (queue_id < 64) {
5664                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5665                 mask &= ~(1 << (queue_id - 32));
5666                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5667         }
5668
5669         return 0;
5670 }
5671
5672 static void
5673 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5674                      uint8_t queue, uint8_t msix_vector)
5675 {
5676         uint32_t tmp, idx;
5677
5678         if (direction == -1) {
5679                 /* other causes */
5680                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5681                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5682                 tmp &= ~0xFF;
5683                 tmp |= msix_vector;
5684                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5685         } else {
5686                 /* rx or tx cause */
5687                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5688                 idx = ((16 * (queue & 1)) + (8 * direction));
5689                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5690                 tmp &= ~(0xFF << idx);
5691                 tmp |= (msix_vector << idx);
5692                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5693         }
5694 }
5695
5696 /**
5697  * set the IVAR registers, mapping interrupt causes to vectors
5698  * @param hw
5699  *  pointer to ixgbe_hw struct
5700  * @direction
5701  *  0 for Rx, 1 for Tx, -1 for other causes
5702  * @queue
5703  *  queue to map the corresponding interrupt to
5704  * @msix_vector
5705  *  the vector to map to the corresponding queue
5706  */
5707 static void
5708 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5709                    uint8_t queue, uint8_t msix_vector)
5710 {
5711         uint32_t tmp, idx;
5712
5713         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5714         if (hw->mac.type == ixgbe_mac_82598EB) {
5715                 if (direction == -1)
5716                         direction = 0;
5717                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5718                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5719                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5720                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5721                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5722         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5723                         (hw->mac.type == ixgbe_mac_X540) ||
5724                         (hw->mac.type == ixgbe_mac_X550)) {
5725                 if (direction == -1) {
5726                         /* other causes */
5727                         idx = ((queue & 1) * 8);
5728                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5729                         tmp &= ~(0xFF << idx);
5730                         tmp |= (msix_vector << idx);
5731                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5732                 } else {
5733                         /* rx or tx causes */
5734                         idx = ((16 * (queue & 1)) + (8 * direction));
5735                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5736                         tmp &= ~(0xFF << idx);
5737                         tmp |= (msix_vector << idx);
5738                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5739                 }
5740         }
5741 }
5742
5743 static void
5744 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5745 {
5746         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5747         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5748         struct ixgbe_hw *hw =
5749                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5750         uint32_t q_idx;
5751         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5752         uint32_t base = IXGBE_MISC_VEC_ID;
5753
5754         /* Configure VF other cause ivar */
5755         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5756
5757         /* won't configure msix register if no mapping is done
5758          * between intr vector and event fd.
5759          */
5760         if (!rte_intr_dp_is_en(intr_handle))
5761                 return;
5762
5763         if (rte_intr_allow_others(intr_handle)) {
5764                 base = IXGBE_RX_VEC_START;
5765                 vector_idx = IXGBE_RX_VEC_START;
5766         }
5767
5768         /* Configure all RX queues of VF */
5769         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5770                 /* Force all queue use vector 0,
5771                  * as IXGBE_VF_MAXMSIVECOTR = 1
5772                  */
5773                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5774                 intr_handle->intr_vec[q_idx] = vector_idx;
5775                 if (vector_idx < base + intr_handle->nb_efd - 1)
5776                         vector_idx++;
5777         }
5778 }
5779
5780 /**
5781  * Sets up the hardware to properly generate MSI-X interrupts
5782  * @hw
5783  *  board private structure
5784  */
5785 static void
5786 ixgbe_configure_msix(struct rte_eth_dev *dev)
5787 {
5788         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5789         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5790         struct ixgbe_hw *hw =
5791                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5792         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5793         uint32_t vec = IXGBE_MISC_VEC_ID;
5794         uint32_t mask;
5795         uint32_t gpie;
5796
5797         /* won't configure msix register if no mapping is done
5798          * between intr vector and event fd
5799          */
5800         if (!rte_intr_dp_is_en(intr_handle))
5801                 return;
5802
5803         if (rte_intr_allow_others(intr_handle))
5804                 vec = base = IXGBE_RX_VEC_START;
5805
5806         /* setup GPIE for MSI-x mode */
5807         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5808         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5809                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5810         /* auto clearing and auto setting corresponding bits in EIMS
5811          * when MSI-X interrupt is triggered
5812          */
5813         if (hw->mac.type == ixgbe_mac_82598EB) {
5814                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5815         } else {
5816                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5817                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5818         }
5819         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5820
5821         /* Populate the IVAR table and set the ITR values to the
5822          * corresponding register.
5823          */
5824         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5825              queue_id++) {
5826                 /* by default, 1:1 mapping */
5827                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5828                 intr_handle->intr_vec[queue_id] = vec;
5829                 if (vec < base + intr_handle->nb_efd - 1)
5830                         vec++;
5831         }
5832
5833         switch (hw->mac.type) {
5834         case ixgbe_mac_82598EB:
5835                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5836                                    IXGBE_MISC_VEC_ID);
5837                 break;
5838         case ixgbe_mac_82599EB:
5839         case ixgbe_mac_X540:
5840         case ixgbe_mac_X550:
5841                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5842                 break;
5843         default:
5844                 break;
5845         }
5846         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5847                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5848
5849         /* set up to autoclear timer, and the vectors */
5850         mask = IXGBE_EIMS_ENABLE_MASK;
5851         mask &= ~(IXGBE_EIMS_OTHER |
5852                   IXGBE_EIMS_MAILBOX |
5853                   IXGBE_EIMS_LSC);
5854
5855         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5856 }
5857
5858 int
5859 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5860                            uint16_t queue_idx, uint16_t tx_rate)
5861 {
5862         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5863         uint32_t rf_dec, rf_int;
5864         uint32_t bcnrc_val;
5865         uint16_t link_speed = dev->data->dev_link.link_speed;
5866
5867         if (queue_idx >= hw->mac.max_tx_queues)
5868                 return -EINVAL;
5869
5870         if (tx_rate != 0) {
5871                 /* Calculate the rate factor values to set */
5872                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5873                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5874                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5875
5876                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5877                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5878                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5879                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5880         } else {
5881                 bcnrc_val = 0;
5882         }
5883
5884         /*
5885          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5886          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5887          * set as 0x4.
5888          */
5889         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5890                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5891                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5892                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5893                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5894         else
5895                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5896                         IXGBE_MMW_SIZE_DEFAULT);
5897
5898         /* Set RTTBCNRC of queue X */
5899         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5900         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5901         IXGBE_WRITE_FLUSH(hw);
5902
5903         return 0;
5904 }
5905
5906 static int
5907 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5908                      __attribute__((unused)) uint32_t index,
5909                      __attribute__((unused)) uint32_t pool)
5910 {
5911         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5912         int diag;
5913
5914         /*
5915          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5916          * operation. Trap this case to avoid exhausting the [very limited]
5917          * set of PF resources used to store VF MAC addresses.
5918          */
5919         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5920                 return -1;
5921         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5922         if (diag != 0)
5923                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5924                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5925                             mac_addr->addr_bytes[0],
5926                             mac_addr->addr_bytes[1],
5927                             mac_addr->addr_bytes[2],
5928                             mac_addr->addr_bytes[3],
5929                             mac_addr->addr_bytes[4],
5930                             mac_addr->addr_bytes[5],
5931                             diag);
5932         return diag;
5933 }
5934
5935 static void
5936 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5937 {
5938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5939         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5940         struct ether_addr *mac_addr;
5941         uint32_t i;
5942         int diag;
5943
5944         /*
5945          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5946          * not support the deletion of a given MAC address.
5947          * Instead, it imposes to delete all MAC addresses, then to add again
5948          * all MAC addresses with the exception of the one to be deleted.
5949          */
5950         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5951
5952         /*
5953          * Add again all MAC addresses, with the exception of the deleted one
5954          * and of the permanent MAC address.
5955          */
5956         for (i = 0, mac_addr = dev->data->mac_addrs;
5957              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5958                 /* Skip the deleted MAC address */
5959                 if (i == index)
5960                         continue;
5961                 /* Skip NULL MAC addresses */
5962                 if (is_zero_ether_addr(mac_addr))
5963                         continue;
5964                 /* Skip the permanent MAC address */
5965                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5966                         continue;
5967                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5968                 if (diag != 0)
5969                         PMD_DRV_LOG(ERR,
5970                                     "Adding again MAC address "
5971                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5972                                     "diag=%d",
5973                                     mac_addr->addr_bytes[0],
5974                                     mac_addr->addr_bytes[1],
5975                                     mac_addr->addr_bytes[2],
5976                                     mac_addr->addr_bytes[3],
5977                                     mac_addr->addr_bytes[4],
5978                                     mac_addr->addr_bytes[5],
5979                                     diag);
5980         }
5981 }
5982
5983 static void
5984 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5985 {
5986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5987
5988         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5989 }
5990
5991 int
5992 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5993                         struct rte_eth_syn_filter *filter,
5994                         bool add)
5995 {
5996         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5997         struct ixgbe_filter_info *filter_info =
5998                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5999         uint32_t syn_info;
6000         uint32_t synqf;
6001
6002         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6003                 return -EINVAL;
6004
6005         syn_info = filter_info->syn_info;
6006
6007         if (add) {
6008                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6009                         return -EINVAL;
6010                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6011                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6012
6013                 if (filter->hig_pri)
6014                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6015                 else
6016                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6017         } else {
6018                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6019                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6020                         return -ENOENT;
6021                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6022         }
6023
6024         filter_info->syn_info = synqf;
6025         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6026         IXGBE_WRITE_FLUSH(hw);
6027         return 0;
6028 }
6029
6030 static int
6031 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6032                         struct rte_eth_syn_filter *filter)
6033 {
6034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6035         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6036
6037         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6038                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6039                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6040                 return 0;
6041         }
6042         return -ENOENT;
6043 }
6044
6045 static int
6046 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6047                         enum rte_filter_op filter_op,
6048                         void *arg)
6049 {
6050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6051         int ret;
6052
6053         MAC_TYPE_FILTER_SUP(hw->mac.type);
6054
6055         if (filter_op == RTE_ETH_FILTER_NOP)
6056                 return 0;
6057
6058         if (arg == NULL) {
6059                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6060                             filter_op);
6061                 return -EINVAL;
6062         }
6063
6064         switch (filter_op) {
6065         case RTE_ETH_FILTER_ADD:
6066                 ret = ixgbe_syn_filter_set(dev,
6067                                 (struct rte_eth_syn_filter *)arg,
6068                                 TRUE);
6069                 break;
6070         case RTE_ETH_FILTER_DELETE:
6071                 ret = ixgbe_syn_filter_set(dev,
6072                                 (struct rte_eth_syn_filter *)arg,
6073                                 FALSE);
6074                 break;
6075         case RTE_ETH_FILTER_GET:
6076                 ret = ixgbe_syn_filter_get(dev,
6077                                 (struct rte_eth_syn_filter *)arg);
6078                 break;
6079         default:
6080                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6081                 ret = -EINVAL;
6082                 break;
6083         }
6084
6085         return ret;
6086 }
6087
6088
6089 static inline enum ixgbe_5tuple_protocol
6090 convert_protocol_type(uint8_t protocol_value)
6091 {
6092         if (protocol_value == IPPROTO_TCP)
6093                 return IXGBE_FILTER_PROTOCOL_TCP;
6094         else if (protocol_value == IPPROTO_UDP)
6095                 return IXGBE_FILTER_PROTOCOL_UDP;
6096         else if (protocol_value == IPPROTO_SCTP)
6097                 return IXGBE_FILTER_PROTOCOL_SCTP;
6098         else
6099                 return IXGBE_FILTER_PROTOCOL_NONE;
6100 }
6101
6102 /* inject a 5-tuple filter to HW */
6103 static inline void
6104 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6105                            struct ixgbe_5tuple_filter *filter)
6106 {
6107         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6108         int i;
6109         uint32_t ftqf, sdpqf;
6110         uint32_t l34timir = 0;
6111         uint8_t mask = 0xff;
6112
6113         i = filter->index;
6114
6115         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6116                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6117         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6118
6119         ftqf = (uint32_t)(filter->filter_info.proto &
6120                 IXGBE_FTQF_PROTOCOL_MASK);
6121         ftqf |= (uint32_t)((filter->filter_info.priority &
6122                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6123         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6124                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6125         if (filter->filter_info.dst_ip_mask == 0)
6126                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6127         if (filter->filter_info.src_port_mask == 0)
6128                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6129         if (filter->filter_info.dst_port_mask == 0)
6130                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6131         if (filter->filter_info.proto_mask == 0)
6132                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6133         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6134         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6135         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6136
6137         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6138         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6139         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6140         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6141
6142         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6143         l34timir |= (uint32_t)(filter->queue <<
6144                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6145         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6146 }
6147
6148 /*
6149  * add a 5tuple filter
6150  *
6151  * @param
6152  * dev: Pointer to struct rte_eth_dev.
6153  * index: the index the filter allocates.
6154  * filter: ponter to the filter that will be added.
6155  * rx_queue: the queue id the filter assigned to.
6156  *
6157  * @return
6158  *    - On success, zero.
6159  *    - On failure, a negative value.
6160  */
6161 static int
6162 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6163                         struct ixgbe_5tuple_filter *filter)
6164 {
6165         struct ixgbe_filter_info *filter_info =
6166                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6167         int i, idx, shift;
6168
6169         /*
6170          * look for an unused 5tuple filter index,
6171          * and insert the filter to list.
6172          */
6173         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6174                 idx = i / (sizeof(uint32_t) * NBBY);
6175                 shift = i % (sizeof(uint32_t) * NBBY);
6176                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6177                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6178                         filter->index = i;
6179                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6180                                           filter,
6181                                           entries);
6182                         break;
6183                 }
6184         }
6185         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6186                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6187                 return -ENOSYS;
6188         }
6189
6190         ixgbe_inject_5tuple_filter(dev, filter);
6191
6192         return 0;
6193 }
6194
6195 /*
6196  * remove a 5tuple filter
6197  *
6198  * @param
6199  * dev: Pointer to struct rte_eth_dev.
6200  * filter: the pointer of the filter will be removed.
6201  */
6202 static void
6203 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6204                         struct ixgbe_5tuple_filter *filter)
6205 {
6206         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6207         struct ixgbe_filter_info *filter_info =
6208                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6209         uint16_t index = filter->index;
6210
6211         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6212                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6213         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6214         rte_free(filter);
6215
6216         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6217         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6218         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6219         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6220         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6221 }
6222
6223 static int
6224 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6225 {
6226         struct ixgbe_hw *hw;
6227         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6228         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6229
6230         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6231
6232         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6233                 return -EINVAL;
6234
6235         /* refuse mtu that requires the support of scattered packets when this
6236          * feature has not been enabled before.
6237          */
6238         if (!rx_conf->enable_scatter &&
6239             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6240              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6241                 return -EINVAL;
6242
6243         /*
6244          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6245          * request of the version 2.0 of the mailbox API.
6246          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6247          * of the mailbox API.
6248          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6249          * prior to 3.11.33 which contains the following change:
6250          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6251          */
6252         ixgbevf_rlpml_set_vf(hw, max_frame);
6253
6254         /* update max frame size */
6255         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6256         return 0;
6257 }
6258
6259 static inline struct ixgbe_5tuple_filter *
6260 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6261                         struct ixgbe_5tuple_filter_info *key)
6262 {
6263         struct ixgbe_5tuple_filter *it;
6264
6265         TAILQ_FOREACH(it, filter_list, entries) {
6266                 if (memcmp(key, &it->filter_info,
6267                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6268                         return it;
6269                 }
6270         }
6271         return NULL;
6272 }
6273
6274 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6275 static inline int
6276 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6277                         struct ixgbe_5tuple_filter_info *filter_info)
6278 {
6279         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6280                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6281                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6282                 return -EINVAL;
6283
6284         switch (filter->dst_ip_mask) {
6285         case UINT32_MAX:
6286                 filter_info->dst_ip_mask = 0;
6287                 filter_info->dst_ip = filter->dst_ip;
6288                 break;
6289         case 0:
6290                 filter_info->dst_ip_mask = 1;
6291                 break;
6292         default:
6293                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6294                 return -EINVAL;
6295         }
6296
6297         switch (filter->src_ip_mask) {
6298         case UINT32_MAX:
6299                 filter_info->src_ip_mask = 0;
6300                 filter_info->src_ip = filter->src_ip;
6301                 break;
6302         case 0:
6303                 filter_info->src_ip_mask = 1;
6304                 break;
6305         default:
6306                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6307                 return -EINVAL;
6308         }
6309
6310         switch (filter->dst_port_mask) {
6311         case UINT16_MAX:
6312                 filter_info->dst_port_mask = 0;
6313                 filter_info->dst_port = filter->dst_port;
6314                 break;
6315         case 0:
6316                 filter_info->dst_port_mask = 1;
6317                 break;
6318         default:
6319                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6320                 return -EINVAL;
6321         }
6322
6323         switch (filter->src_port_mask) {
6324         case UINT16_MAX:
6325                 filter_info->src_port_mask = 0;
6326                 filter_info->src_port = filter->src_port;
6327                 break;
6328         case 0:
6329                 filter_info->src_port_mask = 1;
6330                 break;
6331         default:
6332                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6333                 return -EINVAL;
6334         }
6335
6336         switch (filter->proto_mask) {
6337         case UINT8_MAX:
6338                 filter_info->proto_mask = 0;
6339                 filter_info->proto =
6340                         convert_protocol_type(filter->proto);
6341                 break;
6342         case 0:
6343                 filter_info->proto_mask = 1;
6344                 break;
6345         default:
6346                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6347                 return -EINVAL;
6348         }
6349
6350         filter_info->priority = (uint8_t)filter->priority;
6351         return 0;
6352 }
6353
6354 /*
6355  * add or delete a ntuple filter
6356  *
6357  * @param
6358  * dev: Pointer to struct rte_eth_dev.
6359  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6360  * add: if true, add filter, if false, remove filter
6361  *
6362  * @return
6363  *    - On success, zero.
6364  *    - On failure, a negative value.
6365  */
6366 int
6367 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6368                         struct rte_eth_ntuple_filter *ntuple_filter,
6369                         bool add)
6370 {
6371         struct ixgbe_filter_info *filter_info =
6372                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6373         struct ixgbe_5tuple_filter_info filter_5tuple;
6374         struct ixgbe_5tuple_filter *filter;
6375         int ret;
6376
6377         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6378                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6379                 return -EINVAL;
6380         }
6381
6382         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6383         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6384         if (ret < 0)
6385                 return ret;
6386
6387         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6388                                          &filter_5tuple);
6389         if (filter != NULL && add) {
6390                 PMD_DRV_LOG(ERR, "filter exists.");
6391                 return -EEXIST;
6392         }
6393         if (filter == NULL && !add) {
6394                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6395                 return -ENOENT;
6396         }
6397
6398         if (add) {
6399                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6400                                 sizeof(struct ixgbe_5tuple_filter), 0);
6401                 if (filter == NULL)
6402                         return -ENOMEM;
6403                 rte_memcpy(&filter->filter_info,
6404                                  &filter_5tuple,
6405                                  sizeof(struct ixgbe_5tuple_filter_info));
6406                 filter->queue = ntuple_filter->queue;
6407                 ret = ixgbe_add_5tuple_filter(dev, filter);
6408                 if (ret < 0) {
6409                         rte_free(filter);
6410                         return ret;
6411                 }
6412         } else
6413                 ixgbe_remove_5tuple_filter(dev, filter);
6414
6415         return 0;
6416 }
6417
6418 /*
6419  * get a ntuple filter
6420  *
6421  * @param
6422  * dev: Pointer to struct rte_eth_dev.
6423  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6424  *
6425  * @return
6426  *    - On success, zero.
6427  *    - On failure, a negative value.
6428  */
6429 static int
6430 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6431                         struct rte_eth_ntuple_filter *ntuple_filter)
6432 {
6433         struct ixgbe_filter_info *filter_info =
6434                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6435         struct ixgbe_5tuple_filter_info filter_5tuple;
6436         struct ixgbe_5tuple_filter *filter;
6437         int ret;
6438
6439         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6440                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6441                 return -EINVAL;
6442         }
6443
6444         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6445         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6446         if (ret < 0)
6447                 return ret;
6448
6449         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6450                                          &filter_5tuple);
6451         if (filter == NULL) {
6452                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6453                 return -ENOENT;
6454         }
6455         ntuple_filter->queue = filter->queue;
6456         return 0;
6457 }
6458
6459 /*
6460  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6461  * @dev: pointer to rte_eth_dev structure
6462  * @filter_op:operation will be taken.
6463  * @arg: a pointer to specific structure corresponding to the filter_op
6464  *
6465  * @return
6466  *    - On success, zero.
6467  *    - On failure, a negative value.
6468  */
6469 static int
6470 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6471                                 enum rte_filter_op filter_op,
6472                                 void *arg)
6473 {
6474         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6475         int ret;
6476
6477         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6478
6479         if (filter_op == RTE_ETH_FILTER_NOP)
6480                 return 0;
6481
6482         if (arg == NULL) {
6483                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6484                             filter_op);
6485                 return -EINVAL;
6486         }
6487
6488         switch (filter_op) {
6489         case RTE_ETH_FILTER_ADD:
6490                 ret = ixgbe_add_del_ntuple_filter(dev,
6491                         (struct rte_eth_ntuple_filter *)arg,
6492                         TRUE);
6493                 break;
6494         case RTE_ETH_FILTER_DELETE:
6495                 ret = ixgbe_add_del_ntuple_filter(dev,
6496                         (struct rte_eth_ntuple_filter *)arg,
6497                         FALSE);
6498                 break;
6499         case RTE_ETH_FILTER_GET:
6500                 ret = ixgbe_get_ntuple_filter(dev,
6501                         (struct rte_eth_ntuple_filter *)arg);
6502                 break;
6503         default:
6504                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6505                 ret = -EINVAL;
6506                 break;
6507         }
6508         return ret;
6509 }
6510
6511 int
6512 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6513                         struct rte_eth_ethertype_filter *filter,
6514                         bool add)
6515 {
6516         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6517         struct ixgbe_filter_info *filter_info =
6518                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6519         uint32_t etqf = 0;
6520         uint32_t etqs = 0;
6521         int ret;
6522         struct ixgbe_ethertype_filter ethertype_filter;
6523
6524         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6525                 return -EINVAL;
6526
6527         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6528                 filter->ether_type == ETHER_TYPE_IPv6) {
6529                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6530                         " ethertype filter.", filter->ether_type);
6531                 return -EINVAL;
6532         }
6533
6534         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6535                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6536                 return -EINVAL;
6537         }
6538         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6539                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6540                 return -EINVAL;
6541         }
6542
6543         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6544         if (ret >= 0 && add) {
6545                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6546                             filter->ether_type);
6547                 return -EEXIST;
6548         }
6549         if (ret < 0 && !add) {
6550                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6551                             filter->ether_type);
6552                 return -ENOENT;
6553         }
6554
6555         if (add) {
6556                 etqf = IXGBE_ETQF_FILTER_EN;
6557                 etqf |= (uint32_t)filter->ether_type;
6558                 etqs |= (uint32_t)((filter->queue <<
6559                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6560                                     IXGBE_ETQS_RX_QUEUE);
6561                 etqs |= IXGBE_ETQS_QUEUE_EN;
6562
6563                 ethertype_filter.ethertype = filter->ether_type;
6564                 ethertype_filter.etqf = etqf;
6565                 ethertype_filter.etqs = etqs;
6566                 ethertype_filter.conf = FALSE;
6567                 ret = ixgbe_ethertype_filter_insert(filter_info,
6568                                                     &ethertype_filter);
6569                 if (ret < 0) {
6570                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6571                         return -ENOSPC;
6572                 }
6573         } else {
6574                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6575                 if (ret < 0)
6576                         return -ENOSYS;
6577         }
6578         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6579         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6580         IXGBE_WRITE_FLUSH(hw);
6581
6582         return 0;
6583 }
6584
6585 static int
6586 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6587                         struct rte_eth_ethertype_filter *filter)
6588 {
6589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6590         struct ixgbe_filter_info *filter_info =
6591                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6592         uint32_t etqf, etqs;
6593         int ret;
6594
6595         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6596         if (ret < 0) {
6597                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6598                             filter->ether_type);
6599                 return -ENOENT;
6600         }
6601
6602         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6603         if (etqf & IXGBE_ETQF_FILTER_EN) {
6604                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6605                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6606                 filter->flags = 0;
6607                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6608                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6609                 return 0;
6610         }
6611         return -ENOENT;
6612 }
6613
6614 /*
6615  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6616  * @dev: pointer to rte_eth_dev structure
6617  * @filter_op:operation will be taken.
6618  * @arg: a pointer to specific structure corresponding to the filter_op
6619  */
6620 static int
6621 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6622                                 enum rte_filter_op filter_op,
6623                                 void *arg)
6624 {
6625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6626         int ret;
6627
6628         MAC_TYPE_FILTER_SUP(hw->mac.type);
6629
6630         if (filter_op == RTE_ETH_FILTER_NOP)
6631                 return 0;
6632
6633         if (arg == NULL) {
6634                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6635                             filter_op);
6636                 return -EINVAL;
6637         }
6638
6639         switch (filter_op) {
6640         case RTE_ETH_FILTER_ADD:
6641                 ret = ixgbe_add_del_ethertype_filter(dev,
6642                         (struct rte_eth_ethertype_filter *)arg,
6643                         TRUE);
6644                 break;
6645         case RTE_ETH_FILTER_DELETE:
6646                 ret = ixgbe_add_del_ethertype_filter(dev,
6647                         (struct rte_eth_ethertype_filter *)arg,
6648                         FALSE);
6649                 break;
6650         case RTE_ETH_FILTER_GET:
6651                 ret = ixgbe_get_ethertype_filter(dev,
6652                         (struct rte_eth_ethertype_filter *)arg);
6653                 break;
6654         default:
6655                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6656                 ret = -EINVAL;
6657                 break;
6658         }
6659         return ret;
6660 }
6661
6662 static int
6663 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6664                      enum rte_filter_type filter_type,
6665                      enum rte_filter_op filter_op,
6666                      void *arg)
6667 {
6668         int ret = 0;
6669
6670         switch (filter_type) {
6671         case RTE_ETH_FILTER_NTUPLE:
6672                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6673                 break;
6674         case RTE_ETH_FILTER_ETHERTYPE:
6675                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6676                 break;
6677         case RTE_ETH_FILTER_SYN:
6678                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6679                 break;
6680         case RTE_ETH_FILTER_FDIR:
6681                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6682                 break;
6683         case RTE_ETH_FILTER_L2_TUNNEL:
6684                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6685                 break;
6686         case RTE_ETH_FILTER_GENERIC:
6687                 if (filter_op != RTE_ETH_FILTER_GET)
6688                         return -EINVAL;
6689                 *(const void **)arg = &ixgbe_flow_ops;
6690                 break;
6691         default:
6692                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6693                                                         filter_type);
6694                 ret = -EINVAL;
6695                 break;
6696         }
6697
6698         return ret;
6699 }
6700
6701 static u8 *
6702 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6703                         u8 **mc_addr_ptr, u32 *vmdq)
6704 {
6705         u8 *mc_addr;
6706
6707         *vmdq = 0;
6708         mc_addr = *mc_addr_ptr;
6709         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6710         return mc_addr;
6711 }
6712
6713 static int
6714 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6715                           struct ether_addr *mc_addr_set,
6716                           uint32_t nb_mc_addr)
6717 {
6718         struct ixgbe_hw *hw;
6719         u8 *mc_addr_list;
6720
6721         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6722         mc_addr_list = (u8 *)mc_addr_set;
6723         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6724                                          ixgbe_dev_addr_list_itr, TRUE);
6725 }
6726
6727 static uint64_t
6728 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6729 {
6730         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6731         uint64_t systime_cycles;
6732
6733         switch (hw->mac.type) {
6734         case ixgbe_mac_X550:
6735         case ixgbe_mac_X550EM_x:
6736         case ixgbe_mac_X550EM_a:
6737                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6738                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6739                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6740                                 * NSEC_PER_SEC;
6741                 break;
6742         default:
6743                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6744                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6745                                 << 32;
6746         }
6747
6748         return systime_cycles;
6749 }
6750
6751 static uint64_t
6752 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6753 {
6754         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6755         uint64_t rx_tstamp_cycles;
6756
6757         switch (hw->mac.type) {
6758         case ixgbe_mac_X550:
6759         case ixgbe_mac_X550EM_x:
6760         case ixgbe_mac_X550EM_a:
6761                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6762                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6763                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6764                                 * NSEC_PER_SEC;
6765                 break;
6766         default:
6767                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6768                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6769                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6770                                 << 32;
6771         }
6772
6773         return rx_tstamp_cycles;
6774 }
6775
6776 static uint64_t
6777 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6778 {
6779         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6780         uint64_t tx_tstamp_cycles;
6781
6782         switch (hw->mac.type) {
6783         case ixgbe_mac_X550:
6784         case ixgbe_mac_X550EM_x:
6785         case ixgbe_mac_X550EM_a:
6786                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6787                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6788                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6789                                 * NSEC_PER_SEC;
6790                 break;
6791         default:
6792                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6793                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6794                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6795                                 << 32;
6796         }
6797
6798         return tx_tstamp_cycles;
6799 }
6800
6801 static void
6802 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6803 {
6804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6805         struct ixgbe_adapter *adapter =
6806                 (struct ixgbe_adapter *)dev->data->dev_private;
6807         struct rte_eth_link link;
6808         uint32_t incval = 0;
6809         uint32_t shift = 0;
6810
6811         /* Get current link speed. */
6812         memset(&link, 0, sizeof(link));
6813         ixgbe_dev_link_update(dev, 1);
6814         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6815
6816         switch (link.link_speed) {
6817         case ETH_SPEED_NUM_100M:
6818                 incval = IXGBE_INCVAL_100;
6819                 shift = IXGBE_INCVAL_SHIFT_100;
6820                 break;
6821         case ETH_SPEED_NUM_1G:
6822                 incval = IXGBE_INCVAL_1GB;
6823                 shift = IXGBE_INCVAL_SHIFT_1GB;
6824                 break;
6825         case ETH_SPEED_NUM_10G:
6826         default:
6827                 incval = IXGBE_INCVAL_10GB;
6828                 shift = IXGBE_INCVAL_SHIFT_10GB;
6829                 break;
6830         }
6831
6832         switch (hw->mac.type) {
6833         case ixgbe_mac_X550:
6834         case ixgbe_mac_X550EM_x:
6835         case ixgbe_mac_X550EM_a:
6836                 /* Independent of link speed. */
6837                 incval = 1;
6838                 /* Cycles read will be interpreted as ns. */
6839                 shift = 0;
6840                 /* Fall-through */
6841         case ixgbe_mac_X540:
6842                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6843                 break;
6844         case ixgbe_mac_82599EB:
6845                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6846                 shift -= IXGBE_INCVAL_SHIFT_82599;
6847                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6848                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6849                 break;
6850         default:
6851                 /* Not supported. */
6852                 return;
6853         }
6854
6855         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6856         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6857         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6858
6859         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6860         adapter->systime_tc.cc_shift = shift;
6861         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6862
6863         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6864         adapter->rx_tstamp_tc.cc_shift = shift;
6865         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6866
6867         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6868         adapter->tx_tstamp_tc.cc_shift = shift;
6869         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6870 }
6871
6872 static int
6873 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6874 {
6875         struct ixgbe_adapter *adapter =
6876                         (struct ixgbe_adapter *)dev->data->dev_private;
6877
6878         adapter->systime_tc.nsec += delta;
6879         adapter->rx_tstamp_tc.nsec += delta;
6880         adapter->tx_tstamp_tc.nsec += delta;
6881
6882         return 0;
6883 }
6884
6885 static int
6886 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6887 {
6888         uint64_t ns;
6889         struct ixgbe_adapter *adapter =
6890                         (struct ixgbe_adapter *)dev->data->dev_private;
6891
6892         ns = rte_timespec_to_ns(ts);
6893         /* Set the timecounters to a new value. */
6894         adapter->systime_tc.nsec = ns;
6895         adapter->rx_tstamp_tc.nsec = ns;
6896         adapter->tx_tstamp_tc.nsec = ns;
6897
6898         return 0;
6899 }
6900
6901 static int
6902 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6903 {
6904         uint64_t ns, systime_cycles;
6905         struct ixgbe_adapter *adapter =
6906                         (struct ixgbe_adapter *)dev->data->dev_private;
6907
6908         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6909         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6910         *ts = rte_ns_to_timespec(ns);
6911
6912         return 0;
6913 }
6914
6915 static int
6916 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6917 {
6918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6919         uint32_t tsync_ctl;
6920         uint32_t tsauxc;
6921
6922         /* Stop the timesync system time. */
6923         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6924         /* Reset the timesync system time value. */
6925         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6926         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6927
6928         /* Enable system time for platforms where it isn't on by default. */
6929         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6930         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6931         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6932
6933         ixgbe_start_timecounters(dev);
6934
6935         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6936         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6937                         (ETHER_TYPE_1588 |
6938                          IXGBE_ETQF_FILTER_EN |
6939                          IXGBE_ETQF_1588));
6940
6941         /* Enable timestamping of received PTP packets. */
6942         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6943         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6944         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6945
6946         /* Enable timestamping of transmitted PTP packets. */
6947         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6948         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6949         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6950
6951         IXGBE_WRITE_FLUSH(hw);
6952
6953         return 0;
6954 }
6955
6956 static int
6957 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6958 {
6959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6960         uint32_t tsync_ctl;
6961
6962         /* Disable timestamping of transmitted PTP packets. */
6963         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6964         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6965         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6966
6967         /* Disable timestamping of received PTP packets. */
6968         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6969         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6970         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6971
6972         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6973         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6974
6975         /* Stop incrementating the System Time registers. */
6976         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6977
6978         return 0;
6979 }
6980
6981 static int
6982 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6983                                  struct timespec *timestamp,
6984                                  uint32_t flags __rte_unused)
6985 {
6986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6987         struct ixgbe_adapter *adapter =
6988                 (struct ixgbe_adapter *)dev->data->dev_private;
6989         uint32_t tsync_rxctl;
6990         uint64_t rx_tstamp_cycles;
6991         uint64_t ns;
6992
6993         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6994         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6995                 return -EINVAL;
6996
6997         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6998         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6999         *timestamp = rte_ns_to_timespec(ns);
7000
7001         return  0;
7002 }
7003
7004 static int
7005 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7006                                  struct timespec *timestamp)
7007 {
7008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7009         struct ixgbe_adapter *adapter =
7010                 (struct ixgbe_adapter *)dev->data->dev_private;
7011         uint32_t tsync_txctl;
7012         uint64_t tx_tstamp_cycles;
7013         uint64_t ns;
7014
7015         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7016         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7017                 return -EINVAL;
7018
7019         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7020         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7021         *timestamp = rte_ns_to_timespec(ns);
7022
7023         return 0;
7024 }
7025
7026 static int
7027 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7028 {
7029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7030         int count = 0;
7031         int g_ind = 0;
7032         const struct reg_info *reg_group;
7033         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7034                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7035
7036         while ((reg_group = reg_set[g_ind++]))
7037                 count += ixgbe_regs_group_count(reg_group);
7038
7039         return count;
7040 }
7041
7042 static int
7043 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7044 {
7045         int count = 0;
7046         int g_ind = 0;
7047         const struct reg_info *reg_group;
7048
7049         while ((reg_group = ixgbevf_regs[g_ind++]))
7050                 count += ixgbe_regs_group_count(reg_group);
7051
7052         return count;
7053 }
7054
7055 static int
7056 ixgbe_get_regs(struct rte_eth_dev *dev,
7057               struct rte_dev_reg_info *regs)
7058 {
7059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7060         uint32_t *data = regs->data;
7061         int g_ind = 0;
7062         int count = 0;
7063         const struct reg_info *reg_group;
7064         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7065                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7066
7067         if (data == NULL) {
7068                 regs->length = ixgbe_get_reg_length(dev);
7069                 regs->width = sizeof(uint32_t);
7070                 return 0;
7071         }
7072
7073         /* Support only full register dump */
7074         if ((regs->length == 0) ||
7075             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7076                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7077                         hw->device_id;
7078                 while ((reg_group = reg_set[g_ind++]))
7079                         count += ixgbe_read_regs_group(dev, &data[count],
7080                                 reg_group);
7081                 return 0;
7082         }
7083
7084         return -ENOTSUP;
7085 }
7086
7087 static int
7088 ixgbevf_get_regs(struct rte_eth_dev *dev,
7089                 struct rte_dev_reg_info *regs)
7090 {
7091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7092         uint32_t *data = regs->data;
7093         int g_ind = 0;
7094         int count = 0;
7095         const struct reg_info *reg_group;
7096
7097         if (data == NULL) {
7098                 regs->length = ixgbevf_get_reg_length(dev);
7099                 regs->width = sizeof(uint32_t);
7100                 return 0;
7101         }
7102
7103         /* Support only full register dump */
7104         if ((regs->length == 0) ||
7105             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7106                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7107                         hw->device_id;
7108                 while ((reg_group = ixgbevf_regs[g_ind++]))
7109                         count += ixgbe_read_regs_group(dev, &data[count],
7110                                                       reg_group);
7111                 return 0;
7112         }
7113
7114         return -ENOTSUP;
7115 }
7116
7117 static int
7118 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7119 {
7120         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7121
7122         /* Return unit is byte count */
7123         return hw->eeprom.word_size * 2;
7124 }
7125
7126 static int
7127 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7128                 struct rte_dev_eeprom_info *in_eeprom)
7129 {
7130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7131         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7132         uint16_t *data = in_eeprom->data;
7133         int first, length;
7134
7135         first = in_eeprom->offset >> 1;
7136         length = in_eeprom->length >> 1;
7137         if ((first > hw->eeprom.word_size) ||
7138             ((first + length) > hw->eeprom.word_size))
7139                 return -EINVAL;
7140
7141         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7142
7143         return eeprom->ops.read_buffer(hw, first, length, data);
7144 }
7145
7146 static int
7147 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7148                 struct rte_dev_eeprom_info *in_eeprom)
7149 {
7150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7151         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7152         uint16_t *data = in_eeprom->data;
7153         int first, length;
7154
7155         first = in_eeprom->offset >> 1;
7156         length = in_eeprom->length >> 1;
7157         if ((first > hw->eeprom.word_size) ||
7158             ((first + length) > hw->eeprom.word_size))
7159                 return -EINVAL;
7160
7161         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7162
7163         return eeprom->ops.write_buffer(hw,  first, length, data);
7164 }
7165
7166 uint16_t
7167 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7168         switch (mac_type) {
7169         case ixgbe_mac_X550:
7170         case ixgbe_mac_X550EM_x:
7171         case ixgbe_mac_X550EM_a:
7172                 return ETH_RSS_RETA_SIZE_512;
7173         case ixgbe_mac_X550_vf:
7174         case ixgbe_mac_X550EM_x_vf:
7175         case ixgbe_mac_X550EM_a_vf:
7176                 return ETH_RSS_RETA_SIZE_64;
7177         default:
7178                 return ETH_RSS_RETA_SIZE_128;
7179         }
7180 }
7181
7182 uint32_t
7183 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7184         switch (mac_type) {
7185         case ixgbe_mac_X550:
7186         case ixgbe_mac_X550EM_x:
7187         case ixgbe_mac_X550EM_a:
7188                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7189                         return IXGBE_RETA(reta_idx >> 2);
7190                 else
7191                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7192         case ixgbe_mac_X550_vf:
7193         case ixgbe_mac_X550EM_x_vf:
7194         case ixgbe_mac_X550EM_a_vf:
7195                 return IXGBE_VFRETA(reta_idx >> 2);
7196         default:
7197                 return IXGBE_RETA(reta_idx >> 2);
7198         }
7199 }
7200
7201 uint32_t
7202 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7203         switch (mac_type) {
7204         case ixgbe_mac_X550_vf:
7205         case ixgbe_mac_X550EM_x_vf:
7206         case ixgbe_mac_X550EM_a_vf:
7207                 return IXGBE_VFMRQC;
7208         default:
7209                 return IXGBE_MRQC;
7210         }
7211 }
7212
7213 uint32_t
7214 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7215         switch (mac_type) {
7216         case ixgbe_mac_X550_vf:
7217         case ixgbe_mac_X550EM_x_vf:
7218         case ixgbe_mac_X550EM_a_vf:
7219                 return IXGBE_VFRSSRK(i);
7220         default:
7221                 return IXGBE_RSSRK(i);
7222         }
7223 }
7224
7225 bool
7226 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7227         switch (mac_type) {
7228         case ixgbe_mac_82599_vf:
7229         case ixgbe_mac_X540_vf:
7230                 return 0;
7231         default:
7232                 return 1;
7233         }
7234 }
7235
7236 static int
7237 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7238                         struct rte_eth_dcb_info *dcb_info)
7239 {
7240         struct ixgbe_dcb_config *dcb_config =
7241                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7242         struct ixgbe_dcb_tc_config *tc;
7243         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7244         uint8_t nb_tcs;
7245         uint8_t i, j;
7246
7247         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7248                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7249         else
7250                 dcb_info->nb_tcs = 1;
7251
7252         tc_queue = &dcb_info->tc_queue;
7253         nb_tcs = dcb_info->nb_tcs;
7254
7255         if (dcb_config->vt_mode) { /* vt is enabled*/
7256                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7257                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7258                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7259                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7260                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7261                         for (j = 0; j < nb_tcs; j++) {
7262                                 tc_queue->tc_rxq[0][j].base = j;
7263                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7264                                 tc_queue->tc_txq[0][j].base = j;
7265                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7266                         }
7267                 } else {
7268                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7269                                 for (j = 0; j < nb_tcs; j++) {
7270                                         tc_queue->tc_rxq[i][j].base =
7271                                                 i * nb_tcs + j;
7272                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7273                                         tc_queue->tc_txq[i][j].base =
7274                                                 i * nb_tcs + j;
7275                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7276                                 }
7277                         }
7278                 }
7279         } else { /* vt is disabled*/
7280                 struct rte_eth_dcb_rx_conf *rx_conf =
7281                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7282                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7283                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7284                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7285                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7286                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7287                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7288                         }
7289                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7290                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7291                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7292                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7293                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7294                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7295                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7296                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7297                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7298                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7299                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7300                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7301                         }
7302                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7303                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7304                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7305                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7306                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7307                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7308                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7309                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7310                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7311                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7312                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7313                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7314                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7315                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7316                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7317                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7318                 }
7319         }
7320         for (i = 0; i < dcb_info->nb_tcs; i++) {
7321                 tc = &dcb_config->tc_config[i];
7322                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7323         }
7324         return 0;
7325 }
7326
7327 /* Update e-tag ether type */
7328 static int
7329 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7330                             uint16_t ether_type)
7331 {
7332         uint32_t etag_etype;
7333
7334         if (hw->mac.type != ixgbe_mac_X550 &&
7335             hw->mac.type != ixgbe_mac_X550EM_x &&
7336             hw->mac.type != ixgbe_mac_X550EM_a) {
7337                 return -ENOTSUP;
7338         }
7339
7340         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7341         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7342         etag_etype |= ether_type;
7343         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7344         IXGBE_WRITE_FLUSH(hw);
7345
7346         return 0;
7347 }
7348
7349 /* Config l2 tunnel ether type */
7350 static int
7351 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7352                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7353 {
7354         int ret = 0;
7355         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7356         struct ixgbe_l2_tn_info *l2_tn_info =
7357                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7358
7359         if (l2_tunnel == NULL)
7360                 return -EINVAL;
7361
7362         switch (l2_tunnel->l2_tunnel_type) {
7363         case RTE_L2_TUNNEL_TYPE_E_TAG:
7364                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7365                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7366                 break;
7367         default:
7368                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7369                 ret = -EINVAL;
7370                 break;
7371         }
7372
7373         return ret;
7374 }
7375
7376 /* Enable e-tag tunnel */
7377 static int
7378 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7379 {
7380         uint32_t etag_etype;
7381
7382         if (hw->mac.type != ixgbe_mac_X550 &&
7383             hw->mac.type != ixgbe_mac_X550EM_x &&
7384             hw->mac.type != ixgbe_mac_X550EM_a) {
7385                 return -ENOTSUP;
7386         }
7387
7388         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7389         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7390         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7391         IXGBE_WRITE_FLUSH(hw);
7392
7393         return 0;
7394 }
7395
7396 /* Enable l2 tunnel */
7397 static int
7398 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7399                            enum rte_eth_tunnel_type l2_tunnel_type)
7400 {
7401         int ret = 0;
7402         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7403         struct ixgbe_l2_tn_info *l2_tn_info =
7404                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7405
7406         switch (l2_tunnel_type) {
7407         case RTE_L2_TUNNEL_TYPE_E_TAG:
7408                 l2_tn_info->e_tag_en = TRUE;
7409                 ret = ixgbe_e_tag_enable(hw);
7410                 break;
7411         default:
7412                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7413                 ret = -EINVAL;
7414                 break;
7415         }
7416
7417         return ret;
7418 }
7419
7420 /* Disable e-tag tunnel */
7421 static int
7422 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7423 {
7424         uint32_t etag_etype;
7425
7426         if (hw->mac.type != ixgbe_mac_X550 &&
7427             hw->mac.type != ixgbe_mac_X550EM_x &&
7428             hw->mac.type != ixgbe_mac_X550EM_a) {
7429                 return -ENOTSUP;
7430         }
7431
7432         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7433         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7434         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7435         IXGBE_WRITE_FLUSH(hw);
7436
7437         return 0;
7438 }
7439
7440 /* Disable l2 tunnel */
7441 static int
7442 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7443                             enum rte_eth_tunnel_type l2_tunnel_type)
7444 {
7445         int ret = 0;
7446         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7447         struct ixgbe_l2_tn_info *l2_tn_info =
7448                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7449
7450         switch (l2_tunnel_type) {
7451         case RTE_L2_TUNNEL_TYPE_E_TAG:
7452                 l2_tn_info->e_tag_en = FALSE;
7453                 ret = ixgbe_e_tag_disable(hw);
7454                 break;
7455         default:
7456                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7457                 ret = -EINVAL;
7458                 break;
7459         }
7460
7461         return ret;
7462 }
7463
7464 static int
7465 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7466                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7467 {
7468         int ret = 0;
7469         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7470         uint32_t i, rar_entries;
7471         uint32_t rar_low, rar_high;
7472
7473         if (hw->mac.type != ixgbe_mac_X550 &&
7474             hw->mac.type != ixgbe_mac_X550EM_x &&
7475             hw->mac.type != ixgbe_mac_X550EM_a) {
7476                 return -ENOTSUP;
7477         }
7478
7479         rar_entries = ixgbe_get_num_rx_addrs(hw);
7480
7481         for (i = 1; i < rar_entries; i++) {
7482                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7483                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7484                 if ((rar_high & IXGBE_RAH_AV) &&
7485                     (rar_high & IXGBE_RAH_ADTYPE) &&
7486                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7487                      l2_tunnel->tunnel_id)) {
7488                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7489                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7490
7491                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7492
7493                         return ret;
7494                 }
7495         }
7496
7497         return ret;
7498 }
7499
7500 static int
7501 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7502                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7503 {
7504         int ret = 0;
7505         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7506         uint32_t i, rar_entries;
7507         uint32_t rar_low, rar_high;
7508
7509         if (hw->mac.type != ixgbe_mac_X550 &&
7510             hw->mac.type != ixgbe_mac_X550EM_x &&
7511             hw->mac.type != ixgbe_mac_X550EM_a) {
7512                 return -ENOTSUP;
7513         }
7514
7515         /* One entry for one tunnel. Try to remove potential existing entry. */
7516         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7517
7518         rar_entries = ixgbe_get_num_rx_addrs(hw);
7519
7520         for (i = 1; i < rar_entries; i++) {
7521                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7522                 if (rar_high & IXGBE_RAH_AV) {
7523                         continue;
7524                 } else {
7525                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7526                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7527                         rar_low = l2_tunnel->tunnel_id;
7528
7529                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7530                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7531
7532                         return ret;
7533                 }
7534         }
7535
7536         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7537                      " Please remove a rule before adding a new one.");
7538         return -EINVAL;
7539 }
7540
7541 static inline struct ixgbe_l2_tn_filter *
7542 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7543                           struct ixgbe_l2_tn_key *key)
7544 {
7545         int ret;
7546
7547         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7548         if (ret < 0)
7549                 return NULL;
7550
7551         return l2_tn_info->hash_map[ret];
7552 }
7553
7554 static inline int
7555 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7556                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7557 {
7558         int ret;
7559
7560         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7561                                &l2_tn_filter->key);
7562
7563         if (ret < 0) {
7564                 PMD_DRV_LOG(ERR,
7565                             "Failed to insert L2 tunnel filter"
7566                             " to hash table %d!",
7567                             ret);
7568                 return ret;
7569         }
7570
7571         l2_tn_info->hash_map[ret] = l2_tn_filter;
7572
7573         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7574
7575         return 0;
7576 }
7577
7578 static inline int
7579 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7580                           struct ixgbe_l2_tn_key *key)
7581 {
7582         int ret;
7583         struct ixgbe_l2_tn_filter *l2_tn_filter;
7584
7585         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7586
7587         if (ret < 0) {
7588                 PMD_DRV_LOG(ERR,
7589                             "No such L2 tunnel filter to delete %d!",
7590                             ret);
7591                 return ret;
7592         }
7593
7594         l2_tn_filter = l2_tn_info->hash_map[ret];
7595         l2_tn_info->hash_map[ret] = NULL;
7596
7597         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7598         rte_free(l2_tn_filter);
7599
7600         return 0;
7601 }
7602
7603 /* Add l2 tunnel filter */
7604 int
7605 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7606                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7607                                bool restore)
7608 {
7609         int ret;
7610         struct ixgbe_l2_tn_info *l2_tn_info =
7611                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7612         struct ixgbe_l2_tn_key key;
7613         struct ixgbe_l2_tn_filter *node;
7614
7615         if (!restore) {
7616                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7617                 key.tn_id = l2_tunnel->tunnel_id;
7618
7619                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7620
7621                 if (node) {
7622                         PMD_DRV_LOG(ERR,
7623                                     "The L2 tunnel filter already exists!");
7624                         return -EINVAL;
7625                 }
7626
7627                 node = rte_zmalloc("ixgbe_l2_tn",
7628                                    sizeof(struct ixgbe_l2_tn_filter),
7629                                    0);
7630                 if (!node)
7631                         return -ENOMEM;
7632
7633                 rte_memcpy(&node->key,
7634                                  &key,
7635                                  sizeof(struct ixgbe_l2_tn_key));
7636                 node->pool = l2_tunnel->pool;
7637                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7638                 if (ret < 0) {
7639                         rte_free(node);
7640                         return ret;
7641                 }
7642         }
7643
7644         switch (l2_tunnel->l2_tunnel_type) {
7645         case RTE_L2_TUNNEL_TYPE_E_TAG:
7646                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7647                 break;
7648         default:
7649                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7650                 ret = -EINVAL;
7651                 break;
7652         }
7653
7654         if ((!restore) && (ret < 0))
7655                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7656
7657         return ret;
7658 }
7659
7660 /* Delete l2 tunnel filter */
7661 int
7662 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7663                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7664 {
7665         int ret;
7666         struct ixgbe_l2_tn_info *l2_tn_info =
7667                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7668         struct ixgbe_l2_tn_key key;
7669
7670         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7671         key.tn_id = l2_tunnel->tunnel_id;
7672         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7673         if (ret < 0)
7674                 return ret;
7675
7676         switch (l2_tunnel->l2_tunnel_type) {
7677         case RTE_L2_TUNNEL_TYPE_E_TAG:
7678                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7679                 break;
7680         default:
7681                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7682                 ret = -EINVAL;
7683                 break;
7684         }
7685
7686         return ret;
7687 }
7688
7689 /**
7690  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7691  * @dev: pointer to rte_eth_dev structure
7692  * @filter_op:operation will be taken.
7693  * @arg: a pointer to specific structure corresponding to the filter_op
7694  */
7695 static int
7696 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7697                                   enum rte_filter_op filter_op,
7698                                   void *arg)
7699 {
7700         int ret;
7701
7702         if (filter_op == RTE_ETH_FILTER_NOP)
7703                 return 0;
7704
7705         if (arg == NULL) {
7706                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7707                             filter_op);
7708                 return -EINVAL;
7709         }
7710
7711         switch (filter_op) {
7712         case RTE_ETH_FILTER_ADD:
7713                 ret = ixgbe_dev_l2_tunnel_filter_add
7714                         (dev,
7715                          (struct rte_eth_l2_tunnel_conf *)arg,
7716                          FALSE);
7717                 break;
7718         case RTE_ETH_FILTER_DELETE:
7719                 ret = ixgbe_dev_l2_tunnel_filter_del
7720                         (dev,
7721                          (struct rte_eth_l2_tunnel_conf *)arg);
7722                 break;
7723         default:
7724                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7725                 ret = -EINVAL;
7726                 break;
7727         }
7728         return ret;
7729 }
7730
7731 static int
7732 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7733 {
7734         int ret = 0;
7735         uint32_t ctrl;
7736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7737
7738         if (hw->mac.type != ixgbe_mac_X550 &&
7739             hw->mac.type != ixgbe_mac_X550EM_x &&
7740             hw->mac.type != ixgbe_mac_X550EM_a) {
7741                 return -ENOTSUP;
7742         }
7743
7744         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7745         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7746         if (en)
7747                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7748         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7749
7750         return ret;
7751 }
7752
7753 /* Enable l2 tunnel forwarding */
7754 static int
7755 ixgbe_dev_l2_tunnel_forwarding_enable
7756         (struct rte_eth_dev *dev,
7757          enum rte_eth_tunnel_type l2_tunnel_type)
7758 {
7759         struct ixgbe_l2_tn_info *l2_tn_info =
7760                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7761         int ret = 0;
7762
7763         switch (l2_tunnel_type) {
7764         case RTE_L2_TUNNEL_TYPE_E_TAG:
7765                 l2_tn_info->e_tag_fwd_en = TRUE;
7766                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7767                 break;
7768         default:
7769                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7770                 ret = -EINVAL;
7771                 break;
7772         }
7773
7774         return ret;
7775 }
7776
7777 /* Disable l2 tunnel forwarding */
7778 static int
7779 ixgbe_dev_l2_tunnel_forwarding_disable
7780         (struct rte_eth_dev *dev,
7781          enum rte_eth_tunnel_type l2_tunnel_type)
7782 {
7783         struct ixgbe_l2_tn_info *l2_tn_info =
7784                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7785         int ret = 0;
7786
7787         switch (l2_tunnel_type) {
7788         case RTE_L2_TUNNEL_TYPE_E_TAG:
7789                 l2_tn_info->e_tag_fwd_en = FALSE;
7790                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7791                 break;
7792         default:
7793                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7794                 ret = -EINVAL;
7795                 break;
7796         }
7797
7798         return ret;
7799 }
7800
7801 static int
7802 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7803                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7804                              bool en)
7805 {
7806         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7807         int ret = 0;
7808         uint32_t vmtir, vmvir;
7809         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7810
7811         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7812                 PMD_DRV_LOG(ERR,
7813                             "VF id %u should be less than %u",
7814                             l2_tunnel->vf_id,
7815                             pci_dev->max_vfs);
7816                 return -EINVAL;
7817         }
7818
7819         if (hw->mac.type != ixgbe_mac_X550 &&
7820             hw->mac.type != ixgbe_mac_X550EM_x &&
7821             hw->mac.type != ixgbe_mac_X550EM_a) {
7822                 return -ENOTSUP;
7823         }
7824
7825         if (en)
7826                 vmtir = l2_tunnel->tunnel_id;
7827         else
7828                 vmtir = 0;
7829
7830         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7831
7832         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7833         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7834         if (en)
7835                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7836         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7837
7838         return ret;
7839 }
7840
7841 /* Enable l2 tunnel tag insertion */
7842 static int
7843 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7844                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7845 {
7846         int ret = 0;
7847
7848         switch (l2_tunnel->l2_tunnel_type) {
7849         case RTE_L2_TUNNEL_TYPE_E_TAG:
7850                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7851                 break;
7852         default:
7853                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7854                 ret = -EINVAL;
7855                 break;
7856         }
7857
7858         return ret;
7859 }
7860
7861 /* Disable l2 tunnel tag insertion */
7862 static int
7863 ixgbe_dev_l2_tunnel_insertion_disable
7864         (struct rte_eth_dev *dev,
7865          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7866 {
7867         int ret = 0;
7868
7869         switch (l2_tunnel->l2_tunnel_type) {
7870         case RTE_L2_TUNNEL_TYPE_E_TAG:
7871                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7872                 break;
7873         default:
7874                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7875                 ret = -EINVAL;
7876                 break;
7877         }
7878
7879         return ret;
7880 }
7881
7882 static int
7883 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7884                              bool en)
7885 {
7886         int ret = 0;
7887         uint32_t qde;
7888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7889
7890         if (hw->mac.type != ixgbe_mac_X550 &&
7891             hw->mac.type != ixgbe_mac_X550EM_x &&
7892             hw->mac.type != ixgbe_mac_X550EM_a) {
7893                 return -ENOTSUP;
7894         }
7895
7896         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7897         if (en)
7898                 qde |= IXGBE_QDE_STRIP_TAG;
7899         else
7900                 qde &= ~IXGBE_QDE_STRIP_TAG;
7901         qde &= ~IXGBE_QDE_READ;
7902         qde |= IXGBE_QDE_WRITE;
7903         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7904
7905         return ret;
7906 }
7907
7908 /* Enable l2 tunnel tag stripping */
7909 static int
7910 ixgbe_dev_l2_tunnel_stripping_enable
7911         (struct rte_eth_dev *dev,
7912          enum rte_eth_tunnel_type l2_tunnel_type)
7913 {
7914         int ret = 0;
7915
7916         switch (l2_tunnel_type) {
7917         case RTE_L2_TUNNEL_TYPE_E_TAG:
7918                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7919                 break;
7920         default:
7921                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7922                 ret = -EINVAL;
7923                 break;
7924         }
7925
7926         return ret;
7927 }
7928
7929 /* Disable l2 tunnel tag stripping */
7930 static int
7931 ixgbe_dev_l2_tunnel_stripping_disable
7932         (struct rte_eth_dev *dev,
7933          enum rte_eth_tunnel_type l2_tunnel_type)
7934 {
7935         int ret = 0;
7936
7937         switch (l2_tunnel_type) {
7938         case RTE_L2_TUNNEL_TYPE_E_TAG:
7939                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7940                 break;
7941         default:
7942                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7943                 ret = -EINVAL;
7944                 break;
7945         }
7946
7947         return ret;
7948 }
7949
7950 /* Enable/disable l2 tunnel offload functions */
7951 static int
7952 ixgbe_dev_l2_tunnel_offload_set
7953         (struct rte_eth_dev *dev,
7954          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7955          uint32_t mask,
7956          uint8_t en)
7957 {
7958         int ret = 0;
7959
7960         if (l2_tunnel == NULL)
7961                 return -EINVAL;
7962
7963         ret = -EINVAL;
7964         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7965                 if (en)
7966                         ret = ixgbe_dev_l2_tunnel_enable(
7967                                 dev,
7968                                 l2_tunnel->l2_tunnel_type);
7969                 else
7970                         ret = ixgbe_dev_l2_tunnel_disable(
7971                                 dev,
7972                                 l2_tunnel->l2_tunnel_type);
7973         }
7974
7975         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7976                 if (en)
7977                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7978                                 dev,
7979                                 l2_tunnel);
7980                 else
7981                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7982                                 dev,
7983                                 l2_tunnel);
7984         }
7985
7986         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7987                 if (en)
7988                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7989                                 dev,
7990                                 l2_tunnel->l2_tunnel_type);
7991                 else
7992                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7993                                 dev,
7994                                 l2_tunnel->l2_tunnel_type);
7995         }
7996
7997         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7998                 if (en)
7999                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8000                                 dev,
8001                                 l2_tunnel->l2_tunnel_type);
8002                 else
8003                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8004                                 dev,
8005                                 l2_tunnel->l2_tunnel_type);
8006         }
8007
8008         return ret;
8009 }
8010
8011 static int
8012 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8013                         uint16_t port)
8014 {
8015         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8016         IXGBE_WRITE_FLUSH(hw);
8017
8018         return 0;
8019 }
8020
8021 /* There's only one register for VxLAN UDP port.
8022  * So, we cannot add several ports. Will update it.
8023  */
8024 static int
8025 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8026                      uint16_t port)
8027 {
8028         if (port == 0) {
8029                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8030                 return -EINVAL;
8031         }
8032
8033         return ixgbe_update_vxlan_port(hw, port);
8034 }
8035
8036 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8037  * UDP port, it must have a value.
8038  * So, will reset it to the original value 0.
8039  */
8040 static int
8041 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8042                      uint16_t port)
8043 {
8044         uint16_t cur_port;
8045
8046         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8047
8048         if (cur_port != port) {
8049                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8050                 return -EINVAL;
8051         }
8052
8053         return ixgbe_update_vxlan_port(hw, 0);
8054 }
8055
8056 /* Add UDP tunneling port */
8057 static int
8058 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8059                               struct rte_eth_udp_tunnel *udp_tunnel)
8060 {
8061         int ret = 0;
8062         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8063
8064         if (hw->mac.type != ixgbe_mac_X550 &&
8065             hw->mac.type != ixgbe_mac_X550EM_x &&
8066             hw->mac.type != ixgbe_mac_X550EM_a) {
8067                 return -ENOTSUP;
8068         }
8069
8070         if (udp_tunnel == NULL)
8071                 return -EINVAL;
8072
8073         switch (udp_tunnel->prot_type) {
8074         case RTE_TUNNEL_TYPE_VXLAN:
8075                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8076                 break;
8077
8078         case RTE_TUNNEL_TYPE_GENEVE:
8079         case RTE_TUNNEL_TYPE_TEREDO:
8080                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8081                 ret = -EINVAL;
8082                 break;
8083
8084         default:
8085                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8086                 ret = -EINVAL;
8087                 break;
8088         }
8089
8090         return ret;
8091 }
8092
8093 /* Remove UDP tunneling port */
8094 static int
8095 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8096                               struct rte_eth_udp_tunnel *udp_tunnel)
8097 {
8098         int ret = 0;
8099         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8100
8101         if (hw->mac.type != ixgbe_mac_X550 &&
8102             hw->mac.type != ixgbe_mac_X550EM_x &&
8103             hw->mac.type != ixgbe_mac_X550EM_a) {
8104                 return -ENOTSUP;
8105         }
8106
8107         if (udp_tunnel == NULL)
8108                 return -EINVAL;
8109
8110         switch (udp_tunnel->prot_type) {
8111         case RTE_TUNNEL_TYPE_VXLAN:
8112                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8113                 break;
8114         case RTE_TUNNEL_TYPE_GENEVE:
8115         case RTE_TUNNEL_TYPE_TEREDO:
8116                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8117                 ret = -EINVAL;
8118                 break;
8119         default:
8120                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8121                 ret = -EINVAL;
8122                 break;
8123         }
8124
8125         return ret;
8126 }
8127
8128 static void
8129 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8130 {
8131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8132
8133         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8134 }
8135
8136 static void
8137 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8138 {
8139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8140
8141         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8142 }
8143
8144 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8145 {
8146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8147         u32 in_msg = 0;
8148
8149         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8150                 return;
8151
8152         /* PF reset VF event */
8153         if (in_msg == IXGBE_PF_CONTROL_MSG)
8154                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8155                                               NULL, NULL);
8156 }
8157
8158 static int
8159 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8160 {
8161         uint32_t eicr;
8162         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8163         struct ixgbe_interrupt *intr =
8164                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8165         ixgbevf_intr_disable(hw);
8166
8167         /* read-on-clear nic registers here */
8168         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8169         intr->flags = 0;
8170
8171         /* only one misc vector supported - mailbox */
8172         eicr &= IXGBE_VTEICR_MASK;
8173         if (eicr == IXGBE_MISC_VEC_ID)
8174                 intr->flags |= IXGBE_FLAG_MAILBOX;
8175
8176         return 0;
8177 }
8178
8179 static int
8180 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8181 {
8182         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8183         struct ixgbe_interrupt *intr =
8184                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8185
8186         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8187                 ixgbevf_mbx_process(dev);
8188                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8189         }
8190
8191         ixgbevf_intr_enable(hw);
8192
8193         return 0;
8194 }
8195
8196 static void
8197 ixgbevf_dev_interrupt_handler(void *param)
8198 {
8199         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8200
8201         ixgbevf_dev_interrupt_get_status(dev);
8202         ixgbevf_dev_interrupt_action(dev);
8203 }
8204
8205 /**
8206  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8207  *  @hw: pointer to hardware structure
8208  *
8209  *  Stops the transmit data path and waits for the HW to internally empty
8210  *  the Tx security block
8211  **/
8212 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8213 {
8214 #define IXGBE_MAX_SECTX_POLL 40
8215
8216         int i;
8217         int sectxreg;
8218
8219         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8220         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8221         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8222         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8223                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8224                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8225                         break;
8226                 /* Use interrupt-safe sleep just in case */
8227                 usec_delay(1000);
8228         }
8229
8230         /* For informational purposes only */
8231         if (i >= IXGBE_MAX_SECTX_POLL)
8232                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8233                          "path fully disabled.  Continuing with init.");
8234
8235         return IXGBE_SUCCESS;
8236 }
8237
8238 /**
8239  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8240  *  @hw: pointer to hardware structure
8241  *
8242  *  Enables the transmit data path.
8243  **/
8244 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8245 {
8246         uint32_t sectxreg;
8247
8248         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8249         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8250         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8251         IXGBE_WRITE_FLUSH(hw);
8252
8253         return IXGBE_SUCCESS;
8254 }
8255
8256 /* restore n-tuple filter */
8257 static inline void
8258 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8259 {
8260         struct ixgbe_filter_info *filter_info =
8261                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8262         struct ixgbe_5tuple_filter *node;
8263
8264         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8265                 ixgbe_inject_5tuple_filter(dev, node);
8266         }
8267 }
8268
8269 /* restore ethernet type filter */
8270 static inline void
8271 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8272 {
8273         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8274         struct ixgbe_filter_info *filter_info =
8275                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8276         int i;
8277
8278         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8279                 if (filter_info->ethertype_mask & (1 << i)) {
8280                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8281                                         filter_info->ethertype_filters[i].etqf);
8282                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8283                                         filter_info->ethertype_filters[i].etqs);
8284                         IXGBE_WRITE_FLUSH(hw);
8285                 }
8286         }
8287 }
8288
8289 /* restore SYN filter */
8290 static inline void
8291 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8292 {
8293         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8294         struct ixgbe_filter_info *filter_info =
8295                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8296         uint32_t synqf;
8297
8298         synqf = filter_info->syn_info;
8299
8300         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8301                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8302                 IXGBE_WRITE_FLUSH(hw);
8303         }
8304 }
8305
8306 /* restore L2 tunnel filter */
8307 static inline void
8308 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8309 {
8310         struct ixgbe_l2_tn_info *l2_tn_info =
8311                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8312         struct ixgbe_l2_tn_filter *node;
8313         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8314
8315         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8316                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8317                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8318                 l2_tn_conf.pool           = node->pool;
8319                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8320         }
8321 }
8322
8323 static int
8324 ixgbe_filter_restore(struct rte_eth_dev *dev)
8325 {
8326         ixgbe_ntuple_filter_restore(dev);
8327         ixgbe_ethertype_filter_restore(dev);
8328         ixgbe_syn_filter_restore(dev);
8329         ixgbe_fdir_filter_restore(dev);
8330         ixgbe_l2_tn_filter_restore(dev);
8331
8332         return 0;
8333 }
8334
8335 static void
8336 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8337 {
8338         struct ixgbe_l2_tn_info *l2_tn_info =
8339                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8340         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8341
8342         if (l2_tn_info->e_tag_en)
8343                 (void)ixgbe_e_tag_enable(hw);
8344
8345         if (l2_tn_info->e_tag_fwd_en)
8346                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8347
8348         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8349 }
8350
8351 /* remove all the n-tuple filters */
8352 void
8353 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8354 {
8355         struct ixgbe_filter_info *filter_info =
8356                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8357         struct ixgbe_5tuple_filter *p_5tuple;
8358
8359         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8360                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8361 }
8362
8363 /* remove all the ether type filters */
8364 void
8365 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8366 {
8367         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8368         struct ixgbe_filter_info *filter_info =
8369                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8370         int i;
8371
8372         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8373                 if (filter_info->ethertype_mask & (1 << i) &&
8374                     !filter_info->ethertype_filters[i].conf) {
8375                         (void)ixgbe_ethertype_filter_remove(filter_info,
8376                                                             (uint8_t)i);
8377                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8378                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8379                         IXGBE_WRITE_FLUSH(hw);
8380                 }
8381         }
8382 }
8383
8384 /* remove the SYN filter */
8385 void
8386 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8387 {
8388         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8389         struct ixgbe_filter_info *filter_info =
8390                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8391
8392         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8393                 filter_info->syn_info = 0;
8394
8395                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8396                 IXGBE_WRITE_FLUSH(hw);
8397         }
8398 }
8399
8400 /* remove all the L2 tunnel filters */
8401 int
8402 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8403 {
8404         struct ixgbe_l2_tn_info *l2_tn_info =
8405                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8406         struct ixgbe_l2_tn_filter *l2_tn_filter;
8407         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8408         int ret = 0;
8409
8410         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8411                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8412                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8413                 l2_tn_conf.pool           = l2_tn_filter->pool;
8414                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8415                 if (ret < 0)
8416                         return ret;
8417         }
8418
8419         return 0;
8420 }
8421
8422 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8423 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8424 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8425 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8426 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8427 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");