drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 enum ixgbevf_xcast_modes {
 158         IXGBEVF_XCAST_MODE_NONE = 0,
 159         IXGBEVF_XCAST_MODE_MULTI,
 160         IXGBEVF_XCAST_MODE_ALLMULTI,
 161 };
 162
 163 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 164 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 165
 166 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 167 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 197                                struct rte_eth_dev_info *dev_info);
 198 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 199 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 200                                  struct rte_eth_dev_info *dev_info);
 201 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 202
 203 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 204                 uint16_t vlan_id, int on);
 205 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 206                                enum rte_vlan_type vlan_type,
 207                                uint16_t tpid_id);
 208 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 209                 uint16_t queue, bool on);
 210 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 211                 int on);
 212 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 213 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 214 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 215 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 216 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 217
 218 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 220 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 221                                struct rte_eth_fc_conf *fc_conf);
 222 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 225                 struct rte_eth_pfc_conf *pfc_conf);
 226 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 227                         struct rte_eth_rss_reta_entry64 *reta_conf,
 228                         uint16_t reta_size);
 229 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 230                         struct rte_eth_rss_reta_entry64 *reta_conf,
 231                         uint16_t reta_size);
 232 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 233 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 237                                       struct rte_intr_handle *handle);
 238 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 239                 void *param);
 240 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 241 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 242                 uint32_t index, uint32_t pool);
 243 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 244 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 245                                            struct ether_addr *mac_addr);
 246 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 247
 248 /* For Virtual Function support */
 249 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 250 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 251 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 252 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 256 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 257 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 258                 struct rte_eth_stats *stats);
 259 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 260 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 261                 uint16_t vlan_id, int on);
 262 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 263                 uint16_t queue, int on);
 264 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id);
 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 269                                              uint16_t queue_id);
 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 271                                  uint8_t queue, uint8_t msix_vector);
 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 273 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 274 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 275
 276 /* For Eth VMDQ APIs support */
 277 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 278                 ether_addr * mac_addr, uint8_t on);
 279 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 280 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 281                 uint16_t rx_mask, uint8_t on);
 282 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 283 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 284 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 285                 uint64_t pool_mask, uint8_t vlan_on);
 286 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 287                 struct rte_eth_mirror_conf *mirror_conf,
 288                 uint8_t rule_id, uint8_t on);
 289 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 290                 uint8_t rule_id);
 291 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 292                                           uint16_t queue_id);
 293 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 294                                            uint16_t queue_id);
 295 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 296                                uint8_t queue, uint8_t msix_vector);
 297 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 298
 299 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 300                 uint16_t queue_idx, uint16_t tx_rate);
 301 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 302                 uint16_t tx_rate, uint64_t q_msk);
 303
 304 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 305                                  struct ether_addr *mac_addr,
 306                                  uint32_t index, uint32_t pool);
 307 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 308 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 309                                              struct ether_addr *mac_addr);
 310 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 311                         struct rte_eth_syn_filter *filter,
 312                         bool add);
 313 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 314                         struct rte_eth_syn_filter *filter);
 315 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 316                         enum rte_filter_op filter_op,
 317                         void *arg);
 318 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 319                         struct ixgbe_5tuple_filter *filter);
 320 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 321                         struct ixgbe_5tuple_filter *filter);
 322 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 323                         struct rte_eth_ntuple_filter *filter,
 324                         bool add);
 325 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 326                                 enum rte_filter_op filter_op,
 327                                 void *arg);
 328 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 329                         struct rte_eth_ntuple_filter *filter);
 330 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 331                         struct rte_eth_ethertype_filter *filter,
 332                         bool add);
 333 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 334                                 enum rte_filter_op filter_op,
 335                                 void *arg);
 336 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 337                         struct rte_eth_ethertype_filter *filter);
 338 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 339                      enum rte_filter_type filter_type,
 340                      enum rte_filter_op filter_op,
 341                      void *arg);
 342 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 343
 344 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 345                                       struct ether_addr *mc_addr_set,
 346                                       uint32_t nb_mc_addr);
 347 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 348                                    struct rte_eth_dcb_info *dcb_info);
 349
 350 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 351 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 352                             struct rte_dev_reg_info *regs);
 353 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 354 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 355                                 struct rte_dev_eeprom_info *eeprom);
 356 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 357                                 struct rte_dev_eeprom_info *eeprom);
 358
 359 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 360 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 361                                 struct rte_dev_reg_info *regs);
 362
 363 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 364 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 365 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 366                                             struct timespec *timestamp,
 367                                             uint32_t flags);
 368 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 369                                             struct timespec *timestamp);
 370 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 371 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 372                                    struct timespec *timestamp);
 373 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 374                                    const struct timespec *timestamp);
 375 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 376                                           void *param);
 377
 378 static int ixgbe_dev_l2_tunnel_eth_type_conf
 379         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 380 static int ixgbe_dev_l2_tunnel_offload_set
 381         (struct rte_eth_dev *dev,
 382          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 383          uint32_t mask,
 384          uint8_t en);
 385 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 386                                              enum rte_filter_op filter_op,
 387                                              void *arg);
 388
 389 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 390                                          struct rte_eth_udp_tunnel *udp_tunnel);
 391 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 392                                          struct rte_eth_udp_tunnel *udp_tunnel);
 393
 394 /*
 395  * Define VF Stats MACRO for Non "cleared on read" register
 396  */
 397 #define UPDATE_VF_STAT(reg, last, cur)                          \
 398 {                                                               \
 399         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 400         cur += (latest - last) & UINT_MAX;                      \
 401         last = latest;                                          \
 402 }
 403
 404 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 405 {                                                                \
 406         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 407         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 408         u64 latest = ((new_msb << 32) | new_lsb);                \
 409         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 410         last = latest;                                           \
 411 }
 412
 413 #define IXGBE_SET_HWSTRIP(h, q) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (h)->bitmap[idx] |= 1 << bit;\
 417         } while (0)
 418
 419 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 420                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 421                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 422                 (h)->bitmap[idx] &= ~(1 << bit);\
 423         } while (0)
 424
 425 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 426                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 427                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 428                 (r) = (h)->bitmap[idx] >> bit & 1;\
 429         } while (0)
 430
 431 /*
 432  * The set of PCI devices this driver supports
 433  */
 434 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 488 #ifdef RTE_NIC_BYPASS
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 490 #endif
 491         { .vendor_id = 0, /* sentinel */ },
 492 };
 493
 494 /*
 495  * The set of PCI devices this driver supports (for 82599 VF)
 496  */
 497 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 507         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 508         { .vendor_id = 0, /* sentinel */ },
 509 };
 510
 511 static const struct rte_eth_desc_lim rx_desc_lim = {
 512         .nb_max = IXGBE_MAX_RING_DESC,
 513         .nb_min = IXGBE_MIN_RING_DESC,
 514         .nb_align = IXGBE_RXD_ALIGN,
 515 };
 516
 517 static const struct rte_eth_desc_lim tx_desc_lim = {
 518         .nb_max = IXGBE_MAX_RING_DESC,
 519         .nb_min = IXGBE_MIN_RING_DESC,
 520         .nb_align = IXGBE_TXD_ALIGN,
 521 };
 522
 523 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 524         .dev_configure        = ixgbe_dev_configure,
 525         .dev_start            = ixgbe_dev_start,
 526         .dev_stop             = ixgbe_dev_stop,
 527         .dev_set_link_up    = ixgbe_dev_set_link_up,
 528         .dev_set_link_down  = ixgbe_dev_set_link_down,
 529         .dev_close            = ixgbe_dev_close,
 530         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 531         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 532         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 533         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 534         .link_update          = ixgbe_dev_link_update,
 535         .stats_get            = ixgbe_dev_stats_get,
 536         .xstats_get           = ixgbe_dev_xstats_get,
 537         .stats_reset          = ixgbe_dev_stats_reset,
 538         .xstats_reset         = ixgbe_dev_xstats_reset,
 539         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 540         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 541         .dev_infos_get        = ixgbe_dev_info_get,
 542         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 543         .mtu_set              = ixgbe_dev_mtu_set,
 544         .vlan_filter_set      = ixgbe_vlan_filter_set,
 545         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 546         .vlan_offload_set     = ixgbe_vlan_offload_set,
 547         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 548         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 549         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 550         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 551         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 552         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 553         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 554         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 555         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 556         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 557         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 558         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 559         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 560         .dev_led_on           = ixgbe_dev_led_on,
 561         .dev_led_off          = ixgbe_dev_led_off,
 562         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 563         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 564         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 565         .mac_addr_add         = ixgbe_add_rar,
 566         .mac_addr_remove      = ixgbe_remove_rar,
 567         .mac_addr_set         = ixgbe_set_default_mac_addr,
 568         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 569         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 570         .mirror_rule_set      = ixgbe_mirror_rule_set,
 571         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 572         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 573         .set_vf_rx            = ixgbe_set_pool_rx,
 574         .set_vf_tx            = ixgbe_set_pool_tx,
 575         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 576         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 577         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 578         .reta_update          = ixgbe_dev_rss_reta_update,
 579         .reta_query           = ixgbe_dev_rss_reta_query,
 580 #ifdef RTE_NIC_BYPASS
 581         .bypass_init          = ixgbe_bypass_init,
 582         .bypass_state_set     = ixgbe_bypass_state_store,
 583         .bypass_state_show    = ixgbe_bypass_state_show,
 584         .bypass_event_set     = ixgbe_bypass_event_store,
 585         .bypass_event_show    = ixgbe_bypass_event_show,
 586         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 587         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 588         .bypass_ver_show      = ixgbe_bypass_ver_show,
 589         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 590 #endif /* RTE_NIC_BYPASS */
 591         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 592         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 593         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 594         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 595         .rxq_info_get         = ixgbe_rxq_info_get,
 596         .txq_info_get         = ixgbe_txq_info_get,
 597         .timesync_enable      = ixgbe_timesync_enable,
 598         .timesync_disable     = ixgbe_timesync_disable,
 599         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 600         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 601         .get_reg              = ixgbe_get_regs,
 602         .get_eeprom_length    = ixgbe_get_eeprom_length,
 603         .get_eeprom           = ixgbe_get_eeprom,
 604         .set_eeprom           = ixgbe_set_eeprom,
 605         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 606         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 607         .timesync_read_time   = ixgbe_timesync_read_time,
 608         .timesync_write_time  = ixgbe_timesync_write_time,
 609         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 610         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 611         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 612         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 613 };
 614
 615 /*
 616  * dev_ops for virtual function, bare necessities for basic vf
 617  * operation have been implemented
 618  */
 619 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 620         .dev_configure        = ixgbevf_dev_configure,
 621         .dev_start            = ixgbevf_dev_start,
 622         .dev_stop             = ixgbevf_dev_stop,
 623         .link_update          = ixgbe_dev_link_update,
 624         .stats_get            = ixgbevf_dev_stats_get,
 625         .xstats_get           = ixgbevf_dev_xstats_get,
 626         .stats_reset          = ixgbevf_dev_stats_reset,
 627         .xstats_reset         = ixgbevf_dev_stats_reset,
 628         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 629         .dev_close            = ixgbevf_dev_close,
 630         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 631         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 632         .dev_infos_get        = ixgbevf_dev_info_get,
 633         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 634         .mtu_set              = ixgbevf_dev_set_mtu,
 635         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 636         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 637         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 638         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 639         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 640         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 641         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 642         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 643         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 644         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 645         .mac_addr_add         = ixgbevf_add_mac_addr,
 646         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 647         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 648         .rxq_info_get         = ixgbe_rxq_info_get,
 649         .txq_info_get         = ixgbe_txq_info_get,
 650         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 651         .get_reg              = ixgbevf_get_regs,
 652         .reta_update          = ixgbe_dev_rss_reta_update,
 653         .reta_query           = ixgbe_dev_rss_reta_query,
 654         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 655         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 656 };
 657
 658 /* store statistics names and its offset in stats structure */
 659 struct rte_ixgbe_xstats_name_off {
 660         char name[RTE_ETH_XSTATS_NAME_SIZE];
 661         unsigned offset;
 662 };
 663
 664 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 665         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 666         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 667         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 668         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 669         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 670         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 671         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 672         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 673         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 674         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 675         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 676         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 677         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 678         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 679         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 680                 prc1023)},
 681         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 682                 prc1522)},
 683         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 684         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 685         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 686         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 687         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 688         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 689         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 690         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 691         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 692         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 693         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 694         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 695         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 696         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 697         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 698         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 699         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 700                 ptc1023)},
 701         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 702                 ptc1522)},
 703         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 704         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 705         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 706         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 707
 708         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 709                 fdirustat_add)},
 710         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirustat_remove)},
 712         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 713                 fdirfstat_fadd)},
 714         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 715                 fdirfstat_fremove)},
 716         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 717                 fdirmatch)},
 718         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 719                 fdirmiss)},
 720
 721         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 722         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 723         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 724                 fclast)},
 725         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 726         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 727         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 728         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 729         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 730                 fcoe_noddp)},
 731         {"rx_fcoe_no_direct_data_placement_ext_buff",
 732                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 733
 734         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 735                 lxontxc)},
 736         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxonrxc)},
 738         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxofftxc)},
 740         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxoffrxc)},
 742         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 743 };
 744
 745 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 746                            sizeof(rte_ixgbe_stats_strings[0]))
 747
 748 /* Per-queue statistics */
 749 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 750         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 751         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 752         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 753         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 754 };
 755
 756 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 757                            sizeof(rte_ixgbe_rxq_strings[0]))
 758 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 759
 760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 761         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 762         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 763         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 764                 pxon2offc)},
 765 };
 766
 767 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 768                            sizeof(rte_ixgbe_txq_strings[0]))
 769 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 770
 771 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 772         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 773 };
 774
 775 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 776                 sizeof(rte_ixgbevf_stats_strings[0]))
 777
 778 /**
 779  * Atomically reads the link status information from global
 780  * structure rte_eth_dev.
 781  *
 782  * @param dev
 783  *   - Pointer to the structure rte_eth_dev to read from.
 784  *   - Pointer to the buffer to be saved with the link status.
 785  *
 786  * @return
 787  *   - On success, zero.
 788  *   - On failure, negative value.
 789  */
 790 static inline int
 791 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 792                                 struct rte_eth_link *link)
 793 {
 794         struct rte_eth_link *dst = link;
 795         struct rte_eth_link *src = &(dev->data->dev_link);
 796
 797         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 798                                         *(uint64_t *)src) == 0)
 799                 return -1;
 800
 801         return 0;
 802 }
 803
 804 /**
 805  * Atomically writes the link status information into global
 806  * structure rte_eth_dev.
 807  *
 808  * @param dev
 809  *   - Pointer to the structure rte_eth_dev to read from.
 810  *   - Pointer to the buffer to be saved with the link status.
 811  *
 812  * @return
 813  *   - On success, zero.
 814  *   - On failure, negative value.
 815  */
 816 static inline int
 817 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 818                                 struct rte_eth_link *link)
 819 {
 820         struct rte_eth_link *dst = &(dev->data->dev_link);
 821         struct rte_eth_link *src = link;
 822
 823         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 824                                         *(uint64_t *)src) == 0)
 825                 return -1;
 826
 827         return 0;
 828 }
 829
 830 /*
 831  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 832  */
 833 static inline int
 834 ixgbe_is_sfp(struct ixgbe_hw *hw)
 835 {
 836         switch (hw->phy.type) {
 837         case ixgbe_phy_sfp_avago:
 838         case ixgbe_phy_sfp_ftl:
 839         case ixgbe_phy_sfp_intel:
 840         case ixgbe_phy_sfp_unknown:
 841         case ixgbe_phy_sfp_passive_tyco:
 842         case ixgbe_phy_sfp_passive_unknown:
 843                 return 1;
 844         default:
 845                 return 0;
 846         }
 847 }
 848
 849 static inline int32_t
 850 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 851 {
 852         uint32_t ctrl_ext;
 853         int32_t status;
 854
 855         status = ixgbe_reset_hw(hw);
 856
 857         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 858         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 859         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 860         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 861         IXGBE_WRITE_FLUSH(hw);
 862
 863         return status;
 864 }
 865
 866 static inline void
 867 ixgbe_enable_intr(struct rte_eth_dev *dev)
 868 {
 869         struct ixgbe_interrupt *intr =
 870                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 871         struct ixgbe_hw *hw =
 872                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 873
 874         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 875         IXGBE_WRITE_FLUSH(hw);
 876 }
 877
 878 /*
 879  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 880  */
 881 static void
 882 ixgbe_disable_intr(struct ixgbe_hw *hw)
 883 {
 884         PMD_INIT_FUNC_TRACE();
 885
 886         if (hw->mac.type == ixgbe_mac_82598EB) {
 887                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 888         } else {
 889                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 890                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 891                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 892         }
 893         IXGBE_WRITE_FLUSH(hw);
 894 }
 895
 896 /*
 897  * This function resets queue statistics mapping registers.
 898  * From Niantic datasheet, Initialization of Statistics section:
 899  * "...if software requires the queue counters, the RQSMR and TQSM registers
 900  * must be re-programmed following a device reset.
 901  */
 902 static void
 903 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 904 {
 905         uint32_t i;
 906
 907         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 908                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 909                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 910         }
 911 }
 912
 913
 914 static int
 915 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 916                                   uint16_t queue_id,
 917                                   uint8_t stat_idx,
 918                                   uint8_t is_rx)
 919 {
 920 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 921 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 922 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 923
 924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 925         struct ixgbe_stat_mapping_registers *stat_mappings =
 926                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 927         uint32_t qsmr_mask = 0;
 928         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 929         uint32_t q_map;
 930         uint8_t n, offset;
 931
 932         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 933                 (hw->mac.type != ixgbe_mac_X540) &&
 934                 (hw->mac.type != ixgbe_mac_X550) &&
 935                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 936                 (hw->mac.type != ixgbe_mac_X550EM_a))
 937                 return -ENOSYS;
 938
 939         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 940                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 941                      queue_id, stat_idx);
 942
 943         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 944         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 945                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 946                 return -EIO;
 947         }
 948         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 949
 950         /* Now clear any previous stat_idx set */
 951         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 952         if (!is_rx)
 953                 stat_mappings->tqsm[n] &= ~clearing_mask;
 954         else
 955                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 956
 957         q_map = (uint32_t)stat_idx;
 958         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 959         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 960         if (!is_rx)
 961                 stat_mappings->tqsm[n] |= qsmr_mask;
 962         else
 963                 stat_mappings->rqsmr[n] |= qsmr_mask;
 964
 965         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 966                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 967                      queue_id, stat_idx);
 968         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 969                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 970
 971         /* Now write the mapping in the appropriate register */
 972         if (is_rx) {
 973                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 974                              stat_mappings->rqsmr[n], n);
 975                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 976         } else {
 977                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 978                              stat_mappings->tqsm[n], n);
 979                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 980         }
 981         return 0;
 982 }
 983
 984 static void
 985 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 986 {
 987         struct ixgbe_stat_mapping_registers *stat_mappings =
 988                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 990         int i;
 991
 992         /* write whatever was in stat mapping table to the NIC */
 993         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 994                 /* rx */
 995                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 996
 997                 /* tx */
 998                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 999         }
1000 }
1001
1002 static void
1003 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1004 {
1005         uint8_t i;
1006         struct ixgbe_dcb_tc_config *tc;
1007         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1008
1009         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1010         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1011         for (i = 0; i < dcb_max_tc; i++) {
1012                 tc = &dcb_config->tc_config[i];
1013                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1014                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1015                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1016                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1017                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1018                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1019                 tc->pfc = ixgbe_dcb_pfc_disabled;
1020         }
1021
1022         /* Initialize default user to priority mapping, UPx->TC0 */
1023         tc = &dcb_config->tc_config[0];
1024         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1025         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1026         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1027                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1028                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1029         }
1030         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1031         dcb_config->pfc_mode_enable = false;
1032         dcb_config->vt_mode = true;
1033         dcb_config->round_robin_enable = false;
1034         /* support all DCB capabilities in 82599 */
1035         dcb_config->support.capabilities = 0xFF;
1036
1037         /*we only support 4 Tcs for X540, X550 */
1038         if (hw->mac.type == ixgbe_mac_X540 ||
1039                 hw->mac.type == ixgbe_mac_X550 ||
1040                 hw->mac.type == ixgbe_mac_X550EM_x ||
1041                 hw->mac.type == ixgbe_mac_X550EM_a) {
1042                 dcb_config->num_tcs.pg_tcs = 4;
1043                 dcb_config->num_tcs.pfc_tcs = 4;
1044         }
1045 }
1046
1047 /*
1048  * Ensure that all locks are released before first NVM or PHY access
1049  */
1050 static void
1051 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1052 {
1053         uint16_t mask;
1054
1055         /*
1056          * Phy lock should not fail in this early stage. If this is the case,
1057          * it is due to an improper exit of the application.
1058          * So force the release of the faulty lock. Release of common lock
1059          * is done automatically by swfw_sync function.
1060          */
1061         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1062         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1063                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1064         }
1065         ixgbe_release_swfw_semaphore(hw, mask);
1066
1067         /*
1068          * These ones are more tricky since they are common to all ports; but
1069          * swfw_sync retries last long enough (1s) to be almost sure that if
1070          * lock can not be taken it is due to an improper lock of the
1071          * semaphore.
1072          */
1073         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1074         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1075                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1076         }
1077         ixgbe_release_swfw_semaphore(hw, mask);
1078 }
1079
1080 /*
1081  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1082  * It returns 0 on success.
1083  */
1084 static int
1085 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1086 {
1087         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1088         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1089         struct ixgbe_hw *hw =
1090                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1091         struct ixgbe_vfta *shadow_vfta =
1092                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1093         struct ixgbe_hwstrip *hwstrip =
1094                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1095         struct ixgbe_dcb_config *dcb_config =
1096                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1097         struct ixgbe_filter_info *filter_info =
1098                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1099         uint32_t ctrl_ext;
1100         uint16_t csum;
1101         int diag, i;
1102
1103         PMD_INIT_FUNC_TRACE();
1104
1105         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1106         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1107         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1108
1109         /*
1110          * For secondary processes, we don't initialise any further as primary
1111          * has already done this work. Only check we don't need a different
1112          * RX and TX function.
1113          */
1114         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1115                 struct ixgbe_tx_queue *txq;
1116                 /* TX queue function in primary, set by last queue initialized
1117                  * Tx queue may not initialized by primary process
1118                  */
1119                 if (eth_dev->data->tx_queues) {
1120                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1121                         ixgbe_set_tx_function(eth_dev, txq);
1122                 } else {
1123                         /* Use default TX function if we get here */
1124                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1125                                      "Using default TX function.");
1126                 }
1127
1128                 ixgbe_set_rx_function(eth_dev);
1129
1130                 return 0;
1131         }
1132
1133         rte_eth_copy_pci_info(eth_dev, pci_dev);
1134
1135         /* Vendor and Device ID need to be set before init of shared code */
1136         hw->device_id = pci_dev->id.device_id;
1137         hw->vendor_id = pci_dev->id.vendor_id;
1138         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1139         hw->allow_unsupported_sfp = 1;
1140
1141         /* Initialize the shared code (base driver) */
1142 #ifdef RTE_NIC_BYPASS
1143         diag = ixgbe_bypass_init_shared_code(hw);
1144 #else
1145         diag = ixgbe_init_shared_code(hw);
1146 #endif /* RTE_NIC_BYPASS */
1147
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1150                 return -EIO;
1151         }
1152
1153         /* pick up the PCI bus settings for reporting later */
1154         ixgbe_get_bus_info(hw);
1155
1156         /* Unlock any pending hardware semaphore */
1157         ixgbe_swfw_lock_reset(hw);
1158
1159         /* Initialize DCB configuration*/
1160         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1161         ixgbe_dcb_init(hw, dcb_config);
1162         /* Get Hardware Flow Control setting */
1163         hw->fc.requested_mode = ixgbe_fc_full;
1164         hw->fc.current_mode = ixgbe_fc_full;
1165         hw->fc.pause_time = IXGBE_FC_PAUSE;
1166         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1167                 hw->fc.low_water[i] = IXGBE_FC_LO;
1168                 hw->fc.high_water[i] = IXGBE_FC_HI;
1169         }
1170         hw->fc.send_xon = 1;
1171
1172         /* Make sure we have a good EEPROM before we read from it */
1173         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1174         if (diag != IXGBE_SUCCESS) {
1175                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1176                 return -EIO;
1177         }
1178
1179 #ifdef RTE_NIC_BYPASS
1180         diag = ixgbe_bypass_init_hw(hw);
1181 #else
1182         diag = ixgbe_init_hw(hw);
1183 #endif /* RTE_NIC_BYPASS */
1184
1185         /*
1186          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1187          * is called too soon after the kernel driver unbinding/binding occurs.
1188          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1189          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1190          * also called. See ixgbe_identify_phy_82599(). The reason for the
1191          * failure is not known, and only occuts when virtualisation features
1192          * are disabled in the bios. A delay of 100ms  was found to be enough by
1193          * trial-and-error, and is doubled to be safe.
1194          */
1195         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1196                 rte_delay_ms(200);
1197                 diag = ixgbe_init_hw(hw);
1198         }
1199
1200         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1201                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1202                              "LOM.  Please be aware there may be issues associated "
1203                              "with your hardware.");
1204                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1205                              "please contact your Intel or hardware representative "
1206                              "who provided you with this hardware.");
1207         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1208                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1209         if (diag) {
1210                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1211                 return -EIO;
1212         }
1213
1214         /* Reset the hw statistics */
1215         ixgbe_dev_stats_reset(eth_dev);
1216
1217         /* disable interrupt */
1218         ixgbe_disable_intr(hw);
1219
1220         /* reset mappings for queue statistics hw counters*/
1221         ixgbe_reset_qstat_mappings(hw);
1222
1223         /* Allocate memory for storing MAC addresses */
1224         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1225                                                hw->mac.num_rar_entries, 0);
1226         if (eth_dev->data->mac_addrs == NULL) {
1227                 PMD_INIT_LOG(ERR,
1228                              "Failed to allocate %u bytes needed to store "
1229                              "MAC addresses",
1230                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1231                 return -ENOMEM;
1232         }
1233         /* Copy the permanent MAC address */
1234         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1235                         &eth_dev->data->mac_addrs[0]);
1236
1237         /* Allocate memory for storing hash filter MAC addresses */
1238         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1239                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1240         if (eth_dev->data->hash_mac_addrs == NULL) {
1241                 PMD_INIT_LOG(ERR,
1242                              "Failed to allocate %d bytes needed to store MAC addresses",
1243                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1244                 return -ENOMEM;
1245         }
1246
1247         /* initialize the vfta */
1248         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1249
1250         /* initialize the hw strip bitmap*/
1251         memset(hwstrip, 0, sizeof(*hwstrip));
1252
1253         /* initialize PF if max_vfs not zero */
1254         ixgbe_pf_host_init(eth_dev);
1255
1256         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1257         /* let hardware know driver is loaded */
1258         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1259         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1260         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1261         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1262         IXGBE_WRITE_FLUSH(hw);
1263
1264         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1265                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1266                              (int) hw->mac.type, (int) hw->phy.type,
1267                              (int) hw->phy.sfp_type);
1268         else
1269                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1270                              (int) hw->mac.type, (int) hw->phy.type);
1271
1272         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1273                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1274                      pci_dev->id.device_id);
1275
1276         rte_intr_callback_register(intr_handle,
1277                                    ixgbe_dev_interrupt_handler, eth_dev);
1278
1279         /* enable uio/vfio intr/eventfd mapping */
1280         rte_intr_enable(intr_handle);
1281
1282         /* enable support intr */
1283         ixgbe_enable_intr(eth_dev);
1284
1285         /* initialize 5tuple filter list */
1286         TAILQ_INIT(&filter_info->fivetuple_list);
1287         memset(filter_info->fivetuple_mask, 0,
1288                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1289
1290         return 0;
1291 }
1292
1293 static int
1294 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1295 {
1296         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1297         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1298         struct ixgbe_hw *hw;
1299
1300         PMD_INIT_FUNC_TRACE();
1301
1302         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1303                 return -EPERM;
1304
1305         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1306
1307         if (hw->adapter_stopped == 0)
1308                 ixgbe_dev_close(eth_dev);
1309
1310         eth_dev->dev_ops = NULL;
1311         eth_dev->rx_pkt_burst = NULL;
1312         eth_dev->tx_pkt_burst = NULL;
1313
1314         /* Unlock any pending hardware semaphore */
1315         ixgbe_swfw_lock_reset(hw);
1316
1317         /* disable uio intr before callback unregister */
1318         rte_intr_disable(intr_handle);
1319         rte_intr_callback_unregister(intr_handle,
1320                                      ixgbe_dev_interrupt_handler, eth_dev);
1321
1322         /* uninitialize PF if max_vfs not zero */
1323         ixgbe_pf_host_uninit(eth_dev);
1324
1325         rte_free(eth_dev->data->mac_addrs);
1326         eth_dev->data->mac_addrs = NULL;
1327
1328         rte_free(eth_dev->data->hash_mac_addrs);
1329         eth_dev->data->hash_mac_addrs = NULL;
1330
1331         return 0;
1332 }
1333
1334 /*
1335  * Negotiate mailbox API version with the PF.
1336  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1337  * Then we try to negotiate starting with the most recent one.
1338  * If all negotiation attempts fail, then we will proceed with
1339  * the default one (ixgbe_mbox_api_10).
1340  */
1341 static void
1342 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1343 {
1344         int32_t i;
1345
1346         /* start with highest supported, proceed down */
1347         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1348                 ixgbe_mbox_api_12,
1349                 ixgbe_mbox_api_11,
1350                 ixgbe_mbox_api_10,
1351         };
1352
1353         for (i = 0;
1354                         i != RTE_DIM(sup_ver) &&
1355                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1356                         i++)
1357                 ;
1358 }
1359
1360 static void
1361 generate_random_mac_addr(struct ether_addr *mac_addr)
1362 {
1363         uint64_t random;
1364
1365         /* Set Organizationally Unique Identifier (OUI) prefix. */
1366         mac_addr->addr_bytes[0] = 0x00;
1367         mac_addr->addr_bytes[1] = 0x09;
1368         mac_addr->addr_bytes[2] = 0xC0;
1369         /* Force indication of locally assigned MAC address. */
1370         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1371         /* Generate the last 3 bytes of the MAC address with a random number. */
1372         random = rte_rand();
1373         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1374 }
1375
1376 /*
1377  * Virtual Function device init
1378  */
1379 static int
1380 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1381 {
1382         int diag;
1383         uint32_t tc, tcs;
1384         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1385         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1386         struct ixgbe_hw *hw =
1387                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1388         struct ixgbe_vfta *shadow_vfta =
1389                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1390         struct ixgbe_hwstrip *hwstrip =
1391                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1392         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1393
1394         PMD_INIT_FUNC_TRACE();
1395
1396         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1397         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1398         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1399
1400         /* for secondary processes, we don't initialise any further as primary
1401          * has already done this work. Only check we don't need a different
1402          * RX function
1403          */
1404         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1405                 struct ixgbe_tx_queue *txq;
1406                 /* TX queue function in primary, set by last queue initialized
1407                  * Tx queue may not initialized by primary process
1408                  */
1409                 if (eth_dev->data->tx_queues) {
1410                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1411                         ixgbe_set_tx_function(eth_dev, txq);
1412                 } else {
1413                         /* Use default TX function if we get here */
1414                         PMD_INIT_LOG(NOTICE,
1415                                      "No TX queues configured yet. Using default TX function.");
1416                 }
1417
1418                 ixgbe_set_rx_function(eth_dev);
1419
1420                 return 0;
1421         }
1422
1423         rte_eth_copy_pci_info(eth_dev, pci_dev);
1424
1425         hw->device_id = pci_dev->id.device_id;
1426         hw->vendor_id = pci_dev->id.vendor_id;
1427         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1428
1429         /* initialize the vfta */
1430         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1431
1432         /* initialize the hw strip bitmap*/
1433         memset(hwstrip, 0, sizeof(*hwstrip));
1434
1435         /* Initialize the shared code (base driver) */
1436         diag = ixgbe_init_shared_code(hw);
1437         if (diag != IXGBE_SUCCESS) {
1438                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1439                 return -EIO;
1440         }
1441
1442         /* init_mailbox_params */
1443         hw->mbx.ops.init_params(hw);
1444
1445         /* Reset the hw statistics */
1446         ixgbevf_dev_stats_reset(eth_dev);
1447
1448         /* Disable the interrupts for VF */
1449         ixgbevf_intr_disable(hw);
1450
1451         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1452         diag = hw->mac.ops.reset_hw(hw);
1453
1454         /*
1455          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1456          * the underlying PF driver has not assigned a MAC address to the VF.
1457          * In this case, assign a random MAC address.
1458          */
1459         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1460                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1461                 return diag;
1462         }
1463
1464         /* negotiate mailbox API version to use with the PF. */
1465         ixgbevf_negotiate_api(hw);
1466
1467         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1468         ixgbevf_get_queues(hw, &tcs, &tc);
1469
1470         /* Allocate memory for storing MAC addresses */
1471         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1472                                                hw->mac.num_rar_entries, 0);
1473         if (eth_dev->data->mac_addrs == NULL) {
1474                 PMD_INIT_LOG(ERR,
1475                              "Failed to allocate %u bytes needed to store "
1476                              "MAC addresses",
1477                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1478                 return -ENOMEM;
1479         }
1480
1481         /* Generate a random MAC address, if none was assigned by PF. */
1482         if (is_zero_ether_addr(perm_addr)) {
1483                 generate_random_mac_addr(perm_addr);
1484                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1485                 if (diag) {
1486                         rte_free(eth_dev->data->mac_addrs);
1487                         eth_dev->data->mac_addrs = NULL;
1488                         return diag;
1489                 }
1490                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1491                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1492                              "%02x:%02x:%02x:%02x:%02x:%02x",
1493                              perm_addr->addr_bytes[0],
1494                              perm_addr->addr_bytes[1],
1495                              perm_addr->addr_bytes[2],
1496                              perm_addr->addr_bytes[3],
1497                              perm_addr->addr_bytes[4],
1498                              perm_addr->addr_bytes[5]);
1499         }
1500
1501         /* Copy the permanent MAC address */
1502         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1503
1504         /* reset the hardware with the new settings */
1505         diag = hw->mac.ops.start_hw(hw);
1506         switch (diag) {
1507         case  0:
1508                 break;
1509
1510         default:
1511                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1512                 return -EIO;
1513         }
1514
1515         rte_intr_callback_register(intr_handle,
1516                                    ixgbevf_dev_interrupt_handler, eth_dev);
1517         rte_intr_enable(intr_handle);
1518         ixgbevf_intr_enable(hw);
1519
1520         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1521                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1522                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1523
1524         return 0;
1525 }
1526
1527 /* Virtual Function device uninit */
1528
1529 static int
1530 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1531 {
1532         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1533         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1534         struct ixgbe_hw *hw;
1535
1536         PMD_INIT_FUNC_TRACE();
1537
1538         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1539                 return -EPERM;
1540
1541         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1542
1543         if (hw->adapter_stopped == 0)
1544                 ixgbevf_dev_close(eth_dev);
1545
1546         eth_dev->dev_ops = NULL;
1547         eth_dev->rx_pkt_burst = NULL;
1548         eth_dev->tx_pkt_burst = NULL;
1549
1550         /* Disable the interrupts for VF */
1551         ixgbevf_intr_disable(hw);
1552
1553         rte_free(eth_dev->data->mac_addrs);
1554         eth_dev->data->mac_addrs = NULL;
1555
1556         rte_intr_disable(intr_handle);
1557         rte_intr_callback_unregister(intr_handle,
1558                                      ixgbevf_dev_interrupt_handler, eth_dev);
1559
1560         return 0;
1561 }
1562
1563 static struct eth_driver rte_ixgbe_pmd = {
1564         .pci_drv = {
1565                 .id_table = pci_id_ixgbe_map,
1566                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1567                         RTE_PCI_DRV_DETACHABLE,
1568                 .probe = rte_eth_dev_pci_probe,
1569                 .remove = rte_eth_dev_pci_remove,
1570         },
1571         .eth_dev_init = eth_ixgbe_dev_init,
1572         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1573         .dev_private_size = sizeof(struct ixgbe_adapter),
1574 };
1575
1576 /*
1577  * virtual function driver struct
1578  */
1579 static struct eth_driver rte_ixgbevf_pmd = {
1580         .pci_drv = {
1581                 .id_table = pci_id_ixgbevf_map,
1582                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1583                 .probe = rte_eth_dev_pci_probe,
1584                 .remove = rte_eth_dev_pci_remove,
1585         },
1586         .eth_dev_init = eth_ixgbevf_dev_init,
1587         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1588         .dev_private_size = sizeof(struct ixgbe_adapter),
1589 };
1590
1591 static int
1592 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1593 {
1594         struct ixgbe_hw *hw =
1595                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596         struct ixgbe_vfta *shadow_vfta =
1597                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1598         uint32_t vfta;
1599         uint32_t vid_idx;
1600         uint32_t vid_bit;
1601
1602         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1603         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1604         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1605         if (on)
1606                 vfta |= vid_bit;
1607         else
1608                 vfta &= ~vid_bit;
1609         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1610
1611         /* update local VFTA copy */
1612         shadow_vfta->vfta[vid_idx] = vfta;
1613
1614         return 0;
1615 }
1616
1617 static void
1618 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1619 {
1620         if (on)
1621                 ixgbe_vlan_hw_strip_enable(dev, queue);
1622         else
1623                 ixgbe_vlan_hw_strip_disable(dev, queue);
1624 }
1625
1626 static int
1627 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1628                     enum rte_vlan_type vlan_type,
1629                     uint16_t tpid)
1630 {
1631         struct ixgbe_hw *hw =
1632                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         int ret = 0;
1634         uint32_t reg;
1635         uint32_t qinq;
1636
1637         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1638         qinq &= IXGBE_DMATXCTL_GDV;
1639
1640         switch (vlan_type) {
1641         case ETH_VLAN_TYPE_INNER:
1642                 if (qinq) {
1643                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1644                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1645                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1646                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1647                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1648                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1649                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1650                 } else {
1651                         ret = -ENOTSUP;
1652                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1653                                     " by single VLAN");
1654                 }
1655                 break;
1656         case ETH_VLAN_TYPE_OUTER:
1657                 if (qinq) {
1658                         /* Only the high 16-bits is valid */
1659                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1660                                         IXGBE_EXVET_VET_EXT_SHIFT);
1661                 } else {
1662                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1663                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1664                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1665                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1666                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1667                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1668                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1669                 }
1670
1671                 break;
1672         default:
1673                 ret = -EINVAL;
1674                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1675                 break;
1676         }
1677
1678         return ret;
1679 }
1680
1681 void
1682 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1683 {
1684         struct ixgbe_hw *hw =
1685                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686         uint32_t vlnctrl;
1687
1688         PMD_INIT_FUNC_TRACE();
1689
1690         /* Filter Table Disable */
1691         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1692         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1693
1694         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1695 }
1696
1697 void
1698 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1699 {
1700         struct ixgbe_hw *hw =
1701                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1702         struct ixgbe_vfta *shadow_vfta =
1703                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1704         uint32_t vlnctrl;
1705         uint16_t i;
1706
1707         PMD_INIT_FUNC_TRACE();
1708
1709         /* Filter Table Enable */
1710         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1711         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1712         vlnctrl |= IXGBE_VLNCTRL_VFE;
1713
1714         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1715
1716         /* write whatever is in local vfta copy */
1717         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1718                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1719 }
1720
1721 static void
1722 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1723 {
1724         struct ixgbe_hwstrip *hwstrip =
1725                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1726         struct ixgbe_rx_queue *rxq;
1727
1728         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1729                 return;
1730
1731         if (on)
1732                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1733         else
1734                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1735
1736         if (queue >= dev->data->nb_rx_queues)
1737                 return;
1738
1739         rxq = dev->data->rx_queues[queue];
1740
1741         if (on)
1742                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1743         else
1744                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1745 }
1746
1747 static void
1748 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1749 {
1750         struct ixgbe_hw *hw =
1751                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752         uint32_t ctrl;
1753
1754         PMD_INIT_FUNC_TRACE();
1755
1756         if (hw->mac.type == ixgbe_mac_82598EB) {
1757                 /* No queue level support */
1758                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1759                 return;
1760         }
1761
1762         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1763         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1764         ctrl &= ~IXGBE_RXDCTL_VME;
1765         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1766
1767         /* record those setting for HW strip per queue */
1768         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1769 }
1770
1771 static void
1772 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1773 {
1774         struct ixgbe_hw *hw =
1775                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1776         uint32_t ctrl;
1777
1778         PMD_INIT_FUNC_TRACE();
1779
1780         if (hw->mac.type == ixgbe_mac_82598EB) {
1781                 /* No queue level supported */
1782                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1783                 return;
1784         }
1785
1786         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1787         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1788         ctrl |= IXGBE_RXDCTL_VME;
1789         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1790
1791         /* record those setting for HW strip per queue */
1792         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1793 }
1794
1795 void
1796 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1797 {
1798         struct ixgbe_hw *hw =
1799                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800         uint32_t ctrl;
1801         uint16_t i;
1802         struct ixgbe_rx_queue *rxq;
1803
1804         PMD_INIT_FUNC_TRACE();
1805
1806         if (hw->mac.type == ixgbe_mac_82598EB) {
1807                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1808                 ctrl &= ~IXGBE_VLNCTRL_VME;
1809                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1810         } else {
1811                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1812                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1813                         rxq = dev->data->rx_queues[i];
1814                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1815                         ctrl &= ~IXGBE_RXDCTL_VME;
1816                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1817
1818                         /* record those setting for HW strip per queue */
1819                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1820                 }
1821         }
1822 }
1823
1824 void
1825 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1826 {
1827         struct ixgbe_hw *hw =
1828                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829         uint32_t ctrl;
1830         uint16_t i;
1831         struct ixgbe_rx_queue *rxq;
1832
1833         PMD_INIT_FUNC_TRACE();
1834
1835         if (hw->mac.type == ixgbe_mac_82598EB) {
1836                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1837                 ctrl |= IXGBE_VLNCTRL_VME;
1838                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1839         } else {
1840                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1841                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1842                         rxq = dev->data->rx_queues[i];
1843                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1844                         ctrl |= IXGBE_RXDCTL_VME;
1845                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1846
1847                         /* record those setting for HW strip per queue */
1848                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1849                 }
1850         }
1851 }
1852
1853 static void
1854 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1855 {
1856         struct ixgbe_hw *hw =
1857                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858         uint32_t ctrl;
1859
1860         PMD_INIT_FUNC_TRACE();
1861
1862         /* DMATXCTRL: Geric Double VLAN Disable */
1863         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1864         ctrl &= ~IXGBE_DMATXCTL_GDV;
1865         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1866
1867         /* CTRL_EXT: Global Double VLAN Disable */
1868         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1869         ctrl &= ~IXGBE_EXTENDED_VLAN;
1870         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1871
1872 }
1873
1874 static void
1875 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1876 {
1877         struct ixgbe_hw *hw =
1878                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         uint32_t ctrl;
1880
1881         PMD_INIT_FUNC_TRACE();
1882
1883         /* DMATXCTRL: Geric Double VLAN Enable */
1884         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1885         ctrl |= IXGBE_DMATXCTL_GDV;
1886         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1887
1888         /* CTRL_EXT: Global Double VLAN Enable */
1889         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1890         ctrl |= IXGBE_EXTENDED_VLAN;
1891         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1892
1893         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1894         if (hw->mac.type == ixgbe_mac_X550 ||
1895             hw->mac.type == ixgbe_mac_X550EM_x ||
1896             hw->mac.type == ixgbe_mac_X550EM_a) {
1897                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1898                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1899                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1900         }
1901
1902         /*
1903          * VET EXT field in the EXVET register = 0x8100 by default
1904          * So no need to change. Same to VT field of DMATXCTL register
1905          */
1906 }
1907
1908 static void
1909 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1910 {
1911         if (mask & ETH_VLAN_STRIP_MASK) {
1912                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1913                         ixgbe_vlan_hw_strip_enable_all(dev);
1914                 else
1915                         ixgbe_vlan_hw_strip_disable_all(dev);
1916         }
1917
1918         if (mask & ETH_VLAN_FILTER_MASK) {
1919                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1920                         ixgbe_vlan_hw_filter_enable(dev);
1921                 else
1922                         ixgbe_vlan_hw_filter_disable(dev);
1923         }
1924
1925         if (mask & ETH_VLAN_EXTEND_MASK) {
1926                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1927                         ixgbe_vlan_hw_extend_enable(dev);
1928                 else
1929                         ixgbe_vlan_hw_extend_disable(dev);
1930         }
1931 }
1932
1933 static void
1934 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1935 {
1936         struct ixgbe_hw *hw =
1937                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1939         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1940
1941         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1942         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1943 }
1944
1945 static int
1946 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1947 {
1948         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
1949
1950         switch (nb_rx_q) {
1951         case 1:
1952         case 2:
1953                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1954                 break;
1955         case 4:
1956                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1957                 break;
1958         default:
1959                 return -EINVAL;
1960         }
1961
1962         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1963         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
1964
1965         return 0;
1966 }
1967
1968 static int
1969 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1970 {
1971         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1974         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1975
1976         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1977                 /* check multi-queue mode */
1978                 switch (dev_conf->rxmode.mq_mode) {
1979                 case ETH_MQ_RX_VMDQ_DCB:
1980                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1981                         break;
1982                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1983                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1984                         PMD_INIT_LOG(ERR, "SRIOV active,"
1985                                         " unsupported mq_mode rx %d.",
1986                                         dev_conf->rxmode.mq_mode);
1987                         return -EINVAL;
1988                 case ETH_MQ_RX_RSS:
1989                 case ETH_MQ_RX_VMDQ_RSS:
1990                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1991                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1992                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1993                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1994                                                 " invalid queue number"
1995                                                 " for VMDQ RSS, allowed"
1996                                                 " value are 1, 2 or 4.");
1997                                         return -EINVAL;
1998                                 }
1999                         break;
2000                 case ETH_MQ_RX_VMDQ_ONLY:
2001                 case ETH_MQ_RX_NONE:
2002                         /* if nothing mq mode configure, use default scheme */
2003                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2004                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2005                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2006                         break;
2007                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2008                         /* SRIOV only works in VMDq enable mode */
2009                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2010                                         " wrong mq_mode rx %d.",
2011                                         dev_conf->rxmode.mq_mode);
2012                         return -EINVAL;
2013                 }
2014
2015                 switch (dev_conf->txmode.mq_mode) {
2016                 case ETH_MQ_TX_VMDQ_DCB:
2017                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2018                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2019                         break;
2020                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2021                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2022                         break;
2023                 }
2024
2025                 /* check valid queue number */
2026                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2027                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2028                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2029                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2030                                         " must be less than or equal to %d.",
2031                                         nb_rx_q, nb_tx_q,
2032                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2033                         return -EINVAL;
2034                 }
2035         } else {
2036                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2037                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2038                                           " not supported.");
2039                         return -EINVAL;
2040                 }
2041                 /* check configuration for vmdb+dcb mode */
2042                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2043                         const struct rte_eth_vmdq_dcb_conf *conf;
2044
2045                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2046                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2047                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2048                                 return -EINVAL;
2049                         }
2050                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2051                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2052                                conf->nb_queue_pools == ETH_32_POOLS)) {
2053                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2054                                                 " nb_queue_pools must be %d or %d.",
2055                                                 ETH_16_POOLS, ETH_32_POOLS);
2056                                 return -EINVAL;
2057                         }
2058                 }
2059                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2060                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2061
2062                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2063                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2064                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2065                                 return -EINVAL;
2066                         }
2067                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2068                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2069                                conf->nb_queue_pools == ETH_32_POOLS)) {
2070                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2071                                                 " nb_queue_pools != %d and"
2072                                                 " nb_queue_pools != %d.",
2073                                                 ETH_16_POOLS, ETH_32_POOLS);
2074                                 return -EINVAL;
2075                         }
2076                 }
2077
2078                 /* For DCB mode check our configuration before we go further */
2079                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2080                         const struct rte_eth_dcb_rx_conf *conf;
2081
2082                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2083                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2084                                                  IXGBE_DCB_NB_QUEUES);
2085                                 return -EINVAL;
2086                         }
2087                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2088                         if (!(conf->nb_tcs == ETH_4_TCS ||
2089                                conf->nb_tcs == ETH_8_TCS)) {
2090                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2091                                                 " and nb_tcs != %d.",
2092                                                 ETH_4_TCS, ETH_8_TCS);
2093                                 return -EINVAL;
2094                         }
2095                 }
2096
2097                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2098                         const struct rte_eth_dcb_tx_conf *conf;
2099
2100                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2101                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2102                                                  IXGBE_DCB_NB_QUEUES);
2103                                 return -EINVAL;
2104                         }
2105                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2106                         if (!(conf->nb_tcs == ETH_4_TCS ||
2107                                conf->nb_tcs == ETH_8_TCS)) {
2108                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2109                                                 " and nb_tcs != %d.",
2110                                                 ETH_4_TCS, ETH_8_TCS);
2111                                 return -EINVAL;
2112                         }
2113                 }
2114
2115                 /*
2116                  * When DCB/VT is off, maximum number of queues changes,
2117                  * except for 82598EB, which remains constant.
2118                  */
2119                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2120                                 hw->mac.type != ixgbe_mac_82598EB) {
2121                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2122                                 PMD_INIT_LOG(ERR,
2123                                              "Neither VT nor DCB are enabled, "
2124                                              "nb_tx_q > %d.",
2125                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2126                                 return -EINVAL;
2127                         }
2128                 }
2129         }
2130         return 0;
2131 }
2132
2133 static int
2134 ixgbe_dev_configure(struct rte_eth_dev *dev)
2135 {
2136         struct ixgbe_interrupt *intr =
2137                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2138         struct ixgbe_adapter *adapter =
2139                 (struct ixgbe_adapter *)dev->data->dev_private;
2140         int ret;
2141
2142         PMD_INIT_FUNC_TRACE();
2143         /* multipe queue mode checking */
2144         ret  = ixgbe_check_mq_mode(dev);
2145         if (ret != 0) {
2146                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2147                             ret);
2148                 return ret;
2149         }
2150
2151         /* set flag to update link status after init */
2152         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2153
2154         /*
2155          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2156          * allocation or vector Rx preconditions we will reset it.
2157          */
2158         adapter->rx_bulk_alloc_allowed = true;
2159         adapter->rx_vec_allowed = true;
2160
2161         return 0;
2162 }
2163
2164 static void
2165 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2166 {
2167         struct ixgbe_hw *hw =
2168                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169         struct ixgbe_interrupt *intr =
2170                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2171         uint32_t gpie;
2172
2173         /* only set up it on X550EM_X */
2174         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2175                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2176                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2177                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2178                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2179                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2180         }
2181 }
2182
2183 /*
2184  * Configure device link speed and setup link.
2185  * It returns 0 on success.
2186  */
2187 static int
2188 ixgbe_dev_start(struct rte_eth_dev *dev)
2189 {
2190         struct ixgbe_hw *hw =
2191                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192         struct ixgbe_vf_info *vfinfo =
2193                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2194         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2195         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2196         uint32_t intr_vector = 0;
2197         int err, link_up = 0, negotiate = 0;
2198         uint32_t speed = 0;
2199         int mask = 0;
2200         int status;
2201         uint16_t vf, idx;
2202         uint32_t *link_speeds;
2203
2204         PMD_INIT_FUNC_TRACE();
2205
2206         /* IXGBE devices don't support:
2207         *    - half duplex (checked afterwards for valid speeds)
2208         *    - fixed speed: TODO implement
2209         */
2210         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2211                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2212                              dev->data->port_id);
2213                 return -EINVAL;
2214         }
2215
2216         /* disable uio/vfio intr/eventfd mapping */
2217         rte_intr_disable(intr_handle);
2218
2219         /* stop adapter */
2220         hw->adapter_stopped = 0;
2221         ixgbe_stop_adapter(hw);
2222
2223         /* reinitialize adapter
2224          * this calls reset and start
2225          */
2226         status = ixgbe_pf_reset_hw(hw);
2227         if (status != 0)
2228                 return -1;
2229         hw->mac.ops.start_hw(hw);
2230         hw->mac.get_link_status = true;
2231
2232         /* configure PF module if SRIOV enabled */
2233         ixgbe_pf_host_configure(dev);
2234
2235         ixgbe_dev_phy_intr_setup(dev);
2236
2237         /* check and configure queue intr-vector mapping */
2238         if ((rte_intr_cap_multiple(intr_handle) ||
2239              !RTE_ETH_DEV_SRIOV(dev).active) &&
2240             dev->data->dev_conf.intr_conf.rxq != 0) {
2241                 intr_vector = dev->data->nb_rx_queues;
2242                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2243                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2244                                         IXGBE_MAX_INTR_QUEUE_NUM);
2245                         return -ENOTSUP;
2246                 }
2247                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2248                         return -1;
2249         }
2250
2251         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2252                 intr_handle->intr_vec =
2253                         rte_zmalloc("intr_vec",
2254                                     dev->data->nb_rx_queues * sizeof(int), 0);
2255                 if (intr_handle->intr_vec == NULL) {
2256                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2257                                      " intr_vec\n", dev->data->nb_rx_queues);
2258                         return -ENOMEM;
2259                 }
2260         }
2261
2262         /* confiugre msix for sleep until rx interrupt */
2263         ixgbe_configure_msix(dev);
2264
2265         /* initialize transmission unit */
2266         ixgbe_dev_tx_init(dev);
2267
2268         /* This can fail when allocating mbufs for descriptor rings */
2269         err = ixgbe_dev_rx_init(dev);
2270         if (err) {
2271                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2272                 goto error;
2273         }
2274
2275     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2276                 ETH_VLAN_EXTEND_MASK;
2277         ixgbe_vlan_offload_set(dev, mask);
2278
2279         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2280                 /* Enable vlan filtering for VMDq */
2281                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2282         }
2283
2284         /* Configure DCB hw */
2285         ixgbe_configure_dcb(dev);
2286
2287         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2288                 err = ixgbe_fdir_configure(dev);
2289                 if (err)
2290                         goto error;
2291         }
2292
2293         /* Restore vf rate limit */
2294         if (vfinfo != NULL) {
2295                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2296                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2297                                 if (vfinfo[vf].tx_rate[idx] != 0)
2298                                         ixgbe_set_vf_rate_limit(dev, vf,
2299                                                 vfinfo[vf].tx_rate[idx],
2300                                                 1 << idx);
2301         }
2302
2303         ixgbe_restore_statistics_mapping(dev);
2304
2305         err = ixgbe_dev_rxtx_start(dev);
2306         if (err < 0) {
2307                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2308                 goto error;
2309         }
2310
2311         /* Skip link setup if loopback mode is enabled for 82599. */
2312         if (hw->mac.type == ixgbe_mac_82599EB &&
2313                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2314                 goto skip_link_setup;
2315
2316         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2317                 err = hw->mac.ops.setup_sfp(hw);
2318                 if (err)
2319                         goto error;
2320         }
2321
2322         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2323                 /* Turn on the copper */
2324                 ixgbe_set_phy_power(hw, true);
2325         } else {
2326                 /* Turn on the laser */
2327                 ixgbe_enable_tx_laser(hw);
2328         }
2329
2330         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2331         if (err)
2332                 goto error;
2333         dev->data->dev_link.link_status = link_up;
2334
2335         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2336         if (err)
2337                 goto error;
2338
2339         link_speeds = &dev->data->dev_conf.link_speeds;
2340         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2341                         ETH_LINK_SPEED_10G)) {
2342                 PMD_INIT_LOG(ERR, "Invalid link setting");
2343                 goto error;
2344         }
2345
2346         speed = 0x0;
2347         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2348                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2349                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2350                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2351         } else {
2352                 if (*link_speeds & ETH_LINK_SPEED_10G)
2353                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2354                 if (*link_speeds & ETH_LINK_SPEED_1G)
2355                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2356                 if (*link_speeds & ETH_LINK_SPEED_100M)
2357                         speed |= IXGBE_LINK_SPEED_100_FULL;
2358         }
2359
2360         err = ixgbe_setup_link(hw, speed, link_up);
2361         if (err)
2362                 goto error;
2363
2364 skip_link_setup:
2365
2366         if (rte_intr_allow_others(intr_handle)) {
2367                 /* check if lsc interrupt is enabled */
2368                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2369                         ixgbe_dev_lsc_interrupt_setup(dev);
2370         } else {
2371                 rte_intr_callback_unregister(intr_handle,
2372                                              ixgbe_dev_interrupt_handler, dev);
2373                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2374                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2375                                      " no intr multiplex\n");
2376         }
2377
2378         /* check if rxq interrupt is enabled */
2379         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2380             rte_intr_dp_is_en(intr_handle))
2381                 ixgbe_dev_rxq_interrupt_setup(dev);
2382
2383         /* enable uio/vfio intr/eventfd mapping */
2384         rte_intr_enable(intr_handle);
2385
2386         /* resume enabled intr since hw reset */
2387         ixgbe_enable_intr(dev);
2388
2389         return 0;
2390
2391 error:
2392         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2393         ixgbe_dev_clear_queues(dev);
2394         return -EIO;
2395 }
2396
2397 /*
2398  * Stop device: disable rx and tx functions to allow for reconfiguring.
2399  */
2400 static void
2401 ixgbe_dev_stop(struct rte_eth_dev *dev)
2402 {
2403         struct rte_eth_link link;
2404         struct ixgbe_hw *hw =
2405                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406         struct ixgbe_vf_info *vfinfo =
2407                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2408         struct ixgbe_filter_info *filter_info =
2409                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2410         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2411         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2412         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2413         int vf;
2414
2415         PMD_INIT_FUNC_TRACE();
2416
2417         /* disable interrupts */
2418         ixgbe_disable_intr(hw);
2419
2420         /* reset the NIC */
2421         ixgbe_pf_reset_hw(hw);
2422         hw->adapter_stopped = 0;
2423
2424         /* stop adapter */
2425         ixgbe_stop_adapter(hw);
2426
2427         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2428                 vfinfo[vf].clear_to_send = false;
2429
2430         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2431                 /* Turn off the copper */
2432                 ixgbe_set_phy_power(hw, false);
2433         } else {
2434                 /* Turn off the laser */
2435                 ixgbe_disable_tx_laser(hw);
2436         }
2437
2438         ixgbe_dev_clear_queues(dev);
2439
2440         /* Clear stored conf */
2441         dev->data->scattered_rx = 0;
2442         dev->data->lro = 0;
2443
2444         /* Clear recorded link status */
2445         memset(&link, 0, sizeof(link));
2446         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2447
2448         /* Remove all ntuple filters of the device */
2449         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2450              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2451                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2452                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2453                              p_5tuple, entries);
2454                 rte_free(p_5tuple);
2455         }
2456         memset(filter_info->fivetuple_mask, 0,
2457                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2458
2459         if (!rte_intr_allow_others(intr_handle))
2460                 /* resume to the default handler */
2461                 rte_intr_callback_register(intr_handle,
2462                                            ixgbe_dev_interrupt_handler,
2463                                            (void *)dev);
2464
2465         /* Clean datapath event and queue/vec mapping */
2466         rte_intr_efd_disable(intr_handle);
2467         if (intr_handle->intr_vec != NULL) {
2468                 rte_free(intr_handle->intr_vec);
2469                 intr_handle->intr_vec = NULL;
2470         }
2471 }
2472
2473 /*
2474  * Set device link up: enable tx.
2475  */
2476 static int
2477 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2478 {
2479         struct ixgbe_hw *hw =
2480                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481         if (hw->mac.type == ixgbe_mac_82599EB) {
2482 #ifdef RTE_NIC_BYPASS
2483                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2484                         /* Not suported in bypass mode */
2485                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2486                                      "by device id 0x%x", hw->device_id);
2487                         return -ENOTSUP;
2488                 }
2489 #endif
2490         }
2491
2492         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2493                 /* Turn on the copper */
2494                 ixgbe_set_phy_power(hw, true);
2495         } else {
2496                 /* Turn on the laser */
2497                 ixgbe_enable_tx_laser(hw);
2498         }
2499
2500         return 0;
2501 }
2502
2503 /*
2504  * Set device link down: disable tx.
2505  */
2506 static int
2507 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2508 {
2509         struct ixgbe_hw *hw =
2510                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511         if (hw->mac.type == ixgbe_mac_82599EB) {
2512 #ifdef RTE_NIC_BYPASS
2513                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2514                         /* Not suported in bypass mode */
2515                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2516                                      "by device id 0x%x", hw->device_id);
2517                         return -ENOTSUP;
2518                 }
2519 #endif
2520         }
2521
2522         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2523                 /* Turn off the copper */
2524                 ixgbe_set_phy_power(hw, false);
2525         } else {
2526                 /* Turn off the laser */
2527                 ixgbe_disable_tx_laser(hw);
2528         }
2529
2530         return 0;
2531 }
2532
2533 /*
2534  * Reest and stop device.
2535  */
2536 static void
2537 ixgbe_dev_close(struct rte_eth_dev *dev)
2538 {
2539         struct ixgbe_hw *hw =
2540                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541
2542         PMD_INIT_FUNC_TRACE();
2543
2544         ixgbe_pf_reset_hw(hw);
2545
2546         ixgbe_dev_stop(dev);
2547         hw->adapter_stopped = 1;
2548
2549         ixgbe_dev_free_queues(dev);
2550
2551         ixgbe_disable_pcie_master(hw);
2552
2553         /* reprogram the RAR[0] in case user changed it. */
2554         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2555 }
2556
2557 static void
2558 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2559                            struct ixgbe_hw_stats *hw_stats,
2560                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2561                            uint64_t *total_qprc, uint64_t *total_qprdc)
2562 {
2563         uint32_t bprc, lxon, lxoff, total;
2564         uint32_t delta_gprc = 0;
2565         unsigned i;
2566         /* Workaround for RX byte count not including CRC bytes when CRC
2567 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2568          * is disabled.
2569 +        */
2570         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2571                         IXGBE_HLREG0_RXCRCSTRP);
2572
2573         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2574         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2575         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2576         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2577
2578         for (i = 0; i < 8; i++) {
2579                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2580
2581                 /* global total per queue */
2582                 hw_stats->mpc[i] += mp;
2583                 /* Running comprehensive total for stats display */
2584                 *total_missed_rx += hw_stats->mpc[i];
2585                 if (hw->mac.type == ixgbe_mac_82598EB) {
2586                         hw_stats->rnbc[i] +=
2587                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2588                         hw_stats->pxonrxc[i] +=
2589                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2590                         hw_stats->pxoffrxc[i] +=
2591                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2592                 } else {
2593                         hw_stats->pxonrxc[i] +=
2594                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2595                         hw_stats->pxoffrxc[i] +=
2596                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2597                         hw_stats->pxon2offc[i] +=
2598                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2599                 }
2600                 hw_stats->pxontxc[i] +=
2601                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2602                 hw_stats->pxofftxc[i] +=
2603                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2604         }
2605         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2606                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2607                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2608                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2609
2610                 delta_gprc += delta_qprc;
2611
2612                 hw_stats->qprc[i] += delta_qprc;
2613                 hw_stats->qptc[i] += delta_qptc;
2614
2615                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2616                 hw_stats->qbrc[i] +=
2617                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2618                 if (crc_strip == 0)
2619                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2620
2621                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2622                 hw_stats->qbtc[i] +=
2623                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2624
2625                 hw_stats->qprdc[i] += delta_qprdc;
2626                 *total_qprdc += hw_stats->qprdc[i];
2627
2628                 *total_qprc += hw_stats->qprc[i];
2629                 *total_qbrc += hw_stats->qbrc[i];
2630         }
2631         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2632         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2633         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2634
2635         /*
2636          * An errata states that gprc actually counts good + missed packets:
2637          * Workaround to set gprc to summated queue packet receives
2638          */
2639         hw_stats->gprc = *total_qprc;
2640
2641         if (hw->mac.type != ixgbe_mac_82598EB) {
2642                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2643                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2644                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2645                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2646                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2647                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2648                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2649                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2650         } else {
2651                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2652                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2653                 /* 82598 only has a counter in the high register */
2654                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2655                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2656                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2657         }
2658         uint64_t old_tpr = hw_stats->tpr;
2659
2660         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2661         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2662
2663         if (crc_strip == 0)
2664                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2665
2666         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2667         hw_stats->gptc += delta_gptc;
2668         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2669         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2670
2671         /*
2672          * Workaround: mprc hardware is incorrectly counting
2673          * broadcasts, so for now we subtract those.
2674          */
2675         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2676         hw_stats->bprc += bprc;
2677         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2678         if (hw->mac.type == ixgbe_mac_82598EB)
2679                 hw_stats->mprc -= bprc;
2680
2681         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2682         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2683         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2684         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2685         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2686         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2687
2688         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2689         hw_stats->lxontxc += lxon;
2690         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2691         hw_stats->lxofftxc += lxoff;
2692         total = lxon + lxoff;
2693
2694         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2695         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2696         hw_stats->gptc -= total;
2697         hw_stats->mptc -= total;
2698         hw_stats->ptc64 -= total;
2699         hw_stats->gotc -= total * ETHER_MIN_LEN;
2700
2701         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2702         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2703         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2704         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2705         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2706         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2707         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2708         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2709         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2710         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2711         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2712         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2713         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2714         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2715         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2716         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2717         /* Only read FCOE on 82599 */
2718         if (hw->mac.type != ixgbe_mac_82598EB) {
2719                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2720                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2721                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2722                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2723                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2724         }
2725
2726         /* Flow Director Stats registers */
2727         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2728         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2729 }
2730
2731 /*
2732  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2733  */
2734 static void
2735 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2736 {
2737         struct ixgbe_hw *hw =
2738                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2739         struct ixgbe_hw_stats *hw_stats =
2740                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2741         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2742         unsigned i;
2743
2744         total_missed_rx = 0;
2745         total_qbrc = 0;
2746         total_qprc = 0;
2747         total_qprdc = 0;
2748
2749         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2750                         &total_qprc, &total_qprdc);
2751
2752         if (stats == NULL)
2753                 return;
2754
2755         /* Fill out the rte_eth_stats statistics structure */
2756         stats->ipackets = total_qprc;
2757         stats->ibytes = total_qbrc;
2758         stats->opackets = hw_stats->gptc;
2759         stats->obytes = hw_stats->gotc;
2760
2761         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2762                 stats->q_ipackets[i] = hw_stats->qprc[i];
2763                 stats->q_opackets[i] = hw_stats->qptc[i];
2764                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2765                 stats->q_obytes[i] = hw_stats->qbtc[i];
2766                 stats->q_errors[i] = hw_stats->qprdc[i];
2767         }
2768
2769         /* Rx Errors */
2770         stats->imissed  = total_missed_rx;
2771         stats->ierrors  = hw_stats->crcerrs +
2772                           hw_stats->mspdc +
2773                           hw_stats->rlec +
2774                           hw_stats->ruc +
2775                           hw_stats->roc +
2776                           hw_stats->illerrc +
2777                           hw_stats->errbc +
2778                           hw_stats->rfc +
2779                           hw_stats->fccrc +
2780                           hw_stats->fclast;
2781
2782         /* Tx Errors */
2783         stats->oerrors  = 0;
2784 }
2785
2786 static void
2787 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2788 {
2789         struct ixgbe_hw_stats *stats =
2790                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2791
2792         /* HW registers are cleared on read */
2793         ixgbe_dev_stats_get(dev, NULL);
2794
2795         /* Reset software totals */
2796         memset(stats, 0, sizeof(*stats));
2797 }
2798
2799 /* This function calculates the number of xstats based on the current config */
2800 static unsigned
2801 ixgbe_xstats_calc_num(void) {
2802         return IXGBE_NB_HW_STATS +
2803                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2804                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2805 }
2806
2807 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2808         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2809 {
2810         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2811         unsigned stat, i, count;
2812
2813         if (xstats_names != NULL) {
2814                 count = 0;
2815
2816                 /* Note: limit >= cnt_stats checked upstream
2817                  * in rte_eth_xstats_names()
2818                  */
2819
2820                 /* Extended stats from ixgbe_hw_stats */
2821                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2822                         snprintf(xstats_names[count].name,
2823                                 sizeof(xstats_names[count].name),
2824                                 "%s",
2825                                 rte_ixgbe_stats_strings[i].name);
2826                         count++;
2827                 }
2828
2829                 /* RX Priority Stats */
2830                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2831                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2832                                 snprintf(xstats_names[count].name,
2833                                         sizeof(xstats_names[count].name),
2834                                         "rx_priority%u_%s", i,
2835                                         rte_ixgbe_rxq_strings[stat].name);
2836                                 count++;
2837                         }
2838                 }
2839
2840                 /* TX Priority Stats */
2841                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2842                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2843                                 snprintf(xstats_names[count].name,
2844                                         sizeof(xstats_names[count].name),
2845                                         "tx_priority%u_%s", i,
2846                                         rte_ixgbe_txq_strings[stat].name);
2847                                 count++;
2848                         }
2849                 }
2850         }
2851         return cnt_stats;
2852 }
2853
2854 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2855         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2856 {
2857         unsigned i;
2858
2859         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2860                 return -ENOMEM;
2861
2862         if (xstats_names != NULL)
2863                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2864                         snprintf(xstats_names[i].name,
2865                                 sizeof(xstats_names[i].name),
2866                                 "%s", rte_ixgbevf_stats_strings[i].name);
2867         return IXGBEVF_NB_XSTATS;
2868 }
2869
2870 static int
2871 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2872                                          unsigned n)
2873 {
2874         struct ixgbe_hw *hw =
2875                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         struct ixgbe_hw_stats *hw_stats =
2877                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2878         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2879         unsigned i, stat, count = 0;
2880
2881         count = ixgbe_xstats_calc_num();
2882
2883         if (n < count)
2884                 return count;
2885
2886         total_missed_rx = 0;
2887         total_qbrc = 0;
2888         total_qprc = 0;
2889         total_qprdc = 0;
2890
2891         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2892                                    &total_qprc, &total_qprdc);
2893
2894         /* If this is a reset xstats is NULL, and we have cleared the
2895          * registers by reading them.
2896          */
2897         if (!xstats)
2898                 return 0;
2899
2900         /* Extended stats from ixgbe_hw_stats */
2901         count = 0;
2902         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2903                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2904                                 rte_ixgbe_stats_strings[i].offset);
2905                 count++;
2906         }
2907
2908         /* RX Priority Stats */
2909         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2910                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2911                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2912                                         rte_ixgbe_rxq_strings[stat].offset +
2913                                         (sizeof(uint64_t) * i));
2914                         count++;
2915                 }
2916         }
2917
2918         /* TX Priority Stats */
2919         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2920                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2921                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2922                                         rte_ixgbe_txq_strings[stat].offset +
2923                                         (sizeof(uint64_t) * i));
2924                         count++;
2925                 }
2926         }
2927         return count;
2928 }
2929
2930 static void
2931 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2932 {
2933         struct ixgbe_hw_stats *stats =
2934                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2935
2936         unsigned count = ixgbe_xstats_calc_num();
2937
2938         /* HW registers are cleared on read */
2939         ixgbe_dev_xstats_get(dev, NULL, count);
2940
2941         /* Reset software totals */
2942         memset(stats, 0, sizeof(*stats));
2943 }
2944
2945 static void
2946 ixgbevf_update_stats(struct rte_eth_dev *dev)
2947 {
2948         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2949         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2950                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2951
2952         /* Good Rx packet, include VF loopback */
2953         UPDATE_VF_STAT(IXGBE_VFGPRC,
2954             hw_stats->last_vfgprc, hw_stats->vfgprc);
2955
2956         /* Good Rx octets, include VF loopback */
2957         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2958             hw_stats->last_vfgorc, hw_stats->vfgorc);
2959
2960         /* Good Tx packet, include VF loopback */
2961         UPDATE_VF_STAT(IXGBE_VFGPTC,
2962             hw_stats->last_vfgptc, hw_stats->vfgptc);
2963
2964         /* Good Tx octets, include VF loopback */
2965         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2966             hw_stats->last_vfgotc, hw_stats->vfgotc);
2967
2968         /* Rx Multicst Packet */
2969         UPDATE_VF_STAT(IXGBE_VFMPRC,
2970             hw_stats->last_vfmprc, hw_stats->vfmprc);
2971 }
2972
2973 static int
2974 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2975                        unsigned n)
2976 {
2977         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2978                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2979         unsigned i;
2980
2981         if (n < IXGBEVF_NB_XSTATS)
2982                 return IXGBEVF_NB_XSTATS;
2983
2984         ixgbevf_update_stats(dev);
2985
2986         if (!xstats)
2987                 return 0;
2988
2989         /* Extended stats */
2990         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2991                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2992                         rte_ixgbevf_stats_strings[i].offset);
2993         }
2994
2995         return IXGBEVF_NB_XSTATS;
2996 }
2997
2998 static void
2999 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3000 {
3001         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3002                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3003
3004         ixgbevf_update_stats(dev);
3005
3006         if (stats == NULL)
3007                 return;
3008
3009         stats->ipackets = hw_stats->vfgprc;
3010         stats->ibytes = hw_stats->vfgorc;
3011         stats->opackets = hw_stats->vfgptc;
3012         stats->obytes = hw_stats->vfgotc;
3013 }
3014
3015 static void
3016 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3017 {
3018         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3019                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3020
3021         /* Sync HW register to the last stats */
3022         ixgbevf_dev_stats_get(dev, NULL);
3023
3024         /* reset HW current stats*/
3025         hw_stats->vfgprc = 0;
3026         hw_stats->vfgorc = 0;
3027         hw_stats->vfgptc = 0;
3028         hw_stats->vfgotc = 0;
3029 }
3030
3031 static void
3032 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3033 {
3034         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3036         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3037
3038         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3039         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3040         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3041                 /*
3042                  * When DCB/VT is off, maximum number of queues changes,
3043                  * except for 82598EB, which remains constant.
3044                  */
3045                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3046                                 hw->mac.type != ixgbe_mac_82598EB)
3047                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3048         }
3049         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3050         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3051         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3052         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3053         dev_info->max_vfs = pci_dev->max_vfs;
3054         if (hw->mac.type == ixgbe_mac_82598EB)
3055                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3056         else
3057                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3058         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3059         dev_info->rx_offload_capa =
3060                 DEV_RX_OFFLOAD_VLAN_STRIP |
3061                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3062                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3063                 DEV_RX_OFFLOAD_TCP_CKSUM;
3064
3065         /*
3066          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3067          * mode.
3068          */
3069         if ((hw->mac.type == ixgbe_mac_82599EB ||
3070              hw->mac.type == ixgbe_mac_X540) &&
3071             !RTE_ETH_DEV_SRIOV(dev).active)
3072                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3073
3074         if (hw->mac.type == ixgbe_mac_X550 ||
3075             hw->mac.type == ixgbe_mac_X550EM_x ||
3076             hw->mac.type == ixgbe_mac_X550EM_a)
3077                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3078
3079         dev_info->tx_offload_capa =
3080                 DEV_TX_OFFLOAD_VLAN_INSERT |
3081                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3082                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3083                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3084                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3085                 DEV_TX_OFFLOAD_TCP_TSO;
3086
3087         if (hw->mac.type == ixgbe_mac_X550 ||
3088             hw->mac.type == ixgbe_mac_X550EM_x ||
3089             hw->mac.type == ixgbe_mac_X550EM_a)
3090                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3091
3092         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3093                 .rx_thresh = {
3094                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3095                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3096                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3097                 },
3098                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3099                 .rx_drop_en = 0,
3100         };
3101
3102         dev_info->default_txconf = (struct rte_eth_txconf) {
3103                 .tx_thresh = {
3104                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3105                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3106                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3107                 },
3108                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3109                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3110                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3111                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3112         };
3113
3114         dev_info->rx_desc_lim = rx_desc_lim;
3115         dev_info->tx_desc_lim = tx_desc_lim;
3116
3117         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3118         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3119         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3120
3121         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3122         if (hw->mac.type == ixgbe_mac_X540 ||
3123             hw->mac.type == ixgbe_mac_X540_vf ||
3124             hw->mac.type == ixgbe_mac_X550 ||
3125             hw->mac.type == ixgbe_mac_X550_vf) {
3126                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3127         }
3128 }
3129
3130 static const uint32_t *
3131 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3132 {
3133         static const uint32_t ptypes[] = {
3134                 /* For non-vec functions,
3135                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3136                  * for vec functions,
3137                  * refers to _recv_raw_pkts_vec().
3138                  */
3139                 RTE_PTYPE_L2_ETHER,
3140                 RTE_PTYPE_L3_IPV4,
3141                 RTE_PTYPE_L3_IPV4_EXT,
3142                 RTE_PTYPE_L3_IPV6,
3143                 RTE_PTYPE_L3_IPV6_EXT,
3144                 RTE_PTYPE_L4_SCTP,
3145                 RTE_PTYPE_L4_TCP,
3146                 RTE_PTYPE_L4_UDP,
3147                 RTE_PTYPE_TUNNEL_IP,
3148                 RTE_PTYPE_INNER_L3_IPV6,
3149                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3150                 RTE_PTYPE_INNER_L4_TCP,
3151                 RTE_PTYPE_INNER_L4_UDP,
3152                 RTE_PTYPE_UNKNOWN
3153         };
3154
3155         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3156             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3157             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3158             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3159                 return ptypes;
3160         return NULL;
3161 }
3162
3163 static void
3164 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3165                      struct rte_eth_dev_info *dev_info)
3166 {
3167         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3169
3170         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3171         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3172         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3173         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3174         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3175         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3176         dev_info->max_vfs = pci_dev->max_vfs;
3177         if (hw->mac.type == ixgbe_mac_82598EB)
3178                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3179         else
3180                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3181         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3182                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3183                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3184                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3185         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3186                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3187                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3188                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3189                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3190                                 DEV_TX_OFFLOAD_TCP_TSO;
3191
3192         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3193                 .rx_thresh = {
3194                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3195                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3196                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3197                 },
3198                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3199                 .rx_drop_en = 0,
3200         };
3201
3202         dev_info->default_txconf = (struct rte_eth_txconf) {
3203                 .tx_thresh = {
3204                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3205                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3206                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3207                 },
3208                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3209                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3210                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3211                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3212         };
3213
3214         dev_info->rx_desc_lim = rx_desc_lim;
3215         dev_info->tx_desc_lim = tx_desc_lim;
3216 }
3217
3218 /* return 0 means link status changed, -1 means not changed */
3219 static int
3220 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3221 {
3222         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3223         struct rte_eth_link link, old;
3224         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3225         int link_up;
3226         int diag;
3227
3228         link.link_status = ETH_LINK_DOWN;
3229         link.link_speed = 0;
3230         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3231         memset(&old, 0, sizeof(old));
3232         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3233
3234         hw->mac.get_link_status = true;
3235
3236         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3237         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3238                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3239         else
3240                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3241
3242         if (diag != 0) {
3243                 link.link_speed = ETH_SPEED_NUM_100M;
3244                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3245                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3246                 if (link.link_status == old.link_status)
3247                         return -1;
3248                 return 0;
3249         }
3250
3251         if (link_up == 0) {
3252                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3253                 if (link.link_status == old.link_status)
3254                         return -1;
3255                 return 0;
3256         }
3257         link.link_status = ETH_LINK_UP;
3258         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3259
3260         switch (link_speed) {
3261         default:
3262         case IXGBE_LINK_SPEED_UNKNOWN:
3263                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3264                 link.link_speed = ETH_SPEED_NUM_100M;
3265                 break;
3266
3267         case IXGBE_LINK_SPEED_100_FULL:
3268                 link.link_speed = ETH_SPEED_NUM_100M;
3269                 break;
3270
3271         case IXGBE_LINK_SPEED_1GB_FULL:
3272                 link.link_speed = ETH_SPEED_NUM_1G;
3273                 break;
3274
3275         case IXGBE_LINK_SPEED_10GB_FULL:
3276                 link.link_speed = ETH_SPEED_NUM_10G;
3277                 break;
3278         }
3279         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3280
3281         if (link.link_status == old.link_status)
3282                 return -1;
3283
3284         return 0;
3285 }
3286
3287 static void
3288 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3289 {
3290         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3291         uint32_t fctrl;
3292
3293         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3294         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3295         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3296 }
3297
3298 static void
3299 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3300 {
3301         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3302         uint32_t fctrl;
3303
3304         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3305         fctrl &= (~IXGBE_FCTRL_UPE);
3306         if (dev->data->all_multicast == 1)
3307                 fctrl |= IXGBE_FCTRL_MPE;
3308         else
3309                 fctrl &= (~IXGBE_FCTRL_MPE);
3310         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3311 }
3312
3313 static void
3314 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3315 {
3316         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3317         uint32_t fctrl;
3318
3319         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3320         fctrl |= IXGBE_FCTRL_MPE;
3321         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3322 }
3323
3324 static void
3325 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3326 {
3327         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3328         uint32_t fctrl;
3329
3330         if (dev->data->promiscuous == 1)
3331                 return; /* must remain in all_multicast mode */
3332
3333         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3334         fctrl &= (~IXGBE_FCTRL_MPE);
3335         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3336 }
3337
3338 /**
3339  * It clears the interrupt causes and enables the interrupt.
3340  * It will be called once only during nic initialized.
3341  *
3342  * @param dev
3343  *  Pointer to struct rte_eth_dev.
3344  *
3345  * @return
3346  *  - On success, zero.
3347  *  - On failure, a negative value.
3348  */
3349 static int
3350 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3351 {
3352         struct ixgbe_interrupt *intr =
3353                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3354
3355         ixgbe_dev_link_status_print(dev);
3356         intr->mask |= IXGBE_EICR_LSC;
3357
3358         return 0;
3359 }
3360
3361 /**
3362  * It clears the interrupt causes and enables the interrupt.
3363  * It will be called once only during nic initialized.
3364  *
3365  * @param dev
3366  *  Pointer to struct rte_eth_dev.
3367  *
3368  * @return
3369  *  - On success, zero.
3370  *  - On failure, a negative value.
3371  */
3372 static int
3373 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3374 {
3375         struct ixgbe_interrupt *intr =
3376                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3377
3378         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3379
3380         return 0;
3381 }
3382
3383 /*
3384  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3385  *
3386  * @param dev
3387  *  Pointer to struct rte_eth_dev.
3388  *
3389  * @return
3390  *  - On success, zero.
3391  *  - On failure, a negative value.
3392  */
3393 static int
3394 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3395 {
3396         uint32_t eicr;
3397         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3398         struct ixgbe_interrupt *intr =
3399                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3400
3401         /* clear all cause mask */
3402         ixgbe_disable_intr(hw);
3403
3404         /* read-on-clear nic registers here */
3405         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3406         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3407
3408         intr->flags = 0;
3409
3410         /* set flag for async link update */
3411         if (eicr & IXGBE_EICR_LSC)
3412                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3413
3414         if (eicr & IXGBE_EICR_MAILBOX)
3415                 intr->flags |= IXGBE_FLAG_MAILBOX;
3416
3417         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3418             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3419             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3420                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3421
3422         return 0;
3423 }
3424
3425 /**
3426  * It gets and then prints the link status.
3427  *
3428  * @param dev
3429  *  Pointer to struct rte_eth_dev.
3430  *
3431  * @return
3432  *  - On success, zero.
3433  *  - On failure, a negative value.
3434  */
3435 static void
3436 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3437 {
3438         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3439         struct rte_eth_link link;
3440
3441         memset(&link, 0, sizeof(link));
3442         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3443         if (link.link_status) {
3444                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3445                                         (int)(dev->data->port_id),
3446                                         (unsigned)link.link_speed,
3447                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3448                                         "full-duplex" : "half-duplex");
3449         } else {
3450                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3451                                 (int)(dev->data->port_id));
3452         }
3453         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3454                                 pci_dev->addr.domain,
3455                                 pci_dev->addr.bus,
3456                                 pci_dev->addr.devid,
3457                                 pci_dev->addr.function);
3458 }
3459
3460 /*
3461  * It executes link_update after knowing an interrupt occurred.
3462  *
3463  * @param dev
3464  *  Pointer to struct rte_eth_dev.
3465  *
3466  * @return
3467  *  - On success, zero.
3468  *  - On failure, a negative value.
3469  */
3470 static int
3471 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3472                            struct rte_intr_handle *intr_handle)
3473 {
3474         struct ixgbe_interrupt *intr =
3475                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3476         int64_t timeout;
3477         struct rte_eth_link link;
3478         int intr_enable_delay = false;
3479         struct ixgbe_hw *hw =
3480                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3481
3482         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3483
3484         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3485                 ixgbe_pf_mbx_process(dev);
3486                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3487         }
3488
3489         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3490                 ixgbe_handle_lasi(hw);
3491                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3492         }
3493
3494         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3495                 /* get the link status before link update, for predicting later */
3496                 memset(&link, 0, sizeof(link));
3497                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3498
3499                 ixgbe_dev_link_update(dev, 0);
3500
3501                 /* likely to up */
3502                 if (!link.link_status)
3503                         /* handle it 1 sec later, wait it being stable */
3504                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3505                 /* likely to down */
3506                 else
3507                         /* handle it 4 sec later, wait it being stable */
3508                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3509
3510                 ixgbe_dev_link_status_print(dev);
3511
3512                 intr_enable_delay = true;
3513         }
3514
3515         if (intr_enable_delay) {
3516                 if (rte_eal_alarm_set(timeout * 1000,
3517                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3518                         PMD_DRV_LOG(ERR, "Error setting alarm");
3519         } else {
3520                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3521                 ixgbe_enable_intr(dev);
3522                 rte_intr_enable(intr_handle);
3523         }
3524
3525
3526         return 0;
3527 }
3528
3529 /**
3530  * Interrupt handler which shall be registered for alarm callback for delayed
3531  * handling specific interrupt to wait for the stable nic state. As the
3532  * NIC interrupt state is not stable for ixgbe after link is just down,
3533  * it needs to wait 4 seconds to get the stable status.
3534  *
3535  * @param handle
3536  *  Pointer to interrupt handle.
3537  * @param param
3538  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3539  *
3540  * @return
3541  *  void
3542  */
3543 static void
3544 ixgbe_dev_interrupt_delayed_handler(void *param)
3545 {
3546         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3547         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3548         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3549         struct ixgbe_interrupt *intr =
3550                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3551         struct ixgbe_hw *hw =
3552                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3553         uint32_t eicr;
3554
3555         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3556         if (eicr & IXGBE_EICR_MAILBOX)
3557                 ixgbe_pf_mbx_process(dev);
3558
3559         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3560                 ixgbe_handle_lasi(hw);
3561                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3562         }
3563
3564         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3565                 ixgbe_dev_link_update(dev, 0);
3566                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3567                 ixgbe_dev_link_status_print(dev);
3568                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3569         }
3570
3571         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3572         ixgbe_enable_intr(dev);
3573         rte_intr_enable(intr_handle);
3574 }
3575
3576 /**
3577  * Interrupt handler triggered by NIC  for handling
3578  * specific interrupt.
3579  *
3580  * @param handle
3581  *  Pointer to interrupt handle.
3582  * @param param
3583  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3584  *
3585  * @return
3586  *  void
3587  */
3588 static void
3589 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3590                             void *param)
3591 {
3592         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3593
3594         ixgbe_dev_interrupt_get_status(dev);
3595         ixgbe_dev_interrupt_action(dev, handle);
3596 }
3597
3598 static int
3599 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3600 {
3601         struct ixgbe_hw *hw;
3602
3603         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3604         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3605 }
3606
3607 static int
3608 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3609 {
3610         struct ixgbe_hw *hw;
3611
3612         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3613         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3614 }
3615
3616 static int
3617 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3618 {
3619         struct ixgbe_hw *hw;
3620         uint32_t mflcn_reg;
3621         uint32_t fccfg_reg;
3622         int rx_pause;
3623         int tx_pause;
3624
3625         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3626
3627         fc_conf->pause_time = hw->fc.pause_time;
3628         fc_conf->high_water = hw->fc.high_water[0];
3629         fc_conf->low_water = hw->fc.low_water[0];
3630         fc_conf->send_xon = hw->fc.send_xon;
3631         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3632
3633         /*
3634          * Return rx_pause status according to actual setting of
3635          * MFLCN register.
3636          */
3637         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3638         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3639                 rx_pause = 1;
3640         else
3641                 rx_pause = 0;
3642
3643         /*
3644          * Return tx_pause status according to actual setting of
3645          * FCCFG register.
3646          */
3647         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3648         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3649                 tx_pause = 1;
3650         else
3651                 tx_pause = 0;
3652
3653         if (rx_pause && tx_pause)
3654                 fc_conf->mode = RTE_FC_FULL;
3655         else if (rx_pause)
3656                 fc_conf->mode = RTE_FC_RX_PAUSE;
3657         else if (tx_pause)
3658                 fc_conf->mode = RTE_FC_TX_PAUSE;
3659         else
3660                 fc_conf->mode = RTE_FC_NONE;
3661
3662         return 0;
3663 }
3664
3665 static int
3666 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3667 {
3668         struct ixgbe_hw *hw;
3669         int err;
3670         uint32_t rx_buf_size;
3671         uint32_t max_high_water;
3672         uint32_t mflcn;
3673         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3674                 ixgbe_fc_none,
3675                 ixgbe_fc_rx_pause,
3676                 ixgbe_fc_tx_pause,
3677                 ixgbe_fc_full
3678         };
3679
3680         PMD_INIT_FUNC_TRACE();
3681
3682         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3683         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3684         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3685
3686         /*
3687          * At least reserve one Ethernet frame for watermark
3688          * high_water/low_water in kilo bytes for ixgbe
3689          */
3690         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3691         if ((fc_conf->high_water > max_high_water) ||
3692                 (fc_conf->high_water < fc_conf->low_water)) {
3693                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3694                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3695                 return -EINVAL;
3696         }
3697
3698         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3699         hw->fc.pause_time     = fc_conf->pause_time;
3700         hw->fc.high_water[0]  = fc_conf->high_water;
3701         hw->fc.low_water[0]   = fc_conf->low_water;
3702         hw->fc.send_xon       = fc_conf->send_xon;
3703         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3704
3705         err = ixgbe_fc_enable(hw);
3706
3707         /* Not negotiated is not an error case */
3708         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3709
3710                 /* check if we want to forward MAC frames - driver doesn't have native
3711                  * capability to do that, so we'll write the registers ourselves */
3712
3713                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3714
3715                 /* set or clear MFLCN.PMCF bit depending on configuration */
3716                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3717                         mflcn |= IXGBE_MFLCN_PMCF;
3718                 else
3719                         mflcn &= ~IXGBE_MFLCN_PMCF;
3720
3721                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3722                 IXGBE_WRITE_FLUSH(hw);
3723
3724                 return 0;
3725         }
3726
3727         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3728         return -EIO;
3729 }
3730
3731 /**
3732  *  ixgbe_pfc_enable_generic - Enable flow control
3733  *  @hw: pointer to hardware structure
3734  *  @tc_num: traffic class number
3735  *  Enable flow control according to the current settings.
3736  */
3737 static int
3738 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3739 {
3740         int ret_val = 0;
3741         uint32_t mflcn_reg, fccfg_reg;
3742         uint32_t reg;
3743         uint32_t fcrtl, fcrth;
3744         uint8_t i;
3745         uint8_t nb_rx_en;
3746
3747         /* Validate the water mark configuration */
3748         if (!hw->fc.pause_time) {
3749                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3750                 goto out;
3751         }
3752
3753         /* Low water mark of zero causes XOFF floods */
3754         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3755                  /* High/Low water can not be 0 */
3756                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3757                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3758                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3759                         goto out;
3760                 }
3761
3762                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3763                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3764                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3765                         goto out;
3766                 }
3767         }
3768         /* Negotiate the fc mode to use */
3769         ixgbe_fc_autoneg(hw);
3770
3771         /* Disable any previous flow control settings */
3772         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3773         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3774
3775         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3776         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3777
3778         switch (hw->fc.current_mode) {
3779         case ixgbe_fc_none:
3780                 /*
3781                  * If the count of enabled RX Priority Flow control >1,
3782                  * and the TX pause can not be disabled
3783                  */
3784                 nb_rx_en = 0;
3785                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3786                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3787                         if (reg & IXGBE_FCRTH_FCEN)
3788                                 nb_rx_en++;
3789                 }
3790                 if (nb_rx_en > 1)
3791                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3792                 break;
3793         case ixgbe_fc_rx_pause:
3794                 /*
3795                  * Rx Flow control is enabled and Tx Flow control is
3796                  * disabled by software override. Since there really
3797                  * isn't a way to advertise that we are capable of RX
3798                  * Pause ONLY, we will advertise that we support both
3799                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3800                  * disable the adapter's ability to send PAUSE frames.
3801                  */
3802                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3803                 /*
3804                  * If the count of enabled RX Priority Flow control >1,
3805                  * and the TX pause can not be disabled
3806                  */
3807                 nb_rx_en = 0;
3808                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3809                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3810                         if (reg & IXGBE_FCRTH_FCEN)
3811                                 nb_rx_en++;
3812                 }
3813                 if (nb_rx_en > 1)
3814                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3815                 break;
3816         case ixgbe_fc_tx_pause:
3817                 /*
3818                  * Tx Flow control is enabled, and Rx Flow control is
3819                  * disabled by software override.
3820                  */
3821                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3822                 break;
3823         case ixgbe_fc_full:
3824                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3825                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3826                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3827                 break;
3828         default:
3829                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3830                 ret_val = IXGBE_ERR_CONFIG;
3831                 goto out;
3832         }
3833
3834         /* Set 802.3x based flow control settings. */
3835         mflcn_reg |= IXGBE_MFLCN_DPF;
3836         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3837         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3838
3839         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3840         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3841                 hw->fc.high_water[tc_num]) {
3842                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3843                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3844                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3845         } else {
3846                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3847                 /*
3848                  * In order to prevent Tx hangs when the internal Tx
3849                  * switch is enabled we must set the high water mark
3850                  * to the maximum FCRTH value.  This allows the Tx
3851                  * switch to function even under heavy Rx workloads.
3852                  */
3853                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3854         }
3855         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3856
3857         /* Configure pause time (2 TCs per register) */
3858         reg = hw->fc.pause_time * 0x00010001;
3859         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3860                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3861
3862         /* Configure flow control refresh threshold value */
3863         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3864
3865 out:
3866         return ret_val;
3867 }
3868
3869 static int
3870 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3871 {
3872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3873         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3874
3875         if (hw->mac.type != ixgbe_mac_82598EB) {
3876                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3877         }
3878         return ret_val;
3879 }
3880
3881 static int
3882 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3883 {
3884         int err;
3885         uint32_t rx_buf_size;
3886         uint32_t max_high_water;
3887         uint8_t tc_num;
3888         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3889         struct ixgbe_hw *hw =
3890                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3891         struct ixgbe_dcb_config *dcb_config =
3892                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3893
3894         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3895                 ixgbe_fc_none,
3896                 ixgbe_fc_rx_pause,
3897                 ixgbe_fc_tx_pause,
3898                 ixgbe_fc_full
3899         };
3900
3901         PMD_INIT_FUNC_TRACE();
3902
3903         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3904         tc_num = map[pfc_conf->priority];
3905         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3906         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3907         /*
3908          * At least reserve one Ethernet frame for watermark
3909          * high_water/low_water in kilo bytes for ixgbe
3910          */
3911         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3912         if ((pfc_conf->fc.high_water > max_high_water) ||
3913             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3914                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3915                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3916                 return -EINVAL;
3917         }
3918
3919         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3920         hw->fc.pause_time = pfc_conf->fc.pause_time;
3921         hw->fc.send_xon = pfc_conf->fc.send_xon;
3922         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3923         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3924
3925         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3926
3927         /* Not negotiated is not an error case */
3928         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3929                 return 0;
3930
3931         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3932         return -EIO;
3933 }
3934
3935 static int
3936 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3937                           struct rte_eth_rss_reta_entry64 *reta_conf,
3938                           uint16_t reta_size)
3939 {
3940         uint16_t i, sp_reta_size;
3941         uint8_t j, mask;
3942         uint32_t reta, r;
3943         uint16_t idx, shift;
3944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3945         uint32_t reta_reg;
3946
3947         PMD_INIT_FUNC_TRACE();
3948
3949         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3950                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3951                         "NIC.");
3952                 return -ENOTSUP;
3953         }
3954
3955         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3956         if (reta_size != sp_reta_size) {
3957                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3958                         "(%d) doesn't match the number hardware can supported "
3959                         "(%d)\n", reta_size, sp_reta_size);
3960                 return -EINVAL;
3961         }
3962
3963         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3964                 idx = i / RTE_RETA_GROUP_SIZE;
3965                 shift = i % RTE_RETA_GROUP_SIZE;
3966                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3967                                                 IXGBE_4_BIT_MASK);
3968                 if (!mask)
3969                         continue;
3970                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3971                 if (mask == IXGBE_4_BIT_MASK)
3972                         r = 0;
3973                 else
3974                         r = IXGBE_READ_REG(hw, reta_reg);
3975                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3976                         if (mask & (0x1 << j))
3977                                 reta |= reta_conf[idx].reta[shift + j] <<
3978                                                         (CHAR_BIT * j);
3979                         else
3980                                 reta |= r & (IXGBE_8_BIT_MASK <<
3981                                                 (CHAR_BIT * j));
3982                 }
3983                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3984         }
3985
3986         return 0;
3987 }
3988
3989 static int
3990 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3991                          struct rte_eth_rss_reta_entry64 *reta_conf,
3992                          uint16_t reta_size)
3993 {
3994         uint16_t i, sp_reta_size;
3995         uint8_t j, mask;
3996         uint32_t reta;
3997         uint16_t idx, shift;
3998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3999         uint32_t reta_reg;
4000
4001         PMD_INIT_FUNC_TRACE();
4002         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4003         if (reta_size != sp_reta_size) {
4004                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4005                         "(%d) doesn't match the number hardware can supported "
4006                         "(%d)\n", reta_size, sp_reta_size);
4007                 return -EINVAL;
4008         }
4009
4010         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4011                 idx = i / RTE_RETA_GROUP_SIZE;
4012                 shift = i % RTE_RETA_GROUP_SIZE;
4013                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4014                                                 IXGBE_4_BIT_MASK);
4015                 if (!mask)
4016                         continue;
4017
4018                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4019                 reta = IXGBE_READ_REG(hw, reta_reg);
4020                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4021                         if (mask & (0x1 << j))
4022                                 reta_conf[idx].reta[shift + j] =
4023                                         ((reta >> (CHAR_BIT * j)) &
4024                                                 IXGBE_8_BIT_MASK);
4025                 }
4026         }
4027
4028         return 0;
4029 }
4030
4031 static void
4032 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4033                                 uint32_t index, uint32_t pool)
4034 {
4035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4036         uint32_t enable_addr = 1;
4037
4038         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4039 }
4040
4041 static void
4042 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4043 {
4044         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4045
4046         ixgbe_clear_rar(hw, index);
4047 }
4048
4049 static void
4050 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4051 {
4052         ixgbe_remove_rar(dev, 0);
4053
4054         ixgbe_add_rar(dev, addr, 0, 0);
4055 }
4056
4057 int
4058 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4059                 struct ether_addr *mac_addr)
4060 {
4061         struct ixgbe_hw *hw;
4062         struct ixgbe_vf_info *vfinfo;
4063         int rar_entry;
4064         uint8_t *new_mac = (uint8_t *)(mac_addr);
4065         struct rte_eth_dev *dev;
4066         struct rte_eth_dev_info dev_info;
4067
4068         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4069
4070         dev = &rte_eth_devices[port];
4071         rte_eth_dev_info_get(port, &dev_info);
4072
4073         if (vf >= dev_info.max_vfs)
4074                 return -EINVAL;
4075
4076         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4077         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4078         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4079
4080         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4081                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4082                                 ETHER_ADDR_LEN);
4083                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4084                                 IXGBE_RAH_AV);
4085         }
4086         return -EINVAL;
4087 }
4088
4089 static int
4090 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4091 {
4092         uint32_t hlreg0;
4093         uint32_t maxfrs;
4094         struct ixgbe_hw *hw;
4095         struct rte_eth_dev_info dev_info;
4096         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4097
4098         ixgbe_dev_info_get(dev, &dev_info);
4099
4100         /* check that mtu is within the allowed range */
4101         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4102                 return -EINVAL;
4103
4104         /* refuse mtu that requires the support of scattered packets when this
4105          * feature has not been enabled before.
4106          */
4107         if (!dev->data->scattered_rx &&
4108             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4109              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4110                 return -EINVAL;
4111
4112         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4113         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4114
4115         /* switch to jumbo mode if needed */
4116         if (frame_size > ETHER_MAX_LEN) {
4117                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4118                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4119         } else {
4120                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4121                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4122         }
4123         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4124
4125         /* update max frame size */
4126         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4127
4128         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4129         maxfrs &= 0x0000FFFF;
4130         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4131         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4132
4133         return 0;
4134 }
4135
4136 /*
4137  * Virtual Function operations
4138  */
4139 static void
4140 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4141 {
4142         PMD_INIT_FUNC_TRACE();
4143
4144         /* Clear interrupt mask to stop from interrupts being generated */
4145         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4146
4147         IXGBE_WRITE_FLUSH(hw);
4148 }
4149
4150 static void
4151 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4152 {
4153         PMD_INIT_FUNC_TRACE();
4154
4155         /* VF enable interrupt autoclean */
4156         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4157         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4158         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4159
4160         IXGBE_WRITE_FLUSH(hw);
4161 }
4162
4163 static int
4164 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4165 {
4166         struct rte_eth_conf *conf = &dev->data->dev_conf;
4167         struct ixgbe_adapter *adapter =
4168                         (struct ixgbe_adapter *)dev->data->dev_private;
4169
4170         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4171                      dev->data->port_id);
4172
4173         /*
4174          * VF has no ability to enable/disable HW CRC
4175          * Keep the persistent behavior the same as Host PF
4176          */
4177 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4178         if (!conf->rxmode.hw_strip_crc) {
4179                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4180                 conf->rxmode.hw_strip_crc = 1;
4181         }
4182 #else
4183         if (conf->rxmode.hw_strip_crc) {
4184                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4185                 conf->rxmode.hw_strip_crc = 0;
4186         }
4187 #endif
4188
4189         /*
4190          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4191          * allocation or vector Rx preconditions we will reset it.
4192          */
4193         adapter->rx_bulk_alloc_allowed = true;
4194         adapter->rx_vec_allowed = true;
4195
4196         return 0;
4197 }
4198
4199 static int
4200 ixgbevf_dev_start(struct rte_eth_dev *dev)
4201 {
4202         struct ixgbe_hw *hw =
4203                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4204         uint32_t intr_vector = 0;
4205         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4206         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4207
4208         int err, mask = 0;
4209
4210         PMD_INIT_FUNC_TRACE();
4211
4212         hw->mac.ops.reset_hw(hw);
4213         hw->mac.get_link_status = true;
4214
4215         /* negotiate mailbox API version to use with the PF. */
4216         ixgbevf_negotiate_api(hw);
4217
4218         ixgbevf_dev_tx_init(dev);
4219
4220         /* This can fail when allocating mbufs for descriptor rings */
4221         err = ixgbevf_dev_rx_init(dev);
4222         if (err) {
4223                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4224                 ixgbe_dev_clear_queues(dev);
4225                 return err;
4226         }
4227
4228         /* Set vfta */
4229         ixgbevf_set_vfta_all(dev, 1);
4230
4231         /* Set HW strip */
4232         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4233                 ETH_VLAN_EXTEND_MASK;
4234         ixgbevf_vlan_offload_set(dev, mask);
4235
4236         ixgbevf_dev_rxtx_start(dev);
4237
4238         /* check and configure queue intr-vector mapping */
4239         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4240                 intr_vector = dev->data->nb_rx_queues;
4241                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4242                         return -1;
4243         }
4244
4245         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4246                 intr_handle->intr_vec =
4247                         rte_zmalloc("intr_vec",
4248                                     dev->data->nb_rx_queues * sizeof(int), 0);
4249                 if (intr_handle->intr_vec == NULL) {
4250                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4251                                      " intr_vec\n", dev->data->nb_rx_queues);
4252                         return -ENOMEM;
4253                 }
4254         }
4255         ixgbevf_configure_msix(dev);
4256
4257         rte_intr_enable(intr_handle);
4258
4259         /* Re-enable interrupt for VF */
4260         ixgbevf_intr_enable(hw);
4261
4262         return 0;
4263 }
4264
4265 static void
4266 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4267 {
4268         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4269         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4270         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4271
4272         PMD_INIT_FUNC_TRACE();
4273
4274         ixgbevf_intr_disable(hw);
4275
4276         hw->adapter_stopped = 1;
4277         ixgbe_stop_adapter(hw);
4278
4279         /*
4280           * Clear what we set, but we still keep shadow_vfta to
4281           * restore after device starts
4282           */
4283         ixgbevf_set_vfta_all(dev, 0);
4284
4285         /* Clear stored conf */
4286         dev->data->scattered_rx = 0;
4287
4288         ixgbe_dev_clear_queues(dev);
4289
4290         /* Clean datapath event and queue/vec mapping */
4291         rte_intr_efd_disable(intr_handle);
4292         if (intr_handle->intr_vec != NULL) {
4293                 rte_free(intr_handle->intr_vec);
4294                 intr_handle->intr_vec = NULL;
4295         }
4296 }
4297
4298 static void
4299 ixgbevf_dev_close(struct rte_eth_dev *dev)
4300 {
4301         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4302
4303         PMD_INIT_FUNC_TRACE();
4304
4305         ixgbe_reset_hw(hw);
4306
4307         ixgbevf_dev_stop(dev);
4308
4309         ixgbe_dev_free_queues(dev);
4310
4311         /**
4312          * Remove the VF MAC address ro ensure
4313          * that the VF traffic goes to the PF
4314          * after stop, close and detach of the VF
4315          **/
4316         ixgbevf_remove_mac_addr(dev, 0);
4317 }
4318
4319 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4320 {
4321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4322         struct ixgbe_vfta *shadow_vfta =
4323                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4324         int i = 0, j = 0, vfta = 0, mask = 1;
4325
4326         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4327                 vfta = shadow_vfta->vfta[i];
4328                 if (vfta) {
4329                         mask = 1;
4330                         for (j = 0; j < 32; j++) {
4331                                 if (vfta & mask)
4332                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4333                                                        on, false);
4334                                 mask <<= 1;
4335                         }
4336                 }
4337         }
4338
4339 }
4340
4341 static int
4342 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4343 {
4344         struct ixgbe_hw *hw =
4345                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4346         struct ixgbe_vfta *shadow_vfta =
4347                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4348         uint32_t vid_idx = 0;
4349         uint32_t vid_bit = 0;
4350         int ret = 0;
4351
4352         PMD_INIT_FUNC_TRACE();
4353
4354         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4355         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4356         if (ret) {
4357                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4358                 return ret;
4359         }
4360         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4361         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4362
4363         /* Save what we set and retore it after device reset */
4364         if (on)
4365                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4366         else
4367                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4368
4369         return 0;
4370 }
4371
4372 static void
4373 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4374 {
4375         struct ixgbe_hw *hw =
4376                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4377         uint32_t ctrl;
4378
4379         PMD_INIT_FUNC_TRACE();
4380
4381         if (queue >= hw->mac.max_rx_queues)
4382                 return;
4383
4384         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4385         if (on)
4386                 ctrl |= IXGBE_RXDCTL_VME;
4387         else
4388                 ctrl &= ~IXGBE_RXDCTL_VME;
4389         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4390
4391         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4392 }
4393
4394 static void
4395 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4396 {
4397         struct ixgbe_hw *hw =
4398                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4399         uint16_t i;
4400         int on = 0;
4401
4402         /* VF function only support hw strip feature, others are not support */
4403         if (mask & ETH_VLAN_STRIP_MASK) {
4404                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4405
4406                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4407                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4408         }
4409 }
4410
4411 static int
4412 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4413 {
4414         uint32_t reg_val;
4415
4416         /* we only need to do this if VMDq is enabled */
4417         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4418         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4419                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4420                 return -1;
4421         }
4422
4423         return 0;
4424 }
4425
4426 static uint32_t
4427 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4428 {
4429         uint32_t vector = 0;
4430
4431         switch (hw->mac.mc_filter_type) {
4432         case 0:   /* use bits [47:36] of the address */
4433                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4434                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4435                 break;
4436         case 1:   /* use bits [46:35] of the address */
4437                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4438                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4439                 break;
4440         case 2:   /* use bits [45:34] of the address */
4441                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4442                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4443                 break;
4444         case 3:   /* use bits [43:32] of the address */
4445                 vector = ((uc_addr->addr_bytes[4]) |
4446                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4447                 break;
4448         default:  /* Invalid mc_filter_type */
4449                 break;
4450         }
4451
4452         /* vector can only be 12-bits or boundary will be exceeded */
4453         vector &= 0xFFF;
4454         return vector;
4455 }
4456
4457 static int
4458 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4459                         uint8_t on)
4460 {
4461         uint32_t vector;
4462         uint32_t uta_idx;
4463         uint32_t reg_val;
4464         uint32_t uta_shift;
4465         uint32_t rc;
4466         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4467         const uint32_t ixgbe_uta_bit_shift = 5;
4468         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4469         const uint32_t bit1 = 0x1;
4470
4471         struct ixgbe_hw *hw =
4472                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4473         struct ixgbe_uta_info *uta_info =
4474                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4475
4476         /* The UTA table only exists on 82599 hardware and newer */
4477         if (hw->mac.type < ixgbe_mac_82599EB)
4478                 return -ENOTSUP;
4479
4480         vector = ixgbe_uta_vector(hw, mac_addr);
4481         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4482         uta_shift = vector & ixgbe_uta_bit_mask;
4483
4484         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4485         if (rc == on)
4486                 return 0;
4487
4488         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4489         if (on) {
4490                 uta_info->uta_in_use++;
4491                 reg_val |= (bit1 << uta_shift);
4492                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4493         } else {
4494                 uta_info->uta_in_use--;
4495                 reg_val &= ~(bit1 << uta_shift);
4496                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4497         }
4498
4499         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4500
4501         if (uta_info->uta_in_use > 0)
4502                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4503                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4504         else
4505                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4506
4507         return 0;
4508 }
4509
4510 static int
4511 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4512 {
4513         int i;
4514         struct ixgbe_hw *hw =
4515                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4516         struct ixgbe_uta_info *uta_info =
4517                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4518
4519         /* The UTA table only exists on 82599 hardware and newer */
4520         if (hw->mac.type < ixgbe_mac_82599EB)
4521                 return -ENOTSUP;
4522
4523         if (on) {
4524                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4525                         uta_info->uta_shadow[i] = ~0;
4526                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4527                 }
4528         } else {
4529                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4530                         uta_info->uta_shadow[i] = 0;
4531                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4532                 }
4533         }
4534         return 0;
4535
4536 }
4537
4538 uint32_t
4539 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4540 {
4541         uint32_t new_val = orig_val;
4542
4543         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4544                 new_val |= IXGBE_VMOLR_AUPE;
4545         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4546                 new_val |= IXGBE_VMOLR_ROMPE;
4547         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4548                 new_val |= IXGBE_VMOLR_ROPE;
4549         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4550                 new_val |= IXGBE_VMOLR_BAM;
4551         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4552                 new_val |= IXGBE_VMOLR_MPE;
4553
4554         return new_val;
4555 }
4556
4557 static int
4558 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4559                                uint16_t rx_mask, uint8_t on)
4560 {
4561         int val = 0;
4562
4563         struct ixgbe_hw *hw =
4564                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4565         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4566
4567         if (hw->mac.type == ixgbe_mac_82598EB) {
4568                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4569                              " on 82599 hardware and newer");
4570                 return -ENOTSUP;
4571         }
4572         if (ixgbe_vmdq_mode_check(hw) < 0)
4573                 return -ENOTSUP;
4574
4575         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4576
4577         if (on)
4578                 vmolr |= val;
4579         else
4580                 vmolr &= ~val;
4581
4582         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4583
4584         return 0;
4585 }
4586
4587 static int
4588 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4589 {
4590         uint32_t reg, addr;
4591         uint32_t val;
4592         const uint8_t bit1 = 0x1;
4593
4594         struct ixgbe_hw *hw =
4595                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4596
4597         if (ixgbe_vmdq_mode_check(hw) < 0)
4598                 return -ENOTSUP;
4599
4600         if (pool >= ETH_64_POOLS)
4601                 return -EINVAL;
4602
4603         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4604         if (pool >= 32) {
4605                 addr = IXGBE_VFRE(1);
4606                 val = bit1 << (pool - 32);
4607         } else {
4608                 addr = IXGBE_VFRE(0);
4609                 val = bit1 << pool;
4610         }
4611
4612         reg = IXGBE_READ_REG(hw, addr);
4613
4614         if (on)
4615                 reg |= val;
4616         else
4617                 reg &= ~val;
4618
4619         IXGBE_WRITE_REG(hw, addr, reg);
4620
4621         return 0;
4622 }
4623
4624 static int
4625 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4626 {
4627         uint32_t reg, addr;
4628         uint32_t val;
4629         const uint8_t bit1 = 0x1;
4630
4631         struct ixgbe_hw *hw =
4632                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4633
4634         if (ixgbe_vmdq_mode_check(hw) < 0)
4635                 return -ENOTSUP;
4636
4637         if (pool >= ETH_64_POOLS)
4638                 return -EINVAL;
4639
4640         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4641         if (pool >= 32) {
4642                 addr = IXGBE_VFTE(1);
4643                 val = bit1 << (pool - 32);
4644         } else {
4645                 addr = IXGBE_VFTE(0);
4646                 val = bit1 << pool;
4647         }
4648
4649         reg = IXGBE_READ_REG(hw, addr);
4650
4651         if (on)
4652                 reg |= val;
4653         else
4654                 reg &= ~val;
4655
4656         IXGBE_WRITE_REG(hw, addr, reg);
4657
4658         return 0;
4659 }
4660
4661 static int
4662 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4663                         uint64_t pool_mask, uint8_t vlan_on)
4664 {
4665         int ret = 0;
4666         uint16_t pool_idx;
4667         struct ixgbe_hw *hw =
4668                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4669
4670         if (ixgbe_vmdq_mode_check(hw) < 0)
4671                 return -ENOTSUP;
4672         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4673                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4674                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4675                                                    vlan_on, false);
4676                         if (ret < 0)
4677                                 return ret;
4678                 }
4679         }
4680
4681         return ret;
4682 }
4683
4684 int
4685 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4686 {
4687         struct ixgbe_hw *hw;
4688         struct ixgbe_mac_info *mac;
4689         struct rte_eth_dev *dev;
4690         struct rte_eth_dev_info dev_info;
4691
4692         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4693
4694         dev = &rte_eth_devices[port];
4695         rte_eth_dev_info_get(port, &dev_info);
4696
4697         if (vf >= dev_info.max_vfs)
4698                 return -EINVAL;
4699
4700         if (on > 1)
4701                 return -EINVAL;
4702
4703         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4704         mac = &hw->mac;
4705
4706         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4707
4708         return 0;
4709 }
4710
4711 int
4712 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4713 {
4714         struct ixgbe_hw *hw;
4715         struct ixgbe_mac_info *mac;
4716         struct rte_eth_dev *dev;
4717         struct rte_eth_dev_info dev_info;
4718
4719         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4720
4721         dev = &rte_eth_devices[port];
4722         rte_eth_dev_info_get(port, &dev_info);
4723
4724         if (vf >= dev_info.max_vfs)
4725                 return -EINVAL;
4726
4727         if (on > 1)
4728                 return -EINVAL;
4729
4730         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4731         mac = &hw->mac;
4732         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4733
4734         return 0;
4735 }
4736
4737 int
4738 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4739 {
4740         struct ixgbe_hw *hw;
4741         uint32_t ctrl;
4742         struct rte_eth_dev *dev;
4743         struct rte_eth_dev_info dev_info;
4744
4745         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4746
4747         dev = &rte_eth_devices[port];
4748         rte_eth_dev_info_get(port, &dev_info);
4749
4750         if (vf >= dev_info.max_vfs)
4751                 return -EINVAL;
4752
4753         if (vlan_id > 4095)
4754                 return -EINVAL;
4755
4756         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4757         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4758         if (vlan_id) {
4759                 ctrl = vlan_id;
4760                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4761         } else {
4762                 ctrl = 0;
4763         }
4764
4765         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4766
4767         return 0;
4768 }
4769
4770 int
4771 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4772 {
4773         struct ixgbe_hw *hw;
4774         uint32_t ctrl;
4775         struct rte_eth_dev *dev;
4776
4777         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4778
4779         dev = &rte_eth_devices[port];
4780
4781         if (on > 1)
4782                 return -EINVAL;
4783
4784         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4785         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4786         /* enable or disable VMDQ loopback */
4787         if (on)
4788                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4789         else
4790                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4791
4792         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4793
4794         return 0;
4795 }
4796
4797 int
4798 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4799 {
4800         struct ixgbe_hw *hw;
4801         uint32_t reg_value;
4802         int i;
4803         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4804         struct rte_eth_dev *dev;
4805
4806         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4807
4808         dev = &rte_eth_devices[port];
4809
4810         if (on > 1)
4811                 return -EINVAL;
4812
4813         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4814         for (i = 0; i <= num_queues; i++) {
4815                 reg_value = IXGBE_QDE_WRITE |
4816                                 (i << IXGBE_QDE_IDX_SHIFT) |
4817                                 (on & IXGBE_QDE_ENABLE);
4818                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4819         }
4820
4821         return 0;
4822 }
4823
4824 int
4825 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4826 {
4827         struct ixgbe_hw *hw;
4828         uint32_t reg_value;
4829         struct rte_eth_dev *dev;
4830         struct rte_eth_dev_info dev_info;
4831
4832         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4833
4834         dev = &rte_eth_devices[port];
4835         rte_eth_dev_info_get(port, &dev_info);
4836
4837         /* only support VF's 0 to 63 */
4838         if ((vf >= dev_info.max_vfs) || (vf > 63))
4839                 return -EINVAL;
4840
4841         if (on > 1)
4842                 return -EINVAL;
4843
4844         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4846         if (on)
4847                 reg_value |= IXGBE_SRRCTL_DROP_EN;
4848         else
4849                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4850
4851         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4852
4853         return 0;
4854 }
4855
4856 int
4857 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4858 {
4859         struct rte_eth_dev *dev;
4860         struct rte_eth_dev_info dev_info;
4861         uint16_t queues_per_pool;
4862         uint32_t q;
4863
4864         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4865
4866         dev = &rte_eth_devices[port];
4867         rte_eth_dev_info_get(port, &dev_info);
4868
4869         if (vf >= dev_info.max_vfs)
4870                 return -EINVAL;
4871
4872         if (on > 1)
4873                 return -EINVAL;
4874
4875         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
4876
4877         /* The PF has 128 queue pairs and in SRIOV configuration
4878          * those queues will be assigned to VF's, so RXDCTL
4879          * registers will be dealing with queues which will be
4880          * assigned to VF's.
4881          * Let's say we have SRIOV configured with 31 VF's then the
4882          * first 124 queues 0-123 will be allocated to VF's and only
4883          * the last 4 queues 123-127 will be assigned to the PF.
4884          */
4885
4886         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
4887
4888         for (q = 0; q < queues_per_pool; q++)
4889                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
4890                                 q + vf * queues_per_pool, on);
4891         return 0;
4892 }
4893
4894 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4895 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4896 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4897 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4898 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4899         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4900         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4901
4902 static int
4903 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4904                         struct rte_eth_mirror_conf *mirror_conf,
4905                         uint8_t rule_id, uint8_t on)
4906 {
4907         uint32_t mr_ctl, vlvf;
4908         uint32_t mp_lsb = 0;
4909         uint32_t mv_msb = 0;
4910         uint32_t mv_lsb = 0;
4911         uint32_t mp_msb = 0;
4912         uint8_t i = 0;
4913         int reg_index = 0;
4914         uint64_t vlan_mask = 0;
4915
4916         const uint8_t pool_mask_offset = 32;
4917         const uint8_t vlan_mask_offset = 32;
4918         const uint8_t dst_pool_offset = 8;
4919         const uint8_t rule_mr_offset  = 4;
4920         const uint8_t mirror_rule_mask = 0x0F;
4921
4922         struct ixgbe_mirror_info *mr_info =
4923                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4924         struct ixgbe_hw *hw =
4925                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4926         uint8_t mirror_type = 0;
4927
4928         if (ixgbe_vmdq_mode_check(hw) < 0)
4929                 return -ENOTSUP;
4930
4931         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4932                 return -EINVAL;
4933
4934         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4935                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4936                         mirror_conf->rule_type);
4937                 return -EINVAL;
4938         }
4939
4940         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4941                 mirror_type |= IXGBE_MRCTL_VLME;
4942                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4943                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4944                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4945                                 /* search vlan id related pool vlan filter index */
4946                                 reg_index = ixgbe_find_vlvf_slot(hw,
4947                                                  mirror_conf->vlan.vlan_id[i],
4948                                                  false);
4949                                 if (reg_index < 0)
4950                                         return -EINVAL;
4951                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4952                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4953                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4954                                       mirror_conf->vlan.vlan_id[i]))
4955                                         vlan_mask |= (1ULL << reg_index);
4956                                 else
4957                                         return -EINVAL;
4958                         }
4959                 }
4960
4961                 if (on) {
4962                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4963                         mv_msb = vlan_mask >> vlan_mask_offset;
4964
4965                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4966                                                 mirror_conf->vlan.vlan_mask;
4967                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4968                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4969                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4970                                                 mirror_conf->vlan.vlan_id[i];
4971                         }
4972                 } else {
4973                         mv_lsb = 0;
4974                         mv_msb = 0;
4975                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4976                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4977                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4978                 }
4979         }
4980
4981         /*
4982          * if enable pool mirror, write related pool mask register,if disable
4983          * pool mirror, clear PFMRVM register
4984          */
4985         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4986                 mirror_type |= IXGBE_MRCTL_VPME;
4987                 if (on) {
4988                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4989                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4990                         mr_info->mr_conf[rule_id].pool_mask =
4991                                         mirror_conf->pool_mask;
4992
4993                 } else {
4994                         mp_lsb = 0;
4995                         mp_msb = 0;
4996                         mr_info->mr_conf[rule_id].pool_mask = 0;
4997                 }
4998         }
4999         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5000                 mirror_type |= IXGBE_MRCTL_UPME;
5001         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5002                 mirror_type |= IXGBE_MRCTL_DPME;
5003
5004         /* read  mirror control register and recalculate it */
5005         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5006
5007         if (on) {
5008                 mr_ctl |= mirror_type;
5009                 mr_ctl &= mirror_rule_mask;
5010                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5011         } else
5012                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5013
5014         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5015         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5016
5017         /* write mirrror control  register */
5018         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5019
5020         /* write pool mirrror control  register */
5021         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5022                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5023                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5024                                 mp_msb);
5025         }
5026         /* write VLAN mirrror control  register */
5027         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5028                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5029                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5030                                 mv_msb);
5031         }
5032
5033         return 0;
5034 }
5035
5036 static int
5037 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5038 {
5039         int mr_ctl = 0;
5040         uint32_t lsb_val = 0;
5041         uint32_t msb_val = 0;
5042         const uint8_t rule_mr_offset = 4;
5043
5044         struct ixgbe_hw *hw =
5045                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5046         struct ixgbe_mirror_info *mr_info =
5047                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5048
5049         if (ixgbe_vmdq_mode_check(hw) < 0)
5050                 return -ENOTSUP;
5051
5052         memset(&mr_info->mr_conf[rule_id], 0,
5053                 sizeof(struct rte_eth_mirror_conf));
5054
5055         /* clear PFVMCTL register */
5056         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5057
5058         /* clear pool mask register */
5059         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5060         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5061
5062         /* clear vlan mask register */
5063         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5064         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5065
5066         return 0;
5067 }
5068
5069 static int
5070 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5071 {
5072         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5073         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5074         uint32_t mask;
5075         struct ixgbe_hw *hw =
5076                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5077
5078         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5079         mask |= (1 << IXGBE_MISC_VEC_ID);
5080         RTE_SET_USED(queue_id);
5081         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5082
5083         rte_intr_enable(intr_handle);
5084
5085         return 0;
5086 }
5087
5088 static int
5089 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5090 {
5091         uint32_t mask;
5092         struct ixgbe_hw *hw =
5093                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5094
5095         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5096         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5097         RTE_SET_USED(queue_id);
5098         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5099
5100         return 0;
5101 }
5102
5103 static int
5104 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5105 {
5106         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5107         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5108         uint32_t mask;
5109         struct ixgbe_hw *hw =
5110                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5111         struct ixgbe_interrupt *intr =
5112                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5113
5114         if (queue_id < 16) {
5115                 ixgbe_disable_intr(hw);
5116                 intr->mask |= (1 << queue_id);
5117                 ixgbe_enable_intr(dev);
5118         } else if (queue_id < 32) {
5119                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5120                 mask &= (1 << queue_id);
5121                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5122         } else if (queue_id < 64) {
5123                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5124                 mask &= (1 << (queue_id - 32));
5125                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5126         }
5127         rte_intr_enable(intr_handle);
5128
5129         return 0;
5130 }
5131
5132 static int
5133 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5134 {
5135         uint32_t mask;
5136         struct ixgbe_hw *hw =
5137                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5138         struct ixgbe_interrupt *intr =
5139                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5140
5141         if (queue_id < 16) {
5142                 ixgbe_disable_intr(hw);
5143                 intr->mask &= ~(1 << queue_id);
5144                 ixgbe_enable_intr(dev);
5145         } else if (queue_id < 32) {
5146                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5147                 mask &= ~(1 << queue_id);
5148                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5149         } else if (queue_id < 64) {
5150                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5151                 mask &= ~(1 << (queue_id - 32));
5152                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5153         }
5154
5155         return 0;
5156 }
5157
5158 static void
5159 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5160                      uint8_t queue, uint8_t msix_vector)
5161 {
5162         uint32_t tmp, idx;
5163
5164         if (direction == -1) {
5165                 /* other causes */
5166                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5167                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5168                 tmp &= ~0xFF;
5169                 tmp |= msix_vector;
5170                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5171         } else {
5172                 /* rx or tx cause */
5173                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5174                 idx = ((16 * (queue & 1)) + (8 * direction));
5175                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5176                 tmp &= ~(0xFF << idx);
5177                 tmp |= (msix_vector << idx);
5178                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5179         }
5180 }
5181
5182 /**
5183  * set the IVAR registers, mapping interrupt causes to vectors
5184  * @param hw
5185  *  pointer to ixgbe_hw struct
5186  * @direction
5187  *  0 for Rx, 1 for Tx, -1 for other causes
5188  * @queue
5189  *  queue to map the corresponding interrupt to
5190  * @msix_vector
5191  *  the vector to map to the corresponding queue
5192  */
5193 static void
5194 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5195                    uint8_t queue, uint8_t msix_vector)
5196 {
5197         uint32_t tmp, idx;
5198
5199         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5200         if (hw->mac.type == ixgbe_mac_82598EB) {
5201                 if (direction == -1)
5202                         direction = 0;
5203                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5204                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5205                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5206                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5207                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5208         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5209                         (hw->mac.type == ixgbe_mac_X540)) {
5210                 if (direction == -1) {
5211                         /* other causes */
5212                         idx = ((queue & 1) * 8);
5213                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5214                         tmp &= ~(0xFF << idx);
5215                         tmp |= (msix_vector << idx);
5216                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5217                 } else {
5218                         /* rx or tx causes */
5219                         idx = ((16 * (queue & 1)) + (8 * direction));
5220                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5221                         tmp &= ~(0xFF << idx);
5222                         tmp |= (msix_vector << idx);
5223                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5224                 }
5225         }
5226 }
5227
5228 static void
5229 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5230 {
5231         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5232         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5233         struct ixgbe_hw *hw =
5234                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5235         uint32_t q_idx;
5236         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5237
5238         /* Configure VF other cause ivar */
5239         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5240
5241         /* won't configure msix register if no mapping is done
5242          * between intr vector and event fd.
5243          */
5244         if (!rte_intr_dp_is_en(intr_handle))
5245                 return;
5246
5247         /* Configure all RX queues of VF */
5248         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5249                 /* Force all queue use vector 0,
5250                  * as IXGBE_VF_MAXMSIVECOTR = 1
5251                  */
5252                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5253                 intr_handle->intr_vec[q_idx] = vector_idx;
5254         }
5255 }
5256
5257 /**
5258  * Sets up the hardware to properly generate MSI-X interrupts
5259  * @hw
5260  *  board private structure
5261  */
5262 static void
5263 ixgbe_configure_msix(struct rte_eth_dev *dev)
5264 {
5265         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5266         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5267         struct ixgbe_hw *hw =
5268                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5269         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5270         uint32_t vec = IXGBE_MISC_VEC_ID;
5271         uint32_t mask;
5272         uint32_t gpie;
5273
5274         /* won't configure msix register if no mapping is done
5275          * between intr vector and event fd
5276          */
5277         if (!rte_intr_dp_is_en(intr_handle))
5278                 return;
5279
5280         if (rte_intr_allow_others(intr_handle))
5281                 vec = base = IXGBE_RX_VEC_START;
5282
5283         /* setup GPIE for MSI-x mode */
5284         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5285         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5286                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5287         /* auto clearing and auto setting corresponding bits in EIMS
5288          * when MSI-X interrupt is triggered
5289          */
5290         if (hw->mac.type == ixgbe_mac_82598EB) {
5291                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5292         } else {
5293                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5294                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5295         }
5296         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5297
5298         /* Populate the IVAR table and set the ITR values to the
5299          * corresponding register.
5300          */
5301         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5302              queue_id++) {
5303                 /* by default, 1:1 mapping */
5304                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5305                 intr_handle->intr_vec[queue_id] = vec;
5306                 if (vec < base + intr_handle->nb_efd - 1)
5307                         vec++;
5308         }
5309
5310         switch (hw->mac.type) {
5311         case ixgbe_mac_82598EB:
5312                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5313                                    IXGBE_MISC_VEC_ID);
5314                 break;
5315         case ixgbe_mac_82599EB:
5316         case ixgbe_mac_X540:
5317                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5318                 break;
5319         default:
5320                 break;
5321         }
5322         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5323                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5324
5325         /* set up to autoclear timer, and the vectors */
5326         mask = IXGBE_EIMS_ENABLE_MASK;
5327         mask &= ~(IXGBE_EIMS_OTHER |
5328                   IXGBE_EIMS_MAILBOX |
5329                   IXGBE_EIMS_LSC);
5330
5331         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5332 }
5333
5334 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5335         uint16_t queue_idx, uint16_t tx_rate)
5336 {
5337         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5338         uint32_t rf_dec, rf_int;
5339         uint32_t bcnrc_val;
5340         uint16_t link_speed = dev->data->dev_link.link_speed;
5341
5342         if (queue_idx >= hw->mac.max_tx_queues)
5343                 return -EINVAL;
5344
5345         if (tx_rate != 0) {
5346                 /* Calculate the rate factor values to set */
5347                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5348                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5349                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5350
5351                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5352                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5353                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5354                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5355         } else {
5356                 bcnrc_val = 0;
5357         }
5358
5359         /*
5360          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5361          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5362          * set as 0x4.
5363          */
5364         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5365                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5366                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5367                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5368                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5369         else
5370                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5371                         IXGBE_MMW_SIZE_DEFAULT);
5372
5373         /* Set RTTBCNRC of queue X */
5374         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5375         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5376         IXGBE_WRITE_FLUSH(hw);
5377
5378         return 0;
5379 }
5380
5381 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5382         uint16_t tx_rate, uint64_t q_msk)
5383 {
5384         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5385         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5386         struct ixgbe_vf_info *vfinfo =
5387                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5388         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5389         uint32_t queue_stride =
5390                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5391         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5392         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5393         uint16_t total_rate = 0;
5394
5395         if (queue_end >= hw->mac.max_tx_queues)
5396                 return -EINVAL;
5397
5398         if (vfinfo != NULL) {
5399                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5400                         if (vf_idx == vf)
5401                                 continue;
5402                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5403                                 idx++)
5404                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5405                 }
5406         } else
5407                 return -EINVAL;
5408
5409         /* Store tx_rate for this vf. */
5410         for (idx = 0; idx < nb_q_per_pool; idx++) {
5411                 if (((uint64_t)0x1 << idx) & q_msk) {
5412                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5413                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5414                         total_rate += tx_rate;
5415                 }
5416         }
5417
5418         if (total_rate > dev->data->dev_link.link_speed) {
5419                 /*
5420                  * Reset stored TX rate of the VF if it causes exceed
5421                  * link speed.
5422                  */
5423                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5424                 return -EINVAL;
5425         }
5426
5427         /* Set RTTBCNRC of each queue/pool for vf X  */
5428         for (; queue_idx <= queue_end; queue_idx++) {
5429                 if (0x1 & q_msk)
5430                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5431                 q_msk = q_msk >> 1;
5432         }
5433
5434         return 0;
5435 }
5436
5437 static void
5438 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5439                      __attribute__((unused)) uint32_t index,
5440                      __attribute__((unused)) uint32_t pool)
5441 {
5442         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5443         int diag;
5444
5445         /*
5446          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5447          * operation. Trap this case to avoid exhausting the [very limited]
5448          * set of PF resources used to store VF MAC addresses.
5449          */
5450         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5451                 return;
5452         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5453         if (diag == 0)
5454                 return;
5455         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5456 }
5457
5458 static void
5459 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5460 {
5461         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5462         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5463         struct ether_addr *mac_addr;
5464         uint32_t i;
5465         int diag;
5466
5467         /*
5468          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5469          * not support the deletion of a given MAC address.
5470          * Instead, it imposes to delete all MAC addresses, then to add again
5471          * all MAC addresses with the exception of the one to be deleted.
5472          */
5473         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5474
5475         /*
5476          * Add again all MAC addresses, with the exception of the deleted one
5477          * and of the permanent MAC address.
5478          */
5479         for (i = 0, mac_addr = dev->data->mac_addrs;
5480              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5481                 /* Skip the deleted MAC address */
5482                 if (i == index)
5483                         continue;
5484                 /* Skip NULL MAC addresses */
5485                 if (is_zero_ether_addr(mac_addr))
5486                         continue;
5487                 /* Skip the permanent MAC address */
5488                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5489                         continue;
5490                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5491                 if (diag != 0)
5492                         PMD_DRV_LOG(ERR,
5493                                     "Adding again MAC address "
5494                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5495                                     "diag=%d",
5496                                     mac_addr->addr_bytes[0],
5497                                     mac_addr->addr_bytes[1],
5498                                     mac_addr->addr_bytes[2],
5499                                     mac_addr->addr_bytes[3],
5500                                     mac_addr->addr_bytes[4],
5501                                     mac_addr->addr_bytes[5],
5502                                     diag);
5503         }
5504 }
5505
5506 static void
5507 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5508 {
5509         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5510
5511         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5512 }
5513
5514 #define MAC_TYPE_FILTER_SUP(type)    do {\
5515         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5516                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5517                 (type) != ixgbe_mac_X550EM_a)\
5518                 return -ENOTSUP;\
5519 } while (0)
5520
5521 static int
5522 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5523                         struct rte_eth_syn_filter *filter,
5524                         bool add)
5525 {
5526         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5527         uint32_t synqf;
5528
5529         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5530                 return -EINVAL;
5531
5532         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5533
5534         if (add) {
5535                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5536                         return -EINVAL;
5537                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5538                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5539
5540                 if (filter->hig_pri)
5541                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5542                 else
5543                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5544         } else {
5545                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5546                         return -ENOENT;
5547                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5548         }
5549         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5550         IXGBE_WRITE_FLUSH(hw);
5551         return 0;
5552 }
5553
5554 static int
5555 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5556                         struct rte_eth_syn_filter *filter)
5557 {
5558         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5559         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5560
5561         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5562                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5563                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5564                 return 0;
5565         }
5566         return -ENOENT;
5567 }
5568
5569 static int
5570 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5571                         enum rte_filter_op filter_op,
5572                         void *arg)
5573 {
5574         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5575         int ret;
5576
5577         MAC_TYPE_FILTER_SUP(hw->mac.type);
5578
5579         if (filter_op == RTE_ETH_FILTER_NOP)
5580                 return 0;
5581
5582         if (arg == NULL) {
5583                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5584                             filter_op);
5585                 return -EINVAL;
5586         }
5587
5588         switch (filter_op) {
5589         case RTE_ETH_FILTER_ADD:
5590                 ret = ixgbe_syn_filter_set(dev,
5591                                 (struct rte_eth_syn_filter *)arg,
5592                                 TRUE);
5593                 break;
5594         case RTE_ETH_FILTER_DELETE:
5595                 ret = ixgbe_syn_filter_set(dev,
5596                                 (struct rte_eth_syn_filter *)arg,
5597                                 FALSE);
5598                 break;
5599         case RTE_ETH_FILTER_GET:
5600                 ret = ixgbe_syn_filter_get(dev,
5601                                 (struct rte_eth_syn_filter *)arg);
5602                 break;
5603         default:
5604                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5605                 ret = -EINVAL;
5606                 break;
5607         }
5608
5609         return ret;
5610 }
5611
5612
5613 static inline enum ixgbe_5tuple_protocol
5614 convert_protocol_type(uint8_t protocol_value)
5615 {
5616         if (protocol_value == IPPROTO_TCP)
5617                 return IXGBE_FILTER_PROTOCOL_TCP;
5618         else if (protocol_value == IPPROTO_UDP)
5619                 return IXGBE_FILTER_PROTOCOL_UDP;
5620         else if (protocol_value == IPPROTO_SCTP)
5621                 return IXGBE_FILTER_PROTOCOL_SCTP;
5622         else
5623                 return IXGBE_FILTER_PROTOCOL_NONE;
5624 }
5625
5626 /*
5627  * add a 5tuple filter
5628  *
5629  * @param
5630  * dev: Pointer to struct rte_eth_dev.
5631  * index: the index the filter allocates.
5632  * filter: ponter to the filter that will be added.
5633  * rx_queue: the queue id the filter assigned to.
5634  *
5635  * @return
5636  *    - On success, zero.
5637  *    - On failure, a negative value.
5638  */
5639 static int
5640 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5641                         struct ixgbe_5tuple_filter *filter)
5642 {
5643         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5644         struct ixgbe_filter_info *filter_info =
5645                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5646         int i, idx, shift;
5647         uint32_t ftqf, sdpqf;
5648         uint32_t l34timir = 0;
5649         uint8_t mask = 0xff;
5650
5651         /*
5652          * look for an unused 5tuple filter index,
5653          * and insert the filter to list.
5654          */
5655         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5656                 idx = i / (sizeof(uint32_t) * NBBY);
5657                 shift = i % (sizeof(uint32_t) * NBBY);
5658                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5659                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5660                         filter->index = i;
5661                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5662                                           filter,
5663                                           entries);
5664                         break;
5665                 }
5666         }
5667         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5668                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5669                 return -ENOSYS;
5670         }
5671
5672         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5673                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5674         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5675
5676         ftqf = (uint32_t)(filter->filter_info.proto &
5677                 IXGBE_FTQF_PROTOCOL_MASK);
5678         ftqf |= (uint32_t)((filter->filter_info.priority &
5679                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5680         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5681                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5682         if (filter->filter_info.dst_ip_mask == 0)
5683                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5684         if (filter->filter_info.src_port_mask == 0)
5685                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5686         if (filter->filter_info.dst_port_mask == 0)
5687                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5688         if (filter->filter_info.proto_mask == 0)
5689                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5690         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5691         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5692         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5693
5694         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5695         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5696         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5697         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5698
5699         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5700         l34timir |= (uint32_t)(filter->queue <<
5701                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5702         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5703         return 0;
5704 }
5705
5706 /*
5707  * remove a 5tuple filter
5708  *
5709  * @param
5710  * dev: Pointer to struct rte_eth_dev.
5711  * filter: the pointer of the filter will be removed.
5712  */
5713 static void
5714 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5715                         struct ixgbe_5tuple_filter *filter)
5716 {
5717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5718         struct ixgbe_filter_info *filter_info =
5719                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5720         uint16_t index = filter->index;
5721
5722         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5723                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5724         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5725         rte_free(filter);
5726
5727         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5728         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5729         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5730         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5731         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5732 }
5733
5734 static int
5735 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5736 {
5737         struct ixgbe_hw *hw;
5738         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5739
5740         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5741
5742         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5743                 return -EINVAL;
5744
5745         /* refuse mtu that requires the support of scattered packets when this
5746          * feature has not been enabled before.
5747          */
5748         if (!dev->data->scattered_rx &&
5749             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5750              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5751                 return -EINVAL;
5752
5753         /*
5754          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5755          * request of the version 2.0 of the mailbox API.
5756          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5757          * of the mailbox API.
5758          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5759          * prior to 3.11.33 which contains the following change:
5760          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5761          */
5762         ixgbevf_rlpml_set_vf(hw, max_frame);
5763
5764         /* update max frame size */
5765         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5766         return 0;
5767 }
5768
5769 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5770         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5771                 return -ENOTSUP;\
5772 } while (0)
5773
5774 static inline struct ixgbe_5tuple_filter *
5775 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5776                         struct ixgbe_5tuple_filter_info *key)
5777 {
5778         struct ixgbe_5tuple_filter *it;
5779
5780         TAILQ_FOREACH(it, filter_list, entries) {
5781                 if (memcmp(key, &it->filter_info,
5782                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5783                         return it;
5784                 }
5785         }
5786         return NULL;
5787 }
5788
5789 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5790 static inline int
5791 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5792                         struct ixgbe_5tuple_filter_info *filter_info)
5793 {
5794         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5795                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5796                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5797                 return -EINVAL;
5798
5799         switch (filter->dst_ip_mask) {
5800         case UINT32_MAX:
5801                 filter_info->dst_ip_mask = 0;
5802                 filter_info->dst_ip = filter->dst_ip;
5803                 break;
5804         case 0:
5805                 filter_info->dst_ip_mask = 1;
5806                 break;
5807         default:
5808                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5809                 return -EINVAL;
5810         }
5811
5812         switch (filter->src_ip_mask) {
5813         case UINT32_MAX:
5814                 filter_info->src_ip_mask = 0;
5815                 filter_info->src_ip = filter->src_ip;
5816                 break;
5817         case 0:
5818                 filter_info->src_ip_mask = 1;
5819                 break;
5820         default:
5821                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5822                 return -EINVAL;
5823         }
5824
5825         switch (filter->dst_port_mask) {
5826         case UINT16_MAX:
5827                 filter_info->dst_port_mask = 0;
5828                 filter_info->dst_port = filter->dst_port;
5829                 break;
5830         case 0:
5831                 filter_info->dst_port_mask = 1;
5832                 break;
5833         default:
5834                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5835                 return -EINVAL;
5836         }
5837
5838         switch (filter->src_port_mask) {
5839         case UINT16_MAX:
5840                 filter_info->src_port_mask = 0;
5841                 filter_info->src_port = filter->src_port;
5842                 break;
5843         case 0:
5844                 filter_info->src_port_mask = 1;
5845                 break;
5846         default:
5847                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5848                 return -EINVAL;
5849         }
5850
5851         switch (filter->proto_mask) {
5852         case UINT8_MAX:
5853                 filter_info->proto_mask = 0;
5854                 filter_info->proto =
5855                         convert_protocol_type(filter->proto);
5856                 break;
5857         case 0:
5858                 filter_info->proto_mask = 1;
5859                 break;
5860         default:
5861                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5862                 return -EINVAL;
5863         }
5864
5865         filter_info->priority = (uint8_t)filter->priority;
5866         return 0;
5867 }
5868
5869 /*
5870  * add or delete a ntuple filter
5871  *
5872  * @param
5873  * dev: Pointer to struct rte_eth_dev.
5874  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5875  * add: if true, add filter, if false, remove filter
5876  *
5877  * @return
5878  *    - On success, zero.
5879  *    - On failure, a negative value.
5880  */
5881 static int
5882 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5883                         struct rte_eth_ntuple_filter *ntuple_filter,
5884                         bool add)
5885 {
5886         struct ixgbe_filter_info *filter_info =
5887                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5888         struct ixgbe_5tuple_filter_info filter_5tuple;
5889         struct ixgbe_5tuple_filter *filter;
5890         int ret;
5891
5892         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5893                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5894                 return -EINVAL;
5895         }
5896
5897         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5898         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5899         if (ret < 0)
5900                 return ret;
5901
5902         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5903                                          &filter_5tuple);
5904         if (filter != NULL && add) {
5905                 PMD_DRV_LOG(ERR, "filter exists.");
5906                 return -EEXIST;
5907         }
5908         if (filter == NULL && !add) {
5909                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5910                 return -ENOENT;
5911         }
5912
5913         if (add) {
5914                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5915                                 sizeof(struct ixgbe_5tuple_filter), 0);
5916                 if (filter == NULL)
5917                         return -ENOMEM;
5918                 (void)rte_memcpy(&filter->filter_info,
5919                                  &filter_5tuple,
5920                                  sizeof(struct ixgbe_5tuple_filter_info));
5921                 filter->queue = ntuple_filter->queue;
5922                 ret = ixgbe_add_5tuple_filter(dev, filter);
5923                 if (ret < 0) {
5924                         rte_free(filter);
5925                         return ret;
5926                 }
5927         } else
5928                 ixgbe_remove_5tuple_filter(dev, filter);
5929
5930         return 0;
5931 }
5932
5933 /*
5934  * get a ntuple filter
5935  *
5936  * @param
5937  * dev: Pointer to struct rte_eth_dev.
5938  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5939  *
5940  * @return
5941  *    - On success, zero.
5942  *    - On failure, a negative value.
5943  */
5944 static int
5945 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5946                         struct rte_eth_ntuple_filter *ntuple_filter)
5947 {
5948         struct ixgbe_filter_info *filter_info =
5949                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5950         struct ixgbe_5tuple_filter_info filter_5tuple;
5951         struct ixgbe_5tuple_filter *filter;
5952         int ret;
5953
5954         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5955                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5956                 return -EINVAL;
5957         }
5958
5959         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5960         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5961         if (ret < 0)
5962                 return ret;
5963
5964         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5965                                          &filter_5tuple);
5966         if (filter == NULL) {
5967                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5968                 return -ENOENT;
5969         }
5970         ntuple_filter->queue = filter->queue;
5971         return 0;
5972 }
5973
5974 /*
5975  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5976  * @dev: pointer to rte_eth_dev structure
5977  * @filter_op:operation will be taken.
5978  * @arg: a pointer to specific structure corresponding to the filter_op
5979  *
5980  * @return
5981  *    - On success, zero.
5982  *    - On failure, a negative value.
5983  */
5984 static int
5985 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5986                                 enum rte_filter_op filter_op,
5987                                 void *arg)
5988 {
5989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5990         int ret;
5991
5992         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5993
5994         if (filter_op == RTE_ETH_FILTER_NOP)
5995                 return 0;
5996
5997         if (arg == NULL) {
5998                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5999                             filter_op);
6000                 return -EINVAL;
6001         }
6002
6003         switch (filter_op) {
6004         case RTE_ETH_FILTER_ADD:
6005                 ret = ixgbe_add_del_ntuple_filter(dev,
6006                         (struct rte_eth_ntuple_filter *)arg,
6007                         TRUE);
6008                 break;
6009         case RTE_ETH_FILTER_DELETE:
6010                 ret = ixgbe_add_del_ntuple_filter(dev,
6011                         (struct rte_eth_ntuple_filter *)arg,
6012                         FALSE);
6013                 break;
6014         case RTE_ETH_FILTER_GET:
6015                 ret = ixgbe_get_ntuple_filter(dev,
6016                         (struct rte_eth_ntuple_filter *)arg);
6017                 break;
6018         default:
6019                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6020                 ret = -EINVAL;
6021                 break;
6022         }
6023         return ret;
6024 }
6025
6026 static inline int
6027 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6028                         uint16_t ethertype)
6029 {
6030         int i;
6031
6032         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6033                 if (filter_info->ethertype_filters[i] == ethertype &&
6034                     (filter_info->ethertype_mask & (1 << i)))
6035                         return i;
6036         }
6037         return -1;
6038 }
6039
6040 static inline int
6041 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6042                         uint16_t ethertype)
6043 {
6044         int i;
6045
6046         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6047                 if (!(filter_info->ethertype_mask & (1 << i))) {
6048                         filter_info->ethertype_mask |= 1 << i;
6049                         filter_info->ethertype_filters[i] = ethertype;
6050                         return i;
6051                 }
6052         }
6053         return -1;
6054 }
6055
6056 static inline int
6057 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6058                         uint8_t idx)
6059 {
6060         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6061                 return -1;
6062         filter_info->ethertype_mask &= ~(1 << idx);
6063         filter_info->ethertype_filters[idx] = 0;
6064         return idx;
6065 }
6066
6067 static int
6068 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6069                         struct rte_eth_ethertype_filter *filter,
6070                         bool add)
6071 {
6072         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6073         struct ixgbe_filter_info *filter_info =
6074                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6075         uint32_t etqf = 0;
6076         uint32_t etqs = 0;
6077         int ret;
6078
6079         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6080                 return -EINVAL;
6081
6082         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6083                 filter->ether_type == ETHER_TYPE_IPv6) {
6084                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6085                         " ethertype filter.", filter->ether_type);
6086                 return -EINVAL;
6087         }
6088
6089         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6090                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6091                 return -EINVAL;
6092         }
6093         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6094                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6095                 return -EINVAL;
6096         }
6097
6098         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6099         if (ret >= 0 && add) {
6100                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6101                             filter->ether_type);
6102                 return -EEXIST;
6103         }
6104         if (ret < 0 && !add) {
6105                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6106                             filter->ether_type);
6107                 return -ENOENT;
6108         }
6109
6110         if (add) {
6111                 ret = ixgbe_ethertype_filter_insert(filter_info,
6112                         filter->ether_type);
6113                 if (ret < 0) {
6114                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6115                         return -ENOSYS;
6116                 }
6117                 etqf = IXGBE_ETQF_FILTER_EN;
6118                 etqf |= (uint32_t)filter->ether_type;
6119                 etqs |= (uint32_t)((filter->queue <<
6120                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6121                                     IXGBE_ETQS_RX_QUEUE);
6122                 etqs |= IXGBE_ETQS_QUEUE_EN;
6123         } else {
6124                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6125                 if (ret < 0)
6126                         return -ENOSYS;
6127         }
6128         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6129         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6130         IXGBE_WRITE_FLUSH(hw);
6131
6132         return 0;
6133 }
6134
6135 static int
6136 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6137                         struct rte_eth_ethertype_filter *filter)
6138 {
6139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6140         struct ixgbe_filter_info *filter_info =
6141                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6142         uint32_t etqf, etqs;
6143         int ret;
6144
6145         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6146         if (ret < 0) {
6147                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6148                             filter->ether_type);
6149                 return -ENOENT;
6150         }
6151
6152         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6153         if (etqf & IXGBE_ETQF_FILTER_EN) {
6154                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6155                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6156                 filter->flags = 0;
6157                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6158                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6159                 return 0;
6160         }
6161         return -ENOENT;
6162 }
6163
6164 /*
6165  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6166  * @dev: pointer to rte_eth_dev structure
6167  * @filter_op:operation will be taken.
6168  * @arg: a pointer to specific structure corresponding to the filter_op
6169  */
6170 static int
6171 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6172                                 enum rte_filter_op filter_op,
6173                                 void *arg)
6174 {
6175         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6176         int ret;
6177
6178         MAC_TYPE_FILTER_SUP(hw->mac.type);
6179
6180         if (filter_op == RTE_ETH_FILTER_NOP)
6181                 return 0;
6182
6183         if (arg == NULL) {
6184                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6185                             filter_op);
6186                 return -EINVAL;
6187         }
6188
6189         switch (filter_op) {
6190         case RTE_ETH_FILTER_ADD:
6191                 ret = ixgbe_add_del_ethertype_filter(dev,
6192                         (struct rte_eth_ethertype_filter *)arg,
6193                         TRUE);
6194                 break;
6195         case RTE_ETH_FILTER_DELETE:
6196                 ret = ixgbe_add_del_ethertype_filter(dev,
6197                         (struct rte_eth_ethertype_filter *)arg,
6198                         FALSE);
6199                 break;
6200         case RTE_ETH_FILTER_GET:
6201                 ret = ixgbe_get_ethertype_filter(dev,
6202                         (struct rte_eth_ethertype_filter *)arg);
6203                 break;
6204         default:
6205                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6206                 ret = -EINVAL;
6207                 break;
6208         }
6209         return ret;
6210 }
6211
6212 static int
6213 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6214                      enum rte_filter_type filter_type,
6215                      enum rte_filter_op filter_op,
6216                      void *arg)
6217 {
6218         int ret = -EINVAL;
6219
6220         switch (filter_type) {
6221         case RTE_ETH_FILTER_NTUPLE:
6222                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6223                 break;
6224         case RTE_ETH_FILTER_ETHERTYPE:
6225                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6226                 break;
6227         case RTE_ETH_FILTER_SYN:
6228                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6229                 break;
6230         case RTE_ETH_FILTER_FDIR:
6231                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6232                 break;
6233         case RTE_ETH_FILTER_L2_TUNNEL:
6234                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6235                 break;
6236         default:
6237                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6238                                                         filter_type);
6239                 break;
6240         }
6241
6242         return ret;
6243 }
6244
6245 static u8 *
6246 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6247                         u8 **mc_addr_ptr, u32 *vmdq)
6248 {
6249         u8 *mc_addr;
6250
6251         *vmdq = 0;
6252         mc_addr = *mc_addr_ptr;
6253         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6254         return mc_addr;
6255 }
6256
6257 static int
6258 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6259                           struct ether_addr *mc_addr_set,
6260                           uint32_t nb_mc_addr)
6261 {
6262         struct ixgbe_hw *hw;
6263         u8 *mc_addr_list;
6264
6265         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6266         mc_addr_list = (u8 *)mc_addr_set;
6267         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6268                                          ixgbe_dev_addr_list_itr, TRUE);
6269 }
6270
6271 static uint64_t
6272 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6273 {
6274         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6275         uint64_t systime_cycles;
6276
6277         switch (hw->mac.type) {
6278         case ixgbe_mac_X550:
6279         case ixgbe_mac_X550EM_x:
6280         case ixgbe_mac_X550EM_a:
6281                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6282                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6283                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6284                                 * NSEC_PER_SEC;
6285                 break;
6286         default:
6287                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6288                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6289                                 << 32;
6290         }
6291
6292         return systime_cycles;
6293 }
6294
6295 static uint64_t
6296 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6297 {
6298         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6299         uint64_t rx_tstamp_cycles;
6300
6301         switch (hw->mac.type) {
6302         case ixgbe_mac_X550:
6303         case ixgbe_mac_X550EM_x:
6304         case ixgbe_mac_X550EM_a:
6305                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6306                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6307                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6308                                 * NSEC_PER_SEC;
6309                 break;
6310         default:
6311                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6312                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6313                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6314                                 << 32;
6315         }
6316
6317         return rx_tstamp_cycles;
6318 }
6319
6320 static uint64_t
6321 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6322 {
6323         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6324         uint64_t tx_tstamp_cycles;
6325
6326         switch (hw->mac.type) {
6327         case ixgbe_mac_X550:
6328         case ixgbe_mac_X550EM_x:
6329         case ixgbe_mac_X550EM_a:
6330                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6331                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6332                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6333                                 * NSEC_PER_SEC;
6334                 break;
6335         default:
6336                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6337                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6338                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6339                                 << 32;
6340         }
6341
6342         return tx_tstamp_cycles;
6343 }
6344
6345 static void
6346 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6347 {
6348         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6349         struct ixgbe_adapter *adapter =
6350                 (struct ixgbe_adapter *)dev->data->dev_private;
6351         struct rte_eth_link link;
6352         uint32_t incval = 0;
6353         uint32_t shift = 0;
6354
6355         /* Get current link speed. */
6356         memset(&link, 0, sizeof(link));
6357         ixgbe_dev_link_update(dev, 1);
6358         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6359
6360         switch (link.link_speed) {
6361         case ETH_SPEED_NUM_100M:
6362                 incval = IXGBE_INCVAL_100;
6363                 shift = IXGBE_INCVAL_SHIFT_100;
6364                 break;
6365         case ETH_SPEED_NUM_1G:
6366                 incval = IXGBE_INCVAL_1GB;
6367                 shift = IXGBE_INCVAL_SHIFT_1GB;
6368                 break;
6369         case ETH_SPEED_NUM_10G:
6370         default:
6371                 incval = IXGBE_INCVAL_10GB;
6372                 shift = IXGBE_INCVAL_SHIFT_10GB;
6373                 break;
6374         }
6375
6376         switch (hw->mac.type) {
6377         case ixgbe_mac_X550:
6378         case ixgbe_mac_X550EM_x:
6379         case ixgbe_mac_X550EM_a:
6380                 /* Independent of link speed. */
6381                 incval = 1;
6382                 /* Cycles read will be interpreted as ns. */
6383                 shift = 0;
6384                 /* Fall-through */
6385         case ixgbe_mac_X540:
6386                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6387                 break;
6388         case ixgbe_mac_82599EB:
6389                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6390                 shift -= IXGBE_INCVAL_SHIFT_82599;
6391                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6392                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6393                 break;
6394         default:
6395                 /* Not supported. */
6396                 return;
6397         }
6398
6399         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6400         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6401         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6402
6403         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6404         adapter->systime_tc.cc_shift = shift;
6405         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6406
6407         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6408         adapter->rx_tstamp_tc.cc_shift = shift;
6409         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6410
6411         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6412         adapter->tx_tstamp_tc.cc_shift = shift;
6413         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6414 }
6415
6416 static int
6417 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6418 {
6419         struct ixgbe_adapter *adapter =
6420                         (struct ixgbe_adapter *)dev->data->dev_private;
6421
6422         adapter->systime_tc.nsec += delta;
6423         adapter->rx_tstamp_tc.nsec += delta;
6424         adapter->tx_tstamp_tc.nsec += delta;
6425
6426         return 0;
6427 }
6428
6429 static int
6430 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6431 {
6432         uint64_t ns;
6433         struct ixgbe_adapter *adapter =
6434                         (struct ixgbe_adapter *)dev->data->dev_private;
6435
6436         ns = rte_timespec_to_ns(ts);
6437         /* Set the timecounters to a new value. */
6438         adapter->systime_tc.nsec = ns;
6439         adapter->rx_tstamp_tc.nsec = ns;
6440         adapter->tx_tstamp_tc.nsec = ns;
6441
6442         return 0;
6443 }
6444
6445 static int
6446 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6447 {
6448         uint64_t ns, systime_cycles;
6449         struct ixgbe_adapter *adapter =
6450                         (struct ixgbe_adapter *)dev->data->dev_private;
6451
6452         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6453         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6454         *ts = rte_ns_to_timespec(ns);
6455
6456         return 0;
6457 }
6458
6459 static int
6460 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6461 {
6462         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6463         uint32_t tsync_ctl;
6464         uint32_t tsauxc;
6465
6466         /* Stop the timesync system time. */
6467         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6468         /* Reset the timesync system time value. */
6469         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6470         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6471
6472         /* Enable system time for platforms where it isn't on by default. */
6473         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6474         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6475         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6476
6477         ixgbe_start_timecounters(dev);
6478
6479         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6480         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6481                         (ETHER_TYPE_1588 |
6482                          IXGBE_ETQF_FILTER_EN |
6483                          IXGBE_ETQF_1588));
6484
6485         /* Enable timestamping of received PTP packets. */
6486         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6487         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6488         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6489
6490         /* Enable timestamping of transmitted PTP packets. */
6491         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6492         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6493         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6494
6495         IXGBE_WRITE_FLUSH(hw);
6496
6497         return 0;
6498 }
6499
6500 static int
6501 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6502 {
6503         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6504         uint32_t tsync_ctl;
6505
6506         /* Disable timestamping of transmitted PTP packets. */
6507         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6508         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6509         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6510
6511         /* Disable timestamping of received PTP packets. */
6512         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6513         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6514         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6515
6516         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6517         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6518
6519         /* Stop incrementating the System Time registers. */
6520         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6521
6522         return 0;
6523 }
6524
6525 static int
6526 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6527                                  struct timespec *timestamp,
6528                                  uint32_t flags __rte_unused)
6529 {
6530         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6531         struct ixgbe_adapter *adapter =
6532                 (struct ixgbe_adapter *)dev->data->dev_private;
6533         uint32_t tsync_rxctl;
6534         uint64_t rx_tstamp_cycles;
6535         uint64_t ns;
6536
6537         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6538         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6539                 return -EINVAL;
6540
6541         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6542         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6543         *timestamp = rte_ns_to_timespec(ns);
6544
6545         return  0;
6546 }
6547
6548 static int
6549 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6550                                  struct timespec *timestamp)
6551 {
6552         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6553         struct ixgbe_adapter *adapter =
6554                 (struct ixgbe_adapter *)dev->data->dev_private;
6555         uint32_t tsync_txctl;
6556         uint64_t tx_tstamp_cycles;
6557         uint64_t ns;
6558
6559         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6560         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6561                 return -EINVAL;
6562
6563         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6564         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6565         *timestamp = rte_ns_to_timespec(ns);
6566
6567         return 0;
6568 }
6569
6570 static int
6571 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6572 {
6573         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6574         int count = 0;
6575         int g_ind = 0;
6576         const struct reg_info *reg_group;
6577         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6578                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6579
6580         while ((reg_group = reg_set[g_ind++]))
6581                 count += ixgbe_regs_group_count(reg_group);
6582
6583         return count;
6584 }
6585
6586 static int
6587 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6588 {
6589         int count = 0;
6590         int g_ind = 0;
6591         const struct reg_info *reg_group;
6592
6593         while ((reg_group = ixgbevf_regs[g_ind++]))
6594                 count += ixgbe_regs_group_count(reg_group);
6595
6596         return count;
6597 }
6598
6599 static int
6600 ixgbe_get_regs(struct rte_eth_dev *dev,
6601               struct rte_dev_reg_info *regs)
6602 {
6603         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6604         uint32_t *data = regs->data;
6605         int g_ind = 0;
6606         int count = 0;
6607         const struct reg_info *reg_group;
6608         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6609                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6610
6611         if (data == NULL) {
6612                 regs->length = ixgbe_get_reg_length(dev);
6613                 regs->width = sizeof(uint32_t);
6614                 return 0;
6615         }
6616
6617         /* Support only full register dump */
6618         if ((regs->length == 0) ||
6619             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6620                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6621                         hw->device_id;
6622                 while ((reg_group = reg_set[g_ind++]))
6623                         count += ixgbe_read_regs_group(dev, &data[count],
6624                                 reg_group);
6625                 return 0;
6626         }
6627
6628         return -ENOTSUP;
6629 }
6630
6631 static int
6632 ixgbevf_get_regs(struct rte_eth_dev *dev,
6633                 struct rte_dev_reg_info *regs)
6634 {
6635         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6636         uint32_t *data = regs->data;
6637         int g_ind = 0;
6638         int count = 0;
6639         const struct reg_info *reg_group;
6640
6641         if (data == NULL) {
6642                 regs->length = ixgbevf_get_reg_length(dev);
6643                 regs->width = sizeof(uint32_t);
6644                 return 0;
6645         }
6646
6647         /* Support only full register dump */
6648         if ((regs->length == 0) ||
6649             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6650                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6651                         hw->device_id;
6652                 while ((reg_group = ixgbevf_regs[g_ind++]))
6653                         count += ixgbe_read_regs_group(dev, &data[count],
6654                                                       reg_group);
6655                 return 0;
6656         }
6657
6658         return -ENOTSUP;
6659 }
6660
6661 static int
6662 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6663 {
6664         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6665
6666         /* Return unit is byte count */
6667         return hw->eeprom.word_size * 2;
6668 }
6669
6670 static int
6671 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6672                 struct rte_dev_eeprom_info *in_eeprom)
6673 {
6674         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6675         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6676         uint16_t *data = in_eeprom->data;
6677         int first, length;
6678
6679         first = in_eeprom->offset >> 1;
6680         length = in_eeprom->length >> 1;
6681         if ((first > hw->eeprom.word_size) ||
6682             ((first + length) > hw->eeprom.word_size))
6683                 return -EINVAL;
6684
6685         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6686
6687         return eeprom->ops.read_buffer(hw, first, length, data);
6688 }
6689
6690 static int
6691 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6692                 struct rte_dev_eeprom_info *in_eeprom)
6693 {
6694         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6695         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6696         uint16_t *data = in_eeprom->data;
6697         int first, length;
6698
6699         first = in_eeprom->offset >> 1;
6700         length = in_eeprom->length >> 1;
6701         if ((first > hw->eeprom.word_size) ||
6702             ((first + length) > hw->eeprom.word_size))
6703                 return -EINVAL;
6704
6705         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6706
6707         return eeprom->ops.write_buffer(hw,  first, length, data);
6708 }
6709
6710 uint16_t
6711 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6712         switch (mac_type) {
6713         case ixgbe_mac_X550:
6714         case ixgbe_mac_X550EM_x:
6715         case ixgbe_mac_X550EM_a:
6716                 return ETH_RSS_RETA_SIZE_512;
6717         case ixgbe_mac_X550_vf:
6718         case ixgbe_mac_X550EM_x_vf:
6719         case ixgbe_mac_X550EM_a_vf:
6720                 return ETH_RSS_RETA_SIZE_64;
6721         default:
6722                 return ETH_RSS_RETA_SIZE_128;
6723         }
6724 }
6725
6726 uint32_t
6727 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6728         switch (mac_type) {
6729         case ixgbe_mac_X550:
6730         case ixgbe_mac_X550EM_x:
6731         case ixgbe_mac_X550EM_a:
6732                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6733                         return IXGBE_RETA(reta_idx >> 2);
6734                 else
6735                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6736         case ixgbe_mac_X550_vf:
6737         case ixgbe_mac_X550EM_x_vf:
6738         case ixgbe_mac_X550EM_a_vf:
6739                 return IXGBE_VFRETA(reta_idx >> 2);
6740         default:
6741                 return IXGBE_RETA(reta_idx >> 2);
6742         }
6743 }
6744
6745 uint32_t
6746 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6747         switch (mac_type) {
6748         case ixgbe_mac_X550_vf:
6749         case ixgbe_mac_X550EM_x_vf:
6750         case ixgbe_mac_X550EM_a_vf:
6751                 return IXGBE_VFMRQC;
6752         default:
6753                 return IXGBE_MRQC;
6754         }
6755 }
6756
6757 uint32_t
6758 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6759         switch (mac_type) {
6760         case ixgbe_mac_X550_vf:
6761         case ixgbe_mac_X550EM_x_vf:
6762         case ixgbe_mac_X550EM_a_vf:
6763                 return IXGBE_VFRSSRK(i);
6764         default:
6765                 return IXGBE_RSSRK(i);
6766         }
6767 }
6768
6769 bool
6770 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6771         switch (mac_type) {
6772         case ixgbe_mac_82599_vf:
6773         case ixgbe_mac_X540_vf:
6774                 return 0;
6775         default:
6776                 return 1;
6777         }
6778 }
6779
6780 static int
6781 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6782                         struct rte_eth_dcb_info *dcb_info)
6783 {
6784         struct ixgbe_dcb_config *dcb_config =
6785                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6786         struct ixgbe_dcb_tc_config *tc;
6787         uint8_t i, j;
6788
6789         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6790                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6791         else
6792                 dcb_info->nb_tcs = 1;
6793
6794         if (dcb_config->vt_mode) { /* vt is enabled*/
6795                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6796                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6797                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6798                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6799                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6800                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6801                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6802                                                 i * dcb_info->nb_tcs + j;
6803                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6804                                 dcb_info->tc_queue.tc_txq[i][j].base =
6805                                                 i * dcb_info->nb_tcs + j;
6806                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6807                         }
6808                 }
6809         } else { /* vt is disabled*/
6810                 struct rte_eth_dcb_rx_conf *rx_conf =
6811                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6812                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6813                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6814                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6815                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6816                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6817                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6818                         }
6819                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6820                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6821                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6822                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6823                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6824                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6825                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6826                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6827                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6828                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6829                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6830                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6831                         }
6832                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6833                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6834                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6835                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6836                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6837                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6838                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6839                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6840                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6841                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6842                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6843                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6844                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6845                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6846                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6847                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6848                 }
6849         }
6850         for (i = 0; i < dcb_info->nb_tcs; i++) {
6851                 tc = &dcb_config->tc_config[i];
6852                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6853         }
6854         return 0;
6855 }
6856
6857 /* Update e-tag ether type */
6858 static int
6859 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6860                             uint16_t ether_type)
6861 {
6862         uint32_t etag_etype;
6863
6864         if (hw->mac.type != ixgbe_mac_X550 &&
6865             hw->mac.type != ixgbe_mac_X550EM_x &&
6866             hw->mac.type != ixgbe_mac_X550EM_a) {
6867                 return -ENOTSUP;
6868         }
6869
6870         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6871         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6872         etag_etype |= ether_type;
6873         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6874         IXGBE_WRITE_FLUSH(hw);
6875
6876         return 0;
6877 }
6878
6879 /* Config l2 tunnel ether type */
6880 static int
6881 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6882                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6883 {
6884         int ret = 0;
6885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6886
6887         if (l2_tunnel == NULL)
6888                 return -EINVAL;
6889
6890         switch (l2_tunnel->l2_tunnel_type) {
6891         case RTE_L2_TUNNEL_TYPE_E_TAG:
6892                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6893                 break;
6894         default:
6895                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6896                 ret = -EINVAL;
6897                 break;
6898         }
6899
6900         return ret;
6901 }
6902
6903 /* Enable e-tag tunnel */
6904 static int
6905 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6906 {
6907         uint32_t etag_etype;
6908
6909         if (hw->mac.type != ixgbe_mac_X550 &&
6910             hw->mac.type != ixgbe_mac_X550EM_x &&
6911             hw->mac.type != ixgbe_mac_X550EM_a) {
6912                 return -ENOTSUP;
6913         }
6914
6915         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6916         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6917         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6918         IXGBE_WRITE_FLUSH(hw);
6919
6920         return 0;
6921 }
6922
6923 /* Enable l2 tunnel */
6924 static int
6925 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6926                            enum rte_eth_tunnel_type l2_tunnel_type)
6927 {
6928         int ret = 0;
6929         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6930
6931         switch (l2_tunnel_type) {
6932         case RTE_L2_TUNNEL_TYPE_E_TAG:
6933                 ret = ixgbe_e_tag_enable(hw);
6934                 break;
6935         default:
6936                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6937                 ret = -EINVAL;
6938                 break;
6939         }
6940
6941         return ret;
6942 }
6943
6944 /* Disable e-tag tunnel */
6945 static int
6946 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6947 {
6948         uint32_t etag_etype;
6949
6950         if (hw->mac.type != ixgbe_mac_X550 &&
6951             hw->mac.type != ixgbe_mac_X550EM_x &&
6952             hw->mac.type != ixgbe_mac_X550EM_a) {
6953                 return -ENOTSUP;
6954         }
6955
6956         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6957         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6958         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6959         IXGBE_WRITE_FLUSH(hw);
6960
6961         return 0;
6962 }
6963
6964 /* Disable l2 tunnel */
6965 static int
6966 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6967                             enum rte_eth_tunnel_type l2_tunnel_type)
6968 {
6969         int ret = 0;
6970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6971
6972         switch (l2_tunnel_type) {
6973         case RTE_L2_TUNNEL_TYPE_E_TAG:
6974                 ret = ixgbe_e_tag_disable(hw);
6975                 break;
6976         default:
6977                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6978                 ret = -EINVAL;
6979                 break;
6980         }
6981
6982         return ret;
6983 }
6984
6985 static int
6986 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6987                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6988 {
6989         int ret = 0;
6990         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6991         uint32_t i, rar_entries;
6992         uint32_t rar_low, rar_high;
6993
6994         if (hw->mac.type != ixgbe_mac_X550 &&
6995             hw->mac.type != ixgbe_mac_X550EM_x &&
6996             hw->mac.type != ixgbe_mac_X550EM_a) {
6997                 return -ENOTSUP;
6998         }
6999
7000         rar_entries = ixgbe_get_num_rx_addrs(hw);
7001
7002         for (i = 1; i < rar_entries; i++) {
7003                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7004                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7005                 if ((rar_high & IXGBE_RAH_AV) &&
7006                     (rar_high & IXGBE_RAH_ADTYPE) &&
7007                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7008                      l2_tunnel->tunnel_id)) {
7009                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7010                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7011
7012                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7013
7014                         return ret;
7015                 }
7016         }
7017
7018         return ret;
7019 }
7020
7021 static int
7022 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7023                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7024 {
7025         int ret = 0;
7026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7027         uint32_t i, rar_entries;
7028         uint32_t rar_low, rar_high;
7029
7030         if (hw->mac.type != ixgbe_mac_X550 &&
7031             hw->mac.type != ixgbe_mac_X550EM_x &&
7032             hw->mac.type != ixgbe_mac_X550EM_a) {
7033                 return -ENOTSUP;
7034         }
7035
7036         /* One entry for one tunnel. Try to remove potential existing entry. */
7037         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7038
7039         rar_entries = ixgbe_get_num_rx_addrs(hw);
7040
7041         for (i = 1; i < rar_entries; i++) {
7042                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7043                 if (rar_high & IXGBE_RAH_AV) {
7044                         continue;
7045                 } else {
7046                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7047                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7048                         rar_low = l2_tunnel->tunnel_id;
7049
7050                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7051                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7052
7053                         return ret;
7054                 }
7055         }
7056
7057         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7058                      " Please remove a rule before adding a new one.");
7059         return -EINVAL;
7060 }
7061
7062 /* Add l2 tunnel filter */
7063 static int
7064 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7065                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7066 {
7067         int ret = 0;
7068
7069         switch (l2_tunnel->l2_tunnel_type) {
7070         case RTE_L2_TUNNEL_TYPE_E_TAG:
7071                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7072                 break;
7073         default:
7074                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7075                 ret = -EINVAL;
7076                 break;
7077         }
7078
7079         return ret;
7080 }
7081
7082 /* Delete l2 tunnel filter */
7083 static int
7084 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7085                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7086 {
7087         int ret = 0;
7088
7089         switch (l2_tunnel->l2_tunnel_type) {
7090         case RTE_L2_TUNNEL_TYPE_E_TAG:
7091                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7092                 break;
7093         default:
7094                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7095                 ret = -EINVAL;
7096                 break;
7097         }
7098
7099         return ret;
7100 }
7101
7102 /**
7103  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7104  * @dev: pointer to rte_eth_dev structure
7105  * @filter_op:operation will be taken.
7106  * @arg: a pointer to specific structure corresponding to the filter_op
7107  */
7108 static int
7109 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7110                                   enum rte_filter_op filter_op,
7111                                   void *arg)
7112 {
7113         int ret = 0;
7114
7115         if (filter_op == RTE_ETH_FILTER_NOP)
7116                 return 0;
7117
7118         if (arg == NULL) {
7119                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7120                             filter_op);
7121                 return -EINVAL;
7122         }
7123
7124         switch (filter_op) {
7125         case RTE_ETH_FILTER_ADD:
7126                 ret = ixgbe_dev_l2_tunnel_filter_add
7127                         (dev,
7128                          (struct rte_eth_l2_tunnel_conf *)arg);
7129                 break;
7130         case RTE_ETH_FILTER_DELETE:
7131                 ret = ixgbe_dev_l2_tunnel_filter_del
7132                         (dev,
7133                          (struct rte_eth_l2_tunnel_conf *)arg);
7134                 break;
7135         default:
7136                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7137                 ret = -EINVAL;
7138                 break;
7139         }
7140         return ret;
7141 }
7142
7143 static int
7144 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7145 {
7146         int ret = 0;
7147         uint32_t ctrl;
7148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7149
7150         if (hw->mac.type != ixgbe_mac_X550 &&
7151             hw->mac.type != ixgbe_mac_X550EM_x &&
7152             hw->mac.type != ixgbe_mac_X550EM_a) {
7153                 return -ENOTSUP;
7154         }
7155
7156         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7157         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7158         if (en)
7159                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7160         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7161
7162         return ret;
7163 }
7164
7165 /* Enable l2 tunnel forwarding */
7166 static int
7167 ixgbe_dev_l2_tunnel_forwarding_enable
7168         (struct rte_eth_dev *dev,
7169          enum rte_eth_tunnel_type l2_tunnel_type)
7170 {
7171         int ret = 0;
7172
7173         switch (l2_tunnel_type) {
7174         case RTE_L2_TUNNEL_TYPE_E_TAG:
7175                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7176                 break;
7177         default:
7178                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7179                 ret = -EINVAL;
7180                 break;
7181         }
7182
7183         return ret;
7184 }
7185
7186 /* Disable l2 tunnel forwarding */
7187 static int
7188 ixgbe_dev_l2_tunnel_forwarding_disable
7189         (struct rte_eth_dev *dev,
7190          enum rte_eth_tunnel_type l2_tunnel_type)
7191 {
7192         int ret = 0;
7193
7194         switch (l2_tunnel_type) {
7195         case RTE_L2_TUNNEL_TYPE_E_TAG:
7196                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7197                 break;
7198         default:
7199                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7200                 ret = -EINVAL;
7201                 break;
7202         }
7203
7204         return ret;
7205 }
7206
7207 static int
7208 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7209                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7210                              bool en)
7211 {
7212         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7213         int ret = 0;
7214         uint32_t vmtir, vmvir;
7215         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7216
7217         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7218                 PMD_DRV_LOG(ERR,
7219                             "VF id %u should be less than %u",
7220                             l2_tunnel->vf_id,
7221                             pci_dev->max_vfs);
7222                 return -EINVAL;
7223         }
7224
7225         if (hw->mac.type != ixgbe_mac_X550 &&
7226             hw->mac.type != ixgbe_mac_X550EM_x &&
7227             hw->mac.type != ixgbe_mac_X550EM_a) {
7228                 return -ENOTSUP;
7229         }
7230
7231         if (en)
7232                 vmtir = l2_tunnel->tunnel_id;
7233         else
7234                 vmtir = 0;
7235
7236         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7237
7238         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7239         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7240         if (en)
7241                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7242         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7243
7244         return ret;
7245 }
7246
7247 /* Enable l2 tunnel tag insertion */
7248 static int
7249 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7250                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7251 {
7252         int ret = 0;
7253
7254         switch (l2_tunnel->l2_tunnel_type) {
7255         case RTE_L2_TUNNEL_TYPE_E_TAG:
7256                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7257                 break;
7258         default:
7259                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7260                 ret = -EINVAL;
7261                 break;
7262         }
7263
7264         return ret;
7265 }
7266
7267 /* Disable l2 tunnel tag insertion */
7268 static int
7269 ixgbe_dev_l2_tunnel_insertion_disable
7270         (struct rte_eth_dev *dev,
7271          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7272 {
7273         int ret = 0;
7274
7275         switch (l2_tunnel->l2_tunnel_type) {
7276         case RTE_L2_TUNNEL_TYPE_E_TAG:
7277                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7278                 break;
7279         default:
7280                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7281                 ret = -EINVAL;
7282                 break;
7283         }
7284
7285         return ret;
7286 }
7287
7288 static int
7289 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7290                              bool en)
7291 {
7292         int ret = 0;
7293         uint32_t qde;
7294         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7295
7296         if (hw->mac.type != ixgbe_mac_X550 &&
7297             hw->mac.type != ixgbe_mac_X550EM_x &&
7298             hw->mac.type != ixgbe_mac_X550EM_a) {
7299                 return -ENOTSUP;
7300         }
7301
7302         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7303         if (en)
7304                 qde |= IXGBE_QDE_STRIP_TAG;
7305         else
7306                 qde &= ~IXGBE_QDE_STRIP_TAG;
7307         qde &= ~IXGBE_QDE_READ;
7308         qde |= IXGBE_QDE_WRITE;
7309         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7310
7311         return ret;
7312 }
7313
7314 /* Enable l2 tunnel tag stripping */
7315 static int
7316 ixgbe_dev_l2_tunnel_stripping_enable
7317         (struct rte_eth_dev *dev,
7318          enum rte_eth_tunnel_type l2_tunnel_type)
7319 {
7320         int ret = 0;
7321
7322         switch (l2_tunnel_type) {
7323         case RTE_L2_TUNNEL_TYPE_E_TAG:
7324                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7325                 break;
7326         default:
7327                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7328                 ret = -EINVAL;
7329                 break;
7330         }
7331
7332         return ret;
7333 }
7334
7335 /* Disable l2 tunnel tag stripping */
7336 static int
7337 ixgbe_dev_l2_tunnel_stripping_disable
7338         (struct rte_eth_dev *dev,
7339          enum rte_eth_tunnel_type l2_tunnel_type)
7340 {
7341         int ret = 0;
7342
7343         switch (l2_tunnel_type) {
7344         case RTE_L2_TUNNEL_TYPE_E_TAG:
7345                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7346                 break;
7347         default:
7348                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7349                 ret = -EINVAL;
7350                 break;
7351         }
7352
7353         return ret;
7354 }
7355
7356 /* Enable/disable l2 tunnel offload functions */
7357 static int
7358 ixgbe_dev_l2_tunnel_offload_set
7359         (struct rte_eth_dev *dev,
7360          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7361          uint32_t mask,
7362          uint8_t en)
7363 {
7364         int ret = 0;
7365
7366         if (l2_tunnel == NULL)
7367                 return -EINVAL;
7368
7369         ret = -EINVAL;
7370         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7371                 if (en)
7372                         ret = ixgbe_dev_l2_tunnel_enable(
7373                                 dev,
7374                                 l2_tunnel->l2_tunnel_type);
7375                 else
7376                         ret = ixgbe_dev_l2_tunnel_disable(
7377                                 dev,
7378                                 l2_tunnel->l2_tunnel_type);
7379         }
7380
7381         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7382                 if (en)
7383                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7384                                 dev,
7385                                 l2_tunnel);
7386                 else
7387                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7388                                 dev,
7389                                 l2_tunnel);
7390         }
7391
7392         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7393                 if (en)
7394                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7395                                 dev,
7396                                 l2_tunnel->l2_tunnel_type);
7397                 else
7398                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7399                                 dev,
7400                                 l2_tunnel->l2_tunnel_type);
7401         }
7402
7403         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7404                 if (en)
7405                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7406                                 dev,
7407                                 l2_tunnel->l2_tunnel_type);
7408                 else
7409                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7410                                 dev,
7411                                 l2_tunnel->l2_tunnel_type);
7412         }
7413
7414         return ret;
7415 }
7416
7417 static int
7418 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7419                         uint16_t port)
7420 {
7421         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7422         IXGBE_WRITE_FLUSH(hw);
7423
7424         return 0;
7425 }
7426
7427 /* There's only one register for VxLAN UDP port.
7428  * So, we cannot add several ports. Will update it.
7429  */
7430 static int
7431 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7432                      uint16_t port)
7433 {
7434         if (port == 0) {
7435                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7436                 return -EINVAL;
7437         }
7438
7439         return ixgbe_update_vxlan_port(hw, port);
7440 }
7441
7442 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7443  * UDP port, it must have a value.
7444  * So, will reset it to the original value 0.
7445  */
7446 static int
7447 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7448                      uint16_t port)
7449 {
7450         uint16_t cur_port;
7451
7452         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7453
7454         if (cur_port != port) {
7455                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7456                 return -EINVAL;
7457         }
7458
7459         return ixgbe_update_vxlan_port(hw, 0);
7460 }
7461
7462 /* Add UDP tunneling port */
7463 static int
7464 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7465                               struct rte_eth_udp_tunnel *udp_tunnel)
7466 {
7467         int ret = 0;
7468         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7469
7470         if (hw->mac.type != ixgbe_mac_X550 &&
7471             hw->mac.type != ixgbe_mac_X550EM_x &&
7472             hw->mac.type != ixgbe_mac_X550EM_a) {
7473                 return -ENOTSUP;
7474         }
7475
7476         if (udp_tunnel == NULL)
7477                 return -EINVAL;
7478
7479         switch (udp_tunnel->prot_type) {
7480         case RTE_TUNNEL_TYPE_VXLAN:
7481                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7482                 break;
7483
7484         case RTE_TUNNEL_TYPE_GENEVE:
7485         case RTE_TUNNEL_TYPE_TEREDO:
7486                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7487                 ret = -EINVAL;
7488                 break;
7489
7490         default:
7491                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7492                 ret = -EINVAL;
7493                 break;
7494         }
7495
7496         return ret;
7497 }
7498
7499 /* Remove UDP tunneling port */
7500 static int
7501 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7502                               struct rte_eth_udp_tunnel *udp_tunnel)
7503 {
7504         int ret = 0;
7505         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7506
7507         if (hw->mac.type != ixgbe_mac_X550 &&
7508             hw->mac.type != ixgbe_mac_X550EM_x &&
7509             hw->mac.type != ixgbe_mac_X550EM_a) {
7510                 return -ENOTSUP;
7511         }
7512
7513         if (udp_tunnel == NULL)
7514                 return -EINVAL;
7515
7516         switch (udp_tunnel->prot_type) {
7517         case RTE_TUNNEL_TYPE_VXLAN:
7518                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7519                 break;
7520         case RTE_TUNNEL_TYPE_GENEVE:
7521         case RTE_TUNNEL_TYPE_TEREDO:
7522                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7523                 ret = -EINVAL;
7524                 break;
7525         default:
7526                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7527                 ret = -EINVAL;
7528                 break;
7529         }
7530
7531         return ret;
7532 }
7533
7534 static void
7535 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7536 {
7537         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7538
7539         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7540 }
7541
7542 static void
7543 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7544 {
7545         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7546
7547         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7548 }
7549
7550 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7551 {
7552         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7553         u32 in_msg = 0;
7554
7555         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7556                 return;
7557
7558         /* PF reset VF event */
7559         if (in_msg == IXGBE_PF_CONTROL_MSG)
7560                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7561 }
7562
7563 static int
7564 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7565 {
7566         uint32_t eicr;
7567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7568         struct ixgbe_interrupt *intr =
7569                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7570         ixgbevf_intr_disable(hw);
7571
7572         /* read-on-clear nic registers here */
7573         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7574         intr->flags = 0;
7575
7576         /* only one misc vector supported - mailbox */
7577         eicr &= IXGBE_VTEICR_MASK;
7578         if (eicr == IXGBE_MISC_VEC_ID)
7579                 intr->flags |= IXGBE_FLAG_MAILBOX;
7580
7581         return 0;
7582 }
7583
7584 static int
7585 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7586 {
7587         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7588         struct ixgbe_interrupt *intr =
7589                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7590
7591         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7592                 ixgbevf_mbx_process(dev);
7593                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7594         }
7595
7596         ixgbevf_intr_enable(hw);
7597
7598         return 0;
7599 }
7600
7601 static void
7602 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7603                               void *param)
7604 {
7605         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7606
7607         ixgbevf_dev_interrupt_get_status(dev);
7608         ixgbevf_dev_interrupt_action(dev);
7609 }
7610
7611 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7612 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7613 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
7614 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7615 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
7616 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");