drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 enum ixgbevf_xcast_modes {
 158         IXGBEVF_XCAST_MODE_NONE = 0,
 159         IXGBEVF_XCAST_MODE_MULTI,
 160         IXGBEVF_XCAST_MODE_ALLMULTI,
 161 };
 162
 163 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 164 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 165
 166 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 167 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 197                                struct rte_eth_dev_info *dev_info);
 198 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 199 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 200                                  struct rte_eth_dev_info *dev_info);
 201 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 202
 203 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 204                 uint16_t vlan_id, int on);
 205 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 206                                enum rte_vlan_type vlan_type,
 207                                uint16_t tpid_id);
 208 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 209                 uint16_t queue, bool on);
 210 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 211                 int on);
 212 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 213 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 214 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 215 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 216 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 217
 218 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 220 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 221                                struct rte_eth_fc_conf *fc_conf);
 222 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 225                 struct rte_eth_pfc_conf *pfc_conf);
 226 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 227                         struct rte_eth_rss_reta_entry64 *reta_conf,
 228                         uint16_t reta_size);
 229 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 230                         struct rte_eth_rss_reta_entry64 *reta_conf,
 231                         uint16_t reta_size);
 232 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 233 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 237                                       struct rte_intr_handle *handle);
 238 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 239                 void *param);
 240 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 241 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 242                 uint32_t index, uint32_t pool);
 243 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 244 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 245                                            struct ether_addr *mac_addr);
 246 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 247
 248 /* For Virtual Function support */
 249 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 250 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 251 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 252 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 256 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 257 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 258                 struct rte_eth_stats *stats);
 259 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 260 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 261                 uint16_t vlan_id, int on);
 262 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 263                 uint16_t queue, int on);
 264 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id);
 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 269                                              uint16_t queue_id);
 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 271                                  uint8_t queue, uint8_t msix_vector);
 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 273 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 274 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 275
 276 /* For Eth VMDQ APIs support */
 277 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 278                 ether_addr * mac_addr, uint8_t on);
 279 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 280 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 281                 uint16_t rx_mask, uint8_t on);
 282 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 283 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 284 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 285                 uint64_t pool_mask, uint8_t vlan_on);
 286 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 287                 struct rte_eth_mirror_conf *mirror_conf,
 288                 uint8_t rule_id, uint8_t on);
 289 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 290                 uint8_t rule_id);
 291 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 292                                           uint16_t queue_id);
 293 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 294                                            uint16_t queue_id);
 295 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 296                                uint8_t queue, uint8_t msix_vector);
 297 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 298
 299 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 300                 uint16_t queue_idx, uint16_t tx_rate);
 301 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 302                 uint16_t tx_rate, uint64_t q_msk);
 303
 304 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 305                                  struct ether_addr *mac_addr,
 306                                  uint32_t index, uint32_t pool);
 307 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 308 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 309                                              struct ether_addr *mac_addr);
 310 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 311                         struct rte_eth_syn_filter *filter,
 312                         bool add);
 313 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 314                         struct rte_eth_syn_filter *filter);
 315 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 316                         enum rte_filter_op filter_op,
 317                         void *arg);
 318 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 319                         struct ixgbe_5tuple_filter *filter);
 320 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 321                         struct ixgbe_5tuple_filter *filter);
 322 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 323                         struct rte_eth_ntuple_filter *filter,
 324                         bool add);
 325 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 326                                 enum rte_filter_op filter_op,
 327                                 void *arg);
 328 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 329                         struct rte_eth_ntuple_filter *filter);
 330 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 331                         struct rte_eth_ethertype_filter *filter,
 332                         bool add);
 333 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 334                                 enum rte_filter_op filter_op,
 335                                 void *arg);
 336 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 337                         struct rte_eth_ethertype_filter *filter);
 338 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 339                      enum rte_filter_type filter_type,
 340                      enum rte_filter_op filter_op,
 341                      void *arg);
 342 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 343
 344 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 345                                       struct ether_addr *mc_addr_set,
 346                                       uint32_t nb_mc_addr);
 347 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 348                                    struct rte_eth_dcb_info *dcb_info);
 349
 350 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 351 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 352                             struct rte_dev_reg_info *regs);
 353 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 354 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 355                                 struct rte_dev_eeprom_info *eeprom);
 356 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 357                                 struct rte_dev_eeprom_info *eeprom);
 358
 359 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 360 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 361                                 struct rte_dev_reg_info *regs);
 362
 363 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 364 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 365 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 366                                             struct timespec *timestamp,
 367                                             uint32_t flags);
 368 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 369                                             struct timespec *timestamp);
 370 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 371 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 372                                    struct timespec *timestamp);
 373 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 374                                    const struct timespec *timestamp);
 375 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 376                                           void *param);
 377
 378 static int ixgbe_dev_l2_tunnel_eth_type_conf
 379         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 380 static int ixgbe_dev_l2_tunnel_offload_set
 381         (struct rte_eth_dev *dev,
 382          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 383          uint32_t mask,
 384          uint8_t en);
 385 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 386                                              enum rte_filter_op filter_op,
 387                                              void *arg);
 388
 389 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 390                                          struct rte_eth_udp_tunnel *udp_tunnel);
 391 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 392                                          struct rte_eth_udp_tunnel *udp_tunnel);
 393
 394 /*
 395  * Define VF Stats MACRO for Non "cleared on read" register
 396  */
 397 #define UPDATE_VF_STAT(reg, last, cur)                          \
 398 {                                                               \
 399         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 400         cur += (latest - last) & UINT_MAX;                      \
 401         last = latest;                                          \
 402 }
 403
 404 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 405 {                                                                \
 406         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 407         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 408         u64 latest = ((new_msb << 32) | new_lsb);                \
 409         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 410         last = latest;                                           \
 411 }
 412
 413 #define IXGBE_SET_HWSTRIP(h, q) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (h)->bitmap[idx] |= 1 << bit;\
 417         } while (0)
 418
 419 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 420                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 421                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 422                 (h)->bitmap[idx] &= ~(1 << bit);\
 423         } while (0)
 424
 425 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 426                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 427                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 428                 (r) = (h)->bitmap[idx] >> bit & 1;\
 429         } while (0)
 430
 431 /*
 432  * The set of PCI devices this driver supports
 433  */
 434 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 488 #ifdef RTE_NIC_BYPASS
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 490 #endif
 491         { .vendor_id = 0, /* sentinel */ },
 492 };
 493
 494 /*
 495  * The set of PCI devices this driver supports (for 82599 VF)
 496  */
 497 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 507         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 508         { .vendor_id = 0, /* sentinel */ },
 509 };
 510
 511 static const struct rte_eth_desc_lim rx_desc_lim = {
 512         .nb_max = IXGBE_MAX_RING_DESC,
 513         .nb_min = IXGBE_MIN_RING_DESC,
 514         .nb_align = IXGBE_RXD_ALIGN,
 515 };
 516
 517 static const struct rte_eth_desc_lim tx_desc_lim = {
 518         .nb_max = IXGBE_MAX_RING_DESC,
 519         .nb_min = IXGBE_MIN_RING_DESC,
 520         .nb_align = IXGBE_TXD_ALIGN,
 521         .nb_seg_max = IXGBE_TX_MAX_SEG,
 522         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 523 };
 524
 525 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 526         .dev_configure        = ixgbe_dev_configure,
 527         .dev_start            = ixgbe_dev_start,
 528         .dev_stop             = ixgbe_dev_stop,
 529         .dev_set_link_up    = ixgbe_dev_set_link_up,
 530         .dev_set_link_down  = ixgbe_dev_set_link_down,
 531         .dev_close            = ixgbe_dev_close,
 532         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 533         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 534         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 535         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 536         .link_update          = ixgbe_dev_link_update,
 537         .stats_get            = ixgbe_dev_stats_get,
 538         .xstats_get           = ixgbe_dev_xstats_get,
 539         .stats_reset          = ixgbe_dev_stats_reset,
 540         .xstats_reset         = ixgbe_dev_xstats_reset,
 541         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 542         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 543         .dev_infos_get        = ixgbe_dev_info_get,
 544         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 545         .mtu_set              = ixgbe_dev_mtu_set,
 546         .vlan_filter_set      = ixgbe_vlan_filter_set,
 547         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 548         .vlan_offload_set     = ixgbe_vlan_offload_set,
 549         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 550         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 551         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 552         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 553         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 554         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 555         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 556         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 557         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 558         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 559         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 560         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 561         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 562         .dev_led_on           = ixgbe_dev_led_on,
 563         .dev_led_off          = ixgbe_dev_led_off,
 564         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 565         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 566         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 567         .mac_addr_add         = ixgbe_add_rar,
 568         .mac_addr_remove      = ixgbe_remove_rar,
 569         .mac_addr_set         = ixgbe_set_default_mac_addr,
 570         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 571         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 572         .mirror_rule_set      = ixgbe_mirror_rule_set,
 573         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 574         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 575         .set_vf_rx            = ixgbe_set_pool_rx,
 576         .set_vf_tx            = ixgbe_set_pool_tx,
 577         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 578         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 579         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 580         .reta_update          = ixgbe_dev_rss_reta_update,
 581         .reta_query           = ixgbe_dev_rss_reta_query,
 582 #ifdef RTE_NIC_BYPASS
 583         .bypass_init          = ixgbe_bypass_init,
 584         .bypass_state_set     = ixgbe_bypass_state_store,
 585         .bypass_state_show    = ixgbe_bypass_state_show,
 586         .bypass_event_set     = ixgbe_bypass_event_store,
 587         .bypass_event_show    = ixgbe_bypass_event_show,
 588         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 589         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 590         .bypass_ver_show      = ixgbe_bypass_ver_show,
 591         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 592 #endif /* RTE_NIC_BYPASS */
 593         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 594         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 595         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 596         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 597         .rxq_info_get         = ixgbe_rxq_info_get,
 598         .txq_info_get         = ixgbe_txq_info_get,
 599         .timesync_enable      = ixgbe_timesync_enable,
 600         .timesync_disable     = ixgbe_timesync_disable,
 601         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 602         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 603         .get_reg              = ixgbe_get_regs,
 604         .get_eeprom_length    = ixgbe_get_eeprom_length,
 605         .get_eeprom           = ixgbe_get_eeprom,
 606         .set_eeprom           = ixgbe_set_eeprom,
 607         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 608         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 609         .timesync_read_time   = ixgbe_timesync_read_time,
 610         .timesync_write_time  = ixgbe_timesync_write_time,
 611         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 612         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 613         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 614         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 615 };
 616
 617 /*
 618  * dev_ops for virtual function, bare necessities for basic vf
 619  * operation have been implemented
 620  */
 621 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 622         .dev_configure        = ixgbevf_dev_configure,
 623         .dev_start            = ixgbevf_dev_start,
 624         .dev_stop             = ixgbevf_dev_stop,
 625         .link_update          = ixgbe_dev_link_update,
 626         .stats_get            = ixgbevf_dev_stats_get,
 627         .xstats_get           = ixgbevf_dev_xstats_get,
 628         .stats_reset          = ixgbevf_dev_stats_reset,
 629         .xstats_reset         = ixgbevf_dev_stats_reset,
 630         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 631         .dev_close            = ixgbevf_dev_close,
 632         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 633         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 634         .dev_infos_get        = ixgbevf_dev_info_get,
 635         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 636         .mtu_set              = ixgbevf_dev_set_mtu,
 637         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 638         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 639         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 640         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 641         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 642         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 643         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 644         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 645         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 646         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 647         .mac_addr_add         = ixgbevf_add_mac_addr,
 648         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 649         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 650         .rxq_info_get         = ixgbe_rxq_info_get,
 651         .txq_info_get         = ixgbe_txq_info_get,
 652         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 653         .get_reg              = ixgbevf_get_regs,
 654         .reta_update          = ixgbe_dev_rss_reta_update,
 655         .reta_query           = ixgbe_dev_rss_reta_query,
 656         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 657         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 658 };
 659
 660 /* store statistics names and its offset in stats structure */
 661 struct rte_ixgbe_xstats_name_off {
 662         char name[RTE_ETH_XSTATS_NAME_SIZE];
 663         unsigned offset;
 664 };
 665
 666 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 667         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 668         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 669         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 670         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 671         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 672         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 673         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 674         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 675         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 676         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 677         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 678         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 679         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 680         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 681         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 682                 prc1023)},
 683         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 684                 prc1522)},
 685         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 686         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 687         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 688         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 689         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 690         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 691         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 692         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 693         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 694         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 695         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 696         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 697         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 698         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 699         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 700         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 701         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 702                 ptc1023)},
 703         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 704                 ptc1522)},
 705         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 706         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 707         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 708         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 709
 710         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirustat_add)},
 712         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 713                 fdirustat_remove)},
 714         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 715                 fdirfstat_fadd)},
 716         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 717                 fdirfstat_fremove)},
 718         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 719                 fdirmatch)},
 720         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 721                 fdirmiss)},
 722
 723         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 724         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 725         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 726                 fclast)},
 727         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 728         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 729         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 730         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 731         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 732                 fcoe_noddp)},
 733         {"rx_fcoe_no_direct_data_placement_ext_buff",
 734                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 735
 736         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxontxc)},
 738         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxonrxc)},
 740         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxofftxc)},
 742         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 743                 lxoffrxc)},
 744         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 745 };
 746
 747 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 748                            sizeof(rte_ixgbe_stats_strings[0]))
 749
 750 /* Per-queue statistics */
 751 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 752         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 753         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 754         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 755         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 756 };
 757
 758 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 759                            sizeof(rte_ixgbe_rxq_strings[0]))
 760 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 761
 762 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 763         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 764         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 765         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 766                 pxon2offc)},
 767 };
 768
 769 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 770                            sizeof(rte_ixgbe_txq_strings[0]))
 771 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 772
 773 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 774         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 775 };
 776
 777 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 778                 sizeof(rte_ixgbevf_stats_strings[0]))
 779
 780 /**
 781  * Atomically reads the link status information from global
 782  * structure rte_eth_dev.
 783  *
 784  * @param dev
 785  *   - Pointer to the structure rte_eth_dev to read from.
 786  *   - Pointer to the buffer to be saved with the link status.
 787  *
 788  * @return
 789  *   - On success, zero.
 790  *   - On failure, negative value.
 791  */
 792 static inline int
 793 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 794                                 struct rte_eth_link *link)
 795 {
 796         struct rte_eth_link *dst = link;
 797         struct rte_eth_link *src = &(dev->data->dev_link);
 798
 799         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 800                                         *(uint64_t *)src) == 0)
 801                 return -1;
 802
 803         return 0;
 804 }
 805
 806 /**
 807  * Atomically writes the link status information into global
 808  * structure rte_eth_dev.
 809  *
 810  * @param dev
 811  *   - Pointer to the structure rte_eth_dev to read from.
 812  *   - Pointer to the buffer to be saved with the link status.
 813  *
 814  * @return
 815  *   - On success, zero.
 816  *   - On failure, negative value.
 817  */
 818 static inline int
 819 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 820                                 struct rte_eth_link *link)
 821 {
 822         struct rte_eth_link *dst = &(dev->data->dev_link);
 823         struct rte_eth_link *src = link;
 824
 825         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 826                                         *(uint64_t *)src) == 0)
 827                 return -1;
 828
 829         return 0;
 830 }
 831
 832 /*
 833  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 834  */
 835 static inline int
 836 ixgbe_is_sfp(struct ixgbe_hw *hw)
 837 {
 838         switch (hw->phy.type) {
 839         case ixgbe_phy_sfp_avago:
 840         case ixgbe_phy_sfp_ftl:
 841         case ixgbe_phy_sfp_intel:
 842         case ixgbe_phy_sfp_unknown:
 843         case ixgbe_phy_sfp_passive_tyco:
 844         case ixgbe_phy_sfp_passive_unknown:
 845                 return 1;
 846         default:
 847                 return 0;
 848         }
 849 }
 850
 851 static inline int32_t
 852 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 853 {
 854         uint32_t ctrl_ext;
 855         int32_t status;
 856
 857         status = ixgbe_reset_hw(hw);
 858
 859         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 860         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 861         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 862         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 863         IXGBE_WRITE_FLUSH(hw);
 864
 865         return status;
 866 }
 867
 868 static inline void
 869 ixgbe_enable_intr(struct rte_eth_dev *dev)
 870 {
 871         struct ixgbe_interrupt *intr =
 872                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 873         struct ixgbe_hw *hw =
 874                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 875
 876         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 877         IXGBE_WRITE_FLUSH(hw);
 878 }
 879
 880 /*
 881  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 882  */
 883 static void
 884 ixgbe_disable_intr(struct ixgbe_hw *hw)
 885 {
 886         PMD_INIT_FUNC_TRACE();
 887
 888         if (hw->mac.type == ixgbe_mac_82598EB) {
 889                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 890         } else {
 891                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 892                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 893                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 894         }
 895         IXGBE_WRITE_FLUSH(hw);
 896 }
 897
 898 /*
 899  * This function resets queue statistics mapping registers.
 900  * From Niantic datasheet, Initialization of Statistics section:
 901  * "...if software requires the queue counters, the RQSMR and TQSM registers
 902  * must be re-programmed following a device reset.
 903  */
 904 static void
 905 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 906 {
 907         uint32_t i;
 908
 909         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 910                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 911                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 912         }
 913 }
 914
 915
 916 static int
 917 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 918                                   uint16_t queue_id,
 919                                   uint8_t stat_idx,
 920                                   uint8_t is_rx)
 921 {
 922 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 923 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 924 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 925
 926         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 927         struct ixgbe_stat_mapping_registers *stat_mappings =
 928                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 929         uint32_t qsmr_mask = 0;
 930         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 931         uint32_t q_map;
 932         uint8_t n, offset;
 933
 934         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 935                 (hw->mac.type != ixgbe_mac_X540) &&
 936                 (hw->mac.type != ixgbe_mac_X550) &&
 937                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 938                 (hw->mac.type != ixgbe_mac_X550EM_a))
 939                 return -ENOSYS;
 940
 941         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 942                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 943                      queue_id, stat_idx);
 944
 945         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 946         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 947                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 948                 return -EIO;
 949         }
 950         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 951
 952         /* Now clear any previous stat_idx set */
 953         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 954         if (!is_rx)
 955                 stat_mappings->tqsm[n] &= ~clearing_mask;
 956         else
 957                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 958
 959         q_map = (uint32_t)stat_idx;
 960         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 961         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 962         if (!is_rx)
 963                 stat_mappings->tqsm[n] |= qsmr_mask;
 964         else
 965                 stat_mappings->rqsmr[n] |= qsmr_mask;
 966
 967         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 968                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 969                      queue_id, stat_idx);
 970         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 971                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 972
 973         /* Now write the mapping in the appropriate register */
 974         if (is_rx) {
 975                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 976                              stat_mappings->rqsmr[n], n);
 977                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 978         } else {
 979                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 980                              stat_mappings->tqsm[n], n);
 981                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 982         }
 983         return 0;
 984 }
 985
 986 static void
 987 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 988 {
 989         struct ixgbe_stat_mapping_registers *stat_mappings =
 990                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 992         int i;
 993
 994         /* write whatever was in stat mapping table to the NIC */
 995         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 996                 /* rx */
 997                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 998
 999                 /* tx */
1000                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1001         }
1002 }
1003
1004 static void
1005 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1006 {
1007         uint8_t i;
1008         struct ixgbe_dcb_tc_config *tc;
1009         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1010
1011         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1012         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1013         for (i = 0; i < dcb_max_tc; i++) {
1014                 tc = &dcb_config->tc_config[i];
1015                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1016                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1017                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1018                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1019                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1020                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1021                 tc->pfc = ixgbe_dcb_pfc_disabled;
1022         }
1023
1024         /* Initialize default user to priority mapping, UPx->TC0 */
1025         tc = &dcb_config->tc_config[0];
1026         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1027         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1028         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1029                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1030                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1031         }
1032         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1033         dcb_config->pfc_mode_enable = false;
1034         dcb_config->vt_mode = true;
1035         dcb_config->round_robin_enable = false;
1036         /* support all DCB capabilities in 82599 */
1037         dcb_config->support.capabilities = 0xFF;
1038
1039         /*we only support 4 Tcs for X540, X550 */
1040         if (hw->mac.type == ixgbe_mac_X540 ||
1041                 hw->mac.type == ixgbe_mac_X550 ||
1042                 hw->mac.type == ixgbe_mac_X550EM_x ||
1043                 hw->mac.type == ixgbe_mac_X550EM_a) {
1044                 dcb_config->num_tcs.pg_tcs = 4;
1045                 dcb_config->num_tcs.pfc_tcs = 4;
1046         }
1047 }
1048
1049 /*
1050  * Ensure that all locks are released before first NVM or PHY access
1051  */
1052 static void
1053 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1054 {
1055         uint16_t mask;
1056
1057         /*
1058          * Phy lock should not fail in this early stage. If this is the case,
1059          * it is due to an improper exit of the application.
1060          * So force the release of the faulty lock. Release of common lock
1061          * is done automatically by swfw_sync function.
1062          */
1063         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1064         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1065                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1066         }
1067         ixgbe_release_swfw_semaphore(hw, mask);
1068
1069         /*
1070          * These ones are more tricky since they are common to all ports; but
1071          * swfw_sync retries last long enough (1s) to be almost sure that if
1072          * lock can not be taken it is due to an improper lock of the
1073          * semaphore.
1074          */
1075         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1076         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1077                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1078         }
1079         ixgbe_release_swfw_semaphore(hw, mask);
1080 }
1081
1082 /*
1083  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1084  * It returns 0 on success.
1085  */
1086 static int
1087 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1088 {
1089         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1090         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1091         struct ixgbe_hw *hw =
1092                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1093         struct ixgbe_vfta *shadow_vfta =
1094                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1095         struct ixgbe_hwstrip *hwstrip =
1096                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1097         struct ixgbe_dcb_config *dcb_config =
1098                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1099         struct ixgbe_filter_info *filter_info =
1100                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1101         uint32_t ctrl_ext;
1102         uint16_t csum;
1103         int diag, i;
1104
1105         PMD_INIT_FUNC_TRACE();
1106
1107         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1108         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1109         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1110         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1111
1112         /*
1113          * For secondary processes, we don't initialise any further as primary
1114          * has already done this work. Only check we don't need a different
1115          * RX and TX function.
1116          */
1117         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1118                 struct ixgbe_tx_queue *txq;
1119                 /* TX queue function in primary, set by last queue initialized
1120                  * Tx queue may not initialized by primary process
1121                  */
1122                 if (eth_dev->data->tx_queues) {
1123                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1124                         ixgbe_set_tx_function(eth_dev, txq);
1125                 } else {
1126                         /* Use default TX function if we get here */
1127                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1128                                      "Using default TX function.");
1129                 }
1130
1131                 ixgbe_set_rx_function(eth_dev);
1132
1133                 return 0;
1134         }
1135
1136         rte_eth_copy_pci_info(eth_dev, pci_dev);
1137         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1138
1139         /* Vendor and Device ID need to be set before init of shared code */
1140         hw->device_id = pci_dev->id.device_id;
1141         hw->vendor_id = pci_dev->id.vendor_id;
1142         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1143         hw->allow_unsupported_sfp = 1;
1144
1145         /* Initialize the shared code (base driver) */
1146 #ifdef RTE_NIC_BYPASS
1147         diag = ixgbe_bypass_init_shared_code(hw);
1148 #else
1149         diag = ixgbe_init_shared_code(hw);
1150 #endif /* RTE_NIC_BYPASS */
1151
1152         if (diag != IXGBE_SUCCESS) {
1153                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1154                 return -EIO;
1155         }
1156
1157         /* pick up the PCI bus settings for reporting later */
1158         ixgbe_get_bus_info(hw);
1159
1160         /* Unlock any pending hardware semaphore */
1161         ixgbe_swfw_lock_reset(hw);
1162
1163         /* Initialize DCB configuration*/
1164         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1165         ixgbe_dcb_init(hw, dcb_config);
1166         /* Get Hardware Flow Control setting */
1167         hw->fc.requested_mode = ixgbe_fc_full;
1168         hw->fc.current_mode = ixgbe_fc_full;
1169         hw->fc.pause_time = IXGBE_FC_PAUSE;
1170         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1171                 hw->fc.low_water[i] = IXGBE_FC_LO;
1172                 hw->fc.high_water[i] = IXGBE_FC_HI;
1173         }
1174         hw->fc.send_xon = 1;
1175
1176         /* Make sure we have a good EEPROM before we read from it */
1177         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1178         if (diag != IXGBE_SUCCESS) {
1179                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1180                 return -EIO;
1181         }
1182
1183 #ifdef RTE_NIC_BYPASS
1184         diag = ixgbe_bypass_init_hw(hw);
1185 #else
1186         diag = ixgbe_init_hw(hw);
1187 #endif /* RTE_NIC_BYPASS */
1188
1189         /*
1190          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1191          * is called too soon after the kernel driver unbinding/binding occurs.
1192          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1193          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1194          * also called. See ixgbe_identify_phy_82599(). The reason for the
1195          * failure is not known, and only occuts when virtualisation features
1196          * are disabled in the bios. A delay of 100ms  was found to be enough by
1197          * trial-and-error, and is doubled to be safe.
1198          */
1199         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1200                 rte_delay_ms(200);
1201                 diag = ixgbe_init_hw(hw);
1202         }
1203
1204         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1205                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1206                              "LOM.  Please be aware there may be issues associated "
1207                              "with your hardware.");
1208                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1209                              "please contact your Intel or hardware representative "
1210                              "who provided you with this hardware.");
1211         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1212                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1213         if (diag) {
1214                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1215                 return -EIO;
1216         }
1217
1218         /* Reset the hw statistics */
1219         ixgbe_dev_stats_reset(eth_dev);
1220
1221         /* disable interrupt */
1222         ixgbe_disable_intr(hw);
1223
1224         /* reset mappings for queue statistics hw counters*/
1225         ixgbe_reset_qstat_mappings(hw);
1226
1227         /* Allocate memory for storing MAC addresses */
1228         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1229                                                hw->mac.num_rar_entries, 0);
1230         if (eth_dev->data->mac_addrs == NULL) {
1231                 PMD_INIT_LOG(ERR,
1232                              "Failed to allocate %u bytes needed to store "
1233                              "MAC addresses",
1234                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1235                 return -ENOMEM;
1236         }
1237         /* Copy the permanent MAC address */
1238         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1239                         &eth_dev->data->mac_addrs[0]);
1240
1241         /* Allocate memory for storing hash filter MAC addresses */
1242         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1243                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1244         if (eth_dev->data->hash_mac_addrs == NULL) {
1245                 PMD_INIT_LOG(ERR,
1246                              "Failed to allocate %d bytes needed to store MAC addresses",
1247                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1248                 return -ENOMEM;
1249         }
1250
1251         /* initialize the vfta */
1252         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1253
1254         /* initialize the hw strip bitmap*/
1255         memset(hwstrip, 0, sizeof(*hwstrip));
1256
1257         /* initialize PF if max_vfs not zero */
1258         ixgbe_pf_host_init(eth_dev);
1259
1260         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1261         /* let hardware know driver is loaded */
1262         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1263         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1264         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1265         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1266         IXGBE_WRITE_FLUSH(hw);
1267
1268         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1269                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1270                              (int) hw->mac.type, (int) hw->phy.type,
1271                              (int) hw->phy.sfp_type);
1272         else
1273                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1274                              (int) hw->mac.type, (int) hw->phy.type);
1275
1276         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1277                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1278                      pci_dev->id.device_id);
1279
1280         rte_intr_callback_register(intr_handle,
1281                                    ixgbe_dev_interrupt_handler, eth_dev);
1282
1283         /* enable uio/vfio intr/eventfd mapping */
1284         rte_intr_enable(intr_handle);
1285
1286         /* enable support intr */
1287         ixgbe_enable_intr(eth_dev);
1288
1289         /* initialize 5tuple filter list */
1290         TAILQ_INIT(&filter_info->fivetuple_list);
1291         memset(filter_info->fivetuple_mask, 0,
1292                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1293
1294         return 0;
1295 }
1296
1297 static int
1298 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1299 {
1300         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1301         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1302         struct ixgbe_hw *hw;
1303
1304         PMD_INIT_FUNC_TRACE();
1305
1306         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1307                 return -EPERM;
1308
1309         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1310
1311         if (hw->adapter_stopped == 0)
1312                 ixgbe_dev_close(eth_dev);
1313
1314         eth_dev->dev_ops = NULL;
1315         eth_dev->rx_pkt_burst = NULL;
1316         eth_dev->tx_pkt_burst = NULL;
1317
1318         /* Unlock any pending hardware semaphore */
1319         ixgbe_swfw_lock_reset(hw);
1320
1321         /* disable uio intr before callback unregister */
1322         rte_intr_disable(intr_handle);
1323         rte_intr_callback_unregister(intr_handle,
1324                                      ixgbe_dev_interrupt_handler, eth_dev);
1325
1326         /* uninitialize PF if max_vfs not zero */
1327         ixgbe_pf_host_uninit(eth_dev);
1328
1329         rte_free(eth_dev->data->mac_addrs);
1330         eth_dev->data->mac_addrs = NULL;
1331
1332         rte_free(eth_dev->data->hash_mac_addrs);
1333         eth_dev->data->hash_mac_addrs = NULL;
1334
1335         return 0;
1336 }
1337
1338 /*
1339  * Negotiate mailbox API version with the PF.
1340  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1341  * Then we try to negotiate starting with the most recent one.
1342  * If all negotiation attempts fail, then we will proceed with
1343  * the default one (ixgbe_mbox_api_10).
1344  */
1345 static void
1346 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1347 {
1348         int32_t i;
1349
1350         /* start with highest supported, proceed down */
1351         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1352                 ixgbe_mbox_api_12,
1353                 ixgbe_mbox_api_11,
1354                 ixgbe_mbox_api_10,
1355         };
1356
1357         for (i = 0;
1358                         i != RTE_DIM(sup_ver) &&
1359                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1360                         i++)
1361                 ;
1362 }
1363
1364 static void
1365 generate_random_mac_addr(struct ether_addr *mac_addr)
1366 {
1367         uint64_t random;
1368
1369         /* Set Organizationally Unique Identifier (OUI) prefix. */
1370         mac_addr->addr_bytes[0] = 0x00;
1371         mac_addr->addr_bytes[1] = 0x09;
1372         mac_addr->addr_bytes[2] = 0xC0;
1373         /* Force indication of locally assigned MAC address. */
1374         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1375         /* Generate the last 3 bytes of the MAC address with a random number. */
1376         random = rte_rand();
1377         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1378 }
1379
1380 /*
1381  * Virtual Function device init
1382  */
1383 static int
1384 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1385 {
1386         int diag;
1387         uint32_t tc, tcs;
1388         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1389         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1390         struct ixgbe_hw *hw =
1391                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1392         struct ixgbe_vfta *shadow_vfta =
1393                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1394         struct ixgbe_hwstrip *hwstrip =
1395                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1396         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1397
1398         PMD_INIT_FUNC_TRACE();
1399
1400         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1401         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1402         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1403
1404         /* for secondary processes, we don't initialise any further as primary
1405          * has already done this work. Only check we don't need a different
1406          * RX function
1407          */
1408         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1409                 struct ixgbe_tx_queue *txq;
1410                 /* TX queue function in primary, set by last queue initialized
1411                  * Tx queue may not initialized by primary process
1412                  */
1413                 if (eth_dev->data->tx_queues) {
1414                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1415                         ixgbe_set_tx_function(eth_dev, txq);
1416                 } else {
1417                         /* Use default TX function if we get here */
1418                         PMD_INIT_LOG(NOTICE,
1419                                      "No TX queues configured yet. Using default TX function.");
1420                 }
1421
1422                 ixgbe_set_rx_function(eth_dev);
1423
1424                 return 0;
1425         }
1426
1427         rte_eth_copy_pci_info(eth_dev, pci_dev);
1428         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1429
1430         hw->device_id = pci_dev->id.device_id;
1431         hw->vendor_id = pci_dev->id.vendor_id;
1432         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1433
1434         /* initialize the vfta */
1435         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1436
1437         /* initialize the hw strip bitmap*/
1438         memset(hwstrip, 0, sizeof(*hwstrip));
1439
1440         /* Initialize the shared code (base driver) */
1441         diag = ixgbe_init_shared_code(hw);
1442         if (diag != IXGBE_SUCCESS) {
1443                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1444                 return -EIO;
1445         }
1446
1447         /* init_mailbox_params */
1448         hw->mbx.ops.init_params(hw);
1449
1450         /* Reset the hw statistics */
1451         ixgbevf_dev_stats_reset(eth_dev);
1452
1453         /* Disable the interrupts for VF */
1454         ixgbevf_intr_disable(hw);
1455
1456         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1457         diag = hw->mac.ops.reset_hw(hw);
1458
1459         /*
1460          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1461          * the underlying PF driver has not assigned a MAC address to the VF.
1462          * In this case, assign a random MAC address.
1463          */
1464         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1465                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1466                 return diag;
1467         }
1468
1469         /* negotiate mailbox API version to use with the PF. */
1470         ixgbevf_negotiate_api(hw);
1471
1472         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1473         ixgbevf_get_queues(hw, &tcs, &tc);
1474
1475         /* Allocate memory for storing MAC addresses */
1476         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1477                                                hw->mac.num_rar_entries, 0);
1478         if (eth_dev->data->mac_addrs == NULL) {
1479                 PMD_INIT_LOG(ERR,
1480                              "Failed to allocate %u bytes needed to store "
1481                              "MAC addresses",
1482                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1483                 return -ENOMEM;
1484         }
1485
1486         /* Generate a random MAC address, if none was assigned by PF. */
1487         if (is_zero_ether_addr(perm_addr)) {
1488                 generate_random_mac_addr(perm_addr);
1489                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1490                 if (diag) {
1491                         rte_free(eth_dev->data->mac_addrs);
1492                         eth_dev->data->mac_addrs = NULL;
1493                         return diag;
1494                 }
1495                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1496                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1497                              "%02x:%02x:%02x:%02x:%02x:%02x",
1498                              perm_addr->addr_bytes[0],
1499                              perm_addr->addr_bytes[1],
1500                              perm_addr->addr_bytes[2],
1501                              perm_addr->addr_bytes[3],
1502                              perm_addr->addr_bytes[4],
1503                              perm_addr->addr_bytes[5]);
1504         }
1505
1506         /* Copy the permanent MAC address */
1507         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1508
1509         /* reset the hardware with the new settings */
1510         diag = hw->mac.ops.start_hw(hw);
1511         switch (diag) {
1512         case  0:
1513                 break;
1514
1515         default:
1516                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1517                 return -EIO;
1518         }
1519
1520         rte_intr_callback_register(intr_handle,
1521                                    ixgbevf_dev_interrupt_handler, eth_dev);
1522         rte_intr_enable(intr_handle);
1523         ixgbevf_intr_enable(hw);
1524
1525         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1526                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1527                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1528
1529         return 0;
1530 }
1531
1532 /* Virtual Function device uninit */
1533
1534 static int
1535 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1536 {
1537         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1538         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1539         struct ixgbe_hw *hw;
1540
1541         PMD_INIT_FUNC_TRACE();
1542
1543         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1544                 return -EPERM;
1545
1546         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1547
1548         if (hw->adapter_stopped == 0)
1549                 ixgbevf_dev_close(eth_dev);
1550
1551         eth_dev->dev_ops = NULL;
1552         eth_dev->rx_pkt_burst = NULL;
1553         eth_dev->tx_pkt_burst = NULL;
1554
1555         /* Disable the interrupts for VF */
1556         ixgbevf_intr_disable(hw);
1557
1558         rte_free(eth_dev->data->mac_addrs);
1559         eth_dev->data->mac_addrs = NULL;
1560
1561         rte_intr_disable(intr_handle);
1562         rte_intr_callback_unregister(intr_handle,
1563                                      ixgbevf_dev_interrupt_handler, eth_dev);
1564
1565         return 0;
1566 }
1567
1568 static struct eth_driver rte_ixgbe_pmd = {
1569         .pci_drv = {
1570                 .id_table = pci_id_ixgbe_map,
1571                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1572                 .probe = rte_eth_dev_pci_probe,
1573                 .remove = rte_eth_dev_pci_remove,
1574         },
1575         .eth_dev_init = eth_ixgbe_dev_init,
1576         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1577         .dev_private_size = sizeof(struct ixgbe_adapter),
1578 };
1579
1580 /*
1581  * virtual function driver struct
1582  */
1583 static struct eth_driver rte_ixgbevf_pmd = {
1584         .pci_drv = {
1585                 .id_table = pci_id_ixgbevf_map,
1586                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1587                 .probe = rte_eth_dev_pci_probe,
1588                 .remove = rte_eth_dev_pci_remove,
1589         },
1590         .eth_dev_init = eth_ixgbevf_dev_init,
1591         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1592         .dev_private_size = sizeof(struct ixgbe_adapter),
1593 };
1594
1595 static int
1596 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1597 {
1598         struct ixgbe_hw *hw =
1599                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1600         struct ixgbe_vfta *shadow_vfta =
1601                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1602         uint32_t vfta;
1603         uint32_t vid_idx;
1604         uint32_t vid_bit;
1605
1606         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1607         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1608         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1609         if (on)
1610                 vfta |= vid_bit;
1611         else
1612                 vfta &= ~vid_bit;
1613         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1614
1615         /* update local VFTA copy */
1616         shadow_vfta->vfta[vid_idx] = vfta;
1617
1618         return 0;
1619 }
1620
1621 static void
1622 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1623 {
1624         if (on)
1625                 ixgbe_vlan_hw_strip_enable(dev, queue);
1626         else
1627                 ixgbe_vlan_hw_strip_disable(dev, queue);
1628 }
1629
1630 static int
1631 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1632                     enum rte_vlan_type vlan_type,
1633                     uint16_t tpid)
1634 {
1635         struct ixgbe_hw *hw =
1636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637         int ret = 0;
1638         uint32_t reg;
1639         uint32_t qinq;
1640
1641         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1642         qinq &= IXGBE_DMATXCTL_GDV;
1643
1644         switch (vlan_type) {
1645         case ETH_VLAN_TYPE_INNER:
1646                 if (qinq) {
1647                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1648                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1649                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1650                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1651                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1652                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1653                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1654                 } else {
1655                         ret = -ENOTSUP;
1656                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1657                                     " by single VLAN");
1658                 }
1659                 break;
1660         case ETH_VLAN_TYPE_OUTER:
1661                 if (qinq) {
1662                         /* Only the high 16-bits is valid */
1663                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1664                                         IXGBE_EXVET_VET_EXT_SHIFT);
1665                 } else {
1666                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1667                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1668                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1669                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1670                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1671                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1672                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1673                 }
1674
1675                 break;
1676         default:
1677                 ret = -EINVAL;
1678                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1679                 break;
1680         }
1681
1682         return ret;
1683 }
1684
1685 void
1686 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1687 {
1688         struct ixgbe_hw *hw =
1689                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1690         uint32_t vlnctrl;
1691
1692         PMD_INIT_FUNC_TRACE();
1693
1694         /* Filter Table Disable */
1695         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1696         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1697
1698         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1699 }
1700
1701 void
1702 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1703 {
1704         struct ixgbe_hw *hw =
1705                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1706         struct ixgbe_vfta *shadow_vfta =
1707                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1708         uint32_t vlnctrl;
1709         uint16_t i;
1710
1711         PMD_INIT_FUNC_TRACE();
1712
1713         /* Filter Table Enable */
1714         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1715         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1716         vlnctrl |= IXGBE_VLNCTRL_VFE;
1717
1718         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1719
1720         /* write whatever is in local vfta copy */
1721         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1722                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1723 }
1724
1725 static void
1726 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1727 {
1728         struct ixgbe_hwstrip *hwstrip =
1729                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1730         struct ixgbe_rx_queue *rxq;
1731
1732         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1733                 return;
1734
1735         if (on)
1736                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1737         else
1738                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1739
1740         if (queue >= dev->data->nb_rx_queues)
1741                 return;
1742
1743         rxq = dev->data->rx_queues[queue];
1744
1745         if (on)
1746                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1747         else
1748                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1749 }
1750
1751 static void
1752 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1753 {
1754         struct ixgbe_hw *hw =
1755                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1756         uint32_t ctrl;
1757
1758         PMD_INIT_FUNC_TRACE();
1759
1760         if (hw->mac.type == ixgbe_mac_82598EB) {
1761                 /* No queue level support */
1762                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1763                 return;
1764         }
1765
1766         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1767         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1768         ctrl &= ~IXGBE_RXDCTL_VME;
1769         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1770
1771         /* record those setting for HW strip per queue */
1772         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1773 }
1774
1775 static void
1776 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1777 {
1778         struct ixgbe_hw *hw =
1779                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1780         uint32_t ctrl;
1781
1782         PMD_INIT_FUNC_TRACE();
1783
1784         if (hw->mac.type == ixgbe_mac_82598EB) {
1785                 /* No queue level supported */
1786                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1787                 return;
1788         }
1789
1790         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1791         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1792         ctrl |= IXGBE_RXDCTL_VME;
1793         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1794
1795         /* record those setting for HW strip per queue */
1796         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1797 }
1798
1799 void
1800 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1801 {
1802         struct ixgbe_hw *hw =
1803                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1804         uint32_t ctrl;
1805         uint16_t i;
1806         struct ixgbe_rx_queue *rxq;
1807
1808         PMD_INIT_FUNC_TRACE();
1809
1810         if (hw->mac.type == ixgbe_mac_82598EB) {
1811                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1812                 ctrl &= ~IXGBE_VLNCTRL_VME;
1813                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1814         } else {
1815                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1816                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1817                         rxq = dev->data->rx_queues[i];
1818                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1819                         ctrl &= ~IXGBE_RXDCTL_VME;
1820                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1821
1822                         /* record those setting for HW strip per queue */
1823                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1824                 }
1825         }
1826 }
1827
1828 void
1829 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1830 {
1831         struct ixgbe_hw *hw =
1832                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833         uint32_t ctrl;
1834         uint16_t i;
1835         struct ixgbe_rx_queue *rxq;
1836
1837         PMD_INIT_FUNC_TRACE();
1838
1839         if (hw->mac.type == ixgbe_mac_82598EB) {
1840                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1841                 ctrl |= IXGBE_VLNCTRL_VME;
1842                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1843         } else {
1844                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1845                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1846                         rxq = dev->data->rx_queues[i];
1847                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1848                         ctrl |= IXGBE_RXDCTL_VME;
1849                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1850
1851                         /* record those setting for HW strip per queue */
1852                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1853                 }
1854         }
1855 }
1856
1857 static void
1858 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1859 {
1860         struct ixgbe_hw *hw =
1861                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862         uint32_t ctrl;
1863
1864         PMD_INIT_FUNC_TRACE();
1865
1866         /* DMATXCTRL: Geric Double VLAN Disable */
1867         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1868         ctrl &= ~IXGBE_DMATXCTL_GDV;
1869         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1870
1871         /* CTRL_EXT: Global Double VLAN Disable */
1872         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1873         ctrl &= ~IXGBE_EXTENDED_VLAN;
1874         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1875
1876 }
1877
1878 static void
1879 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1880 {
1881         struct ixgbe_hw *hw =
1882                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1883         uint32_t ctrl;
1884
1885         PMD_INIT_FUNC_TRACE();
1886
1887         /* DMATXCTRL: Geric Double VLAN Enable */
1888         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1889         ctrl |= IXGBE_DMATXCTL_GDV;
1890         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1891
1892         /* CTRL_EXT: Global Double VLAN Enable */
1893         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1894         ctrl |= IXGBE_EXTENDED_VLAN;
1895         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1896
1897         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1898         if (hw->mac.type == ixgbe_mac_X550 ||
1899             hw->mac.type == ixgbe_mac_X550EM_x ||
1900             hw->mac.type == ixgbe_mac_X550EM_a) {
1901                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1902                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1903                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1904         }
1905
1906         /*
1907          * VET EXT field in the EXVET register = 0x8100 by default
1908          * So no need to change. Same to VT field of DMATXCTL register
1909          */
1910 }
1911
1912 static void
1913 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1914 {
1915         if (mask & ETH_VLAN_STRIP_MASK) {
1916                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1917                         ixgbe_vlan_hw_strip_enable_all(dev);
1918                 else
1919                         ixgbe_vlan_hw_strip_disable_all(dev);
1920         }
1921
1922         if (mask & ETH_VLAN_FILTER_MASK) {
1923                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1924                         ixgbe_vlan_hw_filter_enable(dev);
1925                 else
1926                         ixgbe_vlan_hw_filter_disable(dev);
1927         }
1928
1929         if (mask & ETH_VLAN_EXTEND_MASK) {
1930                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1931                         ixgbe_vlan_hw_extend_enable(dev);
1932                 else
1933                         ixgbe_vlan_hw_extend_disable(dev);
1934         }
1935 }
1936
1937 static void
1938 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1939 {
1940         struct ixgbe_hw *hw =
1941                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1943         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1944
1945         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1946         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1947 }
1948
1949 static int
1950 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1951 {
1952         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
1953
1954         switch (nb_rx_q) {
1955         case 1:
1956         case 2:
1957                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1958                 break;
1959         case 4:
1960                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1961                 break;
1962         default:
1963                 return -EINVAL;
1964         }
1965
1966         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1967         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
1968
1969         return 0;
1970 }
1971
1972 static int
1973 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1974 {
1975         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1977         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1978         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1979
1980         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1981                 /* check multi-queue mode */
1982                 switch (dev_conf->rxmode.mq_mode) {
1983                 case ETH_MQ_RX_VMDQ_DCB:
1984                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1985                         break;
1986                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1987                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1988                         PMD_INIT_LOG(ERR, "SRIOV active,"
1989                                         " unsupported mq_mode rx %d.",
1990                                         dev_conf->rxmode.mq_mode);
1991                         return -EINVAL;
1992                 case ETH_MQ_RX_RSS:
1993                 case ETH_MQ_RX_VMDQ_RSS:
1994                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1995                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1996                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1997                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1998                                                 " invalid queue number"
1999                                                 " for VMDQ RSS, allowed"
2000                                                 " value are 1, 2 or 4.");
2001                                         return -EINVAL;
2002                                 }
2003                         break;
2004                 case ETH_MQ_RX_VMDQ_ONLY:
2005                 case ETH_MQ_RX_NONE:
2006                         /* if nothing mq mode configure, use default scheme */
2007                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2008                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2009                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2010                         break;
2011                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2012                         /* SRIOV only works in VMDq enable mode */
2013                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2014                                         " wrong mq_mode rx %d.",
2015                                         dev_conf->rxmode.mq_mode);
2016                         return -EINVAL;
2017                 }
2018
2019                 switch (dev_conf->txmode.mq_mode) {
2020                 case ETH_MQ_TX_VMDQ_DCB:
2021                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2022                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2023                         break;
2024                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2025                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2026                         break;
2027                 }
2028
2029                 /* check valid queue number */
2030                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2031                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2032                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2033                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2034                                         " must be less than or equal to %d.",
2035                                         nb_rx_q, nb_tx_q,
2036                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2037                         return -EINVAL;
2038                 }
2039         } else {
2040                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2041                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2042                                           " not supported.");
2043                         return -EINVAL;
2044                 }
2045                 /* check configuration for vmdb+dcb mode */
2046                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2047                         const struct rte_eth_vmdq_dcb_conf *conf;
2048
2049                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2050                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2051                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2052                                 return -EINVAL;
2053                         }
2054                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2055                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2056                                conf->nb_queue_pools == ETH_32_POOLS)) {
2057                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2058                                                 " nb_queue_pools must be %d or %d.",
2059                                                 ETH_16_POOLS, ETH_32_POOLS);
2060                                 return -EINVAL;
2061                         }
2062                 }
2063                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2064                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2065
2066                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2067                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2068                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2069                                 return -EINVAL;
2070                         }
2071                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2072                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2073                                conf->nb_queue_pools == ETH_32_POOLS)) {
2074                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2075                                                 " nb_queue_pools != %d and"
2076                                                 " nb_queue_pools != %d.",
2077                                                 ETH_16_POOLS, ETH_32_POOLS);
2078                                 return -EINVAL;
2079                         }
2080                 }
2081
2082                 /* For DCB mode check our configuration before we go further */
2083                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2084                         const struct rte_eth_dcb_rx_conf *conf;
2085
2086                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2087                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2088                                                  IXGBE_DCB_NB_QUEUES);
2089                                 return -EINVAL;
2090                         }
2091                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2092                         if (!(conf->nb_tcs == ETH_4_TCS ||
2093                                conf->nb_tcs == ETH_8_TCS)) {
2094                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2095                                                 " and nb_tcs != %d.",
2096                                                 ETH_4_TCS, ETH_8_TCS);
2097                                 return -EINVAL;
2098                         }
2099                 }
2100
2101                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2102                         const struct rte_eth_dcb_tx_conf *conf;
2103
2104                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2105                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2106                                                  IXGBE_DCB_NB_QUEUES);
2107                                 return -EINVAL;
2108                         }
2109                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2110                         if (!(conf->nb_tcs == ETH_4_TCS ||
2111                                conf->nb_tcs == ETH_8_TCS)) {
2112                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2113                                                 " and nb_tcs != %d.",
2114                                                 ETH_4_TCS, ETH_8_TCS);
2115                                 return -EINVAL;
2116                         }
2117                 }
2118
2119                 /*
2120                  * When DCB/VT is off, maximum number of queues changes,
2121                  * except for 82598EB, which remains constant.
2122                  */
2123                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2124                                 hw->mac.type != ixgbe_mac_82598EB) {
2125                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2126                                 PMD_INIT_LOG(ERR,
2127                                              "Neither VT nor DCB are enabled, "
2128                                              "nb_tx_q > %d.",
2129                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2130                                 return -EINVAL;
2131                         }
2132                 }
2133         }
2134         return 0;
2135 }
2136
2137 static int
2138 ixgbe_dev_configure(struct rte_eth_dev *dev)
2139 {
2140         struct ixgbe_interrupt *intr =
2141                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2142         struct ixgbe_adapter *adapter =
2143                 (struct ixgbe_adapter *)dev->data->dev_private;
2144         int ret;
2145
2146         PMD_INIT_FUNC_TRACE();
2147         /* multipe queue mode checking */
2148         ret  = ixgbe_check_mq_mode(dev);
2149         if (ret != 0) {
2150                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2151                             ret);
2152                 return ret;
2153         }
2154
2155         /* set flag to update link status after init */
2156         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2157
2158         /*
2159          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2160          * allocation or vector Rx preconditions we will reset it.
2161          */
2162         adapter->rx_bulk_alloc_allowed = true;
2163         adapter->rx_vec_allowed = true;
2164
2165         return 0;
2166 }
2167
2168 static void
2169 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2170 {
2171         struct ixgbe_hw *hw =
2172                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173         struct ixgbe_interrupt *intr =
2174                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2175         uint32_t gpie;
2176
2177         /* only set up it on X550EM_X */
2178         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2179                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2180                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2181                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2182                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2183                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2184         }
2185 }
2186
2187 /*
2188  * Configure device link speed and setup link.
2189  * It returns 0 on success.
2190  */
2191 static int
2192 ixgbe_dev_start(struct rte_eth_dev *dev)
2193 {
2194         struct ixgbe_hw *hw =
2195                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196         struct ixgbe_vf_info *vfinfo =
2197                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2198         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2199         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2200         uint32_t intr_vector = 0;
2201         int err, link_up = 0, negotiate = 0;
2202         uint32_t speed = 0;
2203         int mask = 0;
2204         int status;
2205         uint16_t vf, idx;
2206         uint32_t *link_speeds;
2207
2208         PMD_INIT_FUNC_TRACE();
2209
2210         /* IXGBE devices don't support:
2211         *    - half duplex (checked afterwards for valid speeds)
2212         *    - fixed speed: TODO implement
2213         */
2214         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2215                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2216                              dev->data->port_id);
2217                 return -EINVAL;
2218         }
2219
2220         /* disable uio/vfio intr/eventfd mapping */
2221         rte_intr_disable(intr_handle);
2222
2223         /* stop adapter */
2224         hw->adapter_stopped = 0;
2225         ixgbe_stop_adapter(hw);
2226
2227         /* reinitialize adapter
2228          * this calls reset and start
2229          */
2230         status = ixgbe_pf_reset_hw(hw);
2231         if (status != 0)
2232                 return -1;
2233         hw->mac.ops.start_hw(hw);
2234         hw->mac.get_link_status = true;
2235
2236         /* configure PF module if SRIOV enabled */
2237         ixgbe_pf_host_configure(dev);
2238
2239         ixgbe_dev_phy_intr_setup(dev);
2240
2241         /* check and configure queue intr-vector mapping */
2242         if ((rte_intr_cap_multiple(intr_handle) ||
2243              !RTE_ETH_DEV_SRIOV(dev).active) &&
2244             dev->data->dev_conf.intr_conf.rxq != 0) {
2245                 intr_vector = dev->data->nb_rx_queues;
2246                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2247                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2248                                         IXGBE_MAX_INTR_QUEUE_NUM);
2249                         return -ENOTSUP;
2250                 }
2251                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2252                         return -1;
2253         }
2254
2255         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2256                 intr_handle->intr_vec =
2257                         rte_zmalloc("intr_vec",
2258                                     dev->data->nb_rx_queues * sizeof(int), 0);
2259                 if (intr_handle->intr_vec == NULL) {
2260                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2261                                      " intr_vec\n", dev->data->nb_rx_queues);
2262                         return -ENOMEM;
2263                 }
2264         }
2265
2266         /* confiugre msix for sleep until rx interrupt */
2267         ixgbe_configure_msix(dev);
2268
2269         /* initialize transmission unit */
2270         ixgbe_dev_tx_init(dev);
2271
2272         /* This can fail when allocating mbufs for descriptor rings */
2273         err = ixgbe_dev_rx_init(dev);
2274         if (err) {
2275                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2276                 goto error;
2277         }
2278
2279     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2280                 ETH_VLAN_EXTEND_MASK;
2281         ixgbe_vlan_offload_set(dev, mask);
2282
2283         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2284                 /* Enable vlan filtering for VMDq */
2285                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2286         }
2287
2288         /* Configure DCB hw */
2289         ixgbe_configure_dcb(dev);
2290
2291         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2292                 err = ixgbe_fdir_configure(dev);
2293                 if (err)
2294                         goto error;
2295         }
2296
2297         /* Restore vf rate limit */
2298         if (vfinfo != NULL) {
2299                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2300                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2301                                 if (vfinfo[vf].tx_rate[idx] != 0)
2302                                         ixgbe_set_vf_rate_limit(dev, vf,
2303                                                 vfinfo[vf].tx_rate[idx],
2304                                                 1 << idx);
2305         }
2306
2307         ixgbe_restore_statistics_mapping(dev);
2308
2309         err = ixgbe_dev_rxtx_start(dev);
2310         if (err < 0) {
2311                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2312                 goto error;
2313         }
2314
2315         /* Skip link setup if loopback mode is enabled for 82599. */
2316         if (hw->mac.type == ixgbe_mac_82599EB &&
2317                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2318                 goto skip_link_setup;
2319
2320         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2321                 err = hw->mac.ops.setup_sfp(hw);
2322                 if (err)
2323                         goto error;
2324         }
2325
2326         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2327                 /* Turn on the copper */
2328                 ixgbe_set_phy_power(hw, true);
2329         } else {
2330                 /* Turn on the laser */
2331                 ixgbe_enable_tx_laser(hw);
2332         }
2333
2334         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2335         if (err)
2336                 goto error;
2337         dev->data->dev_link.link_status = link_up;
2338
2339         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2340         if (err)
2341                 goto error;
2342
2343         link_speeds = &dev->data->dev_conf.link_speeds;
2344         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2345                         ETH_LINK_SPEED_10G)) {
2346                 PMD_INIT_LOG(ERR, "Invalid link setting");
2347                 goto error;
2348         }
2349
2350         speed = 0x0;
2351         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2352                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2353                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2354                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2355         } else {
2356                 if (*link_speeds & ETH_LINK_SPEED_10G)
2357                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2358                 if (*link_speeds & ETH_LINK_SPEED_1G)
2359                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2360                 if (*link_speeds & ETH_LINK_SPEED_100M)
2361                         speed |= IXGBE_LINK_SPEED_100_FULL;
2362         }
2363
2364         err = ixgbe_setup_link(hw, speed, link_up);
2365         if (err)
2366                 goto error;
2367
2368 skip_link_setup:
2369
2370         if (rte_intr_allow_others(intr_handle)) {
2371                 /* check if lsc interrupt is enabled */
2372                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2373                         ixgbe_dev_lsc_interrupt_setup(dev);
2374         } else {
2375                 rte_intr_callback_unregister(intr_handle,
2376                                              ixgbe_dev_interrupt_handler, dev);
2377                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2378                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2379                                      " no intr multiplex\n");
2380         }
2381
2382         /* check if rxq interrupt is enabled */
2383         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2384             rte_intr_dp_is_en(intr_handle))
2385                 ixgbe_dev_rxq_interrupt_setup(dev);
2386
2387         /* enable uio/vfio intr/eventfd mapping */
2388         rte_intr_enable(intr_handle);
2389
2390         /* resume enabled intr since hw reset */
2391         ixgbe_enable_intr(dev);
2392
2393         return 0;
2394
2395 error:
2396         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2397         ixgbe_dev_clear_queues(dev);
2398         return -EIO;
2399 }
2400
2401 /*
2402  * Stop device: disable rx and tx functions to allow for reconfiguring.
2403  */
2404 static void
2405 ixgbe_dev_stop(struct rte_eth_dev *dev)
2406 {
2407         struct rte_eth_link link;
2408         struct ixgbe_hw *hw =
2409                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2410         struct ixgbe_vf_info *vfinfo =
2411                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2412         struct ixgbe_filter_info *filter_info =
2413                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2414         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2415         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2416         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2417         int vf;
2418
2419         PMD_INIT_FUNC_TRACE();
2420
2421         /* disable interrupts */
2422         ixgbe_disable_intr(hw);
2423
2424         /* reset the NIC */
2425         ixgbe_pf_reset_hw(hw);
2426         hw->adapter_stopped = 0;
2427
2428         /* stop adapter */
2429         ixgbe_stop_adapter(hw);
2430
2431         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2432                 vfinfo[vf].clear_to_send = false;
2433
2434         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2435                 /* Turn off the copper */
2436                 ixgbe_set_phy_power(hw, false);
2437         } else {
2438                 /* Turn off the laser */
2439                 ixgbe_disable_tx_laser(hw);
2440         }
2441
2442         ixgbe_dev_clear_queues(dev);
2443
2444         /* Clear stored conf */
2445         dev->data->scattered_rx = 0;
2446         dev->data->lro = 0;
2447
2448         /* Clear recorded link status */
2449         memset(&link, 0, sizeof(link));
2450         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2451
2452         /* Remove all ntuple filters of the device */
2453         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2454              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2455                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2456                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2457                              p_5tuple, entries);
2458                 rte_free(p_5tuple);
2459         }
2460         memset(filter_info->fivetuple_mask, 0,
2461                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2462
2463         if (!rte_intr_allow_others(intr_handle))
2464                 /* resume to the default handler */
2465                 rte_intr_callback_register(intr_handle,
2466                                            ixgbe_dev_interrupt_handler,
2467                                            (void *)dev);
2468
2469         /* Clean datapath event and queue/vec mapping */
2470         rte_intr_efd_disable(intr_handle);
2471         if (intr_handle->intr_vec != NULL) {
2472                 rte_free(intr_handle->intr_vec);
2473                 intr_handle->intr_vec = NULL;
2474         }
2475 }
2476
2477 /*
2478  * Set device link up: enable tx.
2479  */
2480 static int
2481 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2482 {
2483         struct ixgbe_hw *hw =
2484                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2485         if (hw->mac.type == ixgbe_mac_82599EB) {
2486 #ifdef RTE_NIC_BYPASS
2487                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2488                         /* Not suported in bypass mode */
2489                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2490                                      "by device id 0x%x", hw->device_id);
2491                         return -ENOTSUP;
2492                 }
2493 #endif
2494         }
2495
2496         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2497                 /* Turn on the copper */
2498                 ixgbe_set_phy_power(hw, true);
2499         } else {
2500                 /* Turn on the laser */
2501                 ixgbe_enable_tx_laser(hw);
2502         }
2503
2504         return 0;
2505 }
2506
2507 /*
2508  * Set device link down: disable tx.
2509  */
2510 static int
2511 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2512 {
2513         struct ixgbe_hw *hw =
2514                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2515         if (hw->mac.type == ixgbe_mac_82599EB) {
2516 #ifdef RTE_NIC_BYPASS
2517                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2518                         /* Not suported in bypass mode */
2519                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2520                                      "by device id 0x%x", hw->device_id);
2521                         return -ENOTSUP;
2522                 }
2523 #endif
2524         }
2525
2526         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2527                 /* Turn off the copper */
2528                 ixgbe_set_phy_power(hw, false);
2529         } else {
2530                 /* Turn off the laser */
2531                 ixgbe_disable_tx_laser(hw);
2532         }
2533
2534         return 0;
2535 }
2536
2537 /*
2538  * Reest and stop device.
2539  */
2540 static void
2541 ixgbe_dev_close(struct rte_eth_dev *dev)
2542 {
2543         struct ixgbe_hw *hw =
2544                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2545
2546         PMD_INIT_FUNC_TRACE();
2547
2548         ixgbe_pf_reset_hw(hw);
2549
2550         ixgbe_dev_stop(dev);
2551         hw->adapter_stopped = 1;
2552
2553         ixgbe_dev_free_queues(dev);
2554
2555         ixgbe_disable_pcie_master(hw);
2556
2557         /* reprogram the RAR[0] in case user changed it. */
2558         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2559 }
2560
2561 static void
2562 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2563                            struct ixgbe_hw_stats *hw_stats,
2564                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2565                            uint64_t *total_qprc, uint64_t *total_qprdc)
2566 {
2567         uint32_t bprc, lxon, lxoff, total;
2568         uint32_t delta_gprc = 0;
2569         unsigned i;
2570         /* Workaround for RX byte count not including CRC bytes when CRC
2571 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2572          * is disabled.
2573 +        */
2574         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2575                         IXGBE_HLREG0_RXCRCSTRP);
2576
2577         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2578         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2579         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2580         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2581
2582         for (i = 0; i < 8; i++) {
2583                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2584
2585                 /* global total per queue */
2586                 hw_stats->mpc[i] += mp;
2587                 /* Running comprehensive total for stats display */
2588                 *total_missed_rx += hw_stats->mpc[i];
2589                 if (hw->mac.type == ixgbe_mac_82598EB) {
2590                         hw_stats->rnbc[i] +=
2591                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2592                         hw_stats->pxonrxc[i] +=
2593                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2594                         hw_stats->pxoffrxc[i] +=
2595                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2596                 } else {
2597                         hw_stats->pxonrxc[i] +=
2598                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2599                         hw_stats->pxoffrxc[i] +=
2600                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2601                         hw_stats->pxon2offc[i] +=
2602                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2603                 }
2604                 hw_stats->pxontxc[i] +=
2605                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2606                 hw_stats->pxofftxc[i] +=
2607                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2608         }
2609         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2610                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2611                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2612                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2613
2614                 delta_gprc += delta_qprc;
2615
2616                 hw_stats->qprc[i] += delta_qprc;
2617                 hw_stats->qptc[i] += delta_qptc;
2618
2619                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2620                 hw_stats->qbrc[i] +=
2621                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2622                 if (crc_strip == 0)
2623                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2624
2625                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2626                 hw_stats->qbtc[i] +=
2627                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2628
2629                 hw_stats->qprdc[i] += delta_qprdc;
2630                 *total_qprdc += hw_stats->qprdc[i];
2631
2632                 *total_qprc += hw_stats->qprc[i];
2633                 *total_qbrc += hw_stats->qbrc[i];
2634         }
2635         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2636         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2637         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2638
2639         /*
2640          * An errata states that gprc actually counts good + missed packets:
2641          * Workaround to set gprc to summated queue packet receives
2642          */
2643         hw_stats->gprc = *total_qprc;
2644
2645         if (hw->mac.type != ixgbe_mac_82598EB) {
2646                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2647                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2648                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2649                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2650                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2651                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2652                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2653                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2654         } else {
2655                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2656                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2657                 /* 82598 only has a counter in the high register */
2658                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2659                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2660                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2661         }
2662         uint64_t old_tpr = hw_stats->tpr;
2663
2664         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2665         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2666
2667         if (crc_strip == 0)
2668                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2669
2670         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2671         hw_stats->gptc += delta_gptc;
2672         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2673         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2674
2675         /*
2676          * Workaround: mprc hardware is incorrectly counting
2677          * broadcasts, so for now we subtract those.
2678          */
2679         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2680         hw_stats->bprc += bprc;
2681         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2682         if (hw->mac.type == ixgbe_mac_82598EB)
2683                 hw_stats->mprc -= bprc;
2684
2685         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2686         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2687         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2688         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2689         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2690         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2691
2692         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2693         hw_stats->lxontxc += lxon;
2694         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2695         hw_stats->lxofftxc += lxoff;
2696         total = lxon + lxoff;
2697
2698         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2699         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2700         hw_stats->gptc -= total;
2701         hw_stats->mptc -= total;
2702         hw_stats->ptc64 -= total;
2703         hw_stats->gotc -= total * ETHER_MIN_LEN;
2704
2705         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2706         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2707         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2708         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2709         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2710         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2711         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2712         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2713         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2714         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2715         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2716         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2717         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2718         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2719         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2720         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2721         /* Only read FCOE on 82599 */
2722         if (hw->mac.type != ixgbe_mac_82598EB) {
2723                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2724                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2725                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2726                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2727                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2728         }
2729
2730         /* Flow Director Stats registers */
2731         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2732         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2733 }
2734
2735 /*
2736  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2737  */
2738 static void
2739 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2740 {
2741         struct ixgbe_hw *hw =
2742                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2743         struct ixgbe_hw_stats *hw_stats =
2744                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2745         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2746         unsigned i;
2747
2748         total_missed_rx = 0;
2749         total_qbrc = 0;
2750         total_qprc = 0;
2751         total_qprdc = 0;
2752
2753         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2754                         &total_qprc, &total_qprdc);
2755
2756         if (stats == NULL)
2757                 return;
2758
2759         /* Fill out the rte_eth_stats statistics structure */
2760         stats->ipackets = total_qprc;
2761         stats->ibytes = total_qbrc;
2762         stats->opackets = hw_stats->gptc;
2763         stats->obytes = hw_stats->gotc;
2764
2765         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2766                 stats->q_ipackets[i] = hw_stats->qprc[i];
2767                 stats->q_opackets[i] = hw_stats->qptc[i];
2768                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2769                 stats->q_obytes[i] = hw_stats->qbtc[i];
2770                 stats->q_errors[i] = hw_stats->qprdc[i];
2771         }
2772
2773         /* Rx Errors */
2774         stats->imissed  = total_missed_rx;
2775         stats->ierrors  = hw_stats->crcerrs +
2776                           hw_stats->mspdc +
2777                           hw_stats->rlec +
2778                           hw_stats->ruc +
2779                           hw_stats->roc +
2780                           hw_stats->illerrc +
2781                           hw_stats->errbc +
2782                           hw_stats->rfc +
2783                           hw_stats->fccrc +
2784                           hw_stats->fclast;
2785
2786         /* Tx Errors */
2787         stats->oerrors  = 0;
2788 }
2789
2790 static void
2791 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2792 {
2793         struct ixgbe_hw_stats *stats =
2794                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2795
2796         /* HW registers are cleared on read */
2797         ixgbe_dev_stats_get(dev, NULL);
2798
2799         /* Reset software totals */
2800         memset(stats, 0, sizeof(*stats));
2801 }
2802
2803 /* This function calculates the number of xstats based on the current config */
2804 static unsigned
2805 ixgbe_xstats_calc_num(void) {
2806         return IXGBE_NB_HW_STATS +
2807                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2808                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2809 }
2810
2811 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2812         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2813 {
2814         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2815         unsigned stat, i, count;
2816
2817         if (xstats_names != NULL) {
2818                 count = 0;
2819
2820                 /* Note: limit >= cnt_stats checked upstream
2821                  * in rte_eth_xstats_names()
2822                  */
2823
2824                 /* Extended stats from ixgbe_hw_stats */
2825                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2826                         snprintf(xstats_names[count].name,
2827                                 sizeof(xstats_names[count].name),
2828                                 "%s",
2829                                 rte_ixgbe_stats_strings[i].name);
2830                         count++;
2831                 }
2832
2833                 /* RX Priority Stats */
2834                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2835                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2836                                 snprintf(xstats_names[count].name,
2837                                         sizeof(xstats_names[count].name),
2838                                         "rx_priority%u_%s", i,
2839                                         rte_ixgbe_rxq_strings[stat].name);
2840                                 count++;
2841                         }
2842                 }
2843
2844                 /* TX Priority Stats */
2845                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2846                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2847                                 snprintf(xstats_names[count].name,
2848                                         sizeof(xstats_names[count].name),
2849                                         "tx_priority%u_%s", i,
2850                                         rte_ixgbe_txq_strings[stat].name);
2851                                 count++;
2852                         }
2853                 }
2854         }
2855         return cnt_stats;
2856 }
2857
2858 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2859         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2860 {
2861         unsigned i;
2862
2863         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2864                 return -ENOMEM;
2865
2866         if (xstats_names != NULL)
2867                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2868                         snprintf(xstats_names[i].name,
2869                                 sizeof(xstats_names[i].name),
2870                                 "%s", rte_ixgbevf_stats_strings[i].name);
2871         return IXGBEVF_NB_XSTATS;
2872 }
2873
2874 static int
2875 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2876                                          unsigned n)
2877 {
2878         struct ixgbe_hw *hw =
2879                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2880         struct ixgbe_hw_stats *hw_stats =
2881                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2882         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2883         unsigned i, stat, count = 0;
2884
2885         count = ixgbe_xstats_calc_num();
2886
2887         if (n < count)
2888                 return count;
2889
2890         total_missed_rx = 0;
2891         total_qbrc = 0;
2892         total_qprc = 0;
2893         total_qprdc = 0;
2894
2895         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2896                                    &total_qprc, &total_qprdc);
2897
2898         /* If this is a reset xstats is NULL, and we have cleared the
2899          * registers by reading them.
2900          */
2901         if (!xstats)
2902                 return 0;
2903
2904         /* Extended stats from ixgbe_hw_stats */
2905         count = 0;
2906         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2907                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2908                                 rte_ixgbe_stats_strings[i].offset);
2909                 xstats[count].id = count;
2910                 count++;
2911         }
2912
2913         /* RX Priority Stats */
2914         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2915                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2916                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2917                                         rte_ixgbe_rxq_strings[stat].offset +
2918                                         (sizeof(uint64_t) * i));
2919                         xstats[count].id = count;
2920                         count++;
2921                 }
2922         }
2923
2924         /* TX Priority Stats */
2925         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2926                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2927                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2928                                         rte_ixgbe_txq_strings[stat].offset +
2929                                         (sizeof(uint64_t) * i));
2930                         xstats[count].id = count;
2931                         count++;
2932                 }
2933         }
2934         return count;
2935 }
2936
2937 static void
2938 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2939 {
2940         struct ixgbe_hw_stats *stats =
2941                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2942
2943         unsigned count = ixgbe_xstats_calc_num();
2944
2945         /* HW registers are cleared on read */
2946         ixgbe_dev_xstats_get(dev, NULL, count);
2947
2948         /* Reset software totals */
2949         memset(stats, 0, sizeof(*stats));
2950 }
2951
2952 static void
2953 ixgbevf_update_stats(struct rte_eth_dev *dev)
2954 {
2955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2956         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2957                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2958
2959         /* Good Rx packet, include VF loopback */
2960         UPDATE_VF_STAT(IXGBE_VFGPRC,
2961             hw_stats->last_vfgprc, hw_stats->vfgprc);
2962
2963         /* Good Rx octets, include VF loopback */
2964         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2965             hw_stats->last_vfgorc, hw_stats->vfgorc);
2966
2967         /* Good Tx packet, include VF loopback */
2968         UPDATE_VF_STAT(IXGBE_VFGPTC,
2969             hw_stats->last_vfgptc, hw_stats->vfgptc);
2970
2971         /* Good Tx octets, include VF loopback */
2972         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2973             hw_stats->last_vfgotc, hw_stats->vfgotc);
2974
2975         /* Rx Multicst Packet */
2976         UPDATE_VF_STAT(IXGBE_VFMPRC,
2977             hw_stats->last_vfmprc, hw_stats->vfmprc);
2978 }
2979
2980 static int
2981 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2982                        unsigned n)
2983 {
2984         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2985                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2986         unsigned i;
2987
2988         if (n < IXGBEVF_NB_XSTATS)
2989                 return IXGBEVF_NB_XSTATS;
2990
2991         ixgbevf_update_stats(dev);
2992
2993         if (!xstats)
2994                 return 0;
2995
2996         /* Extended stats */
2997         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2998                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2999                         rte_ixgbevf_stats_strings[i].offset);
3000         }
3001
3002         return IXGBEVF_NB_XSTATS;
3003 }
3004
3005 static void
3006 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3007 {
3008         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3009                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3010
3011         ixgbevf_update_stats(dev);
3012
3013         if (stats == NULL)
3014                 return;
3015
3016         stats->ipackets = hw_stats->vfgprc;
3017         stats->ibytes = hw_stats->vfgorc;
3018         stats->opackets = hw_stats->vfgptc;
3019         stats->obytes = hw_stats->vfgotc;
3020 }
3021
3022 static void
3023 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3024 {
3025         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3026                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3027
3028         /* Sync HW register to the last stats */
3029         ixgbevf_dev_stats_get(dev, NULL);
3030
3031         /* reset HW current stats*/
3032         hw_stats->vfgprc = 0;
3033         hw_stats->vfgorc = 0;
3034         hw_stats->vfgptc = 0;
3035         hw_stats->vfgotc = 0;
3036 }
3037
3038 static void
3039 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3040 {
3041         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3043         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3044
3045         dev_info->pci_dev = pci_dev;
3046         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3047         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3048         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3049                 /*
3050                  * When DCB/VT is off, maximum number of queues changes,
3051                  * except for 82598EB, which remains constant.
3052                  */
3053                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3054                                 hw->mac.type != ixgbe_mac_82598EB)
3055                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3056         }
3057         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3058         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3059         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3060         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3061         dev_info->max_vfs = pci_dev->max_vfs;
3062         if (hw->mac.type == ixgbe_mac_82598EB)
3063                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3064         else
3065                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3066         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3067         dev_info->rx_offload_capa =
3068                 DEV_RX_OFFLOAD_VLAN_STRIP |
3069                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3070                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3071                 DEV_RX_OFFLOAD_TCP_CKSUM;
3072
3073         /*
3074          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3075          * mode.
3076          */
3077         if ((hw->mac.type == ixgbe_mac_82599EB ||
3078              hw->mac.type == ixgbe_mac_X540) &&
3079             !RTE_ETH_DEV_SRIOV(dev).active)
3080                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3081
3082         if (hw->mac.type == ixgbe_mac_X550 ||
3083             hw->mac.type == ixgbe_mac_X550EM_x ||
3084             hw->mac.type == ixgbe_mac_X550EM_a)
3085                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3086
3087         dev_info->tx_offload_capa =
3088                 DEV_TX_OFFLOAD_VLAN_INSERT |
3089                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3090                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3091                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3092                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3093                 DEV_TX_OFFLOAD_TCP_TSO;
3094
3095         if (hw->mac.type == ixgbe_mac_X550 ||
3096             hw->mac.type == ixgbe_mac_X550EM_x ||
3097             hw->mac.type == ixgbe_mac_X550EM_a)
3098                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3099
3100         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3101                 .rx_thresh = {
3102                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3103                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3104                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3105                 },
3106                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3107                 .rx_drop_en = 0,
3108         };
3109
3110         dev_info->default_txconf = (struct rte_eth_txconf) {
3111                 .tx_thresh = {
3112                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3113                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3114                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3115                 },
3116                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3117                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3118                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3119                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3120         };
3121
3122         dev_info->rx_desc_lim = rx_desc_lim;
3123         dev_info->tx_desc_lim = tx_desc_lim;
3124
3125         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3126         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3127         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3128
3129         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3130         if (hw->mac.type == ixgbe_mac_X540 ||
3131             hw->mac.type == ixgbe_mac_X540_vf ||
3132             hw->mac.type == ixgbe_mac_X550 ||
3133             hw->mac.type == ixgbe_mac_X550_vf) {
3134                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3135         }
3136 }
3137
3138 static const uint32_t *
3139 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3140 {
3141         static const uint32_t ptypes[] = {
3142                 /* For non-vec functions,
3143                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3144                  * for vec functions,
3145                  * refers to _recv_raw_pkts_vec().
3146                  */
3147                 RTE_PTYPE_L2_ETHER,
3148                 RTE_PTYPE_L3_IPV4,
3149                 RTE_PTYPE_L3_IPV4_EXT,
3150                 RTE_PTYPE_L3_IPV6,
3151                 RTE_PTYPE_L3_IPV6_EXT,
3152                 RTE_PTYPE_L4_SCTP,
3153                 RTE_PTYPE_L4_TCP,
3154                 RTE_PTYPE_L4_UDP,
3155                 RTE_PTYPE_TUNNEL_IP,
3156                 RTE_PTYPE_INNER_L3_IPV6,
3157                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3158                 RTE_PTYPE_INNER_L4_TCP,
3159                 RTE_PTYPE_INNER_L4_UDP,
3160                 RTE_PTYPE_UNKNOWN
3161         };
3162
3163         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3164             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3165             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3166             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3167                 return ptypes;
3168         return NULL;
3169 }
3170
3171 static void
3172 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3173                      struct rte_eth_dev_info *dev_info)
3174 {
3175         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3176         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3177
3178         dev_info->pci_dev = pci_dev;
3179         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3180         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3181         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3182         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3183         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3184         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3185         dev_info->max_vfs = pci_dev->max_vfs;
3186         if (hw->mac.type == ixgbe_mac_82598EB)
3187                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3188         else
3189                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3190         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3191                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3192                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3193                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3194         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3195                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3196                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3197                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3198                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3199                                 DEV_TX_OFFLOAD_TCP_TSO;
3200
3201         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3202                 .rx_thresh = {
3203                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3204                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3205                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3206                 },
3207                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3208                 .rx_drop_en = 0,
3209         };
3210
3211         dev_info->default_txconf = (struct rte_eth_txconf) {
3212                 .tx_thresh = {
3213                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3214                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3215                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3216                 },
3217                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3218                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3219                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3220                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3221         };
3222
3223         dev_info->rx_desc_lim = rx_desc_lim;
3224         dev_info->tx_desc_lim = tx_desc_lim;
3225 }
3226
3227 /* return 0 means link status changed, -1 means not changed */
3228 static int
3229 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3230 {
3231         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3232         struct rte_eth_link link, old;
3233         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3234         int link_up;
3235         int diag;
3236
3237         link.link_status = ETH_LINK_DOWN;
3238         link.link_speed = 0;
3239         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3240         memset(&old, 0, sizeof(old));
3241         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3242
3243         hw->mac.get_link_status = true;
3244
3245         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3246         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3247                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3248         else
3249                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3250
3251         if (diag != 0) {
3252                 link.link_speed = ETH_SPEED_NUM_100M;
3253                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3254                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3255                 if (link.link_status == old.link_status)
3256                         return -1;
3257                 return 0;
3258         }
3259
3260         if (link_up == 0) {
3261                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3262                 if (link.link_status == old.link_status)
3263                         return -1;
3264                 return 0;
3265         }
3266         link.link_status = ETH_LINK_UP;
3267         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3268
3269         switch (link_speed) {
3270         default:
3271         case IXGBE_LINK_SPEED_UNKNOWN:
3272                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3273                 link.link_speed = ETH_SPEED_NUM_100M;
3274                 break;
3275
3276         case IXGBE_LINK_SPEED_100_FULL:
3277                 link.link_speed = ETH_SPEED_NUM_100M;
3278                 break;
3279
3280         case IXGBE_LINK_SPEED_1GB_FULL:
3281                 link.link_speed = ETH_SPEED_NUM_1G;
3282                 break;
3283
3284         case IXGBE_LINK_SPEED_10GB_FULL:
3285                 link.link_speed = ETH_SPEED_NUM_10G;
3286                 break;
3287         }
3288         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3289
3290         if (link.link_status == old.link_status)
3291                 return -1;
3292
3293         return 0;
3294 }
3295
3296 static void
3297 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3298 {
3299         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300         uint32_t fctrl;
3301
3302         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3303         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3304         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3305 }
3306
3307 static void
3308 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3309 {
3310         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3311         uint32_t fctrl;
3312
3313         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3314         fctrl &= (~IXGBE_FCTRL_UPE);
3315         if (dev->data->all_multicast == 1)
3316                 fctrl |= IXGBE_FCTRL_MPE;
3317         else
3318                 fctrl &= (~IXGBE_FCTRL_MPE);
3319         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3320 }
3321
3322 static void
3323 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3324 {
3325         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3326         uint32_t fctrl;
3327
3328         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3329         fctrl |= IXGBE_FCTRL_MPE;
3330         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3331 }
3332
3333 static void
3334 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3335 {
3336         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337         uint32_t fctrl;
3338
3339         if (dev->data->promiscuous == 1)
3340                 return; /* must remain in all_multicast mode */
3341
3342         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3343         fctrl &= (~IXGBE_FCTRL_MPE);
3344         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3345 }
3346
3347 /**
3348  * It clears the interrupt causes and enables the interrupt.
3349  * It will be called once only during nic initialized.
3350  *
3351  * @param dev
3352  *  Pointer to struct rte_eth_dev.
3353  *
3354  * @return
3355  *  - On success, zero.
3356  *  - On failure, a negative value.
3357  */
3358 static int
3359 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3360 {
3361         struct ixgbe_interrupt *intr =
3362                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3363
3364         ixgbe_dev_link_status_print(dev);
3365         intr->mask |= IXGBE_EICR_LSC;
3366
3367         return 0;
3368 }
3369
3370 /**
3371  * It clears the interrupt causes and enables the interrupt.
3372  * It will be called once only during nic initialized.
3373  *
3374  * @param dev
3375  *  Pointer to struct rte_eth_dev.
3376  *
3377  * @return
3378  *  - On success, zero.
3379  *  - On failure, a negative value.
3380  */
3381 static int
3382 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3383 {
3384         struct ixgbe_interrupt *intr =
3385                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3386
3387         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3388
3389         return 0;
3390 }
3391
3392 /*
3393  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3394  *
3395  * @param dev
3396  *  Pointer to struct rte_eth_dev.
3397  *
3398  * @return
3399  *  - On success, zero.
3400  *  - On failure, a negative value.
3401  */
3402 static int
3403 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3404 {
3405         uint32_t eicr;
3406         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3407         struct ixgbe_interrupt *intr =
3408                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3409
3410         /* clear all cause mask */
3411         ixgbe_disable_intr(hw);
3412
3413         /* read-on-clear nic registers here */
3414         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3415         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3416
3417         intr->flags = 0;
3418
3419         /* set flag for async link update */
3420         if (eicr & IXGBE_EICR_LSC)
3421                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3422
3423         if (eicr & IXGBE_EICR_MAILBOX)
3424                 intr->flags |= IXGBE_FLAG_MAILBOX;
3425
3426         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3427             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3428             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3429                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3430
3431         return 0;
3432 }
3433
3434 /**
3435  * It gets and then prints the link status.
3436  *
3437  * @param dev
3438  *  Pointer to struct rte_eth_dev.
3439  *
3440  * @return
3441  *  - On success, zero.
3442  *  - On failure, a negative value.
3443  */
3444 static void
3445 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3446 {
3447         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3448         struct rte_eth_link link;
3449
3450         memset(&link, 0, sizeof(link));
3451         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3452         if (link.link_status) {
3453                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3454                                         (int)(dev->data->port_id),
3455                                         (unsigned)link.link_speed,
3456                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3457                                         "full-duplex" : "half-duplex");
3458         } else {
3459                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3460                                 (int)(dev->data->port_id));
3461         }
3462         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3463                                 pci_dev->addr.domain,
3464                                 pci_dev->addr.bus,
3465                                 pci_dev->addr.devid,
3466                                 pci_dev->addr.function);
3467 }
3468
3469 /*
3470  * It executes link_update after knowing an interrupt occurred.
3471  *
3472  * @param dev
3473  *  Pointer to struct rte_eth_dev.
3474  *
3475  * @return
3476  *  - On success, zero.
3477  *  - On failure, a negative value.
3478  */
3479 static int
3480 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3481                            struct rte_intr_handle *intr_handle)
3482 {
3483         struct ixgbe_interrupt *intr =
3484                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3485         int64_t timeout;
3486         struct rte_eth_link link;
3487         int intr_enable_delay = false;
3488         struct ixgbe_hw *hw =
3489                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3490
3491         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3492
3493         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3494                 ixgbe_pf_mbx_process(dev);
3495                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3496         }
3497
3498         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3499                 ixgbe_handle_lasi(hw);
3500                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3501         }
3502
3503         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3504                 /* get the link status before link update, for predicting later */
3505                 memset(&link, 0, sizeof(link));
3506                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3507
3508                 ixgbe_dev_link_update(dev, 0);
3509
3510                 /* likely to up */
3511                 if (!link.link_status)
3512                         /* handle it 1 sec later, wait it being stable */
3513                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3514                 /* likely to down */
3515                 else
3516                         /* handle it 4 sec later, wait it being stable */
3517                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3518
3519                 ixgbe_dev_link_status_print(dev);
3520
3521                 intr_enable_delay = true;
3522         }
3523
3524         if (intr_enable_delay) {
3525                 if (rte_eal_alarm_set(timeout * 1000,
3526                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3527                         PMD_DRV_LOG(ERR, "Error setting alarm");
3528         } else {
3529                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3530                 ixgbe_enable_intr(dev);
3531                 rte_intr_enable(intr_handle);
3532         }
3533
3534
3535         return 0;
3536 }
3537
3538 /**
3539  * Interrupt handler which shall be registered for alarm callback for delayed
3540  * handling specific interrupt to wait for the stable nic state. As the
3541  * NIC interrupt state is not stable for ixgbe after link is just down,
3542  * it needs to wait 4 seconds to get the stable status.
3543  *
3544  * @param handle
3545  *  Pointer to interrupt handle.
3546  * @param param
3547  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3548  *
3549  * @return
3550  *  void
3551  */
3552 static void
3553 ixgbe_dev_interrupt_delayed_handler(void *param)
3554 {
3555         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3556         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3557         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3558         struct ixgbe_interrupt *intr =
3559                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3560         struct ixgbe_hw *hw =
3561                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3562         uint32_t eicr;
3563
3564         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3565         if (eicr & IXGBE_EICR_MAILBOX)
3566                 ixgbe_pf_mbx_process(dev);
3567
3568         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3569                 ixgbe_handle_lasi(hw);
3570                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3571         }
3572
3573         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3574                 ixgbe_dev_link_update(dev, 0);
3575                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3576                 ixgbe_dev_link_status_print(dev);
3577                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3578         }
3579
3580         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3581         ixgbe_enable_intr(dev);
3582         rte_intr_enable(intr_handle);
3583 }
3584
3585 /**
3586  * Interrupt handler triggered by NIC  for handling
3587  * specific interrupt.
3588  *
3589  * @param handle
3590  *  Pointer to interrupt handle.
3591  * @param param
3592  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3593  *
3594  * @return
3595  *  void
3596  */
3597 static void
3598 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3599                             void *param)
3600 {
3601         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3602
3603         ixgbe_dev_interrupt_get_status(dev);
3604         ixgbe_dev_interrupt_action(dev, handle);
3605 }
3606
3607 static int
3608 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3609 {
3610         struct ixgbe_hw *hw;
3611
3612         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3613         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3614 }
3615
3616 static int
3617 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3618 {
3619         struct ixgbe_hw *hw;
3620
3621         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3622         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3623 }
3624
3625 static int
3626 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3627 {
3628         struct ixgbe_hw *hw;
3629         uint32_t mflcn_reg;
3630         uint32_t fccfg_reg;
3631         int rx_pause;
3632         int tx_pause;
3633
3634         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635
3636         fc_conf->pause_time = hw->fc.pause_time;
3637         fc_conf->high_water = hw->fc.high_water[0];
3638         fc_conf->low_water = hw->fc.low_water[0];
3639         fc_conf->send_xon = hw->fc.send_xon;
3640         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3641
3642         /*
3643          * Return rx_pause status according to actual setting of
3644          * MFLCN register.
3645          */
3646         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3647         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3648                 rx_pause = 1;
3649         else
3650                 rx_pause = 0;
3651
3652         /*
3653          * Return tx_pause status according to actual setting of
3654          * FCCFG register.
3655          */
3656         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3657         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3658                 tx_pause = 1;
3659         else
3660                 tx_pause = 0;
3661
3662         if (rx_pause && tx_pause)
3663                 fc_conf->mode = RTE_FC_FULL;
3664         else if (rx_pause)
3665                 fc_conf->mode = RTE_FC_RX_PAUSE;
3666         else if (tx_pause)
3667                 fc_conf->mode = RTE_FC_TX_PAUSE;
3668         else
3669                 fc_conf->mode = RTE_FC_NONE;
3670
3671         return 0;
3672 }
3673
3674 static int
3675 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3676 {
3677         struct ixgbe_hw *hw;
3678         int err;
3679         uint32_t rx_buf_size;
3680         uint32_t max_high_water;
3681         uint32_t mflcn;
3682         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3683                 ixgbe_fc_none,
3684                 ixgbe_fc_rx_pause,
3685                 ixgbe_fc_tx_pause,
3686                 ixgbe_fc_full
3687         };
3688
3689         PMD_INIT_FUNC_TRACE();
3690
3691         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3692         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3693         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3694
3695         /*
3696          * At least reserve one Ethernet frame for watermark
3697          * high_water/low_water in kilo bytes for ixgbe
3698          */
3699         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3700         if ((fc_conf->high_water > max_high_water) ||
3701                 (fc_conf->high_water < fc_conf->low_water)) {
3702                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3703                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3704                 return -EINVAL;
3705         }
3706
3707         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3708         hw->fc.pause_time     = fc_conf->pause_time;
3709         hw->fc.high_water[0]  = fc_conf->high_water;
3710         hw->fc.low_water[0]   = fc_conf->low_water;
3711         hw->fc.send_xon       = fc_conf->send_xon;
3712         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3713
3714         err = ixgbe_fc_enable(hw);
3715
3716         /* Not negotiated is not an error case */
3717         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3718
3719                 /* check if we want to forward MAC frames - driver doesn't have native
3720                  * capability to do that, so we'll write the registers ourselves */
3721
3722                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3723
3724                 /* set or clear MFLCN.PMCF bit depending on configuration */
3725                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3726                         mflcn |= IXGBE_MFLCN_PMCF;
3727                 else
3728                         mflcn &= ~IXGBE_MFLCN_PMCF;
3729
3730                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3731                 IXGBE_WRITE_FLUSH(hw);
3732
3733                 return 0;
3734         }
3735
3736         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3737         return -EIO;
3738 }
3739
3740 /**
3741  *  ixgbe_pfc_enable_generic - Enable flow control
3742  *  @hw: pointer to hardware structure
3743  *  @tc_num: traffic class number
3744  *  Enable flow control according to the current settings.
3745  */
3746 static int
3747 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3748 {
3749         int ret_val = 0;
3750         uint32_t mflcn_reg, fccfg_reg;
3751         uint32_t reg;
3752         uint32_t fcrtl, fcrth;
3753         uint8_t i;
3754         uint8_t nb_rx_en;
3755
3756         /* Validate the water mark configuration */
3757         if (!hw->fc.pause_time) {
3758                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3759                 goto out;
3760         }
3761
3762         /* Low water mark of zero causes XOFF floods */
3763         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3764                  /* High/Low water can not be 0 */
3765                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3766                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3767                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3768                         goto out;
3769                 }
3770
3771                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3772                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3773                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3774                         goto out;
3775                 }
3776         }
3777         /* Negotiate the fc mode to use */
3778         ixgbe_fc_autoneg(hw);
3779
3780         /* Disable any previous flow control settings */
3781         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3782         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3783
3784         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3785         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3786
3787         switch (hw->fc.current_mode) {
3788         case ixgbe_fc_none:
3789                 /*
3790                  * If the count of enabled RX Priority Flow control >1,
3791                  * and the TX pause can not be disabled
3792                  */
3793                 nb_rx_en = 0;
3794                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3795                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3796                         if (reg & IXGBE_FCRTH_FCEN)
3797                                 nb_rx_en++;
3798                 }
3799                 if (nb_rx_en > 1)
3800                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3801                 break;
3802         case ixgbe_fc_rx_pause:
3803                 /*
3804                  * Rx Flow control is enabled and Tx Flow control is
3805                  * disabled by software override. Since there really
3806                  * isn't a way to advertise that we are capable of RX
3807                  * Pause ONLY, we will advertise that we support both
3808                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3809                  * disable the adapter's ability to send PAUSE frames.
3810                  */
3811                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3812                 /*
3813                  * If the count of enabled RX Priority Flow control >1,
3814                  * and the TX pause can not be disabled
3815                  */
3816                 nb_rx_en = 0;
3817                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3818                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3819                         if (reg & IXGBE_FCRTH_FCEN)
3820                                 nb_rx_en++;
3821                 }
3822                 if (nb_rx_en > 1)
3823                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3824                 break;
3825         case ixgbe_fc_tx_pause:
3826                 /*
3827                  * Tx Flow control is enabled, and Rx Flow control is
3828                  * disabled by software override.
3829                  */
3830                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3831                 break;
3832         case ixgbe_fc_full:
3833                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3834                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3835                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3836                 break;
3837         default:
3838                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3839                 ret_val = IXGBE_ERR_CONFIG;
3840                 goto out;
3841         }
3842
3843         /* Set 802.3x based flow control settings. */
3844         mflcn_reg |= IXGBE_MFLCN_DPF;
3845         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3846         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3847
3848         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3849         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3850                 hw->fc.high_water[tc_num]) {
3851                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3852                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3853                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3854         } else {
3855                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3856                 /*
3857                  * In order to prevent Tx hangs when the internal Tx
3858                  * switch is enabled we must set the high water mark
3859                  * to the maximum FCRTH value.  This allows the Tx
3860                  * switch to function even under heavy Rx workloads.
3861                  */
3862                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3863         }
3864         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3865
3866         /* Configure pause time (2 TCs per register) */
3867         reg = hw->fc.pause_time * 0x00010001;
3868         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3869                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3870
3871         /* Configure flow control refresh threshold value */
3872         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3873
3874 out:
3875         return ret_val;
3876 }
3877
3878 static int
3879 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3880 {
3881         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3882         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3883
3884         if (hw->mac.type != ixgbe_mac_82598EB) {
3885                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3886         }
3887         return ret_val;
3888 }
3889
3890 static int
3891 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3892 {
3893         int err;
3894         uint32_t rx_buf_size;
3895         uint32_t max_high_water;
3896         uint8_t tc_num;
3897         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3898         struct ixgbe_hw *hw =
3899                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3900         struct ixgbe_dcb_config *dcb_config =
3901                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3902
3903         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3904                 ixgbe_fc_none,
3905                 ixgbe_fc_rx_pause,
3906                 ixgbe_fc_tx_pause,
3907                 ixgbe_fc_full
3908         };
3909
3910         PMD_INIT_FUNC_TRACE();
3911
3912         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3913         tc_num = map[pfc_conf->priority];
3914         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3915         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3916         /*
3917          * At least reserve one Ethernet frame for watermark
3918          * high_water/low_water in kilo bytes for ixgbe
3919          */
3920         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3921         if ((pfc_conf->fc.high_water > max_high_water) ||
3922             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3923                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3924                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3925                 return -EINVAL;
3926         }
3927
3928         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3929         hw->fc.pause_time = pfc_conf->fc.pause_time;
3930         hw->fc.send_xon = pfc_conf->fc.send_xon;
3931         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3932         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3933
3934         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3935
3936         /* Not negotiated is not an error case */
3937         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3938                 return 0;
3939
3940         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3941         return -EIO;
3942 }
3943
3944 static int
3945 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3946                           struct rte_eth_rss_reta_entry64 *reta_conf,
3947                           uint16_t reta_size)
3948 {
3949         uint16_t i, sp_reta_size;
3950         uint8_t j, mask;
3951         uint32_t reta, r;
3952         uint16_t idx, shift;
3953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3954         uint32_t reta_reg;
3955
3956         PMD_INIT_FUNC_TRACE();
3957
3958         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3959                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3960                         "NIC.");
3961                 return -ENOTSUP;
3962         }
3963
3964         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3965         if (reta_size != sp_reta_size) {
3966                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3967                         "(%d) doesn't match the number hardware can supported "
3968                         "(%d)\n", reta_size, sp_reta_size);
3969                 return -EINVAL;
3970         }
3971
3972         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3973                 idx = i / RTE_RETA_GROUP_SIZE;
3974                 shift = i % RTE_RETA_GROUP_SIZE;
3975                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3976                                                 IXGBE_4_BIT_MASK);
3977                 if (!mask)
3978                         continue;
3979                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3980                 if (mask == IXGBE_4_BIT_MASK)
3981                         r = 0;
3982                 else
3983                         r = IXGBE_READ_REG(hw, reta_reg);
3984                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3985                         if (mask & (0x1 << j))
3986                                 reta |= reta_conf[idx].reta[shift + j] <<
3987                                                         (CHAR_BIT * j);
3988                         else
3989                                 reta |= r & (IXGBE_8_BIT_MASK <<
3990                                                 (CHAR_BIT * j));
3991                 }
3992                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3993         }
3994
3995         return 0;
3996 }
3997
3998 static int
3999 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4000                          struct rte_eth_rss_reta_entry64 *reta_conf,
4001                          uint16_t reta_size)
4002 {
4003         uint16_t i, sp_reta_size;
4004         uint8_t j, mask;
4005         uint32_t reta;
4006         uint16_t idx, shift;
4007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4008         uint32_t reta_reg;
4009
4010         PMD_INIT_FUNC_TRACE();
4011         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4012         if (reta_size != sp_reta_size) {
4013                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4014                         "(%d) doesn't match the number hardware can supported "
4015                         "(%d)\n", reta_size, sp_reta_size);
4016                 return -EINVAL;
4017         }
4018
4019         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4020                 idx = i / RTE_RETA_GROUP_SIZE;
4021                 shift = i % RTE_RETA_GROUP_SIZE;
4022                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4023                                                 IXGBE_4_BIT_MASK);
4024                 if (!mask)
4025                         continue;
4026
4027                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4028                 reta = IXGBE_READ_REG(hw, reta_reg);
4029                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4030                         if (mask & (0x1 << j))
4031                                 reta_conf[idx].reta[shift + j] =
4032                                         ((reta >> (CHAR_BIT * j)) &
4033                                                 IXGBE_8_BIT_MASK);
4034                 }
4035         }
4036
4037         return 0;
4038 }
4039
4040 static void
4041 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4042                                 uint32_t index, uint32_t pool)
4043 {
4044         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4045         uint32_t enable_addr = 1;
4046
4047         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4048 }
4049
4050 static void
4051 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4052 {
4053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4054
4055         ixgbe_clear_rar(hw, index);
4056 }
4057
4058 static void
4059 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4060 {
4061         ixgbe_remove_rar(dev, 0);
4062
4063         ixgbe_add_rar(dev, addr, 0, 0);
4064 }
4065
4066 int
4067 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4068                 struct ether_addr *mac_addr)
4069 {
4070         struct ixgbe_hw *hw;
4071         struct ixgbe_vf_info *vfinfo;
4072         int rar_entry;
4073         uint8_t *new_mac = (uint8_t *)(mac_addr);
4074         struct rte_eth_dev *dev;
4075         struct rte_eth_dev_info dev_info;
4076
4077         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4078
4079         dev = &rte_eth_devices[port];
4080         rte_eth_dev_info_get(port, &dev_info);
4081
4082         if (vf >= dev_info.max_vfs)
4083                 return -EINVAL;
4084
4085         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4086         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4087         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4088
4089         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4090                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4091                                 ETHER_ADDR_LEN);
4092                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4093                                 IXGBE_RAH_AV);
4094         }
4095         return -EINVAL;
4096 }
4097
4098 static int
4099 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4100 {
4101         uint32_t hlreg0;
4102         uint32_t maxfrs;
4103         struct ixgbe_hw *hw;
4104         struct rte_eth_dev_info dev_info;
4105         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4106
4107         ixgbe_dev_info_get(dev, &dev_info);
4108
4109         /* check that mtu is within the allowed range */
4110         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4111                 return -EINVAL;
4112
4113         /* refuse mtu that requires the support of scattered packets when this
4114          * feature has not been enabled before.
4115          */
4116         if (!dev->data->scattered_rx &&
4117             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4118              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4119                 return -EINVAL;
4120
4121         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4122         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4123
4124         /* switch to jumbo mode if needed */
4125         if (frame_size > ETHER_MAX_LEN) {
4126                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4127                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4128         } else {
4129                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4130                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4131         }
4132         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4133
4134         /* update max frame size */
4135         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4136
4137         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4138         maxfrs &= 0x0000FFFF;
4139         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4140         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4141
4142         return 0;
4143 }
4144
4145 /*
4146  * Virtual Function operations
4147  */
4148 static void
4149 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4150 {
4151         PMD_INIT_FUNC_TRACE();
4152
4153         /* Clear interrupt mask to stop from interrupts being generated */
4154         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4155
4156         IXGBE_WRITE_FLUSH(hw);
4157 }
4158
4159 static void
4160 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4161 {
4162         PMD_INIT_FUNC_TRACE();
4163
4164         /* VF enable interrupt autoclean */
4165         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4166         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4167         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4168
4169         IXGBE_WRITE_FLUSH(hw);
4170 }
4171
4172 static int
4173 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4174 {
4175         struct rte_eth_conf *conf = &dev->data->dev_conf;
4176         struct ixgbe_adapter *adapter =
4177                         (struct ixgbe_adapter *)dev->data->dev_private;
4178
4179         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4180                      dev->data->port_id);
4181
4182         /*
4183          * VF has no ability to enable/disable HW CRC
4184          * Keep the persistent behavior the same as Host PF
4185          */
4186 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4187         if (!conf->rxmode.hw_strip_crc) {
4188                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4189                 conf->rxmode.hw_strip_crc = 1;
4190         }
4191 #else
4192         if (conf->rxmode.hw_strip_crc) {
4193                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4194                 conf->rxmode.hw_strip_crc = 0;
4195         }
4196 #endif
4197
4198         /*
4199          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4200          * allocation or vector Rx preconditions we will reset it.
4201          */
4202         adapter->rx_bulk_alloc_allowed = true;
4203         adapter->rx_vec_allowed = true;
4204
4205         return 0;
4206 }
4207
4208 static int
4209 ixgbevf_dev_start(struct rte_eth_dev *dev)
4210 {
4211         struct ixgbe_hw *hw =
4212                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4213         uint32_t intr_vector = 0;
4214         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4215         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4216
4217         int err, mask = 0;
4218
4219         PMD_INIT_FUNC_TRACE();
4220
4221         hw->mac.ops.reset_hw(hw);
4222         hw->mac.get_link_status = true;
4223
4224         /* negotiate mailbox API version to use with the PF. */
4225         ixgbevf_negotiate_api(hw);
4226
4227         ixgbevf_dev_tx_init(dev);
4228
4229         /* This can fail when allocating mbufs for descriptor rings */
4230         err = ixgbevf_dev_rx_init(dev);
4231         if (err) {
4232                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4233                 ixgbe_dev_clear_queues(dev);
4234                 return err;
4235         }
4236
4237         /* Set vfta */
4238         ixgbevf_set_vfta_all(dev, 1);
4239
4240         /* Set HW strip */
4241         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4242                 ETH_VLAN_EXTEND_MASK;
4243         ixgbevf_vlan_offload_set(dev, mask);
4244
4245         ixgbevf_dev_rxtx_start(dev);
4246
4247         /* check and configure queue intr-vector mapping */
4248         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4249                 intr_vector = dev->data->nb_rx_queues;
4250                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4251                         return -1;
4252         }
4253
4254         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4255                 intr_handle->intr_vec =
4256                         rte_zmalloc("intr_vec",
4257                                     dev->data->nb_rx_queues * sizeof(int), 0);
4258                 if (intr_handle->intr_vec == NULL) {
4259                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4260                                      " intr_vec\n", dev->data->nb_rx_queues);
4261                         return -ENOMEM;
4262                 }
4263         }
4264         ixgbevf_configure_msix(dev);
4265
4266         rte_intr_enable(intr_handle);
4267
4268         /* Re-enable interrupt for VF */
4269         ixgbevf_intr_enable(hw);
4270
4271         return 0;
4272 }
4273
4274 static void
4275 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4276 {
4277         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4278         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4279         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4280
4281         PMD_INIT_FUNC_TRACE();
4282
4283         ixgbevf_intr_disable(hw);
4284
4285         hw->adapter_stopped = 1;
4286         ixgbe_stop_adapter(hw);
4287
4288         /*
4289           * Clear what we set, but we still keep shadow_vfta to
4290           * restore after device starts
4291           */
4292         ixgbevf_set_vfta_all(dev, 0);
4293
4294         /* Clear stored conf */
4295         dev->data->scattered_rx = 0;
4296
4297         ixgbe_dev_clear_queues(dev);
4298
4299         /* Clean datapath event and queue/vec mapping */
4300         rte_intr_efd_disable(intr_handle);
4301         if (intr_handle->intr_vec != NULL) {
4302                 rte_free(intr_handle->intr_vec);
4303                 intr_handle->intr_vec = NULL;
4304         }
4305 }
4306
4307 static void
4308 ixgbevf_dev_close(struct rte_eth_dev *dev)
4309 {
4310         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4311
4312         PMD_INIT_FUNC_TRACE();
4313
4314         ixgbe_reset_hw(hw);
4315
4316         ixgbevf_dev_stop(dev);
4317
4318         ixgbe_dev_free_queues(dev);
4319
4320         /**
4321          * Remove the VF MAC address ro ensure
4322          * that the VF traffic goes to the PF
4323          * after stop, close and detach of the VF
4324          **/
4325         ixgbevf_remove_mac_addr(dev, 0);
4326 }
4327
4328 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4329 {
4330         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4331         struct ixgbe_vfta *shadow_vfta =
4332                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4333         int i = 0, j = 0, vfta = 0, mask = 1;
4334
4335         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4336                 vfta = shadow_vfta->vfta[i];
4337                 if (vfta) {
4338                         mask = 1;
4339                         for (j = 0; j < 32; j++) {
4340                                 if (vfta & mask)
4341                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4342                                                        on, false);
4343                                 mask <<= 1;
4344                         }
4345                 }
4346         }
4347
4348 }
4349
4350 static int
4351 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4352 {
4353         struct ixgbe_hw *hw =
4354                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4355         struct ixgbe_vfta *shadow_vfta =
4356                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4357         uint32_t vid_idx = 0;
4358         uint32_t vid_bit = 0;
4359         int ret = 0;
4360
4361         PMD_INIT_FUNC_TRACE();
4362
4363         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4364         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4365         if (ret) {
4366                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4367                 return ret;
4368         }
4369         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4370         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4371
4372         /* Save what we set and retore it after device reset */
4373         if (on)
4374                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4375         else
4376                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4377
4378         return 0;
4379 }
4380
4381 static void
4382 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4383 {
4384         struct ixgbe_hw *hw =
4385                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4386         uint32_t ctrl;
4387
4388         PMD_INIT_FUNC_TRACE();
4389
4390         if (queue >= hw->mac.max_rx_queues)
4391                 return;
4392
4393         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4394         if (on)
4395                 ctrl |= IXGBE_RXDCTL_VME;
4396         else
4397                 ctrl &= ~IXGBE_RXDCTL_VME;
4398         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4399
4400         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4401 }
4402
4403 static void
4404 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4405 {
4406         struct ixgbe_hw *hw =
4407                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4408         uint16_t i;
4409         int on = 0;
4410
4411         /* VF function only support hw strip feature, others are not support */
4412         if (mask & ETH_VLAN_STRIP_MASK) {
4413                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4414
4415                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4416                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4417         }
4418 }
4419
4420 static int
4421 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4422 {
4423         uint32_t reg_val;
4424
4425         /* we only need to do this if VMDq is enabled */
4426         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4427         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4428                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4429                 return -1;
4430         }
4431
4432         return 0;
4433 }
4434
4435 static uint32_t
4436 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4437 {
4438         uint32_t vector = 0;
4439
4440         switch (hw->mac.mc_filter_type) {
4441         case 0:   /* use bits [47:36] of the address */
4442                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4443                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4444                 break;
4445         case 1:   /* use bits [46:35] of the address */
4446                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4447                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4448                 break;
4449         case 2:   /* use bits [45:34] of the address */
4450                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4451                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4452                 break;
4453         case 3:   /* use bits [43:32] of the address */
4454                 vector = ((uc_addr->addr_bytes[4]) |
4455                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4456                 break;
4457         default:  /* Invalid mc_filter_type */
4458                 break;
4459         }
4460
4461         /* vector can only be 12-bits or boundary will be exceeded */
4462         vector &= 0xFFF;
4463         return vector;
4464 }
4465
4466 static int
4467 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4468                         uint8_t on)
4469 {
4470         uint32_t vector;
4471         uint32_t uta_idx;
4472         uint32_t reg_val;
4473         uint32_t uta_shift;
4474         uint32_t rc;
4475         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4476         const uint32_t ixgbe_uta_bit_shift = 5;
4477         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4478         const uint32_t bit1 = 0x1;
4479
4480         struct ixgbe_hw *hw =
4481                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4482         struct ixgbe_uta_info *uta_info =
4483                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4484
4485         /* The UTA table only exists on 82599 hardware and newer */
4486         if (hw->mac.type < ixgbe_mac_82599EB)
4487                 return -ENOTSUP;
4488
4489         vector = ixgbe_uta_vector(hw, mac_addr);
4490         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4491         uta_shift = vector & ixgbe_uta_bit_mask;
4492
4493         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4494         if (rc == on)
4495                 return 0;
4496
4497         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4498         if (on) {
4499                 uta_info->uta_in_use++;
4500                 reg_val |= (bit1 << uta_shift);
4501                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4502         } else {
4503                 uta_info->uta_in_use--;
4504                 reg_val &= ~(bit1 << uta_shift);
4505                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4506         }
4507
4508         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4509
4510         if (uta_info->uta_in_use > 0)
4511                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4512                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4513         else
4514                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4515
4516         return 0;
4517 }
4518
4519 static int
4520 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4521 {
4522         int i;
4523         struct ixgbe_hw *hw =
4524                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4525         struct ixgbe_uta_info *uta_info =
4526                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4527
4528         /* The UTA table only exists on 82599 hardware and newer */
4529         if (hw->mac.type < ixgbe_mac_82599EB)
4530                 return -ENOTSUP;
4531
4532         if (on) {
4533                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4534                         uta_info->uta_shadow[i] = ~0;
4535                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4536                 }
4537         } else {
4538                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4539                         uta_info->uta_shadow[i] = 0;
4540                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4541                 }
4542         }
4543         return 0;
4544
4545 }
4546
4547 uint32_t
4548 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4549 {
4550         uint32_t new_val = orig_val;
4551
4552         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4553                 new_val |= IXGBE_VMOLR_AUPE;
4554         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4555                 new_val |= IXGBE_VMOLR_ROMPE;
4556         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4557                 new_val |= IXGBE_VMOLR_ROPE;
4558         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4559                 new_val |= IXGBE_VMOLR_BAM;
4560         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4561                 new_val |= IXGBE_VMOLR_MPE;
4562
4563         return new_val;
4564 }
4565
4566 static int
4567 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4568                                uint16_t rx_mask, uint8_t on)
4569 {
4570         int val = 0;
4571
4572         struct ixgbe_hw *hw =
4573                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4574         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4575
4576         if (hw->mac.type == ixgbe_mac_82598EB) {
4577                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4578                              " on 82599 hardware and newer");
4579                 return -ENOTSUP;
4580         }
4581         if (ixgbe_vmdq_mode_check(hw) < 0)
4582                 return -ENOTSUP;
4583
4584         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4585
4586         if (on)
4587                 vmolr |= val;
4588         else
4589                 vmolr &= ~val;
4590
4591         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4592
4593         return 0;
4594 }
4595
4596 static int
4597 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4598 {
4599         uint32_t reg, addr;
4600         uint32_t val;
4601         const uint8_t bit1 = 0x1;
4602
4603         struct ixgbe_hw *hw =
4604                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4605
4606         if (ixgbe_vmdq_mode_check(hw) < 0)
4607                 return -ENOTSUP;
4608
4609         if (pool >= ETH_64_POOLS)
4610                 return -EINVAL;
4611
4612         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4613         if (pool >= 32) {
4614                 addr = IXGBE_VFRE(1);
4615                 val = bit1 << (pool - 32);
4616         } else {
4617                 addr = IXGBE_VFRE(0);
4618                 val = bit1 << pool;
4619         }
4620
4621         reg = IXGBE_READ_REG(hw, addr);
4622
4623         if (on)
4624                 reg |= val;
4625         else
4626                 reg &= ~val;
4627
4628         IXGBE_WRITE_REG(hw, addr, reg);
4629
4630         return 0;
4631 }
4632
4633 static int
4634 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4635 {
4636         uint32_t reg, addr;
4637         uint32_t val;
4638         const uint8_t bit1 = 0x1;
4639
4640         struct ixgbe_hw *hw =
4641                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4642
4643         if (ixgbe_vmdq_mode_check(hw) < 0)
4644                 return -ENOTSUP;
4645
4646         if (pool >= ETH_64_POOLS)
4647                 return -EINVAL;
4648
4649         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4650         if (pool >= 32) {
4651                 addr = IXGBE_VFTE(1);
4652                 val = bit1 << (pool - 32);
4653         } else {
4654                 addr = IXGBE_VFTE(0);
4655                 val = bit1 << pool;
4656         }
4657
4658         reg = IXGBE_READ_REG(hw, addr);
4659
4660         if (on)
4661                 reg |= val;
4662         else
4663                 reg &= ~val;
4664
4665         IXGBE_WRITE_REG(hw, addr, reg);
4666
4667         return 0;
4668 }
4669
4670 static int
4671 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4672                         uint64_t pool_mask, uint8_t vlan_on)
4673 {
4674         int ret = 0;
4675         uint16_t pool_idx;
4676         struct ixgbe_hw *hw =
4677                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4678
4679         if (ixgbe_vmdq_mode_check(hw) < 0)
4680                 return -ENOTSUP;
4681         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4682                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4683                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4684                                                    vlan_on, false);
4685                         if (ret < 0)
4686                                 return ret;
4687                 }
4688         }
4689
4690         return ret;
4691 }
4692
4693 int
4694 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4695 {
4696         struct ixgbe_hw *hw;
4697         struct ixgbe_mac_info *mac;
4698         struct rte_eth_dev *dev;
4699         struct rte_eth_dev_info dev_info;
4700
4701         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4702
4703         dev = &rte_eth_devices[port];
4704         rte_eth_dev_info_get(port, &dev_info);
4705
4706         if (vf >= dev_info.max_vfs)
4707                 return -EINVAL;
4708
4709         if (on > 1)
4710                 return -EINVAL;
4711
4712         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4713         mac = &hw->mac;
4714
4715         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4716
4717         return 0;
4718 }
4719
4720 int
4721 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4722 {
4723         struct ixgbe_hw *hw;
4724         struct ixgbe_mac_info *mac;
4725         struct rte_eth_dev *dev;
4726         struct rte_eth_dev_info dev_info;
4727
4728         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4729
4730         dev = &rte_eth_devices[port];
4731         rte_eth_dev_info_get(port, &dev_info);
4732
4733         if (vf >= dev_info.max_vfs)
4734                 return -EINVAL;
4735
4736         if (on > 1)
4737                 return -EINVAL;
4738
4739         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4740         mac = &hw->mac;
4741         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4742
4743         return 0;
4744 }
4745
4746 int
4747 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4748 {
4749         struct ixgbe_hw *hw;
4750         uint32_t ctrl;
4751         struct rte_eth_dev *dev;
4752         struct rte_eth_dev_info dev_info;
4753
4754         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4755
4756         dev = &rte_eth_devices[port];
4757         rte_eth_dev_info_get(port, &dev_info);
4758
4759         if (vf >= dev_info.max_vfs)
4760                 return -EINVAL;
4761
4762         if (vlan_id > 4095)
4763                 return -EINVAL;
4764
4765         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4766         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4767         if (vlan_id) {
4768                 ctrl = vlan_id;
4769                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4770         } else {
4771                 ctrl = 0;
4772         }
4773
4774         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4775
4776         return 0;
4777 }
4778
4779 int
4780 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4781 {
4782         struct ixgbe_hw *hw;
4783         uint32_t ctrl;
4784         struct rte_eth_dev *dev;
4785
4786         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4787
4788         dev = &rte_eth_devices[port];
4789
4790         if (on > 1)
4791                 return -EINVAL;
4792
4793         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4794         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4795         /* enable or disable VMDQ loopback */
4796         if (on)
4797                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4798         else
4799                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4800
4801         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4802
4803         return 0;
4804 }
4805
4806 int
4807 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4808 {
4809         struct ixgbe_hw *hw;
4810         uint32_t reg_value;
4811         int i;
4812         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4813         struct rte_eth_dev *dev;
4814
4815         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4816
4817         dev = &rte_eth_devices[port];
4818
4819         if (on > 1)
4820                 return -EINVAL;
4821
4822         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4823         for (i = 0; i <= num_queues; i++) {
4824                 reg_value = IXGBE_QDE_WRITE |
4825                                 (i << IXGBE_QDE_IDX_SHIFT) |
4826                                 (on & IXGBE_QDE_ENABLE);
4827                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4828         }
4829
4830         return 0;
4831 }
4832
4833 int
4834 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4835 {
4836         struct ixgbe_hw *hw;
4837         uint32_t reg_value;
4838         struct rte_eth_dev *dev;
4839         struct rte_eth_dev_info dev_info;
4840
4841         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4842
4843         dev = &rte_eth_devices[port];
4844         rte_eth_dev_info_get(port, &dev_info);
4845
4846         /* only support VF's 0 to 63 */
4847         if ((vf >= dev_info.max_vfs) || (vf > 63))
4848                 return -EINVAL;
4849
4850         if (on > 1)
4851                 return -EINVAL;
4852
4853         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4854         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4855         if (on)
4856                 reg_value |= IXGBE_SRRCTL_DROP_EN;
4857         else
4858                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4859
4860         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4861
4862         return 0;
4863 }
4864
4865 int
4866 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4867 {
4868         struct rte_eth_dev *dev;
4869         struct rte_eth_dev_info dev_info;
4870         uint16_t queues_per_pool;
4871         uint32_t q;
4872
4873         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4874
4875         dev = &rte_eth_devices[port];
4876         rte_eth_dev_info_get(port, &dev_info);
4877
4878         if (vf >= dev_info.max_vfs)
4879                 return -EINVAL;
4880
4881         if (on > 1)
4882                 return -EINVAL;
4883
4884         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
4885
4886         /* The PF has 128 queue pairs and in SRIOV configuration
4887          * those queues will be assigned to VF's, so RXDCTL
4888          * registers will be dealing with queues which will be
4889          * assigned to VF's.
4890          * Let's say we have SRIOV configured with 31 VF's then the
4891          * first 124 queues 0-123 will be allocated to VF's and only
4892          * the last 4 queues 123-127 will be assigned to the PF.
4893          */
4894
4895         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
4896
4897         for (q = 0; q < queues_per_pool; q++)
4898                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
4899                                 q + vf * queues_per_pool, on);
4900         return 0;
4901 }
4902
4903 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4904 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4905 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4906 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4907 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4908         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4909         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4910
4911 static int
4912 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4913                         struct rte_eth_mirror_conf *mirror_conf,
4914                         uint8_t rule_id, uint8_t on)
4915 {
4916         uint32_t mr_ctl, vlvf;
4917         uint32_t mp_lsb = 0;
4918         uint32_t mv_msb = 0;
4919         uint32_t mv_lsb = 0;
4920         uint32_t mp_msb = 0;
4921         uint8_t i = 0;
4922         int reg_index = 0;
4923         uint64_t vlan_mask = 0;
4924
4925         const uint8_t pool_mask_offset = 32;
4926         const uint8_t vlan_mask_offset = 32;
4927         const uint8_t dst_pool_offset = 8;
4928         const uint8_t rule_mr_offset  = 4;
4929         const uint8_t mirror_rule_mask = 0x0F;
4930
4931         struct ixgbe_mirror_info *mr_info =
4932                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4933         struct ixgbe_hw *hw =
4934                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4935         uint8_t mirror_type = 0;
4936
4937         if (ixgbe_vmdq_mode_check(hw) < 0)
4938                 return -ENOTSUP;
4939
4940         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4941                 return -EINVAL;
4942
4943         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4944                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4945                         mirror_conf->rule_type);
4946                 return -EINVAL;
4947         }
4948
4949         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4950                 mirror_type |= IXGBE_MRCTL_VLME;
4951                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4952                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4953                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4954                                 /* search vlan id related pool vlan filter index */
4955                                 reg_index = ixgbe_find_vlvf_slot(hw,
4956                                                  mirror_conf->vlan.vlan_id[i],
4957                                                  false);
4958                                 if (reg_index < 0)
4959                                         return -EINVAL;
4960                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4961                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4962                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4963                                       mirror_conf->vlan.vlan_id[i]))
4964                                         vlan_mask |= (1ULL << reg_index);
4965                                 else
4966                                         return -EINVAL;
4967                         }
4968                 }
4969
4970                 if (on) {
4971                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4972                         mv_msb = vlan_mask >> vlan_mask_offset;
4973
4974                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4975                                                 mirror_conf->vlan.vlan_mask;
4976                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4977                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4978                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4979                                                 mirror_conf->vlan.vlan_id[i];
4980                         }
4981                 } else {
4982                         mv_lsb = 0;
4983                         mv_msb = 0;
4984                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4985                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4986                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4987                 }
4988         }
4989
4990         /*
4991          * if enable pool mirror, write related pool mask register,if disable
4992          * pool mirror, clear PFMRVM register
4993          */
4994         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4995                 mirror_type |= IXGBE_MRCTL_VPME;
4996                 if (on) {
4997                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4998                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4999                         mr_info->mr_conf[rule_id].pool_mask =
5000                                         mirror_conf->pool_mask;
5001
5002                 } else {
5003                         mp_lsb = 0;
5004                         mp_msb = 0;
5005                         mr_info->mr_conf[rule_id].pool_mask = 0;
5006                 }
5007         }
5008         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5009                 mirror_type |= IXGBE_MRCTL_UPME;
5010         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5011                 mirror_type |= IXGBE_MRCTL_DPME;
5012
5013         /* read  mirror control register and recalculate it */
5014         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5015
5016         if (on) {
5017                 mr_ctl |= mirror_type;
5018                 mr_ctl &= mirror_rule_mask;
5019                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5020         } else
5021                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5022
5023         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5024         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5025
5026         /* write mirrror control  register */
5027         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5028
5029         /* write pool mirrror control  register */
5030         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5031                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5032                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5033                                 mp_msb);
5034         }
5035         /* write VLAN mirrror control  register */
5036         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5037                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5038                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5039                                 mv_msb);
5040         }
5041
5042         return 0;
5043 }
5044
5045 static int
5046 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5047 {
5048         int mr_ctl = 0;
5049         uint32_t lsb_val = 0;
5050         uint32_t msb_val = 0;
5051         const uint8_t rule_mr_offset = 4;
5052
5053         struct ixgbe_hw *hw =
5054                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5055         struct ixgbe_mirror_info *mr_info =
5056                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5057
5058         if (ixgbe_vmdq_mode_check(hw) < 0)
5059                 return -ENOTSUP;
5060
5061         memset(&mr_info->mr_conf[rule_id], 0,
5062                 sizeof(struct rte_eth_mirror_conf));
5063
5064         /* clear PFVMCTL register */
5065         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5066
5067         /* clear pool mask register */
5068         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5069         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5070
5071         /* clear vlan mask register */
5072         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5073         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5074
5075         return 0;
5076 }
5077
5078 static int
5079 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5080 {
5081         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5082         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5083         uint32_t mask;
5084         struct ixgbe_hw *hw =
5085                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5086
5087         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5088         mask |= (1 << IXGBE_MISC_VEC_ID);
5089         RTE_SET_USED(queue_id);
5090         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5091
5092         rte_intr_enable(intr_handle);
5093
5094         return 0;
5095 }
5096
5097 static int
5098 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5099 {
5100         uint32_t mask;
5101         struct ixgbe_hw *hw =
5102                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5103
5104         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5105         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5106         RTE_SET_USED(queue_id);
5107         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5108
5109         return 0;
5110 }
5111
5112 static int
5113 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5114 {
5115         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5116         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5117         uint32_t mask;
5118         struct ixgbe_hw *hw =
5119                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5120         struct ixgbe_interrupt *intr =
5121                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5122
5123         if (queue_id < 16) {
5124                 ixgbe_disable_intr(hw);
5125                 intr->mask |= (1 << queue_id);
5126                 ixgbe_enable_intr(dev);
5127         } else if (queue_id < 32) {
5128                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5129                 mask &= (1 << queue_id);
5130                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5131         } else if (queue_id < 64) {
5132                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5133                 mask &= (1 << (queue_id - 32));
5134                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5135         }
5136         rte_intr_enable(intr_handle);
5137
5138         return 0;
5139 }
5140
5141 static int
5142 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5143 {
5144         uint32_t mask;
5145         struct ixgbe_hw *hw =
5146                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5147         struct ixgbe_interrupt *intr =
5148                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5149
5150         if (queue_id < 16) {
5151                 ixgbe_disable_intr(hw);
5152                 intr->mask &= ~(1 << queue_id);
5153                 ixgbe_enable_intr(dev);
5154         } else if (queue_id < 32) {
5155                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5156                 mask &= ~(1 << queue_id);
5157                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5158         } else if (queue_id < 64) {
5159                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5160                 mask &= ~(1 << (queue_id - 32));
5161                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5162         }
5163
5164         return 0;
5165 }
5166
5167 static void
5168 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5169                      uint8_t queue, uint8_t msix_vector)
5170 {
5171         uint32_t tmp, idx;
5172
5173         if (direction == -1) {
5174                 /* other causes */
5175                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5176                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5177                 tmp &= ~0xFF;
5178                 tmp |= msix_vector;
5179                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5180         } else {
5181                 /* rx or tx cause */
5182                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5183                 idx = ((16 * (queue & 1)) + (8 * direction));
5184                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5185                 tmp &= ~(0xFF << idx);
5186                 tmp |= (msix_vector << idx);
5187                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5188         }
5189 }
5190
5191 /**
5192  * set the IVAR registers, mapping interrupt causes to vectors
5193  * @param hw
5194  *  pointer to ixgbe_hw struct
5195  * @direction
5196  *  0 for Rx, 1 for Tx, -1 for other causes
5197  * @queue
5198  *  queue to map the corresponding interrupt to
5199  * @msix_vector
5200  *  the vector to map to the corresponding queue
5201  */
5202 static void
5203 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5204                    uint8_t queue, uint8_t msix_vector)
5205 {
5206         uint32_t tmp, idx;
5207
5208         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5209         if (hw->mac.type == ixgbe_mac_82598EB) {
5210                 if (direction == -1)
5211                         direction = 0;
5212                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5213                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5214                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5215                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5216                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5217         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5218                         (hw->mac.type == ixgbe_mac_X540)) {
5219                 if (direction == -1) {
5220                         /* other causes */
5221                         idx = ((queue & 1) * 8);
5222                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5223                         tmp &= ~(0xFF << idx);
5224                         tmp |= (msix_vector << idx);
5225                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5226                 } else {
5227                         /* rx or tx causes */
5228                         idx = ((16 * (queue & 1)) + (8 * direction));
5229                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5230                         tmp &= ~(0xFF << idx);
5231                         tmp |= (msix_vector << idx);
5232                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5233                 }
5234         }
5235 }
5236
5237 static void
5238 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5239 {
5240         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5241         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5242         struct ixgbe_hw *hw =
5243                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5244         uint32_t q_idx;
5245         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5246
5247         /* Configure VF other cause ivar */
5248         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5249
5250         /* won't configure msix register if no mapping is done
5251          * between intr vector and event fd.
5252          */
5253         if (!rte_intr_dp_is_en(intr_handle))
5254                 return;
5255
5256         /* Configure all RX queues of VF */
5257         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5258                 /* Force all queue use vector 0,
5259                  * as IXGBE_VF_MAXMSIVECOTR = 1
5260                  */
5261                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5262                 intr_handle->intr_vec[q_idx] = vector_idx;
5263         }
5264 }
5265
5266 /**
5267  * Sets up the hardware to properly generate MSI-X interrupts
5268  * @hw
5269  *  board private structure
5270  */
5271 static void
5272 ixgbe_configure_msix(struct rte_eth_dev *dev)
5273 {
5274         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5275         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5276         struct ixgbe_hw *hw =
5277                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5278         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5279         uint32_t vec = IXGBE_MISC_VEC_ID;
5280         uint32_t mask;
5281         uint32_t gpie;
5282
5283         /* won't configure msix register if no mapping is done
5284          * between intr vector and event fd
5285          */
5286         if (!rte_intr_dp_is_en(intr_handle))
5287                 return;
5288
5289         if (rte_intr_allow_others(intr_handle))
5290                 vec = base = IXGBE_RX_VEC_START;
5291
5292         /* setup GPIE for MSI-x mode */
5293         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5294         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5295                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5296         /* auto clearing and auto setting corresponding bits in EIMS
5297          * when MSI-X interrupt is triggered
5298          */
5299         if (hw->mac.type == ixgbe_mac_82598EB) {
5300                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5301         } else {
5302                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5303                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5304         }
5305         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5306
5307         /* Populate the IVAR table and set the ITR values to the
5308          * corresponding register.
5309          */
5310         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5311              queue_id++) {
5312                 /* by default, 1:1 mapping */
5313                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5314                 intr_handle->intr_vec[queue_id] = vec;
5315                 if (vec < base + intr_handle->nb_efd - 1)
5316                         vec++;
5317         }
5318
5319         switch (hw->mac.type) {
5320         case ixgbe_mac_82598EB:
5321                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5322                                    IXGBE_MISC_VEC_ID);
5323                 break;
5324         case ixgbe_mac_82599EB:
5325         case ixgbe_mac_X540:
5326                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5327                 break;
5328         default:
5329                 break;
5330         }
5331         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5332                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5333
5334         /* set up to autoclear timer, and the vectors */
5335         mask = IXGBE_EIMS_ENABLE_MASK;
5336         mask &= ~(IXGBE_EIMS_OTHER |
5337                   IXGBE_EIMS_MAILBOX |
5338                   IXGBE_EIMS_LSC);
5339
5340         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5341 }
5342
5343 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5344         uint16_t queue_idx, uint16_t tx_rate)
5345 {
5346         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5347         uint32_t rf_dec, rf_int;
5348         uint32_t bcnrc_val;
5349         uint16_t link_speed = dev->data->dev_link.link_speed;
5350
5351         if (queue_idx >= hw->mac.max_tx_queues)
5352                 return -EINVAL;
5353
5354         if (tx_rate != 0) {
5355                 /* Calculate the rate factor values to set */
5356                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5357                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5358                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5359
5360                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5361                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5362                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5363                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5364         } else {
5365                 bcnrc_val = 0;
5366         }
5367
5368         /*
5369          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5370          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5371          * set as 0x4.
5372          */
5373         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5374                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5375                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5376                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5377                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5378         else
5379                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5380                         IXGBE_MMW_SIZE_DEFAULT);
5381
5382         /* Set RTTBCNRC of queue X */
5383         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5384         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5385         IXGBE_WRITE_FLUSH(hw);
5386
5387         return 0;
5388 }
5389
5390 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5391         uint16_t tx_rate, uint64_t q_msk)
5392 {
5393         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5394         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5395         struct ixgbe_vf_info *vfinfo =
5396                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5397         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5398         uint32_t queue_stride =
5399                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5400         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5401         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5402         uint16_t total_rate = 0;
5403
5404         if (queue_end >= hw->mac.max_tx_queues)
5405                 return -EINVAL;
5406
5407         if (vfinfo != NULL) {
5408                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5409                         if (vf_idx == vf)
5410                                 continue;
5411                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5412                                 idx++)
5413                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5414                 }
5415         } else
5416                 return -EINVAL;
5417
5418         /* Store tx_rate for this vf. */
5419         for (idx = 0; idx < nb_q_per_pool; idx++) {
5420                 if (((uint64_t)0x1 << idx) & q_msk) {
5421                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5422                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5423                         total_rate += tx_rate;
5424                 }
5425         }
5426
5427         if (total_rate > dev->data->dev_link.link_speed) {
5428                 /*
5429                  * Reset stored TX rate of the VF if it causes exceed
5430                  * link speed.
5431                  */
5432                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5433                 return -EINVAL;
5434         }
5435
5436         /* Set RTTBCNRC of each queue/pool for vf X  */
5437         for (; queue_idx <= queue_end; queue_idx++) {
5438                 if (0x1 & q_msk)
5439                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5440                 q_msk = q_msk >> 1;
5441         }
5442
5443         return 0;
5444 }
5445
5446 static void
5447 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5448                      __attribute__((unused)) uint32_t index,
5449                      __attribute__((unused)) uint32_t pool)
5450 {
5451         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5452         int diag;
5453
5454         /*
5455          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5456          * operation. Trap this case to avoid exhausting the [very limited]
5457          * set of PF resources used to store VF MAC addresses.
5458          */
5459         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5460                 return;
5461         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5462         if (diag == 0)
5463                 return;
5464         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5465 }
5466
5467 static void
5468 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5469 {
5470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5471         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5472         struct ether_addr *mac_addr;
5473         uint32_t i;
5474         int diag;
5475
5476         /*
5477          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5478          * not support the deletion of a given MAC address.
5479          * Instead, it imposes to delete all MAC addresses, then to add again
5480          * all MAC addresses with the exception of the one to be deleted.
5481          */
5482         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5483
5484         /*
5485          * Add again all MAC addresses, with the exception of the deleted one
5486          * and of the permanent MAC address.
5487          */
5488         for (i = 0, mac_addr = dev->data->mac_addrs;
5489              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5490                 /* Skip the deleted MAC address */
5491                 if (i == index)
5492                         continue;
5493                 /* Skip NULL MAC addresses */
5494                 if (is_zero_ether_addr(mac_addr))
5495                         continue;
5496                 /* Skip the permanent MAC address */
5497                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5498                         continue;
5499                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5500                 if (diag != 0)
5501                         PMD_DRV_LOG(ERR,
5502                                     "Adding again MAC address "
5503                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5504                                     "diag=%d",
5505                                     mac_addr->addr_bytes[0],
5506                                     mac_addr->addr_bytes[1],
5507                                     mac_addr->addr_bytes[2],
5508                                     mac_addr->addr_bytes[3],
5509                                     mac_addr->addr_bytes[4],
5510                                     mac_addr->addr_bytes[5],
5511                                     diag);
5512         }
5513 }
5514
5515 static void
5516 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5517 {
5518         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5519
5520         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5521 }
5522
5523 #define MAC_TYPE_FILTER_SUP(type)    do {\
5524         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5525                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5526                 (type) != ixgbe_mac_X550EM_a)\
5527                 return -ENOTSUP;\
5528 } while (0)
5529
5530 static int
5531 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5532                         struct rte_eth_syn_filter *filter,
5533                         bool add)
5534 {
5535         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5536         uint32_t synqf;
5537
5538         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5539                 return -EINVAL;
5540
5541         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5542
5543         if (add) {
5544                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5545                         return -EINVAL;
5546                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5547                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5548
5549                 if (filter->hig_pri)
5550                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5551                 else
5552                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5553         } else {
5554                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5555                         return -ENOENT;
5556                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5557         }
5558         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5559         IXGBE_WRITE_FLUSH(hw);
5560         return 0;
5561 }
5562
5563 static int
5564 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5565                         struct rte_eth_syn_filter *filter)
5566 {
5567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5568         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5569
5570         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5571                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5572                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5573                 return 0;
5574         }
5575         return -ENOENT;
5576 }
5577
5578 static int
5579 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5580                         enum rte_filter_op filter_op,
5581                         void *arg)
5582 {
5583         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5584         int ret;
5585
5586         MAC_TYPE_FILTER_SUP(hw->mac.type);
5587
5588         if (filter_op == RTE_ETH_FILTER_NOP)
5589                 return 0;
5590
5591         if (arg == NULL) {
5592                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5593                             filter_op);
5594                 return -EINVAL;
5595         }
5596
5597         switch (filter_op) {
5598         case RTE_ETH_FILTER_ADD:
5599                 ret = ixgbe_syn_filter_set(dev,
5600                                 (struct rte_eth_syn_filter *)arg,
5601                                 TRUE);
5602                 break;
5603         case RTE_ETH_FILTER_DELETE:
5604                 ret = ixgbe_syn_filter_set(dev,
5605                                 (struct rte_eth_syn_filter *)arg,
5606                                 FALSE);
5607                 break;
5608         case RTE_ETH_FILTER_GET:
5609                 ret = ixgbe_syn_filter_get(dev,
5610                                 (struct rte_eth_syn_filter *)arg);
5611                 break;
5612         default:
5613                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5614                 ret = -EINVAL;
5615                 break;
5616         }
5617
5618         return ret;
5619 }
5620
5621
5622 static inline enum ixgbe_5tuple_protocol
5623 convert_protocol_type(uint8_t protocol_value)
5624 {
5625         if (protocol_value == IPPROTO_TCP)
5626                 return IXGBE_FILTER_PROTOCOL_TCP;
5627         else if (protocol_value == IPPROTO_UDP)
5628                 return IXGBE_FILTER_PROTOCOL_UDP;
5629         else if (protocol_value == IPPROTO_SCTP)
5630                 return IXGBE_FILTER_PROTOCOL_SCTP;
5631         else
5632                 return IXGBE_FILTER_PROTOCOL_NONE;
5633 }
5634
5635 /*
5636  * add a 5tuple filter
5637  *
5638  * @param
5639  * dev: Pointer to struct rte_eth_dev.
5640  * index: the index the filter allocates.
5641  * filter: ponter to the filter that will be added.
5642  * rx_queue: the queue id the filter assigned to.
5643  *
5644  * @return
5645  *    - On success, zero.
5646  *    - On failure, a negative value.
5647  */
5648 static int
5649 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5650                         struct ixgbe_5tuple_filter *filter)
5651 {
5652         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5653         struct ixgbe_filter_info *filter_info =
5654                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5655         int i, idx, shift;
5656         uint32_t ftqf, sdpqf;
5657         uint32_t l34timir = 0;
5658         uint8_t mask = 0xff;
5659
5660         /*
5661          * look for an unused 5tuple filter index,
5662          * and insert the filter to list.
5663          */
5664         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5665                 idx = i / (sizeof(uint32_t) * NBBY);
5666                 shift = i % (sizeof(uint32_t) * NBBY);
5667                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5668                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5669                         filter->index = i;
5670                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5671                                           filter,
5672                                           entries);
5673                         break;
5674                 }
5675         }
5676         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5677                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5678                 return -ENOSYS;
5679         }
5680
5681         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5682                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5683         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5684
5685         ftqf = (uint32_t)(filter->filter_info.proto &
5686                 IXGBE_FTQF_PROTOCOL_MASK);
5687         ftqf |= (uint32_t)((filter->filter_info.priority &
5688                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5689         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5690                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5691         if (filter->filter_info.dst_ip_mask == 0)
5692                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5693         if (filter->filter_info.src_port_mask == 0)
5694                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5695         if (filter->filter_info.dst_port_mask == 0)
5696                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5697         if (filter->filter_info.proto_mask == 0)
5698                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5699         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5700         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5701         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5702
5703         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5704         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5705         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5706         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5707
5708         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5709         l34timir |= (uint32_t)(filter->queue <<
5710                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5711         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5712         return 0;
5713 }
5714
5715 /*
5716  * remove a 5tuple filter
5717  *
5718  * @param
5719  * dev: Pointer to struct rte_eth_dev.
5720  * filter: the pointer of the filter will be removed.
5721  */
5722 static void
5723 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5724                         struct ixgbe_5tuple_filter *filter)
5725 {
5726         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5727         struct ixgbe_filter_info *filter_info =
5728                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5729         uint16_t index = filter->index;
5730
5731         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5732                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5733         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5734         rte_free(filter);
5735
5736         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5737         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5738         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5739         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5740         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5741 }
5742
5743 static int
5744 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5745 {
5746         struct ixgbe_hw *hw;
5747         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5748
5749         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5750
5751         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5752                 return -EINVAL;
5753
5754         /* refuse mtu that requires the support of scattered packets when this
5755          * feature has not been enabled before.
5756          */
5757         if (!dev->data->scattered_rx &&
5758             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5759              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5760                 return -EINVAL;
5761
5762         /*
5763          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5764          * request of the version 2.0 of the mailbox API.
5765          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5766          * of the mailbox API.
5767          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5768          * prior to 3.11.33 which contains the following change:
5769          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5770          */
5771         ixgbevf_rlpml_set_vf(hw, max_frame);
5772
5773         /* update max frame size */
5774         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5775         return 0;
5776 }
5777
5778 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5779         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5780                 return -ENOTSUP;\
5781 } while (0)
5782
5783 static inline struct ixgbe_5tuple_filter *
5784 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5785                         struct ixgbe_5tuple_filter_info *key)
5786 {
5787         struct ixgbe_5tuple_filter *it;
5788
5789         TAILQ_FOREACH(it, filter_list, entries) {
5790                 if (memcmp(key, &it->filter_info,
5791                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5792                         return it;
5793                 }
5794         }
5795         return NULL;
5796 }
5797
5798 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5799 static inline int
5800 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5801                         struct ixgbe_5tuple_filter_info *filter_info)
5802 {
5803         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5804                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5805                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5806                 return -EINVAL;
5807
5808         switch (filter->dst_ip_mask) {
5809         case UINT32_MAX:
5810                 filter_info->dst_ip_mask = 0;
5811                 filter_info->dst_ip = filter->dst_ip;
5812                 break;
5813         case 0:
5814                 filter_info->dst_ip_mask = 1;
5815                 break;
5816         default:
5817                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5818                 return -EINVAL;
5819         }
5820
5821         switch (filter->src_ip_mask) {
5822         case UINT32_MAX:
5823                 filter_info->src_ip_mask = 0;
5824                 filter_info->src_ip = filter->src_ip;
5825                 break;
5826         case 0:
5827                 filter_info->src_ip_mask = 1;
5828                 break;
5829         default:
5830                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5831                 return -EINVAL;
5832         }
5833
5834         switch (filter->dst_port_mask) {
5835         case UINT16_MAX:
5836                 filter_info->dst_port_mask = 0;
5837                 filter_info->dst_port = filter->dst_port;
5838                 break;
5839         case 0:
5840                 filter_info->dst_port_mask = 1;
5841                 break;
5842         default:
5843                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5844                 return -EINVAL;
5845         }
5846
5847         switch (filter->src_port_mask) {
5848         case UINT16_MAX:
5849                 filter_info->src_port_mask = 0;
5850                 filter_info->src_port = filter->src_port;
5851                 break;
5852         case 0:
5853                 filter_info->src_port_mask = 1;
5854                 break;
5855         default:
5856                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5857                 return -EINVAL;
5858         }
5859
5860         switch (filter->proto_mask) {
5861         case UINT8_MAX:
5862                 filter_info->proto_mask = 0;
5863                 filter_info->proto =
5864                         convert_protocol_type(filter->proto);
5865                 break;
5866         case 0:
5867                 filter_info->proto_mask = 1;
5868                 break;
5869         default:
5870                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5871                 return -EINVAL;
5872         }
5873
5874         filter_info->priority = (uint8_t)filter->priority;
5875         return 0;
5876 }
5877
5878 /*
5879  * add or delete a ntuple filter
5880  *
5881  * @param
5882  * dev: Pointer to struct rte_eth_dev.
5883  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5884  * add: if true, add filter, if false, remove filter
5885  *
5886  * @return
5887  *    - On success, zero.
5888  *    - On failure, a negative value.
5889  */
5890 static int
5891 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5892                         struct rte_eth_ntuple_filter *ntuple_filter,
5893                         bool add)
5894 {
5895         struct ixgbe_filter_info *filter_info =
5896                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5897         struct ixgbe_5tuple_filter_info filter_5tuple;
5898         struct ixgbe_5tuple_filter *filter;
5899         int ret;
5900
5901         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5902                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5903                 return -EINVAL;
5904         }
5905
5906         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5907         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5908         if (ret < 0)
5909                 return ret;
5910
5911         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5912                                          &filter_5tuple);
5913         if (filter != NULL && add) {
5914                 PMD_DRV_LOG(ERR, "filter exists.");
5915                 return -EEXIST;
5916         }
5917         if (filter == NULL && !add) {
5918                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5919                 return -ENOENT;
5920         }
5921
5922         if (add) {
5923                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5924                                 sizeof(struct ixgbe_5tuple_filter), 0);
5925                 if (filter == NULL)
5926                         return -ENOMEM;
5927                 (void)rte_memcpy(&filter->filter_info,
5928                                  &filter_5tuple,
5929                                  sizeof(struct ixgbe_5tuple_filter_info));
5930                 filter->queue = ntuple_filter->queue;
5931                 ret = ixgbe_add_5tuple_filter(dev, filter);
5932                 if (ret < 0) {
5933                         rte_free(filter);
5934                         return ret;
5935                 }
5936         } else
5937                 ixgbe_remove_5tuple_filter(dev, filter);
5938
5939         return 0;
5940 }
5941
5942 /*
5943  * get a ntuple filter
5944  *
5945  * @param
5946  * dev: Pointer to struct rte_eth_dev.
5947  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5948  *
5949  * @return
5950  *    - On success, zero.
5951  *    - On failure, a negative value.
5952  */
5953 static int
5954 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5955                         struct rte_eth_ntuple_filter *ntuple_filter)
5956 {
5957         struct ixgbe_filter_info *filter_info =
5958                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5959         struct ixgbe_5tuple_filter_info filter_5tuple;
5960         struct ixgbe_5tuple_filter *filter;
5961         int ret;
5962
5963         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5964                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5965                 return -EINVAL;
5966         }
5967
5968         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5969         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5970         if (ret < 0)
5971                 return ret;
5972
5973         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5974                                          &filter_5tuple);
5975         if (filter == NULL) {
5976                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5977                 return -ENOENT;
5978         }
5979         ntuple_filter->queue = filter->queue;
5980         return 0;
5981 }
5982
5983 /*
5984  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5985  * @dev: pointer to rte_eth_dev structure
5986  * @filter_op:operation will be taken.
5987  * @arg: a pointer to specific structure corresponding to the filter_op
5988  *
5989  * @return
5990  *    - On success, zero.
5991  *    - On failure, a negative value.
5992  */
5993 static int
5994 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5995                                 enum rte_filter_op filter_op,
5996                                 void *arg)
5997 {
5998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5999         int ret;
6000
6001         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6002
6003         if (filter_op == RTE_ETH_FILTER_NOP)
6004                 return 0;
6005
6006         if (arg == NULL) {
6007                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6008                             filter_op);
6009                 return -EINVAL;
6010         }
6011
6012         switch (filter_op) {
6013         case RTE_ETH_FILTER_ADD:
6014                 ret = ixgbe_add_del_ntuple_filter(dev,
6015                         (struct rte_eth_ntuple_filter *)arg,
6016                         TRUE);
6017                 break;
6018         case RTE_ETH_FILTER_DELETE:
6019                 ret = ixgbe_add_del_ntuple_filter(dev,
6020                         (struct rte_eth_ntuple_filter *)arg,
6021                         FALSE);
6022                 break;
6023         case RTE_ETH_FILTER_GET:
6024                 ret = ixgbe_get_ntuple_filter(dev,
6025                         (struct rte_eth_ntuple_filter *)arg);
6026                 break;
6027         default:
6028                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6029                 ret = -EINVAL;
6030                 break;
6031         }
6032         return ret;
6033 }
6034
6035 static inline int
6036 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6037                         uint16_t ethertype)
6038 {
6039         int i;
6040
6041         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6042                 if (filter_info->ethertype_filters[i] == ethertype &&
6043                     (filter_info->ethertype_mask & (1 << i)))
6044                         return i;
6045         }
6046         return -1;
6047 }
6048
6049 static inline int
6050 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6051                         uint16_t ethertype)
6052 {
6053         int i;
6054
6055         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6056                 if (!(filter_info->ethertype_mask & (1 << i))) {
6057                         filter_info->ethertype_mask |= 1 << i;
6058                         filter_info->ethertype_filters[i] = ethertype;
6059                         return i;
6060                 }
6061         }
6062         return -1;
6063 }
6064
6065 static inline int
6066 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6067                         uint8_t idx)
6068 {
6069         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6070                 return -1;
6071         filter_info->ethertype_mask &= ~(1 << idx);
6072         filter_info->ethertype_filters[idx] = 0;
6073         return idx;
6074 }
6075
6076 static int
6077 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6078                         struct rte_eth_ethertype_filter *filter,
6079                         bool add)
6080 {
6081         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6082         struct ixgbe_filter_info *filter_info =
6083                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6084         uint32_t etqf = 0;
6085         uint32_t etqs = 0;
6086         int ret;
6087
6088         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6089                 return -EINVAL;
6090
6091         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6092                 filter->ether_type == ETHER_TYPE_IPv6) {
6093                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6094                         " ethertype filter.", filter->ether_type);
6095                 return -EINVAL;
6096         }
6097
6098         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6099                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6100                 return -EINVAL;
6101         }
6102         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6103                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6104                 return -EINVAL;
6105         }
6106
6107         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6108         if (ret >= 0 && add) {
6109                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6110                             filter->ether_type);
6111                 return -EEXIST;
6112         }
6113         if (ret < 0 && !add) {
6114                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6115                             filter->ether_type);
6116                 return -ENOENT;
6117         }
6118
6119         if (add) {
6120                 ret = ixgbe_ethertype_filter_insert(filter_info,
6121                         filter->ether_type);
6122                 if (ret < 0) {
6123                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6124                         return -ENOSYS;
6125                 }
6126                 etqf = IXGBE_ETQF_FILTER_EN;
6127                 etqf |= (uint32_t)filter->ether_type;
6128                 etqs |= (uint32_t)((filter->queue <<
6129                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6130                                     IXGBE_ETQS_RX_QUEUE);
6131                 etqs |= IXGBE_ETQS_QUEUE_EN;
6132         } else {
6133                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6134                 if (ret < 0)
6135                         return -ENOSYS;
6136         }
6137         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6138         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6139         IXGBE_WRITE_FLUSH(hw);
6140
6141         return 0;
6142 }
6143
6144 static int
6145 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6146                         struct rte_eth_ethertype_filter *filter)
6147 {
6148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6149         struct ixgbe_filter_info *filter_info =
6150                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6151         uint32_t etqf, etqs;
6152         int ret;
6153
6154         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6155         if (ret < 0) {
6156                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6157                             filter->ether_type);
6158                 return -ENOENT;
6159         }
6160
6161         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6162         if (etqf & IXGBE_ETQF_FILTER_EN) {
6163                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6164                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6165                 filter->flags = 0;
6166                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6167                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6168                 return 0;
6169         }
6170         return -ENOENT;
6171 }
6172
6173 /*
6174  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6175  * @dev: pointer to rte_eth_dev structure
6176  * @filter_op:operation will be taken.
6177  * @arg: a pointer to specific structure corresponding to the filter_op
6178  */
6179 static int
6180 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6181                                 enum rte_filter_op filter_op,
6182                                 void *arg)
6183 {
6184         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6185         int ret;
6186
6187         MAC_TYPE_FILTER_SUP(hw->mac.type);
6188
6189         if (filter_op == RTE_ETH_FILTER_NOP)
6190                 return 0;
6191
6192         if (arg == NULL) {
6193                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6194                             filter_op);
6195                 return -EINVAL;
6196         }
6197
6198         switch (filter_op) {
6199         case RTE_ETH_FILTER_ADD:
6200                 ret = ixgbe_add_del_ethertype_filter(dev,
6201                         (struct rte_eth_ethertype_filter *)arg,
6202                         TRUE);
6203                 break;
6204         case RTE_ETH_FILTER_DELETE:
6205                 ret = ixgbe_add_del_ethertype_filter(dev,
6206                         (struct rte_eth_ethertype_filter *)arg,
6207                         FALSE);
6208                 break;
6209         case RTE_ETH_FILTER_GET:
6210                 ret = ixgbe_get_ethertype_filter(dev,
6211                         (struct rte_eth_ethertype_filter *)arg);
6212                 break;
6213         default:
6214                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6215                 ret = -EINVAL;
6216                 break;
6217         }
6218         return ret;
6219 }
6220
6221 static int
6222 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6223                      enum rte_filter_type filter_type,
6224                      enum rte_filter_op filter_op,
6225                      void *arg)
6226 {
6227         int ret = -EINVAL;
6228
6229         switch (filter_type) {
6230         case RTE_ETH_FILTER_NTUPLE:
6231                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6232                 break;
6233         case RTE_ETH_FILTER_ETHERTYPE:
6234                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6235                 break;
6236         case RTE_ETH_FILTER_SYN:
6237                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6238                 break;
6239         case RTE_ETH_FILTER_FDIR:
6240                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6241                 break;
6242         case RTE_ETH_FILTER_L2_TUNNEL:
6243                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6244                 break;
6245         default:
6246                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6247                                                         filter_type);
6248                 break;
6249         }
6250
6251         return ret;
6252 }
6253
6254 static u8 *
6255 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6256                         u8 **mc_addr_ptr, u32 *vmdq)
6257 {
6258         u8 *mc_addr;
6259
6260         *vmdq = 0;
6261         mc_addr = *mc_addr_ptr;
6262         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6263         return mc_addr;
6264 }
6265
6266 static int
6267 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6268                           struct ether_addr *mc_addr_set,
6269                           uint32_t nb_mc_addr)
6270 {
6271         struct ixgbe_hw *hw;
6272         u8 *mc_addr_list;
6273
6274         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6275         mc_addr_list = (u8 *)mc_addr_set;
6276         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6277                                          ixgbe_dev_addr_list_itr, TRUE);
6278 }
6279
6280 static uint64_t
6281 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6282 {
6283         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6284         uint64_t systime_cycles;
6285
6286         switch (hw->mac.type) {
6287         case ixgbe_mac_X550:
6288         case ixgbe_mac_X550EM_x:
6289         case ixgbe_mac_X550EM_a:
6290                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6291                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6292                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6293                                 * NSEC_PER_SEC;
6294                 break;
6295         default:
6296                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6297                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6298                                 << 32;
6299         }
6300
6301         return systime_cycles;
6302 }
6303
6304 static uint64_t
6305 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6306 {
6307         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6308         uint64_t rx_tstamp_cycles;
6309
6310         switch (hw->mac.type) {
6311         case ixgbe_mac_X550:
6312         case ixgbe_mac_X550EM_x:
6313         case ixgbe_mac_X550EM_a:
6314                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6315                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6316                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6317                                 * NSEC_PER_SEC;
6318                 break;
6319         default:
6320                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6321                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6322                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6323                                 << 32;
6324         }
6325
6326         return rx_tstamp_cycles;
6327 }
6328
6329 static uint64_t
6330 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6331 {
6332         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6333         uint64_t tx_tstamp_cycles;
6334
6335         switch (hw->mac.type) {
6336         case ixgbe_mac_X550:
6337         case ixgbe_mac_X550EM_x:
6338         case ixgbe_mac_X550EM_a:
6339                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6340                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6341                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6342                                 * NSEC_PER_SEC;
6343                 break;
6344         default:
6345                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6346                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6347                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6348                                 << 32;
6349         }
6350
6351         return tx_tstamp_cycles;
6352 }
6353
6354 static void
6355 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6356 {
6357         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6358         struct ixgbe_adapter *adapter =
6359                 (struct ixgbe_adapter *)dev->data->dev_private;
6360         struct rte_eth_link link;
6361         uint32_t incval = 0;
6362         uint32_t shift = 0;
6363
6364         /* Get current link speed. */
6365         memset(&link, 0, sizeof(link));
6366         ixgbe_dev_link_update(dev, 1);
6367         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6368
6369         switch (link.link_speed) {
6370         case ETH_SPEED_NUM_100M:
6371                 incval = IXGBE_INCVAL_100;
6372                 shift = IXGBE_INCVAL_SHIFT_100;
6373                 break;
6374         case ETH_SPEED_NUM_1G:
6375                 incval = IXGBE_INCVAL_1GB;
6376                 shift = IXGBE_INCVAL_SHIFT_1GB;
6377                 break;
6378         case ETH_SPEED_NUM_10G:
6379         default:
6380                 incval = IXGBE_INCVAL_10GB;
6381                 shift = IXGBE_INCVAL_SHIFT_10GB;
6382                 break;
6383         }
6384
6385         switch (hw->mac.type) {
6386         case ixgbe_mac_X550:
6387         case ixgbe_mac_X550EM_x:
6388         case ixgbe_mac_X550EM_a:
6389                 /* Independent of link speed. */
6390                 incval = 1;
6391                 /* Cycles read will be interpreted as ns. */
6392                 shift = 0;
6393                 /* Fall-through */
6394         case ixgbe_mac_X540:
6395                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6396                 break;
6397         case ixgbe_mac_82599EB:
6398                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6399                 shift -= IXGBE_INCVAL_SHIFT_82599;
6400                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6401                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6402                 break;
6403         default:
6404                 /* Not supported. */
6405                 return;
6406         }
6407
6408         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6409         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6410         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6411
6412         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6413         adapter->systime_tc.cc_shift = shift;
6414         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6415
6416         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6417         adapter->rx_tstamp_tc.cc_shift = shift;
6418         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6419
6420         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6421         adapter->tx_tstamp_tc.cc_shift = shift;
6422         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6423 }
6424
6425 static int
6426 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6427 {
6428         struct ixgbe_adapter *adapter =
6429                         (struct ixgbe_adapter *)dev->data->dev_private;
6430
6431         adapter->systime_tc.nsec += delta;
6432         adapter->rx_tstamp_tc.nsec += delta;
6433         adapter->tx_tstamp_tc.nsec += delta;
6434
6435         return 0;
6436 }
6437
6438 static int
6439 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6440 {
6441         uint64_t ns;
6442         struct ixgbe_adapter *adapter =
6443                         (struct ixgbe_adapter *)dev->data->dev_private;
6444
6445         ns = rte_timespec_to_ns(ts);
6446         /* Set the timecounters to a new value. */
6447         adapter->systime_tc.nsec = ns;
6448         adapter->rx_tstamp_tc.nsec = ns;
6449         adapter->tx_tstamp_tc.nsec = ns;
6450
6451         return 0;
6452 }
6453
6454 static int
6455 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6456 {
6457         uint64_t ns, systime_cycles;
6458         struct ixgbe_adapter *adapter =
6459                         (struct ixgbe_adapter *)dev->data->dev_private;
6460
6461         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6462         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6463         *ts = rte_ns_to_timespec(ns);
6464
6465         return 0;
6466 }
6467
6468 static int
6469 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6470 {
6471         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6472         uint32_t tsync_ctl;
6473         uint32_t tsauxc;
6474
6475         /* Stop the timesync system time. */
6476         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6477         /* Reset the timesync system time value. */
6478         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6479         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6480
6481         /* Enable system time for platforms where it isn't on by default. */
6482         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6483         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6484         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6485
6486         ixgbe_start_timecounters(dev);
6487
6488         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6489         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6490                         (ETHER_TYPE_1588 |
6491                          IXGBE_ETQF_FILTER_EN |
6492                          IXGBE_ETQF_1588));
6493
6494         /* Enable timestamping of received PTP packets. */
6495         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6496         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6497         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6498
6499         /* Enable timestamping of transmitted PTP packets. */
6500         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6501         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6502         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6503
6504         IXGBE_WRITE_FLUSH(hw);
6505
6506         return 0;
6507 }
6508
6509 static int
6510 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6511 {
6512         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6513         uint32_t tsync_ctl;
6514
6515         /* Disable timestamping of transmitted PTP packets. */
6516         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6517         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6518         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6519
6520         /* Disable timestamping of received PTP packets. */
6521         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6522         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6523         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6524
6525         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6526         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6527
6528         /* Stop incrementating the System Time registers. */
6529         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6530
6531         return 0;
6532 }
6533
6534 static int
6535 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6536                                  struct timespec *timestamp,
6537                                  uint32_t flags __rte_unused)
6538 {
6539         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6540         struct ixgbe_adapter *adapter =
6541                 (struct ixgbe_adapter *)dev->data->dev_private;
6542         uint32_t tsync_rxctl;
6543         uint64_t rx_tstamp_cycles;
6544         uint64_t ns;
6545
6546         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6547         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6548                 return -EINVAL;
6549
6550         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6551         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6552         *timestamp = rte_ns_to_timespec(ns);
6553
6554         return  0;
6555 }
6556
6557 static int
6558 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6559                                  struct timespec *timestamp)
6560 {
6561         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6562         struct ixgbe_adapter *adapter =
6563                 (struct ixgbe_adapter *)dev->data->dev_private;
6564         uint32_t tsync_txctl;
6565         uint64_t tx_tstamp_cycles;
6566         uint64_t ns;
6567
6568         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6569         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6570                 return -EINVAL;
6571
6572         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6573         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6574         *timestamp = rte_ns_to_timespec(ns);
6575
6576         return 0;
6577 }
6578
6579 static int
6580 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6581 {
6582         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6583         int count = 0;
6584         int g_ind = 0;
6585         const struct reg_info *reg_group;
6586         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6587                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6588
6589         while ((reg_group = reg_set[g_ind++]))
6590                 count += ixgbe_regs_group_count(reg_group);
6591
6592         return count;
6593 }
6594
6595 static int
6596 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6597 {
6598         int count = 0;
6599         int g_ind = 0;
6600         const struct reg_info *reg_group;
6601
6602         while ((reg_group = ixgbevf_regs[g_ind++]))
6603                 count += ixgbe_regs_group_count(reg_group);
6604
6605         return count;
6606 }
6607
6608 static int
6609 ixgbe_get_regs(struct rte_eth_dev *dev,
6610               struct rte_dev_reg_info *regs)
6611 {
6612         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6613         uint32_t *data = regs->data;
6614         int g_ind = 0;
6615         int count = 0;
6616         const struct reg_info *reg_group;
6617         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6618                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6619
6620         if (data == NULL) {
6621                 regs->length = ixgbe_get_reg_length(dev);
6622                 regs->width = sizeof(uint32_t);
6623                 return 0;
6624         }
6625
6626         /* Support only full register dump */
6627         if ((regs->length == 0) ||
6628             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6629                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6630                         hw->device_id;
6631                 while ((reg_group = reg_set[g_ind++]))
6632                         count += ixgbe_read_regs_group(dev, &data[count],
6633                                 reg_group);
6634                 return 0;
6635         }
6636
6637         return -ENOTSUP;
6638 }
6639
6640 static int
6641 ixgbevf_get_regs(struct rte_eth_dev *dev,
6642                 struct rte_dev_reg_info *regs)
6643 {
6644         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6645         uint32_t *data = regs->data;
6646         int g_ind = 0;
6647         int count = 0;
6648         const struct reg_info *reg_group;
6649
6650         if (data == NULL) {
6651                 regs->length = ixgbevf_get_reg_length(dev);
6652                 regs->width = sizeof(uint32_t);
6653                 return 0;
6654         }
6655
6656         /* Support only full register dump */
6657         if ((regs->length == 0) ||
6658             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6659                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6660                         hw->device_id;
6661                 while ((reg_group = ixgbevf_regs[g_ind++]))
6662                         count += ixgbe_read_regs_group(dev, &data[count],
6663                                                       reg_group);
6664                 return 0;
6665         }
6666
6667         return -ENOTSUP;
6668 }
6669
6670 static int
6671 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6672 {
6673         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6674
6675         /* Return unit is byte count */
6676         return hw->eeprom.word_size * 2;
6677 }
6678
6679 static int
6680 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6681                 struct rte_dev_eeprom_info *in_eeprom)
6682 {
6683         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6684         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6685         uint16_t *data = in_eeprom->data;
6686         int first, length;
6687
6688         first = in_eeprom->offset >> 1;
6689         length = in_eeprom->length >> 1;
6690         if ((first > hw->eeprom.word_size) ||
6691             ((first + length) > hw->eeprom.word_size))
6692                 return -EINVAL;
6693
6694         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6695
6696         return eeprom->ops.read_buffer(hw, first, length, data);
6697 }
6698
6699 static int
6700 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6701                 struct rte_dev_eeprom_info *in_eeprom)
6702 {
6703         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6704         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6705         uint16_t *data = in_eeprom->data;
6706         int first, length;
6707
6708         first = in_eeprom->offset >> 1;
6709         length = in_eeprom->length >> 1;
6710         if ((first > hw->eeprom.word_size) ||
6711             ((first + length) > hw->eeprom.word_size))
6712                 return -EINVAL;
6713
6714         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6715
6716         return eeprom->ops.write_buffer(hw,  first, length, data);
6717 }
6718
6719 uint16_t
6720 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6721         switch (mac_type) {
6722         case ixgbe_mac_X550:
6723         case ixgbe_mac_X550EM_x:
6724         case ixgbe_mac_X550EM_a:
6725                 return ETH_RSS_RETA_SIZE_512;
6726         case ixgbe_mac_X550_vf:
6727         case ixgbe_mac_X550EM_x_vf:
6728         case ixgbe_mac_X550EM_a_vf:
6729                 return ETH_RSS_RETA_SIZE_64;
6730         default:
6731                 return ETH_RSS_RETA_SIZE_128;
6732         }
6733 }
6734
6735 uint32_t
6736 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6737         switch (mac_type) {
6738         case ixgbe_mac_X550:
6739         case ixgbe_mac_X550EM_x:
6740         case ixgbe_mac_X550EM_a:
6741                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6742                         return IXGBE_RETA(reta_idx >> 2);
6743                 else
6744                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6745         case ixgbe_mac_X550_vf:
6746         case ixgbe_mac_X550EM_x_vf:
6747         case ixgbe_mac_X550EM_a_vf:
6748                 return IXGBE_VFRETA(reta_idx >> 2);
6749         default:
6750                 return IXGBE_RETA(reta_idx >> 2);
6751         }
6752 }
6753
6754 uint32_t
6755 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6756         switch (mac_type) {
6757         case ixgbe_mac_X550_vf:
6758         case ixgbe_mac_X550EM_x_vf:
6759         case ixgbe_mac_X550EM_a_vf:
6760                 return IXGBE_VFMRQC;
6761         default:
6762                 return IXGBE_MRQC;
6763         }
6764 }
6765
6766 uint32_t
6767 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6768         switch (mac_type) {
6769         case ixgbe_mac_X550_vf:
6770         case ixgbe_mac_X550EM_x_vf:
6771         case ixgbe_mac_X550EM_a_vf:
6772                 return IXGBE_VFRSSRK(i);
6773         default:
6774                 return IXGBE_RSSRK(i);
6775         }
6776 }
6777
6778 bool
6779 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6780         switch (mac_type) {
6781         case ixgbe_mac_82599_vf:
6782         case ixgbe_mac_X540_vf:
6783                 return 0;
6784         default:
6785                 return 1;
6786         }
6787 }
6788
6789 static int
6790 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6791                         struct rte_eth_dcb_info *dcb_info)
6792 {
6793         struct ixgbe_dcb_config *dcb_config =
6794                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6795         struct ixgbe_dcb_tc_config *tc;
6796         uint8_t i, j;
6797
6798         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6799                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6800         else
6801                 dcb_info->nb_tcs = 1;
6802
6803         if (dcb_config->vt_mode) { /* vt is enabled*/
6804                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6805                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6806                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6807                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6808                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6809                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6810                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6811                                                 i * dcb_info->nb_tcs + j;
6812                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6813                                 dcb_info->tc_queue.tc_txq[i][j].base =
6814                                                 i * dcb_info->nb_tcs + j;
6815                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6816                         }
6817                 }
6818         } else { /* vt is disabled*/
6819                 struct rte_eth_dcb_rx_conf *rx_conf =
6820                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6821                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6822                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6823                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6824                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6825                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6826                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6827                         }
6828                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6829                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6830                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6831                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6832                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6833                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6834                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6835                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6836                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6837                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6838                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6839                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6840                         }
6841                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6842                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6843                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6844                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6845                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6846                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6847                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6848                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6849                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6850                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6851                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6852                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6853                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6854                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6855                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6856                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6857                 }
6858         }
6859         for (i = 0; i < dcb_info->nb_tcs; i++) {
6860                 tc = &dcb_config->tc_config[i];
6861                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6862         }
6863         return 0;
6864 }
6865
6866 /* Update e-tag ether type */
6867 static int
6868 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6869                             uint16_t ether_type)
6870 {
6871         uint32_t etag_etype;
6872
6873         if (hw->mac.type != ixgbe_mac_X550 &&
6874             hw->mac.type != ixgbe_mac_X550EM_x &&
6875             hw->mac.type != ixgbe_mac_X550EM_a) {
6876                 return -ENOTSUP;
6877         }
6878
6879         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6880         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6881         etag_etype |= ether_type;
6882         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6883         IXGBE_WRITE_FLUSH(hw);
6884
6885         return 0;
6886 }
6887
6888 /* Config l2 tunnel ether type */
6889 static int
6890 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6891                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6892 {
6893         int ret = 0;
6894         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6895
6896         if (l2_tunnel == NULL)
6897                 return -EINVAL;
6898
6899         switch (l2_tunnel->l2_tunnel_type) {
6900         case RTE_L2_TUNNEL_TYPE_E_TAG:
6901                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6902                 break;
6903         default:
6904                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6905                 ret = -EINVAL;
6906                 break;
6907         }
6908
6909         return ret;
6910 }
6911
6912 /* Enable e-tag tunnel */
6913 static int
6914 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6915 {
6916         uint32_t etag_etype;
6917
6918         if (hw->mac.type != ixgbe_mac_X550 &&
6919             hw->mac.type != ixgbe_mac_X550EM_x &&
6920             hw->mac.type != ixgbe_mac_X550EM_a) {
6921                 return -ENOTSUP;
6922         }
6923
6924         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6925         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6926         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6927         IXGBE_WRITE_FLUSH(hw);
6928
6929         return 0;
6930 }
6931
6932 /* Enable l2 tunnel */
6933 static int
6934 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6935                            enum rte_eth_tunnel_type l2_tunnel_type)
6936 {
6937         int ret = 0;
6938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6939
6940         switch (l2_tunnel_type) {
6941         case RTE_L2_TUNNEL_TYPE_E_TAG:
6942                 ret = ixgbe_e_tag_enable(hw);
6943                 break;
6944         default:
6945                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6946                 ret = -EINVAL;
6947                 break;
6948         }
6949
6950         return ret;
6951 }
6952
6953 /* Disable e-tag tunnel */
6954 static int
6955 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6956 {
6957         uint32_t etag_etype;
6958
6959         if (hw->mac.type != ixgbe_mac_X550 &&
6960             hw->mac.type != ixgbe_mac_X550EM_x &&
6961             hw->mac.type != ixgbe_mac_X550EM_a) {
6962                 return -ENOTSUP;
6963         }
6964
6965         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6966         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6967         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6968         IXGBE_WRITE_FLUSH(hw);
6969
6970         return 0;
6971 }
6972
6973 /* Disable l2 tunnel */
6974 static int
6975 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6976                             enum rte_eth_tunnel_type l2_tunnel_type)
6977 {
6978         int ret = 0;
6979         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6980
6981         switch (l2_tunnel_type) {
6982         case RTE_L2_TUNNEL_TYPE_E_TAG:
6983                 ret = ixgbe_e_tag_disable(hw);
6984                 break;
6985         default:
6986                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6987                 ret = -EINVAL;
6988                 break;
6989         }
6990
6991         return ret;
6992 }
6993
6994 static int
6995 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6996                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6997 {
6998         int ret = 0;
6999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7000         uint32_t i, rar_entries;
7001         uint32_t rar_low, rar_high;
7002
7003         if (hw->mac.type != ixgbe_mac_X550 &&
7004             hw->mac.type != ixgbe_mac_X550EM_x &&
7005             hw->mac.type != ixgbe_mac_X550EM_a) {
7006                 return -ENOTSUP;
7007         }
7008
7009         rar_entries = ixgbe_get_num_rx_addrs(hw);
7010
7011         for (i = 1; i < rar_entries; i++) {
7012                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7013                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7014                 if ((rar_high & IXGBE_RAH_AV) &&
7015                     (rar_high & IXGBE_RAH_ADTYPE) &&
7016                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7017                      l2_tunnel->tunnel_id)) {
7018                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7019                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7020
7021                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7022
7023                         return ret;
7024                 }
7025         }
7026
7027         return ret;
7028 }
7029
7030 static int
7031 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7032                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7033 {
7034         int ret = 0;
7035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7036         uint32_t i, rar_entries;
7037         uint32_t rar_low, rar_high;
7038
7039         if (hw->mac.type != ixgbe_mac_X550 &&
7040             hw->mac.type != ixgbe_mac_X550EM_x &&
7041             hw->mac.type != ixgbe_mac_X550EM_a) {
7042                 return -ENOTSUP;
7043         }
7044
7045         /* One entry for one tunnel. Try to remove potential existing entry. */
7046         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7047
7048         rar_entries = ixgbe_get_num_rx_addrs(hw);
7049
7050         for (i = 1; i < rar_entries; i++) {
7051                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7052                 if (rar_high & IXGBE_RAH_AV) {
7053                         continue;
7054                 } else {
7055                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7056                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7057                         rar_low = l2_tunnel->tunnel_id;
7058
7059                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7060                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7061
7062                         return ret;
7063                 }
7064         }
7065
7066         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7067                      " Please remove a rule before adding a new one.");
7068         return -EINVAL;
7069 }
7070
7071 /* Add l2 tunnel filter */
7072 static int
7073 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7074                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7075 {
7076         int ret = 0;
7077
7078         switch (l2_tunnel->l2_tunnel_type) {
7079         case RTE_L2_TUNNEL_TYPE_E_TAG:
7080                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7081                 break;
7082         default:
7083                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7084                 ret = -EINVAL;
7085                 break;
7086         }
7087
7088         return ret;
7089 }
7090
7091 /* Delete l2 tunnel filter */
7092 static int
7093 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7094                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7095 {
7096         int ret = 0;
7097
7098         switch (l2_tunnel->l2_tunnel_type) {
7099         case RTE_L2_TUNNEL_TYPE_E_TAG:
7100                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7101                 break;
7102         default:
7103                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7104                 ret = -EINVAL;
7105                 break;
7106         }
7107
7108         return ret;
7109 }
7110
7111 /**
7112  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7113  * @dev: pointer to rte_eth_dev structure
7114  * @filter_op:operation will be taken.
7115  * @arg: a pointer to specific structure corresponding to the filter_op
7116  */
7117 static int
7118 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7119                                   enum rte_filter_op filter_op,
7120                                   void *arg)
7121 {
7122         int ret = 0;
7123
7124         if (filter_op == RTE_ETH_FILTER_NOP)
7125                 return 0;
7126
7127         if (arg == NULL) {
7128                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7129                             filter_op);
7130                 return -EINVAL;
7131         }
7132
7133         switch (filter_op) {
7134         case RTE_ETH_FILTER_ADD:
7135                 ret = ixgbe_dev_l2_tunnel_filter_add
7136                         (dev,
7137                          (struct rte_eth_l2_tunnel_conf *)arg);
7138                 break;
7139         case RTE_ETH_FILTER_DELETE:
7140                 ret = ixgbe_dev_l2_tunnel_filter_del
7141                         (dev,
7142                          (struct rte_eth_l2_tunnel_conf *)arg);
7143                 break;
7144         default:
7145                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7146                 ret = -EINVAL;
7147                 break;
7148         }
7149         return ret;
7150 }
7151
7152 static int
7153 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7154 {
7155         int ret = 0;
7156         uint32_t ctrl;
7157         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7158
7159         if (hw->mac.type != ixgbe_mac_X550 &&
7160             hw->mac.type != ixgbe_mac_X550EM_x &&
7161             hw->mac.type != ixgbe_mac_X550EM_a) {
7162                 return -ENOTSUP;
7163         }
7164
7165         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7166         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7167         if (en)
7168                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7169         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7170
7171         return ret;
7172 }
7173
7174 /* Enable l2 tunnel forwarding */
7175 static int
7176 ixgbe_dev_l2_tunnel_forwarding_enable
7177         (struct rte_eth_dev *dev,
7178          enum rte_eth_tunnel_type l2_tunnel_type)
7179 {
7180         int ret = 0;
7181
7182         switch (l2_tunnel_type) {
7183         case RTE_L2_TUNNEL_TYPE_E_TAG:
7184                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7185                 break;
7186         default:
7187                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7188                 ret = -EINVAL;
7189                 break;
7190         }
7191
7192         return ret;
7193 }
7194
7195 /* Disable l2 tunnel forwarding */
7196 static int
7197 ixgbe_dev_l2_tunnel_forwarding_disable
7198         (struct rte_eth_dev *dev,
7199          enum rte_eth_tunnel_type l2_tunnel_type)
7200 {
7201         int ret = 0;
7202
7203         switch (l2_tunnel_type) {
7204         case RTE_L2_TUNNEL_TYPE_E_TAG:
7205                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7206                 break;
7207         default:
7208                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7209                 ret = -EINVAL;
7210                 break;
7211         }
7212
7213         return ret;
7214 }
7215
7216 static int
7217 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7218                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7219                              bool en)
7220 {
7221         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7222         int ret = 0;
7223         uint32_t vmtir, vmvir;
7224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7225
7226         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7227                 PMD_DRV_LOG(ERR,
7228                             "VF id %u should be less than %u",
7229                             l2_tunnel->vf_id,
7230                             pci_dev->max_vfs);
7231                 return -EINVAL;
7232         }
7233
7234         if (hw->mac.type != ixgbe_mac_X550 &&
7235             hw->mac.type != ixgbe_mac_X550EM_x &&
7236             hw->mac.type != ixgbe_mac_X550EM_a) {
7237                 return -ENOTSUP;
7238         }
7239
7240         if (en)
7241                 vmtir = l2_tunnel->tunnel_id;
7242         else
7243                 vmtir = 0;
7244
7245         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7246
7247         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7248         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7249         if (en)
7250                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7251         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7252
7253         return ret;
7254 }
7255
7256 /* Enable l2 tunnel tag insertion */
7257 static int
7258 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7259                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7260 {
7261         int ret = 0;
7262
7263         switch (l2_tunnel->l2_tunnel_type) {
7264         case RTE_L2_TUNNEL_TYPE_E_TAG:
7265                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7266                 break;
7267         default:
7268                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7269                 ret = -EINVAL;
7270                 break;
7271         }
7272
7273         return ret;
7274 }
7275
7276 /* Disable l2 tunnel tag insertion */
7277 static int
7278 ixgbe_dev_l2_tunnel_insertion_disable
7279         (struct rte_eth_dev *dev,
7280          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7281 {
7282         int ret = 0;
7283
7284         switch (l2_tunnel->l2_tunnel_type) {
7285         case RTE_L2_TUNNEL_TYPE_E_TAG:
7286                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7287                 break;
7288         default:
7289                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7290                 ret = -EINVAL;
7291                 break;
7292         }
7293
7294         return ret;
7295 }
7296
7297 static int
7298 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7299                              bool en)
7300 {
7301         int ret = 0;
7302         uint32_t qde;
7303         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7304
7305         if (hw->mac.type != ixgbe_mac_X550 &&
7306             hw->mac.type != ixgbe_mac_X550EM_x &&
7307             hw->mac.type != ixgbe_mac_X550EM_a) {
7308                 return -ENOTSUP;
7309         }
7310
7311         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7312         if (en)
7313                 qde |= IXGBE_QDE_STRIP_TAG;
7314         else
7315                 qde &= ~IXGBE_QDE_STRIP_TAG;
7316         qde &= ~IXGBE_QDE_READ;
7317         qde |= IXGBE_QDE_WRITE;
7318         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7319
7320         return ret;
7321 }
7322
7323 /* Enable l2 tunnel tag stripping */
7324 static int
7325 ixgbe_dev_l2_tunnel_stripping_enable
7326         (struct rte_eth_dev *dev,
7327          enum rte_eth_tunnel_type l2_tunnel_type)
7328 {
7329         int ret = 0;
7330
7331         switch (l2_tunnel_type) {
7332         case RTE_L2_TUNNEL_TYPE_E_TAG:
7333                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7334                 break;
7335         default:
7336                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7337                 ret = -EINVAL;
7338                 break;
7339         }
7340
7341         return ret;
7342 }
7343
7344 /* Disable l2 tunnel tag stripping */
7345 static int
7346 ixgbe_dev_l2_tunnel_stripping_disable
7347         (struct rte_eth_dev *dev,
7348          enum rte_eth_tunnel_type l2_tunnel_type)
7349 {
7350         int ret = 0;
7351
7352         switch (l2_tunnel_type) {
7353         case RTE_L2_TUNNEL_TYPE_E_TAG:
7354                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7355                 break;
7356         default:
7357                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7358                 ret = -EINVAL;
7359                 break;
7360         }
7361
7362         return ret;
7363 }
7364
7365 /* Enable/disable l2 tunnel offload functions */
7366 static int
7367 ixgbe_dev_l2_tunnel_offload_set
7368         (struct rte_eth_dev *dev,
7369          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7370          uint32_t mask,
7371          uint8_t en)
7372 {
7373         int ret = 0;
7374
7375         if (l2_tunnel == NULL)
7376                 return -EINVAL;
7377
7378         ret = -EINVAL;
7379         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7380                 if (en)
7381                         ret = ixgbe_dev_l2_tunnel_enable(
7382                                 dev,
7383                                 l2_tunnel->l2_tunnel_type);
7384                 else
7385                         ret = ixgbe_dev_l2_tunnel_disable(
7386                                 dev,
7387                                 l2_tunnel->l2_tunnel_type);
7388         }
7389
7390         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7391                 if (en)
7392                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7393                                 dev,
7394                                 l2_tunnel);
7395                 else
7396                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7397                                 dev,
7398                                 l2_tunnel);
7399         }
7400
7401         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7402                 if (en)
7403                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7404                                 dev,
7405                                 l2_tunnel->l2_tunnel_type);
7406                 else
7407                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7408                                 dev,
7409                                 l2_tunnel->l2_tunnel_type);
7410         }
7411
7412         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7413                 if (en)
7414                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7415                                 dev,
7416                                 l2_tunnel->l2_tunnel_type);
7417                 else
7418                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7419                                 dev,
7420                                 l2_tunnel->l2_tunnel_type);
7421         }
7422
7423         return ret;
7424 }
7425
7426 static int
7427 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7428                         uint16_t port)
7429 {
7430         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7431         IXGBE_WRITE_FLUSH(hw);
7432
7433         return 0;
7434 }
7435
7436 /* There's only one register for VxLAN UDP port.
7437  * So, we cannot add several ports. Will update it.
7438  */
7439 static int
7440 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7441                      uint16_t port)
7442 {
7443         if (port == 0) {
7444                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7445                 return -EINVAL;
7446         }
7447
7448         return ixgbe_update_vxlan_port(hw, port);
7449 }
7450
7451 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7452  * UDP port, it must have a value.
7453  * So, will reset it to the original value 0.
7454  */
7455 static int
7456 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7457                      uint16_t port)
7458 {
7459         uint16_t cur_port;
7460
7461         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7462
7463         if (cur_port != port) {
7464                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7465                 return -EINVAL;
7466         }
7467
7468         return ixgbe_update_vxlan_port(hw, 0);
7469 }
7470
7471 /* Add UDP tunneling port */
7472 static int
7473 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7474                               struct rte_eth_udp_tunnel *udp_tunnel)
7475 {
7476         int ret = 0;
7477         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7478
7479         if (hw->mac.type != ixgbe_mac_X550 &&
7480             hw->mac.type != ixgbe_mac_X550EM_x &&
7481             hw->mac.type != ixgbe_mac_X550EM_a) {
7482                 return -ENOTSUP;
7483         }
7484
7485         if (udp_tunnel == NULL)
7486                 return -EINVAL;
7487
7488         switch (udp_tunnel->prot_type) {
7489         case RTE_TUNNEL_TYPE_VXLAN:
7490                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7491                 break;
7492
7493         case RTE_TUNNEL_TYPE_GENEVE:
7494         case RTE_TUNNEL_TYPE_TEREDO:
7495                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7496                 ret = -EINVAL;
7497                 break;
7498
7499         default:
7500                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7501                 ret = -EINVAL;
7502                 break;
7503         }
7504
7505         return ret;
7506 }
7507
7508 /* Remove UDP tunneling port */
7509 static int
7510 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7511                               struct rte_eth_udp_tunnel *udp_tunnel)
7512 {
7513         int ret = 0;
7514         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7515
7516         if (hw->mac.type != ixgbe_mac_X550 &&
7517             hw->mac.type != ixgbe_mac_X550EM_x &&
7518             hw->mac.type != ixgbe_mac_X550EM_a) {
7519                 return -ENOTSUP;
7520         }
7521
7522         if (udp_tunnel == NULL)
7523                 return -EINVAL;
7524
7525         switch (udp_tunnel->prot_type) {
7526         case RTE_TUNNEL_TYPE_VXLAN:
7527                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7528                 break;
7529         case RTE_TUNNEL_TYPE_GENEVE:
7530         case RTE_TUNNEL_TYPE_TEREDO:
7531                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7532                 ret = -EINVAL;
7533                 break;
7534         default:
7535                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7536                 ret = -EINVAL;
7537                 break;
7538         }
7539
7540         return ret;
7541 }
7542
7543 static void
7544 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7545 {
7546         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7547
7548         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7549 }
7550
7551 static void
7552 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7553 {
7554         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7555
7556         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7557 }
7558
7559 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7560 {
7561         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7562         u32 in_msg = 0;
7563
7564         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7565                 return;
7566
7567         /* PF reset VF event */
7568         if (in_msg == IXGBE_PF_CONTROL_MSG)
7569                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7570 }
7571
7572 static int
7573 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7574 {
7575         uint32_t eicr;
7576         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7577         struct ixgbe_interrupt *intr =
7578                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7579         ixgbevf_intr_disable(hw);
7580
7581         /* read-on-clear nic registers here */
7582         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7583         intr->flags = 0;
7584
7585         /* only one misc vector supported - mailbox */
7586         eicr &= IXGBE_VTEICR_MASK;
7587         if (eicr == IXGBE_MISC_VEC_ID)
7588                 intr->flags |= IXGBE_FLAG_MAILBOX;
7589
7590         return 0;
7591 }
7592
7593 static int
7594 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7595 {
7596         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7597         struct ixgbe_interrupt *intr =
7598                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7599
7600         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7601                 ixgbevf_mbx_process(dev);
7602                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7603         }
7604
7605         ixgbevf_intr_enable(hw);
7606
7607         return 0;
7608 }
7609
7610 static void
7611 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7612                               void *param)
7613 {
7614         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7615
7616         ixgbevf_dev_interrupt_get_status(dev);
7617         ixgbevf_dev_interrupt_action(dev);
7618 }
7619
7620 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7621 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7622 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
7623 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7624 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
7625 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");