drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define IXGBE_TIMINCA_16NS_SHIFT 24
 130 #define IXGBE_TIMINCA_INCVALUE   16000000
 131 #define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
 132                                   | IXGBE_TIMINCA_INCVALUE)
 133
 134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 147                                 int wait_to_complete);
 148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 149                                 struct rte_eth_stats *stats);
 150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 151                                 struct rte_eth_xstats *xstats, unsigned n);
 152 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 153 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 155                                              uint16_t queue_id,
 156                                              uint8_t stat_idx,
 157                                              uint8_t is_rx);
 158 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 159                                struct rte_eth_dev_info *dev_info);
 160 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 161                                  struct rte_eth_dev_info *dev_info);
 162 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 163
 164 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 165                 uint16_t vlan_id, int on);
 166 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 167 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 168                 uint16_t queue, bool on);
 169 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 170                 int on);
 171 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 172 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 173 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 174 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 176
 177 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 179 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 180                                struct rte_eth_fc_conf *fc_conf);
 181 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 182                                struct rte_eth_fc_conf *fc_conf);
 183 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 184                 struct rte_eth_pfc_conf *pfc_conf);
 185 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 186                         struct rte_eth_rss_reta_entry64 *reta_conf,
 187                         uint16_t reta_size);
 188 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 189                         struct rte_eth_rss_reta_entry64 *reta_conf,
 190                         uint16_t reta_size);
 191 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 192 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 193 #ifdef RTE_NEXT_ABI
 194 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 195 #endif
 196 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 197 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 198 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 199                 void *param);
 200 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 201 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 202                 uint32_t index, uint32_t pool);
 203 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 204 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 205                                            struct ether_addr *mac_addr);
 206 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 207
 208 /* For Virtual Function support */
 209 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 210 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 211 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
 212 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
 213 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 214 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 215 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 216 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 217 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 218 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 219 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 220                 struct rte_eth_stats *stats);
 221 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 222 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 223                 uint16_t vlan_id, int on);
 224 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 225                 uint16_t queue, int on);
 226 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 227 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 228 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 229                                           void *param);
 230 #ifdef RTE_NEXT_ABI
 231 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 232                                             uint16_t queue_id);
 233 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 234                                              uint16_t queue_id);
 235 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 236                                  uint8_t queue, uint8_t msix_vector);
 237 #endif
 238 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 239
 240 /* For Eth VMDQ APIs support */
 241 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 242                 ether_addr* mac_addr,uint8_t on);
 243 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 244 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 245                 uint16_t rx_mask, uint8_t on);
 246 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 247 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 248 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 249                 uint64_t pool_mask,uint8_t vlan_on);
 250 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 251                 struct rte_eth_mirror_conf *mirror_conf,
 252                 uint8_t rule_id, uint8_t on);
 253 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 254                 uint8_t rule_id);
 255 #ifdef RTE_NEXT_ABI
 256 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 257                                           uint16_t queue_id);
 258 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 259                                            uint16_t queue_id);
 260 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 261                                uint8_t queue, uint8_t msix_vector);
 262 #endif
 263 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 264
 265 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 266                 uint16_t queue_idx, uint16_t tx_rate);
 267 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 268                 uint16_t tx_rate, uint64_t q_msk);
 269
 270 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 271                                  struct ether_addr *mac_addr,
 272                                  uint32_t index, uint32_t pool);
 273 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 274 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 275                                              struct ether_addr *mac_addr);
 276 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 277                         struct rte_eth_syn_filter *filter,
 278                         bool add);
 279 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 280                         struct rte_eth_syn_filter *filter);
 281 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 282                         enum rte_filter_op filter_op,
 283                         void *arg);
 284 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 285                         struct ixgbe_5tuple_filter *filter);
 286 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 287                         struct ixgbe_5tuple_filter *filter);
 288 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 289                         struct rte_eth_ntuple_filter *filter,
 290                         bool add);
 291 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 292                                 enum rte_filter_op filter_op,
 293                                 void *arg);
 294 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 295                         struct rte_eth_ntuple_filter *filter);
 296 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 297                         struct rte_eth_ethertype_filter *filter,
 298                         bool add);
 299 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 300                                 enum rte_filter_op filter_op,
 301                                 void *arg);
 302 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 303                         struct rte_eth_ethertype_filter *filter);
 304 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 305                      enum rte_filter_type filter_type,
 306                      enum rte_filter_op filter_op,
 307                      void *arg);
 308 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 309
 310 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 311                                       struct ether_addr *mc_addr_set,
 312                                       uint32_t nb_mc_addr);
 313
 314 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 315 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 316                             struct rte_dev_reg_info *regs);
 317 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 318 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 319                                 struct rte_dev_eeprom_info *eeprom);
 320 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 321                                 struct rte_dev_eeprom_info *eeprom);
 322
 323 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 324 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 325                                 struct rte_dev_reg_info *regs);
 326
 327 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 328 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 329 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 330                                             struct timespec *timestamp,
 331                                             uint32_t flags);
 332 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 333                                             struct timespec *timestamp);
 334
 335 /*
 336  * Define VF Stats MACRO for Non "cleared on read" register
 337  */
 338 #define UPDATE_VF_STAT(reg, last, cur)                          \
 339 {                                                               \
 340         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 341         cur += latest - last;                                   \
 342         last = latest;                                          \
 343 }
 344
 345 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 346 {                                                                \
 347         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 348         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 349         u64 latest = ((new_msb << 32) | new_lsb);                \
 350         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 351         last = latest;                                           \
 352 }
 353
 354 #define IXGBE_SET_HWSTRIP(h, q) do{\
 355                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 356                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 357                 (h)->bitmap[idx] |= 1 << bit;\
 358         }while(0)
 359
 360 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 361                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 362                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 363                 (h)->bitmap[idx] &= ~(1 << bit);\
 364         }while(0)
 365
 366 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 367                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 368                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 369                 (r) = (h)->bitmap[idx] >> bit & 1;\
 370         }while(0)
 371
 372 /*
 373  * The set of PCI devices this driver supports
 374  */
 375 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 376
 377 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 378 #include "rte_pci_dev_ids.h"
 379
 380 { .vendor_id = 0, /* sentinel */ },
 381 };
 382
 383
 384 /*
 385  * The set of PCI devices this driver supports (for 82599 VF)
 386  */
 387 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 388
 389 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 390 #include "rte_pci_dev_ids.h"
 391 { .vendor_id = 0, /* sentinel */ },
 392
 393 };
 394
 395 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 396         .dev_configure        = ixgbe_dev_configure,
 397         .dev_start            = ixgbe_dev_start,
 398         .dev_stop             = ixgbe_dev_stop,
 399         .dev_set_link_up    = ixgbe_dev_set_link_up,
 400         .dev_set_link_down  = ixgbe_dev_set_link_down,
 401         .dev_close            = ixgbe_dev_close,
 402         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 403         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 404         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 405         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 406         .link_update          = ixgbe_dev_link_update,
 407         .stats_get            = ixgbe_dev_stats_get,
 408         .xstats_get           = ixgbe_dev_xstats_get,
 409         .stats_reset          = ixgbe_dev_stats_reset,
 410         .xstats_reset         = ixgbe_dev_xstats_reset,
 411         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 412         .dev_infos_get        = ixgbe_dev_info_get,
 413         .mtu_set              = ixgbe_dev_mtu_set,
 414         .vlan_filter_set      = ixgbe_vlan_filter_set,
 415         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 416         .vlan_offload_set     = ixgbe_vlan_offload_set,
 417         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 418         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 419         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 420         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 421         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 422         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 423 #ifdef RTE_NEXT_ABI
 424         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 425         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 426 #endif
 427         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 428         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 429         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 430         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 431         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 432         .dev_led_on           = ixgbe_dev_led_on,
 433         .dev_led_off          = ixgbe_dev_led_off,
 434         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 435         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 436         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 437         .mac_addr_add         = ixgbe_add_rar,
 438         .mac_addr_remove      = ixgbe_remove_rar,
 439         .mac_addr_set         = ixgbe_set_default_mac_addr,
 440         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 441         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 442         .mirror_rule_set      = ixgbe_mirror_rule_set,
 443         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 444         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 445         .set_vf_rx            = ixgbe_set_pool_rx,
 446         .set_vf_tx            = ixgbe_set_pool_tx,
 447         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 448         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 449         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 450         .reta_update          = ixgbe_dev_rss_reta_update,
 451         .reta_query           = ixgbe_dev_rss_reta_query,
 452 #ifdef RTE_NIC_BYPASS
 453         .bypass_init          = ixgbe_bypass_init,
 454         .bypass_state_set     = ixgbe_bypass_state_store,
 455         .bypass_state_show    = ixgbe_bypass_state_show,
 456         .bypass_event_set     = ixgbe_bypass_event_store,
 457         .bypass_event_show    = ixgbe_bypass_event_show,
 458         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 459         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 460         .bypass_ver_show      = ixgbe_bypass_ver_show,
 461         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 462 #endif /* RTE_NIC_BYPASS */
 463         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 464         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 465         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 466         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 467         .timesync_enable      = ixgbe_timesync_enable,
 468         .timesync_disable     = ixgbe_timesync_disable,
 469         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 470         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 471         .get_reg_length       = ixgbe_get_reg_length,
 472         .get_reg              = ixgbe_get_regs,
 473         .get_eeprom_length    = ixgbe_get_eeprom_length,
 474         .get_eeprom           = ixgbe_get_eeprom,
 475         .set_eeprom           = ixgbe_set_eeprom,
 476 };
 477
 478 /*
 479  * dev_ops for virtual function, bare necessities for basic vf
 480  * operation have been implemented
 481  */
 482 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 483         .dev_configure        = ixgbevf_dev_configure,
 484         .dev_start            = ixgbevf_dev_start,
 485         .dev_stop             = ixgbevf_dev_stop,
 486         .link_update          = ixgbe_dev_link_update,
 487         .stats_get            = ixgbevf_dev_stats_get,
 488         .stats_reset          = ixgbevf_dev_stats_reset,
 489         .dev_close            = ixgbevf_dev_close,
 490         .dev_infos_get        = ixgbevf_dev_info_get,
 491         .mtu_set              = ixgbevf_dev_set_mtu,
 492         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 493         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 494         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 495         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 496         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 497         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 498         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 499         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 500 #ifdef RTE_NEXT_ABI
 501         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 502         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 503 #endif
 504         .mac_addr_add         = ixgbevf_add_mac_addr,
 505         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 506         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 507         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 508         .get_reg_length       = ixgbevf_get_reg_length,
 509         .get_reg              = ixgbevf_get_regs,
 510 };
 511
 512 /* store statistics names and its offset in stats structure */
 513 struct rte_ixgbe_xstats_name_off {
 514         char name[RTE_ETH_XSTATS_NAME_SIZE];
 515         unsigned offset;
 516 };
 517
 518 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 519         {"rx_illegal_byte_err", offsetof(struct ixgbe_hw_stats, errbc)},
 520         {"rx_len_err", offsetof(struct ixgbe_hw_stats, rlec)},
 521         {"rx_undersize_count", offsetof(struct ixgbe_hw_stats, ruc)},
 522         {"rx_oversize_count", offsetof(struct ixgbe_hw_stats, roc)},
 523         {"rx_fragment_count", offsetof(struct ixgbe_hw_stats, rfc)},
 524         {"rx_jabber_count", offsetof(struct ixgbe_hw_stats, rjc)},
 525         {"l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 526         {"mac_local_fault", offsetof(struct ixgbe_hw_stats, mlfc)},
 527         {"mac_remote_fault", offsetof(struct ixgbe_hw_stats, mrfc)},
 528         {"mac_short_pkt_discard", offsetof(struct ixgbe_hw_stats, mspdc)},
 529         {"fccrc_error", offsetof(struct ixgbe_hw_stats, fccrc)},
 530         {"fcoe_drop", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 531         {"fc_last_error", offsetof(struct ixgbe_hw_stats, fclast)},
 532         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 533         {"rx_phy_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 534         {"mgmt_pkts_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 535         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 536         {"fdir_match", offsetof(struct ixgbe_hw_stats, fdirmatch)},
 537         {"fdir_miss", offsetof(struct ixgbe_hw_stats, fdirmiss)},
 538         {"tx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxontxc)},
 539         {"rx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 540         {"tx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 541         {"rx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 542 };
 543
 544 #define IXGBE_NB_XSTATS (sizeof(rte_ixgbe_stats_strings) /      \
 545                 sizeof(rte_ixgbe_stats_strings[0]))
 546
 547 /**
 548  * Atomically reads the link status information from global
 549  * structure rte_eth_dev.
 550  *
 551  * @param dev
 552  *   - Pointer to the structure rte_eth_dev to read from.
 553  *   - Pointer to the buffer to be saved with the link status.
 554  *
 555  * @return
 556  *   - On success, zero.
 557  *   - On failure, negative value.
 558  */
 559 static inline int
 560 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 561                                 struct rte_eth_link *link)
 562 {
 563         struct rte_eth_link *dst = link;
 564         struct rte_eth_link *src = &(dev->data->dev_link);
 565
 566         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 567                                         *(uint64_t *)src) == 0)
 568                 return -1;
 569
 570         return 0;
 571 }
 572
 573 /**
 574  * Atomically writes the link status information into global
 575  * structure rte_eth_dev.
 576  *
 577  * @param dev
 578  *   - Pointer to the structure rte_eth_dev to read from.
 579  *   - Pointer to the buffer to be saved with the link status.
 580  *
 581  * @return
 582  *   - On success, zero.
 583  *   - On failure, negative value.
 584  */
 585 static inline int
 586 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 587                                 struct rte_eth_link *link)
 588 {
 589         struct rte_eth_link *dst = &(dev->data->dev_link);
 590         struct rte_eth_link *src = link;
 591
 592         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 593                                         *(uint64_t *)src) == 0)
 594                 return -1;
 595
 596         return 0;
 597 }
 598
 599 /*
 600  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 601  */
 602 static inline int
 603 ixgbe_is_sfp(struct ixgbe_hw *hw)
 604 {
 605         switch (hw->phy.type) {
 606         case ixgbe_phy_sfp_avago:
 607         case ixgbe_phy_sfp_ftl:
 608         case ixgbe_phy_sfp_intel:
 609         case ixgbe_phy_sfp_unknown:
 610         case ixgbe_phy_sfp_passive_tyco:
 611         case ixgbe_phy_sfp_passive_unknown:
 612                 return 1;
 613         default:
 614                 return 0;
 615         }
 616 }
 617
 618 static inline int32_t
 619 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 620 {
 621         uint32_t ctrl_ext;
 622         int32_t status;
 623
 624         status = ixgbe_reset_hw(hw);
 625
 626         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 627         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 628         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 629         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 630         IXGBE_WRITE_FLUSH(hw);
 631
 632         return status;
 633 }
 634
 635 static inline void
 636 ixgbe_enable_intr(struct rte_eth_dev *dev)
 637 {
 638         struct ixgbe_interrupt *intr =
 639                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 640         struct ixgbe_hw *hw =
 641                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 642
 643         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 644         IXGBE_WRITE_FLUSH(hw);
 645 }
 646
 647 /*
 648  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 649  */
 650 static void
 651 ixgbe_disable_intr(struct ixgbe_hw *hw)
 652 {
 653         PMD_INIT_FUNC_TRACE();
 654
 655         if (hw->mac.type == ixgbe_mac_82598EB) {
 656                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 657         } else {
 658                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 659                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 660                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 661         }
 662         IXGBE_WRITE_FLUSH(hw);
 663 }
 664
 665 /*
 666  * This function resets queue statistics mapping registers.
 667  * From Niantic datasheet, Initialization of Statistics section:
 668  * "...if software requires the queue counters, the RQSMR and TQSM registers
 669  * must be re-programmed following a device reset.
 670  */
 671 static void
 672 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 673 {
 674         uint32_t i;
 675
 676         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 677                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 678                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 679         }
 680 }
 681
 682
 683 static int
 684 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 685                                   uint16_t queue_id,
 686                                   uint8_t stat_idx,
 687                                   uint8_t is_rx)
 688 {
 689 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 690 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 691 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 692
 693         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 694         struct ixgbe_stat_mapping_registers *stat_mappings =
 695                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 696         uint32_t qsmr_mask = 0;
 697         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 698         uint32_t q_map;
 699         uint8_t n, offset;
 700
 701         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 702                 (hw->mac.type != ixgbe_mac_X540) &&
 703                 (hw->mac.type != ixgbe_mac_X550) &&
 704                 (hw->mac.type != ixgbe_mac_X550EM_x))
 705                 return -ENOSYS;
 706
 707         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 708                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 709                      queue_id, stat_idx);
 710
 711         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 712         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 713                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 714                 return -EIO;
 715         }
 716         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 717
 718         /* Now clear any previous stat_idx set */
 719         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 720         if (!is_rx)
 721                 stat_mappings->tqsm[n] &= ~clearing_mask;
 722         else
 723                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 724
 725         q_map = (uint32_t)stat_idx;
 726         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 727         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 728         if (!is_rx)
 729                 stat_mappings->tqsm[n] |= qsmr_mask;
 730         else
 731                 stat_mappings->rqsmr[n] |= qsmr_mask;
 732
 733         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 734                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 735                      queue_id, stat_idx);
 736         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 737                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 738
 739         /* Now write the mapping in the appropriate register */
 740         if (is_rx) {
 741                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 742                              stat_mappings->rqsmr[n], n);
 743                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 744         }
 745         else {
 746                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 747                              stat_mappings->tqsm[n], n);
 748                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 749         }
 750         return 0;
 751 }
 752
 753 static void
 754 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 755 {
 756         struct ixgbe_stat_mapping_registers *stat_mappings =
 757                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 758         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 759         int i;
 760
 761         /* write whatever was in stat mapping table to the NIC */
 762         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 763                 /* rx */
 764                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 765
 766                 /* tx */
 767                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 768         }
 769 }
 770
 771 static void
 772 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 773 {
 774         uint8_t i;
 775         struct ixgbe_dcb_tc_config *tc;
 776         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 777
 778         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 779         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 780         for (i = 0; i < dcb_max_tc; i++) {
 781                 tc = &dcb_config->tc_config[i];
 782                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 783                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 784                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 785                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 786                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 787                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 788                 tc->pfc = ixgbe_dcb_pfc_disabled;
 789         }
 790
 791         /* Initialize default user to priority mapping, UPx->TC0 */
 792         tc = &dcb_config->tc_config[0];
 793         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 794         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 795         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 796                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 797                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 798         }
 799         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 800         dcb_config->pfc_mode_enable = false;
 801         dcb_config->vt_mode = true;
 802         dcb_config->round_robin_enable = false;
 803         /* support all DCB capabilities in 82599 */
 804         dcb_config->support.capabilities = 0xFF;
 805
 806         /*we only support 4 Tcs for X540, X550 */
 807         if (hw->mac.type == ixgbe_mac_X540 ||
 808                 hw->mac.type == ixgbe_mac_X550 ||
 809                 hw->mac.type == ixgbe_mac_X550EM_x) {
 810                 dcb_config->num_tcs.pg_tcs = 4;
 811                 dcb_config->num_tcs.pfc_tcs = 4;
 812         }
 813 }
 814
 815 /*
 816  * Ensure that all locks are released before first NVM or PHY access
 817  */
 818 static void
 819 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 820 {
 821         uint16_t mask;
 822
 823         /*
 824          * Phy lock should not fail in this early stage. If this is the case,
 825          * it is due to an improper exit of the application.
 826          * So force the release of the faulty lock. Release of common lock
 827          * is done automatically by swfw_sync function.
 828          */
 829         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 830         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 831                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 832         }
 833         ixgbe_release_swfw_semaphore(hw, mask);
 834
 835         /*
 836          * These ones are more tricky since they are common to all ports; but
 837          * swfw_sync retries last long enough (1s) to be almost sure that if
 838          * lock can not be taken it is due to an improper lock of the
 839          * semaphore.
 840          */
 841         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 842         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 843                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 844         }
 845         ixgbe_release_swfw_semaphore(hw, mask);
 846 }
 847
 848 /*
 849  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 850  * It returns 0 on success.
 851  */
 852 static int
 853 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 854 {
 855         struct rte_pci_device *pci_dev;
 856         struct ixgbe_hw *hw =
 857                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 858         struct ixgbe_vfta * shadow_vfta =
 859                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 860         struct ixgbe_hwstrip *hwstrip =
 861                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 862         struct ixgbe_dcb_config *dcb_config =
 863                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 864         struct ixgbe_filter_info *filter_info =
 865                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 866         uint32_t ctrl_ext;
 867         uint16_t csum;
 868         int diag, i;
 869
 870         PMD_INIT_FUNC_TRACE();
 871
 872         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 873         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 874         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 875
 876         /*
 877          * For secondary processes, we don't initialise any further as primary
 878          * has already done this work. Only check we don't need a different
 879          * RX and TX function.
 880          */
 881         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 882                 struct ixgbe_tx_queue *txq;
 883                 /* TX queue function in primary, set by last queue initialized
 884                  * Tx queue may not initialized by primary process */
 885                 if (eth_dev->data->tx_queues) {
 886                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 887                         ixgbe_set_tx_function(eth_dev, txq);
 888                 } else {
 889                         /* Use default TX function if we get here */
 890                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 891                                              "Using default TX function.");
 892                 }
 893
 894                 ixgbe_set_rx_function(eth_dev);
 895
 896                 return 0;
 897         }
 898         pci_dev = eth_dev->pci_dev;
 899
 900         /* Vendor and Device ID need to be set before init of shared code */
 901         hw->device_id = pci_dev->id.device_id;
 902         hw->vendor_id = pci_dev->id.vendor_id;
 903         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 904         hw->allow_unsupported_sfp = 1;
 905
 906         /* Initialize the shared code (base driver) */
 907 #ifdef RTE_NIC_BYPASS
 908         diag = ixgbe_bypass_init_shared_code(hw);
 909 #else
 910         diag = ixgbe_init_shared_code(hw);
 911 #endif /* RTE_NIC_BYPASS */
 912
 913         if (diag != IXGBE_SUCCESS) {
 914                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 915                 return -EIO;
 916         }
 917
 918         /* pick up the PCI bus settings for reporting later */
 919         ixgbe_get_bus_info(hw);
 920
 921         /* Unlock any pending hardware semaphore */
 922         ixgbe_swfw_lock_reset(hw);
 923
 924         /* Initialize DCB configuration*/
 925         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 926         ixgbe_dcb_init(hw,dcb_config);
 927         /* Get Hardware Flow Control setting */
 928         hw->fc.requested_mode = ixgbe_fc_full;
 929         hw->fc.current_mode = ixgbe_fc_full;
 930         hw->fc.pause_time = IXGBE_FC_PAUSE;
 931         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 932                 hw->fc.low_water[i] = IXGBE_FC_LO;
 933                 hw->fc.high_water[i] = IXGBE_FC_HI;
 934         }
 935         hw->fc.send_xon = 1;
 936
 937         /* Make sure we have a good EEPROM before we read from it */
 938         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 939         if (diag != IXGBE_SUCCESS) {
 940                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 941                 return -EIO;
 942         }
 943
 944 #ifdef RTE_NIC_BYPASS
 945         diag = ixgbe_bypass_init_hw(hw);
 946 #else
 947         diag = ixgbe_init_hw(hw);
 948 #endif /* RTE_NIC_BYPASS */
 949
 950         /*
 951          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 952          * is called too soon after the kernel driver unbinding/binding occurs.
 953          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 954          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 955          * also called. See ixgbe_identify_phy_82599(). The reason for the
 956          * failure is not known, and only occuts when virtualisation features
 957          * are disabled in the bios. A delay of 100ms  was found to be enough by
 958          * trial-and-error, and is doubled to be safe.
 959          */
 960         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 961                 rte_delay_ms(200);
 962                 diag = ixgbe_init_hw(hw);
 963         }
 964
 965         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 966                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 967                     "LOM.  Please be aware there may be issues associated "
 968                     "with your hardware.");
 969                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 970                     "please contact your Intel or hardware representative "
 971                     "who provided you with this hardware.");
 972         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 973                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 974         if (diag) {
 975                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 976                 return -EIO;
 977         }
 978
 979         /* Reset the hw statistics */
 980         ixgbe_dev_stats_reset(eth_dev);
 981
 982         /* disable interrupt */
 983         ixgbe_disable_intr(hw);
 984
 985         /* reset mappings for queue statistics hw counters*/
 986         ixgbe_reset_qstat_mappings(hw);
 987
 988         /* Allocate memory for storing MAC addresses */
 989         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 990                         hw->mac.num_rar_entries, 0);
 991         if (eth_dev->data->mac_addrs == NULL) {
 992                 PMD_INIT_LOG(ERR,
 993                         "Failed to allocate %u bytes needed to store "
 994                         "MAC addresses",
 995                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 996                 return -ENOMEM;
 997         }
 998         /* Copy the permanent MAC address */
 999         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1000                         &eth_dev->data->mac_addrs[0]);
1001
1002         /* Allocate memory for storing hash filter MAC addresses */
1003         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1004                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1005         if (eth_dev->data->hash_mac_addrs == NULL) {
1006                 PMD_INIT_LOG(ERR,
1007                         "Failed to allocate %d bytes needed to store MAC addresses",
1008                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1009                 return -ENOMEM;
1010         }
1011
1012         /* initialize the vfta */
1013         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1014
1015         /* initialize the hw strip bitmap*/
1016         memset(hwstrip, 0, sizeof(*hwstrip));
1017
1018         /* initialize PF if max_vfs not zero */
1019         ixgbe_pf_host_init(eth_dev);
1020
1021         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1022         /* let hardware know driver is loaded */
1023         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1024         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1025         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1026         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1027         IXGBE_WRITE_FLUSH(hw);
1028
1029         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1030                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1031                              (int) hw->mac.type, (int) hw->phy.type,
1032                              (int) hw->phy.sfp_type);
1033         else
1034                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1035                              (int) hw->mac.type, (int) hw->phy.type);
1036
1037         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1038                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1039                         pci_dev->id.device_id);
1040
1041         /* enable support intr */
1042         ixgbe_enable_intr(eth_dev);
1043
1044         /* initialize 5tuple filter list */
1045         TAILQ_INIT(&filter_info->fivetuple_list);
1046         memset(filter_info->fivetuple_mask, 0,
1047                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1048
1049         return 0;
1050 }
1051
1052 static int
1053 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1054 {
1055         struct rte_pci_device *pci_dev;
1056         struct ixgbe_hw *hw;
1057
1058         PMD_INIT_FUNC_TRACE();
1059
1060         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1061                 return -EPERM;
1062
1063         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1064         pci_dev = eth_dev->pci_dev;
1065
1066         if (hw->adapter_stopped == 0)
1067                 ixgbe_dev_close(eth_dev);
1068
1069         eth_dev->dev_ops = NULL;
1070         eth_dev->rx_pkt_burst = NULL;
1071         eth_dev->tx_pkt_burst = NULL;
1072
1073         /* Unlock any pending hardware semaphore */
1074         ixgbe_swfw_lock_reset(hw);
1075
1076         /* disable uio intr before callback unregister */
1077         rte_intr_disable(&(pci_dev->intr_handle));
1078         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1079                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1080
1081         /* uninitialize PF if max_vfs not zero */
1082         ixgbe_pf_host_uninit(eth_dev);
1083
1084         rte_free(eth_dev->data->mac_addrs);
1085         eth_dev->data->mac_addrs = NULL;
1086
1087         rte_free(eth_dev->data->hash_mac_addrs);
1088         eth_dev->data->hash_mac_addrs = NULL;
1089
1090         return 0;
1091 }
1092
1093 /*
1094  * Negotiate mailbox API version with the PF.
1095  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1096  * Then we try to negotiate starting with the most recent one.
1097  * If all negotiation attempts fail, then we will proceed with
1098  * the default one (ixgbe_mbox_api_10).
1099  */
1100 static void
1101 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1102 {
1103         int32_t i;
1104
1105         /* start with highest supported, proceed down */
1106         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1107                 ixgbe_mbox_api_11,
1108                 ixgbe_mbox_api_10,
1109         };
1110
1111         for (i = 0;
1112                         i != RTE_DIM(sup_ver) &&
1113                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1114                         i++)
1115                 ;
1116 }
1117
1118 static void
1119 generate_random_mac_addr(struct ether_addr *mac_addr)
1120 {
1121         uint64_t random;
1122
1123         /* Set Organizationally Unique Identifier (OUI) prefix. */
1124         mac_addr->addr_bytes[0] = 0x00;
1125         mac_addr->addr_bytes[1] = 0x09;
1126         mac_addr->addr_bytes[2] = 0xC0;
1127         /* Force indication of locally assigned MAC address. */
1128         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1129         /* Generate the last 3 bytes of the MAC address with a random number. */
1130         random = rte_rand();
1131         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1132 }
1133
1134 /*
1135  * Virtual Function device init
1136  */
1137 static int
1138 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1139 {
1140         int diag;
1141         uint32_t tc, tcs;
1142         struct rte_pci_device *pci_dev;
1143         struct ixgbe_hw *hw =
1144                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1145         struct ixgbe_vfta * shadow_vfta =
1146                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1147         struct ixgbe_hwstrip *hwstrip =
1148                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1149         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1150
1151         PMD_INIT_FUNC_TRACE();
1152
1153         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1154         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1155         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1156
1157         /* for secondary processes, we don't initialise any further as primary
1158          * has already done this work. Only check we don't need a different
1159          * RX function */
1160         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1161                 if (eth_dev->data->scattered_rx)
1162                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1163                 return 0;
1164         }
1165
1166         pci_dev = eth_dev->pci_dev;
1167
1168         hw->device_id = pci_dev->id.device_id;
1169         hw->vendor_id = pci_dev->id.vendor_id;
1170         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1171
1172         /* initialize the vfta */
1173         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1174
1175         /* initialize the hw strip bitmap*/
1176         memset(hwstrip, 0, sizeof(*hwstrip));
1177
1178         /* Initialize the shared code (base driver) */
1179         diag = ixgbe_init_shared_code(hw);
1180         if (diag != IXGBE_SUCCESS) {
1181                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1182                 return -EIO;
1183         }
1184
1185         /* init_mailbox_params */
1186         hw->mbx.ops.init_params(hw);
1187
1188         /* Reset the hw statistics */
1189         ixgbevf_dev_stats_reset(eth_dev);
1190
1191         /* Disable the interrupts for VF */
1192         ixgbevf_intr_disable(hw);
1193
1194         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1195         diag = hw->mac.ops.reset_hw(hw);
1196
1197         /*
1198          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1199          * the underlying PF driver has not assigned a MAC address to the VF.
1200          * In this case, assign a random MAC address.
1201          */
1202         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1203                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1204                 return (diag);
1205         }
1206
1207         /* negotiate mailbox API version to use with the PF. */
1208         ixgbevf_negotiate_api(hw);
1209
1210         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1211         ixgbevf_get_queues(hw, &tcs, &tc);
1212
1213         /* Allocate memory for storing MAC addresses */
1214         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1215                         hw->mac.num_rar_entries, 0);
1216         if (eth_dev->data->mac_addrs == NULL) {
1217                 PMD_INIT_LOG(ERR,
1218                         "Failed to allocate %u bytes needed to store "
1219                         "MAC addresses",
1220                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1221                 return -ENOMEM;
1222         }
1223
1224         /* Generate a random MAC address, if none was assigned by PF. */
1225         if (is_zero_ether_addr(perm_addr)) {
1226                 generate_random_mac_addr(perm_addr);
1227                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1228                 if (diag) {
1229                         rte_free(eth_dev->data->mac_addrs);
1230                         eth_dev->data->mac_addrs = NULL;
1231                         return diag;
1232                 }
1233                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1234                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1235                              "%02x:%02x:%02x:%02x:%02x:%02x",
1236                              perm_addr->addr_bytes[0],
1237                              perm_addr->addr_bytes[1],
1238                              perm_addr->addr_bytes[2],
1239                              perm_addr->addr_bytes[3],
1240                              perm_addr->addr_bytes[4],
1241                              perm_addr->addr_bytes[5]);
1242         }
1243
1244         /* Copy the permanent MAC address */
1245         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1246
1247         /* reset the hardware with the new settings */
1248         diag = hw->mac.ops.start_hw(hw);
1249         switch (diag) {
1250                 case  0:
1251                         break;
1252
1253                 default:
1254                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1255                         return (-EIO);
1256         }
1257
1258         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1259                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1260                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1261
1262         return 0;
1263 }
1264
1265 /* Virtual Function device uninit */
1266
1267 static int
1268 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1269 {
1270         struct ixgbe_hw *hw;
1271         unsigned i;
1272
1273         PMD_INIT_FUNC_TRACE();
1274
1275         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1276                 return -EPERM;
1277
1278         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1279
1280         if (hw->adapter_stopped == 0)
1281                 ixgbevf_dev_close(eth_dev);
1282
1283         eth_dev->dev_ops = NULL;
1284         eth_dev->rx_pkt_burst = NULL;
1285         eth_dev->tx_pkt_burst = NULL;
1286
1287         /* Disable the interrupts for VF */
1288         ixgbevf_intr_disable(hw);
1289
1290         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1291                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1292                 eth_dev->data->rx_queues[i] = NULL;
1293         }
1294         eth_dev->data->nb_rx_queues = 0;
1295
1296         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1297                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1298                 eth_dev->data->tx_queues[i] = NULL;
1299         }
1300         eth_dev->data->nb_tx_queues = 0;
1301
1302         rte_free(eth_dev->data->mac_addrs);
1303         eth_dev->data->mac_addrs = NULL;
1304
1305         return 0;
1306 }
1307
1308 static struct eth_driver rte_ixgbe_pmd = {
1309         .pci_drv = {
1310                 .name = "rte_ixgbe_pmd",
1311                 .id_table = pci_id_ixgbe_map,
1312                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1313                         RTE_PCI_DRV_DETACHABLE,
1314         },
1315         .eth_dev_init = eth_ixgbe_dev_init,
1316         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1317         .dev_private_size = sizeof(struct ixgbe_adapter),
1318 };
1319
1320 /*
1321  * virtual function driver struct
1322  */
1323 static struct eth_driver rte_ixgbevf_pmd = {
1324         .pci_drv = {
1325                 .name = "rte_ixgbevf_pmd",
1326                 .id_table = pci_id_ixgbevf_map,
1327                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1328         },
1329         .eth_dev_init = eth_ixgbevf_dev_init,
1330         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1331         .dev_private_size = sizeof(struct ixgbe_adapter),
1332 };
1333
1334 /*
1335  * Driver initialization routine.
1336  * Invoked once at EAL init time.
1337  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1338  */
1339 static int
1340 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1341 {
1342         PMD_INIT_FUNC_TRACE();
1343
1344         rte_eth_driver_register(&rte_ixgbe_pmd);
1345         return 0;
1346 }
1347
1348 /*
1349  * VF Driver initialization routine.
1350  * Invoked one at EAL init time.
1351  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1352  */
1353 static int
1354 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1355 {
1356         PMD_INIT_FUNC_TRACE();
1357
1358         rte_eth_driver_register(&rte_ixgbevf_pmd);
1359         return (0);
1360 }
1361
1362 static int
1363 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1364 {
1365         struct ixgbe_hw *hw =
1366                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1367         struct ixgbe_vfta * shadow_vfta =
1368                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1369         uint32_t vfta;
1370         uint32_t vid_idx;
1371         uint32_t vid_bit;
1372
1373         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1374         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1375         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1376         if (on)
1377                 vfta |= vid_bit;
1378         else
1379                 vfta &= ~vid_bit;
1380         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1381
1382         /* update local VFTA copy */
1383         shadow_vfta->vfta[vid_idx] = vfta;
1384
1385         return 0;
1386 }
1387
1388 static void
1389 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1390 {
1391         if (on)
1392                 ixgbe_vlan_hw_strip_enable(dev, queue);
1393         else
1394                 ixgbe_vlan_hw_strip_disable(dev, queue);
1395 }
1396
1397 static void
1398 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1399 {
1400         struct ixgbe_hw *hw =
1401                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1402
1403         /* Only the high 16-bits is valid */
1404         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1405 }
1406
1407 void
1408 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1409 {
1410         struct ixgbe_hw *hw =
1411                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1412         uint32_t vlnctrl;
1413
1414         PMD_INIT_FUNC_TRACE();
1415
1416         /* Filter Table Disable */
1417         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1418         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1419
1420         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1421 }
1422
1423 void
1424 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1425 {
1426         struct ixgbe_hw *hw =
1427                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428         struct ixgbe_vfta * shadow_vfta =
1429                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1430         uint32_t vlnctrl;
1431         uint16_t i;
1432
1433         PMD_INIT_FUNC_TRACE();
1434
1435         /* Filter Table Enable */
1436         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1437         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1438         vlnctrl |= IXGBE_VLNCTRL_VFE;
1439
1440         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1441
1442         /* write whatever is in local vfta copy */
1443         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1444                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1445 }
1446
1447 static void
1448 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1449 {
1450         struct ixgbe_hwstrip *hwstrip =
1451                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1452
1453         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1454                 return;
1455
1456         if (on)
1457                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1458         else
1459                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1460 }
1461
1462 static void
1463 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1464 {
1465         struct ixgbe_hw *hw =
1466                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1467         uint32_t ctrl;
1468
1469         PMD_INIT_FUNC_TRACE();
1470
1471         if (hw->mac.type == ixgbe_mac_82598EB) {
1472                 /* No queue level support */
1473                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1474                 return;
1475         }
1476         else {
1477                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1478                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1479                 ctrl &= ~IXGBE_RXDCTL_VME;
1480                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1481         }
1482         /* record those setting for HW strip per queue */
1483         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1484 }
1485
1486 static void
1487 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1488 {
1489         struct ixgbe_hw *hw =
1490                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1491         uint32_t ctrl;
1492
1493         PMD_INIT_FUNC_TRACE();
1494
1495         if (hw->mac.type == ixgbe_mac_82598EB) {
1496                 /* No queue level supported */
1497                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1498                 return;
1499         }
1500         else {
1501                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1502                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1503                 ctrl |= IXGBE_RXDCTL_VME;
1504                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1505         }
1506         /* record those setting for HW strip per queue */
1507         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1508 }
1509
1510 void
1511 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1512 {
1513         struct ixgbe_hw *hw =
1514                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1515         uint32_t ctrl;
1516         uint16_t i;
1517
1518         PMD_INIT_FUNC_TRACE();
1519
1520         if (hw->mac.type == ixgbe_mac_82598EB) {
1521                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1522                 ctrl &= ~IXGBE_VLNCTRL_VME;
1523                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1524         }
1525         else {
1526                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1527                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1528                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1529                         ctrl &= ~IXGBE_RXDCTL_VME;
1530                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1531
1532                         /* record those setting for HW strip per queue */
1533                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1534                 }
1535         }
1536 }
1537
1538 void
1539 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1540 {
1541         struct ixgbe_hw *hw =
1542                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1543         uint32_t ctrl;
1544         uint16_t i;
1545
1546         PMD_INIT_FUNC_TRACE();
1547
1548         if (hw->mac.type == ixgbe_mac_82598EB) {
1549                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1550                 ctrl |= IXGBE_VLNCTRL_VME;
1551                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1552         }
1553         else {
1554                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1555                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1556                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1557                         ctrl |= IXGBE_RXDCTL_VME;
1558                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1559
1560                         /* record those setting for HW strip per queue */
1561                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1562                 }
1563         }
1564 }
1565
1566 static void
1567 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1568 {
1569         struct ixgbe_hw *hw =
1570                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1571         uint32_t ctrl;
1572
1573         PMD_INIT_FUNC_TRACE();
1574
1575         /* DMATXCTRL: Geric Double VLAN Disable */
1576         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1577         ctrl &= ~IXGBE_DMATXCTL_GDV;
1578         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1579
1580         /* CTRL_EXT: Global Double VLAN Disable */
1581         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1582         ctrl &= ~IXGBE_EXTENDED_VLAN;
1583         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1584
1585 }
1586
1587 static void
1588 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1589 {
1590         struct ixgbe_hw *hw =
1591                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1592         uint32_t ctrl;
1593
1594         PMD_INIT_FUNC_TRACE();
1595
1596         /* DMATXCTRL: Geric Double VLAN Enable */
1597         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1598         ctrl |= IXGBE_DMATXCTL_GDV;
1599         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1600
1601         /* CTRL_EXT: Global Double VLAN Enable */
1602         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1603         ctrl |= IXGBE_EXTENDED_VLAN;
1604         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1605
1606         /*
1607          * VET EXT field in the EXVET register = 0x8100 by default
1608          * So no need to change. Same to VT field of DMATXCTL register
1609          */
1610 }
1611
1612 static void
1613 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1614 {
1615         if(mask & ETH_VLAN_STRIP_MASK){
1616                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1617                         ixgbe_vlan_hw_strip_enable_all(dev);
1618                 else
1619                         ixgbe_vlan_hw_strip_disable_all(dev);
1620         }
1621
1622         if(mask & ETH_VLAN_FILTER_MASK){
1623                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1624                         ixgbe_vlan_hw_filter_enable(dev);
1625                 else
1626                         ixgbe_vlan_hw_filter_disable(dev);
1627         }
1628
1629         if(mask & ETH_VLAN_EXTEND_MASK){
1630                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1631                         ixgbe_vlan_hw_extend_enable(dev);
1632                 else
1633                         ixgbe_vlan_hw_extend_disable(dev);
1634         }
1635 }
1636
1637 static void
1638 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1639 {
1640         struct ixgbe_hw *hw =
1641                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1642         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1643         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1644         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1645         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1646 }
1647
1648 static int
1649 ixgbe_dev_configure(struct rte_eth_dev *dev)
1650 {
1651         struct ixgbe_interrupt *intr =
1652                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1653         struct ixgbe_adapter *adapter =
1654                 (struct ixgbe_adapter *)dev->data->dev_private;
1655
1656         PMD_INIT_FUNC_TRACE();
1657
1658         /* set flag to update link status after init */
1659         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1660
1661         /*
1662          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1663          * allocation or vector Rx preconditions we will reset it.
1664          */
1665         adapter->rx_bulk_alloc_allowed = true;
1666         adapter->rx_vec_allowed = true;
1667
1668         return 0;
1669 }
1670
1671 /*
1672  * Configure device link speed and setup link.
1673  * It returns 0 on success.
1674  */
1675 static int
1676 ixgbe_dev_start(struct rte_eth_dev *dev)
1677 {
1678         struct ixgbe_hw *hw =
1679                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680         struct ixgbe_vf_info *vfinfo =
1681                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1682         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1683 #ifdef RTE_NEXT_ABI
1684         uint32_t intr_vector = 0;
1685 #endif
1686         int err, link_up = 0, negotiate = 0;
1687         uint32_t speed = 0;
1688         int mask = 0;
1689         int status;
1690         uint16_t vf, idx;
1691
1692         PMD_INIT_FUNC_TRACE();
1693
1694         /* IXGBE devices don't support half duplex */
1695         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1696                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1697                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1698                              dev->data->dev_conf.link_duplex,
1699                              dev->data->port_id);
1700                 return -EINVAL;
1701         }
1702
1703         /* stop adapter */
1704         hw->adapter_stopped = 0;
1705         ixgbe_stop_adapter(hw);
1706
1707         /* reinitialize adapter
1708          * this calls reset and start */
1709         status = ixgbe_pf_reset_hw(hw);
1710         if (status != 0)
1711                 return -1;
1712         hw->mac.ops.start_hw(hw);
1713         hw->mac.get_link_status = true;
1714
1715         /* configure PF module if SRIOV enabled */
1716         ixgbe_pf_host_configure(dev);
1717
1718 #ifdef RTE_NEXT_ABI
1719         /* check and configure queue intr-vector mapping */
1720         if (dev->data->dev_conf.intr_conf.rxq != 0)
1721                 intr_vector = dev->data->nb_rx_queues;
1722
1723         if (rte_intr_efd_enable(intr_handle, intr_vector))
1724                 return -1;
1725
1726         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1727                 intr_handle->intr_vec =
1728                         rte_zmalloc("intr_vec",
1729                                     dev->data->nb_rx_queues * sizeof(int),
1730                                     0);
1731                 if (intr_handle->intr_vec == NULL) {
1732                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1733                                      " intr_vec\n", dev->data->nb_rx_queues);
1734                         return -ENOMEM;
1735                 }
1736         }
1737 #endif
1738
1739         /* confiugre msix for sleep until rx interrupt */
1740         ixgbe_configure_msix(dev);
1741
1742         /* initialize transmission unit */
1743         ixgbe_dev_tx_init(dev);
1744
1745         /* This can fail when allocating mbufs for descriptor rings */
1746         err = ixgbe_dev_rx_init(dev);
1747         if (err) {
1748                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1749                 goto error;
1750         }
1751
1752         err = ixgbe_dev_rxtx_start(dev);
1753         if (err < 0) {
1754                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1755                 goto error;
1756         }
1757
1758         /* Skip link setup if loopback mode is enabled for 82599. */
1759         if (hw->mac.type == ixgbe_mac_82599EB &&
1760                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1761                 goto skip_link_setup;
1762
1763         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1764                 err = hw->mac.ops.setup_sfp(hw);
1765                 if (err)
1766                         goto error;
1767         }
1768
1769         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1770                 /* Turn on the copper */
1771                 ixgbe_set_phy_power(hw, true);
1772         } else {
1773                 /* Turn on the laser */
1774                 ixgbe_enable_tx_laser(hw);
1775         }
1776
1777         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1778         if (err)
1779                 goto error;
1780         dev->data->dev_link.link_status = link_up;
1781
1782         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1783         if (err)
1784                 goto error;
1785
1786         switch(dev->data->dev_conf.link_speed) {
1787         case ETH_LINK_SPEED_AUTONEG:
1788                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1789                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1790                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1791                 break;
1792         case ETH_LINK_SPEED_100:
1793                 /*
1794                  * Invalid for 82598 but error will be detected by
1795                  * ixgbe_setup_link()
1796                  */
1797                 speed = IXGBE_LINK_SPEED_100_FULL;
1798                 break;
1799         case ETH_LINK_SPEED_1000:
1800                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1801                 break;
1802         case ETH_LINK_SPEED_10000:
1803                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1804                 break;
1805         default:
1806                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1807                              dev->data->dev_conf.link_speed,
1808                              dev->data->port_id);
1809                 goto error;
1810         }
1811
1812         err = ixgbe_setup_link(hw, speed, link_up);
1813         if (err)
1814                 goto error;
1815
1816 skip_link_setup:
1817
1818         /* check if lsc interrupt is enabled */
1819         if (dev->data->dev_conf.intr_conf.lsc != 0) {
1820                 if (rte_intr_allow_others(intr_handle)) {
1821                         rte_intr_callback_register(intr_handle,
1822                                                    ixgbe_dev_interrupt_handler,
1823                                                    (void *)dev);
1824                         ixgbe_dev_lsc_interrupt_setup(dev);
1825                 } else
1826                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1827                                      " no intr multiplex\n");
1828         }
1829
1830 #ifdef RTE_NEXT_ABI
1831         /* check if rxq interrupt is enabled */
1832         if (dev->data->dev_conf.intr_conf.rxq != 0)
1833                 ixgbe_dev_rxq_interrupt_setup(dev);
1834 #endif
1835
1836         /* enable uio/vfio intr/eventfd mapping */
1837         rte_intr_enable(intr_handle);
1838
1839         /* resume enabled intr since hw reset */
1840         ixgbe_enable_intr(dev);
1841
1842         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1843                 ETH_VLAN_EXTEND_MASK;
1844         ixgbe_vlan_offload_set(dev, mask);
1845
1846         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1847                 /* Enable vlan filtering for VMDq */
1848                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1849         }
1850
1851         /* Configure DCB hw */
1852         ixgbe_configure_dcb(dev);
1853
1854         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1855                 err = ixgbe_fdir_configure(dev);
1856                 if (err)
1857                         goto error;
1858         }
1859
1860         /* Restore vf rate limit */
1861         if (vfinfo != NULL) {
1862                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1863                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1864                                 if (vfinfo[vf].tx_rate[idx] != 0)
1865                                         ixgbe_set_vf_rate_limit(dev, vf,
1866                                                 vfinfo[vf].tx_rate[idx],
1867                                                 1 << idx);
1868         }
1869
1870         ixgbe_restore_statistics_mapping(dev);
1871
1872         return (0);
1873
1874 error:
1875         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1876         ixgbe_dev_clear_queues(dev);
1877         return -EIO;
1878 }
1879
1880 /*
1881  * Stop device: disable rx and tx functions to allow for reconfiguring.
1882  */
1883 static void
1884 ixgbe_dev_stop(struct rte_eth_dev *dev)
1885 {
1886         struct rte_eth_link link;
1887         struct ixgbe_hw *hw =
1888                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1889         struct ixgbe_vf_info *vfinfo =
1890                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1891         struct ixgbe_filter_info *filter_info =
1892                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1893         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1894         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1895         int vf;
1896
1897         PMD_INIT_FUNC_TRACE();
1898
1899         /* disable interrupts */
1900         ixgbe_disable_intr(hw);
1901
1902         /* disable intr eventfd mapping */
1903         rte_intr_disable(intr_handle);
1904
1905         /* reset the NIC */
1906         ixgbe_pf_reset_hw(hw);
1907         hw->adapter_stopped = 0;
1908
1909         /* stop adapter */
1910         ixgbe_stop_adapter(hw);
1911
1912         for (vf = 0; vfinfo != NULL &&
1913                      vf < dev->pci_dev->max_vfs; vf++)
1914                 vfinfo[vf].clear_to_send = false;
1915
1916         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1917                 /* Turn off the copper */
1918                 ixgbe_set_phy_power(hw, false);
1919         } else {
1920                 /* Turn off the laser */
1921                 ixgbe_disable_tx_laser(hw);
1922         }
1923
1924         ixgbe_dev_clear_queues(dev);
1925
1926         /* Clear stored conf */
1927         dev->data->scattered_rx = 0;
1928         dev->data->lro = 0;
1929
1930         /* Clear recorded link status */
1931         memset(&link, 0, sizeof(link));
1932         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1933
1934         /* Remove all ntuple filters of the device */
1935         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1936              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1937                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1938                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1939                              p_5tuple, entries);
1940                 rte_free(p_5tuple);
1941         }
1942         memset(filter_info->fivetuple_mask, 0,
1943                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1944
1945 #ifdef RTE_NEXT_ABI
1946         /* Clean datapath event and queue/vec mapping */
1947         rte_intr_efd_disable(intr_handle);
1948         if (intr_handle->intr_vec != NULL) {
1949                 rte_free(intr_handle->intr_vec);
1950                 intr_handle->intr_vec = NULL;
1951         }
1952 #endif
1953 }
1954
1955 /*
1956  * Set device link up: enable tx.
1957  */
1958 static int
1959 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1960 {
1961         struct ixgbe_hw *hw =
1962                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1963         if (hw->mac.type == ixgbe_mac_82599EB) {
1964 #ifdef RTE_NIC_BYPASS
1965                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1966                         /* Not suported in bypass mode */
1967                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1968                                      "by device id 0x%x", hw->device_id);
1969                         return -ENOTSUP;
1970                 }
1971 #endif
1972         }
1973
1974         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1975                 /* Turn on the copper */
1976                 ixgbe_set_phy_power(hw, true);
1977         } else {
1978                 /* Turn on the laser */
1979                 ixgbe_enable_tx_laser(hw);
1980         }
1981
1982         return 0;
1983 }
1984
1985 /*
1986  * Set device link down: disable tx.
1987  */
1988 static int
1989 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1990 {
1991         struct ixgbe_hw *hw =
1992                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993         if (hw->mac.type == ixgbe_mac_82599EB) {
1994 #ifdef RTE_NIC_BYPASS
1995                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1996                         /* Not suported in bypass mode */
1997                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1998                                      "by device id 0x%x", hw->device_id);
1999                         return -ENOTSUP;
2000                 }
2001 #endif
2002         }
2003
2004         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2005                 /* Turn off the copper */
2006                 ixgbe_set_phy_power(hw, false);
2007         } else {
2008                 /* Turn off the laser */
2009                 ixgbe_disable_tx_laser(hw);
2010         }
2011
2012         return 0;
2013 }
2014
2015 /*
2016  * Reest and stop device.
2017  */
2018 static void
2019 ixgbe_dev_close(struct rte_eth_dev *dev)
2020 {
2021         struct ixgbe_hw *hw =
2022                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023
2024         PMD_INIT_FUNC_TRACE();
2025
2026         ixgbe_pf_reset_hw(hw);
2027
2028         ixgbe_dev_stop(dev);
2029         hw->adapter_stopped = 1;
2030
2031         ixgbe_dev_free_queues(dev);
2032
2033         ixgbe_disable_pcie_master(hw);
2034
2035         /* reprogram the RAR[0] in case user changed it. */
2036         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2037 }
2038
2039 static void
2040 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2041                                                    *hw_stats, uint64_t *total_missed_rx,
2042                                                    uint64_t *total_qbrc, uint64_t *total_qprc,
2043                                                    uint64_t *total_qprdc)
2044 {
2045         uint32_t bprc, lxon, lxoff, total;
2046         unsigned i;
2047
2048         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2049         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2050         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2051         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2052
2053         for (i = 0; i < 8; i++) {
2054                 uint32_t mp;
2055                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2056                 /* global total per queue */
2057                 hw_stats->mpc[i] += mp;
2058                 /* Running comprehensive total for stats display */
2059                 *total_missed_rx += hw_stats->mpc[i];
2060                 if (hw->mac.type == ixgbe_mac_82598EB)
2061                         hw_stats->rnbc[i] +=
2062                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2063                 hw_stats->pxontxc[i] +=
2064                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2065                 hw_stats->pxonrxc[i] +=
2066                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2067                 hw_stats->pxofftxc[i] +=
2068                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2069                 hw_stats->pxoffrxc[i] +=
2070                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2071                 hw_stats->pxon2offc[i] +=
2072                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2073         }
2074         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2075                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2076                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2077                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2078                 hw_stats->qbrc[i] +=
2079                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2080                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2081                 hw_stats->qbtc[i] +=
2082                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2083                 *total_qprdc += hw_stats->qprdc[i] +=
2084                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2085
2086                 *total_qprc += hw_stats->qprc[i];
2087                 *total_qbrc += hw_stats->qbrc[i];
2088         }
2089         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2090         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2091         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2092
2093         /* Note that gprc counts missed packets */
2094         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2095
2096         if (hw->mac.type != ixgbe_mac_82598EB) {
2097                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2098                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2099                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2100                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2101                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2102                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2103                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2104                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2105         } else {
2106                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2107                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2108                 /* 82598 only has a counter in the high register */
2109                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2110                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2111                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2112         }
2113
2114         /*
2115          * Workaround: mprc hardware is incorrectly counting
2116          * broadcasts, so for now we subtract those.
2117          */
2118         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2119         hw_stats->bprc += bprc;
2120         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2121         if (hw->mac.type == ixgbe_mac_82598EB)
2122                 hw_stats->mprc -= bprc;
2123
2124         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2125         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2126         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2127         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2128         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2129         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2130
2131         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2132         hw_stats->lxontxc += lxon;
2133         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2134         hw_stats->lxofftxc += lxoff;
2135         total = lxon + lxoff;
2136
2137         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2138         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2139         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2140         hw_stats->gptc -= total;
2141         hw_stats->mptc -= total;
2142         hw_stats->ptc64 -= total;
2143         hw_stats->gotc -= total * ETHER_MIN_LEN;
2144
2145         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2146         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2147         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2148         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2149         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2150         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2151         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2152         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2153         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2154         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2155         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2156         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2157         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2158         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2159         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2160         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2161         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2162         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2163         /* Only read FCOE on 82599 */
2164         if (hw->mac.type != ixgbe_mac_82598EB) {
2165                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2166                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2167                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2168                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2169                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2170         }
2171
2172         /* Flow Director Stats registers */
2173         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2174         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2175 }
2176
2177 /*
2178  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2179  */
2180 static void
2181 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2182 {
2183         struct ixgbe_hw *hw =
2184                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185         struct ixgbe_hw_stats *hw_stats =
2186                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2187         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2188         unsigned i;
2189
2190         total_missed_rx = 0;
2191         total_qbrc = 0;
2192         total_qprc = 0;
2193         total_qprdc = 0;
2194
2195         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2196                         &total_qprc, &total_qprdc);
2197
2198         if (stats == NULL)
2199                 return;
2200
2201         /* Fill out the rte_eth_stats statistics structure */
2202         stats->ipackets = total_qprc;
2203         stats->ibytes = total_qbrc;
2204         stats->opackets = hw_stats->gptc;
2205         stats->obytes = hw_stats->gotc;
2206
2207         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2208                 stats->q_ipackets[i] = hw_stats->qprc[i];
2209                 stats->q_opackets[i] = hw_stats->qptc[i];
2210                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2211                 stats->q_obytes[i] = hw_stats->qbtc[i];
2212                 stats->q_errors[i] = hw_stats->qprdc[i];
2213         }
2214
2215         /* Rx Errors */
2216         stats->ierrors  = hw_stats->crcerrs +
2217                           hw_stats->rlec +
2218                           hw_stats->ruc +
2219                           hw_stats->roc +
2220                           total_missed_rx +
2221                           hw_stats->illerrc +
2222                           hw_stats->errbc +
2223                           hw_stats->xec +
2224                           hw_stats->mlfc +
2225                           hw_stats->mrfc +
2226                           hw_stats->rfc +
2227                           hw_stats->rjc +
2228                           hw_stats->fccrc +
2229                           hw_stats->fclast;
2230
2231         /* Tx Errors */
2232         stats->oerrors  = 0;
2233 }
2234
2235 static void
2236 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2237 {
2238         struct ixgbe_hw_stats *stats =
2239                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2240
2241         /* HW registers are cleared on read */
2242         ixgbe_dev_stats_get(dev, NULL);
2243
2244         /* Reset software totals */
2245         memset(stats, 0, sizeof(*stats));
2246 }
2247
2248 static int
2249 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2250                                          unsigned n)
2251 {
2252         struct ixgbe_hw *hw =
2253                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2254         struct ixgbe_hw_stats *hw_stats =
2255                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2256         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2257         unsigned i, count = IXGBE_NB_XSTATS;
2258
2259         if (n < count)
2260                 return count;
2261
2262         total_missed_rx = 0;
2263         total_qbrc = 0;
2264         total_qprc = 0;
2265         total_qprdc = 0;
2266
2267         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2268                                                            &total_qprc, &total_qprdc);
2269
2270         /* If this is a reset xstats is NULL, and we have cleared the
2271          * registers by reading them.
2272          */
2273         if (!xstats)
2274                 return 0;
2275
2276         /* Extended stats */
2277         for (i = 0; i < IXGBE_NB_XSTATS; i++) {
2278                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2279                                 "%s", rte_ixgbe_stats_strings[i].name);
2280                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2281                                                         rte_ixgbe_stats_strings[i].offset);
2282         }
2283
2284         return count;
2285 }
2286
2287 static void
2288 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2289 {
2290         struct ixgbe_hw_stats *stats =
2291                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2292
2293         /* HW registers are cleared on read */
2294         ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2295
2296         /* Reset software totals */
2297         memset(stats, 0, sizeof(*stats));
2298 }
2299
2300 static void
2301 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2302 {
2303         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2304         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2305                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2306
2307         /* Good Rx packet, include VF loopback */
2308         UPDATE_VF_STAT(IXGBE_VFGPRC,
2309             hw_stats->last_vfgprc, hw_stats->vfgprc);
2310
2311         /* Good Rx octets, include VF loopback */
2312         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2313             hw_stats->last_vfgorc, hw_stats->vfgorc);
2314
2315         /* Good Tx packet, include VF loopback */
2316         UPDATE_VF_STAT(IXGBE_VFGPTC,
2317             hw_stats->last_vfgptc, hw_stats->vfgptc);
2318
2319         /* Good Tx octets, include VF loopback */
2320         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2321             hw_stats->last_vfgotc, hw_stats->vfgotc);
2322
2323         /* Rx Multicst Packet */
2324         UPDATE_VF_STAT(IXGBE_VFMPRC,
2325             hw_stats->last_vfmprc, hw_stats->vfmprc);
2326
2327         if (stats == NULL)
2328                 return;
2329
2330         stats->ipackets = hw_stats->vfgprc;
2331         stats->ibytes = hw_stats->vfgorc;
2332         stats->opackets = hw_stats->vfgptc;
2333         stats->obytes = hw_stats->vfgotc;
2334         stats->imcasts = hw_stats->vfmprc;
2335         /* stats->imcasts should be removed as imcasts is deprecated */
2336 }
2337
2338 static void
2339 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2340 {
2341         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2342                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2343
2344         /* Sync HW register to the last stats */
2345         ixgbevf_dev_stats_get(dev, NULL);
2346
2347         /* reset HW current stats*/
2348         hw_stats->vfgprc = 0;
2349         hw_stats->vfgorc = 0;
2350         hw_stats->vfgptc = 0;
2351         hw_stats->vfgotc = 0;
2352         hw_stats->vfmprc = 0;
2353
2354 }
2355
2356 static void
2357 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2358 {
2359         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2360
2361         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2362         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2363         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2364         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2365         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2366         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2367         dev_info->max_vfs = dev->pci_dev->max_vfs;
2368         if (hw->mac.type == ixgbe_mac_82598EB)
2369                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2370         else
2371                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2372         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2373         dev_info->rx_offload_capa =
2374                 DEV_RX_OFFLOAD_VLAN_STRIP |
2375                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2376                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2377                 DEV_RX_OFFLOAD_TCP_CKSUM;
2378
2379         /*
2380          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2381          * mode.
2382          */
2383         if ((hw->mac.type == ixgbe_mac_82599EB ||
2384              hw->mac.type == ixgbe_mac_X540) &&
2385             !RTE_ETH_DEV_SRIOV(dev).active)
2386                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2387
2388         dev_info->tx_offload_capa =
2389                 DEV_TX_OFFLOAD_VLAN_INSERT |
2390                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2391                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2392                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2393                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2394                 DEV_TX_OFFLOAD_TCP_TSO;
2395
2396         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2397                 .rx_thresh = {
2398                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2399                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2400                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2401                 },
2402                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2403                 .rx_drop_en = 0,
2404         };
2405
2406         dev_info->default_txconf = (struct rte_eth_txconf) {
2407                 .tx_thresh = {
2408                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2409                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2410                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2411                 },
2412                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2413                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2414                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2415                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2416         };
2417         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2418         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2419         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2420 }
2421
2422 static void
2423 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2424                      struct rte_eth_dev_info *dev_info)
2425 {
2426         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427
2428         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2429         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2430         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2431         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2432         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2433         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2434         dev_info->max_vfs = dev->pci_dev->max_vfs;
2435         if (hw->mac.type == ixgbe_mac_82598EB)
2436                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2437         else
2438                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2439         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2440                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2441                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2442                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2443         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2444                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2445                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2446                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2447                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2448
2449         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2450                 .rx_thresh = {
2451                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2452                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2453                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2454                 },
2455                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2456                 .rx_drop_en = 0,
2457         };
2458
2459         dev_info->default_txconf = (struct rte_eth_txconf) {
2460                 .tx_thresh = {
2461                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2462                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2463                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2464                 },
2465                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2466                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2467                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2468                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2469         };
2470 }
2471
2472 /* return 0 means link status changed, -1 means not changed */
2473 static int
2474 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2475 {
2476         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477         struct rte_eth_link link, old;
2478         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2479         int link_up;
2480         int diag;
2481
2482         link.link_status = 0;
2483         link.link_speed = 0;
2484         link.link_duplex = 0;
2485         memset(&old, 0, sizeof(old));
2486         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2487
2488         hw->mac.get_link_status = true;
2489
2490         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2491         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2492                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2493         else
2494                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2495
2496         if (diag != 0) {
2497                 link.link_speed = ETH_LINK_SPEED_100;
2498                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2499                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2500                 if (link.link_status == old.link_status)
2501                         return -1;
2502                 return 0;
2503         }
2504
2505         if (link_up == 0) {
2506                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2507                 if (link.link_status == old.link_status)
2508                         return -1;
2509                 return 0;
2510         }
2511         link.link_status = 1;
2512         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2513
2514         switch (link_speed) {
2515         default:
2516         case IXGBE_LINK_SPEED_UNKNOWN:
2517                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2518                 link.link_speed = ETH_LINK_SPEED_100;
2519                 break;
2520
2521         case IXGBE_LINK_SPEED_100_FULL:
2522                 link.link_speed = ETH_LINK_SPEED_100;
2523                 break;
2524
2525         case IXGBE_LINK_SPEED_1GB_FULL:
2526                 link.link_speed = ETH_LINK_SPEED_1000;
2527                 break;
2528
2529         case IXGBE_LINK_SPEED_10GB_FULL:
2530                 link.link_speed = ETH_LINK_SPEED_10000;
2531                 break;
2532         }
2533         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2534
2535         if (link.link_status == old.link_status)
2536                 return -1;
2537
2538         return 0;
2539 }
2540
2541 static void
2542 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2543 {
2544         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2545         uint32_t fctrl;
2546
2547         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2548         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2549         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2550 }
2551
2552 static void
2553 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2554 {
2555         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2556         uint32_t fctrl;
2557
2558         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2559         fctrl &= (~IXGBE_FCTRL_UPE);
2560         if (dev->data->all_multicast == 1)
2561                 fctrl |= IXGBE_FCTRL_MPE;
2562         else
2563                 fctrl &= (~IXGBE_FCTRL_MPE);
2564         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2565 }
2566
2567 static void
2568 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2569 {
2570         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2571         uint32_t fctrl;
2572
2573         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2574         fctrl |= IXGBE_FCTRL_MPE;
2575         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2576 }
2577
2578 static void
2579 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2580 {
2581         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2582         uint32_t fctrl;
2583
2584         if (dev->data->promiscuous == 1)
2585                 return; /* must remain in all_multicast mode */
2586
2587         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2588         fctrl &= (~IXGBE_FCTRL_MPE);
2589         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2590 }
2591
2592 /**
2593  * It clears the interrupt causes and enables the interrupt.
2594  * It will be called once only during nic initialized.
2595  *
2596  * @param dev
2597  *  Pointer to struct rte_eth_dev.
2598  *
2599  * @return
2600  *  - On success, zero.
2601  *  - On failure, a negative value.
2602  */
2603 static int
2604 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2605 {
2606         struct ixgbe_interrupt *intr =
2607                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2608
2609         ixgbe_dev_link_status_print(dev);
2610         intr->mask |= IXGBE_EICR_LSC;
2611
2612         return 0;
2613 }
2614
2615 /**
2616  * It clears the interrupt causes and enables the interrupt.
2617  * It will be called once only during nic initialized.
2618  *
2619  * @param dev
2620  *  Pointer to struct rte_eth_dev.
2621  *
2622  * @return
2623  *  - On success, zero.
2624  *  - On failure, a negative value.
2625  */
2626 #ifdef RTE_NEXT_ABI
2627 static int
2628 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2629 {
2630         struct ixgbe_interrupt *intr =
2631                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2632
2633         intr->mask |= IXGBE_EICR_RTX_QUEUE;
2634
2635         return 0;
2636 }
2637 #endif
2638
2639 /*
2640  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2641  *
2642  * @param dev
2643  *  Pointer to struct rte_eth_dev.
2644  *
2645  * @return
2646  *  - On success, zero.
2647  *  - On failure, a negative value.
2648  */
2649 static int
2650 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2651 {
2652         uint32_t eicr;
2653         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654         struct ixgbe_interrupt *intr =
2655                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2656
2657         /* clear all cause mask */
2658         ixgbe_disable_intr(hw);
2659
2660         /* read-on-clear nic registers here */
2661         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2662         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2663
2664         intr->flags = 0;
2665
2666         /* set flag for async link update */
2667         if (eicr & IXGBE_EICR_LSC)
2668                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2669
2670         if (eicr & IXGBE_EICR_MAILBOX)
2671                 intr->flags |= IXGBE_FLAG_MAILBOX;
2672
2673         return 0;
2674 }
2675
2676 static int
2677 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
2678 {
2679         uint32_t eicr;
2680         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681         struct ixgbe_interrupt *intr =
2682                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2683
2684         /* clear all cause mask */
2685         ixgbevf_intr_disable(hw);
2686
2687         /* read-on-clear nic registers here */
2688         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
2689         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2690
2691         intr->flags = 0;
2692
2693         /* set flag for async link update */
2694         if (eicr & IXGBE_EICR_LSC)
2695                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2696
2697         return 0;
2698 }
2699
2700 /**
2701  * It gets and then prints the link status.
2702  *
2703  * @param dev
2704  *  Pointer to struct rte_eth_dev.
2705  *
2706  * @return
2707  *  - On success, zero.
2708  *  - On failure, a negative value.
2709  */
2710 static void
2711 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2712 {
2713         struct rte_eth_link link;
2714
2715         memset(&link, 0, sizeof(link));
2716         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2717         if (link.link_status) {
2718                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2719                                         (int)(dev->data->port_id),
2720                                         (unsigned)link.link_speed,
2721                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2722                                         "full-duplex" : "half-duplex");
2723         } else {
2724                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2725                                 (int)(dev->data->port_id));
2726         }
2727         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2728                                 dev->pci_dev->addr.domain,
2729                                 dev->pci_dev->addr.bus,
2730                                 dev->pci_dev->addr.devid,
2731                                 dev->pci_dev->addr.function);
2732 }
2733
2734 /*
2735  * It executes link_update after knowing an interrupt occurred.
2736  *
2737  * @param dev
2738  *  Pointer to struct rte_eth_dev.
2739  *
2740  * @return
2741  *  - On success, zero.
2742  *  - On failure, a negative value.
2743  */
2744 static int
2745 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2746 {
2747         struct ixgbe_interrupt *intr =
2748                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2749         int64_t timeout;
2750         struct rte_eth_link link;
2751         int intr_enable_delay = false;
2752
2753         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2754
2755         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2756                 ixgbe_pf_mbx_process(dev);
2757                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2758         }
2759
2760         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2761                 /* get the link status before link update, for predicting later */
2762                 memset(&link, 0, sizeof(link));
2763                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2764
2765                 ixgbe_dev_link_update(dev, 0);
2766
2767                 /* likely to up */
2768                 if (!link.link_status)
2769                         /* handle it 1 sec later, wait it being stable */
2770                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2771                 /* likely to down */
2772                 else
2773                         /* handle it 4 sec later, wait it being stable */
2774                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2775
2776                 ixgbe_dev_link_status_print(dev);
2777
2778                 intr_enable_delay = true;
2779         }
2780
2781         if (intr_enable_delay) {
2782                 if (rte_eal_alarm_set(timeout * 1000,
2783                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2784                         PMD_DRV_LOG(ERR, "Error setting alarm");
2785         } else {
2786                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2787                 ixgbe_enable_intr(dev);
2788                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2789         }
2790
2791
2792         return 0;
2793 }
2794
2795 static int
2796 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
2797 {
2798         struct ixgbe_hw *hw =
2799                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2800
2801         PMD_DRV_LOG(DEBUG, "enable intr immediately");
2802         ixgbevf_intr_enable(hw);
2803         rte_intr_enable(&dev->pci_dev->intr_handle);
2804         return 0;
2805 }
2806
2807 /**
2808  * Interrupt handler which shall be registered for alarm callback for delayed
2809  * handling specific interrupt to wait for the stable nic state. As the
2810  * NIC interrupt state is not stable for ixgbe after link is just down,
2811  * it needs to wait 4 seconds to get the stable status.
2812  *
2813  * @param handle
2814  *  Pointer to interrupt handle.
2815  * @param param
2816  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2817  *
2818  * @return
2819  *  void
2820  */
2821 static void
2822 ixgbe_dev_interrupt_delayed_handler(void *param)
2823 {
2824         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2825         struct ixgbe_interrupt *intr =
2826                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2827         struct ixgbe_hw *hw =
2828                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2829         uint32_t eicr;
2830
2831         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2832         if (eicr & IXGBE_EICR_MAILBOX)
2833                 ixgbe_pf_mbx_process(dev);
2834
2835         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2836                 ixgbe_dev_link_update(dev, 0);
2837                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2838                 ixgbe_dev_link_status_print(dev);
2839                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2840         }
2841
2842         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2843         ixgbe_enable_intr(dev);
2844         rte_intr_enable(&(dev->pci_dev->intr_handle));
2845 }
2846
2847 /**
2848  * Interrupt handler triggered by NIC  for handling
2849  * specific interrupt.
2850  *
2851  * @param handle
2852  *  Pointer to interrupt handle.
2853  * @param param
2854  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2855  *
2856  * @return
2857  *  void
2858  */
2859 static void
2860 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2861                             void *param)
2862 {
2863         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2864
2865         ixgbe_dev_interrupt_get_status(dev);
2866         ixgbe_dev_interrupt_action(dev);
2867 }
2868
2869 static void
2870 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2871                               void *param)
2872 {
2873         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2874
2875         ixgbevf_dev_interrupt_get_status(dev);
2876         ixgbevf_dev_interrupt_action(dev);
2877 }
2878
2879 static int
2880 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2881 {
2882         struct ixgbe_hw *hw;
2883
2884         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2885         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2886 }
2887
2888 static int
2889 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2890 {
2891         struct ixgbe_hw *hw;
2892
2893         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2894         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2895 }
2896
2897 static int
2898 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2899 {
2900         struct ixgbe_hw *hw;
2901         uint32_t mflcn_reg;
2902         uint32_t fccfg_reg;
2903         int rx_pause;
2904         int tx_pause;
2905
2906         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2907
2908         fc_conf->pause_time = hw->fc.pause_time;
2909         fc_conf->high_water = hw->fc.high_water[0];
2910         fc_conf->low_water = hw->fc.low_water[0];
2911         fc_conf->send_xon = hw->fc.send_xon;
2912         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2913
2914         /*
2915          * Return rx_pause status according to actual setting of
2916          * MFLCN register.
2917          */
2918         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2919         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2920                 rx_pause = 1;
2921         else
2922                 rx_pause = 0;
2923
2924         /*
2925          * Return tx_pause status according to actual setting of
2926          * FCCFG register.
2927          */
2928         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2929         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2930                 tx_pause = 1;
2931         else
2932                 tx_pause = 0;
2933
2934         if (rx_pause && tx_pause)
2935                 fc_conf->mode = RTE_FC_FULL;
2936         else if (rx_pause)
2937                 fc_conf->mode = RTE_FC_RX_PAUSE;
2938         else if (tx_pause)
2939                 fc_conf->mode = RTE_FC_TX_PAUSE;
2940         else
2941                 fc_conf->mode = RTE_FC_NONE;
2942
2943         return 0;
2944 }
2945
2946 static int
2947 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2948 {
2949         struct ixgbe_hw *hw;
2950         int err;
2951         uint32_t rx_buf_size;
2952         uint32_t max_high_water;
2953         uint32_t mflcn;
2954         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2955                 ixgbe_fc_none,
2956                 ixgbe_fc_rx_pause,
2957                 ixgbe_fc_tx_pause,
2958                 ixgbe_fc_full
2959         };
2960
2961         PMD_INIT_FUNC_TRACE();
2962
2963         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2965         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2966
2967         /*
2968          * At least reserve one Ethernet frame for watermark
2969          * high_water/low_water in kilo bytes for ixgbe
2970          */
2971         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2972         if ((fc_conf->high_water > max_high_water) ||
2973                 (fc_conf->high_water < fc_conf->low_water)) {
2974                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2975                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2976                 return (-EINVAL);
2977         }
2978
2979         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2980         hw->fc.pause_time     = fc_conf->pause_time;
2981         hw->fc.high_water[0]  = fc_conf->high_water;
2982         hw->fc.low_water[0]   = fc_conf->low_water;
2983         hw->fc.send_xon       = fc_conf->send_xon;
2984         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2985
2986         err = ixgbe_fc_enable(hw);
2987
2988         /* Not negotiated is not an error case */
2989         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2990
2991                 /* check if we want to forward MAC frames - driver doesn't have native
2992                  * capability to do that, so we'll write the registers ourselves */
2993
2994                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2995
2996                 /* set or clear MFLCN.PMCF bit depending on configuration */
2997                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2998                         mflcn |= IXGBE_MFLCN_PMCF;
2999                 else
3000                         mflcn &= ~IXGBE_MFLCN_PMCF;
3001
3002                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3003                 IXGBE_WRITE_FLUSH(hw);
3004
3005                 return 0;
3006         }
3007
3008         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3009         return -EIO;
3010 }
3011
3012 /**
3013  *  ixgbe_pfc_enable_generic - Enable flow control
3014  *  @hw: pointer to hardware structure
3015  *  @tc_num: traffic class number
3016  *  Enable flow control according to the current settings.
3017  */
3018 static int
3019 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3020 {
3021         int ret_val = 0;
3022         uint32_t mflcn_reg, fccfg_reg;
3023         uint32_t reg;
3024         uint32_t fcrtl, fcrth;
3025         uint8_t i;
3026         uint8_t nb_rx_en;
3027
3028         /* Validate the water mark configuration */
3029         if (!hw->fc.pause_time) {
3030                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3031                 goto out;
3032         }
3033
3034         /* Low water mark of zero causes XOFF floods */
3035         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3036                  /* High/Low water can not be 0 */
3037                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3038                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3039                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3040                         goto out;
3041                 }
3042
3043                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3044                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3045                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3046                         goto out;
3047                 }
3048         }
3049         /* Negotiate the fc mode to use */
3050         ixgbe_fc_autoneg(hw);
3051
3052         /* Disable any previous flow control settings */
3053         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3054         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3055
3056         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3057         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3058
3059         switch (hw->fc.current_mode) {
3060         case ixgbe_fc_none:
3061                 /*
3062                  * If the count of enabled RX Priority Flow control >1,
3063                  * and the TX pause can not be disabled
3064                  */
3065                 nb_rx_en = 0;
3066                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3067                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3068                         if (reg & IXGBE_FCRTH_FCEN)
3069                                 nb_rx_en++;
3070                 }
3071                 if (nb_rx_en > 1)
3072                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3073                 break;
3074         case ixgbe_fc_rx_pause:
3075                 /*
3076                  * Rx Flow control is enabled and Tx Flow control is
3077                  * disabled by software override. Since there really
3078                  * isn't a way to advertise that we are capable of RX
3079                  * Pause ONLY, we will advertise that we support both
3080                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3081                  * disable the adapter's ability to send PAUSE frames.
3082                  */
3083                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3084                 /*
3085                  * If the count of enabled RX Priority Flow control >1,
3086                  * and the TX pause can not be disabled
3087                  */
3088                 nb_rx_en = 0;
3089                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3090                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3091                         if (reg & IXGBE_FCRTH_FCEN)
3092                                 nb_rx_en++;
3093                 }
3094                 if (nb_rx_en > 1)
3095                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3096                 break;
3097         case ixgbe_fc_tx_pause:
3098                 /*
3099                  * Tx Flow control is enabled, and Rx Flow control is
3100                  * disabled by software override.
3101                  */
3102                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3103                 break;
3104         case ixgbe_fc_full:
3105                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3106                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3107                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3108                 break;
3109         default:
3110                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3111                 ret_val = IXGBE_ERR_CONFIG;
3112                 goto out;
3113                 break;
3114         }
3115
3116         /* Set 802.3x based flow control settings. */
3117         mflcn_reg |= IXGBE_MFLCN_DPF;
3118         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3119         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3120
3121         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3122         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3123                 hw->fc.high_water[tc_num]) {
3124                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3125                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3126                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3127         } else {
3128                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3129                 /*
3130                  * In order to prevent Tx hangs when the internal Tx
3131                  * switch is enabled we must set the high water mark
3132                  * to the maximum FCRTH value.  This allows the Tx
3133                  * switch to function even under heavy Rx workloads.
3134                  */
3135                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3136         }
3137         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3138
3139         /* Configure pause time (2 TCs per register) */
3140         reg = hw->fc.pause_time * 0x00010001;
3141         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3142                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3143
3144         /* Configure flow control refresh threshold value */
3145         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3146
3147 out:
3148         return ret_val;
3149 }
3150
3151 static int
3152 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3153 {
3154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3155         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3156
3157         if(hw->mac.type != ixgbe_mac_82598EB) {
3158                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3159         }
3160         return ret_val;
3161 }
3162
3163 static int
3164 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3165 {
3166         int err;
3167         uint32_t rx_buf_size;
3168         uint32_t max_high_water;
3169         uint8_t tc_num;
3170         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3171         struct ixgbe_hw *hw =
3172                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3173         struct ixgbe_dcb_config *dcb_config =
3174                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3175
3176         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3177                 ixgbe_fc_none,
3178                 ixgbe_fc_rx_pause,
3179                 ixgbe_fc_tx_pause,
3180                 ixgbe_fc_full
3181         };
3182
3183         PMD_INIT_FUNC_TRACE();
3184
3185         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3186         tc_num = map[pfc_conf->priority];
3187         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3188         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3189         /*
3190          * At least reserve one Ethernet frame for watermark
3191          * high_water/low_water in kilo bytes for ixgbe
3192          */
3193         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3194         if ((pfc_conf->fc.high_water > max_high_water) ||
3195             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3196                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3197                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3198                 return (-EINVAL);
3199         }
3200
3201         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3202         hw->fc.pause_time = pfc_conf->fc.pause_time;
3203         hw->fc.send_xon = pfc_conf->fc.send_xon;
3204         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3205         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3206
3207         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3208
3209         /* Not negotiated is not an error case */
3210         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3211                 return 0;
3212
3213         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3214         return -EIO;
3215 }
3216
3217 static int
3218 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3219                           struct rte_eth_rss_reta_entry64 *reta_conf,
3220                           uint16_t reta_size)
3221 {
3222         uint8_t i, j, mask;
3223         uint32_t reta, r;
3224         uint16_t idx, shift;
3225         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3226
3227         PMD_INIT_FUNC_TRACE();
3228         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3229                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3230                         "(%d) doesn't match the number hardware can supported "
3231                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3232                 return -EINVAL;
3233         }
3234
3235         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3236                 idx = i / RTE_RETA_GROUP_SIZE;
3237                 shift = i % RTE_RETA_GROUP_SIZE;
3238                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3239                                                 IXGBE_4_BIT_MASK);
3240                 if (!mask)
3241                         continue;
3242                 if (mask == IXGBE_4_BIT_MASK)
3243                         r = 0;
3244                 else
3245                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
3246                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3247                         if (mask & (0x1 << j))
3248                                 reta |= reta_conf[idx].reta[shift + j] <<
3249                                                         (CHAR_BIT * j);
3250                         else
3251                                 reta |= r & (IXGBE_8_BIT_MASK <<
3252                                                 (CHAR_BIT * j));
3253                 }
3254                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3255         }
3256
3257         return 0;
3258 }
3259
3260 static int
3261 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3262                          struct rte_eth_rss_reta_entry64 *reta_conf,
3263                          uint16_t reta_size)
3264 {
3265         uint8_t i, j, mask;
3266         uint32_t reta;
3267         uint16_t idx, shift;
3268         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269
3270         PMD_INIT_FUNC_TRACE();
3271         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3272                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3273                         "(%d) doesn't match the number hardware can supported "
3274                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3275                 return -EINVAL;
3276         }
3277
3278         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
3279                 idx = i / RTE_RETA_GROUP_SIZE;
3280                 shift = i % RTE_RETA_GROUP_SIZE;
3281                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3282                                                 IXGBE_4_BIT_MASK);
3283                 if (!mask)
3284                         continue;
3285
3286                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
3287                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3288                         if (mask & (0x1 << j))
3289                                 reta_conf[idx].reta[shift + j] =
3290                                         ((reta >> (CHAR_BIT * j)) &
3291                                                 IXGBE_8_BIT_MASK);
3292                 }
3293         }
3294
3295         return 0;
3296 }
3297
3298 static void
3299 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3300                                 uint32_t index, uint32_t pool)
3301 {
3302         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3303         uint32_t enable_addr = 1;
3304
3305         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3306 }
3307
3308 static void
3309 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3310 {
3311         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3312
3313         ixgbe_clear_rar(hw, index);
3314 }
3315
3316 static void
3317 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3318 {
3319         ixgbe_remove_rar(dev, 0);
3320
3321         ixgbe_add_rar(dev, addr, 0, 0);
3322 }
3323
3324 static int
3325 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3326 {
3327         uint32_t hlreg0;
3328         uint32_t maxfrs;
3329         struct ixgbe_hw *hw;
3330         struct rte_eth_dev_info dev_info;
3331         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3332
3333         ixgbe_dev_info_get(dev, &dev_info);
3334
3335         /* check that mtu is within the allowed range */
3336         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3337                 return -EINVAL;
3338
3339         /* refuse mtu that requires the support of scattered packets when this
3340          * feature has not been enabled before. */
3341         if (!dev->data->scattered_rx &&
3342             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3343              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3344                 return -EINVAL;
3345
3346         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3347         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3348
3349         /* switch to jumbo mode if needed */
3350         if (frame_size > ETHER_MAX_LEN) {
3351                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3352                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3353         } else {
3354                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3355                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3356         }
3357         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3358
3359         /* update max frame size */
3360         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3361
3362         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3363         maxfrs &= 0x0000FFFF;
3364         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3365         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3366
3367         return 0;
3368 }
3369
3370 /*
3371  * Virtual Function operations
3372  */
3373 static void
3374 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3375 {
3376         PMD_INIT_FUNC_TRACE();
3377
3378         /* Clear interrupt mask to stop from interrupts being generated */
3379         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3380
3381         IXGBE_WRITE_FLUSH(hw);
3382 }
3383
3384 static void
3385 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3386 {
3387         PMD_INIT_FUNC_TRACE();
3388
3389         /* VF enable interrupt autoclean */
3390         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3391         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3392         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3393
3394         IXGBE_WRITE_FLUSH(hw);
3395 }
3396
3397 static int
3398 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3399 {
3400         struct rte_eth_conf* conf = &dev->data->dev_conf;
3401         struct ixgbe_adapter *adapter =
3402                         (struct ixgbe_adapter *)dev->data->dev_private;
3403
3404         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3405                      dev->data->port_id);
3406
3407         /*
3408          * VF has no ability to enable/disable HW CRC
3409          * Keep the persistent behavior the same as Host PF
3410          */
3411 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3412         if (!conf->rxmode.hw_strip_crc) {
3413                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3414                 conf->rxmode.hw_strip_crc = 1;
3415         }
3416 #else
3417         if (conf->rxmode.hw_strip_crc) {
3418                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3419                 conf->rxmode.hw_strip_crc = 0;
3420         }
3421 #endif
3422
3423         /*
3424          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3425          * allocation or vector Rx preconditions we will reset it.
3426          */
3427         adapter->rx_bulk_alloc_allowed = true;
3428         adapter->rx_vec_allowed = true;
3429
3430         return 0;
3431 }
3432
3433 static int
3434 ixgbevf_dev_start(struct rte_eth_dev *dev)
3435 {
3436         struct ixgbe_hw *hw =
3437                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3438 #ifdef RTE_NEXT_ABI
3439         uint32_t intr_vector = 0;
3440 #endif
3441         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3442
3443         int err, mask = 0;
3444
3445         PMD_INIT_FUNC_TRACE();
3446
3447         hw->mac.ops.reset_hw(hw);
3448         hw->mac.get_link_status = true;
3449
3450         /* negotiate mailbox API version to use with the PF. */
3451         ixgbevf_negotiate_api(hw);
3452
3453         ixgbevf_dev_tx_init(dev);
3454
3455         /* This can fail when allocating mbufs for descriptor rings */
3456         err = ixgbevf_dev_rx_init(dev);
3457         if (err) {
3458                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3459                 ixgbe_dev_clear_queues(dev);
3460                 return err;
3461         }
3462
3463         /* Set vfta */
3464         ixgbevf_set_vfta_all(dev,1);
3465
3466         /* Set HW strip */
3467         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3468                 ETH_VLAN_EXTEND_MASK;
3469         ixgbevf_vlan_offload_set(dev, mask);
3470
3471         ixgbevf_dev_rxtx_start(dev);
3472
3473 #ifdef RTE_NEXT_ABI
3474         /* check and configure queue intr-vector mapping */
3475         if (dev->data->dev_conf.intr_conf.rxq != 0)
3476                 intr_vector = dev->data->nb_rx_queues;
3477
3478         if (rte_intr_efd_enable(intr_handle, intr_vector))
3479                 return -1;
3480
3481         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3482                 intr_handle->intr_vec =
3483                         rte_zmalloc("intr_vec",
3484                                     dev->data->nb_rx_queues * sizeof(int), 0);
3485                 if (intr_handle->intr_vec == NULL) {
3486                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3487                                      " intr_vec\n", dev->data->nb_rx_queues);
3488                         return -ENOMEM;
3489                 }
3490         }
3491 #endif
3492         ixgbevf_configure_msix(dev);
3493
3494         if (dev->data->dev_conf.intr_conf.lsc != 0) {
3495                 if (rte_intr_allow_others(intr_handle))
3496                         rte_intr_callback_register(intr_handle,
3497                                         ixgbevf_dev_interrupt_handler,
3498                                         (void *)dev);
3499                 else
3500                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
3501                                      " no intr multiplex\n");
3502         }
3503
3504         rte_intr_enable(intr_handle);
3505
3506         /* Re-enable interrupt for VF */
3507         ixgbevf_intr_enable(hw);
3508
3509         return 0;
3510 }
3511
3512 static void
3513 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3514 {
3515         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3516         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3517
3518         PMD_INIT_FUNC_TRACE();
3519
3520         hw->adapter_stopped = 1;
3521         ixgbe_stop_adapter(hw);
3522
3523         /*
3524           * Clear what we set, but we still keep shadow_vfta to
3525           * restore after device starts
3526           */
3527         ixgbevf_set_vfta_all(dev,0);
3528
3529         /* Clear stored conf */
3530         dev->data->scattered_rx = 0;
3531
3532         ixgbe_dev_clear_queues(dev);
3533
3534         /* disable intr eventfd mapping */
3535         rte_intr_disable(intr_handle);
3536
3537 #ifdef RTE_NEXT_ABI
3538         /* Clean datapath event and queue/vec mapping */
3539         rte_intr_efd_disable(intr_handle);
3540         if (intr_handle->intr_vec != NULL) {
3541                 rte_free(intr_handle->intr_vec);
3542                 intr_handle->intr_vec = NULL;
3543         }
3544 #endif
3545 }
3546
3547 static void
3548 ixgbevf_dev_close(struct rte_eth_dev *dev)
3549 {
3550         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3551 #ifdef RTE_NEXT_ABI
3552         struct rte_pci_device *pci_dev;
3553 #endif
3554
3555         PMD_INIT_FUNC_TRACE();
3556
3557         ixgbe_reset_hw(hw);
3558
3559         ixgbevf_dev_stop(dev);
3560
3561         ixgbe_dev_free_queues(dev);
3562
3563         /* reprogram the RAR[0] in case user changed it. */
3564         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3565
3566 #ifdef RTE_NEXT_ABI
3567         pci_dev = dev->pci_dev;
3568         if (pci_dev->intr_handle.intr_vec) {
3569                 rte_free(pci_dev->intr_handle.intr_vec);
3570                 pci_dev->intr_handle.intr_vec = NULL;
3571         }
3572 #endif
3573 }
3574
3575 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3576 {
3577         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3578         struct ixgbe_vfta * shadow_vfta =
3579                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3580         int i = 0, j = 0, vfta = 0, mask = 1;
3581
3582         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3583                 vfta = shadow_vfta->vfta[i];
3584                 if(vfta){
3585                         mask = 1;
3586                         for (j = 0; j < 32; j++){
3587                                 if(vfta & mask)
3588                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3589                                 mask<<=1;
3590                         }
3591                 }
3592         }
3593
3594 }
3595
3596 static int
3597 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3598 {
3599         struct ixgbe_hw *hw =
3600                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601         struct ixgbe_vfta * shadow_vfta =
3602                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3603         uint32_t vid_idx = 0;
3604         uint32_t vid_bit = 0;
3605         int ret = 0;
3606
3607         PMD_INIT_FUNC_TRACE();
3608
3609         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3610         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3611         if(ret){
3612                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3613                 return ret;
3614         }
3615         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3616         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3617
3618         /* Save what we set and retore it after device reset */
3619         if (on)
3620                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3621         else
3622                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3623
3624         return 0;
3625 }
3626
3627 static void
3628 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3629 {
3630         struct ixgbe_hw *hw =
3631                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3632         uint32_t ctrl;
3633
3634         PMD_INIT_FUNC_TRACE();
3635
3636         if(queue >= hw->mac.max_rx_queues)
3637                 return;
3638
3639         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3640         if(on)
3641                 ctrl |= IXGBE_RXDCTL_VME;
3642         else
3643                 ctrl &= ~IXGBE_RXDCTL_VME;
3644         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3645
3646         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3647 }
3648
3649 static void
3650 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3651 {
3652         struct ixgbe_hw *hw =
3653                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3654         uint16_t i;
3655         int on = 0;
3656
3657         /* VF function only support hw strip feature, others are not support */
3658         if(mask & ETH_VLAN_STRIP_MASK){
3659                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3660
3661                 for(i=0; i < hw->mac.max_rx_queues; i++)
3662                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3663         }
3664 }
3665
3666 static int
3667 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3668 {
3669         uint32_t reg_val;
3670
3671         /* we only need to do this if VMDq is enabled */
3672         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3673         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3674                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3675                 return (-1);
3676         }
3677
3678         return 0;
3679 }
3680
3681 static uint32_t
3682 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3683 {
3684         uint32_t vector = 0;
3685         switch (hw->mac.mc_filter_type) {
3686         case 0:   /* use bits [47:36] of the address */
3687                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3688                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3689                 break;
3690         case 1:   /* use bits [46:35] of the address */
3691                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3692                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3693                 break;
3694         case 2:   /* use bits [45:34] of the address */
3695                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3696                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3697                 break;
3698         case 3:   /* use bits [43:32] of the address */
3699                 vector = ((uc_addr->addr_bytes[4]) |
3700                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3701                 break;
3702         default:  /* Invalid mc_filter_type */
3703                 break;
3704         }
3705
3706         /* vector can only be 12-bits or boundary will be exceeded */
3707         vector &= 0xFFF;
3708         return vector;
3709 }
3710
3711 static int
3712 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3713                                uint8_t on)
3714 {
3715         uint32_t vector;
3716         uint32_t uta_idx;
3717         uint32_t reg_val;
3718         uint32_t uta_shift;
3719         uint32_t rc;
3720         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3721         const uint32_t ixgbe_uta_bit_shift = 5;
3722         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3723         const uint32_t bit1 = 0x1;
3724
3725         struct ixgbe_hw *hw =
3726                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3727         struct ixgbe_uta_info *uta_info =
3728                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3729
3730         /* The UTA table only exists on 82599 hardware and newer */
3731         if (hw->mac.type < ixgbe_mac_82599EB)
3732                 return (-ENOTSUP);
3733
3734         vector = ixgbe_uta_vector(hw,mac_addr);
3735         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3736         uta_shift = vector & ixgbe_uta_bit_mask;
3737
3738         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3739         if(rc == on)
3740                 return 0;
3741
3742         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3743         if (on) {
3744                 uta_info->uta_in_use++;
3745                 reg_val |= (bit1 << uta_shift);
3746                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3747         } else {
3748                 uta_info->uta_in_use--;
3749                 reg_val &= ~(bit1 << uta_shift);
3750                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3751         }
3752
3753         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3754
3755         if (uta_info->uta_in_use > 0)
3756                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3757                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3758         else
3759                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3760
3761         return 0;
3762 }
3763
3764 static int
3765 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3766 {
3767         int i;
3768         struct ixgbe_hw *hw =
3769                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3770         struct ixgbe_uta_info *uta_info =
3771                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3772
3773         /* The UTA table only exists on 82599 hardware and newer */
3774         if (hw->mac.type < ixgbe_mac_82599EB)
3775                 return (-ENOTSUP);
3776
3777         if(on) {
3778                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3779                         uta_info->uta_shadow[i] = ~0;
3780                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3781                 }
3782         } else {
3783                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3784                         uta_info->uta_shadow[i] = 0;
3785                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3786                 }
3787         }
3788         return 0;
3789
3790 }
3791
3792 uint32_t
3793 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3794 {
3795         uint32_t new_val = orig_val;
3796
3797         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3798                 new_val |= IXGBE_VMOLR_AUPE;
3799         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3800                 new_val |= IXGBE_VMOLR_ROMPE;
3801         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3802                 new_val |= IXGBE_VMOLR_ROPE;
3803         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3804                 new_val |= IXGBE_VMOLR_BAM;
3805         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3806                 new_val |= IXGBE_VMOLR_MPE;
3807
3808         return new_val;
3809 }
3810
3811 static int
3812 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3813                                uint16_t rx_mask, uint8_t on)
3814 {
3815         int val = 0;
3816
3817         struct ixgbe_hw *hw =
3818                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3819         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3820
3821         if (hw->mac.type == ixgbe_mac_82598EB) {
3822                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3823                              " on 82599 hardware and newer");
3824                 return (-ENOTSUP);
3825         }
3826         if (ixgbe_vmdq_mode_check(hw) < 0)
3827                 return (-ENOTSUP);
3828
3829         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3830
3831         if (on)
3832                 vmolr |= val;
3833         else
3834                 vmolr &= ~val;
3835
3836         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3837
3838         return 0;
3839 }
3840
3841 static int
3842 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3843 {
3844         uint32_t reg,addr;
3845         uint32_t val;
3846         const uint8_t bit1 = 0x1;
3847
3848         struct ixgbe_hw *hw =
3849                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3850
3851         if (ixgbe_vmdq_mode_check(hw) < 0)
3852                 return (-ENOTSUP);
3853
3854         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3855         reg = IXGBE_READ_REG(hw, addr);
3856         val = bit1 << pool;
3857
3858         if (on)
3859                 reg |= val;
3860         else
3861                 reg &= ~val;
3862
3863         IXGBE_WRITE_REG(hw, addr,reg);
3864
3865         return 0;
3866 }
3867
3868 static int
3869 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3870 {
3871         uint32_t reg,addr;
3872         uint32_t val;
3873         const uint8_t bit1 = 0x1;
3874
3875         struct ixgbe_hw *hw =
3876                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3877
3878         if (ixgbe_vmdq_mode_check(hw) < 0)
3879                 return (-ENOTSUP);
3880
3881         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3882         reg = IXGBE_READ_REG(hw, addr);
3883         val = bit1 << pool;
3884
3885         if (on)
3886                 reg |= val;
3887         else
3888                 reg &= ~val;
3889
3890         IXGBE_WRITE_REG(hw, addr,reg);
3891
3892         return 0;
3893 }
3894
3895 static int
3896 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3897                         uint64_t pool_mask, uint8_t vlan_on)
3898 {
3899         int ret = 0;
3900         uint16_t pool_idx;
3901         struct ixgbe_hw *hw =
3902                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3903
3904         if (ixgbe_vmdq_mode_check(hw) < 0)
3905                 return (-ENOTSUP);
3906         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3907                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3908                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3909                         if (ret < 0)
3910                                 return ret;
3911         }
3912
3913         return ret;
3914 }
3915
3916 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
3917 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
3918 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
3919 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
3920 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
3921         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
3922         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
3923
3924 static int
3925 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3926                         struct rte_eth_mirror_conf *mirror_conf,
3927                         uint8_t rule_id, uint8_t on)
3928 {
3929         uint32_t mr_ctl,vlvf;
3930         uint32_t mp_lsb = 0;
3931         uint32_t mv_msb = 0;
3932         uint32_t mv_lsb = 0;
3933         uint32_t mp_msb = 0;
3934         uint8_t i = 0;
3935         int reg_index = 0;
3936         uint64_t vlan_mask = 0;
3937
3938         const uint8_t pool_mask_offset = 32;
3939         const uint8_t vlan_mask_offset = 32;
3940         const uint8_t dst_pool_offset = 8;
3941         const uint8_t rule_mr_offset  = 4;
3942         const uint8_t mirror_rule_mask= 0x0F;
3943
3944         struct ixgbe_mirror_info *mr_info =
3945                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3946         struct ixgbe_hw *hw =
3947                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3948         uint8_t mirror_type = 0;
3949
3950         if (ixgbe_vmdq_mode_check(hw) < 0)
3951                 return -ENOTSUP;
3952
3953         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
3954                 return -EINVAL;
3955
3956         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
3957                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
3958                         mirror_conf->rule_type);
3959                 return -EINVAL;
3960         }
3961
3962         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
3963                 mirror_type |= IXGBE_MRCTL_VLME;
3964                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3965                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3966                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3967                                 /* search vlan id related pool vlan filter index */
3968                                 reg_index = ixgbe_find_vlvf_slot(hw,
3969                                                 mirror_conf->vlan.vlan_id[i]);
3970                                 if(reg_index < 0)
3971                                         return -EINVAL;
3972                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3973                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3974                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
3975                                       mirror_conf->vlan.vlan_id[i]))
3976                                         vlan_mask |= (1ULL << reg_index);
3977                                 else
3978                                         return -EINVAL;
3979                         }
3980                 }
3981
3982                 if (on) {
3983                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3984                         mv_msb = vlan_mask >> vlan_mask_offset;
3985
3986                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3987                                                 mirror_conf->vlan.vlan_mask;
3988                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3989                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3990                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3991                                                 mirror_conf->vlan.vlan_id[i];
3992                         }
3993                 } else {
3994                         mv_lsb = 0;
3995                         mv_msb = 0;
3996                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3997                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3998                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3999                 }
4000         }
4001
4002         /*
4003          * if enable pool mirror, write related pool mask register,if disable
4004          * pool mirror, clear PFMRVM register
4005          */
4006         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4007                 mirror_type |= IXGBE_MRCTL_VPME;
4008                 if (on) {
4009                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4010                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4011                         mr_info->mr_conf[rule_id].pool_mask =
4012                                         mirror_conf->pool_mask;
4013
4014                 } else {
4015                         mp_lsb = 0;
4016                         mp_msb = 0;
4017                         mr_info->mr_conf[rule_id].pool_mask = 0;
4018                 }
4019         }
4020         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4021                 mirror_type |= IXGBE_MRCTL_UPME;
4022         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4023                 mirror_type |= IXGBE_MRCTL_DPME;
4024
4025         /* read  mirror control register and recalculate it */
4026         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4027
4028         if (on) {
4029                 mr_ctl |= mirror_type;
4030                 mr_ctl &= mirror_rule_mask;
4031                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4032         } else
4033                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4034
4035         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4036         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4037
4038         /* write mirrror control  register */
4039         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4040
4041         /* write pool mirrror control  register */
4042         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4043                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4044                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4045                                 mp_msb);
4046         }
4047         /* write VLAN mirrror control  register */
4048         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4049                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4050                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4051                                 mv_msb);
4052         }
4053
4054         return 0;
4055 }
4056
4057 static int
4058 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4059 {
4060         int mr_ctl = 0;
4061         uint32_t lsb_val = 0;
4062         uint32_t msb_val = 0;
4063         const uint8_t rule_mr_offset = 4;
4064
4065         struct ixgbe_hw *hw =
4066                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4067         struct ixgbe_mirror_info *mr_info =
4068                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4069
4070         if (ixgbe_vmdq_mode_check(hw) < 0)
4071                 return (-ENOTSUP);
4072
4073         memset(&mr_info->mr_conf[rule_id], 0,
4074                 sizeof(struct rte_eth_mirror_conf));
4075
4076         /* clear PFVMCTL register */
4077         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4078
4079         /* clear pool mask register */
4080         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4081         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4082
4083         /* clear vlan mask register */
4084         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4085         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4086
4087         return 0;
4088 }
4089
4090 #ifdef RTE_NEXT_ABI
4091 static int
4092 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4093 {
4094         uint32_t mask;
4095         struct ixgbe_hw *hw =
4096                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4097
4098         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4099         mask |= (1 << queue_id);
4100         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4101
4102         rte_intr_enable(&dev->pci_dev->intr_handle);
4103
4104         return 0;
4105 }
4106
4107 static int
4108 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4109 {
4110         uint32_t mask;
4111         struct ixgbe_hw *hw =
4112                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4113
4114         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4115         mask &= ~(1 << queue_id);
4116         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4117
4118         return 0;
4119 }
4120
4121 static int
4122 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4123 {
4124         uint32_t mask;
4125         struct ixgbe_hw *hw =
4126                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127         struct ixgbe_interrupt *intr =
4128                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4129
4130         if (queue_id < 16) {
4131                 ixgbe_disable_intr(hw);
4132                 intr->mask |= (1 << queue_id);
4133                 ixgbe_enable_intr(dev);
4134         } else if (queue_id < 32) {
4135                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4136                 mask &= (1 << queue_id);
4137                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4138         } else if (queue_id < 64) {
4139                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4140                 mask &= (1 << (queue_id - 32));
4141                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4142         }
4143         rte_intr_enable(&dev->pci_dev->intr_handle);
4144
4145         return 0;
4146 }
4147
4148 static int
4149 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4150 {
4151         uint32_t mask;
4152         struct ixgbe_hw *hw =
4153                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4154         struct ixgbe_interrupt *intr =
4155                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4156
4157         if (queue_id < 16) {
4158                 ixgbe_disable_intr(hw);
4159                 intr->mask &= ~(1 << queue_id);
4160                 ixgbe_enable_intr(dev);
4161         } else if (queue_id < 32) {
4162                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4163                 mask &= ~(1 << queue_id);
4164                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4165         } else if (queue_id < 64) {
4166                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4167                 mask &= ~(1 << (queue_id - 32));
4168                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4169         }
4170
4171         return 0;
4172 }
4173
4174 static void
4175 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4176                      uint8_t queue, uint8_t msix_vector)
4177 {
4178         uint32_t tmp, idx;
4179
4180         if (direction == -1) {
4181                 /* other causes */
4182                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4183                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4184                 tmp &= ~0xFF;
4185                 tmp |= msix_vector;
4186                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4187         } else {
4188                 /* rx or tx cause */
4189                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4190                 idx = ((16 * (queue & 1)) + (8 * direction));
4191                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4192                 tmp &= ~(0xFF << idx);
4193                 tmp |= (msix_vector << idx);
4194                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4195         }
4196 }
4197
4198 /**
4199  * set the IVAR registers, mapping interrupt causes to vectors
4200  * @param hw
4201  *  pointer to ixgbe_hw struct
4202  * @direction
4203  *  0 for Rx, 1 for Tx, -1 for other causes
4204  * @queue
4205  *  queue to map the corresponding interrupt to
4206  * @msix_vector
4207  *  the vector to map to the corresponding queue
4208  */
4209 static void
4210 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4211                    uint8_t queue, uint8_t msix_vector)
4212 {
4213         uint32_t tmp, idx;
4214
4215         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4216         if (hw->mac.type == ixgbe_mac_82598EB) {
4217                 if (direction == -1)
4218                         direction = 0;
4219                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4220                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4221                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4222                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4223                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4224         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4225                         (hw->mac.type == ixgbe_mac_X540)) {
4226                 if (direction == -1) {
4227                         /* other causes */
4228                         idx = ((queue & 1) * 8);
4229                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4230                         tmp &= ~(0xFF << idx);
4231                         tmp |= (msix_vector << idx);
4232                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4233                 } else {
4234                         /* rx or tx causes */
4235                         idx = ((16 * (queue & 1)) + (8 * direction));
4236                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4237                         tmp &= ~(0xFF << idx);
4238                         tmp |= (msix_vector << idx);
4239                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4240                 }
4241         }
4242 }
4243 #endif
4244
4245 static void
4246 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4247 {
4248         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4249 #ifdef RTE_NEXT_ABI
4250         struct ixgbe_hw *hw =
4251                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4252         uint32_t q_idx;
4253         uint32_t vector_idx = 0;
4254 #endif
4255
4256         /* won't configure msix register if no mapping is done
4257          * between intr vector and event fd.
4258          */
4259         if (!rte_intr_dp_is_en(intr_handle))
4260                 return;
4261
4262 #ifdef RTE_NEXT_ABI
4263         /* Configure all RX queues of VF */
4264         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4265                 /* Force all queue use vector 0,
4266                  * as IXGBE_VF_MAXMSIVECOTR = 1
4267                  */
4268                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4269                 intr_handle->intr_vec[q_idx] = vector_idx;
4270         }
4271
4272         /* Configure VF Rx queue ivar */
4273         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4274 #endif
4275 }
4276
4277 /**
4278  * Sets up the hardware to properly generate MSI-X interrupts
4279  * @hw
4280  *  board private structure
4281  */
4282 static void
4283 ixgbe_configure_msix(struct rte_eth_dev *dev)
4284 {
4285         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4286 #ifdef RTE_NEXT_ABI
4287         struct ixgbe_hw *hw =
4288                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4289         uint32_t queue_id, vec = 0;
4290         uint32_t mask;
4291         uint32_t gpie;
4292 #endif
4293
4294         /* won't configure msix register if no mapping is done
4295          * between intr vector and event fd
4296          */
4297         if (!rte_intr_dp_is_en(intr_handle))
4298                 return;
4299
4300 #ifdef RTE_NEXT_ABI
4301         /* setup GPIE for MSI-x mode */
4302         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4303         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4304                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4305         /* auto clearing and auto setting corresponding bits in EIMS
4306          * when MSI-X interrupt is triggered
4307          */
4308         if (hw->mac.type == ixgbe_mac_82598EB) {
4309                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4310         } else {
4311                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4312                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4313         }
4314         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4315
4316         /* Populate the IVAR table and set the ITR values to the
4317          * corresponding register.
4318          */
4319         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4320              queue_id++) {
4321                 /* by default, 1:1 mapping */
4322                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4323                 intr_handle->intr_vec[queue_id] = vec;
4324                 if (vec < intr_handle->nb_efd - 1)
4325                         vec++;
4326         }
4327
4328         switch (hw->mac.type) {
4329         case ixgbe_mac_82598EB:
4330                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4331                                    intr_handle->max_intr - 1);
4332                 break;
4333         case ixgbe_mac_82599EB:
4334         case ixgbe_mac_X540:
4335                 ixgbe_set_ivar_map(hw, -1, 1, intr_handle->max_intr - 1);
4336                 break;
4337         default:
4338                 break;
4339         }
4340         IXGBE_WRITE_REG(hw, IXGBE_EITR(queue_id),
4341                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4342
4343         /* set up to autoclear timer, and the vectors */
4344         mask = IXGBE_EIMS_ENABLE_MASK;
4345         mask &= ~(IXGBE_EIMS_OTHER |
4346                   IXGBE_EIMS_MAILBOX |
4347                   IXGBE_EIMS_LSC);
4348
4349         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4350 #endif
4351 }
4352
4353 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4354         uint16_t queue_idx, uint16_t tx_rate)
4355 {
4356         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4357         uint32_t rf_dec, rf_int;
4358         uint32_t bcnrc_val;
4359         uint16_t link_speed = dev->data->dev_link.link_speed;
4360
4361         if (queue_idx >= hw->mac.max_tx_queues)
4362                 return -EINVAL;
4363
4364         if (tx_rate != 0) {
4365                 /* Calculate the rate factor values to set */
4366                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4367                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4368                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4369
4370                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4371                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4372                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4373                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4374         } else {
4375                 bcnrc_val = 0;
4376         }
4377
4378         /*
4379          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4380          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4381          * set as 0x4.
4382          */
4383         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4384                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4385                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4386                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4387                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4388         else
4389                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4390                         IXGBE_MMW_SIZE_DEFAULT);
4391
4392         /* Set RTTBCNRC of queue X */
4393         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4394         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4395         IXGBE_WRITE_FLUSH(hw);
4396
4397         return 0;
4398 }
4399
4400 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4401         uint16_t tx_rate, uint64_t q_msk)
4402 {
4403         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4404         struct ixgbe_vf_info *vfinfo =
4405                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4406         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4407         uint32_t queue_stride =
4408                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4409         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4410         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4411         uint16_t total_rate = 0;
4412
4413         if (queue_end >= hw->mac.max_tx_queues)
4414                 return -EINVAL;
4415
4416         if (vfinfo != NULL) {
4417                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4418                         if (vf_idx == vf)
4419                                 continue;
4420                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4421                                 idx++)
4422                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4423                 }
4424         } else
4425                 return -EINVAL;
4426
4427         /* Store tx_rate for this vf. */
4428         for (idx = 0; idx < nb_q_per_pool; idx++) {
4429                 if (((uint64_t)0x1 << idx) & q_msk) {
4430                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4431                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4432                         total_rate += tx_rate;
4433                 }
4434         }
4435
4436         if (total_rate > dev->data->dev_link.link_speed) {
4437                 /*
4438                  * Reset stored TX rate of the VF if it causes exceed
4439                  * link speed.
4440                  */
4441                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4442                 return -EINVAL;
4443         }
4444
4445         /* Set RTTBCNRC of each queue/pool for vf X  */
4446         for (; queue_idx <= queue_end; queue_idx++) {
4447                 if (0x1 & q_msk)
4448                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4449                 q_msk = q_msk >> 1;
4450         }
4451
4452         return 0;
4453 }
4454
4455 static void
4456 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4457                      __attribute__((unused)) uint32_t index,
4458                      __attribute__((unused)) uint32_t pool)
4459 {
4460         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4461         int diag;
4462
4463         /*
4464          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4465          * operation. Trap this case to avoid exhausting the [very limited]
4466          * set of PF resources used to store VF MAC addresses.
4467          */
4468         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4469                 return;
4470         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4471         if (diag == 0)
4472                 return;
4473         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4474 }
4475
4476 static void
4477 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4478 {
4479         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4480         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4481         struct ether_addr *mac_addr;
4482         uint32_t i;
4483         int diag;
4484
4485         /*
4486          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4487          * not support the deletion of a given MAC address.
4488          * Instead, it imposes to delete all MAC addresses, then to add again
4489          * all MAC addresses with the exception of the one to be deleted.
4490          */
4491         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4492
4493         /*
4494          * Add again all MAC addresses, with the exception of the deleted one
4495          * and of the permanent MAC address.
4496          */
4497         for (i = 0, mac_addr = dev->data->mac_addrs;
4498              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4499                 /* Skip the deleted MAC address */
4500                 if (i == index)
4501                         continue;
4502                 /* Skip NULL MAC addresses */
4503                 if (is_zero_ether_addr(mac_addr))
4504                         continue;
4505                 /* Skip the permanent MAC address */
4506                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4507                         continue;
4508                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4509                 if (diag != 0)
4510                         PMD_DRV_LOG(ERR,
4511                                     "Adding again MAC address "
4512                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4513                                     "diag=%d",
4514                                     mac_addr->addr_bytes[0],
4515                                     mac_addr->addr_bytes[1],
4516                                     mac_addr->addr_bytes[2],
4517                                     mac_addr->addr_bytes[3],
4518                                     mac_addr->addr_bytes[4],
4519                                     mac_addr->addr_bytes[5],
4520                                     diag);
4521         }
4522 }
4523
4524 static void
4525 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4526 {
4527         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4528
4529         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4530 }
4531
4532 #define MAC_TYPE_FILTER_SUP(type)    do {\
4533         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4534                 (type) != ixgbe_mac_X550)\
4535                 return -ENOTSUP;\
4536 } while (0)
4537
4538 static int
4539 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4540                         struct rte_eth_syn_filter *filter,
4541                         bool add)
4542 {
4543         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4544         uint32_t synqf;
4545
4546         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4547                 return -EINVAL;
4548
4549         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4550
4551         if (add) {
4552                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4553                         return -EINVAL;
4554                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4555                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4556
4557                 if (filter->hig_pri)
4558                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4559                 else
4560                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4561         } else {
4562                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4563                         return -ENOENT;
4564                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4565         }
4566         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4567         IXGBE_WRITE_FLUSH(hw);
4568         return 0;
4569 }
4570
4571 static int
4572 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4573                         struct rte_eth_syn_filter *filter)
4574 {
4575         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4576         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4577
4578         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4579                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4580                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4581                 return 0;
4582         }
4583         return -ENOENT;
4584 }
4585
4586 static int
4587 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4588                         enum rte_filter_op filter_op,
4589                         void *arg)
4590 {
4591         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4592         int ret;
4593
4594         MAC_TYPE_FILTER_SUP(hw->mac.type);
4595
4596         if (filter_op == RTE_ETH_FILTER_NOP)
4597                 return 0;
4598
4599         if (arg == NULL) {
4600                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4601                             filter_op);
4602                 return -EINVAL;
4603         }
4604
4605         switch (filter_op) {
4606         case RTE_ETH_FILTER_ADD:
4607                 ret = ixgbe_syn_filter_set(dev,
4608                                 (struct rte_eth_syn_filter *)arg,
4609                                 TRUE);
4610                 break;
4611         case RTE_ETH_FILTER_DELETE:
4612                 ret = ixgbe_syn_filter_set(dev,
4613                                 (struct rte_eth_syn_filter *)arg,
4614                                 FALSE);
4615                 break;
4616         case RTE_ETH_FILTER_GET:
4617                 ret = ixgbe_syn_filter_get(dev,
4618                                 (struct rte_eth_syn_filter *)arg);
4619                 break;
4620         default:
4621                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4622                 ret = -EINVAL;
4623                 break;
4624         }
4625
4626         return ret;
4627 }
4628
4629
4630 static inline enum ixgbe_5tuple_protocol
4631 convert_protocol_type(uint8_t protocol_value)
4632 {
4633         if (protocol_value == IPPROTO_TCP)
4634                 return IXGBE_FILTER_PROTOCOL_TCP;
4635         else if (protocol_value == IPPROTO_UDP)
4636                 return IXGBE_FILTER_PROTOCOL_UDP;
4637         else if (protocol_value == IPPROTO_SCTP)
4638                 return IXGBE_FILTER_PROTOCOL_SCTP;
4639         else
4640                 return IXGBE_FILTER_PROTOCOL_NONE;
4641 }
4642
4643 /*
4644  * add a 5tuple filter
4645  *
4646  * @param
4647  * dev: Pointer to struct rte_eth_dev.
4648  * index: the index the filter allocates.
4649  * filter: ponter to the filter that will be added.
4650  * rx_queue: the queue id the filter assigned to.
4651  *
4652  * @return
4653  *    - On success, zero.
4654  *    - On failure, a negative value.
4655  */
4656 static int
4657 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4658                         struct ixgbe_5tuple_filter *filter)
4659 {
4660         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4661         struct ixgbe_filter_info *filter_info =
4662                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4663         int i, idx, shift;
4664         uint32_t ftqf, sdpqf;
4665         uint32_t l34timir = 0;
4666         uint8_t mask = 0xff;
4667
4668         /*
4669          * look for an unused 5tuple filter index,
4670          * and insert the filter to list.
4671          */
4672         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
4673                 idx = i / (sizeof(uint32_t) * NBBY);
4674                 shift = i % (sizeof(uint32_t) * NBBY);
4675                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
4676                         filter_info->fivetuple_mask[idx] |= 1 << shift;
4677                         filter->index = i;
4678                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4679                                           filter,
4680                                           entries);
4681                         break;
4682                 }
4683         }
4684         if (i >= IXGBE_MAX_FTQF_FILTERS) {
4685                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4686                 return -ENOSYS;
4687         }
4688
4689         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
4690                                 IXGBE_SDPQF_DSTPORT_SHIFT);
4691         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
4692
4693         ftqf = (uint32_t)(filter->filter_info.proto &
4694                 IXGBE_FTQF_PROTOCOL_MASK);
4695         ftqf |= (uint32_t)((filter->filter_info.priority &
4696                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
4697         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
4698                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
4699         if (filter->filter_info.dst_ip_mask == 0)
4700                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
4701         if (filter->filter_info.src_port_mask == 0)
4702                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
4703         if (filter->filter_info.dst_port_mask == 0)
4704                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
4705         if (filter->filter_info.proto_mask == 0)
4706                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
4707         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
4708         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
4709         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
4710
4711         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
4712         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
4713         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
4714         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
4715
4716         l34timir |= IXGBE_L34T_IMIR_RESERVE;
4717         l34timir |= (uint32_t)(filter->queue <<
4718                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
4719         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
4720         return 0;
4721 }
4722
4723 /*
4724  * remove a 5tuple filter
4725  *
4726  * @param
4727  * dev: Pointer to struct rte_eth_dev.
4728  * filter: the pointer of the filter will be removed.
4729  */
4730 static void
4731 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
4732                         struct ixgbe_5tuple_filter *filter)
4733 {
4734         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4735         struct ixgbe_filter_info *filter_info =
4736                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4737         uint16_t index = filter->index;
4738
4739         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
4740                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
4741         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4742         rte_free(filter);
4743
4744         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
4745         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
4746         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
4747         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
4748         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4749 }
4750
4751 static int
4752 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4753 {
4754         struct ixgbe_hw *hw;
4755         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4756
4757         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4758
4759         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4760                 return -EINVAL;
4761
4762         /* refuse mtu that requires the support of scattered packets when this
4763          * feature has not been enabled before. */
4764         if (!dev->data->scattered_rx &&
4765             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4766              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4767                 return -EINVAL;
4768
4769         /*
4770          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4771          * request of the version 2.0 of the mailbox API.
4772          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4773          * of the mailbox API.
4774          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4775          * prior to 3.11.33 which contains the following change:
4776          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4777          */
4778         ixgbevf_rlpml_set_vf(hw, max_frame);
4779
4780         /* update max frame size */
4781         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4782         return 0;
4783 }
4784
4785 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
4786         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4787                 return -ENOTSUP;\
4788 } while (0)
4789
4790 static inline struct ixgbe_5tuple_filter *
4791 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4792                         struct ixgbe_5tuple_filter_info *key)
4793 {
4794         struct ixgbe_5tuple_filter *it;
4795
4796         TAILQ_FOREACH(it, filter_list, entries) {
4797                 if (memcmp(key, &it->filter_info,
4798                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4799                         return it;
4800                 }
4801         }
4802         return NULL;
4803 }
4804
4805 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4806 static inline int
4807 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4808                         struct ixgbe_5tuple_filter_info *filter_info)
4809 {
4810         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4811                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4812                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4813                 return -EINVAL;
4814
4815         switch (filter->dst_ip_mask) {
4816         case UINT32_MAX:
4817                 filter_info->dst_ip_mask = 0;
4818                 filter_info->dst_ip = filter->dst_ip;
4819                 break;
4820         case 0:
4821                 filter_info->dst_ip_mask = 1;
4822                 break;
4823         default:
4824                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4825                 return -EINVAL;
4826         }
4827
4828         switch (filter->src_ip_mask) {
4829         case UINT32_MAX:
4830                 filter_info->src_ip_mask = 0;
4831                 filter_info->src_ip = filter->src_ip;
4832                 break;
4833         case 0:
4834                 filter_info->src_ip_mask = 1;
4835                 break;
4836         default:
4837                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4838                 return -EINVAL;
4839         }
4840
4841         switch (filter->dst_port_mask) {
4842         case UINT16_MAX:
4843                 filter_info->dst_port_mask = 0;
4844                 filter_info->dst_port = filter->dst_port;
4845                 break;
4846         case 0:
4847                 filter_info->dst_port_mask = 1;
4848                 break;
4849         default:
4850                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4851                 return -EINVAL;
4852         }
4853
4854         switch (filter->src_port_mask) {
4855         case UINT16_MAX:
4856                 filter_info->src_port_mask = 0;
4857                 filter_info->src_port = filter->src_port;
4858                 break;
4859         case 0:
4860                 filter_info->src_port_mask = 1;
4861                 break;
4862         default:
4863                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4864                 return -EINVAL;
4865         }
4866
4867         switch (filter->proto_mask) {
4868         case UINT8_MAX:
4869                 filter_info->proto_mask = 0;
4870                 filter_info->proto =
4871                         convert_protocol_type(filter->proto);
4872                 break;
4873         case 0:
4874                 filter_info->proto_mask = 1;
4875                 break;
4876         default:
4877                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4878                 return -EINVAL;
4879         }
4880
4881         filter_info->priority = (uint8_t)filter->priority;
4882         return 0;
4883 }
4884
4885 /*
4886  * add or delete a ntuple filter
4887  *
4888  * @param
4889  * dev: Pointer to struct rte_eth_dev.
4890  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4891  * add: if true, add filter, if false, remove filter
4892  *
4893  * @return
4894  *    - On success, zero.
4895  *    - On failure, a negative value.
4896  */
4897 static int
4898 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4899                         struct rte_eth_ntuple_filter *ntuple_filter,
4900                         bool add)
4901 {
4902         struct ixgbe_filter_info *filter_info =
4903                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4904         struct ixgbe_5tuple_filter_info filter_5tuple;
4905         struct ixgbe_5tuple_filter *filter;
4906         int ret;
4907
4908         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4909                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4910                 return -EINVAL;
4911         }
4912
4913         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4914         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4915         if (ret < 0)
4916                 return ret;
4917
4918         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4919                                          &filter_5tuple);
4920         if (filter != NULL && add) {
4921                 PMD_DRV_LOG(ERR, "filter exists.");
4922                 return -EEXIST;
4923         }
4924         if (filter == NULL && !add) {
4925                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4926                 return -ENOENT;
4927         }
4928
4929         if (add) {
4930                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4931                                 sizeof(struct ixgbe_5tuple_filter), 0);
4932                 if (filter == NULL)
4933                         return -ENOMEM;
4934                 (void)rte_memcpy(&filter->filter_info,
4935                                  &filter_5tuple,
4936                                  sizeof(struct ixgbe_5tuple_filter_info));
4937                 filter->queue = ntuple_filter->queue;
4938                 ret = ixgbe_add_5tuple_filter(dev, filter);
4939                 if (ret < 0) {
4940                         rte_free(filter);
4941                         return ret;
4942                 }
4943         } else
4944                 ixgbe_remove_5tuple_filter(dev, filter);
4945
4946         return 0;
4947 }
4948
4949 /*
4950  * get a ntuple filter
4951  *
4952  * @param
4953  * dev: Pointer to struct rte_eth_dev.
4954  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4955  *
4956  * @return
4957  *    - On success, zero.
4958  *    - On failure, a negative value.
4959  */
4960 static int
4961 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4962                         struct rte_eth_ntuple_filter *ntuple_filter)
4963 {
4964         struct ixgbe_filter_info *filter_info =
4965                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4966         struct ixgbe_5tuple_filter_info filter_5tuple;
4967         struct ixgbe_5tuple_filter *filter;
4968         int ret;
4969
4970         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4971                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4972                 return -EINVAL;
4973         }
4974
4975         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4976         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4977         if (ret < 0)
4978                 return ret;
4979
4980         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4981                                          &filter_5tuple);
4982         if (filter == NULL) {
4983                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4984                 return -ENOENT;
4985         }
4986         ntuple_filter->queue = filter->queue;
4987         return 0;
4988 }
4989
4990 /*
4991  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4992  * @dev: pointer to rte_eth_dev structure
4993  * @filter_op:operation will be taken.
4994  * @arg: a pointer to specific structure corresponding to the filter_op
4995  *
4996  * @return
4997  *    - On success, zero.
4998  *    - On failure, a negative value.
4999  */
5000 static int
5001 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5002                                 enum rte_filter_op filter_op,
5003                                 void *arg)
5004 {
5005         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5006         int ret;
5007
5008         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5009
5010         if (filter_op == RTE_ETH_FILTER_NOP)
5011                 return 0;
5012
5013         if (arg == NULL) {
5014                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5015                             filter_op);
5016                 return -EINVAL;
5017         }
5018
5019         switch (filter_op) {
5020         case RTE_ETH_FILTER_ADD:
5021                 ret = ixgbe_add_del_ntuple_filter(dev,
5022                         (struct rte_eth_ntuple_filter *)arg,
5023                         TRUE);
5024                 break;
5025         case RTE_ETH_FILTER_DELETE:
5026                 ret = ixgbe_add_del_ntuple_filter(dev,
5027                         (struct rte_eth_ntuple_filter *)arg,
5028                         FALSE);
5029                 break;
5030         case RTE_ETH_FILTER_GET:
5031                 ret = ixgbe_get_ntuple_filter(dev,
5032                         (struct rte_eth_ntuple_filter *)arg);
5033                 break;
5034         default:
5035                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5036                 ret = -EINVAL;
5037                 break;
5038         }
5039         return ret;
5040 }
5041
5042 static inline int
5043 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5044                         uint16_t ethertype)
5045 {
5046         int i;
5047
5048         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5049                 if (filter_info->ethertype_filters[i] == ethertype &&
5050                     (filter_info->ethertype_mask & (1 << i)))
5051                         return i;
5052         }
5053         return -1;
5054 }
5055
5056 static inline int
5057 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5058                         uint16_t ethertype)
5059 {
5060         int i;
5061
5062         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5063                 if (!(filter_info->ethertype_mask & (1 << i))) {
5064                         filter_info->ethertype_mask |= 1 << i;
5065                         filter_info->ethertype_filters[i] = ethertype;
5066                         return i;
5067                 }
5068         }
5069         return -1;
5070 }
5071
5072 static inline int
5073 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5074                         uint8_t idx)
5075 {
5076         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5077                 return -1;
5078         filter_info->ethertype_mask &= ~(1 << idx);
5079         filter_info->ethertype_filters[idx] = 0;
5080         return idx;
5081 }
5082
5083 static int
5084 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5085                         struct rte_eth_ethertype_filter *filter,
5086                         bool add)
5087 {
5088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5089         struct ixgbe_filter_info *filter_info =
5090                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5091         uint32_t etqf = 0;
5092         uint32_t etqs = 0;
5093         int ret;
5094
5095         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5096                 return -EINVAL;
5097
5098         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5099                 filter->ether_type == ETHER_TYPE_IPv6) {
5100                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5101                         " ethertype filter.", filter->ether_type);
5102                 return -EINVAL;
5103         }
5104
5105         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5106                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5107                 return -EINVAL;
5108         }
5109         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5110                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5111                 return -EINVAL;
5112         }
5113
5114         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5115         if (ret >= 0 && add) {
5116                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5117                             filter->ether_type);
5118                 return -EEXIST;
5119         }
5120         if (ret < 0 && !add) {
5121                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5122                             filter->ether_type);
5123                 return -ENOENT;
5124         }
5125
5126         if (add) {
5127                 ret = ixgbe_ethertype_filter_insert(filter_info,
5128                         filter->ether_type);
5129                 if (ret < 0) {
5130                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5131                         return -ENOSYS;
5132                 }
5133                 etqf = IXGBE_ETQF_FILTER_EN;
5134                 etqf |= (uint32_t)filter->ether_type;
5135                 etqs |= (uint32_t)((filter->queue <<
5136                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5137                                     IXGBE_ETQS_RX_QUEUE);
5138                 etqs |= IXGBE_ETQS_QUEUE_EN;
5139         } else {
5140                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5141                 if (ret < 0)
5142                         return -ENOSYS;
5143         }
5144         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5145         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5146         IXGBE_WRITE_FLUSH(hw);
5147
5148         return 0;
5149 }
5150
5151 static int
5152 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5153                         struct rte_eth_ethertype_filter *filter)
5154 {
5155         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5156         struct ixgbe_filter_info *filter_info =
5157                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5158         uint32_t etqf, etqs;
5159         int ret;
5160
5161         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5162         if (ret < 0) {
5163                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5164                             filter->ether_type);
5165                 return -ENOENT;
5166         }
5167
5168         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5169         if (etqf & IXGBE_ETQF_FILTER_EN) {
5170                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5171                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5172                 filter->flags = 0;
5173                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5174                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5175                 return 0;
5176         }
5177         return -ENOENT;
5178 }
5179
5180 /*
5181  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5182  * @dev: pointer to rte_eth_dev structure
5183  * @filter_op:operation will be taken.
5184  * @arg: a pointer to specific structure corresponding to the filter_op
5185  */
5186 static int
5187 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5188                                 enum rte_filter_op filter_op,
5189                                 void *arg)
5190 {
5191         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5192         int ret;
5193
5194         MAC_TYPE_FILTER_SUP(hw->mac.type);
5195
5196         if (filter_op == RTE_ETH_FILTER_NOP)
5197                 return 0;
5198
5199         if (arg == NULL) {
5200                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5201                             filter_op);
5202                 return -EINVAL;
5203         }
5204
5205         switch (filter_op) {
5206         case RTE_ETH_FILTER_ADD:
5207                 ret = ixgbe_add_del_ethertype_filter(dev,
5208                         (struct rte_eth_ethertype_filter *)arg,
5209                         TRUE);
5210                 break;
5211         case RTE_ETH_FILTER_DELETE:
5212                 ret = ixgbe_add_del_ethertype_filter(dev,
5213                         (struct rte_eth_ethertype_filter *)arg,
5214                         FALSE);
5215                 break;
5216         case RTE_ETH_FILTER_GET:
5217                 ret = ixgbe_get_ethertype_filter(dev,
5218                         (struct rte_eth_ethertype_filter *)arg);
5219                 break;
5220         default:
5221                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5222                 ret = -EINVAL;
5223                 break;
5224         }
5225         return ret;
5226 }
5227
5228 static int
5229 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5230                      enum rte_filter_type filter_type,
5231                      enum rte_filter_op filter_op,
5232                      void *arg)
5233 {
5234         int ret = -EINVAL;
5235
5236         switch (filter_type) {
5237         case RTE_ETH_FILTER_NTUPLE:
5238                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5239                 break;
5240         case RTE_ETH_FILTER_ETHERTYPE:
5241                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5242                 break;
5243         case RTE_ETH_FILTER_SYN:
5244                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5245                 break;
5246         case RTE_ETH_FILTER_FDIR:
5247                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5248                 break;
5249         default:
5250                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5251                                                         filter_type);
5252                 break;
5253         }
5254
5255         return ret;
5256 }
5257
5258 static u8 *
5259 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5260                         u8 **mc_addr_ptr, u32 *vmdq)
5261 {
5262         u8 *mc_addr;
5263
5264         *vmdq = 0;
5265         mc_addr = *mc_addr_ptr;
5266         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5267         return mc_addr;
5268 }
5269
5270 static int
5271 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5272                           struct ether_addr *mc_addr_set,
5273                           uint32_t nb_mc_addr)
5274 {
5275         struct ixgbe_hw *hw;
5276         u8 *mc_addr_list;
5277
5278         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5279         mc_addr_list = (u8 *)mc_addr_set;
5280         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5281                                          ixgbe_dev_addr_list_itr, TRUE);
5282 }
5283
5284 static int
5285 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5286 {
5287         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5288         uint32_t tsync_ctl;
5289         uint32_t tsauxc;
5290
5291         /* Enable system time for platforms where it isn't on by default. */
5292         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5293         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5294         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5295
5296         /* Start incrementing the register used to timestamp PTP packets. */
5297         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5298
5299         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5300         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5301                         (ETHER_TYPE_1588 |
5302                          IXGBE_ETQF_FILTER_EN |
5303                          IXGBE_ETQF_1588));
5304
5305         /* Enable timestamping of received PTP packets. */
5306         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5307         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5308         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5309
5310         /* Enable timestamping of transmitted PTP packets. */
5311         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5312         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5313         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5314
5315         return 0;
5316 }
5317
5318 static int
5319 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5320 {
5321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5322         uint32_t tsync_ctl;
5323
5324         /* Disable timestamping of transmitted PTP packets. */
5325         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5326         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5327         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5328
5329         /* Disable timestamping of received PTP packets. */
5330         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5331         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5332         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5333
5334         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5335         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5336
5337         /* Stop incrementating the System Time registers. */
5338         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5339
5340         return 0;
5341 }
5342
5343 static int
5344 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5345                                  struct timespec *timestamp,
5346                                  uint32_t flags __rte_unused)
5347 {
5348         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5349         uint32_t tsync_rxctl;
5350         uint32_t rx_stmpl;
5351         uint32_t rx_stmph;
5352
5353         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5354         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5355                 return -EINVAL;
5356
5357         rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5358         rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5359
5360         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5361         timestamp->tv_nsec = 0;
5362
5363         return  0;
5364 }
5365
5366 static int
5367 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5368                                  struct timespec *timestamp)
5369 {
5370         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5371         uint32_t tsync_txctl;
5372         uint32_t tx_stmpl;
5373         uint32_t tx_stmph;
5374
5375         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5376         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5377                 return -EINVAL;
5378
5379         tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5380         tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5381
5382         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5383         timestamp->tv_nsec = 0;
5384
5385         return  0;
5386 }
5387
5388 static int
5389 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5390 {
5391         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5392         int count = 0;
5393         int g_ind = 0;
5394         const struct reg_info *reg_group;
5395         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5396                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5397
5398         while ((reg_group = reg_set[g_ind++]))
5399                 count += ixgbe_regs_group_count(reg_group);
5400
5401         return count;
5402 }
5403
5404 static int
5405 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5406 {
5407         int count = 0;
5408         int g_ind = 0;
5409         const struct reg_info *reg_group;
5410
5411         while ((reg_group = ixgbevf_regs[g_ind++]))
5412                 count += ixgbe_regs_group_count(reg_group);
5413
5414         return count;
5415 }
5416
5417 static int
5418 ixgbe_get_regs(struct rte_eth_dev *dev,
5419               struct rte_dev_reg_info *regs)
5420 {
5421         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5422         uint32_t *data = regs->data;
5423         int g_ind = 0;
5424         int count = 0;
5425         const struct reg_info *reg_group;
5426         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5427                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5428
5429         /* Support only full register dump */
5430         if ((regs->length == 0) ||
5431             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5432                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5433                         hw->device_id;
5434                 while ((reg_group = reg_set[g_ind++]))
5435                         count += ixgbe_read_regs_group(dev, &data[count],
5436                                 reg_group);
5437                 return 0;
5438         }
5439
5440         return -ENOTSUP;
5441 }
5442
5443 static int
5444 ixgbevf_get_regs(struct rte_eth_dev *dev,
5445                 struct rte_dev_reg_info *regs)
5446 {
5447         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5448         uint32_t *data = regs->data;
5449         int g_ind = 0;
5450         int count = 0;
5451         const struct reg_info *reg_group;
5452
5453         /* Support only full register dump */
5454         if ((regs->length == 0) ||
5455             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5456                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5457                         hw->device_id;
5458                 while ((reg_group = ixgbevf_regs[g_ind++]))
5459                         count += ixgbe_read_regs_group(dev, &data[count],
5460                                                       reg_group);
5461                 return 0;
5462         }
5463
5464         return -ENOTSUP;
5465 }
5466
5467 static int
5468 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5469 {
5470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5471
5472         /* Return unit is byte count */
5473         return hw->eeprom.word_size * 2;
5474 }
5475
5476 static int
5477 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5478                 struct rte_dev_eeprom_info *in_eeprom)
5479 {
5480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5481         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5482         uint16_t *data = in_eeprom->data;
5483         int first, length;
5484
5485         first = in_eeprom->offset >> 1;
5486         length = in_eeprom->length >> 1;
5487         if ((first >= hw->eeprom.word_size) ||
5488             ((first + length) >= hw->eeprom.word_size))
5489                 return -EINVAL;
5490
5491         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5492
5493         return eeprom->ops.read_buffer(hw, first, length, data);
5494 }
5495
5496 static int
5497 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5498                 struct rte_dev_eeprom_info *in_eeprom)
5499 {
5500         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5501         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5502         uint16_t *data = in_eeprom->data;
5503         int first, length;
5504
5505         first = in_eeprom->offset >> 1;
5506         length = in_eeprom->length >> 1;
5507         if ((first >= hw->eeprom.word_size) ||
5508             ((first + length) >= hw->eeprom.word_size))
5509                 return -EINVAL;
5510
5511         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5512
5513         return eeprom->ops.write_buffer(hw,  first, length, data);
5514 }
5515
5516 static struct rte_driver rte_ixgbe_driver = {
5517         .type = PMD_PDEV,
5518         .init = rte_ixgbe_pmd_init,
5519 };
5520
5521 static struct rte_driver rte_ixgbevf_driver = {
5522         .type = PMD_PDEV,
5523         .init = rte_ixgbevf_pmd_init,
5524 };
5525
5526 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
5527 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);