drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64 #include <rte_hash_crc.h>
  65
  66 #include "ixgbe_logs.h"
  67 #include "base/ixgbe_api.h"
  68 #include "base/ixgbe_vf.h"
  69 #include "base/ixgbe_common.h"
  70 #include "ixgbe_ethdev.h"
  71 #include "ixgbe_bypass.h"
  72 #include "ixgbe_rxtx.h"
  73 #include "base/ixgbe_type.h"
  74 #include "base/ixgbe_phy.h"
  75 #include "ixgbe_regs.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 158 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 168 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 178                                 int wait_to_complete);
 179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 180                                 struct rte_eth_stats *stats);
 181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 182                                 struct rte_eth_xstat *xstats, unsigned n);
 183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 184                                   struct rte_eth_xstat *xstats, unsigned n);
 185 static int
 186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 187                 uint64_t *values, unsigned int n);
 188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 190 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names,
 192         __rte_unused unsigned int size);
 193 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 195 static int ixgbe_dev_xstats_get_names_by_id(
 196         __rte_unused struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names,
 198         const uint64_t *ids,
 199         unsigned int limit);
 200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 201                                              uint16_t queue_id,
 202                                              uint8_t stat_idx,
 203                                              uint8_t is_rx);
 204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 205                                  size_t fw_size);
 206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_dev_info *dev_info);
 208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 210                                  struct rte_eth_dev_info *dev_info);
 211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 212
 213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 214                 uint16_t vlan_id, int on);
 215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 216                                enum rte_vlan_type vlan_type,
 217                                uint16_t tpid_id);
 218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 219                 uint16_t queue, bool on);
 220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 221                 int on);
 222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 227
 228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 233                                struct rte_eth_fc_conf *fc_conf);
 234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 235                 struct rte_eth_pfc_conf *pfc_conf);
 236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 237                         struct rte_eth_rss_reta_entry64 *reta_conf,
 238                         uint16_t reta_size);
 239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 240                         struct rte_eth_rss_reta_entry64 *reta_conf,
 241                         uint16_t reta_size);
 242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 248                                       struct rte_intr_handle *handle);
 249 static void ixgbe_dev_interrupt_handler(void *param);
 250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 251 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 252                 uint32_t index, uint32_t pool);
 253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 255                                            struct ether_addr *mac_addr);
 256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 257 static bool is_device_supported(struct rte_eth_dev *dev,
 258                                 struct rte_pci_driver *drv);
 259
 260 /* For Virtual Function support */
 261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 263 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 264 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 267 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 268 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 269 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 270                 struct rte_eth_stats *stats);
 271 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 272 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 273                 uint16_t vlan_id, int on);
 274 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 275                 uint16_t queue, int on);
 276 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 277 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 278 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 279                                             uint16_t queue_id);
 280 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 281                                              uint16_t queue_id);
 282 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 283                                  uint8_t queue, uint8_t msix_vector);
 284 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 285 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 286 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 287
 288 /* For Eth VMDQ APIs support */
 289 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 290                 ether_addr * mac_addr, uint8_t on);
 291 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 292 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 293                 struct rte_eth_mirror_conf *mirror_conf,
 294                 uint8_t rule_id, uint8_t on);
 295 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 296                 uint8_t rule_id);
 297 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 298                                           uint16_t queue_id);
 299 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 300                                            uint16_t queue_id);
 301 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 302                                uint8_t queue, uint8_t msix_vector);
 303 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 304
 305 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 306                 uint16_t queue_idx, uint16_t tx_rate);
 307
 308 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 309                                  struct ether_addr *mac_addr,
 310                                  uint32_t index, uint32_t pool);
 311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 313                                              struct ether_addr *mac_addr);
 314 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 315                         struct rte_eth_syn_filter *filter);
 316 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 317                         enum rte_filter_op filter_op,
 318                         void *arg);
 319 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 322                         struct ixgbe_5tuple_filter *filter);
 323 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 327                         struct rte_eth_ntuple_filter *filter);
 328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 332                         struct rte_eth_ethertype_filter *filter);
 333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 334                      enum rte_filter_type filter_type,
 335                      enum rte_filter_op filter_op,
 336                      void *arg);
 337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 338
 339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 340                                       struct ether_addr *mc_addr_set,
 341                                       uint32_t nb_mc_addr);
 342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 343                                    struct rte_eth_dcb_info *dcb_info);
 344
 345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 347                             struct rte_dev_reg_info *regs);
 348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353
 354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 356                                 struct rte_dev_reg_info *regs);
 357
 358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 361                                             struct timespec *timestamp,
 362                                             uint32_t flags);
 363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 364                                             struct timespec *timestamp);
 365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 367                                    struct timespec *timestamp);
 368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 369                                    const struct timespec *timestamp);
 370 static void ixgbevf_dev_interrupt_handler(void *param);
 371
 372 static int ixgbe_dev_l2_tunnel_eth_type_conf
 373         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 374 static int ixgbe_dev_l2_tunnel_offload_set
 375         (struct rte_eth_dev *dev,
 376          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 377          uint32_t mask,
 378          uint8_t en);
 379 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 380                                              enum rte_filter_op filter_op,
 381                                              void *arg);
 382
 383 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 384                                          struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 386                                          struct rte_eth_udp_tunnel *udp_tunnel);
 387 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 388 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 389
 390 /*
 391  * Define VF Stats MACRO for Non "cleared on read" register
 392  */
 393 #define UPDATE_VF_STAT(reg, last, cur)                          \
 394 {                                                               \
 395         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 396         cur += (latest - last) & UINT_MAX;                      \
 397         last = latest;                                          \
 398 }
 399
 400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 401 {                                                                \
 402         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 403         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 404         u64 latest = ((new_msb << 32) | new_lsb);                \
 405         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 406         last = latest;                                           \
 407 }
 408
 409 #define IXGBE_SET_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] |= 1 << bit;\
 413         } while (0)
 414
 415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (h)->bitmap[idx] &= ~(1 << bit);\
 419         } while (0)
 420
 421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 422                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 423                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 424                 (r) = (h)->bitmap[idx] >> bit & 1;\
 425         } while (0)
 426
 427 /*
 428  * The set of PCI devices this driver supports
 429  */
 430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 484 #ifdef RTE_NIC_BYPASS
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 486 #endif
 487         { .vendor_id = 0, /* sentinel */ },
 488 };
 489
 490 /*
 491  * The set of PCI devices this driver supports (for 82599 VF)
 492  */
 493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 504         { .vendor_id = 0, /* sentinel */ },
 505 };
 506
 507 static const struct rte_eth_desc_lim rx_desc_lim = {
 508         .nb_max = IXGBE_MAX_RING_DESC,
 509         .nb_min = IXGBE_MIN_RING_DESC,
 510         .nb_align = IXGBE_RXD_ALIGN,
 511 };
 512
 513 static const struct rte_eth_desc_lim tx_desc_lim = {
 514         .nb_max = IXGBE_MAX_RING_DESC,
 515         .nb_min = IXGBE_MIN_RING_DESC,
 516         .nb_align = IXGBE_TXD_ALIGN,
 517         .nb_seg_max = IXGBE_TX_MAX_SEG,
 518         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 519 };
 520
 521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 522         .dev_configure        = ixgbe_dev_configure,
 523         .dev_start            = ixgbe_dev_start,
 524         .dev_stop             = ixgbe_dev_stop,
 525         .dev_set_link_up    = ixgbe_dev_set_link_up,
 526         .dev_set_link_down  = ixgbe_dev_set_link_down,
 527         .dev_close            = ixgbe_dev_close,
 528         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 529         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 530         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 531         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 532         .link_update          = ixgbe_dev_link_update,
 533         .stats_get            = ixgbe_dev_stats_get,
 534         .xstats_get           = ixgbe_dev_xstats_get,
 535         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 536         .stats_reset          = ixgbe_dev_stats_reset,
 537         .xstats_reset         = ixgbe_dev_xstats_reset,
 538         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 539         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 540         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 541         .fw_version_get       = ixgbe_fw_version_get,
 542         .dev_infos_get        = ixgbe_dev_info_get,
 543         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 544         .mtu_set              = ixgbe_dev_mtu_set,
 545         .vlan_filter_set      = ixgbe_vlan_filter_set,
 546         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 547         .vlan_offload_set     = ixgbe_vlan_offload_set,
 548         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 549         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 550         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 551         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 552         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 553         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 554         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 555         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 556         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 557         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 558         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 559         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 560         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 561         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 562         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 563         .dev_led_on           = ixgbe_dev_led_on,
 564         .dev_led_off          = ixgbe_dev_led_off,
 565         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 566         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 567         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 568         .mac_addr_add         = ixgbe_add_rar,
 569         .mac_addr_remove      = ixgbe_remove_rar,
 570         .mac_addr_set         = ixgbe_set_default_mac_addr,
 571         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 572         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 573         .mirror_rule_set      = ixgbe_mirror_rule_set,
 574         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 575         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 576         .reta_update          = ixgbe_dev_rss_reta_update,
 577         .reta_query           = ixgbe_dev_rss_reta_query,
 578 #ifdef RTE_NIC_BYPASS
 579         .bypass_init          = ixgbe_bypass_init,
 580         .bypass_state_set     = ixgbe_bypass_state_store,
 581         .bypass_state_show    = ixgbe_bypass_state_show,
 582         .bypass_event_set     = ixgbe_bypass_event_store,
 583         .bypass_event_show    = ixgbe_bypass_event_show,
 584         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 585         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 586         .bypass_ver_show      = ixgbe_bypass_ver_show,
 587         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 588 #endif /* RTE_NIC_BYPASS */
 589         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 590         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 591         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 592         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 593         .rxq_info_get         = ixgbe_rxq_info_get,
 594         .txq_info_get         = ixgbe_txq_info_get,
 595         .timesync_enable      = ixgbe_timesync_enable,
 596         .timesync_disable     = ixgbe_timesync_disable,
 597         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 598         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 599         .get_reg              = ixgbe_get_regs,
 600         .get_eeprom_length    = ixgbe_get_eeprom_length,
 601         .get_eeprom           = ixgbe_get_eeprom,
 602         .set_eeprom           = ixgbe_set_eeprom,
 603         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 604         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 605         .timesync_read_time   = ixgbe_timesync_read_time,
 606         .timesync_write_time  = ixgbe_timesync_write_time,
 607         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 608         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 609         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 610         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 611 };
 612
 613 /*
 614  * dev_ops for virtual function, bare necessities for basic vf
 615  * operation have been implemented
 616  */
 617 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 618         .dev_configure        = ixgbevf_dev_configure,
 619         .dev_start            = ixgbevf_dev_start,
 620         .dev_stop             = ixgbevf_dev_stop,
 621         .link_update          = ixgbe_dev_link_update,
 622         .stats_get            = ixgbevf_dev_stats_get,
 623         .xstats_get           = ixgbevf_dev_xstats_get,
 624         .stats_reset          = ixgbevf_dev_stats_reset,
 625         .xstats_reset         = ixgbevf_dev_stats_reset,
 626         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 627         .dev_close            = ixgbevf_dev_close,
 628         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 629         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 630         .dev_infos_get        = ixgbevf_dev_info_get,
 631         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 632         .mtu_set              = ixgbevf_dev_set_mtu,
 633         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 634         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 635         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 636         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 637         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 638         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 639         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 640         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 641         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 642         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 643         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 644         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 645         .mac_addr_add         = ixgbevf_add_mac_addr,
 646         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 647         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 648         .rxq_info_get         = ixgbe_rxq_info_get,
 649         .txq_info_get         = ixgbe_txq_info_get,
 650         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 651         .get_reg              = ixgbevf_get_regs,
 652         .reta_update          = ixgbe_dev_rss_reta_update,
 653         .reta_query           = ixgbe_dev_rss_reta_query,
 654         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 655         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 656 };
 657
 658 /* store statistics names and its offset in stats structure */
 659 struct rte_ixgbe_xstats_name_off {
 660         char name[RTE_ETH_XSTATS_NAME_SIZE];
 661         unsigned offset;
 662 };
 663
 664 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 665         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 666         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 667         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 668         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 669         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 670         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 671         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 672         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 673         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 674         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 675         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 676         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 677         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 678         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 679         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 680                 prc1023)},
 681         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 682                 prc1522)},
 683         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 684         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 685         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 686         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 687         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 688         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 689         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 690         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 691         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 692         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 693         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 694         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 695         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 696         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 697         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 698         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 699         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 700                 ptc1023)},
 701         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 702                 ptc1522)},
 703         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 704         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 705         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 706         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 707
 708         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 709                 fdirustat_add)},
 710         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirustat_remove)},
 712         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 713                 fdirfstat_fadd)},
 714         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 715                 fdirfstat_fremove)},
 716         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 717                 fdirmatch)},
 718         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 719                 fdirmiss)},
 720
 721         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 722         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 723         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 724                 fclast)},
 725         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 726         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 727         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 728         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 729         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 730                 fcoe_noddp)},
 731         {"rx_fcoe_no_direct_data_placement_ext_buff",
 732                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 733
 734         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 735                 lxontxc)},
 736         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxonrxc)},
 738         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxofftxc)},
 740         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxoffrxc)},
 742         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 743 };
 744
 745 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 746                            sizeof(rte_ixgbe_stats_strings[0]))
 747
 748 /* MACsec statistics */
 749 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 750         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 751                 out_pkts_untagged)},
 752         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 753                 out_pkts_encrypted)},
 754         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 755                 out_pkts_protected)},
 756         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 757                 out_octets_encrypted)},
 758         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 759                 out_octets_protected)},
 760         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_untagged)},
 762         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_badtag)},
 764         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_nosci)},
 766         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_unknownsci)},
 768         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 769                 in_octets_decrypted)},
 770         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 771                 in_octets_validated)},
 772         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_unchecked)},
 774         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_delayed)},
 776         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_late)},
 778         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_ok)},
 780         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 781                 in_pkts_invalid)},
 782         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 783                 in_pkts_notvalid)},
 784         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 785                 in_pkts_unusedsa)},
 786         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 787                 in_pkts_notusingsa)},
 788 };
 789
 790 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 791                            sizeof(rte_ixgbe_macsec_strings[0]))
 792
 793 /* Per-queue statistics */
 794 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 795         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 796         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 797         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 798         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 799 };
 800
 801 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 802                            sizeof(rte_ixgbe_rxq_strings[0]))
 803 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 804
 805 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 806         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 807         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 808         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 809                 pxon2offc)},
 810 };
 811
 812 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 813                            sizeof(rte_ixgbe_txq_strings[0]))
 814 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 815
 816 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 817         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 818 };
 819
 820 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 821                 sizeof(rte_ixgbevf_stats_strings[0]))
 822
 823 /**
 824  * Atomically reads the link status information from global
 825  * structure rte_eth_dev.
 826  *
 827  * @param dev
 828  *   - Pointer to the structure rte_eth_dev to read from.
 829  *   - Pointer to the buffer to be saved with the link status.
 830  *
 831  * @return
 832  *   - On success, zero.
 833  *   - On failure, negative value.
 834  */
 835 static inline int
 836 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 837                                 struct rte_eth_link *link)
 838 {
 839         struct rte_eth_link *dst = link;
 840         struct rte_eth_link *src = &(dev->data->dev_link);
 841
 842         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 843                                         *(uint64_t *)src) == 0)
 844                 return -1;
 845
 846         return 0;
 847 }
 848
 849 /**
 850  * Atomically writes the link status information into global
 851  * structure rte_eth_dev.
 852  *
 853  * @param dev
 854  *   - Pointer to the structure rte_eth_dev to read from.
 855  *   - Pointer to the buffer to be saved with the link status.
 856  *
 857  * @return
 858  *   - On success, zero.
 859  *   - On failure, negative value.
 860  */
 861 static inline int
 862 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 863                                 struct rte_eth_link *link)
 864 {
 865         struct rte_eth_link *dst = &(dev->data->dev_link);
 866         struct rte_eth_link *src = link;
 867
 868         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 869                                         *(uint64_t *)src) == 0)
 870                 return -1;
 871
 872         return 0;
 873 }
 874
 875 /*
 876  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 877  */
 878 static inline int
 879 ixgbe_is_sfp(struct ixgbe_hw *hw)
 880 {
 881         switch (hw->phy.type) {
 882         case ixgbe_phy_sfp_avago:
 883         case ixgbe_phy_sfp_ftl:
 884         case ixgbe_phy_sfp_intel:
 885         case ixgbe_phy_sfp_unknown:
 886         case ixgbe_phy_sfp_passive_tyco:
 887         case ixgbe_phy_sfp_passive_unknown:
 888                 return 1;
 889         default:
 890                 return 0;
 891         }
 892 }
 893
 894 static inline int32_t
 895 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 896 {
 897         uint32_t ctrl_ext;
 898         int32_t status;
 899
 900         status = ixgbe_reset_hw(hw);
 901
 902         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 903         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 904         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 905         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 906         IXGBE_WRITE_FLUSH(hw);
 907
 908         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 909                 status = IXGBE_SUCCESS;
 910         return status;
 911 }
 912
 913 static inline void
 914 ixgbe_enable_intr(struct rte_eth_dev *dev)
 915 {
 916         struct ixgbe_interrupt *intr =
 917                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 918         struct ixgbe_hw *hw =
 919                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 920
 921         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 922         IXGBE_WRITE_FLUSH(hw);
 923 }
 924
 925 /*
 926  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 927  */
 928 static void
 929 ixgbe_disable_intr(struct ixgbe_hw *hw)
 930 {
 931         PMD_INIT_FUNC_TRACE();
 932
 933         if (hw->mac.type == ixgbe_mac_82598EB) {
 934                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 935         } else {
 936                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 937                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 938                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 939         }
 940         IXGBE_WRITE_FLUSH(hw);
 941 }
 942
 943 /*
 944  * This function resets queue statistics mapping registers.
 945  * From Niantic datasheet, Initialization of Statistics section:
 946  * "...if software requires the queue counters, the RQSMR and TQSM registers
 947  * must be re-programmed following a device reset.
 948  */
 949 static void
 950 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 951 {
 952         uint32_t i;
 953
 954         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 955                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 956                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 957         }
 958 }
 959
 960
 961 static int
 962 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 963                                   uint16_t queue_id,
 964                                   uint8_t stat_idx,
 965                                   uint8_t is_rx)
 966 {
 967 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 968 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 969 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 970
 971         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 972         struct ixgbe_stat_mapping_registers *stat_mappings =
 973                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 974         uint32_t qsmr_mask = 0;
 975         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 976         uint32_t q_map;
 977         uint8_t n, offset;
 978
 979         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 980                 (hw->mac.type != ixgbe_mac_X540) &&
 981                 (hw->mac.type != ixgbe_mac_X550) &&
 982                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 983                 (hw->mac.type != ixgbe_mac_X550EM_a))
 984                 return -ENOSYS;
 985
 986         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 987                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 988                      queue_id, stat_idx);
 989
 990         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 991         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 992                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 993                 return -EIO;
 994         }
 995         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 996
 997         /* Now clear any previous stat_idx set */
 998         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 999         if (!is_rx)
1000                 stat_mappings->tqsm[n] &= ~clearing_mask;
1001         else
1002                 stat_mappings->rqsmr[n] &= ~clearing_mask;
1003
1004         q_map = (uint32_t)stat_idx;
1005         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1006         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1007         if (!is_rx)
1008                 stat_mappings->tqsm[n] |= qsmr_mask;
1009         else
1010                 stat_mappings->rqsmr[n] |= qsmr_mask;
1011
1012         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1013                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1014                      queue_id, stat_idx);
1015         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1016                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1017
1018         /* Now write the mapping in the appropriate register */
1019         if (is_rx) {
1020                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1021                              stat_mappings->rqsmr[n], n);
1022                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1023         } else {
1024                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1025                              stat_mappings->tqsm[n], n);
1026                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1027         }
1028         return 0;
1029 }
1030
1031 static void
1032 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1033 {
1034         struct ixgbe_stat_mapping_registers *stat_mappings =
1035                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         int i;
1038
1039         /* write whatever was in stat mapping table to the NIC */
1040         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1041                 /* rx */
1042                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1043
1044                 /* tx */
1045                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1046         }
1047 }
1048
1049 static void
1050 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1051 {
1052         uint8_t i;
1053         struct ixgbe_dcb_tc_config *tc;
1054         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1055
1056         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1057         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1058         for (i = 0; i < dcb_max_tc; i++) {
1059                 tc = &dcb_config->tc_config[i];
1060                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1061                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1062                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1063                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1064                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1065                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1066                 tc->pfc = ixgbe_dcb_pfc_disabled;
1067         }
1068
1069         /* Initialize default user to priority mapping, UPx->TC0 */
1070         tc = &dcb_config->tc_config[0];
1071         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1072         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1073         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1074                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1075                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1076         }
1077         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1078         dcb_config->pfc_mode_enable = false;
1079         dcb_config->vt_mode = true;
1080         dcb_config->round_robin_enable = false;
1081         /* support all DCB capabilities in 82599 */
1082         dcb_config->support.capabilities = 0xFF;
1083
1084         /*we only support 4 Tcs for X540, X550 */
1085         if (hw->mac.type == ixgbe_mac_X540 ||
1086                 hw->mac.type == ixgbe_mac_X550 ||
1087                 hw->mac.type == ixgbe_mac_X550EM_x ||
1088                 hw->mac.type == ixgbe_mac_X550EM_a) {
1089                 dcb_config->num_tcs.pg_tcs = 4;
1090                 dcb_config->num_tcs.pfc_tcs = 4;
1091         }
1092 }
1093
1094 /*
1095  * Ensure that all locks are released before first NVM or PHY access
1096  */
1097 static void
1098 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1099 {
1100         uint16_t mask;
1101
1102         /*
1103          * Phy lock should not fail in this early stage. If this is the case,
1104          * it is due to an improper exit of the application.
1105          * So force the release of the faulty lock. Release of common lock
1106          * is done automatically by swfw_sync function.
1107          */
1108         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1109         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1111         }
1112         ixgbe_release_swfw_semaphore(hw, mask);
1113
1114         /*
1115          * These ones are more tricky since they are common to all ports; but
1116          * swfw_sync retries last long enough (1s) to be almost sure that if
1117          * lock can not be taken it is due to an improper lock of the
1118          * semaphore.
1119          */
1120         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1121         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1122                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1123         }
1124         ixgbe_release_swfw_semaphore(hw, mask);
1125 }
1126
1127 /*
1128  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1129  * It returns 0 on success.
1130  */
1131 static int
1132 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1133 {
1134         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1135         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1136         struct ixgbe_hw *hw =
1137                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1138         struct ixgbe_vfta *shadow_vfta =
1139                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1140         struct ixgbe_hwstrip *hwstrip =
1141                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1142         struct ixgbe_dcb_config *dcb_config =
1143                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1144         struct ixgbe_filter_info *filter_info =
1145                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1146         struct ixgbe_bw_conf *bw_conf =
1147                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1148         uint32_t ctrl_ext;
1149         uint16_t csum;
1150         int diag, i;
1151
1152         PMD_INIT_FUNC_TRACE();
1153
1154         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1155         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1156         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1157         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1158
1159         /*
1160          * For secondary processes, we don't initialise any further as primary
1161          * has already done this work. Only check we don't need a different
1162          * RX and TX function.
1163          */
1164         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1165                 struct ixgbe_tx_queue *txq;
1166                 /* TX queue function in primary, set by last queue initialized
1167                  * Tx queue may not initialized by primary process
1168                  */
1169                 if (eth_dev->data->tx_queues) {
1170                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1171                         ixgbe_set_tx_function(eth_dev, txq);
1172                 } else {
1173                         /* Use default TX function if we get here */
1174                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1175                                      "Using default TX function.");
1176                 }
1177
1178                 ixgbe_set_rx_function(eth_dev);
1179
1180                 return 0;
1181         }
1182
1183         rte_eth_copy_pci_info(eth_dev, pci_dev);
1184         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1185
1186         /* Vendor and Device ID need to be set before init of shared code */
1187         hw->device_id = pci_dev->id.device_id;
1188         hw->vendor_id = pci_dev->id.vendor_id;
1189         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1190         hw->allow_unsupported_sfp = 1;
1191
1192         /* Initialize the shared code (base driver) */
1193 #ifdef RTE_NIC_BYPASS
1194         diag = ixgbe_bypass_init_shared_code(hw);
1195 #else
1196         diag = ixgbe_init_shared_code(hw);
1197 #endif /* RTE_NIC_BYPASS */
1198
1199         if (diag != IXGBE_SUCCESS) {
1200                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1201                 return -EIO;
1202         }
1203
1204         /* pick up the PCI bus settings for reporting later */
1205         ixgbe_get_bus_info(hw);
1206
1207         /* Unlock any pending hardware semaphore */
1208         ixgbe_swfw_lock_reset(hw);
1209
1210         /* Initialize DCB configuration*/
1211         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1212         ixgbe_dcb_init(hw, dcb_config);
1213         /* Get Hardware Flow Control setting */
1214         hw->fc.requested_mode = ixgbe_fc_full;
1215         hw->fc.current_mode = ixgbe_fc_full;
1216         hw->fc.pause_time = IXGBE_FC_PAUSE;
1217         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1218                 hw->fc.low_water[i] = IXGBE_FC_LO;
1219                 hw->fc.high_water[i] = IXGBE_FC_HI;
1220         }
1221         hw->fc.send_xon = 1;
1222
1223         /* Make sure we have a good EEPROM before we read from it */
1224         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1225         if (diag != IXGBE_SUCCESS) {
1226                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1227                 return -EIO;
1228         }
1229
1230 #ifdef RTE_NIC_BYPASS
1231         diag = ixgbe_bypass_init_hw(hw);
1232 #else
1233         diag = ixgbe_init_hw(hw);
1234 #endif /* RTE_NIC_BYPASS */
1235
1236         /*
1237          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1238          * is called too soon after the kernel driver unbinding/binding occurs.
1239          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1240          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1241          * also called. See ixgbe_identify_phy_82599(). The reason for the
1242          * failure is not known, and only occuts when virtualisation features
1243          * are disabled in the bios. A delay of 100ms  was found to be enough by
1244          * trial-and-error, and is doubled to be safe.
1245          */
1246         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1247                 rte_delay_ms(200);
1248                 diag = ixgbe_init_hw(hw);
1249         }
1250
1251         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1252                 diag = IXGBE_SUCCESS;
1253
1254         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1255                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1256                              "LOM.  Please be aware there may be issues associated "
1257                              "with your hardware.");
1258                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1259                              "please contact your Intel or hardware representative "
1260                              "who provided you with this hardware.");
1261         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1262                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1263         if (diag) {
1264                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1265                 return -EIO;
1266         }
1267
1268         /* Reset the hw statistics */
1269         ixgbe_dev_stats_reset(eth_dev);
1270
1271         /* disable interrupt */
1272         ixgbe_disable_intr(hw);
1273
1274         /* reset mappings for queue statistics hw counters*/
1275         ixgbe_reset_qstat_mappings(hw);
1276
1277         /* Allocate memory for storing MAC addresses */
1278         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1279                                                hw->mac.num_rar_entries, 0);
1280         if (eth_dev->data->mac_addrs == NULL) {
1281                 PMD_INIT_LOG(ERR,
1282                              "Failed to allocate %u bytes needed to store "
1283                              "MAC addresses",
1284                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1285                 return -ENOMEM;
1286         }
1287         /* Copy the permanent MAC address */
1288         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1289                         &eth_dev->data->mac_addrs[0]);
1290
1291         /* Allocate memory for storing hash filter MAC addresses */
1292         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1293                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1294         if (eth_dev->data->hash_mac_addrs == NULL) {
1295                 PMD_INIT_LOG(ERR,
1296                              "Failed to allocate %d bytes needed to store MAC addresses",
1297                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1298                 return -ENOMEM;
1299         }
1300
1301         /* initialize the vfta */
1302         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1303
1304         /* initialize the hw strip bitmap*/
1305         memset(hwstrip, 0, sizeof(*hwstrip));
1306
1307         /* initialize PF if max_vfs not zero */
1308         ixgbe_pf_host_init(eth_dev);
1309
1310         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1311         /* let hardware know driver is loaded */
1312         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1313         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1314         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1315         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1316         IXGBE_WRITE_FLUSH(hw);
1317
1318         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1319                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1320                              (int) hw->mac.type, (int) hw->phy.type,
1321                              (int) hw->phy.sfp_type);
1322         else
1323                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1324                              (int) hw->mac.type, (int) hw->phy.type);
1325
1326         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1327                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1328                      pci_dev->id.device_id);
1329
1330         rte_intr_callback_register(intr_handle,
1331                                    ixgbe_dev_interrupt_handler, eth_dev);
1332
1333         /* enable uio/vfio intr/eventfd mapping */
1334         rte_intr_enable(intr_handle);
1335
1336         /* enable support intr */
1337         ixgbe_enable_intr(eth_dev);
1338
1339         /* initialize filter info */
1340         memset(filter_info, 0,
1341                sizeof(struct ixgbe_filter_info));
1342
1343         /* initialize 5tuple filter list */
1344         TAILQ_INIT(&filter_info->fivetuple_list);
1345
1346         /* initialize flow director filter list & hash */
1347         ixgbe_fdir_filter_init(eth_dev);
1348
1349         /* initialize l2 tunnel filter list & hash */
1350         ixgbe_l2_tn_filter_init(eth_dev);
1351
1352         TAILQ_INIT(&filter_ntuple_list);
1353         TAILQ_INIT(&filter_ethertype_list);
1354         TAILQ_INIT(&filter_syn_list);
1355         TAILQ_INIT(&filter_fdir_list);
1356         TAILQ_INIT(&filter_l2_tunnel_list);
1357         TAILQ_INIT(&ixgbe_flow_list);
1358
1359         /* initialize bandwidth configuration info */
1360         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1361
1362         return 0;
1363 }
1364
1365 static int
1366 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1367 {
1368         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1369         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1370         struct ixgbe_hw *hw;
1371
1372         PMD_INIT_FUNC_TRACE();
1373
1374         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1375                 return -EPERM;
1376
1377         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1378
1379         if (hw->adapter_stopped == 0)
1380                 ixgbe_dev_close(eth_dev);
1381
1382         eth_dev->dev_ops = NULL;
1383         eth_dev->rx_pkt_burst = NULL;
1384         eth_dev->tx_pkt_burst = NULL;
1385
1386         /* Unlock any pending hardware semaphore */
1387         ixgbe_swfw_lock_reset(hw);
1388
1389         /* disable uio intr before callback unregister */
1390         rte_intr_disable(intr_handle);
1391         rte_intr_callback_unregister(intr_handle,
1392                                      ixgbe_dev_interrupt_handler, eth_dev);
1393
1394         /* uninitialize PF if max_vfs not zero */
1395         ixgbe_pf_host_uninit(eth_dev);
1396
1397         rte_free(eth_dev->data->mac_addrs);
1398         eth_dev->data->mac_addrs = NULL;
1399
1400         rte_free(eth_dev->data->hash_mac_addrs);
1401         eth_dev->data->hash_mac_addrs = NULL;
1402
1403         /* remove all the fdir filters & hash */
1404         ixgbe_fdir_filter_uninit(eth_dev);
1405
1406         /* remove all the L2 tunnel filters & hash */
1407         ixgbe_l2_tn_filter_uninit(eth_dev);
1408
1409         /* Remove all ntuple filters of the device */
1410         ixgbe_ntuple_filter_uninit(eth_dev);
1411
1412         /* clear all the filters list */
1413         ixgbe_filterlist_flush();
1414
1415         return 0;
1416 }
1417
1418 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1419 {
1420         struct ixgbe_filter_info *filter_info =
1421                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1422         struct ixgbe_5tuple_filter *p_5tuple;
1423
1424         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1425                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1426                              p_5tuple,
1427                              entries);
1428                 rte_free(p_5tuple);
1429         }
1430         memset(filter_info->fivetuple_mask, 0,
1431                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1432
1433         return 0;
1434 }
1435
1436 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1437 {
1438         struct ixgbe_hw_fdir_info *fdir_info =
1439                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1440         struct ixgbe_fdir_filter *fdir_filter;
1441
1442                 if (fdir_info->hash_map)
1443                 rte_free(fdir_info->hash_map);
1444         if (fdir_info->hash_handle)
1445                 rte_hash_free(fdir_info->hash_handle);
1446
1447         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1448                 TAILQ_REMOVE(&fdir_info->fdir_list,
1449                              fdir_filter,
1450                              entries);
1451                 rte_free(fdir_filter);
1452         }
1453
1454         return 0;
1455 }
1456
1457 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1458 {
1459         struct ixgbe_l2_tn_info *l2_tn_info =
1460                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1461         struct ixgbe_l2_tn_filter *l2_tn_filter;
1462
1463         if (l2_tn_info->hash_map)
1464                 rte_free(l2_tn_info->hash_map);
1465         if (l2_tn_info->hash_handle)
1466                 rte_hash_free(l2_tn_info->hash_handle);
1467
1468         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1469                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1470                              l2_tn_filter,
1471                              entries);
1472                 rte_free(l2_tn_filter);
1473         }
1474
1475         return 0;
1476 }
1477
1478 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1479 {
1480         struct ixgbe_hw_fdir_info *fdir_info =
1481                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1482         char fdir_hash_name[RTE_HASH_NAMESIZE];
1483         struct rte_hash_parameters fdir_hash_params = {
1484                 .name = fdir_hash_name,
1485                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1486                 .key_len = sizeof(union ixgbe_atr_input),
1487                 .hash_func = rte_hash_crc,
1488                 .hash_func_init_val = 0,
1489                 .socket_id = rte_socket_id(),
1490         };
1491
1492         TAILQ_INIT(&fdir_info->fdir_list);
1493         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1494                  "fdir_%s", eth_dev->data->name);
1495         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1496         if (!fdir_info->hash_handle) {
1497                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1498                 return -EINVAL;
1499         }
1500         fdir_info->hash_map = rte_zmalloc("ixgbe",
1501                                           sizeof(struct ixgbe_fdir_filter *) *
1502                                           IXGBE_MAX_FDIR_FILTER_NUM,
1503                                           0);
1504         if (!fdir_info->hash_map) {
1505                 PMD_INIT_LOG(ERR,
1506                              "Failed to allocate memory for fdir hash map!");
1507                 return -ENOMEM;
1508         }
1509         fdir_info->mask_added = FALSE;
1510
1511         return 0;
1512 }
1513
1514 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1515 {
1516         struct ixgbe_l2_tn_info *l2_tn_info =
1517                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1518         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1519         struct rte_hash_parameters l2_tn_hash_params = {
1520                 .name = l2_tn_hash_name,
1521                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1522                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1523                 .hash_func = rte_hash_crc,
1524                 .hash_func_init_val = 0,
1525                 .socket_id = rte_socket_id(),
1526         };
1527
1528         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1529         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1530                  "l2_tn_%s", eth_dev->data->name);
1531         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1532         if (!l2_tn_info->hash_handle) {
1533                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1534                 return -EINVAL;
1535         }
1536         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1537                                    sizeof(struct ixgbe_l2_tn_filter *) *
1538                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1539                                    0);
1540         if (!l2_tn_info->hash_map) {
1541                 PMD_INIT_LOG(ERR,
1542                         "Failed to allocate memory for L2 TN hash map!");
1543                 return -ENOMEM;
1544         }
1545         l2_tn_info->e_tag_en = FALSE;
1546         l2_tn_info->e_tag_fwd_en = FALSE;
1547         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1548
1549         return 0;
1550 }
1551 /*
1552  * Negotiate mailbox API version with the PF.
1553  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1554  * Then we try to negotiate starting with the most recent one.
1555  * If all negotiation attempts fail, then we will proceed with
1556  * the default one (ixgbe_mbox_api_10).
1557  */
1558 static void
1559 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1560 {
1561         int32_t i;
1562
1563         /* start with highest supported, proceed down */
1564         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1565                 ixgbe_mbox_api_12,
1566                 ixgbe_mbox_api_11,
1567                 ixgbe_mbox_api_10,
1568         };
1569
1570         for (i = 0;
1571                         i != RTE_DIM(sup_ver) &&
1572                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1573                         i++)
1574                 ;
1575 }
1576
1577 static void
1578 generate_random_mac_addr(struct ether_addr *mac_addr)
1579 {
1580         uint64_t random;
1581
1582         /* Set Organizationally Unique Identifier (OUI) prefix. */
1583         mac_addr->addr_bytes[0] = 0x00;
1584         mac_addr->addr_bytes[1] = 0x09;
1585         mac_addr->addr_bytes[2] = 0xC0;
1586         /* Force indication of locally assigned MAC address. */
1587         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1588         /* Generate the last 3 bytes of the MAC address with a random number. */
1589         random = rte_rand();
1590         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1591 }
1592
1593 /*
1594  * Virtual Function device init
1595  */
1596 static int
1597 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1598 {
1599         int diag;
1600         uint32_t tc, tcs;
1601         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1602         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1603         struct ixgbe_hw *hw =
1604                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1605         struct ixgbe_vfta *shadow_vfta =
1606                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1607         struct ixgbe_hwstrip *hwstrip =
1608                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1609         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1610
1611         PMD_INIT_FUNC_TRACE();
1612
1613         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1614         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1615         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1616
1617         /* for secondary processes, we don't initialise any further as primary
1618          * has already done this work. Only check we don't need a different
1619          * RX function
1620          */
1621         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1622                 struct ixgbe_tx_queue *txq;
1623                 /* TX queue function in primary, set by last queue initialized
1624                  * Tx queue may not initialized by primary process
1625                  */
1626                 if (eth_dev->data->tx_queues) {
1627                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1628                         ixgbe_set_tx_function(eth_dev, txq);
1629                 } else {
1630                         /* Use default TX function if we get here */
1631                         PMD_INIT_LOG(NOTICE,
1632                                      "No TX queues configured yet. Using default TX function.");
1633                 }
1634
1635                 ixgbe_set_rx_function(eth_dev);
1636
1637                 return 0;
1638         }
1639
1640         rte_eth_copy_pci_info(eth_dev, pci_dev);
1641         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1642
1643         hw->device_id = pci_dev->id.device_id;
1644         hw->vendor_id = pci_dev->id.vendor_id;
1645         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1646
1647         /* initialize the vfta */
1648         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1649
1650         /* initialize the hw strip bitmap*/
1651         memset(hwstrip, 0, sizeof(*hwstrip));
1652
1653         /* Initialize the shared code (base driver) */
1654         diag = ixgbe_init_shared_code(hw);
1655         if (diag != IXGBE_SUCCESS) {
1656                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1657                 return -EIO;
1658         }
1659
1660         /* init_mailbox_params */
1661         hw->mbx.ops.init_params(hw);
1662
1663         /* Reset the hw statistics */
1664         ixgbevf_dev_stats_reset(eth_dev);
1665
1666         /* Disable the interrupts for VF */
1667         ixgbevf_intr_disable(hw);
1668
1669         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1670         diag = hw->mac.ops.reset_hw(hw);
1671
1672         /*
1673          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1674          * the underlying PF driver has not assigned a MAC address to the VF.
1675          * In this case, assign a random MAC address.
1676          */
1677         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1678                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1679                 return diag;
1680         }
1681
1682         /* negotiate mailbox API version to use with the PF. */
1683         ixgbevf_negotiate_api(hw);
1684
1685         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1686         ixgbevf_get_queues(hw, &tcs, &tc);
1687
1688         /* Allocate memory for storing MAC addresses */
1689         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1690                                                hw->mac.num_rar_entries, 0);
1691         if (eth_dev->data->mac_addrs == NULL) {
1692                 PMD_INIT_LOG(ERR,
1693                              "Failed to allocate %u bytes needed to store "
1694                              "MAC addresses",
1695                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1696                 return -ENOMEM;
1697         }
1698
1699         /* Generate a random MAC address, if none was assigned by PF. */
1700         if (is_zero_ether_addr(perm_addr)) {
1701                 generate_random_mac_addr(perm_addr);
1702                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1703                 if (diag) {
1704                         rte_free(eth_dev->data->mac_addrs);
1705                         eth_dev->data->mac_addrs = NULL;
1706                         return diag;
1707                 }
1708                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1709                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1710                              "%02x:%02x:%02x:%02x:%02x:%02x",
1711                              perm_addr->addr_bytes[0],
1712                              perm_addr->addr_bytes[1],
1713                              perm_addr->addr_bytes[2],
1714                              perm_addr->addr_bytes[3],
1715                              perm_addr->addr_bytes[4],
1716                              perm_addr->addr_bytes[5]);
1717         }
1718
1719         /* Copy the permanent MAC address */
1720         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1721
1722         /* reset the hardware with the new settings */
1723         diag = hw->mac.ops.start_hw(hw);
1724         switch (diag) {
1725         case  0:
1726                 break;
1727
1728         default:
1729                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1730                 return -EIO;
1731         }
1732
1733         rte_intr_callback_register(intr_handle,
1734                                    ixgbevf_dev_interrupt_handler, eth_dev);
1735         rte_intr_enable(intr_handle);
1736         ixgbevf_intr_enable(hw);
1737
1738         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1739                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1740                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1741
1742         return 0;
1743 }
1744
1745 /* Virtual Function device uninit */
1746
1747 static int
1748 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1749 {
1750         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1751         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1752         struct ixgbe_hw *hw;
1753
1754         PMD_INIT_FUNC_TRACE();
1755
1756         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1757                 return -EPERM;
1758
1759         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1760
1761         if (hw->adapter_stopped == 0)
1762                 ixgbevf_dev_close(eth_dev);
1763
1764         eth_dev->dev_ops = NULL;
1765         eth_dev->rx_pkt_burst = NULL;
1766         eth_dev->tx_pkt_burst = NULL;
1767
1768         /* Disable the interrupts for VF */
1769         ixgbevf_intr_disable(hw);
1770
1771         rte_free(eth_dev->data->mac_addrs);
1772         eth_dev->data->mac_addrs = NULL;
1773
1774         rte_intr_disable(intr_handle);
1775         rte_intr_callback_unregister(intr_handle,
1776                                      ixgbevf_dev_interrupt_handler, eth_dev);
1777
1778         return 0;
1779 }
1780
1781 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1782         struct rte_pci_device *pci_dev)
1783 {
1784         return rte_eth_dev_pci_generic_probe(pci_dev,
1785                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1786 }
1787
1788 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1789 {
1790         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1791 }
1792
1793 static struct rte_pci_driver rte_ixgbe_pmd = {
1794         .id_table = pci_id_ixgbe_map,
1795         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1796         .probe = eth_ixgbe_pci_probe,
1797         .remove = eth_ixgbe_pci_remove,
1798 };
1799
1800 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1801         struct rte_pci_device *pci_dev)
1802 {
1803         return rte_eth_dev_pci_generic_probe(pci_dev,
1804                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1805 }
1806
1807 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1808 {
1809         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1810 }
1811
1812 /*
1813  * virtual function driver struct
1814  */
1815 static struct rte_pci_driver rte_ixgbevf_pmd = {
1816         .id_table = pci_id_ixgbevf_map,
1817         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1818         .probe = eth_ixgbevf_pci_probe,
1819         .remove = eth_ixgbevf_pci_remove,
1820 };
1821
1822 static int
1823 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1824 {
1825         struct ixgbe_hw *hw =
1826                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827         struct ixgbe_vfta *shadow_vfta =
1828                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1829         uint32_t vfta;
1830         uint32_t vid_idx;
1831         uint32_t vid_bit;
1832
1833         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1834         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1835         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1836         if (on)
1837                 vfta |= vid_bit;
1838         else
1839                 vfta &= ~vid_bit;
1840         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1841
1842         /* update local VFTA copy */
1843         shadow_vfta->vfta[vid_idx] = vfta;
1844
1845         return 0;
1846 }
1847
1848 static void
1849 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1850 {
1851         if (on)
1852                 ixgbe_vlan_hw_strip_enable(dev, queue);
1853         else
1854                 ixgbe_vlan_hw_strip_disable(dev, queue);
1855 }
1856
1857 static int
1858 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1859                     enum rte_vlan_type vlan_type,
1860                     uint16_t tpid)
1861 {
1862         struct ixgbe_hw *hw =
1863                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864         int ret = 0;
1865         uint32_t reg;
1866         uint32_t qinq;
1867
1868         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1869         qinq &= IXGBE_DMATXCTL_GDV;
1870
1871         switch (vlan_type) {
1872         case ETH_VLAN_TYPE_INNER:
1873                 if (qinq) {
1874                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1875                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1876                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1877                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1878                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1879                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1880                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1881                 } else {
1882                         ret = -ENOTSUP;
1883                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1884                                     " by single VLAN");
1885                 }
1886                 break;
1887         case ETH_VLAN_TYPE_OUTER:
1888                 if (qinq) {
1889                         /* Only the high 16-bits is valid */
1890                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1891                                         IXGBE_EXVET_VET_EXT_SHIFT);
1892                 } else {
1893                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1894                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1895                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1896                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1897                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1898                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1899                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1900                 }
1901
1902                 break;
1903         default:
1904                 ret = -EINVAL;
1905                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1906                 break;
1907         }
1908
1909         return ret;
1910 }
1911
1912 void
1913 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1914 {
1915         struct ixgbe_hw *hw =
1916                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917         uint32_t vlnctrl;
1918
1919         PMD_INIT_FUNC_TRACE();
1920
1921         /* Filter Table Disable */
1922         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1923         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1924
1925         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1926 }
1927
1928 void
1929 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1930 {
1931         struct ixgbe_hw *hw =
1932                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933         struct ixgbe_vfta *shadow_vfta =
1934                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1935         uint32_t vlnctrl;
1936         uint16_t i;
1937
1938         PMD_INIT_FUNC_TRACE();
1939
1940         /* Filter Table Enable */
1941         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1942         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1943         vlnctrl |= IXGBE_VLNCTRL_VFE;
1944
1945         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1946
1947         /* write whatever is in local vfta copy */
1948         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1949                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1950 }
1951
1952 static void
1953 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1954 {
1955         struct ixgbe_hwstrip *hwstrip =
1956                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1957         struct ixgbe_rx_queue *rxq;
1958
1959         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1960                 return;
1961
1962         if (on)
1963                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1964         else
1965                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1966
1967         if (queue >= dev->data->nb_rx_queues)
1968                 return;
1969
1970         rxq = dev->data->rx_queues[queue];
1971
1972         if (on)
1973                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1974         else
1975                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1976 }
1977
1978 static void
1979 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1980 {
1981         struct ixgbe_hw *hw =
1982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983         uint32_t ctrl;
1984
1985         PMD_INIT_FUNC_TRACE();
1986
1987         if (hw->mac.type == ixgbe_mac_82598EB) {
1988                 /* No queue level support */
1989                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1990                 return;
1991         }
1992
1993         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1994         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1995         ctrl &= ~IXGBE_RXDCTL_VME;
1996         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1997
1998         /* record those setting for HW strip per queue */
1999         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2000 }
2001
2002 static void
2003 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2004 {
2005         struct ixgbe_hw *hw =
2006                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2007         uint32_t ctrl;
2008
2009         PMD_INIT_FUNC_TRACE();
2010
2011         if (hw->mac.type == ixgbe_mac_82598EB) {
2012                 /* No queue level supported */
2013                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2014                 return;
2015         }
2016
2017         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2018         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2019         ctrl |= IXGBE_RXDCTL_VME;
2020         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2021
2022         /* record those setting for HW strip per queue */
2023         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2024 }
2025
2026 void
2027 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2028 {
2029         struct ixgbe_hw *hw =
2030                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2031         uint32_t ctrl;
2032         uint16_t i;
2033         struct ixgbe_rx_queue *rxq;
2034
2035         PMD_INIT_FUNC_TRACE();
2036
2037         if (hw->mac.type == ixgbe_mac_82598EB) {
2038                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2039                 ctrl &= ~IXGBE_VLNCTRL_VME;
2040                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2041         } else {
2042                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2043                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2044                         rxq = dev->data->rx_queues[i];
2045                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2046                         ctrl &= ~IXGBE_RXDCTL_VME;
2047                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2048
2049                         /* record those setting for HW strip per queue */
2050                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2051                 }
2052         }
2053 }
2054
2055 void
2056 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2057 {
2058         struct ixgbe_hw *hw =
2059                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060         uint32_t ctrl;
2061         uint16_t i;
2062         struct ixgbe_rx_queue *rxq;
2063
2064         PMD_INIT_FUNC_TRACE();
2065
2066         if (hw->mac.type == ixgbe_mac_82598EB) {
2067                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2068                 ctrl |= IXGBE_VLNCTRL_VME;
2069                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2070         } else {
2071                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2072                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2073                         rxq = dev->data->rx_queues[i];
2074                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2075                         ctrl |= IXGBE_RXDCTL_VME;
2076                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2077
2078                         /* record those setting for HW strip per queue */
2079                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2080                 }
2081         }
2082 }
2083
2084 static void
2085 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2086 {
2087         struct ixgbe_hw *hw =
2088                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089         uint32_t ctrl;
2090
2091         PMD_INIT_FUNC_TRACE();
2092
2093         /* DMATXCTRL: Geric Double VLAN Disable */
2094         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2095         ctrl &= ~IXGBE_DMATXCTL_GDV;
2096         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2097
2098         /* CTRL_EXT: Global Double VLAN Disable */
2099         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2100         ctrl &= ~IXGBE_EXTENDED_VLAN;
2101         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2102
2103 }
2104
2105 static void
2106 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2107 {
2108         struct ixgbe_hw *hw =
2109                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110         uint32_t ctrl;
2111
2112         PMD_INIT_FUNC_TRACE();
2113
2114         /* DMATXCTRL: Geric Double VLAN Enable */
2115         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2116         ctrl |= IXGBE_DMATXCTL_GDV;
2117         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2118
2119         /* CTRL_EXT: Global Double VLAN Enable */
2120         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2121         ctrl |= IXGBE_EXTENDED_VLAN;
2122         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2123
2124         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2125         if (hw->mac.type == ixgbe_mac_X550 ||
2126             hw->mac.type == ixgbe_mac_X550EM_x ||
2127             hw->mac.type == ixgbe_mac_X550EM_a) {
2128                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2129                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2130                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2131         }
2132
2133         /*
2134          * VET EXT field in the EXVET register = 0x8100 by default
2135          * So no need to change. Same to VT field of DMATXCTL register
2136          */
2137 }
2138
2139 static void
2140 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2141 {
2142         if (mask & ETH_VLAN_STRIP_MASK) {
2143                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2144                         ixgbe_vlan_hw_strip_enable_all(dev);
2145                 else
2146                         ixgbe_vlan_hw_strip_disable_all(dev);
2147         }
2148
2149         if (mask & ETH_VLAN_FILTER_MASK) {
2150                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2151                         ixgbe_vlan_hw_filter_enable(dev);
2152                 else
2153                         ixgbe_vlan_hw_filter_disable(dev);
2154         }
2155
2156         if (mask & ETH_VLAN_EXTEND_MASK) {
2157                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2158                         ixgbe_vlan_hw_extend_enable(dev);
2159                 else
2160                         ixgbe_vlan_hw_extend_disable(dev);
2161         }
2162 }
2163
2164 static void
2165 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2166 {
2167         struct ixgbe_hw *hw =
2168                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2170         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2171
2172         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2173         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2174 }
2175
2176 static int
2177 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2178 {
2179         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2180
2181         switch (nb_rx_q) {
2182         case 1:
2183         case 2:
2184                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2185                 break;
2186         case 4:
2187                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2188                 break;
2189         default:
2190                 return -EINVAL;
2191         }
2192
2193         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2194         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2195
2196         return 0;
2197 }
2198
2199 static int
2200 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2201 {
2202         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2205         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2206
2207         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2208                 /* check multi-queue mode */
2209                 switch (dev_conf->rxmode.mq_mode) {
2210                 case ETH_MQ_RX_VMDQ_DCB:
2211                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2212                         break;
2213                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2214                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2215                         PMD_INIT_LOG(ERR, "SRIOV active,"
2216                                         " unsupported mq_mode rx %d.",
2217                                         dev_conf->rxmode.mq_mode);
2218                         return -EINVAL;
2219                 case ETH_MQ_RX_RSS:
2220                 case ETH_MQ_RX_VMDQ_RSS:
2221                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2222                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2223                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2224                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2225                                                 " invalid queue number"
2226                                                 " for VMDQ RSS, allowed"
2227                                                 " value are 1, 2 or 4.");
2228                                         return -EINVAL;
2229                                 }
2230                         break;
2231                 case ETH_MQ_RX_VMDQ_ONLY:
2232                 case ETH_MQ_RX_NONE:
2233                         /* if nothing mq mode configure, use default scheme */
2234                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2235                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2236                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2237                         break;
2238                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2239                         /* SRIOV only works in VMDq enable mode */
2240                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2241                                         " wrong mq_mode rx %d.",
2242                                         dev_conf->rxmode.mq_mode);
2243                         return -EINVAL;
2244                 }
2245
2246                 switch (dev_conf->txmode.mq_mode) {
2247                 case ETH_MQ_TX_VMDQ_DCB:
2248                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2249                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2250                         break;
2251                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2252                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2253                         break;
2254                 }
2255
2256                 /* check valid queue number */
2257                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2258                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2259                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2260                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2261                                         " must be less than or equal to %d.",
2262                                         nb_rx_q, nb_tx_q,
2263                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2264                         return -EINVAL;
2265                 }
2266         } else {
2267                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2268                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2269                                           " not supported.");
2270                         return -EINVAL;
2271                 }
2272                 /* check configuration for vmdb+dcb mode */
2273                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2274                         const struct rte_eth_vmdq_dcb_conf *conf;
2275
2276                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2277                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2278                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2279                                 return -EINVAL;
2280                         }
2281                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2282                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2283                                conf->nb_queue_pools == ETH_32_POOLS)) {
2284                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2285                                                 " nb_queue_pools must be %d or %d.",
2286                                                 ETH_16_POOLS, ETH_32_POOLS);
2287                                 return -EINVAL;
2288                         }
2289                 }
2290                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2291                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2292
2293                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2294                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2295                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2296                                 return -EINVAL;
2297                         }
2298                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2299                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2300                                conf->nb_queue_pools == ETH_32_POOLS)) {
2301                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2302                                                 " nb_queue_pools != %d and"
2303                                                 " nb_queue_pools != %d.",
2304                                                 ETH_16_POOLS, ETH_32_POOLS);
2305                                 return -EINVAL;
2306                         }
2307                 }
2308
2309                 /* For DCB mode check our configuration before we go further */
2310                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2311                         const struct rte_eth_dcb_rx_conf *conf;
2312
2313                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2314                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2315                                                  IXGBE_DCB_NB_QUEUES);
2316                                 return -EINVAL;
2317                         }
2318                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2319                         if (!(conf->nb_tcs == ETH_4_TCS ||
2320                                conf->nb_tcs == ETH_8_TCS)) {
2321                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2322                                                 " and nb_tcs != %d.",
2323                                                 ETH_4_TCS, ETH_8_TCS);
2324                                 return -EINVAL;
2325                         }
2326                 }
2327
2328                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2329                         const struct rte_eth_dcb_tx_conf *conf;
2330
2331                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2332                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2333                                                  IXGBE_DCB_NB_QUEUES);
2334                                 return -EINVAL;
2335                         }
2336                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2337                         if (!(conf->nb_tcs == ETH_4_TCS ||
2338                                conf->nb_tcs == ETH_8_TCS)) {
2339                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2340                                                 " and nb_tcs != %d.",
2341                                                 ETH_4_TCS, ETH_8_TCS);
2342                                 return -EINVAL;
2343                         }
2344                 }
2345
2346                 /*
2347                  * When DCB/VT is off, maximum number of queues changes,
2348                  * except for 82598EB, which remains constant.
2349                  */
2350                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2351                                 hw->mac.type != ixgbe_mac_82598EB) {
2352                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2353                                 PMD_INIT_LOG(ERR,
2354                                              "Neither VT nor DCB are enabled, "
2355                                              "nb_tx_q > %d.",
2356                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2357                                 return -EINVAL;
2358                         }
2359                 }
2360         }
2361         return 0;
2362 }
2363
2364 static int
2365 ixgbe_dev_configure(struct rte_eth_dev *dev)
2366 {
2367         struct ixgbe_interrupt *intr =
2368                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2369         struct ixgbe_adapter *adapter =
2370                 (struct ixgbe_adapter *)dev->data->dev_private;
2371         int ret;
2372
2373         PMD_INIT_FUNC_TRACE();
2374         /* multipe queue mode checking */
2375         ret  = ixgbe_check_mq_mode(dev);
2376         if (ret != 0) {
2377                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2378                             ret);
2379                 return ret;
2380         }
2381
2382         /* set flag to update link status after init */
2383         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2384
2385         /*
2386          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2387          * allocation or vector Rx preconditions we will reset it.
2388          */
2389         adapter->rx_bulk_alloc_allowed = true;
2390         adapter->rx_vec_allowed = true;
2391
2392         return 0;
2393 }
2394
2395 static void
2396 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2397 {
2398         struct ixgbe_hw *hw =
2399                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400         struct ixgbe_interrupt *intr =
2401                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2402         uint32_t gpie;
2403
2404         /* only set up it on X550EM_X */
2405         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2406                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2407                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2408                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2409                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2410                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2411         }
2412 }
2413
2414 int
2415 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2416                         uint16_t tx_rate, uint64_t q_msk)
2417 {
2418         struct ixgbe_hw *hw;
2419         struct ixgbe_vf_info *vfinfo;
2420         struct rte_eth_link link;
2421         uint8_t  nb_q_per_pool;
2422         uint32_t queue_stride;
2423         uint32_t queue_idx, idx = 0, vf_idx;
2424         uint32_t queue_end;
2425         uint16_t total_rate = 0;
2426         struct rte_pci_device *pci_dev;
2427
2428         pci_dev = IXGBE_DEV_TO_PCI(dev);
2429         rte_eth_link_get_nowait(dev->data->port_id, &link);
2430
2431         if (vf >= pci_dev->max_vfs)
2432                 return -EINVAL;
2433
2434         if (tx_rate > link.link_speed)
2435                 return -EINVAL;
2436
2437         if (q_msk == 0)
2438                 return 0;
2439
2440         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2441         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2442         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2443         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2444         queue_idx = vf * queue_stride;
2445         queue_end = queue_idx + nb_q_per_pool - 1;
2446         if (queue_end >= hw->mac.max_tx_queues)
2447                 return -EINVAL;
2448
2449         if (vfinfo) {
2450                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2451                         if (vf_idx == vf)
2452                                 continue;
2453                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2454                                 idx++)
2455                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2456                 }
2457         } else {
2458                 return -EINVAL;
2459         }
2460
2461         /* Store tx_rate for this vf. */
2462         for (idx = 0; idx < nb_q_per_pool; idx++) {
2463                 if (((uint64_t)0x1 << idx) & q_msk) {
2464                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2465                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2466                         total_rate += tx_rate;
2467                 }
2468         }
2469
2470         if (total_rate > dev->data->dev_link.link_speed) {
2471                 /* Reset stored TX rate of the VF if it causes exceed
2472                  * link speed.
2473                  */
2474                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2475                 return -EINVAL;
2476         }
2477
2478         /* Set RTTBCNRC of each queue/pool for vf X  */
2479         for (; queue_idx <= queue_end; queue_idx++) {
2480                 if (0x1 & q_msk)
2481                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2482                 q_msk = q_msk >> 1;
2483         }
2484
2485         return 0;
2486 }
2487
2488 /*
2489  * Configure device link speed and setup link.
2490  * It returns 0 on success.
2491  */
2492 static int
2493 ixgbe_dev_start(struct rte_eth_dev *dev)
2494 {
2495         struct ixgbe_hw *hw =
2496                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2497         struct ixgbe_vf_info *vfinfo =
2498                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2499         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2500         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2501         uint32_t intr_vector = 0;
2502         int err, link_up = 0, negotiate = 0;
2503         uint32_t speed = 0;
2504         int mask = 0;
2505         int status;
2506         uint16_t vf, idx;
2507         uint32_t *link_speeds;
2508
2509         PMD_INIT_FUNC_TRACE();
2510
2511         /* IXGBE devices don't support:
2512         *    - half duplex (checked afterwards for valid speeds)
2513         *    - fixed speed: TODO implement
2514         */
2515         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2516                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2517                              dev->data->port_id);
2518                 return -EINVAL;
2519         }
2520
2521         /* disable uio/vfio intr/eventfd mapping */
2522         rte_intr_disable(intr_handle);
2523
2524         /* stop adapter */
2525         hw->adapter_stopped = 0;
2526         ixgbe_stop_adapter(hw);
2527
2528         /* reinitialize adapter
2529          * this calls reset and start
2530          */
2531         status = ixgbe_pf_reset_hw(hw);
2532         if (status != 0)
2533                 return -1;
2534         hw->mac.ops.start_hw(hw);
2535         hw->mac.get_link_status = true;
2536
2537         /* configure PF module if SRIOV enabled */
2538         ixgbe_pf_host_configure(dev);
2539
2540         ixgbe_dev_phy_intr_setup(dev);
2541
2542         /* check and configure queue intr-vector mapping */
2543         if ((rte_intr_cap_multiple(intr_handle) ||
2544              !RTE_ETH_DEV_SRIOV(dev).active) &&
2545             dev->data->dev_conf.intr_conf.rxq != 0) {
2546                 intr_vector = dev->data->nb_rx_queues;
2547                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2548                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2549                                         IXGBE_MAX_INTR_QUEUE_NUM);
2550                         return -ENOTSUP;
2551                 }
2552                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2553                         return -1;
2554         }
2555
2556         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2557                 intr_handle->intr_vec =
2558                         rte_zmalloc("intr_vec",
2559                                     dev->data->nb_rx_queues * sizeof(int), 0);
2560                 if (intr_handle->intr_vec == NULL) {
2561                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2562                                      " intr_vec", dev->data->nb_rx_queues);
2563                         return -ENOMEM;
2564                 }
2565         }
2566
2567         /* confiugre msix for sleep until rx interrupt */
2568         ixgbe_configure_msix(dev);
2569
2570         /* initialize transmission unit */
2571         ixgbe_dev_tx_init(dev);
2572
2573         /* This can fail when allocating mbufs for descriptor rings */
2574         err = ixgbe_dev_rx_init(dev);
2575         if (err) {
2576                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2577                 goto error;
2578         }
2579
2580     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2581                 ETH_VLAN_EXTEND_MASK;
2582         ixgbe_vlan_offload_set(dev, mask);
2583
2584         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2585                 /* Enable vlan filtering for VMDq */
2586                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2587         }
2588
2589         /* Configure DCB hw */
2590         ixgbe_configure_dcb(dev);
2591
2592         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2593                 err = ixgbe_fdir_configure(dev);
2594                 if (err)
2595                         goto error;
2596         }
2597
2598         /* Restore vf rate limit */
2599         if (vfinfo != NULL) {
2600                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2601                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2602                                 if (vfinfo[vf].tx_rate[idx] != 0)
2603                                         ixgbe_set_vf_rate_limit(
2604                                                 dev, vf,
2605                                                 vfinfo[vf].tx_rate[idx],
2606                                                 1 << idx);
2607         }
2608
2609         ixgbe_restore_statistics_mapping(dev);
2610
2611         err = ixgbe_dev_rxtx_start(dev);
2612         if (err < 0) {
2613                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2614                 goto error;
2615         }
2616
2617         /* Skip link setup if loopback mode is enabled for 82599. */
2618         if (hw->mac.type == ixgbe_mac_82599EB &&
2619                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2620                 goto skip_link_setup;
2621
2622         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2623                 err = hw->mac.ops.setup_sfp(hw);
2624                 if (err)
2625                         goto error;
2626         }
2627
2628         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2629                 /* Turn on the copper */
2630                 ixgbe_set_phy_power(hw, true);
2631         } else {
2632                 /* Turn on the laser */
2633                 ixgbe_enable_tx_laser(hw);
2634         }
2635
2636         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2637         if (err)
2638                 goto error;
2639         dev->data->dev_link.link_status = link_up;
2640
2641         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2642         if (err)
2643                 goto error;
2644
2645         link_speeds = &dev->data->dev_conf.link_speeds;
2646         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2647                         ETH_LINK_SPEED_10G)) {
2648                 PMD_INIT_LOG(ERR, "Invalid link setting");
2649                 goto error;
2650         }
2651
2652         speed = 0x0;
2653         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2654                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2655                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2656                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2657         } else {
2658                 if (*link_speeds & ETH_LINK_SPEED_10G)
2659                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2660                 if (*link_speeds & ETH_LINK_SPEED_1G)
2661                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2662                 if (*link_speeds & ETH_LINK_SPEED_100M)
2663                         speed |= IXGBE_LINK_SPEED_100_FULL;
2664         }
2665
2666         err = ixgbe_setup_link(hw, speed, link_up);
2667         if (err)
2668                 goto error;
2669
2670 skip_link_setup:
2671
2672         if (rte_intr_allow_others(intr_handle)) {
2673                 /* check if lsc interrupt is enabled */
2674                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2675                         ixgbe_dev_lsc_interrupt_setup(dev);
2676                 ixgbe_dev_macsec_interrupt_setup(dev);
2677         } else {
2678                 rte_intr_callback_unregister(intr_handle,
2679                                              ixgbe_dev_interrupt_handler, dev);
2680                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2681                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2682                                      " no intr multiplex");
2683         }
2684
2685         /* check if rxq interrupt is enabled */
2686         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2687             rte_intr_dp_is_en(intr_handle))
2688                 ixgbe_dev_rxq_interrupt_setup(dev);
2689
2690         /* enable uio/vfio intr/eventfd mapping */
2691         rte_intr_enable(intr_handle);
2692
2693         /* resume enabled intr since hw reset */
2694         ixgbe_enable_intr(dev);
2695         ixgbe_l2_tunnel_conf(dev);
2696         ixgbe_filter_restore(dev);
2697
2698         return 0;
2699
2700 error:
2701         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2702         ixgbe_dev_clear_queues(dev);
2703         return -EIO;
2704 }
2705
2706 /*
2707  * Stop device: disable rx and tx functions to allow for reconfiguring.
2708  */
2709 static void
2710 ixgbe_dev_stop(struct rte_eth_dev *dev)
2711 {
2712         struct rte_eth_link link;
2713         struct ixgbe_hw *hw =
2714                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2715         struct ixgbe_vf_info *vfinfo =
2716                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2717         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2718         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2719         int vf;
2720
2721         PMD_INIT_FUNC_TRACE();
2722
2723         /* disable interrupts */
2724         ixgbe_disable_intr(hw);
2725
2726         /* reset the NIC */
2727         ixgbe_pf_reset_hw(hw);
2728         hw->adapter_stopped = 0;
2729
2730         /* stop adapter */
2731         ixgbe_stop_adapter(hw);
2732
2733         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2734                 vfinfo[vf].clear_to_send = false;
2735
2736         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2737                 /* Turn off the copper */
2738                 ixgbe_set_phy_power(hw, false);
2739         } else {
2740                 /* Turn off the laser */
2741                 ixgbe_disable_tx_laser(hw);
2742         }
2743
2744         ixgbe_dev_clear_queues(dev);
2745
2746         /* Clear stored conf */
2747         dev->data->scattered_rx = 0;
2748         dev->data->lro = 0;
2749
2750         /* Clear recorded link status */
2751         memset(&link, 0, sizeof(link));
2752         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2753
2754         if (!rte_intr_allow_others(intr_handle))
2755                 /* resume to the default handler */
2756                 rte_intr_callback_register(intr_handle,
2757                                            ixgbe_dev_interrupt_handler,
2758                                            (void *)dev);
2759
2760         /* Clean datapath event and queue/vec mapping */
2761         rte_intr_efd_disable(intr_handle);
2762         if (intr_handle->intr_vec != NULL) {
2763                 rte_free(intr_handle->intr_vec);
2764                 intr_handle->intr_vec = NULL;
2765         }
2766 }
2767
2768 /*
2769  * Set device link up: enable tx.
2770  */
2771 static int
2772 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2773 {
2774         struct ixgbe_hw *hw =
2775                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2776         if (hw->mac.type == ixgbe_mac_82599EB) {
2777 #ifdef RTE_NIC_BYPASS
2778                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2779                         /* Not suported in bypass mode */
2780                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2781                                      "by device id 0x%x", hw->device_id);
2782                         return -ENOTSUP;
2783                 }
2784 #endif
2785         }
2786
2787         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2788                 /* Turn on the copper */
2789                 ixgbe_set_phy_power(hw, true);
2790         } else {
2791                 /* Turn on the laser */
2792                 ixgbe_enable_tx_laser(hw);
2793         }
2794
2795         return 0;
2796 }
2797
2798 /*
2799  * Set device link down: disable tx.
2800  */
2801 static int
2802 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2803 {
2804         struct ixgbe_hw *hw =
2805                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2806         if (hw->mac.type == ixgbe_mac_82599EB) {
2807 #ifdef RTE_NIC_BYPASS
2808                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2809                         /* Not suported in bypass mode */
2810                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2811                                      "by device id 0x%x", hw->device_id);
2812                         return -ENOTSUP;
2813                 }
2814 #endif
2815         }
2816
2817         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2818                 /* Turn off the copper */
2819                 ixgbe_set_phy_power(hw, false);
2820         } else {
2821                 /* Turn off the laser */
2822                 ixgbe_disable_tx_laser(hw);
2823         }
2824
2825         return 0;
2826 }
2827
2828 /*
2829  * Reest and stop device.
2830  */
2831 static void
2832 ixgbe_dev_close(struct rte_eth_dev *dev)
2833 {
2834         struct ixgbe_hw *hw =
2835                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836
2837         PMD_INIT_FUNC_TRACE();
2838
2839         ixgbe_pf_reset_hw(hw);
2840
2841         ixgbe_dev_stop(dev);
2842         hw->adapter_stopped = 1;
2843
2844         ixgbe_dev_free_queues(dev);
2845
2846         ixgbe_disable_pcie_master(hw);
2847
2848         /* reprogram the RAR[0] in case user changed it. */
2849         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2850 }
2851
2852 static void
2853 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2854                            struct ixgbe_hw_stats *hw_stats,
2855                            struct ixgbe_macsec_stats *macsec_stats,
2856                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2857                            uint64_t *total_qprc, uint64_t *total_qprdc)
2858 {
2859         uint32_t bprc, lxon, lxoff, total;
2860         uint32_t delta_gprc = 0;
2861         unsigned i;
2862         /* Workaround for RX byte count not including CRC bytes when CRC
2863          * strip is enabled. CRC bytes are removed from counters when crc_strip
2864          * is disabled.
2865          */
2866         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2867                         IXGBE_HLREG0_RXCRCSTRP);
2868
2869         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2870         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2871         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2872         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2873
2874         for (i = 0; i < 8; i++) {
2875                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2876
2877                 /* global total per queue */
2878                 hw_stats->mpc[i] += mp;
2879                 /* Running comprehensive total for stats display */
2880                 *total_missed_rx += hw_stats->mpc[i];
2881                 if (hw->mac.type == ixgbe_mac_82598EB) {
2882                         hw_stats->rnbc[i] +=
2883                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2884                         hw_stats->pxonrxc[i] +=
2885                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2886                         hw_stats->pxoffrxc[i] +=
2887                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2888                 } else {
2889                         hw_stats->pxonrxc[i] +=
2890                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2891                         hw_stats->pxoffrxc[i] +=
2892                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2893                         hw_stats->pxon2offc[i] +=
2894                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2895                 }
2896                 hw_stats->pxontxc[i] +=
2897                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2898                 hw_stats->pxofftxc[i] +=
2899                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2900         }
2901         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2902                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2903                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2904                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2905
2906                 delta_gprc += delta_qprc;
2907
2908                 hw_stats->qprc[i] += delta_qprc;
2909                 hw_stats->qptc[i] += delta_qptc;
2910
2911                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2912                 hw_stats->qbrc[i] +=
2913                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2914                 if (crc_strip == 0)
2915                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2916
2917                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2918                 hw_stats->qbtc[i] +=
2919                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2920
2921                 hw_stats->qprdc[i] += delta_qprdc;
2922                 *total_qprdc += hw_stats->qprdc[i];
2923
2924                 *total_qprc += hw_stats->qprc[i];
2925                 *total_qbrc += hw_stats->qbrc[i];
2926         }
2927         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2928         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2929         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2930
2931         /*
2932          * An errata states that gprc actually counts good + missed packets:
2933          * Workaround to set gprc to summated queue packet receives
2934          */
2935         hw_stats->gprc = *total_qprc;
2936
2937         if (hw->mac.type != ixgbe_mac_82598EB) {
2938                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2939                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2940                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2941                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2942                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2943                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2944                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2945                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2946         } else {
2947                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2948                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2949                 /* 82598 only has a counter in the high register */
2950                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2951                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2952                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2953         }
2954         uint64_t old_tpr = hw_stats->tpr;
2955
2956         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2957         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2958
2959         if (crc_strip == 0)
2960                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2961
2962         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2963         hw_stats->gptc += delta_gptc;
2964         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2965         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2966
2967         /*
2968          * Workaround: mprc hardware is incorrectly counting
2969          * broadcasts, so for now we subtract those.
2970          */
2971         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2972         hw_stats->bprc += bprc;
2973         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2974         if (hw->mac.type == ixgbe_mac_82598EB)
2975                 hw_stats->mprc -= bprc;
2976
2977         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2978         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2979         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2980         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2981         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2982         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2983
2984         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2985         hw_stats->lxontxc += lxon;
2986         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2987         hw_stats->lxofftxc += lxoff;
2988         total = lxon + lxoff;
2989
2990         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2991         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2992         hw_stats->gptc -= total;
2993         hw_stats->mptc -= total;
2994         hw_stats->ptc64 -= total;
2995         hw_stats->gotc -= total * ETHER_MIN_LEN;
2996
2997         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2998         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2999         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3000         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3001         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3002         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3003         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3004         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3005         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3006         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3007         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3008         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3009         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3010         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3011         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3012         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3013         /* Only read FCOE on 82599 */
3014         if (hw->mac.type != ixgbe_mac_82598EB) {
3015                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3016                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3017                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3018                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3019                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3020         }
3021
3022         /* Flow Director Stats registers */
3023         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3024         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3025
3026         /* MACsec Stats registers */
3027         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3028         macsec_stats->out_pkts_encrypted +=
3029                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3030         macsec_stats->out_pkts_protected +=
3031                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3032         macsec_stats->out_octets_encrypted +=
3033                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3034         macsec_stats->out_octets_protected +=
3035                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3036         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3037         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3038         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3039         macsec_stats->in_pkts_unknownsci +=
3040                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3041         macsec_stats->in_octets_decrypted +=
3042                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3043         macsec_stats->in_octets_validated +=
3044                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3045         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3046         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3047         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3048         for (i = 0; i < 2; i++) {
3049                 macsec_stats->in_pkts_ok +=
3050                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3051                 macsec_stats->in_pkts_invalid +=
3052                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3053                 macsec_stats->in_pkts_notvalid +=
3054                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3055         }
3056         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3057         macsec_stats->in_pkts_notusingsa +=
3058                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3059 }
3060
3061 /*
3062  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3063  */
3064 static void
3065 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3066 {
3067         struct ixgbe_hw *hw =
3068                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3069         struct ixgbe_hw_stats *hw_stats =
3070                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3071         struct ixgbe_macsec_stats *macsec_stats =
3072                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3073                                 dev->data->dev_private);
3074         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3075         unsigned i;
3076
3077         total_missed_rx = 0;
3078         total_qbrc = 0;
3079         total_qprc = 0;
3080         total_qprdc = 0;
3081
3082         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3083                         &total_qbrc, &total_qprc, &total_qprdc);
3084
3085         if (stats == NULL)
3086                 return;
3087
3088         /* Fill out the rte_eth_stats statistics structure */
3089         stats->ipackets = total_qprc;
3090         stats->ibytes = total_qbrc;
3091         stats->opackets = hw_stats->gptc;
3092         stats->obytes = hw_stats->gotc;
3093
3094         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3095                 stats->q_ipackets[i] = hw_stats->qprc[i];
3096                 stats->q_opackets[i] = hw_stats->qptc[i];
3097                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3098                 stats->q_obytes[i] = hw_stats->qbtc[i];
3099                 stats->q_errors[i] = hw_stats->qprdc[i];
3100         }
3101
3102         /* Rx Errors */
3103         stats->imissed  = total_missed_rx;
3104         stats->ierrors  = hw_stats->crcerrs +
3105                           hw_stats->mspdc +
3106                           hw_stats->rlec +
3107                           hw_stats->ruc +
3108                           hw_stats->roc +
3109                           hw_stats->illerrc +
3110                           hw_stats->errbc +
3111                           hw_stats->rfc +
3112                           hw_stats->fccrc +
3113                           hw_stats->fclast;
3114
3115         /* Tx Errors */
3116         stats->oerrors  = 0;
3117 }
3118
3119 static void
3120 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3121 {
3122         struct ixgbe_hw_stats *stats =
3123                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3124
3125         /* HW registers are cleared on read */
3126         ixgbe_dev_stats_get(dev, NULL);
3127
3128         /* Reset software totals */
3129         memset(stats, 0, sizeof(*stats));
3130 }
3131
3132 /* This function calculates the number of xstats based on the current config */
3133 static unsigned
3134 ixgbe_xstats_calc_num(void) {
3135         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3136                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3137                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3138 }
3139
3140 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3141         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3142 {
3143         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3144         unsigned stat, i, count;
3145
3146         if (xstats_names != NULL) {
3147                 count = 0;
3148
3149                 /* Note: limit >= cnt_stats checked upstream
3150                  * in rte_eth_xstats_names()
3151                  */
3152
3153                 /* Extended stats from ixgbe_hw_stats */
3154                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3155                         snprintf(xstats_names[count].name,
3156                                 sizeof(xstats_names[count].name),
3157                                 "%s",
3158                                 rte_ixgbe_stats_strings[i].name);
3159                         count++;
3160                 }
3161
3162                 /* MACsec Stats */
3163                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3164                         snprintf(xstats_names[count].name,
3165                                 sizeof(xstats_names[count].name),
3166                                 "%s",
3167                                 rte_ixgbe_macsec_strings[i].name);
3168                         count++;
3169                 }
3170
3171                 /* RX Priority Stats */
3172                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3173                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3174                                 snprintf(xstats_names[count].name,
3175                                         sizeof(xstats_names[count].name),
3176                                         "rx_priority%u_%s", i,
3177                                         rte_ixgbe_rxq_strings[stat].name);
3178                                 count++;
3179                         }
3180                 }
3181
3182                 /* TX Priority Stats */
3183                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3184                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3185                                 snprintf(xstats_names[count].name,
3186                                         sizeof(xstats_names[count].name),
3187                                         "tx_priority%u_%s", i,
3188                                         rte_ixgbe_txq_strings[stat].name);
3189                                 count++;
3190                         }
3191                 }
3192         }
3193         return cnt_stats;
3194 }
3195
3196 static int ixgbe_dev_xstats_get_names_by_id(
3197         __rte_unused struct rte_eth_dev *dev,
3198         struct rte_eth_xstat_name *xstats_names,
3199         const uint64_t *ids,
3200         unsigned int limit)
3201 {
3202         if (!ids) {
3203                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3204                 unsigned int stat, i, count;
3205
3206                 if (xstats_names != NULL) {
3207                         count = 0;
3208
3209                         /* Note: limit >= cnt_stats checked upstream
3210                          * in rte_eth_xstats_names()
3211                          */
3212
3213                         /* Extended stats from ixgbe_hw_stats */
3214                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3215                                 snprintf(xstats_names[count].name,
3216                                         sizeof(xstats_names[count].name),
3217                                         "%s",
3218                                         rte_ixgbe_stats_strings[i].name);
3219                                 count++;
3220                         }
3221
3222                         /* MACsec Stats */
3223                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3224                                 snprintf(xstats_names[count].name,
3225                                         sizeof(xstats_names[count].name),
3226                                         "%s",
3227                                         rte_ixgbe_macsec_strings[i].name);
3228                                 count++;
3229                         }
3230
3231                         /* RX Priority Stats */
3232                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3233                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3234                                         snprintf(xstats_names[count].name,
3235                                             sizeof(xstats_names[count].name),
3236                                             "rx_priority%u_%s", i,
3237                                             rte_ixgbe_rxq_strings[stat].name);
3238                                         count++;
3239                                 }
3240                         }
3241
3242                         /* TX Priority Stats */
3243                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3244                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3245                                         snprintf(xstats_names[count].name,
3246                                             sizeof(xstats_names[count].name),
3247                                             "tx_priority%u_%s", i,
3248                                             rte_ixgbe_txq_strings[stat].name);
3249                                         count++;
3250                                 }
3251                         }
3252                 }
3253                 return cnt_stats;
3254         }
3255
3256         uint16_t i;
3257         uint16_t size = ixgbe_xstats_calc_num();
3258         struct rte_eth_xstat_name xstats_names_copy[size];
3259
3260         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3261                         size);
3262
3263         for (i = 0; i < limit; i++) {
3264                 if (ids[i] >= size) {
3265                         PMD_INIT_LOG(ERR, "id value isn't valid");
3266                         return -1;
3267                 }
3268                 strcpy(xstats_names[i].name,
3269                                 xstats_names_copy[ids[i]].name);
3270         }
3271         return limit;
3272 }
3273
3274 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3275         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3276 {
3277         unsigned i;
3278
3279         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3280                 return -ENOMEM;
3281
3282         if (xstats_names != NULL)
3283                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3284                         snprintf(xstats_names[i].name,
3285                                 sizeof(xstats_names[i].name),
3286                                 "%s", rte_ixgbevf_stats_strings[i].name);
3287         return IXGBEVF_NB_XSTATS;
3288 }
3289
3290 static int
3291 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3292                                          unsigned n)
3293 {
3294         struct ixgbe_hw *hw =
3295                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3296         struct ixgbe_hw_stats *hw_stats =
3297                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3298         struct ixgbe_macsec_stats *macsec_stats =
3299                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3300                                 dev->data->dev_private);
3301         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3302         unsigned i, stat, count = 0;
3303
3304         count = ixgbe_xstats_calc_num();
3305
3306         if (n < count)
3307                 return count;
3308
3309         total_missed_rx = 0;
3310         total_qbrc = 0;
3311         total_qprc = 0;
3312         total_qprdc = 0;
3313
3314         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3315                         &total_qbrc, &total_qprc, &total_qprdc);
3316
3317         /* If this is a reset xstats is NULL, and we have cleared the
3318          * registers by reading them.
3319          */
3320         if (!xstats)
3321                 return 0;
3322
3323         /* Extended stats from ixgbe_hw_stats */
3324         count = 0;
3325         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3326                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3327                                 rte_ixgbe_stats_strings[i].offset);
3328                 xstats[count].id = count;
3329                 count++;
3330         }
3331
3332         /* MACsec Stats */
3333         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3334                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3335                                 rte_ixgbe_macsec_strings[i].offset);
3336                 xstats[count].id = count;
3337                 count++;
3338         }
3339
3340         /* RX Priority Stats */
3341         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3342                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3343                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3344                                         rte_ixgbe_rxq_strings[stat].offset +
3345                                         (sizeof(uint64_t) * i));
3346                         xstats[count].id = count;
3347                         count++;
3348                 }
3349         }
3350
3351         /* TX Priority Stats */
3352         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3353                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3354                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3355                                         rte_ixgbe_txq_strings[stat].offset +
3356                                         (sizeof(uint64_t) * i));
3357                         xstats[count].id = count;
3358                         count++;
3359                 }
3360         }
3361         return count;
3362 }
3363
3364 static int
3365 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3366                 uint64_t *values, unsigned int n)
3367 {
3368         if (!ids) {
3369                 struct ixgbe_hw *hw =
3370                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3371                 struct ixgbe_hw_stats *hw_stats =
3372                                 IXGBE_DEV_PRIVATE_TO_STATS(
3373                                                 dev->data->dev_private);
3374                 struct ixgbe_macsec_stats *macsec_stats =
3375                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3376                                         dev->data->dev_private);
3377                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3378                 unsigned int i, stat, count = 0;
3379
3380                 count = ixgbe_xstats_calc_num();
3381
3382                 if (!ids && n < count)
3383                         return count;
3384
3385                 total_missed_rx = 0;
3386                 total_qbrc = 0;
3387                 total_qprc = 0;
3388                 total_qprdc = 0;
3389
3390                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3391                                 &total_missed_rx, &total_qbrc, &total_qprc,
3392                                 &total_qprdc);
3393
3394                 /* If this is a reset xstats is NULL, and we have cleared the
3395                  * registers by reading them.
3396                  */
3397                 if (!ids && !values)
3398                         return 0;
3399
3400                 /* Extended stats from ixgbe_hw_stats */
3401                 count = 0;
3402                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3403                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3404                                         rte_ixgbe_stats_strings[i].offset);
3405                         count++;
3406                 }
3407
3408                 /* MACsec Stats */
3409                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3410                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3411                                         rte_ixgbe_macsec_strings[i].offset);
3412                         count++;
3413                 }
3414
3415                 /* RX Priority Stats */
3416                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3417                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3418                                 values[count] =
3419                                         *(uint64_t *)(((char *)hw_stats) +
3420                                         rte_ixgbe_rxq_strings[stat].offset +
3421                                         (sizeof(uint64_t) * i));
3422                                 count++;
3423                         }
3424                 }
3425
3426                 /* TX Priority Stats */
3427                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3428                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3429                                 values[count] =
3430                                         *(uint64_t *)(((char *)hw_stats) +
3431                                         rte_ixgbe_txq_strings[stat].offset +
3432                                         (sizeof(uint64_t) * i));
3433                                 count++;
3434                         }
3435                 }
3436                 return count;
3437         }
3438
3439         uint16_t i;
3440         uint16_t size = ixgbe_xstats_calc_num();
3441         uint64_t values_copy[size];
3442
3443         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3444
3445         for (i = 0; i < n; i++) {
3446                 if (ids[i] >= size) {
3447                         PMD_INIT_LOG(ERR, "id value isn't valid");
3448                         return -1;
3449                 }
3450                 values[i] = values_copy[ids[i]];
3451         }
3452         return n;
3453 }
3454
3455 static void
3456 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3457 {
3458         struct ixgbe_hw_stats *stats =
3459                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3460         struct ixgbe_macsec_stats *macsec_stats =
3461                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3462                                 dev->data->dev_private);
3463
3464         unsigned count = ixgbe_xstats_calc_num();
3465
3466         /* HW registers are cleared on read */
3467         ixgbe_dev_xstats_get(dev, NULL, count);
3468
3469         /* Reset software totals */
3470         memset(stats, 0, sizeof(*stats));
3471         memset(macsec_stats, 0, sizeof(*macsec_stats));
3472 }
3473
3474 static void
3475 ixgbevf_update_stats(struct rte_eth_dev *dev)
3476 {
3477         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3478         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3479                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3480
3481         /* Good Rx packet, include VF loopback */
3482         UPDATE_VF_STAT(IXGBE_VFGPRC,
3483             hw_stats->last_vfgprc, hw_stats->vfgprc);
3484
3485         /* Good Rx octets, include VF loopback */
3486         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3487             hw_stats->last_vfgorc, hw_stats->vfgorc);
3488
3489         /* Good Tx packet, include VF loopback */
3490         UPDATE_VF_STAT(IXGBE_VFGPTC,
3491             hw_stats->last_vfgptc, hw_stats->vfgptc);
3492
3493         /* Good Tx octets, include VF loopback */
3494         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3495             hw_stats->last_vfgotc, hw_stats->vfgotc);
3496
3497         /* Rx Multicst Packet */
3498         UPDATE_VF_STAT(IXGBE_VFMPRC,
3499             hw_stats->last_vfmprc, hw_stats->vfmprc);
3500 }
3501
3502 static int
3503 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3504                        unsigned n)
3505 {
3506         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3507                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3508         unsigned i;
3509
3510         if (n < IXGBEVF_NB_XSTATS)
3511                 return IXGBEVF_NB_XSTATS;
3512
3513         ixgbevf_update_stats(dev);
3514
3515         if (!xstats)
3516                 return 0;
3517
3518         /* Extended stats */
3519         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3520                 xstats[i].id = i;
3521                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3522                         rte_ixgbevf_stats_strings[i].offset);
3523         }
3524
3525         return IXGBEVF_NB_XSTATS;
3526 }
3527
3528 static void
3529 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3530 {
3531         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3532                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3533
3534         ixgbevf_update_stats(dev);
3535
3536         if (stats == NULL)
3537                 return;
3538
3539         stats->ipackets = hw_stats->vfgprc;
3540         stats->ibytes = hw_stats->vfgorc;
3541         stats->opackets = hw_stats->vfgptc;
3542         stats->obytes = hw_stats->vfgotc;
3543 }
3544
3545 static void
3546 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3547 {
3548         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3549                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3550
3551         /* Sync HW register to the last stats */
3552         ixgbevf_dev_stats_get(dev, NULL);
3553
3554         /* reset HW current stats*/
3555         hw_stats->vfgprc = 0;
3556         hw_stats->vfgorc = 0;
3557         hw_stats->vfgptc = 0;
3558         hw_stats->vfgotc = 0;
3559 }
3560
3561 static int
3562 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3563 {
3564         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3565         u16 eeprom_verh, eeprom_verl;
3566         u32 etrack_id;
3567         int ret;
3568
3569         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3570         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3571
3572         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3573         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3574
3575         ret += 1; /* add the size of '\0' */
3576         if (fw_size < (u32)ret)
3577                 return ret;
3578         else
3579                 return 0;
3580 }
3581
3582 static void
3583 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3584 {
3585         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3588
3589         dev_info->pci_dev = pci_dev;
3590         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3591         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3592         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3593                 /*
3594                  * When DCB/VT is off, maximum number of queues changes,
3595                  * except for 82598EB, which remains constant.
3596                  */
3597                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3598                                 hw->mac.type != ixgbe_mac_82598EB)
3599                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3600         }
3601         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3602         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3603         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3604         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3605         dev_info->max_vfs = pci_dev->max_vfs;
3606         if (hw->mac.type == ixgbe_mac_82598EB)
3607                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3608         else
3609                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3610         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3611         dev_info->rx_offload_capa =
3612                 DEV_RX_OFFLOAD_VLAN_STRIP |
3613                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3614                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3615                 DEV_RX_OFFLOAD_TCP_CKSUM;
3616
3617         /*
3618          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3619          * mode.
3620          */
3621         if ((hw->mac.type == ixgbe_mac_82599EB ||
3622              hw->mac.type == ixgbe_mac_X540) &&
3623             !RTE_ETH_DEV_SRIOV(dev).active)
3624                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3625
3626         if (hw->mac.type == ixgbe_mac_82599EB ||
3627             hw->mac.type == ixgbe_mac_X540)
3628                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3629
3630         if (hw->mac.type == ixgbe_mac_X550 ||
3631             hw->mac.type == ixgbe_mac_X550EM_x ||
3632             hw->mac.type == ixgbe_mac_X550EM_a)
3633                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3634
3635         dev_info->tx_offload_capa =
3636                 DEV_TX_OFFLOAD_VLAN_INSERT |
3637                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3638                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3639                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3640                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3641                 DEV_TX_OFFLOAD_TCP_TSO;
3642
3643         if (hw->mac.type == ixgbe_mac_82599EB ||
3644             hw->mac.type == ixgbe_mac_X540)
3645                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3646
3647         if (hw->mac.type == ixgbe_mac_X550 ||
3648             hw->mac.type == ixgbe_mac_X550EM_x ||
3649             hw->mac.type == ixgbe_mac_X550EM_a)
3650                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3651
3652         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3653                 .rx_thresh = {
3654                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3655                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3656                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3657                 },
3658                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3659                 .rx_drop_en = 0,
3660         };
3661
3662         dev_info->default_txconf = (struct rte_eth_txconf) {
3663                 .tx_thresh = {
3664                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3665                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3666                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3667                 },
3668                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3669                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3670                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3671                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3672         };
3673
3674         dev_info->rx_desc_lim = rx_desc_lim;
3675         dev_info->tx_desc_lim = tx_desc_lim;
3676
3677         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3678         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3679         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3680
3681         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3682         if (hw->mac.type == ixgbe_mac_X540 ||
3683             hw->mac.type == ixgbe_mac_X540_vf ||
3684             hw->mac.type == ixgbe_mac_X550 ||
3685             hw->mac.type == ixgbe_mac_X550_vf) {
3686                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3687         }
3688 }
3689
3690 static const uint32_t *
3691 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3692 {
3693         static const uint32_t ptypes[] = {
3694                 /* For non-vec functions,
3695                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3696                  * for vec functions,
3697                  * refers to _recv_raw_pkts_vec().
3698                  */
3699                 RTE_PTYPE_L2_ETHER,
3700                 RTE_PTYPE_L3_IPV4,
3701                 RTE_PTYPE_L3_IPV4_EXT,
3702                 RTE_PTYPE_L3_IPV6,
3703                 RTE_PTYPE_L3_IPV6_EXT,
3704                 RTE_PTYPE_L4_SCTP,
3705                 RTE_PTYPE_L4_TCP,
3706                 RTE_PTYPE_L4_UDP,
3707                 RTE_PTYPE_TUNNEL_IP,
3708                 RTE_PTYPE_INNER_L3_IPV6,
3709                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3710                 RTE_PTYPE_INNER_L4_TCP,
3711                 RTE_PTYPE_INNER_L4_UDP,
3712                 RTE_PTYPE_UNKNOWN
3713         };
3714
3715         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3716             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3717             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3718             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3719                 return ptypes;
3720         return NULL;
3721 }
3722
3723 static void
3724 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3725                      struct rte_eth_dev_info *dev_info)
3726 {
3727         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3728         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3729
3730         dev_info->pci_dev = pci_dev;
3731         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3732         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3733         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3734         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3735         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3736         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3737         dev_info->max_vfs = pci_dev->max_vfs;
3738         if (hw->mac.type == ixgbe_mac_82598EB)
3739                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3740         else
3741                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3742         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3743                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3744                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3745                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3746         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3747                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3748                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3749                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3750                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3751                                 DEV_TX_OFFLOAD_TCP_TSO;
3752
3753         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3754                 .rx_thresh = {
3755                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3756                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3757                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3758                 },
3759                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3760                 .rx_drop_en = 0,
3761         };
3762
3763         dev_info->default_txconf = (struct rte_eth_txconf) {
3764                 .tx_thresh = {
3765                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3766                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3767                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3768                 },
3769                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3770                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3771                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3772                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3773         };
3774
3775         dev_info->rx_desc_lim = rx_desc_lim;
3776         dev_info->tx_desc_lim = tx_desc_lim;
3777 }
3778
3779 /* return 0 means link status changed, -1 means not changed */
3780 static int
3781 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3782 {
3783         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3784         struct rte_eth_link link, old;
3785         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3786         struct ixgbe_interrupt *intr =
3787                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3788         int link_up;
3789         int diag;
3790         u32 speed = 0;
3791         bool autoneg = false;
3792
3793         link.link_status = ETH_LINK_DOWN;
3794         link.link_speed = 0;
3795         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3796         memset(&old, 0, sizeof(old));
3797         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3798
3799         hw->mac.get_link_status = true;
3800
3801         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3802                 hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
3803                 speed = hw->phy.autoneg_advertised;
3804                 if (!speed)
3805                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3806                 ixgbe_setup_link(hw, speed, true);
3807         }
3808
3809         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3810         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3811                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3812         else
3813                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3814
3815         if (diag != 0) {
3816                 link.link_speed = ETH_SPEED_NUM_100M;
3817                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3818                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3819                 if (link.link_status == old.link_status)
3820                         return -1;
3821                 return 0;
3822         }
3823
3824         if (link_up == 0) {
3825                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3826                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3827                 if (link.link_status == old.link_status)
3828                         return -1;
3829                 return 0;
3830         }
3831         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3832         link.link_status = ETH_LINK_UP;
3833         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3834
3835         switch (link_speed) {
3836         default:
3837         case IXGBE_LINK_SPEED_UNKNOWN:
3838                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3839                 link.link_speed = ETH_SPEED_NUM_100M;
3840                 break;
3841
3842         case IXGBE_LINK_SPEED_100_FULL:
3843                 link.link_speed = ETH_SPEED_NUM_100M;
3844                 break;
3845
3846         case IXGBE_LINK_SPEED_1GB_FULL:
3847                 link.link_speed = ETH_SPEED_NUM_1G;
3848                 break;
3849
3850         case IXGBE_LINK_SPEED_10GB_FULL:
3851                 link.link_speed = ETH_SPEED_NUM_10G;
3852                 break;
3853         }
3854         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3855
3856         if (link.link_status == old.link_status)
3857                 return -1;
3858
3859         return 0;
3860 }
3861
3862 static void
3863 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3864 {
3865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3866         uint32_t fctrl;
3867
3868         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3869         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3870         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3871 }
3872
3873 static void
3874 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3875 {
3876         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3877         uint32_t fctrl;
3878
3879         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3880         fctrl &= (~IXGBE_FCTRL_UPE);
3881         if (dev->data->all_multicast == 1)
3882                 fctrl |= IXGBE_FCTRL_MPE;
3883         else
3884                 fctrl &= (~IXGBE_FCTRL_MPE);
3885         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3886 }
3887
3888 static void
3889 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3890 {
3891         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3892         uint32_t fctrl;
3893
3894         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3895         fctrl |= IXGBE_FCTRL_MPE;
3896         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3897 }
3898
3899 static void
3900 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3901 {
3902         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3903         uint32_t fctrl;
3904
3905         if (dev->data->promiscuous == 1)
3906                 return; /* must remain in all_multicast mode */
3907
3908         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3909         fctrl &= (~IXGBE_FCTRL_MPE);
3910         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3911 }
3912
3913 /**
3914  * It clears the interrupt causes and enables the interrupt.
3915  * It will be called once only during nic initialized.
3916  *
3917  * @param dev
3918  *  Pointer to struct rte_eth_dev.
3919  *
3920  * @return
3921  *  - On success, zero.
3922  *  - On failure, a negative value.
3923  */
3924 static int
3925 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3926 {
3927         struct ixgbe_interrupt *intr =
3928                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3929
3930         ixgbe_dev_link_status_print(dev);
3931         intr->mask |= IXGBE_EICR_LSC;
3932
3933         return 0;
3934 }
3935
3936 /**
3937  * It clears the interrupt causes and enables the interrupt.
3938  * It will be called once only during nic initialized.
3939  *
3940  * @param dev
3941  *  Pointer to struct rte_eth_dev.
3942  *
3943  * @return
3944  *  - On success, zero.
3945  *  - On failure, a negative value.
3946  */
3947 static int
3948 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3949 {
3950         struct ixgbe_interrupt *intr =
3951                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3952
3953         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3954
3955         return 0;
3956 }
3957
3958 /**
3959  * It clears the interrupt causes and enables the interrupt.
3960  * It will be called once only during nic initialized.
3961  *
3962  * @param dev
3963  *  Pointer to struct rte_eth_dev.
3964  *
3965  * @return
3966  *  - On success, zero.
3967  *  - On failure, a negative value.
3968  */
3969 static int
3970 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3971 {
3972         struct ixgbe_interrupt *intr =
3973                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3974
3975         intr->mask |= IXGBE_EICR_LINKSEC;
3976
3977         return 0;
3978 }
3979
3980 /*
3981  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3982  *
3983  * @param dev
3984  *  Pointer to struct rte_eth_dev.
3985  *
3986  * @return
3987  *  - On success, zero.
3988  *  - On failure, a negative value.
3989  */
3990 static int
3991 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3992 {
3993         uint32_t eicr;
3994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3995         struct ixgbe_interrupt *intr =
3996                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3997
3998         /* clear all cause mask */
3999         ixgbe_disable_intr(hw);
4000
4001         /* read-on-clear nic registers here */
4002         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4003         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4004
4005         intr->flags = 0;
4006
4007         /* set flag for async link update */
4008         if (eicr & IXGBE_EICR_LSC)
4009                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4010
4011         if (eicr & IXGBE_EICR_MAILBOX)
4012                 intr->flags |= IXGBE_FLAG_MAILBOX;
4013
4014         if (eicr & IXGBE_EICR_LINKSEC)
4015                 intr->flags |= IXGBE_FLAG_MACSEC;
4016
4017         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4018             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4019             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4020                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4021
4022         return 0;
4023 }
4024
4025 /**
4026  * It gets and then prints the link status.
4027  *
4028  * @param dev
4029  *  Pointer to struct rte_eth_dev.
4030  *
4031  * @return
4032  *  - On success, zero.
4033  *  - On failure, a negative value.
4034  */
4035 static void
4036 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4037 {
4038         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4039         struct rte_eth_link link;
4040
4041         memset(&link, 0, sizeof(link));
4042         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4043         if (link.link_status) {
4044                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4045                                         (int)(dev->data->port_id),
4046                                         (unsigned)link.link_speed,
4047                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4048                                         "full-duplex" : "half-duplex");
4049         } else {
4050                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4051                                 (int)(dev->data->port_id));
4052         }
4053         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4054                                 pci_dev->addr.domain,
4055                                 pci_dev->addr.bus,
4056                                 pci_dev->addr.devid,
4057                                 pci_dev->addr.function);
4058 }
4059
4060 /*
4061  * It executes link_update after knowing an interrupt occurred.
4062  *
4063  * @param dev
4064  *  Pointer to struct rte_eth_dev.
4065  *
4066  * @return
4067  *  - On success, zero.
4068  *  - On failure, a negative value.
4069  */
4070 static int
4071 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4072                            struct rte_intr_handle *intr_handle)
4073 {
4074         struct ixgbe_interrupt *intr =
4075                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4076         int64_t timeout;
4077         struct rte_eth_link link;
4078         struct ixgbe_hw *hw =
4079                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4080
4081         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4082
4083         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4084                 ixgbe_pf_mbx_process(dev);
4085                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4086         }
4087
4088         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4089                 ixgbe_handle_lasi(hw);
4090                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4091         }
4092
4093         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4094                 /* get the link status before link update, for predicting later */
4095                 memset(&link, 0, sizeof(link));
4096                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4097
4098                 ixgbe_dev_link_update(dev, 0);
4099
4100                 /* likely to up */
4101                 if (!link.link_status)
4102                         /* handle it 1 sec later, wait it being stable */
4103                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4104                 /* likely to down */
4105                 else
4106                         /* handle it 4 sec later, wait it being stable */
4107                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4108
4109                 ixgbe_dev_link_status_print(dev);
4110                 intr->mask_original = intr->mask;
4111                 /* only disable lsc interrupt */
4112                 intr->mask &= ~IXGBE_EIMS_LSC;
4113                 if (rte_eal_alarm_set(timeout * 1000,
4114                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4115                         PMD_DRV_LOG(ERR, "Error setting alarm");
4116                 else
4117                         intr->mask = intr->mask_original;
4118         }
4119
4120         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4121         ixgbe_enable_intr(dev);
4122         rte_intr_enable(intr_handle);
4123
4124         return 0;
4125 }
4126
4127 /**
4128  * Interrupt handler which shall be registered for alarm callback for delayed
4129  * handling specific interrupt to wait for the stable nic state. As the
4130  * NIC interrupt state is not stable for ixgbe after link is just down,
4131  * it needs to wait 4 seconds to get the stable status.
4132  *
4133  * @param handle
4134  *  Pointer to interrupt handle.
4135  * @param param
4136  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4137  *
4138  * @return
4139  *  void
4140  */
4141 static void
4142 ixgbe_dev_interrupt_delayed_handler(void *param)
4143 {
4144         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4145         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4146         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4147         struct ixgbe_interrupt *intr =
4148                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4149         struct ixgbe_hw *hw =
4150                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4151         uint32_t eicr;
4152
4153         ixgbe_disable_intr(hw);
4154
4155         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4156         if (eicr & IXGBE_EICR_MAILBOX)
4157                 ixgbe_pf_mbx_process(dev);
4158
4159         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4160                 ixgbe_handle_lasi(hw);
4161                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4162         }
4163
4164         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4165                 ixgbe_dev_link_update(dev, 0);
4166                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4167                 ixgbe_dev_link_status_print(dev);
4168                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4169         }
4170
4171         if (intr->flags & IXGBE_FLAG_MACSEC) {
4172                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4173                                               NULL);
4174                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4175         }
4176
4177         /* restore original mask */
4178         intr->mask = intr->mask_original;
4179         intr->mask_original = 0;
4180
4181         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4182         ixgbe_enable_intr(dev);
4183         rte_intr_enable(intr_handle);
4184 }
4185
4186 /**
4187  * Interrupt handler triggered by NIC  for handling
4188  * specific interrupt.
4189  *
4190  * @param handle
4191  *  Pointer to interrupt handle.
4192  * @param param
4193  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4194  *
4195  * @return
4196  *  void
4197  */
4198 static void
4199 ixgbe_dev_interrupt_handler(void *param)
4200 {
4201         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4202
4203         ixgbe_dev_interrupt_get_status(dev);
4204         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4205 }
4206
4207 static int
4208 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4209 {
4210         struct ixgbe_hw *hw;
4211
4212         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4213         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4214 }
4215
4216 static int
4217 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4218 {
4219         struct ixgbe_hw *hw;
4220
4221         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4222         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4223 }
4224
4225 static int
4226 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4227 {
4228         struct ixgbe_hw *hw;
4229         uint32_t mflcn_reg;
4230         uint32_t fccfg_reg;
4231         int rx_pause;
4232         int tx_pause;
4233
4234         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4235
4236         fc_conf->pause_time = hw->fc.pause_time;
4237         fc_conf->high_water = hw->fc.high_water[0];
4238         fc_conf->low_water = hw->fc.low_water[0];
4239         fc_conf->send_xon = hw->fc.send_xon;
4240         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4241
4242         /*
4243          * Return rx_pause status according to actual setting of
4244          * MFLCN register.
4245          */
4246         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4247         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4248                 rx_pause = 1;
4249         else
4250                 rx_pause = 0;
4251
4252         /*
4253          * Return tx_pause status according to actual setting of
4254          * FCCFG register.
4255          */
4256         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4257         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4258                 tx_pause = 1;
4259         else
4260                 tx_pause = 0;
4261
4262         if (rx_pause && tx_pause)
4263                 fc_conf->mode = RTE_FC_FULL;
4264         else if (rx_pause)
4265                 fc_conf->mode = RTE_FC_RX_PAUSE;
4266         else if (tx_pause)
4267                 fc_conf->mode = RTE_FC_TX_PAUSE;
4268         else
4269                 fc_conf->mode = RTE_FC_NONE;
4270
4271         return 0;
4272 }
4273
4274 static int
4275 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4276 {
4277         struct ixgbe_hw *hw;
4278         int err;
4279         uint32_t rx_buf_size;
4280         uint32_t max_high_water;
4281         uint32_t mflcn;
4282         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4283                 ixgbe_fc_none,
4284                 ixgbe_fc_rx_pause,
4285                 ixgbe_fc_tx_pause,
4286                 ixgbe_fc_full
4287         };
4288
4289         PMD_INIT_FUNC_TRACE();
4290
4291         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4292         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4293         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4294
4295         /*
4296          * At least reserve one Ethernet frame for watermark
4297          * high_water/low_water in kilo bytes for ixgbe
4298          */
4299         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4300         if ((fc_conf->high_water > max_high_water) ||
4301                 (fc_conf->high_water < fc_conf->low_water)) {
4302                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4303                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4304                 return -EINVAL;
4305         }
4306
4307         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4308         hw->fc.pause_time     = fc_conf->pause_time;
4309         hw->fc.high_water[0]  = fc_conf->high_water;
4310         hw->fc.low_water[0]   = fc_conf->low_water;
4311         hw->fc.send_xon       = fc_conf->send_xon;
4312         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4313
4314         err = ixgbe_fc_enable(hw);
4315
4316         /* Not negotiated is not an error case */
4317         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4318
4319                 /* check if we want to forward MAC frames - driver doesn't have native
4320                  * capability to do that, so we'll write the registers ourselves */
4321
4322                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4323
4324                 /* set or clear MFLCN.PMCF bit depending on configuration */
4325                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4326                         mflcn |= IXGBE_MFLCN_PMCF;
4327                 else
4328                         mflcn &= ~IXGBE_MFLCN_PMCF;
4329
4330                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4331                 IXGBE_WRITE_FLUSH(hw);
4332
4333                 return 0;
4334         }
4335
4336         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4337         return -EIO;
4338 }
4339
4340 /**
4341  *  ixgbe_pfc_enable_generic - Enable flow control
4342  *  @hw: pointer to hardware structure
4343  *  @tc_num: traffic class number
4344  *  Enable flow control according to the current settings.
4345  */
4346 static int
4347 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4348 {
4349         int ret_val = 0;
4350         uint32_t mflcn_reg, fccfg_reg;
4351         uint32_t reg;
4352         uint32_t fcrtl, fcrth;
4353         uint8_t i;
4354         uint8_t nb_rx_en;
4355
4356         /* Validate the water mark configuration */
4357         if (!hw->fc.pause_time) {
4358                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4359                 goto out;
4360         }
4361
4362         /* Low water mark of zero causes XOFF floods */
4363         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4364                  /* High/Low water can not be 0 */
4365                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4366                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4367                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4368                         goto out;
4369                 }
4370
4371                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4372                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4373                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4374                         goto out;
4375                 }
4376         }
4377         /* Negotiate the fc mode to use */
4378         ixgbe_fc_autoneg(hw);
4379
4380         /* Disable any previous flow control settings */
4381         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4382         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4383
4384         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4385         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4386
4387         switch (hw->fc.current_mode) {
4388         case ixgbe_fc_none:
4389                 /*
4390                  * If the count of enabled RX Priority Flow control >1,
4391                  * and the TX pause can not be disabled
4392                  */
4393                 nb_rx_en = 0;
4394                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4395                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4396                         if (reg & IXGBE_FCRTH_FCEN)
4397                                 nb_rx_en++;
4398                 }
4399                 if (nb_rx_en > 1)
4400                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4401                 break;
4402         case ixgbe_fc_rx_pause:
4403                 /*
4404                  * Rx Flow control is enabled and Tx Flow control is
4405                  * disabled by software override. Since there really
4406                  * isn't a way to advertise that we are capable of RX
4407                  * Pause ONLY, we will advertise that we support both
4408                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4409                  * disable the adapter's ability to send PAUSE frames.
4410                  */
4411                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4412                 /*
4413                  * If the count of enabled RX Priority Flow control >1,
4414                  * and the TX pause can not be disabled
4415                  */
4416                 nb_rx_en = 0;
4417                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4418                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4419                         if (reg & IXGBE_FCRTH_FCEN)
4420                                 nb_rx_en++;
4421                 }
4422                 if (nb_rx_en > 1)
4423                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4424                 break;
4425         case ixgbe_fc_tx_pause:
4426                 /*
4427                  * Tx Flow control is enabled, and Rx Flow control is
4428                  * disabled by software override.
4429                  */
4430                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4431                 break;
4432         case ixgbe_fc_full:
4433                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4434                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4435                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4436                 break;
4437         default:
4438                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4439                 ret_val = IXGBE_ERR_CONFIG;
4440                 goto out;
4441         }
4442
4443         /* Set 802.3x based flow control settings. */
4444         mflcn_reg |= IXGBE_MFLCN_DPF;
4445         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4446         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4447
4448         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4449         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4450                 hw->fc.high_water[tc_num]) {
4451                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4452                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4453                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4454         } else {
4455                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4456                 /*
4457                  * In order to prevent Tx hangs when the internal Tx
4458                  * switch is enabled we must set the high water mark
4459                  * to the maximum FCRTH value.  This allows the Tx
4460                  * switch to function even under heavy Rx workloads.
4461                  */
4462                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4463         }
4464         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4465
4466         /* Configure pause time (2 TCs per register) */
4467         reg = hw->fc.pause_time * 0x00010001;
4468         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4469                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4470
4471         /* Configure flow control refresh threshold value */
4472         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4473
4474 out:
4475         return ret_val;
4476 }
4477
4478 static int
4479 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4480 {
4481         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4482         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4483
4484         if (hw->mac.type != ixgbe_mac_82598EB) {
4485                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4486         }
4487         return ret_val;
4488 }
4489
4490 static int
4491 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4492 {
4493         int err;
4494         uint32_t rx_buf_size;
4495         uint32_t max_high_water;
4496         uint8_t tc_num;
4497         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4498         struct ixgbe_hw *hw =
4499                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4500         struct ixgbe_dcb_config *dcb_config =
4501                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4502
4503         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4504                 ixgbe_fc_none,
4505                 ixgbe_fc_rx_pause,
4506                 ixgbe_fc_tx_pause,
4507                 ixgbe_fc_full
4508         };
4509
4510         PMD_INIT_FUNC_TRACE();
4511
4512         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4513         tc_num = map[pfc_conf->priority];
4514         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4515         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4516         /*
4517          * At least reserve one Ethernet frame for watermark
4518          * high_water/low_water in kilo bytes for ixgbe
4519          */
4520         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4521         if ((pfc_conf->fc.high_water > max_high_water) ||
4522             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4523                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4524                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4525                 return -EINVAL;
4526         }
4527
4528         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4529         hw->fc.pause_time = pfc_conf->fc.pause_time;
4530         hw->fc.send_xon = pfc_conf->fc.send_xon;
4531         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4532         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4533
4534         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4535
4536         /* Not negotiated is not an error case */
4537         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4538                 return 0;
4539
4540         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4541         return -EIO;
4542 }
4543
4544 static int
4545 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4546                           struct rte_eth_rss_reta_entry64 *reta_conf,
4547                           uint16_t reta_size)
4548 {
4549         uint16_t i, sp_reta_size;
4550         uint8_t j, mask;
4551         uint32_t reta, r;
4552         uint16_t idx, shift;
4553         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4554         uint32_t reta_reg;
4555
4556         PMD_INIT_FUNC_TRACE();
4557
4558         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4559                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4560                         "NIC.");
4561                 return -ENOTSUP;
4562         }
4563
4564         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4565         if (reta_size != sp_reta_size) {
4566                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4567                         "(%d) doesn't match the number hardware can supported "
4568                         "(%d)", reta_size, sp_reta_size);
4569                 return -EINVAL;
4570         }
4571
4572         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4573                 idx = i / RTE_RETA_GROUP_SIZE;
4574                 shift = i % RTE_RETA_GROUP_SIZE;
4575                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4576                                                 IXGBE_4_BIT_MASK);
4577                 if (!mask)
4578                         continue;
4579                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4580                 if (mask == IXGBE_4_BIT_MASK)
4581                         r = 0;
4582                 else
4583                         r = IXGBE_READ_REG(hw, reta_reg);
4584                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4585                         if (mask & (0x1 << j))
4586                                 reta |= reta_conf[idx].reta[shift + j] <<
4587                                                         (CHAR_BIT * j);
4588                         else
4589                                 reta |= r & (IXGBE_8_BIT_MASK <<
4590                                                 (CHAR_BIT * j));
4591                 }
4592                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4593         }
4594
4595         return 0;
4596 }
4597
4598 static int
4599 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4600                          struct rte_eth_rss_reta_entry64 *reta_conf,
4601                          uint16_t reta_size)
4602 {
4603         uint16_t i, sp_reta_size;
4604         uint8_t j, mask;
4605         uint32_t reta;
4606         uint16_t idx, shift;
4607         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4608         uint32_t reta_reg;
4609
4610         PMD_INIT_FUNC_TRACE();
4611         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4612         if (reta_size != sp_reta_size) {
4613                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4614                         "(%d) doesn't match the number hardware can supported "
4615                         "(%d)", reta_size, sp_reta_size);
4616                 return -EINVAL;
4617         }
4618
4619         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4620                 idx = i / RTE_RETA_GROUP_SIZE;
4621                 shift = i % RTE_RETA_GROUP_SIZE;
4622                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4623                                                 IXGBE_4_BIT_MASK);
4624                 if (!mask)
4625                         continue;
4626
4627                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4628                 reta = IXGBE_READ_REG(hw, reta_reg);
4629                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4630                         if (mask & (0x1 << j))
4631                                 reta_conf[idx].reta[shift + j] =
4632                                         ((reta >> (CHAR_BIT * j)) &
4633                                                 IXGBE_8_BIT_MASK);
4634                 }
4635         }
4636
4637         return 0;
4638 }
4639
4640 static void
4641 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4642                                 uint32_t index, uint32_t pool)
4643 {
4644         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4645         uint32_t enable_addr = 1;
4646
4647         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4648 }
4649
4650 static void
4651 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4652 {
4653         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4654
4655         ixgbe_clear_rar(hw, index);
4656 }
4657
4658 static void
4659 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4660 {
4661         ixgbe_remove_rar(dev, 0);
4662
4663         ixgbe_add_rar(dev, addr, 0, 0);
4664 }
4665
4666 static bool
4667 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4668 {
4669         if (strcmp(dev->data->drv_name, drv->driver.name))
4670                 return false;
4671
4672         return true;
4673 }
4674
4675 bool
4676 is_ixgbe_supported(struct rte_eth_dev *dev)
4677 {
4678         return is_device_supported(dev, &rte_ixgbe_pmd);
4679 }
4680
4681 static int
4682 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4683 {
4684         uint32_t hlreg0;
4685         uint32_t maxfrs;
4686         struct ixgbe_hw *hw;
4687         struct rte_eth_dev_info dev_info;
4688         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4689
4690         ixgbe_dev_info_get(dev, &dev_info);
4691
4692         /* check that mtu is within the allowed range */
4693         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4694                 return -EINVAL;
4695
4696         /* refuse mtu that requires the support of scattered packets when this
4697          * feature has not been enabled before.
4698          */
4699         if (!dev->data->scattered_rx &&
4700             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4701              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4702                 return -EINVAL;
4703
4704         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4705         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4706
4707         /* switch to jumbo mode if needed */
4708         if (frame_size > ETHER_MAX_LEN) {
4709                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4710                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4711         } else {
4712                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4713                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4714         }
4715         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4716
4717         /* update max frame size */
4718         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4719
4720         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4721         maxfrs &= 0x0000FFFF;
4722         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4723         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4724
4725         return 0;
4726 }
4727
4728 /*
4729  * Virtual Function operations
4730  */
4731 static void
4732 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4733 {
4734         PMD_INIT_FUNC_TRACE();
4735
4736         /* Clear interrupt mask to stop from interrupts being generated */
4737         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4738
4739         IXGBE_WRITE_FLUSH(hw);
4740 }
4741
4742 static void
4743 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4744 {
4745         PMD_INIT_FUNC_TRACE();
4746
4747         /* VF enable interrupt autoclean */
4748         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4749         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4750         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4751
4752         IXGBE_WRITE_FLUSH(hw);
4753 }
4754
4755 static int
4756 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4757 {
4758         struct rte_eth_conf *conf = &dev->data->dev_conf;
4759         struct ixgbe_adapter *adapter =
4760                         (struct ixgbe_adapter *)dev->data->dev_private;
4761
4762         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4763                      dev->data->port_id);
4764
4765         /*
4766          * VF has no ability to enable/disable HW CRC
4767          * Keep the persistent behavior the same as Host PF
4768          */
4769 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4770         if (!conf->rxmode.hw_strip_crc) {
4771                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4772                 conf->rxmode.hw_strip_crc = 1;
4773         }
4774 #else
4775         if (conf->rxmode.hw_strip_crc) {
4776                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4777                 conf->rxmode.hw_strip_crc = 0;
4778         }
4779 #endif
4780
4781         /*
4782          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4783          * allocation or vector Rx preconditions we will reset it.
4784          */
4785         adapter->rx_bulk_alloc_allowed = true;
4786         adapter->rx_vec_allowed = true;
4787
4788         return 0;
4789 }
4790
4791 static int
4792 ixgbevf_dev_start(struct rte_eth_dev *dev)
4793 {
4794         struct ixgbe_hw *hw =
4795                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4796         uint32_t intr_vector = 0;
4797         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4798         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4799
4800         int err, mask = 0;
4801
4802         PMD_INIT_FUNC_TRACE();
4803
4804         hw->mac.ops.reset_hw(hw);
4805         hw->mac.get_link_status = true;
4806
4807         /* negotiate mailbox API version to use with the PF. */
4808         ixgbevf_negotiate_api(hw);
4809
4810         ixgbevf_dev_tx_init(dev);
4811
4812         /* This can fail when allocating mbufs for descriptor rings */
4813         err = ixgbevf_dev_rx_init(dev);
4814         if (err) {
4815                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4816                 ixgbe_dev_clear_queues(dev);
4817                 return err;
4818         }
4819
4820         /* Set vfta */
4821         ixgbevf_set_vfta_all(dev, 1);
4822
4823         /* Set HW strip */
4824         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4825                 ETH_VLAN_EXTEND_MASK;
4826         ixgbevf_vlan_offload_set(dev, mask);
4827
4828         ixgbevf_dev_rxtx_start(dev);
4829
4830         /* check and configure queue intr-vector mapping */
4831         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4832                 intr_vector = dev->data->nb_rx_queues;
4833                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4834                         return -1;
4835         }
4836
4837         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4838                 intr_handle->intr_vec =
4839                         rte_zmalloc("intr_vec",
4840                                     dev->data->nb_rx_queues * sizeof(int), 0);
4841                 if (intr_handle->intr_vec == NULL) {
4842                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4843                                      " intr_vec", dev->data->nb_rx_queues);
4844                         return -ENOMEM;
4845                 }
4846         }
4847         ixgbevf_configure_msix(dev);
4848
4849         rte_intr_enable(intr_handle);
4850
4851         /* Re-enable interrupt for VF */
4852         ixgbevf_intr_enable(hw);
4853
4854         return 0;
4855 }
4856
4857 static void
4858 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4859 {
4860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4861         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4862         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4863
4864         PMD_INIT_FUNC_TRACE();
4865
4866         ixgbevf_intr_disable(hw);
4867
4868         hw->adapter_stopped = 1;
4869         ixgbe_stop_adapter(hw);
4870
4871         /*
4872           * Clear what we set, but we still keep shadow_vfta to
4873           * restore after device starts
4874           */
4875         ixgbevf_set_vfta_all(dev, 0);
4876
4877         /* Clear stored conf */
4878         dev->data->scattered_rx = 0;
4879
4880         ixgbe_dev_clear_queues(dev);
4881
4882         /* Clean datapath event and queue/vec mapping */
4883         rte_intr_efd_disable(intr_handle);
4884         if (intr_handle->intr_vec != NULL) {
4885                 rte_free(intr_handle->intr_vec);
4886                 intr_handle->intr_vec = NULL;
4887         }
4888 }
4889
4890 static void
4891 ixgbevf_dev_close(struct rte_eth_dev *dev)
4892 {
4893         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4894
4895         PMD_INIT_FUNC_TRACE();
4896
4897         ixgbe_reset_hw(hw);
4898
4899         ixgbevf_dev_stop(dev);
4900
4901         ixgbe_dev_free_queues(dev);
4902
4903         /**
4904          * Remove the VF MAC address ro ensure
4905          * that the VF traffic goes to the PF
4906          * after stop, close and detach of the VF
4907          **/
4908         ixgbevf_remove_mac_addr(dev, 0);
4909 }
4910
4911 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4912 {
4913         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4914         struct ixgbe_vfta *shadow_vfta =
4915                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4916         int i = 0, j = 0, vfta = 0, mask = 1;
4917
4918         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4919                 vfta = shadow_vfta->vfta[i];
4920                 if (vfta) {
4921                         mask = 1;
4922                         for (j = 0; j < 32; j++) {
4923                                 if (vfta & mask)
4924                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4925                                                        on, false);
4926                                 mask <<= 1;
4927                         }
4928                 }
4929         }
4930
4931 }
4932
4933 static int
4934 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4935 {
4936         struct ixgbe_hw *hw =
4937                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4938         struct ixgbe_vfta *shadow_vfta =
4939                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4940         uint32_t vid_idx = 0;
4941         uint32_t vid_bit = 0;
4942         int ret = 0;
4943
4944         PMD_INIT_FUNC_TRACE();
4945
4946         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4947         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4948         if (ret) {
4949                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4950                 return ret;
4951         }
4952         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4953         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4954
4955         /* Save what we set and retore it after device reset */
4956         if (on)
4957                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4958         else
4959                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4960
4961         return 0;
4962 }
4963
4964 static void
4965 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4966 {
4967         struct ixgbe_hw *hw =
4968                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4969         uint32_t ctrl;
4970
4971         PMD_INIT_FUNC_TRACE();
4972
4973         if (queue >= hw->mac.max_rx_queues)
4974                 return;
4975
4976         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4977         if (on)
4978                 ctrl |= IXGBE_RXDCTL_VME;
4979         else
4980                 ctrl &= ~IXGBE_RXDCTL_VME;
4981         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4982
4983         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4984 }
4985
4986 static void
4987 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4988 {
4989         struct ixgbe_hw *hw =
4990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4991         uint16_t i;
4992         int on = 0;
4993
4994         /* VF function only support hw strip feature, others are not support */
4995         if (mask & ETH_VLAN_STRIP_MASK) {
4996                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4997
4998                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4999                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5000         }
5001 }
5002
5003 int
5004 ixgbe_vt_check(struct ixgbe_hw *hw)
5005 {
5006         uint32_t reg_val;
5007
5008         /* if Virtualization Technology is enabled */
5009         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5010         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5011                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5012                 return -1;
5013         }
5014
5015         return 0;
5016 }
5017
5018 static uint32_t
5019 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5020 {
5021         uint32_t vector = 0;
5022
5023         switch (hw->mac.mc_filter_type) {
5024         case 0:   /* use bits [47:36] of the address */
5025                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5026                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5027                 break;
5028         case 1:   /* use bits [46:35] of the address */
5029                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5030                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5031                 break;
5032         case 2:   /* use bits [45:34] of the address */
5033                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5034                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5035                 break;
5036         case 3:   /* use bits [43:32] of the address */
5037                 vector = ((uc_addr->addr_bytes[4]) |
5038                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5039                 break;
5040         default:  /* Invalid mc_filter_type */
5041                 break;
5042         }
5043
5044         /* vector can only be 12-bits or boundary will be exceeded */
5045         vector &= 0xFFF;
5046         return vector;
5047 }
5048
5049 static int
5050 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5051                         uint8_t on)
5052 {
5053         uint32_t vector;
5054         uint32_t uta_idx;
5055         uint32_t reg_val;
5056         uint32_t uta_shift;
5057         uint32_t rc;
5058         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5059         const uint32_t ixgbe_uta_bit_shift = 5;
5060         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5061         const uint32_t bit1 = 0x1;
5062
5063         struct ixgbe_hw *hw =
5064                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5065         struct ixgbe_uta_info *uta_info =
5066                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5067
5068         /* The UTA table only exists on 82599 hardware and newer */
5069         if (hw->mac.type < ixgbe_mac_82599EB)
5070                 return -ENOTSUP;
5071
5072         vector = ixgbe_uta_vector(hw, mac_addr);
5073         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5074         uta_shift = vector & ixgbe_uta_bit_mask;
5075
5076         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5077         if (rc == on)
5078                 return 0;
5079
5080         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5081         if (on) {
5082                 uta_info->uta_in_use++;
5083                 reg_val |= (bit1 << uta_shift);
5084                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5085         } else {
5086                 uta_info->uta_in_use--;
5087                 reg_val &= ~(bit1 << uta_shift);
5088                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5089         }
5090
5091         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5092
5093         if (uta_info->uta_in_use > 0)
5094                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5095                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5096         else
5097                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5098
5099         return 0;
5100 }
5101
5102 static int
5103 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5104 {
5105         int i;
5106         struct ixgbe_hw *hw =
5107                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5108         struct ixgbe_uta_info *uta_info =
5109                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5110
5111         /* The UTA table only exists on 82599 hardware and newer */
5112         if (hw->mac.type < ixgbe_mac_82599EB)
5113                 return -ENOTSUP;
5114
5115         if (on) {
5116                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5117                         uta_info->uta_shadow[i] = ~0;
5118                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5119                 }
5120         } else {
5121                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5122                         uta_info->uta_shadow[i] = 0;
5123                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5124                 }
5125         }
5126         return 0;
5127
5128 }
5129
5130 uint32_t
5131 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5132 {
5133         uint32_t new_val = orig_val;
5134
5135         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5136                 new_val |= IXGBE_VMOLR_AUPE;
5137         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5138                 new_val |= IXGBE_VMOLR_ROMPE;
5139         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5140                 new_val |= IXGBE_VMOLR_ROPE;
5141         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5142                 new_val |= IXGBE_VMOLR_BAM;
5143         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5144                 new_val |= IXGBE_VMOLR_MPE;
5145
5146         return new_val;
5147 }
5148
5149 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5150 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5151 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5152 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5153 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5154         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5155         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5156
5157 static int
5158 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5159                       struct rte_eth_mirror_conf *mirror_conf,
5160                       uint8_t rule_id, uint8_t on)
5161 {
5162         uint32_t mr_ctl, vlvf;
5163         uint32_t mp_lsb = 0;
5164         uint32_t mv_msb = 0;
5165         uint32_t mv_lsb = 0;
5166         uint32_t mp_msb = 0;
5167         uint8_t i = 0;
5168         int reg_index = 0;
5169         uint64_t vlan_mask = 0;
5170
5171         const uint8_t pool_mask_offset = 32;
5172         const uint8_t vlan_mask_offset = 32;
5173         const uint8_t dst_pool_offset = 8;
5174         const uint8_t rule_mr_offset  = 4;
5175         const uint8_t mirror_rule_mask = 0x0F;
5176
5177         struct ixgbe_mirror_info *mr_info =
5178                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5179         struct ixgbe_hw *hw =
5180                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5181         uint8_t mirror_type = 0;
5182
5183         if (ixgbe_vt_check(hw) < 0)
5184                 return -ENOTSUP;
5185
5186         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5187                 return -EINVAL;
5188
5189         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5190                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5191                             mirror_conf->rule_type);
5192                 return -EINVAL;
5193         }
5194
5195         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5196                 mirror_type |= IXGBE_MRCTL_VLME;
5197                 /* Check if vlan id is valid and find conresponding VLAN ID
5198                  * index in VLVF
5199                  */
5200                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5201                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5202                                 /* search vlan id related pool vlan filter
5203                                  * index
5204                                  */
5205                                 reg_index = ixgbe_find_vlvf_slot(
5206                                                 hw,
5207                                                 mirror_conf->vlan.vlan_id[i],
5208                                                 false);
5209                                 if (reg_index < 0)
5210                                         return -EINVAL;
5211                                 vlvf = IXGBE_READ_REG(hw,
5212                                                       IXGBE_VLVF(reg_index));
5213                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5214                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5215                                       mirror_conf->vlan.vlan_id[i]))
5216                                         vlan_mask |= (1ULL << reg_index);
5217                                 else
5218                                         return -EINVAL;
5219                         }
5220                 }
5221
5222                 if (on) {
5223                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5224                         mv_msb = vlan_mask >> vlan_mask_offset;
5225
5226                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5227                                                 mirror_conf->vlan.vlan_mask;
5228                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5229                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5230                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5231                                                 mirror_conf->vlan.vlan_id[i];
5232                         }
5233                 } else {
5234                         mv_lsb = 0;
5235                         mv_msb = 0;
5236                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5237                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5238                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5239                 }
5240         }
5241
5242         /**
5243          * if enable pool mirror, write related pool mask register,if disable
5244          * pool mirror, clear PFMRVM register
5245          */
5246         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5247                 mirror_type |= IXGBE_MRCTL_VPME;
5248                 if (on) {
5249                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5250                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5251                         mr_info->mr_conf[rule_id].pool_mask =
5252                                         mirror_conf->pool_mask;
5253
5254                 } else {
5255                         mp_lsb = 0;
5256                         mp_msb = 0;
5257                         mr_info->mr_conf[rule_id].pool_mask = 0;
5258                 }
5259         }
5260         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5261                 mirror_type |= IXGBE_MRCTL_UPME;
5262         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5263                 mirror_type |= IXGBE_MRCTL_DPME;
5264
5265         /* read  mirror control register and recalculate it */
5266         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5267
5268         if (on) {
5269                 mr_ctl |= mirror_type;
5270                 mr_ctl &= mirror_rule_mask;
5271                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5272         } else {
5273                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5274         }
5275
5276         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5277         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5278
5279         /* write mirrror control  register */
5280         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5281
5282         /* write pool mirrror control  register */
5283         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5284                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5285                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5286                                 mp_msb);
5287         }
5288         /* write VLAN mirrror control  register */
5289         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5290                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5291                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5292                                 mv_msb);
5293         }
5294
5295         return 0;
5296 }
5297
5298 static int
5299 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5300 {
5301         int mr_ctl = 0;
5302         uint32_t lsb_val = 0;
5303         uint32_t msb_val = 0;
5304         const uint8_t rule_mr_offset = 4;
5305
5306         struct ixgbe_hw *hw =
5307                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5308         struct ixgbe_mirror_info *mr_info =
5309                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5310
5311         if (ixgbe_vt_check(hw) < 0)
5312                 return -ENOTSUP;
5313
5314         memset(&mr_info->mr_conf[rule_id], 0,
5315                sizeof(struct rte_eth_mirror_conf));
5316
5317         /* clear PFVMCTL register */
5318         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5319
5320         /* clear pool mask register */
5321         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5322         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5323
5324         /* clear vlan mask register */
5325         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5326         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5327
5328         return 0;
5329 }
5330
5331 static int
5332 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5333 {
5334         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5335         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5336         uint32_t mask;
5337         struct ixgbe_hw *hw =
5338                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5339
5340         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5341         mask |= (1 << IXGBE_MISC_VEC_ID);
5342         RTE_SET_USED(queue_id);
5343         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5344
5345         rte_intr_enable(intr_handle);
5346
5347         return 0;
5348 }
5349
5350 static int
5351 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5352 {
5353         uint32_t mask;
5354         struct ixgbe_hw *hw =
5355                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5356
5357         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5358         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5359         RTE_SET_USED(queue_id);
5360         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5361
5362         return 0;
5363 }
5364
5365 static int
5366 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5367 {
5368         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5369         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5370         uint32_t mask;
5371         struct ixgbe_hw *hw =
5372                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5373         struct ixgbe_interrupt *intr =
5374                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5375
5376         if (queue_id < 16) {
5377                 ixgbe_disable_intr(hw);
5378                 intr->mask |= (1 << queue_id);
5379                 ixgbe_enable_intr(dev);
5380         } else if (queue_id < 32) {
5381                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5382                 mask &= (1 << queue_id);
5383                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5384         } else if (queue_id < 64) {
5385                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5386                 mask &= (1 << (queue_id - 32));
5387                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5388         }
5389         rte_intr_enable(intr_handle);
5390
5391         return 0;
5392 }
5393
5394 static int
5395 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5396 {
5397         uint32_t mask;
5398         struct ixgbe_hw *hw =
5399                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5400         struct ixgbe_interrupt *intr =
5401                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5402
5403         if (queue_id < 16) {
5404                 ixgbe_disable_intr(hw);
5405                 intr->mask &= ~(1 << queue_id);
5406                 ixgbe_enable_intr(dev);
5407         } else if (queue_id < 32) {
5408                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5409                 mask &= ~(1 << queue_id);
5410                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5411         } else if (queue_id < 64) {
5412                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5413                 mask &= ~(1 << (queue_id - 32));
5414                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5415         }
5416
5417         return 0;
5418 }
5419
5420 static void
5421 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5422                      uint8_t queue, uint8_t msix_vector)
5423 {
5424         uint32_t tmp, idx;
5425
5426         if (direction == -1) {
5427                 /* other causes */
5428                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5429                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5430                 tmp &= ~0xFF;
5431                 tmp |= msix_vector;
5432                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5433         } else {
5434                 /* rx or tx cause */
5435                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5436                 idx = ((16 * (queue & 1)) + (8 * direction));
5437                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5438                 tmp &= ~(0xFF << idx);
5439                 tmp |= (msix_vector << idx);
5440                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5441         }
5442 }
5443
5444 /**
5445  * set the IVAR registers, mapping interrupt causes to vectors
5446  * @param hw
5447  *  pointer to ixgbe_hw struct
5448  * @direction
5449  *  0 for Rx, 1 for Tx, -1 for other causes
5450  * @queue
5451  *  queue to map the corresponding interrupt to
5452  * @msix_vector
5453  *  the vector to map to the corresponding queue
5454  */
5455 static void
5456 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5457                    uint8_t queue, uint8_t msix_vector)
5458 {
5459         uint32_t tmp, idx;
5460
5461         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5462         if (hw->mac.type == ixgbe_mac_82598EB) {
5463                 if (direction == -1)
5464                         direction = 0;
5465                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5466                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5467                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5468                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5469                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5470         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5471                         (hw->mac.type == ixgbe_mac_X540)) {
5472                 if (direction == -1) {
5473                         /* other causes */
5474                         idx = ((queue & 1) * 8);
5475                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5476                         tmp &= ~(0xFF << idx);
5477                         tmp |= (msix_vector << idx);
5478                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5479                 } else {
5480                         /* rx or tx causes */
5481                         idx = ((16 * (queue & 1)) + (8 * direction));
5482                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5483                         tmp &= ~(0xFF << idx);
5484                         tmp |= (msix_vector << idx);
5485                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5486                 }
5487         }
5488 }
5489
5490 static void
5491 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5492 {
5493         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5494         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5495         struct ixgbe_hw *hw =
5496                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5497         uint32_t q_idx;
5498         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5499
5500         /* Configure VF other cause ivar */
5501         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5502
5503         /* won't configure msix register if no mapping is done
5504          * between intr vector and event fd.
5505          */
5506         if (!rte_intr_dp_is_en(intr_handle))
5507                 return;
5508
5509         /* Configure all RX queues of VF */
5510         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5511                 /* Force all queue use vector 0,
5512                  * as IXGBE_VF_MAXMSIVECOTR = 1
5513                  */
5514                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5515                 intr_handle->intr_vec[q_idx] = vector_idx;
5516         }
5517 }
5518
5519 /**
5520  * Sets up the hardware to properly generate MSI-X interrupts
5521  * @hw
5522  *  board private structure
5523  */
5524 static void
5525 ixgbe_configure_msix(struct rte_eth_dev *dev)
5526 {
5527         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5528         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5529         struct ixgbe_hw *hw =
5530                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5531         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5532         uint32_t vec = IXGBE_MISC_VEC_ID;
5533         uint32_t mask;
5534         uint32_t gpie;
5535
5536         /* won't configure msix register if no mapping is done
5537          * between intr vector and event fd
5538          */
5539         if (!rte_intr_dp_is_en(intr_handle))
5540                 return;
5541
5542         if (rte_intr_allow_others(intr_handle))
5543                 vec = base = IXGBE_RX_VEC_START;
5544
5545         /* setup GPIE for MSI-x mode */
5546         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5547         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5548                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5549         /* auto clearing and auto setting corresponding bits in EIMS
5550          * when MSI-X interrupt is triggered
5551          */
5552         if (hw->mac.type == ixgbe_mac_82598EB) {
5553                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5554         } else {
5555                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5556                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5557         }
5558         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5559
5560         /* Populate the IVAR table and set the ITR values to the
5561          * corresponding register.
5562          */
5563         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5564              queue_id++) {
5565                 /* by default, 1:1 mapping */
5566                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5567                 intr_handle->intr_vec[queue_id] = vec;
5568                 if (vec < base + intr_handle->nb_efd - 1)
5569                         vec++;
5570         }
5571
5572         switch (hw->mac.type) {
5573         case ixgbe_mac_82598EB:
5574                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5575                                    IXGBE_MISC_VEC_ID);
5576                 break;
5577         case ixgbe_mac_82599EB:
5578         case ixgbe_mac_X540:
5579                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5580                 break;
5581         default:
5582                 break;
5583         }
5584         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5585                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5586
5587         /* set up to autoclear timer, and the vectors */
5588         mask = IXGBE_EIMS_ENABLE_MASK;
5589         mask &= ~(IXGBE_EIMS_OTHER |
5590                   IXGBE_EIMS_MAILBOX |
5591                   IXGBE_EIMS_LSC);
5592
5593         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5594 }
5595
5596 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5597         uint16_t queue_idx, uint16_t tx_rate)
5598 {
5599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5600         uint32_t rf_dec, rf_int;
5601         uint32_t bcnrc_val;
5602         uint16_t link_speed = dev->data->dev_link.link_speed;
5603
5604         if (queue_idx >= hw->mac.max_tx_queues)
5605                 return -EINVAL;
5606
5607         if (tx_rate != 0) {
5608                 /* Calculate the rate factor values to set */
5609                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5610                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5611                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5612
5613                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5614                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5615                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5616                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5617         } else {
5618                 bcnrc_val = 0;
5619         }
5620
5621         /*
5622          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5623          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5624          * set as 0x4.
5625          */
5626         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5627                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5628                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5629                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5630                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5631         else
5632                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5633                         IXGBE_MMW_SIZE_DEFAULT);
5634
5635         /* Set RTTBCNRC of queue X */
5636         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5637         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5638         IXGBE_WRITE_FLUSH(hw);
5639
5640         return 0;
5641 }
5642
5643 static void
5644 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5645                      __attribute__((unused)) uint32_t index,
5646                      __attribute__((unused)) uint32_t pool)
5647 {
5648         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5649         int diag;
5650
5651         /*
5652          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5653          * operation. Trap this case to avoid exhausting the [very limited]
5654          * set of PF resources used to store VF MAC addresses.
5655          */
5656         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5657                 return;
5658         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5659         if (diag == 0)
5660                 return;
5661         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5662 }
5663
5664 static void
5665 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5666 {
5667         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5668         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5669         struct ether_addr *mac_addr;
5670         uint32_t i;
5671         int diag;
5672
5673         /*
5674          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5675          * not support the deletion of a given MAC address.
5676          * Instead, it imposes to delete all MAC addresses, then to add again
5677          * all MAC addresses with the exception of the one to be deleted.
5678          */
5679         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5680
5681         /*
5682          * Add again all MAC addresses, with the exception of the deleted one
5683          * and of the permanent MAC address.
5684          */
5685         for (i = 0, mac_addr = dev->data->mac_addrs;
5686              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5687                 /* Skip the deleted MAC address */
5688                 if (i == index)
5689                         continue;
5690                 /* Skip NULL MAC addresses */
5691                 if (is_zero_ether_addr(mac_addr))
5692                         continue;
5693                 /* Skip the permanent MAC address */
5694                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5695                         continue;
5696                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5697                 if (diag != 0)
5698                         PMD_DRV_LOG(ERR,
5699                                     "Adding again MAC address "
5700                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5701                                     "diag=%d",
5702                                     mac_addr->addr_bytes[0],
5703                                     mac_addr->addr_bytes[1],
5704                                     mac_addr->addr_bytes[2],
5705                                     mac_addr->addr_bytes[3],
5706                                     mac_addr->addr_bytes[4],
5707                                     mac_addr->addr_bytes[5],
5708                                     diag);
5709         }
5710 }
5711
5712 static void
5713 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5714 {
5715         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5716
5717         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5718 }
5719
5720 int
5721 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5722                         struct rte_eth_syn_filter *filter,
5723                         bool add)
5724 {
5725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5726         struct ixgbe_filter_info *filter_info =
5727                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5728         uint32_t syn_info;
5729         uint32_t synqf;
5730
5731         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5732                 return -EINVAL;
5733
5734         syn_info = filter_info->syn_info;
5735
5736         if (add) {
5737                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5738                         return -EINVAL;
5739                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5740                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5741
5742                 if (filter->hig_pri)
5743                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5744                 else
5745                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5746         } else {
5747                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5748                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5749                         return -ENOENT;
5750                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5751         }
5752
5753         filter_info->syn_info = synqf;
5754         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5755         IXGBE_WRITE_FLUSH(hw);
5756         return 0;
5757 }
5758
5759 static int
5760 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5761                         struct rte_eth_syn_filter *filter)
5762 {
5763         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5764         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5765
5766         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5767                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5768                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5769                 return 0;
5770         }
5771         return -ENOENT;
5772 }
5773
5774 static int
5775 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5776                         enum rte_filter_op filter_op,
5777                         void *arg)
5778 {
5779         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5780         int ret;
5781
5782         MAC_TYPE_FILTER_SUP(hw->mac.type);
5783
5784         if (filter_op == RTE_ETH_FILTER_NOP)
5785                 return 0;
5786
5787         if (arg == NULL) {
5788                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5789                             filter_op);
5790                 return -EINVAL;
5791         }
5792
5793         switch (filter_op) {
5794         case RTE_ETH_FILTER_ADD:
5795                 ret = ixgbe_syn_filter_set(dev,
5796                                 (struct rte_eth_syn_filter *)arg,
5797                                 TRUE);
5798                 break;
5799         case RTE_ETH_FILTER_DELETE:
5800                 ret = ixgbe_syn_filter_set(dev,
5801                                 (struct rte_eth_syn_filter *)arg,
5802                                 FALSE);
5803                 break;
5804         case RTE_ETH_FILTER_GET:
5805                 ret = ixgbe_syn_filter_get(dev,
5806                                 (struct rte_eth_syn_filter *)arg);
5807                 break;
5808         default:
5809                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5810                 ret = -EINVAL;
5811                 break;
5812         }
5813
5814         return ret;
5815 }
5816
5817
5818 static inline enum ixgbe_5tuple_protocol
5819 convert_protocol_type(uint8_t protocol_value)
5820 {
5821         if (protocol_value == IPPROTO_TCP)
5822                 return IXGBE_FILTER_PROTOCOL_TCP;
5823         else if (protocol_value == IPPROTO_UDP)
5824                 return IXGBE_FILTER_PROTOCOL_UDP;
5825         else if (protocol_value == IPPROTO_SCTP)
5826                 return IXGBE_FILTER_PROTOCOL_SCTP;
5827         else
5828                 return IXGBE_FILTER_PROTOCOL_NONE;
5829 }
5830
5831 /* inject a 5-tuple filter to HW */
5832 static inline void
5833 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5834                            struct ixgbe_5tuple_filter *filter)
5835 {
5836         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5837         int i;
5838         uint32_t ftqf, sdpqf;
5839         uint32_t l34timir = 0;
5840         uint8_t mask = 0xff;
5841
5842         i = filter->index;
5843
5844         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5845                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5846         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5847
5848         ftqf = (uint32_t)(filter->filter_info.proto &
5849                 IXGBE_FTQF_PROTOCOL_MASK);
5850         ftqf |= (uint32_t)((filter->filter_info.priority &
5851                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5852         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5853                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5854         if (filter->filter_info.dst_ip_mask == 0)
5855                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5856         if (filter->filter_info.src_port_mask == 0)
5857                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5858         if (filter->filter_info.dst_port_mask == 0)
5859                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5860         if (filter->filter_info.proto_mask == 0)
5861                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5862         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5863         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5864         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5865
5866         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5867         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5868         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5869         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5870
5871         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5872         l34timir |= (uint32_t)(filter->queue <<
5873                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5874         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5875 }
5876
5877 /*
5878  * add a 5tuple filter
5879  *
5880  * @param
5881  * dev: Pointer to struct rte_eth_dev.
5882  * index: the index the filter allocates.
5883  * filter: ponter to the filter that will be added.
5884  * rx_queue: the queue id the filter assigned to.
5885  *
5886  * @return
5887  *    - On success, zero.
5888  *    - On failure, a negative value.
5889  */
5890 static int
5891 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5892                         struct ixgbe_5tuple_filter *filter)
5893 {
5894         struct ixgbe_filter_info *filter_info =
5895                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5896         int i, idx, shift;
5897
5898         /*
5899          * look for an unused 5tuple filter index,
5900          * and insert the filter to list.
5901          */
5902         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5903                 idx = i / (sizeof(uint32_t) * NBBY);
5904                 shift = i % (sizeof(uint32_t) * NBBY);
5905                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5906                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5907                         filter->index = i;
5908                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5909                                           filter,
5910                                           entries);
5911                         break;
5912                 }
5913         }
5914         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5915                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5916                 return -ENOSYS;
5917         }
5918
5919         ixgbe_inject_5tuple_filter(dev, filter);
5920
5921         return 0;
5922 }
5923
5924 /*
5925  * remove a 5tuple filter
5926  *
5927  * @param
5928  * dev: Pointer to struct rte_eth_dev.
5929  * filter: the pointer of the filter will be removed.
5930  */
5931 static void
5932 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5933                         struct ixgbe_5tuple_filter *filter)
5934 {
5935         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5936         struct ixgbe_filter_info *filter_info =
5937                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5938         uint16_t index = filter->index;
5939
5940         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5941                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5942         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5943         rte_free(filter);
5944
5945         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5946         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5947         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5948         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5949         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5950 }
5951
5952 static int
5953 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5954 {
5955         struct ixgbe_hw *hw;
5956         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5957
5958         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5959
5960         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5961                 return -EINVAL;
5962
5963         /* refuse mtu that requires the support of scattered packets when this
5964          * feature has not been enabled before.
5965          */
5966         if (!dev->data->scattered_rx &&
5967             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5968              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5969                 return -EINVAL;
5970
5971         /*
5972          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5973          * request of the version 2.0 of the mailbox API.
5974          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5975          * of the mailbox API.
5976          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5977          * prior to 3.11.33 which contains the following change:
5978          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5979          */
5980         ixgbevf_rlpml_set_vf(hw, max_frame);
5981
5982         /* update max frame size */
5983         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5984         return 0;
5985 }
5986
5987 static inline struct ixgbe_5tuple_filter *
5988 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5989                         struct ixgbe_5tuple_filter_info *key)
5990 {
5991         struct ixgbe_5tuple_filter *it;
5992
5993         TAILQ_FOREACH(it, filter_list, entries) {
5994                 if (memcmp(key, &it->filter_info,
5995                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5996                         return it;
5997                 }
5998         }
5999         return NULL;
6000 }
6001
6002 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6003 static inline int
6004 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6005                         struct ixgbe_5tuple_filter_info *filter_info)
6006 {
6007         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6008                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6009                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6010                 return -EINVAL;
6011
6012         switch (filter->dst_ip_mask) {
6013         case UINT32_MAX:
6014                 filter_info->dst_ip_mask = 0;
6015                 filter_info->dst_ip = filter->dst_ip;
6016                 break;
6017         case 0:
6018                 filter_info->dst_ip_mask = 1;
6019                 break;
6020         default:
6021                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6022                 return -EINVAL;
6023         }
6024
6025         switch (filter->src_ip_mask) {
6026         case UINT32_MAX:
6027                 filter_info->src_ip_mask = 0;
6028                 filter_info->src_ip = filter->src_ip;
6029                 break;
6030         case 0:
6031                 filter_info->src_ip_mask = 1;
6032                 break;
6033         default:
6034                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6035                 return -EINVAL;
6036         }
6037
6038         switch (filter->dst_port_mask) {
6039         case UINT16_MAX:
6040                 filter_info->dst_port_mask = 0;
6041                 filter_info->dst_port = filter->dst_port;
6042                 break;
6043         case 0:
6044                 filter_info->dst_port_mask = 1;
6045                 break;
6046         default:
6047                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6048                 return -EINVAL;
6049         }
6050
6051         switch (filter->src_port_mask) {
6052         case UINT16_MAX:
6053                 filter_info->src_port_mask = 0;
6054                 filter_info->src_port = filter->src_port;
6055                 break;
6056         case 0:
6057                 filter_info->src_port_mask = 1;
6058                 break;
6059         default:
6060                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6061                 return -EINVAL;
6062         }
6063
6064         switch (filter->proto_mask) {
6065         case UINT8_MAX:
6066                 filter_info->proto_mask = 0;
6067                 filter_info->proto =
6068                         convert_protocol_type(filter->proto);
6069                 break;
6070         case 0:
6071                 filter_info->proto_mask = 1;
6072                 break;
6073         default:
6074                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6075                 return -EINVAL;
6076         }
6077
6078         filter_info->priority = (uint8_t)filter->priority;
6079         return 0;
6080 }
6081
6082 /*
6083  * add or delete a ntuple filter
6084  *
6085  * @param
6086  * dev: Pointer to struct rte_eth_dev.
6087  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6088  * add: if true, add filter, if false, remove filter
6089  *
6090  * @return
6091  *    - On success, zero.
6092  *    - On failure, a negative value.
6093  */
6094 int
6095 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6096                         struct rte_eth_ntuple_filter *ntuple_filter,
6097                         bool add)
6098 {
6099         struct ixgbe_filter_info *filter_info =
6100                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6101         struct ixgbe_5tuple_filter_info filter_5tuple;
6102         struct ixgbe_5tuple_filter *filter;
6103         int ret;
6104
6105         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6106                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6107                 return -EINVAL;
6108         }
6109
6110         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6111         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6112         if (ret < 0)
6113                 return ret;
6114
6115         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6116                                          &filter_5tuple);
6117         if (filter != NULL && add) {
6118                 PMD_DRV_LOG(ERR, "filter exists.");
6119                 return -EEXIST;
6120         }
6121         if (filter == NULL && !add) {
6122                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6123                 return -ENOENT;
6124         }
6125
6126         if (add) {
6127                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6128                                 sizeof(struct ixgbe_5tuple_filter), 0);
6129                 if (filter == NULL)
6130                         return -ENOMEM;
6131                 (void)rte_memcpy(&filter->filter_info,
6132                                  &filter_5tuple,
6133                                  sizeof(struct ixgbe_5tuple_filter_info));
6134                 filter->queue = ntuple_filter->queue;
6135                 ret = ixgbe_add_5tuple_filter(dev, filter);
6136                 if (ret < 0) {
6137                         rte_free(filter);
6138                         return ret;
6139                 }
6140         } else
6141                 ixgbe_remove_5tuple_filter(dev, filter);
6142
6143         return 0;
6144 }
6145
6146 /*
6147  * get a ntuple filter
6148  *
6149  * @param
6150  * dev: Pointer to struct rte_eth_dev.
6151  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6152  *
6153  * @return
6154  *    - On success, zero.
6155  *    - On failure, a negative value.
6156  */
6157 static int
6158 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6159                         struct rte_eth_ntuple_filter *ntuple_filter)
6160 {
6161         struct ixgbe_filter_info *filter_info =
6162                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6163         struct ixgbe_5tuple_filter_info filter_5tuple;
6164         struct ixgbe_5tuple_filter *filter;
6165         int ret;
6166
6167         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6168                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6169                 return -EINVAL;
6170         }
6171
6172         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6173         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6174         if (ret < 0)
6175                 return ret;
6176
6177         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6178                                          &filter_5tuple);
6179         if (filter == NULL) {
6180                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6181                 return -ENOENT;
6182         }
6183         ntuple_filter->queue = filter->queue;
6184         return 0;
6185 }
6186
6187 /*
6188  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6189  * @dev: pointer to rte_eth_dev structure
6190  * @filter_op:operation will be taken.
6191  * @arg: a pointer to specific structure corresponding to the filter_op
6192  *
6193  * @return
6194  *    - On success, zero.
6195  *    - On failure, a negative value.
6196  */
6197 static int
6198 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6199                                 enum rte_filter_op filter_op,
6200                                 void *arg)
6201 {
6202         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6203         int ret;
6204
6205         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6206
6207         if (filter_op == RTE_ETH_FILTER_NOP)
6208                 return 0;
6209
6210         if (arg == NULL) {
6211                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6212                             filter_op);
6213                 return -EINVAL;
6214         }
6215
6216         switch (filter_op) {
6217         case RTE_ETH_FILTER_ADD:
6218                 ret = ixgbe_add_del_ntuple_filter(dev,
6219                         (struct rte_eth_ntuple_filter *)arg,
6220                         TRUE);
6221                 break;
6222         case RTE_ETH_FILTER_DELETE:
6223                 ret = ixgbe_add_del_ntuple_filter(dev,
6224                         (struct rte_eth_ntuple_filter *)arg,
6225                         FALSE);
6226                 break;
6227         case RTE_ETH_FILTER_GET:
6228                 ret = ixgbe_get_ntuple_filter(dev,
6229                         (struct rte_eth_ntuple_filter *)arg);
6230                 break;
6231         default:
6232                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6233                 ret = -EINVAL;
6234                 break;
6235         }
6236         return ret;
6237 }
6238
6239 int
6240 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6241                         struct rte_eth_ethertype_filter *filter,
6242                         bool add)
6243 {
6244         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6245         struct ixgbe_filter_info *filter_info =
6246                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6247         uint32_t etqf = 0;
6248         uint32_t etqs = 0;
6249         int ret;
6250         struct ixgbe_ethertype_filter ethertype_filter;
6251
6252         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6253                 return -EINVAL;
6254
6255         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6256                 filter->ether_type == ETHER_TYPE_IPv6) {
6257                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6258                         " ethertype filter.", filter->ether_type);
6259                 return -EINVAL;
6260         }
6261
6262         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6263                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6264                 return -EINVAL;
6265         }
6266         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6267                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6268                 return -EINVAL;
6269         }
6270
6271         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6272         if (ret >= 0 && add) {
6273                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6274                             filter->ether_type);
6275                 return -EEXIST;
6276         }
6277         if (ret < 0 && !add) {
6278                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6279                             filter->ether_type);
6280                 return -ENOENT;
6281         }
6282
6283         if (add) {
6284                 etqf = IXGBE_ETQF_FILTER_EN;
6285                 etqf |= (uint32_t)filter->ether_type;
6286                 etqs |= (uint32_t)((filter->queue <<
6287                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6288                                     IXGBE_ETQS_RX_QUEUE);
6289                 etqs |= IXGBE_ETQS_QUEUE_EN;
6290
6291                 ethertype_filter.ethertype = filter->ether_type;
6292                 ethertype_filter.etqf = etqf;
6293                 ethertype_filter.etqs = etqs;
6294                 ethertype_filter.conf = FALSE;
6295                 ret = ixgbe_ethertype_filter_insert(filter_info,
6296                                                     &ethertype_filter);
6297                 if (ret < 0) {
6298                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6299                         return -ENOSPC;
6300                 }
6301         } else {
6302                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6303                 if (ret < 0)
6304                         return -ENOSYS;
6305         }
6306         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6307         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6308         IXGBE_WRITE_FLUSH(hw);
6309
6310         return 0;
6311 }
6312
6313 static int
6314 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6315                         struct rte_eth_ethertype_filter *filter)
6316 {
6317         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6318         struct ixgbe_filter_info *filter_info =
6319                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6320         uint32_t etqf, etqs;
6321         int ret;
6322
6323         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6324         if (ret < 0) {
6325                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6326                             filter->ether_type);
6327                 return -ENOENT;
6328         }
6329
6330         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6331         if (etqf & IXGBE_ETQF_FILTER_EN) {
6332                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6333                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6334                 filter->flags = 0;
6335                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6336                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6337                 return 0;
6338         }
6339         return -ENOENT;
6340 }
6341
6342 /*
6343  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6344  * @dev: pointer to rte_eth_dev structure
6345  * @filter_op:operation will be taken.
6346  * @arg: a pointer to specific structure corresponding to the filter_op
6347  */
6348 static int
6349 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6350                                 enum rte_filter_op filter_op,
6351                                 void *arg)
6352 {
6353         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6354         int ret;
6355
6356         MAC_TYPE_FILTER_SUP(hw->mac.type);
6357
6358         if (filter_op == RTE_ETH_FILTER_NOP)
6359                 return 0;
6360
6361         if (arg == NULL) {
6362                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6363                             filter_op);
6364                 return -EINVAL;
6365         }
6366
6367         switch (filter_op) {
6368         case RTE_ETH_FILTER_ADD:
6369                 ret = ixgbe_add_del_ethertype_filter(dev,
6370                         (struct rte_eth_ethertype_filter *)arg,
6371                         TRUE);
6372                 break;
6373         case RTE_ETH_FILTER_DELETE:
6374                 ret = ixgbe_add_del_ethertype_filter(dev,
6375                         (struct rte_eth_ethertype_filter *)arg,
6376                         FALSE);
6377                 break;
6378         case RTE_ETH_FILTER_GET:
6379                 ret = ixgbe_get_ethertype_filter(dev,
6380                         (struct rte_eth_ethertype_filter *)arg);
6381                 break;
6382         default:
6383                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6384                 ret = -EINVAL;
6385                 break;
6386         }
6387         return ret;
6388 }
6389
6390 static int
6391 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6392                      enum rte_filter_type filter_type,
6393                      enum rte_filter_op filter_op,
6394                      void *arg)
6395 {
6396         int ret = 0;
6397
6398         switch (filter_type) {
6399         case RTE_ETH_FILTER_NTUPLE:
6400                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6401                 break;
6402         case RTE_ETH_FILTER_ETHERTYPE:
6403                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6404                 break;
6405         case RTE_ETH_FILTER_SYN:
6406                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6407                 break;
6408         case RTE_ETH_FILTER_FDIR:
6409                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6410                 break;
6411         case RTE_ETH_FILTER_L2_TUNNEL:
6412                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6413                 break;
6414         case RTE_ETH_FILTER_GENERIC:
6415                 if (filter_op != RTE_ETH_FILTER_GET)
6416                         return -EINVAL;
6417                 *(const void **)arg = &ixgbe_flow_ops;
6418                 break;
6419         default:
6420                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6421                                                         filter_type);
6422                 ret = -EINVAL;
6423                 break;
6424         }
6425
6426         return ret;
6427 }
6428
6429 static u8 *
6430 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6431                         u8 **mc_addr_ptr, u32 *vmdq)
6432 {
6433         u8 *mc_addr;
6434
6435         *vmdq = 0;
6436         mc_addr = *mc_addr_ptr;
6437         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6438         return mc_addr;
6439 }
6440
6441 static int
6442 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6443                           struct ether_addr *mc_addr_set,
6444                           uint32_t nb_mc_addr)
6445 {
6446         struct ixgbe_hw *hw;
6447         u8 *mc_addr_list;
6448
6449         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6450         mc_addr_list = (u8 *)mc_addr_set;
6451         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6452                                          ixgbe_dev_addr_list_itr, TRUE);
6453 }
6454
6455 static uint64_t
6456 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6457 {
6458         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6459         uint64_t systime_cycles;
6460
6461         switch (hw->mac.type) {
6462         case ixgbe_mac_X550:
6463         case ixgbe_mac_X550EM_x:
6464         case ixgbe_mac_X550EM_a:
6465                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6466                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6467                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6468                                 * NSEC_PER_SEC;
6469                 break;
6470         default:
6471                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6472                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6473                                 << 32;
6474         }
6475
6476         return systime_cycles;
6477 }
6478
6479 static uint64_t
6480 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6481 {
6482         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6483         uint64_t rx_tstamp_cycles;
6484
6485         switch (hw->mac.type) {
6486         case ixgbe_mac_X550:
6487         case ixgbe_mac_X550EM_x:
6488         case ixgbe_mac_X550EM_a:
6489                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6490                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6491                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6492                                 * NSEC_PER_SEC;
6493                 break;
6494         default:
6495                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6496                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6497                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6498                                 << 32;
6499         }
6500
6501         return rx_tstamp_cycles;
6502 }
6503
6504 static uint64_t
6505 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6506 {
6507         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6508         uint64_t tx_tstamp_cycles;
6509
6510         switch (hw->mac.type) {
6511         case ixgbe_mac_X550:
6512         case ixgbe_mac_X550EM_x:
6513         case ixgbe_mac_X550EM_a:
6514                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6515                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6516                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6517                                 * NSEC_PER_SEC;
6518                 break;
6519         default:
6520                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6521                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6522                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6523                                 << 32;
6524         }
6525
6526         return tx_tstamp_cycles;
6527 }
6528
6529 static void
6530 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6531 {
6532         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6533         struct ixgbe_adapter *adapter =
6534                 (struct ixgbe_adapter *)dev->data->dev_private;
6535         struct rte_eth_link link;
6536         uint32_t incval = 0;
6537         uint32_t shift = 0;
6538
6539         /* Get current link speed. */
6540         memset(&link, 0, sizeof(link));
6541         ixgbe_dev_link_update(dev, 1);
6542         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6543
6544         switch (link.link_speed) {
6545         case ETH_SPEED_NUM_100M:
6546                 incval = IXGBE_INCVAL_100;
6547                 shift = IXGBE_INCVAL_SHIFT_100;
6548                 break;
6549         case ETH_SPEED_NUM_1G:
6550                 incval = IXGBE_INCVAL_1GB;
6551                 shift = IXGBE_INCVAL_SHIFT_1GB;
6552                 break;
6553         case ETH_SPEED_NUM_10G:
6554         default:
6555                 incval = IXGBE_INCVAL_10GB;
6556                 shift = IXGBE_INCVAL_SHIFT_10GB;
6557                 break;
6558         }
6559
6560         switch (hw->mac.type) {
6561         case ixgbe_mac_X550:
6562         case ixgbe_mac_X550EM_x:
6563         case ixgbe_mac_X550EM_a:
6564                 /* Independent of link speed. */
6565                 incval = 1;
6566                 /* Cycles read will be interpreted as ns. */
6567                 shift = 0;
6568                 /* Fall-through */
6569         case ixgbe_mac_X540:
6570                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6571                 break;
6572         case ixgbe_mac_82599EB:
6573                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6574                 shift -= IXGBE_INCVAL_SHIFT_82599;
6575                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6576                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6577                 break;
6578         default:
6579                 /* Not supported. */
6580                 return;
6581         }
6582
6583         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6584         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6585         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6586
6587         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6588         adapter->systime_tc.cc_shift = shift;
6589         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6590
6591         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6592         adapter->rx_tstamp_tc.cc_shift = shift;
6593         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6594
6595         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6596         adapter->tx_tstamp_tc.cc_shift = shift;
6597         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6598 }
6599
6600 static int
6601 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6602 {
6603         struct ixgbe_adapter *adapter =
6604                         (struct ixgbe_adapter *)dev->data->dev_private;
6605
6606         adapter->systime_tc.nsec += delta;
6607         adapter->rx_tstamp_tc.nsec += delta;
6608         adapter->tx_tstamp_tc.nsec += delta;
6609
6610         return 0;
6611 }
6612
6613 static int
6614 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6615 {
6616         uint64_t ns;
6617         struct ixgbe_adapter *adapter =
6618                         (struct ixgbe_adapter *)dev->data->dev_private;
6619
6620         ns = rte_timespec_to_ns(ts);
6621         /* Set the timecounters to a new value. */
6622         adapter->systime_tc.nsec = ns;
6623         adapter->rx_tstamp_tc.nsec = ns;
6624         adapter->tx_tstamp_tc.nsec = ns;
6625
6626         return 0;
6627 }
6628
6629 static int
6630 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6631 {
6632         uint64_t ns, systime_cycles;
6633         struct ixgbe_adapter *adapter =
6634                         (struct ixgbe_adapter *)dev->data->dev_private;
6635
6636         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6637         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6638         *ts = rte_ns_to_timespec(ns);
6639
6640         return 0;
6641 }
6642
6643 static int
6644 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6645 {
6646         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6647         uint32_t tsync_ctl;
6648         uint32_t tsauxc;
6649
6650         /* Stop the timesync system time. */
6651         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6652         /* Reset the timesync system time value. */
6653         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6654         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6655
6656         /* Enable system time for platforms where it isn't on by default. */
6657         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6658         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6659         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6660
6661         ixgbe_start_timecounters(dev);
6662
6663         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6664         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6665                         (ETHER_TYPE_1588 |
6666                          IXGBE_ETQF_FILTER_EN |
6667                          IXGBE_ETQF_1588));
6668
6669         /* Enable timestamping of received PTP packets. */
6670         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6671         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6672         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6673
6674         /* Enable timestamping of transmitted PTP packets. */
6675         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6676         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6677         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6678
6679         IXGBE_WRITE_FLUSH(hw);
6680
6681         return 0;
6682 }
6683
6684 static int
6685 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6686 {
6687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6688         uint32_t tsync_ctl;
6689
6690         /* Disable timestamping of transmitted PTP packets. */
6691         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6692         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6693         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6694
6695         /* Disable timestamping of received PTP packets. */
6696         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6697         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6698         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6699
6700         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6701         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6702
6703         /* Stop incrementating the System Time registers. */
6704         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6705
6706         return 0;
6707 }
6708
6709 static int
6710 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6711                                  struct timespec *timestamp,
6712                                  uint32_t flags __rte_unused)
6713 {
6714         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6715         struct ixgbe_adapter *adapter =
6716                 (struct ixgbe_adapter *)dev->data->dev_private;
6717         uint32_t tsync_rxctl;
6718         uint64_t rx_tstamp_cycles;
6719         uint64_t ns;
6720
6721         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6722         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6723                 return -EINVAL;
6724
6725         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6726         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6727         *timestamp = rte_ns_to_timespec(ns);
6728
6729         return  0;
6730 }
6731
6732 static int
6733 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6734                                  struct timespec *timestamp)
6735 {
6736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6737         struct ixgbe_adapter *adapter =
6738                 (struct ixgbe_adapter *)dev->data->dev_private;
6739         uint32_t tsync_txctl;
6740         uint64_t tx_tstamp_cycles;
6741         uint64_t ns;
6742
6743         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6744         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6745                 return -EINVAL;
6746
6747         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6748         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6749         *timestamp = rte_ns_to_timespec(ns);
6750
6751         return 0;
6752 }
6753
6754 static int
6755 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6756 {
6757         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6758         int count = 0;
6759         int g_ind = 0;
6760         const struct reg_info *reg_group;
6761         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6762                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6763
6764         while ((reg_group = reg_set[g_ind++]))
6765                 count += ixgbe_regs_group_count(reg_group);
6766
6767         return count;
6768 }
6769
6770 static int
6771 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6772 {
6773         int count = 0;
6774         int g_ind = 0;
6775         const struct reg_info *reg_group;
6776
6777         while ((reg_group = ixgbevf_regs[g_ind++]))
6778                 count += ixgbe_regs_group_count(reg_group);
6779
6780         return count;
6781 }
6782
6783 static int
6784 ixgbe_get_regs(struct rte_eth_dev *dev,
6785               struct rte_dev_reg_info *regs)
6786 {
6787         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6788         uint32_t *data = regs->data;
6789         int g_ind = 0;
6790         int count = 0;
6791         const struct reg_info *reg_group;
6792         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6793                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6794
6795         if (data == NULL) {
6796                 regs->length = ixgbe_get_reg_length(dev);
6797                 regs->width = sizeof(uint32_t);
6798                 return 0;
6799         }
6800
6801         /* Support only full register dump */
6802         if ((regs->length == 0) ||
6803             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6804                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6805                         hw->device_id;
6806                 while ((reg_group = reg_set[g_ind++]))
6807                         count += ixgbe_read_regs_group(dev, &data[count],
6808                                 reg_group);
6809                 return 0;
6810         }
6811
6812         return -ENOTSUP;
6813 }
6814
6815 static int
6816 ixgbevf_get_regs(struct rte_eth_dev *dev,
6817                 struct rte_dev_reg_info *regs)
6818 {
6819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6820         uint32_t *data = regs->data;
6821         int g_ind = 0;
6822         int count = 0;
6823         const struct reg_info *reg_group;
6824
6825         if (data == NULL) {
6826                 regs->length = ixgbevf_get_reg_length(dev);
6827                 regs->width = sizeof(uint32_t);
6828                 return 0;
6829         }
6830
6831         /* Support only full register dump */
6832         if ((regs->length == 0) ||
6833             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6834                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6835                         hw->device_id;
6836                 while ((reg_group = ixgbevf_regs[g_ind++]))
6837                         count += ixgbe_read_regs_group(dev, &data[count],
6838                                                       reg_group);
6839                 return 0;
6840         }
6841
6842         return -ENOTSUP;
6843 }
6844
6845 static int
6846 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6847 {
6848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6849
6850         /* Return unit is byte count */
6851         return hw->eeprom.word_size * 2;
6852 }
6853
6854 static int
6855 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6856                 struct rte_dev_eeprom_info *in_eeprom)
6857 {
6858         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6859         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6860         uint16_t *data = in_eeprom->data;
6861         int first, length;
6862
6863         first = in_eeprom->offset >> 1;
6864         length = in_eeprom->length >> 1;
6865         if ((first > hw->eeprom.word_size) ||
6866             ((first + length) > hw->eeprom.word_size))
6867                 return -EINVAL;
6868
6869         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6870
6871         return eeprom->ops.read_buffer(hw, first, length, data);
6872 }
6873
6874 static int
6875 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6876                 struct rte_dev_eeprom_info *in_eeprom)
6877 {
6878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6879         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6880         uint16_t *data = in_eeprom->data;
6881         int first, length;
6882
6883         first = in_eeprom->offset >> 1;
6884         length = in_eeprom->length >> 1;
6885         if ((first > hw->eeprom.word_size) ||
6886             ((first + length) > hw->eeprom.word_size))
6887                 return -EINVAL;
6888
6889         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6890
6891         return eeprom->ops.write_buffer(hw,  first, length, data);
6892 }
6893
6894 uint16_t
6895 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6896         switch (mac_type) {
6897         case ixgbe_mac_X550:
6898         case ixgbe_mac_X550EM_x:
6899         case ixgbe_mac_X550EM_a:
6900                 return ETH_RSS_RETA_SIZE_512;
6901         case ixgbe_mac_X550_vf:
6902         case ixgbe_mac_X550EM_x_vf:
6903         case ixgbe_mac_X550EM_a_vf:
6904                 return ETH_RSS_RETA_SIZE_64;
6905         default:
6906                 return ETH_RSS_RETA_SIZE_128;
6907         }
6908 }
6909
6910 uint32_t
6911 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6912         switch (mac_type) {
6913         case ixgbe_mac_X550:
6914         case ixgbe_mac_X550EM_x:
6915         case ixgbe_mac_X550EM_a:
6916                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6917                         return IXGBE_RETA(reta_idx >> 2);
6918                 else
6919                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6920         case ixgbe_mac_X550_vf:
6921         case ixgbe_mac_X550EM_x_vf:
6922         case ixgbe_mac_X550EM_a_vf:
6923                 return IXGBE_VFRETA(reta_idx >> 2);
6924         default:
6925                 return IXGBE_RETA(reta_idx >> 2);
6926         }
6927 }
6928
6929 uint32_t
6930 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6931         switch (mac_type) {
6932         case ixgbe_mac_X550_vf:
6933         case ixgbe_mac_X550EM_x_vf:
6934         case ixgbe_mac_X550EM_a_vf:
6935                 return IXGBE_VFMRQC;
6936         default:
6937                 return IXGBE_MRQC;
6938         }
6939 }
6940
6941 uint32_t
6942 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6943         switch (mac_type) {
6944         case ixgbe_mac_X550_vf:
6945         case ixgbe_mac_X550EM_x_vf:
6946         case ixgbe_mac_X550EM_a_vf:
6947                 return IXGBE_VFRSSRK(i);
6948         default:
6949                 return IXGBE_RSSRK(i);
6950         }
6951 }
6952
6953 bool
6954 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6955         switch (mac_type) {
6956         case ixgbe_mac_82599_vf:
6957         case ixgbe_mac_X540_vf:
6958                 return 0;
6959         default:
6960                 return 1;
6961         }
6962 }
6963
6964 static int
6965 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6966                         struct rte_eth_dcb_info *dcb_info)
6967 {
6968         struct ixgbe_dcb_config *dcb_config =
6969                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6970         struct ixgbe_dcb_tc_config *tc;
6971         uint8_t i, j;
6972
6973         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6974                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6975         else
6976                 dcb_info->nb_tcs = 1;
6977
6978         if (dcb_config->vt_mode) { /* vt is enabled*/
6979                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6980                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6981                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6982                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6983                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6984                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6985                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6986                                                 i * dcb_info->nb_tcs + j;
6987                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6988                                 dcb_info->tc_queue.tc_txq[i][j].base =
6989                                                 i * dcb_info->nb_tcs + j;
6990                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6991                         }
6992                 }
6993         } else { /* vt is disabled*/
6994                 struct rte_eth_dcb_rx_conf *rx_conf =
6995                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6996                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6997                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6998                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6999                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7000                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7001                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7002                         }
7003                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7004                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7005                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7006                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7007                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7008                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7009                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7010                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7011                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7012                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7013                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7014                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7015                         }
7016                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7017                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7018                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7019                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7020                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7021                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7022                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7023                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7024                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7025                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7026                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7027                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7028                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7029                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7030                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7031                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7032                 }
7033         }
7034         for (i = 0; i < dcb_info->nb_tcs; i++) {
7035                 tc = &dcb_config->tc_config[i];
7036                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7037         }
7038         return 0;
7039 }
7040
7041 /* Update e-tag ether type */
7042 static int
7043 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7044                             uint16_t ether_type)
7045 {
7046         uint32_t etag_etype;
7047
7048         if (hw->mac.type != ixgbe_mac_X550 &&
7049             hw->mac.type != ixgbe_mac_X550EM_x &&
7050             hw->mac.type != ixgbe_mac_X550EM_a) {
7051                 return -ENOTSUP;
7052         }
7053
7054         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7055         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7056         etag_etype |= ether_type;
7057         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7058         IXGBE_WRITE_FLUSH(hw);
7059
7060         return 0;
7061 }
7062
7063 /* Config l2 tunnel ether type */
7064 static int
7065 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7066                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7067 {
7068         int ret = 0;
7069         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7070         struct ixgbe_l2_tn_info *l2_tn_info =
7071                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7072
7073         if (l2_tunnel == NULL)
7074                 return -EINVAL;
7075
7076         switch (l2_tunnel->l2_tunnel_type) {
7077         case RTE_L2_TUNNEL_TYPE_E_TAG:
7078                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7079                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7080                 break;
7081         default:
7082                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7083                 ret = -EINVAL;
7084                 break;
7085         }
7086
7087         return ret;
7088 }
7089
7090 /* Enable e-tag tunnel */
7091 static int
7092 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7093 {
7094         uint32_t etag_etype;
7095
7096         if (hw->mac.type != ixgbe_mac_X550 &&
7097             hw->mac.type != ixgbe_mac_X550EM_x &&
7098             hw->mac.type != ixgbe_mac_X550EM_a) {
7099                 return -ENOTSUP;
7100         }
7101
7102         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7103         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7104         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7105         IXGBE_WRITE_FLUSH(hw);
7106
7107         return 0;
7108 }
7109
7110 /* Enable l2 tunnel */
7111 static int
7112 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7113                            enum rte_eth_tunnel_type l2_tunnel_type)
7114 {
7115         int ret = 0;
7116         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7117         struct ixgbe_l2_tn_info *l2_tn_info =
7118                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7119
7120         switch (l2_tunnel_type) {
7121         case RTE_L2_TUNNEL_TYPE_E_TAG:
7122                 l2_tn_info->e_tag_en = TRUE;
7123                 ret = ixgbe_e_tag_enable(hw);
7124                 break;
7125         default:
7126                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7127                 ret = -EINVAL;
7128                 break;
7129         }
7130
7131         return ret;
7132 }
7133
7134 /* Disable e-tag tunnel */
7135 static int
7136 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7137 {
7138         uint32_t etag_etype;
7139
7140         if (hw->mac.type != ixgbe_mac_X550 &&
7141             hw->mac.type != ixgbe_mac_X550EM_x &&
7142             hw->mac.type != ixgbe_mac_X550EM_a) {
7143                 return -ENOTSUP;
7144         }
7145
7146         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7147         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7148         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7149         IXGBE_WRITE_FLUSH(hw);
7150
7151         return 0;
7152 }
7153
7154 /* Disable l2 tunnel */
7155 static int
7156 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7157                             enum rte_eth_tunnel_type l2_tunnel_type)
7158 {
7159         int ret = 0;
7160         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7161         struct ixgbe_l2_tn_info *l2_tn_info =
7162                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7163
7164         switch (l2_tunnel_type) {
7165         case RTE_L2_TUNNEL_TYPE_E_TAG:
7166                 l2_tn_info->e_tag_en = FALSE;
7167                 ret = ixgbe_e_tag_disable(hw);
7168                 break;
7169         default:
7170                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7171                 ret = -EINVAL;
7172                 break;
7173         }
7174
7175         return ret;
7176 }
7177
7178 static int
7179 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7180                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7181 {
7182         int ret = 0;
7183         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7184         uint32_t i, rar_entries;
7185         uint32_t rar_low, rar_high;
7186
7187         if (hw->mac.type != ixgbe_mac_X550 &&
7188             hw->mac.type != ixgbe_mac_X550EM_x &&
7189             hw->mac.type != ixgbe_mac_X550EM_a) {
7190                 return -ENOTSUP;
7191         }
7192
7193         rar_entries = ixgbe_get_num_rx_addrs(hw);
7194
7195         for (i = 1; i < rar_entries; i++) {
7196                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7197                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7198                 if ((rar_high & IXGBE_RAH_AV) &&
7199                     (rar_high & IXGBE_RAH_ADTYPE) &&
7200                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7201                      l2_tunnel->tunnel_id)) {
7202                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7203                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7204
7205                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7206
7207                         return ret;
7208                 }
7209         }
7210
7211         return ret;
7212 }
7213
7214 static int
7215 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7216                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7217 {
7218         int ret = 0;
7219         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7220         uint32_t i, rar_entries;
7221         uint32_t rar_low, rar_high;
7222
7223         if (hw->mac.type != ixgbe_mac_X550 &&
7224             hw->mac.type != ixgbe_mac_X550EM_x &&
7225             hw->mac.type != ixgbe_mac_X550EM_a) {
7226                 return -ENOTSUP;
7227         }
7228
7229         /* One entry for one tunnel. Try to remove potential existing entry. */
7230         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7231
7232         rar_entries = ixgbe_get_num_rx_addrs(hw);
7233
7234         for (i = 1; i < rar_entries; i++) {
7235                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7236                 if (rar_high & IXGBE_RAH_AV) {
7237                         continue;
7238                 } else {
7239                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7240                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7241                         rar_low = l2_tunnel->tunnel_id;
7242
7243                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7244                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7245
7246                         return ret;
7247                 }
7248         }
7249
7250         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7251                      " Please remove a rule before adding a new one.");
7252         return -EINVAL;
7253 }
7254
7255 static inline struct ixgbe_l2_tn_filter *
7256 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7257                           struct ixgbe_l2_tn_key *key)
7258 {
7259         int ret;
7260
7261         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7262         if (ret < 0)
7263                 return NULL;
7264
7265         return l2_tn_info->hash_map[ret];
7266 }
7267
7268 static inline int
7269 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7270                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7271 {
7272         int ret;
7273
7274         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7275                                &l2_tn_filter->key);
7276
7277         if (ret < 0) {
7278                 PMD_DRV_LOG(ERR,
7279                             "Failed to insert L2 tunnel filter"
7280                             " to hash table %d!",
7281                             ret);
7282                 return ret;
7283         }
7284
7285         l2_tn_info->hash_map[ret] = l2_tn_filter;
7286
7287         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7288
7289         return 0;
7290 }
7291
7292 static inline int
7293 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7294                           struct ixgbe_l2_tn_key *key)
7295 {
7296         int ret;
7297         struct ixgbe_l2_tn_filter *l2_tn_filter;
7298
7299         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7300
7301         if (ret < 0) {
7302                 PMD_DRV_LOG(ERR,
7303                             "No such L2 tunnel filter to delete %d!",
7304                             ret);
7305                 return ret;
7306         }
7307
7308         l2_tn_filter = l2_tn_info->hash_map[ret];
7309         l2_tn_info->hash_map[ret] = NULL;
7310
7311         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7312         rte_free(l2_tn_filter);
7313
7314         return 0;
7315 }
7316
7317 /* Add l2 tunnel filter */
7318 int
7319 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7320                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7321                                bool restore)
7322 {
7323         int ret;
7324         struct ixgbe_l2_tn_info *l2_tn_info =
7325                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7326         struct ixgbe_l2_tn_key key;
7327         struct ixgbe_l2_tn_filter *node;
7328
7329         if (!restore) {
7330                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7331                 key.tn_id = l2_tunnel->tunnel_id;
7332
7333                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7334
7335                 if (node) {
7336                         PMD_DRV_LOG(ERR,
7337                                     "The L2 tunnel filter already exists!");
7338                         return -EINVAL;
7339                 }
7340
7341                 node = rte_zmalloc("ixgbe_l2_tn",
7342                                    sizeof(struct ixgbe_l2_tn_filter),
7343                                    0);
7344                 if (!node)
7345                         return -ENOMEM;
7346
7347                 (void)rte_memcpy(&node->key,
7348                                  &key,
7349                                  sizeof(struct ixgbe_l2_tn_key));
7350                 node->pool = l2_tunnel->pool;
7351                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7352                 if (ret < 0) {
7353                         rte_free(node);
7354                         return ret;
7355                 }
7356         }
7357
7358         switch (l2_tunnel->l2_tunnel_type) {
7359         case RTE_L2_TUNNEL_TYPE_E_TAG:
7360                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7361                 break;
7362         default:
7363                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7364                 ret = -EINVAL;
7365                 break;
7366         }
7367
7368         if ((!restore) && (ret < 0))
7369                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7370
7371         return ret;
7372 }
7373
7374 /* Delete l2 tunnel filter */
7375 int
7376 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7377                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7378 {
7379         int ret;
7380         struct ixgbe_l2_tn_info *l2_tn_info =
7381                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7382         struct ixgbe_l2_tn_key key;
7383
7384         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7385         key.tn_id = l2_tunnel->tunnel_id;
7386         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7387         if (ret < 0)
7388                 return ret;
7389
7390         switch (l2_tunnel->l2_tunnel_type) {
7391         case RTE_L2_TUNNEL_TYPE_E_TAG:
7392                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7393                 break;
7394         default:
7395                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7396                 ret = -EINVAL;
7397                 break;
7398         }
7399
7400         return ret;
7401 }
7402
7403 /**
7404  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7405  * @dev: pointer to rte_eth_dev structure
7406  * @filter_op:operation will be taken.
7407  * @arg: a pointer to specific structure corresponding to the filter_op
7408  */
7409 static int
7410 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7411                                   enum rte_filter_op filter_op,
7412                                   void *arg)
7413 {
7414         int ret;
7415
7416         if (filter_op == RTE_ETH_FILTER_NOP)
7417                 return 0;
7418
7419         if (arg == NULL) {
7420                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7421                             filter_op);
7422                 return -EINVAL;
7423         }
7424
7425         switch (filter_op) {
7426         case RTE_ETH_FILTER_ADD:
7427                 ret = ixgbe_dev_l2_tunnel_filter_add
7428                         (dev,
7429                          (struct rte_eth_l2_tunnel_conf *)arg,
7430                          FALSE);
7431                 break;
7432         case RTE_ETH_FILTER_DELETE:
7433                 ret = ixgbe_dev_l2_tunnel_filter_del
7434                         (dev,
7435                          (struct rte_eth_l2_tunnel_conf *)arg);
7436                 break;
7437         default:
7438                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7439                 ret = -EINVAL;
7440                 break;
7441         }
7442         return ret;
7443 }
7444
7445 static int
7446 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7447 {
7448         int ret = 0;
7449         uint32_t ctrl;
7450         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7451
7452         if (hw->mac.type != ixgbe_mac_X550 &&
7453             hw->mac.type != ixgbe_mac_X550EM_x &&
7454             hw->mac.type != ixgbe_mac_X550EM_a) {
7455                 return -ENOTSUP;
7456         }
7457
7458         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7459         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7460         if (en)
7461                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7462         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7463
7464         return ret;
7465 }
7466
7467 /* Enable l2 tunnel forwarding */
7468 static int
7469 ixgbe_dev_l2_tunnel_forwarding_enable
7470         (struct rte_eth_dev *dev,
7471          enum rte_eth_tunnel_type l2_tunnel_type)
7472 {
7473         struct ixgbe_l2_tn_info *l2_tn_info =
7474                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7475         int ret = 0;
7476
7477         switch (l2_tunnel_type) {
7478         case RTE_L2_TUNNEL_TYPE_E_TAG:
7479                 l2_tn_info->e_tag_fwd_en = TRUE;
7480                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7481                 break;
7482         default:
7483                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7484                 ret = -EINVAL;
7485                 break;
7486         }
7487
7488         return ret;
7489 }
7490
7491 /* Disable l2 tunnel forwarding */
7492 static int
7493 ixgbe_dev_l2_tunnel_forwarding_disable
7494         (struct rte_eth_dev *dev,
7495          enum rte_eth_tunnel_type l2_tunnel_type)
7496 {
7497         struct ixgbe_l2_tn_info *l2_tn_info =
7498                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7499         int ret = 0;
7500
7501         switch (l2_tunnel_type) {
7502         case RTE_L2_TUNNEL_TYPE_E_TAG:
7503                 l2_tn_info->e_tag_fwd_en = FALSE;
7504                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7505                 break;
7506         default:
7507                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7508                 ret = -EINVAL;
7509                 break;
7510         }
7511
7512         return ret;
7513 }
7514
7515 static int
7516 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7517                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7518                              bool en)
7519 {
7520         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7521         int ret = 0;
7522         uint32_t vmtir, vmvir;
7523         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7524
7525         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7526                 PMD_DRV_LOG(ERR,
7527                             "VF id %u should be less than %u",
7528                             l2_tunnel->vf_id,
7529                             pci_dev->max_vfs);
7530                 return -EINVAL;
7531         }
7532
7533         if (hw->mac.type != ixgbe_mac_X550 &&
7534             hw->mac.type != ixgbe_mac_X550EM_x &&
7535             hw->mac.type != ixgbe_mac_X550EM_a) {
7536                 return -ENOTSUP;
7537         }
7538
7539         if (en)
7540                 vmtir = l2_tunnel->tunnel_id;
7541         else
7542                 vmtir = 0;
7543
7544         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7545
7546         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7547         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7548         if (en)
7549                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7550         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7551
7552         return ret;
7553 }
7554
7555 /* Enable l2 tunnel tag insertion */
7556 static int
7557 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7558                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7559 {
7560         int ret = 0;
7561
7562         switch (l2_tunnel->l2_tunnel_type) {
7563         case RTE_L2_TUNNEL_TYPE_E_TAG:
7564                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7565                 break;
7566         default:
7567                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7568                 ret = -EINVAL;
7569                 break;
7570         }
7571
7572         return ret;
7573 }
7574
7575 /* Disable l2 tunnel tag insertion */
7576 static int
7577 ixgbe_dev_l2_tunnel_insertion_disable
7578         (struct rte_eth_dev *dev,
7579          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7580 {
7581         int ret = 0;
7582
7583         switch (l2_tunnel->l2_tunnel_type) {
7584         case RTE_L2_TUNNEL_TYPE_E_TAG:
7585                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7586                 break;
7587         default:
7588                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7589                 ret = -EINVAL;
7590                 break;
7591         }
7592
7593         return ret;
7594 }
7595
7596 static int
7597 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7598                              bool en)
7599 {
7600         int ret = 0;
7601         uint32_t qde;
7602         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7603
7604         if (hw->mac.type != ixgbe_mac_X550 &&
7605             hw->mac.type != ixgbe_mac_X550EM_x &&
7606             hw->mac.type != ixgbe_mac_X550EM_a) {
7607                 return -ENOTSUP;
7608         }
7609
7610         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7611         if (en)
7612                 qde |= IXGBE_QDE_STRIP_TAG;
7613         else
7614                 qde &= ~IXGBE_QDE_STRIP_TAG;
7615         qde &= ~IXGBE_QDE_READ;
7616         qde |= IXGBE_QDE_WRITE;
7617         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7618
7619         return ret;
7620 }
7621
7622 /* Enable l2 tunnel tag stripping */
7623 static int
7624 ixgbe_dev_l2_tunnel_stripping_enable
7625         (struct rte_eth_dev *dev,
7626          enum rte_eth_tunnel_type l2_tunnel_type)
7627 {
7628         int ret = 0;
7629
7630         switch (l2_tunnel_type) {
7631         case RTE_L2_TUNNEL_TYPE_E_TAG:
7632                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7633                 break;
7634         default:
7635                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7636                 ret = -EINVAL;
7637                 break;
7638         }
7639
7640         return ret;
7641 }
7642
7643 /* Disable l2 tunnel tag stripping */
7644 static int
7645 ixgbe_dev_l2_tunnel_stripping_disable
7646         (struct rte_eth_dev *dev,
7647          enum rte_eth_tunnel_type l2_tunnel_type)
7648 {
7649         int ret = 0;
7650
7651         switch (l2_tunnel_type) {
7652         case RTE_L2_TUNNEL_TYPE_E_TAG:
7653                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7654                 break;
7655         default:
7656                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7657                 ret = -EINVAL;
7658                 break;
7659         }
7660
7661         return ret;
7662 }
7663
7664 /* Enable/disable l2 tunnel offload functions */
7665 static int
7666 ixgbe_dev_l2_tunnel_offload_set
7667         (struct rte_eth_dev *dev,
7668          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7669          uint32_t mask,
7670          uint8_t en)
7671 {
7672         int ret = 0;
7673
7674         if (l2_tunnel == NULL)
7675                 return -EINVAL;
7676
7677         ret = -EINVAL;
7678         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7679                 if (en)
7680                         ret = ixgbe_dev_l2_tunnel_enable(
7681                                 dev,
7682                                 l2_tunnel->l2_tunnel_type);
7683                 else
7684                         ret = ixgbe_dev_l2_tunnel_disable(
7685                                 dev,
7686                                 l2_tunnel->l2_tunnel_type);
7687         }
7688
7689         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7690                 if (en)
7691                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7692                                 dev,
7693                                 l2_tunnel);
7694                 else
7695                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7696                                 dev,
7697                                 l2_tunnel);
7698         }
7699
7700         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7701                 if (en)
7702                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7703                                 dev,
7704                                 l2_tunnel->l2_tunnel_type);
7705                 else
7706                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7707                                 dev,
7708                                 l2_tunnel->l2_tunnel_type);
7709         }
7710
7711         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7712                 if (en)
7713                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7714                                 dev,
7715                                 l2_tunnel->l2_tunnel_type);
7716                 else
7717                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7718                                 dev,
7719                                 l2_tunnel->l2_tunnel_type);
7720         }
7721
7722         return ret;
7723 }
7724
7725 static int
7726 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7727                         uint16_t port)
7728 {
7729         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7730         IXGBE_WRITE_FLUSH(hw);
7731
7732         return 0;
7733 }
7734
7735 /* There's only one register for VxLAN UDP port.
7736  * So, we cannot add several ports. Will update it.
7737  */
7738 static int
7739 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7740                      uint16_t port)
7741 {
7742         if (port == 0) {
7743                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7744                 return -EINVAL;
7745         }
7746
7747         return ixgbe_update_vxlan_port(hw, port);
7748 }
7749
7750 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7751  * UDP port, it must have a value.
7752  * So, will reset it to the original value 0.
7753  */
7754 static int
7755 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7756                      uint16_t port)
7757 {
7758         uint16_t cur_port;
7759
7760         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7761
7762         if (cur_port != port) {
7763                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7764                 return -EINVAL;
7765         }
7766
7767         return ixgbe_update_vxlan_port(hw, 0);
7768 }
7769
7770 /* Add UDP tunneling port */
7771 static int
7772 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7773                               struct rte_eth_udp_tunnel *udp_tunnel)
7774 {
7775         int ret = 0;
7776         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7777
7778         if (hw->mac.type != ixgbe_mac_X550 &&
7779             hw->mac.type != ixgbe_mac_X550EM_x &&
7780             hw->mac.type != ixgbe_mac_X550EM_a) {
7781                 return -ENOTSUP;
7782         }
7783
7784         if (udp_tunnel == NULL)
7785                 return -EINVAL;
7786
7787         switch (udp_tunnel->prot_type) {
7788         case RTE_TUNNEL_TYPE_VXLAN:
7789                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7790                 break;
7791
7792         case RTE_TUNNEL_TYPE_GENEVE:
7793         case RTE_TUNNEL_TYPE_TEREDO:
7794                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7795                 ret = -EINVAL;
7796                 break;
7797
7798         default:
7799                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7800                 ret = -EINVAL;
7801                 break;
7802         }
7803
7804         return ret;
7805 }
7806
7807 /* Remove UDP tunneling port */
7808 static int
7809 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7810                               struct rte_eth_udp_tunnel *udp_tunnel)
7811 {
7812         int ret = 0;
7813         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7814
7815         if (hw->mac.type != ixgbe_mac_X550 &&
7816             hw->mac.type != ixgbe_mac_X550EM_x &&
7817             hw->mac.type != ixgbe_mac_X550EM_a) {
7818                 return -ENOTSUP;
7819         }
7820
7821         if (udp_tunnel == NULL)
7822                 return -EINVAL;
7823
7824         switch (udp_tunnel->prot_type) {
7825         case RTE_TUNNEL_TYPE_VXLAN:
7826                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7827                 break;
7828         case RTE_TUNNEL_TYPE_GENEVE:
7829         case RTE_TUNNEL_TYPE_TEREDO:
7830                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7831                 ret = -EINVAL;
7832                 break;
7833         default:
7834                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7835                 ret = -EINVAL;
7836                 break;
7837         }
7838
7839         return ret;
7840 }
7841
7842 static void
7843 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7844 {
7845         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7846
7847         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7848 }
7849
7850 static void
7851 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7852 {
7853         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7854
7855         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7856 }
7857
7858 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7859 {
7860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7861         u32 in_msg = 0;
7862
7863         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7864                 return;
7865
7866         /* PF reset VF event */
7867         if (in_msg == IXGBE_PF_CONTROL_MSG)
7868                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7869 }
7870
7871 static int
7872 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7873 {
7874         uint32_t eicr;
7875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7876         struct ixgbe_interrupt *intr =
7877                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7878         ixgbevf_intr_disable(hw);
7879
7880         /* read-on-clear nic registers here */
7881         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7882         intr->flags = 0;
7883
7884         /* only one misc vector supported - mailbox */
7885         eicr &= IXGBE_VTEICR_MASK;
7886         if (eicr == IXGBE_MISC_VEC_ID)
7887                 intr->flags |= IXGBE_FLAG_MAILBOX;
7888
7889         return 0;
7890 }
7891
7892 static int
7893 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7894 {
7895         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7896         struct ixgbe_interrupt *intr =
7897                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7898
7899         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7900                 ixgbevf_mbx_process(dev);
7901                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7902         }
7903
7904         ixgbevf_intr_enable(hw);
7905
7906         return 0;
7907 }
7908
7909 static void
7910 ixgbevf_dev_interrupt_handler(void *param)
7911 {
7912         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7913
7914         ixgbevf_dev_interrupt_get_status(dev);
7915         ixgbevf_dev_interrupt_action(dev);
7916 }
7917
7918 /**
7919  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7920  *  @hw: pointer to hardware structure
7921  *
7922  *  Stops the transmit data path and waits for the HW to internally empty
7923  *  the Tx security block
7924  **/
7925 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7926 {
7927 #define IXGBE_MAX_SECTX_POLL 40
7928
7929         int i;
7930         int sectxreg;
7931
7932         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7933         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7934         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7935         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7936                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7937                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7938                         break;
7939                 /* Use interrupt-safe sleep just in case */
7940                 usec_delay(1000);
7941         }
7942
7943         /* For informational purposes only */
7944         if (i >= IXGBE_MAX_SECTX_POLL)
7945                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7946                          "path fully disabled.  Continuing with init.");
7947
7948         return IXGBE_SUCCESS;
7949 }
7950
7951 /**
7952  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7953  *  @hw: pointer to hardware structure
7954  *
7955  *  Enables the transmit data path.
7956  **/
7957 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7958 {
7959         uint32_t sectxreg;
7960
7961         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7962         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7963         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7964         IXGBE_WRITE_FLUSH(hw);
7965
7966         return IXGBE_SUCCESS;
7967 }
7968
7969 /* restore n-tuple filter */
7970 static inline void
7971 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
7972 {
7973         struct ixgbe_filter_info *filter_info =
7974                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7975         struct ixgbe_5tuple_filter *node;
7976
7977         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
7978                 ixgbe_inject_5tuple_filter(dev, node);
7979         }
7980 }
7981
7982 /* restore ethernet type filter */
7983 static inline void
7984 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
7985 {
7986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7987         struct ixgbe_filter_info *filter_info =
7988                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7989         int i;
7990
7991         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
7992                 if (filter_info->ethertype_mask & (1 << i)) {
7993                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
7994                                         filter_info->ethertype_filters[i].etqf);
7995                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
7996                                         filter_info->ethertype_filters[i].etqs);
7997                         IXGBE_WRITE_FLUSH(hw);
7998                 }
7999         }
8000 }
8001
8002 /* restore SYN filter */
8003 static inline void
8004 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8005 {
8006         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8007         struct ixgbe_filter_info *filter_info =
8008                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8009         uint32_t synqf;
8010
8011         synqf = filter_info->syn_info;
8012
8013         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8014                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8015                 IXGBE_WRITE_FLUSH(hw);
8016         }
8017 }
8018
8019 /* restore L2 tunnel filter */
8020 static inline void
8021 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8022 {
8023         struct ixgbe_l2_tn_info *l2_tn_info =
8024                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8025         struct ixgbe_l2_tn_filter *node;
8026         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8027
8028         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8029                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8030                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8031                 l2_tn_conf.pool           = node->pool;
8032                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8033         }
8034 }
8035
8036 static int
8037 ixgbe_filter_restore(struct rte_eth_dev *dev)
8038 {
8039         ixgbe_ntuple_filter_restore(dev);
8040         ixgbe_ethertype_filter_restore(dev);
8041         ixgbe_syn_filter_restore(dev);
8042         ixgbe_fdir_filter_restore(dev);
8043         ixgbe_l2_tn_filter_restore(dev);
8044
8045         return 0;
8046 }
8047
8048 static void
8049 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8050 {
8051         struct ixgbe_l2_tn_info *l2_tn_info =
8052                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8054
8055         if (l2_tn_info->e_tag_en)
8056                 (void)ixgbe_e_tag_enable(hw);
8057
8058         if (l2_tn_info->e_tag_fwd_en)
8059                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8060
8061         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8062 }
8063
8064 /* remove all the n-tuple filters */
8065 void
8066 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8067 {
8068         struct ixgbe_filter_info *filter_info =
8069                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8070         struct ixgbe_5tuple_filter *p_5tuple;
8071
8072         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8073                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8074 }
8075
8076 /* remove all the ether type filters */
8077 void
8078 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8079 {
8080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8081         struct ixgbe_filter_info *filter_info =
8082                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8083         int i;
8084
8085         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8086                 if (filter_info->ethertype_mask & (1 << i) &&
8087                     !filter_info->ethertype_filters[i].conf) {
8088                         (void)ixgbe_ethertype_filter_remove(filter_info,
8089                                                             (uint8_t)i);
8090                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8091                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8092                         IXGBE_WRITE_FLUSH(hw);
8093                 }
8094         }
8095 }
8096
8097 /* remove the SYN filter */
8098 void
8099 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8100 {
8101         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8102         struct ixgbe_filter_info *filter_info =
8103                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8104
8105         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8106                 filter_info->syn_info = 0;
8107
8108                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8109                 IXGBE_WRITE_FLUSH(hw);
8110         }
8111 }
8112
8113 /* remove all the L2 tunnel filters */
8114 int
8115 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8116 {
8117         struct ixgbe_l2_tn_info *l2_tn_info =
8118                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8119         struct ixgbe_l2_tn_filter *l2_tn_filter;
8120         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8121         int ret = 0;
8122
8123         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8124                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8125                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8126                 l2_tn_conf.pool           = l2_tn_filter->pool;
8127                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8128                 if (ret < 0)
8129                         return ret;
8130         }
8131
8132         return 0;
8133 }
8134
8135 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8136 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8137 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8138 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8139 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8140 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");