drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64 #include <rte_hash_crc.h>
  65
  66 #include "ixgbe_logs.h"
  67 #include "base/ixgbe_api.h"
  68 #include "base/ixgbe_vf.h"
  69 #include "base/ixgbe_common.h"
  70 #include "ixgbe_ethdev.h"
  71 #include "ixgbe_bypass.h"
  72 #include "ixgbe_rxtx.h"
  73 #include "base/ixgbe_type.h"
  74 #include "base/ixgbe_phy.h"
  75 #include "ixgbe_regs.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 158 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 168 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 178                                 int wait_to_complete);
 179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 180                                 struct rte_eth_stats *stats);
 181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 182                                 struct rte_eth_xstat *xstats, unsigned n);
 183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 184                                   struct rte_eth_xstat *xstats, unsigned n);
 185 static int
 186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 187                 uint64_t *values, unsigned int n);
 188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 190 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names,
 192         unsigned int size);
 193 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 194         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 195 static int ixgbe_dev_xstats_get_names_by_id(
 196         struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names,
 198         const uint64_t *ids,
 199         unsigned int limit);
 200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 201                                              uint16_t queue_id,
 202                                              uint8_t stat_idx,
 203                                              uint8_t is_rx);
 204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 205                                  size_t fw_size);
 206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_dev_info *dev_info);
 208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 210                                  struct rte_eth_dev_info *dev_info);
 211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 212
 213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 214                 uint16_t vlan_id, int on);
 215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 216                                enum rte_vlan_type vlan_type,
 217                                uint16_t tpid_id);
 218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 219                 uint16_t queue, bool on);
 220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 221                 int on);
 222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 227
 228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 233                                struct rte_eth_fc_conf *fc_conf);
 234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 235                 struct rte_eth_pfc_conf *pfc_conf);
 236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 237                         struct rte_eth_rss_reta_entry64 *reta_conf,
 238                         uint16_t reta_size);
 239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 240                         struct rte_eth_rss_reta_entry64 *reta_conf,
 241                         uint16_t reta_size);
 242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 248                                       struct rte_intr_handle *handle);
 249 static void ixgbe_dev_interrupt_handler(void *param);
 250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 252                          uint32_t index, uint32_t pool);
 253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 255                                            struct ether_addr *mac_addr);
 256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 257 static bool is_device_supported(struct rte_eth_dev *dev,
 258                                 struct rte_pci_driver *drv);
 259
 260 /* For Virtual Function support */
 261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 263 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 264 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 267 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 268 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 269 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 270                 struct rte_eth_stats *stats);
 271 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 272 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 273                 uint16_t vlan_id, int on);
 274 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 275                 uint16_t queue, int on);
 276 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 277 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 278 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 279                                             uint16_t queue_id);
 280 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 281                                              uint16_t queue_id);
 282 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 283                                  uint8_t queue, uint8_t msix_vector);
 284 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 285 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 286 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 287
 288 /* For Eth VMDQ APIs support */
 289 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 290                 ether_addr * mac_addr, uint8_t on);
 291 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 292 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 293                 struct rte_eth_mirror_conf *mirror_conf,
 294                 uint8_t rule_id, uint8_t on);
 295 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 296                 uint8_t rule_id);
 297 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 298                                           uint16_t queue_id);
 299 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 300                                            uint16_t queue_id);
 301 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 302                                uint8_t queue, uint8_t msix_vector);
 303 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 304
 305 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 306                 uint16_t queue_idx, uint16_t tx_rate);
 307
 308 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 309                                 struct ether_addr *mac_addr,
 310                                 uint32_t index, uint32_t pool);
 311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 313                                              struct ether_addr *mac_addr);
 314 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 315                         struct rte_eth_syn_filter *filter);
 316 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 317                         enum rte_filter_op filter_op,
 318                         void *arg);
 319 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 322                         struct ixgbe_5tuple_filter *filter);
 323 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 327                         struct rte_eth_ntuple_filter *filter);
 328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 332                         struct rte_eth_ethertype_filter *filter);
 333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 334                      enum rte_filter_type filter_type,
 335                      enum rte_filter_op filter_op,
 336                      void *arg);
 337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 338
 339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 340                                       struct ether_addr *mc_addr_set,
 341                                       uint32_t nb_mc_addr);
 342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 343                                    struct rte_eth_dcb_info *dcb_info);
 344
 345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 347                             struct rte_dev_reg_info *regs);
 348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353
 354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 356                                 struct rte_dev_reg_info *regs);
 357
 358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 361                                             struct timespec *timestamp,
 362                                             uint32_t flags);
 363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 364                                             struct timespec *timestamp);
 365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 367                                    struct timespec *timestamp);
 368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 369                                    const struct timespec *timestamp);
 370 static void ixgbevf_dev_interrupt_handler(void *param);
 371
 372 static int ixgbe_dev_l2_tunnel_eth_type_conf
 373         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 374 static int ixgbe_dev_l2_tunnel_offload_set
 375         (struct rte_eth_dev *dev,
 376          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 377          uint32_t mask,
 378          uint8_t en);
 379 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 380                                              enum rte_filter_op filter_op,
 381                                              void *arg);
 382
 383 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 384                                          struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 386                                          struct rte_eth_udp_tunnel *udp_tunnel);
 387 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 388 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 389
 390 /*
 391  * Define VF Stats MACRO for Non "cleared on read" register
 392  */
 393 #define UPDATE_VF_STAT(reg, last, cur)                          \
 394 {                                                               \
 395         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 396         cur += (latest - last) & UINT_MAX;                      \
 397         last = latest;                                          \
 398 }
 399
 400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 401 {                                                                \
 402         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 403         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 404         u64 latest = ((new_msb << 32) | new_lsb);                \
 405         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 406         last = latest;                                           \
 407 }
 408
 409 #define IXGBE_SET_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] |= 1 << bit;\
 413         } while (0)
 414
 415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (h)->bitmap[idx] &= ~(1 << bit);\
 419         } while (0)
 420
 421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 422                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 423                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 424                 (r) = (h)->bitmap[idx] >> bit & 1;\
 425         } while (0)
 426
 427 /*
 428  * The set of PCI devices this driver supports
 429  */
 430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 484 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 486 #endif
 487         { .vendor_id = 0, /* sentinel */ },
 488 };
 489
 490 /*
 491  * The set of PCI devices this driver supports (for 82599 VF)
 492  */
 493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 504         { .vendor_id = 0, /* sentinel */ },
 505 };
 506
 507 static const struct rte_eth_desc_lim rx_desc_lim = {
 508         .nb_max = IXGBE_MAX_RING_DESC,
 509         .nb_min = IXGBE_MIN_RING_DESC,
 510         .nb_align = IXGBE_RXD_ALIGN,
 511 };
 512
 513 static const struct rte_eth_desc_lim tx_desc_lim = {
 514         .nb_max = IXGBE_MAX_RING_DESC,
 515         .nb_min = IXGBE_MIN_RING_DESC,
 516         .nb_align = IXGBE_TXD_ALIGN,
 517         .nb_seg_max = IXGBE_TX_MAX_SEG,
 518         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 519 };
 520
 521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 522         .dev_configure        = ixgbe_dev_configure,
 523         .dev_start            = ixgbe_dev_start,
 524         .dev_stop             = ixgbe_dev_stop,
 525         .dev_set_link_up    = ixgbe_dev_set_link_up,
 526         .dev_set_link_down  = ixgbe_dev_set_link_down,
 527         .dev_close            = ixgbe_dev_close,
 528         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 529         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 530         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 531         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 532         .link_update          = ixgbe_dev_link_update,
 533         .stats_get            = ixgbe_dev_stats_get,
 534         .xstats_get           = ixgbe_dev_xstats_get,
 535         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 536         .stats_reset          = ixgbe_dev_stats_reset,
 537         .xstats_reset         = ixgbe_dev_xstats_reset,
 538         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 539         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 540         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 541         .fw_version_get       = ixgbe_fw_version_get,
 542         .dev_infos_get        = ixgbe_dev_info_get,
 543         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 544         .mtu_set              = ixgbe_dev_mtu_set,
 545         .vlan_filter_set      = ixgbe_vlan_filter_set,
 546         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 547         .vlan_offload_set     = ixgbe_vlan_offload_set,
 548         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 549         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 550         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 551         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 552         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 553         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 554         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 555         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 556         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 557         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 558         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 559         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 560         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 561         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 562         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 563         .dev_led_on           = ixgbe_dev_led_on,
 564         .dev_led_off          = ixgbe_dev_led_off,
 565         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 566         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 567         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 568         .mac_addr_add         = ixgbe_add_rar,
 569         .mac_addr_remove      = ixgbe_remove_rar,
 570         .mac_addr_set         = ixgbe_set_default_mac_addr,
 571         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 572         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 573         .mirror_rule_set      = ixgbe_mirror_rule_set,
 574         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 575         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 576         .reta_update          = ixgbe_dev_rss_reta_update,
 577         .reta_query           = ixgbe_dev_rss_reta_query,
 578         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 579         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 580         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 581         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 582         .rxq_info_get         = ixgbe_rxq_info_get,
 583         .txq_info_get         = ixgbe_txq_info_get,
 584         .timesync_enable      = ixgbe_timesync_enable,
 585         .timesync_disable     = ixgbe_timesync_disable,
 586         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 587         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 588         .get_reg              = ixgbe_get_regs,
 589         .get_eeprom_length    = ixgbe_get_eeprom_length,
 590         .get_eeprom           = ixgbe_get_eeprom,
 591         .set_eeprom           = ixgbe_set_eeprom,
 592         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 593         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 594         .timesync_read_time   = ixgbe_timesync_read_time,
 595         .timesync_write_time  = ixgbe_timesync_write_time,
 596         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 597         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 598         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 599         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 600 };
 601
 602 /*
 603  * dev_ops for virtual function, bare necessities for basic vf
 604  * operation have been implemented
 605  */
 606 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 607         .dev_configure        = ixgbevf_dev_configure,
 608         .dev_start            = ixgbevf_dev_start,
 609         .dev_stop             = ixgbevf_dev_stop,
 610         .link_update          = ixgbe_dev_link_update,
 611         .stats_get            = ixgbevf_dev_stats_get,
 612         .xstats_get           = ixgbevf_dev_xstats_get,
 613         .stats_reset          = ixgbevf_dev_stats_reset,
 614         .xstats_reset         = ixgbevf_dev_stats_reset,
 615         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 616         .dev_close            = ixgbevf_dev_close,
 617         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 618         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 619         .dev_infos_get        = ixgbevf_dev_info_get,
 620         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 621         .mtu_set              = ixgbevf_dev_set_mtu,
 622         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 623         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 624         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 625         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 626         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 627         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 628         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 629         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 630         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 631         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 632         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 633         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 634         .mac_addr_add         = ixgbevf_add_mac_addr,
 635         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 636         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 637         .rxq_info_get         = ixgbe_rxq_info_get,
 638         .txq_info_get         = ixgbe_txq_info_get,
 639         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 640         .get_reg              = ixgbevf_get_regs,
 641         .reta_update          = ixgbe_dev_rss_reta_update,
 642         .reta_query           = ixgbe_dev_rss_reta_query,
 643         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 644         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 645 };
 646
 647 /* store statistics names and its offset in stats structure */
 648 struct rte_ixgbe_xstats_name_off {
 649         char name[RTE_ETH_XSTATS_NAME_SIZE];
 650         unsigned offset;
 651 };
 652
 653 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 654         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 655         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 656         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 657         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 658         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 659         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 660         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 661         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 662         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 663         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 664         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 665         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 666         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 667         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 668         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 669                 prc1023)},
 670         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 671                 prc1522)},
 672         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 673         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 674         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 675         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 676         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 677         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 678         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 679         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 680         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 681         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 682         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 683         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 684         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 685         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 686         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 687         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 688         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 689                 ptc1023)},
 690         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 691                 ptc1522)},
 692         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 693         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 694         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 695         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 696
 697         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 698                 fdirustat_add)},
 699         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 700                 fdirustat_remove)},
 701         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 702                 fdirfstat_fadd)},
 703         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 704                 fdirfstat_fremove)},
 705         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 706                 fdirmatch)},
 707         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 708                 fdirmiss)},
 709
 710         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 711         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 712         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 713                 fclast)},
 714         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 715         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 716         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 717         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 718         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 719                 fcoe_noddp)},
 720         {"rx_fcoe_no_direct_data_placement_ext_buff",
 721                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 722
 723         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 724                 lxontxc)},
 725         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 726                 lxonrxc)},
 727         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 728                 lxofftxc)},
 729         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 730                 lxoffrxc)},
 731         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 732 };
 733
 734 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 735                            sizeof(rte_ixgbe_stats_strings[0]))
 736
 737 /* MACsec statistics */
 738 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 739         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 740                 out_pkts_untagged)},
 741         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 742                 out_pkts_encrypted)},
 743         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 744                 out_pkts_protected)},
 745         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 746                 out_octets_encrypted)},
 747         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 748                 out_octets_protected)},
 749         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_untagged)},
 751         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_badtag)},
 753         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_nosci)},
 755         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unknownsci)},
 757         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 758                 in_octets_decrypted)},
 759         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 760                 in_octets_validated)},
 761         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_unchecked)},
 763         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_delayed)},
 765         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_late)},
 767         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_ok)},
 769         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_invalid)},
 771         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_notvalid)},
 773         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_unusedsa)},
 775         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_notusingsa)},
 777 };
 778
 779 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 780                            sizeof(rte_ixgbe_macsec_strings[0]))
 781
 782 /* Per-queue statistics */
 783 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 784         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 785         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 786         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 787         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 788 };
 789
 790 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 791                            sizeof(rte_ixgbe_rxq_strings[0]))
 792 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 793
 794 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 795         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 796         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 797         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 798                 pxon2offc)},
 799 };
 800
 801 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 802                            sizeof(rte_ixgbe_txq_strings[0]))
 803 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 804
 805 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 806         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 807 };
 808
 809 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 810                 sizeof(rte_ixgbevf_stats_strings[0]))
 811
 812 /**
 813  * Atomically reads the link status information from global
 814  * structure rte_eth_dev.
 815  *
 816  * @param dev
 817  *   - Pointer to the structure rte_eth_dev to read from.
 818  *   - Pointer to the buffer to be saved with the link status.
 819  *
 820  * @return
 821  *   - On success, zero.
 822  *   - On failure, negative value.
 823  */
 824 static inline int
 825 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 826                                 struct rte_eth_link *link)
 827 {
 828         struct rte_eth_link *dst = link;
 829         struct rte_eth_link *src = &(dev->data->dev_link);
 830
 831         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 832                                         *(uint64_t *)src) == 0)
 833                 return -1;
 834
 835         return 0;
 836 }
 837
 838 /**
 839  * Atomically writes the link status information into global
 840  * structure rte_eth_dev.
 841  *
 842  * @param dev
 843  *   - Pointer to the structure rte_eth_dev to read from.
 844  *   - Pointer to the buffer to be saved with the link status.
 845  *
 846  * @return
 847  *   - On success, zero.
 848  *   - On failure, negative value.
 849  */
 850 static inline int
 851 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 852                                 struct rte_eth_link *link)
 853 {
 854         struct rte_eth_link *dst = &(dev->data->dev_link);
 855         struct rte_eth_link *src = link;
 856
 857         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 858                                         *(uint64_t *)src) == 0)
 859                 return -1;
 860
 861         return 0;
 862 }
 863
 864 /*
 865  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 866  */
 867 static inline int
 868 ixgbe_is_sfp(struct ixgbe_hw *hw)
 869 {
 870         switch (hw->phy.type) {
 871         case ixgbe_phy_sfp_avago:
 872         case ixgbe_phy_sfp_ftl:
 873         case ixgbe_phy_sfp_intel:
 874         case ixgbe_phy_sfp_unknown:
 875         case ixgbe_phy_sfp_passive_tyco:
 876         case ixgbe_phy_sfp_passive_unknown:
 877                 return 1;
 878         default:
 879                 return 0;
 880         }
 881 }
 882
 883 static inline int32_t
 884 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 885 {
 886         uint32_t ctrl_ext;
 887         int32_t status;
 888
 889         status = ixgbe_reset_hw(hw);
 890
 891         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 892         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 893         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 894         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 895         IXGBE_WRITE_FLUSH(hw);
 896
 897         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 898                 status = IXGBE_SUCCESS;
 899         return status;
 900 }
 901
 902 static inline void
 903 ixgbe_enable_intr(struct rte_eth_dev *dev)
 904 {
 905         struct ixgbe_interrupt *intr =
 906                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 907         struct ixgbe_hw *hw =
 908                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 909
 910         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 911         IXGBE_WRITE_FLUSH(hw);
 912 }
 913
 914 /*
 915  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 916  */
 917 static void
 918 ixgbe_disable_intr(struct ixgbe_hw *hw)
 919 {
 920         PMD_INIT_FUNC_TRACE();
 921
 922         if (hw->mac.type == ixgbe_mac_82598EB) {
 923                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 924         } else {
 925                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 927                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 928         }
 929         IXGBE_WRITE_FLUSH(hw);
 930 }
 931
 932 /*
 933  * This function resets queue statistics mapping registers.
 934  * From Niantic datasheet, Initialization of Statistics section:
 935  * "...if software requires the queue counters, the RQSMR and TQSM registers
 936  * must be re-programmed following a device reset.
 937  */
 938 static void
 939 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 940 {
 941         uint32_t i;
 942
 943         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 944                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 946         }
 947 }
 948
 949
 950 static int
 951 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 952                                   uint16_t queue_id,
 953                                   uint8_t stat_idx,
 954                                   uint8_t is_rx)
 955 {
 956 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 957 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 958 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 959
 960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 961         struct ixgbe_stat_mapping_registers *stat_mappings =
 962                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 963         uint32_t qsmr_mask = 0;
 964         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 965         uint32_t q_map;
 966         uint8_t n, offset;
 967
 968         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 969                 (hw->mac.type != ixgbe_mac_X540) &&
 970                 (hw->mac.type != ixgbe_mac_X550) &&
 971                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 972                 (hw->mac.type != ixgbe_mac_X550EM_a))
 973                 return -ENOSYS;
 974
 975         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 976                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 977                      queue_id, stat_idx);
 978
 979         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 980         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 981                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 982                 return -EIO;
 983         }
 984         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 985
 986         /* Now clear any previous stat_idx set */
 987         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 988         if (!is_rx)
 989                 stat_mappings->tqsm[n] &= ~clearing_mask;
 990         else
 991                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 992
 993         q_map = (uint32_t)stat_idx;
 994         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 995         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 996         if (!is_rx)
 997                 stat_mappings->tqsm[n] |= qsmr_mask;
 998         else
 999                 stat_mappings->rqsmr[n] |= qsmr_mask;
1000
1001         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1002                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1003                      queue_id, stat_idx);
1004         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1005                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1006
1007         /* Now write the mapping in the appropriate register */
1008         if (is_rx) {
1009                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1010                              stat_mappings->rqsmr[n], n);
1011                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1012         } else {
1013                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1014                              stat_mappings->tqsm[n], n);
1015                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1016         }
1017         return 0;
1018 }
1019
1020 static void
1021 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1022 {
1023         struct ixgbe_stat_mapping_registers *stat_mappings =
1024                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026         int i;
1027
1028         /* write whatever was in stat mapping table to the NIC */
1029         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1030                 /* rx */
1031                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1032
1033                 /* tx */
1034                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1035         }
1036 }
1037
1038 static void
1039 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1040 {
1041         uint8_t i;
1042         struct ixgbe_dcb_tc_config *tc;
1043         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1044
1045         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1046         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1047         for (i = 0; i < dcb_max_tc; i++) {
1048                 tc = &dcb_config->tc_config[i];
1049                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1050                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1051                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1052                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1053                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1054                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1055                 tc->pfc = ixgbe_dcb_pfc_disabled;
1056         }
1057
1058         /* Initialize default user to priority mapping, UPx->TC0 */
1059         tc = &dcb_config->tc_config[0];
1060         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1061         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1062         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1063                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1064                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1065         }
1066         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1067         dcb_config->pfc_mode_enable = false;
1068         dcb_config->vt_mode = true;
1069         dcb_config->round_robin_enable = false;
1070         /* support all DCB capabilities in 82599 */
1071         dcb_config->support.capabilities = 0xFF;
1072
1073         /*we only support 4 Tcs for X540, X550 */
1074         if (hw->mac.type == ixgbe_mac_X540 ||
1075                 hw->mac.type == ixgbe_mac_X550 ||
1076                 hw->mac.type == ixgbe_mac_X550EM_x ||
1077                 hw->mac.type == ixgbe_mac_X550EM_a) {
1078                 dcb_config->num_tcs.pg_tcs = 4;
1079                 dcb_config->num_tcs.pfc_tcs = 4;
1080         }
1081 }
1082
1083 /*
1084  * Ensure that all locks are released before first NVM or PHY access
1085  */
1086 static void
1087 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1088 {
1089         uint16_t mask;
1090
1091         /*
1092          * Phy lock should not fail in this early stage. If this is the case,
1093          * it is due to an improper exit of the application.
1094          * So force the release of the faulty lock. Release of common lock
1095          * is done automatically by swfw_sync function.
1096          */
1097         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1098         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1099                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1100         }
1101         ixgbe_release_swfw_semaphore(hw, mask);
1102
1103         /*
1104          * These ones are more tricky since they are common to all ports; but
1105          * swfw_sync retries last long enough (1s) to be almost sure that if
1106          * lock can not be taken it is due to an improper lock of the
1107          * semaphore.
1108          */
1109         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1110         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1111                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1112         }
1113         ixgbe_release_swfw_semaphore(hw, mask);
1114 }
1115
1116 /*
1117  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1118  * It returns 0 on success.
1119  */
1120 static int
1121 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1122 {
1123         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1124         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1125         struct ixgbe_hw *hw =
1126                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1127         struct ixgbe_vfta *shadow_vfta =
1128                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1129         struct ixgbe_hwstrip *hwstrip =
1130                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1131         struct ixgbe_dcb_config *dcb_config =
1132                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1133         struct ixgbe_filter_info *filter_info =
1134                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1135         struct ixgbe_bw_conf *bw_conf =
1136                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1137         uint32_t ctrl_ext;
1138         uint16_t csum;
1139         int diag, i;
1140
1141         PMD_INIT_FUNC_TRACE();
1142
1143         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1144         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1145         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1146         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1147
1148         /*
1149          * For secondary processes, we don't initialise any further as primary
1150          * has already done this work. Only check we don't need a different
1151          * RX and TX function.
1152          */
1153         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1154                 struct ixgbe_tx_queue *txq;
1155                 /* TX queue function in primary, set by last queue initialized
1156                  * Tx queue may not initialized by primary process
1157                  */
1158                 if (eth_dev->data->tx_queues) {
1159                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1160                         ixgbe_set_tx_function(eth_dev, txq);
1161                 } else {
1162                         /* Use default TX function if we get here */
1163                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1164                                      "Using default TX function.");
1165                 }
1166
1167                 ixgbe_set_rx_function(eth_dev);
1168
1169                 return 0;
1170         }
1171
1172         rte_eth_copy_pci_info(eth_dev, pci_dev);
1173         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1174
1175         /* Vendor and Device ID need to be set before init of shared code */
1176         hw->device_id = pci_dev->id.device_id;
1177         hw->vendor_id = pci_dev->id.vendor_id;
1178         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1179         hw->allow_unsupported_sfp = 1;
1180
1181         /* Initialize the shared code (base driver) */
1182 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1183         diag = ixgbe_bypass_init_shared_code(hw);
1184 #else
1185         diag = ixgbe_init_shared_code(hw);
1186 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1187
1188         if (diag != IXGBE_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1190                 return -EIO;
1191         }
1192
1193         /* pick up the PCI bus settings for reporting later */
1194         ixgbe_get_bus_info(hw);
1195
1196         /* Unlock any pending hardware semaphore */
1197         ixgbe_swfw_lock_reset(hw);
1198
1199         /* Initialize DCB configuration*/
1200         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1201         ixgbe_dcb_init(hw, dcb_config);
1202         /* Get Hardware Flow Control setting */
1203         hw->fc.requested_mode = ixgbe_fc_full;
1204         hw->fc.current_mode = ixgbe_fc_full;
1205         hw->fc.pause_time = IXGBE_FC_PAUSE;
1206         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1207                 hw->fc.low_water[i] = IXGBE_FC_LO;
1208                 hw->fc.high_water[i] = IXGBE_FC_HI;
1209         }
1210         hw->fc.send_xon = 1;
1211
1212         /* Make sure we have a good EEPROM before we read from it */
1213         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1214         if (diag != IXGBE_SUCCESS) {
1215                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1216                 return -EIO;
1217         }
1218
1219 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1220         diag = ixgbe_bypass_init_hw(hw);
1221 #else
1222         diag = ixgbe_init_hw(hw);
1223 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1224
1225         /*
1226          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1227          * is called too soon after the kernel driver unbinding/binding occurs.
1228          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1229          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1230          * also called. See ixgbe_identify_phy_82599(). The reason for the
1231          * failure is not known, and only occuts when virtualisation features
1232          * are disabled in the bios. A delay of 100ms  was found to be enough by
1233          * trial-and-error, and is doubled to be safe.
1234          */
1235         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1236                 rte_delay_ms(200);
1237                 diag = ixgbe_init_hw(hw);
1238         }
1239
1240         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1241                 diag = IXGBE_SUCCESS;
1242
1243         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1244                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1245                              "LOM.  Please be aware there may be issues associated "
1246                              "with your hardware.");
1247                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1248                              "please contact your Intel or hardware representative "
1249                              "who provided you with this hardware.");
1250         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1251                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1252         if (diag) {
1253                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1254                 return -EIO;
1255         }
1256
1257         /* Reset the hw statistics */
1258         ixgbe_dev_stats_reset(eth_dev);
1259
1260         /* disable interrupt */
1261         ixgbe_disable_intr(hw);
1262
1263         /* reset mappings for queue statistics hw counters*/
1264         ixgbe_reset_qstat_mappings(hw);
1265
1266         /* Allocate memory for storing MAC addresses */
1267         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1268                                                hw->mac.num_rar_entries, 0);
1269         if (eth_dev->data->mac_addrs == NULL) {
1270                 PMD_INIT_LOG(ERR,
1271                              "Failed to allocate %u bytes needed to store "
1272                              "MAC addresses",
1273                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1274                 return -ENOMEM;
1275         }
1276         /* Copy the permanent MAC address */
1277         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1278                         &eth_dev->data->mac_addrs[0]);
1279
1280         /* Allocate memory for storing hash filter MAC addresses */
1281         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1282                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1283         if (eth_dev->data->hash_mac_addrs == NULL) {
1284                 PMD_INIT_LOG(ERR,
1285                              "Failed to allocate %d bytes needed to store MAC addresses",
1286                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1287                 return -ENOMEM;
1288         }
1289
1290         /* initialize the vfta */
1291         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1292
1293         /* initialize the hw strip bitmap*/
1294         memset(hwstrip, 0, sizeof(*hwstrip));
1295
1296         /* initialize PF if max_vfs not zero */
1297         ixgbe_pf_host_init(eth_dev);
1298
1299         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1300         /* let hardware know driver is loaded */
1301         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1302         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1303         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1304         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1305         IXGBE_WRITE_FLUSH(hw);
1306
1307         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1308                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1309                              (int) hw->mac.type, (int) hw->phy.type,
1310                              (int) hw->phy.sfp_type);
1311         else
1312                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1313                              (int) hw->mac.type, (int) hw->phy.type);
1314
1315         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1316                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1317                      pci_dev->id.device_id);
1318
1319         rte_intr_callback_register(intr_handle,
1320                                    ixgbe_dev_interrupt_handler, eth_dev);
1321
1322         /* enable uio/vfio intr/eventfd mapping */
1323         rte_intr_enable(intr_handle);
1324
1325         /* enable support intr */
1326         ixgbe_enable_intr(eth_dev);
1327
1328         /* initialize filter info */
1329         memset(filter_info, 0,
1330                sizeof(struct ixgbe_filter_info));
1331
1332         /* initialize 5tuple filter list */
1333         TAILQ_INIT(&filter_info->fivetuple_list);
1334
1335         /* initialize flow director filter list & hash */
1336         ixgbe_fdir_filter_init(eth_dev);
1337
1338         /* initialize l2 tunnel filter list & hash */
1339         ixgbe_l2_tn_filter_init(eth_dev);
1340
1341         TAILQ_INIT(&filter_ntuple_list);
1342         TAILQ_INIT(&filter_ethertype_list);
1343         TAILQ_INIT(&filter_syn_list);
1344         TAILQ_INIT(&filter_fdir_list);
1345         TAILQ_INIT(&filter_l2_tunnel_list);
1346         TAILQ_INIT(&ixgbe_flow_list);
1347
1348         /* initialize bandwidth configuration info */
1349         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1350
1351         return 0;
1352 }
1353
1354 static int
1355 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1356 {
1357         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1358         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1359         struct ixgbe_hw *hw;
1360
1361         PMD_INIT_FUNC_TRACE();
1362
1363         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1364                 return -EPERM;
1365
1366         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1367
1368         if (hw->adapter_stopped == 0)
1369                 ixgbe_dev_close(eth_dev);
1370
1371         eth_dev->dev_ops = NULL;
1372         eth_dev->rx_pkt_burst = NULL;
1373         eth_dev->tx_pkt_burst = NULL;
1374
1375         /* Unlock any pending hardware semaphore */
1376         ixgbe_swfw_lock_reset(hw);
1377
1378         /* disable uio intr before callback unregister */
1379         rte_intr_disable(intr_handle);
1380         rte_intr_callback_unregister(intr_handle,
1381                                      ixgbe_dev_interrupt_handler, eth_dev);
1382
1383         /* uninitialize PF if max_vfs not zero */
1384         ixgbe_pf_host_uninit(eth_dev);
1385
1386         rte_free(eth_dev->data->mac_addrs);
1387         eth_dev->data->mac_addrs = NULL;
1388
1389         rte_free(eth_dev->data->hash_mac_addrs);
1390         eth_dev->data->hash_mac_addrs = NULL;
1391
1392         /* remove all the fdir filters & hash */
1393         ixgbe_fdir_filter_uninit(eth_dev);
1394
1395         /* remove all the L2 tunnel filters & hash */
1396         ixgbe_l2_tn_filter_uninit(eth_dev);
1397
1398         /* Remove all ntuple filters of the device */
1399         ixgbe_ntuple_filter_uninit(eth_dev);
1400
1401         /* clear all the filters list */
1402         ixgbe_filterlist_flush();
1403
1404         return 0;
1405 }
1406
1407 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1408 {
1409         struct ixgbe_filter_info *filter_info =
1410                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1411         struct ixgbe_5tuple_filter *p_5tuple;
1412
1413         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1414                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1415                              p_5tuple,
1416                              entries);
1417                 rte_free(p_5tuple);
1418         }
1419         memset(filter_info->fivetuple_mask, 0,
1420                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1421
1422         return 0;
1423 }
1424
1425 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1426 {
1427         struct ixgbe_hw_fdir_info *fdir_info =
1428                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1429         struct ixgbe_fdir_filter *fdir_filter;
1430
1431                 if (fdir_info->hash_map)
1432                 rte_free(fdir_info->hash_map);
1433         if (fdir_info->hash_handle)
1434                 rte_hash_free(fdir_info->hash_handle);
1435
1436         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1437                 TAILQ_REMOVE(&fdir_info->fdir_list,
1438                              fdir_filter,
1439                              entries);
1440                 rte_free(fdir_filter);
1441         }
1442
1443         return 0;
1444 }
1445
1446 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1447 {
1448         struct ixgbe_l2_tn_info *l2_tn_info =
1449                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1450         struct ixgbe_l2_tn_filter *l2_tn_filter;
1451
1452         if (l2_tn_info->hash_map)
1453                 rte_free(l2_tn_info->hash_map);
1454         if (l2_tn_info->hash_handle)
1455                 rte_hash_free(l2_tn_info->hash_handle);
1456
1457         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1458                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1459                              l2_tn_filter,
1460                              entries);
1461                 rte_free(l2_tn_filter);
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1468 {
1469         struct ixgbe_hw_fdir_info *fdir_info =
1470                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1471         char fdir_hash_name[RTE_HASH_NAMESIZE];
1472         struct rte_hash_parameters fdir_hash_params = {
1473                 .name = fdir_hash_name,
1474                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1475                 .key_len = sizeof(union ixgbe_atr_input),
1476                 .hash_func = rte_hash_crc,
1477                 .hash_func_init_val = 0,
1478                 .socket_id = rte_socket_id(),
1479         };
1480
1481         TAILQ_INIT(&fdir_info->fdir_list);
1482         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1483                  "fdir_%s", eth_dev->data->name);
1484         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1485         if (!fdir_info->hash_handle) {
1486                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1487                 return -EINVAL;
1488         }
1489         fdir_info->hash_map = rte_zmalloc("ixgbe",
1490                                           sizeof(struct ixgbe_fdir_filter *) *
1491                                           IXGBE_MAX_FDIR_FILTER_NUM,
1492                                           0);
1493         if (!fdir_info->hash_map) {
1494                 PMD_INIT_LOG(ERR,
1495                              "Failed to allocate memory for fdir hash map!");
1496                 return -ENOMEM;
1497         }
1498         fdir_info->mask_added = FALSE;
1499
1500         return 0;
1501 }
1502
1503 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1504 {
1505         struct ixgbe_l2_tn_info *l2_tn_info =
1506                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1507         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1508         struct rte_hash_parameters l2_tn_hash_params = {
1509                 .name = l2_tn_hash_name,
1510                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1511                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1512                 .hash_func = rte_hash_crc,
1513                 .hash_func_init_val = 0,
1514                 .socket_id = rte_socket_id(),
1515         };
1516
1517         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1518         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1519                  "l2_tn_%s", eth_dev->data->name);
1520         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1521         if (!l2_tn_info->hash_handle) {
1522                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1523                 return -EINVAL;
1524         }
1525         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1526                                    sizeof(struct ixgbe_l2_tn_filter *) *
1527                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1528                                    0);
1529         if (!l2_tn_info->hash_map) {
1530                 PMD_INIT_LOG(ERR,
1531                         "Failed to allocate memory for L2 TN hash map!");
1532                 return -ENOMEM;
1533         }
1534         l2_tn_info->e_tag_en = FALSE;
1535         l2_tn_info->e_tag_fwd_en = FALSE;
1536         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1537
1538         return 0;
1539 }
1540 /*
1541  * Negotiate mailbox API version with the PF.
1542  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1543  * Then we try to negotiate starting with the most recent one.
1544  * If all negotiation attempts fail, then we will proceed with
1545  * the default one (ixgbe_mbox_api_10).
1546  */
1547 static void
1548 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1549 {
1550         int32_t i;
1551
1552         /* start with highest supported, proceed down */
1553         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1554                 ixgbe_mbox_api_12,
1555                 ixgbe_mbox_api_11,
1556                 ixgbe_mbox_api_10,
1557         };
1558
1559         for (i = 0;
1560                         i != RTE_DIM(sup_ver) &&
1561                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1562                         i++)
1563                 ;
1564 }
1565
1566 static void
1567 generate_random_mac_addr(struct ether_addr *mac_addr)
1568 {
1569         uint64_t random;
1570
1571         /* Set Organizationally Unique Identifier (OUI) prefix. */
1572         mac_addr->addr_bytes[0] = 0x00;
1573         mac_addr->addr_bytes[1] = 0x09;
1574         mac_addr->addr_bytes[2] = 0xC0;
1575         /* Force indication of locally assigned MAC address. */
1576         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1577         /* Generate the last 3 bytes of the MAC address with a random number. */
1578         random = rte_rand();
1579         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1580 }
1581
1582 /*
1583  * Virtual Function device init
1584  */
1585 static int
1586 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1587 {
1588         int diag;
1589         uint32_t tc, tcs;
1590         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1591         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1592         struct ixgbe_hw *hw =
1593                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1594         struct ixgbe_vfta *shadow_vfta =
1595                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1596         struct ixgbe_hwstrip *hwstrip =
1597                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1598         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1599
1600         PMD_INIT_FUNC_TRACE();
1601
1602         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1603         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1604         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1605
1606         /* for secondary processes, we don't initialise any further as primary
1607          * has already done this work. Only check we don't need a different
1608          * RX function
1609          */
1610         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1611                 struct ixgbe_tx_queue *txq;
1612                 /* TX queue function in primary, set by last queue initialized
1613                  * Tx queue may not initialized by primary process
1614                  */
1615                 if (eth_dev->data->tx_queues) {
1616                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1617                         ixgbe_set_tx_function(eth_dev, txq);
1618                 } else {
1619                         /* Use default TX function if we get here */
1620                         PMD_INIT_LOG(NOTICE,
1621                                      "No TX queues configured yet. Using default TX function.");
1622                 }
1623
1624                 ixgbe_set_rx_function(eth_dev);
1625
1626                 return 0;
1627         }
1628
1629         rte_eth_copy_pci_info(eth_dev, pci_dev);
1630         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1631
1632         hw->device_id = pci_dev->id.device_id;
1633         hw->vendor_id = pci_dev->id.vendor_id;
1634         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1635
1636         /* initialize the vfta */
1637         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1638
1639         /* initialize the hw strip bitmap*/
1640         memset(hwstrip, 0, sizeof(*hwstrip));
1641
1642         /* Initialize the shared code (base driver) */
1643         diag = ixgbe_init_shared_code(hw);
1644         if (diag != IXGBE_SUCCESS) {
1645                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1646                 return -EIO;
1647         }
1648
1649         /* init_mailbox_params */
1650         hw->mbx.ops.init_params(hw);
1651
1652         /* Reset the hw statistics */
1653         ixgbevf_dev_stats_reset(eth_dev);
1654
1655         /* Disable the interrupts for VF */
1656         ixgbevf_intr_disable(hw);
1657
1658         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1659         diag = hw->mac.ops.reset_hw(hw);
1660
1661         /*
1662          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1663          * the underlying PF driver has not assigned a MAC address to the VF.
1664          * In this case, assign a random MAC address.
1665          */
1666         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1667                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1668                 return diag;
1669         }
1670
1671         /* negotiate mailbox API version to use with the PF. */
1672         ixgbevf_negotiate_api(hw);
1673
1674         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1675         ixgbevf_get_queues(hw, &tcs, &tc);
1676
1677         /* Allocate memory for storing MAC addresses */
1678         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1679                                                hw->mac.num_rar_entries, 0);
1680         if (eth_dev->data->mac_addrs == NULL) {
1681                 PMD_INIT_LOG(ERR,
1682                              "Failed to allocate %u bytes needed to store "
1683                              "MAC addresses",
1684                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1685                 return -ENOMEM;
1686         }
1687
1688         /* Generate a random MAC address, if none was assigned by PF. */
1689         if (is_zero_ether_addr(perm_addr)) {
1690                 generate_random_mac_addr(perm_addr);
1691                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1692                 if (diag) {
1693                         rte_free(eth_dev->data->mac_addrs);
1694                         eth_dev->data->mac_addrs = NULL;
1695                         return diag;
1696                 }
1697                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1698                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1699                              "%02x:%02x:%02x:%02x:%02x:%02x",
1700                              perm_addr->addr_bytes[0],
1701                              perm_addr->addr_bytes[1],
1702                              perm_addr->addr_bytes[2],
1703                              perm_addr->addr_bytes[3],
1704                              perm_addr->addr_bytes[4],
1705                              perm_addr->addr_bytes[5]);
1706         }
1707
1708         /* Copy the permanent MAC address */
1709         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1710
1711         /* reset the hardware with the new settings */
1712         diag = hw->mac.ops.start_hw(hw);
1713         switch (diag) {
1714         case  0:
1715                 break;
1716
1717         default:
1718                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1719                 return -EIO;
1720         }
1721
1722         rte_intr_callback_register(intr_handle,
1723                                    ixgbevf_dev_interrupt_handler, eth_dev);
1724         rte_intr_enable(intr_handle);
1725         ixgbevf_intr_enable(hw);
1726
1727         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1728                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1729                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1730
1731         return 0;
1732 }
1733
1734 /* Virtual Function device uninit */
1735
1736 static int
1737 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1738 {
1739         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1740         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1741         struct ixgbe_hw *hw;
1742
1743         PMD_INIT_FUNC_TRACE();
1744
1745         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1746                 return -EPERM;
1747
1748         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1749
1750         if (hw->adapter_stopped == 0)
1751                 ixgbevf_dev_close(eth_dev);
1752
1753         eth_dev->dev_ops = NULL;
1754         eth_dev->rx_pkt_burst = NULL;
1755         eth_dev->tx_pkt_burst = NULL;
1756
1757         /* Disable the interrupts for VF */
1758         ixgbevf_intr_disable(hw);
1759
1760         rte_free(eth_dev->data->mac_addrs);
1761         eth_dev->data->mac_addrs = NULL;
1762
1763         rte_intr_disable(intr_handle);
1764         rte_intr_callback_unregister(intr_handle,
1765                                      ixgbevf_dev_interrupt_handler, eth_dev);
1766
1767         return 0;
1768 }
1769
1770 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1771         struct rte_pci_device *pci_dev)
1772 {
1773         return rte_eth_dev_pci_generic_probe(pci_dev,
1774                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1775 }
1776
1777 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1778 {
1779         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1780 }
1781
1782 static struct rte_pci_driver rte_ixgbe_pmd = {
1783         .id_table = pci_id_ixgbe_map,
1784         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1785         .probe = eth_ixgbe_pci_probe,
1786         .remove = eth_ixgbe_pci_remove,
1787 };
1788
1789 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1790         struct rte_pci_device *pci_dev)
1791 {
1792         return rte_eth_dev_pci_generic_probe(pci_dev,
1793                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1794 }
1795
1796 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1797 {
1798         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1799 }
1800
1801 /*
1802  * virtual function driver struct
1803  */
1804 static struct rte_pci_driver rte_ixgbevf_pmd = {
1805         .id_table = pci_id_ixgbevf_map,
1806         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1807         .probe = eth_ixgbevf_pci_probe,
1808         .remove = eth_ixgbevf_pci_remove,
1809 };
1810
1811 static int
1812 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1813 {
1814         struct ixgbe_hw *hw =
1815                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816         struct ixgbe_vfta *shadow_vfta =
1817                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1818         uint32_t vfta;
1819         uint32_t vid_idx;
1820         uint32_t vid_bit;
1821
1822         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1823         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1824         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1825         if (on)
1826                 vfta |= vid_bit;
1827         else
1828                 vfta &= ~vid_bit;
1829         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1830
1831         /* update local VFTA copy */
1832         shadow_vfta->vfta[vid_idx] = vfta;
1833
1834         return 0;
1835 }
1836
1837 static void
1838 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1839 {
1840         if (on)
1841                 ixgbe_vlan_hw_strip_enable(dev, queue);
1842         else
1843                 ixgbe_vlan_hw_strip_disable(dev, queue);
1844 }
1845
1846 static int
1847 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1848                     enum rte_vlan_type vlan_type,
1849                     uint16_t tpid)
1850 {
1851         struct ixgbe_hw *hw =
1852                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         int ret = 0;
1854         uint32_t reg;
1855         uint32_t qinq;
1856
1857         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1858         qinq &= IXGBE_DMATXCTL_GDV;
1859
1860         switch (vlan_type) {
1861         case ETH_VLAN_TYPE_INNER:
1862                 if (qinq) {
1863                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1864                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1865                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1866                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1868                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1869                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1870                 } else {
1871                         ret = -ENOTSUP;
1872                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1873                                     " by single VLAN");
1874                 }
1875                 break;
1876         case ETH_VLAN_TYPE_OUTER:
1877                 if (qinq) {
1878                         /* Only the high 16-bits is valid */
1879                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1880                                         IXGBE_EXVET_VET_EXT_SHIFT);
1881                 } else {
1882                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1889                 }
1890
1891                 break;
1892         default:
1893                 ret = -EINVAL;
1894                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1895                 break;
1896         }
1897
1898         return ret;
1899 }
1900
1901 void
1902 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1903 {
1904         struct ixgbe_hw *hw =
1905                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1906         uint32_t vlnctrl;
1907
1908         PMD_INIT_FUNC_TRACE();
1909
1910         /* Filter Table Disable */
1911         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1913
1914         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1915 }
1916
1917 void
1918 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1919 {
1920         struct ixgbe_hw *hw =
1921                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct ixgbe_vfta *shadow_vfta =
1923                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1924         uint32_t vlnctrl;
1925         uint16_t i;
1926
1927         PMD_INIT_FUNC_TRACE();
1928
1929         /* Filter Table Enable */
1930         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1932         vlnctrl |= IXGBE_VLNCTRL_VFE;
1933
1934         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1935
1936         /* write whatever is in local vfta copy */
1937         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1938                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1939 }
1940
1941 static void
1942 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1943 {
1944         struct ixgbe_hwstrip *hwstrip =
1945                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1946         struct ixgbe_rx_queue *rxq;
1947
1948         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1949                 return;
1950
1951         if (on)
1952                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1953         else
1954                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1955
1956         if (queue >= dev->data->nb_rx_queues)
1957                 return;
1958
1959         rxq = dev->data->rx_queues[queue];
1960
1961         if (on)
1962                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1963         else
1964                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1965 }
1966
1967 static void
1968 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1969 {
1970         struct ixgbe_hw *hw =
1971                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972         uint32_t ctrl;
1973
1974         PMD_INIT_FUNC_TRACE();
1975
1976         if (hw->mac.type == ixgbe_mac_82598EB) {
1977                 /* No queue level support */
1978                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1979                 return;
1980         }
1981
1982         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1983         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1984         ctrl &= ~IXGBE_RXDCTL_VME;
1985         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1986
1987         /* record those setting for HW strip per queue */
1988         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1989 }
1990
1991 static void
1992 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1993 {
1994         struct ixgbe_hw *hw =
1995                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996         uint32_t ctrl;
1997
1998         PMD_INIT_FUNC_TRACE();
1999
2000         if (hw->mac.type == ixgbe_mac_82598EB) {
2001                 /* No queue level supported */
2002                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2003                 return;
2004         }
2005
2006         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2007         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2008         ctrl |= IXGBE_RXDCTL_VME;
2009         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2010
2011         /* record those setting for HW strip per queue */
2012         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2013 }
2014
2015 void
2016 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2017 {
2018         struct ixgbe_hw *hw =
2019                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2020         uint32_t ctrl;
2021         uint16_t i;
2022         struct ixgbe_rx_queue *rxq;
2023
2024         PMD_INIT_FUNC_TRACE();
2025
2026         if (hw->mac.type == ixgbe_mac_82598EB) {
2027                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2028                 ctrl &= ~IXGBE_VLNCTRL_VME;
2029                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2030         } else {
2031                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2032                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2033                         rxq = dev->data->rx_queues[i];
2034                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2035                         ctrl &= ~IXGBE_RXDCTL_VME;
2036                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2037
2038                         /* record those setting for HW strip per queue */
2039                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2040                 }
2041         }
2042 }
2043
2044 void
2045 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2046 {
2047         struct ixgbe_hw *hw =
2048                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2049         uint32_t ctrl;
2050         uint16_t i;
2051         struct ixgbe_rx_queue *rxq;
2052
2053         PMD_INIT_FUNC_TRACE();
2054
2055         if (hw->mac.type == ixgbe_mac_82598EB) {
2056                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2057                 ctrl |= IXGBE_VLNCTRL_VME;
2058                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2059         } else {
2060                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2061                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2062                         rxq = dev->data->rx_queues[i];
2063                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2064                         ctrl |= IXGBE_RXDCTL_VME;
2065                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2066
2067                         /* record those setting for HW strip per queue */
2068                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2069                 }
2070         }
2071 }
2072
2073 static void
2074 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2075 {
2076         struct ixgbe_hw *hw =
2077                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078         uint32_t ctrl;
2079
2080         PMD_INIT_FUNC_TRACE();
2081
2082         /* DMATXCTRL: Geric Double VLAN Disable */
2083         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2084         ctrl &= ~IXGBE_DMATXCTL_GDV;
2085         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2086
2087         /* CTRL_EXT: Global Double VLAN Disable */
2088         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2089         ctrl &= ~IXGBE_EXTENDED_VLAN;
2090         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2091
2092 }
2093
2094 static void
2095 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2096 {
2097         struct ixgbe_hw *hw =
2098                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         uint32_t ctrl;
2100
2101         PMD_INIT_FUNC_TRACE();
2102
2103         /* DMATXCTRL: Geric Double VLAN Enable */
2104         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2105         ctrl |= IXGBE_DMATXCTL_GDV;
2106         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2107
2108         /* CTRL_EXT: Global Double VLAN Enable */
2109         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2110         ctrl |= IXGBE_EXTENDED_VLAN;
2111         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2112
2113         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2114         if (hw->mac.type == ixgbe_mac_X550 ||
2115             hw->mac.type == ixgbe_mac_X550EM_x ||
2116             hw->mac.type == ixgbe_mac_X550EM_a) {
2117                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2118                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2119                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2120         }
2121
2122         /*
2123          * VET EXT field in the EXVET register = 0x8100 by default
2124          * So no need to change. Same to VT field of DMATXCTL register
2125          */
2126 }
2127
2128 static void
2129 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2130 {
2131         if (mask & ETH_VLAN_STRIP_MASK) {
2132                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2133                         ixgbe_vlan_hw_strip_enable_all(dev);
2134                 else
2135                         ixgbe_vlan_hw_strip_disable_all(dev);
2136         }
2137
2138         if (mask & ETH_VLAN_FILTER_MASK) {
2139                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2140                         ixgbe_vlan_hw_filter_enable(dev);
2141                 else
2142                         ixgbe_vlan_hw_filter_disable(dev);
2143         }
2144
2145         if (mask & ETH_VLAN_EXTEND_MASK) {
2146                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2147                         ixgbe_vlan_hw_extend_enable(dev);
2148                 else
2149                         ixgbe_vlan_hw_extend_disable(dev);
2150         }
2151 }
2152
2153 static void
2154 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2155 {
2156         struct ixgbe_hw *hw =
2157                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2159         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2160
2161         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2162         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2163 }
2164
2165 static int
2166 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2167 {
2168         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2169
2170         switch (nb_rx_q) {
2171         case 1:
2172         case 2:
2173                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2174                 break;
2175         case 4:
2176                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2177                 break;
2178         default:
2179                 return -EINVAL;
2180         }
2181
2182         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2183         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2184
2185         return 0;
2186 }
2187
2188 static int
2189 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2190 {
2191         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2192         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2194         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2195
2196         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2197                 /* check multi-queue mode */
2198                 switch (dev_conf->rxmode.mq_mode) {
2199                 case ETH_MQ_RX_VMDQ_DCB:
2200                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2201                         break;
2202                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2203                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2204                         PMD_INIT_LOG(ERR, "SRIOV active,"
2205                                         " unsupported mq_mode rx %d.",
2206                                         dev_conf->rxmode.mq_mode);
2207                         return -EINVAL;
2208                 case ETH_MQ_RX_RSS:
2209                 case ETH_MQ_RX_VMDQ_RSS:
2210                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2211                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2212                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2213                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2214                                                 " invalid queue number"
2215                                                 " for VMDQ RSS, allowed"
2216                                                 " value are 1, 2 or 4.");
2217                                         return -EINVAL;
2218                                 }
2219                         break;
2220                 case ETH_MQ_RX_VMDQ_ONLY:
2221                 case ETH_MQ_RX_NONE:
2222                         /* if nothing mq mode configure, use default scheme */
2223                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2224                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2225                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2226                         break;
2227                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2228                         /* SRIOV only works in VMDq enable mode */
2229                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2230                                         " wrong mq_mode rx %d.",
2231                                         dev_conf->rxmode.mq_mode);
2232                         return -EINVAL;
2233                 }
2234
2235                 switch (dev_conf->txmode.mq_mode) {
2236                 case ETH_MQ_TX_VMDQ_DCB:
2237                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2238                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2239                         break;
2240                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2241                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2242                         break;
2243                 }
2244
2245                 /* check valid queue number */
2246                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2247                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2248                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2249                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2250                                         " must be less than or equal to %d.",
2251                                         nb_rx_q, nb_tx_q,
2252                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2253                         return -EINVAL;
2254                 }
2255         } else {
2256                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2257                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2258                                           " not supported.");
2259                         return -EINVAL;
2260                 }
2261                 /* check configuration for vmdb+dcb mode */
2262                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2263                         const struct rte_eth_vmdq_dcb_conf *conf;
2264
2265                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2266                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2267                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2268                                 return -EINVAL;
2269                         }
2270                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2271                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2272                                conf->nb_queue_pools == ETH_32_POOLS)) {
2273                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2274                                                 " nb_queue_pools must be %d or %d.",
2275                                                 ETH_16_POOLS, ETH_32_POOLS);
2276                                 return -EINVAL;
2277                         }
2278                 }
2279                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2280                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2281
2282                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2283                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2284                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2285                                 return -EINVAL;
2286                         }
2287                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2288                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2289                                conf->nb_queue_pools == ETH_32_POOLS)) {
2290                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2291                                                 " nb_queue_pools != %d and"
2292                                                 " nb_queue_pools != %d.",
2293                                                 ETH_16_POOLS, ETH_32_POOLS);
2294                                 return -EINVAL;
2295                         }
2296                 }
2297
2298                 /* For DCB mode check our configuration before we go further */
2299                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2300                         const struct rte_eth_dcb_rx_conf *conf;
2301
2302                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2303                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2304                                                  IXGBE_DCB_NB_QUEUES);
2305                                 return -EINVAL;
2306                         }
2307                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2308                         if (!(conf->nb_tcs == ETH_4_TCS ||
2309                                conf->nb_tcs == ETH_8_TCS)) {
2310                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2311                                                 " and nb_tcs != %d.",
2312                                                 ETH_4_TCS, ETH_8_TCS);
2313                                 return -EINVAL;
2314                         }
2315                 }
2316
2317                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2318                         const struct rte_eth_dcb_tx_conf *conf;
2319
2320                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2321                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2322                                                  IXGBE_DCB_NB_QUEUES);
2323                                 return -EINVAL;
2324                         }
2325                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2326                         if (!(conf->nb_tcs == ETH_4_TCS ||
2327                                conf->nb_tcs == ETH_8_TCS)) {
2328                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2329                                                 " and nb_tcs != %d.",
2330                                                 ETH_4_TCS, ETH_8_TCS);
2331                                 return -EINVAL;
2332                         }
2333                 }
2334
2335                 /*
2336                  * When DCB/VT is off, maximum number of queues changes,
2337                  * except for 82598EB, which remains constant.
2338                  */
2339                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2340                                 hw->mac.type != ixgbe_mac_82598EB) {
2341                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2342                                 PMD_INIT_LOG(ERR,
2343                                              "Neither VT nor DCB are enabled, "
2344                                              "nb_tx_q > %d.",
2345                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2346                                 return -EINVAL;
2347                         }
2348                 }
2349         }
2350         return 0;
2351 }
2352
2353 static int
2354 ixgbe_dev_configure(struct rte_eth_dev *dev)
2355 {
2356         struct ixgbe_interrupt *intr =
2357                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2358         struct ixgbe_adapter *adapter =
2359                 (struct ixgbe_adapter *)dev->data->dev_private;
2360         int ret;
2361
2362         PMD_INIT_FUNC_TRACE();
2363         /* multipe queue mode checking */
2364         ret  = ixgbe_check_mq_mode(dev);
2365         if (ret != 0) {
2366                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2367                             ret);
2368                 return ret;
2369         }
2370
2371         /* set flag to update link status after init */
2372         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2373
2374         /*
2375          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2376          * allocation or vector Rx preconditions we will reset it.
2377          */
2378         adapter->rx_bulk_alloc_allowed = true;
2379         adapter->rx_vec_allowed = true;
2380
2381         return 0;
2382 }
2383
2384 static void
2385 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2386 {
2387         struct ixgbe_hw *hw =
2388                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389         struct ixgbe_interrupt *intr =
2390                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2391         uint32_t gpie;
2392
2393         /* only set up it on X550EM_X */
2394         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2395                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2396                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2397                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2398                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2399                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2400         }
2401 }
2402
2403 int
2404 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2405                         uint16_t tx_rate, uint64_t q_msk)
2406 {
2407         struct ixgbe_hw *hw;
2408         struct ixgbe_vf_info *vfinfo;
2409         struct rte_eth_link link;
2410         uint8_t  nb_q_per_pool;
2411         uint32_t queue_stride;
2412         uint32_t queue_idx, idx = 0, vf_idx;
2413         uint32_t queue_end;
2414         uint16_t total_rate = 0;
2415         struct rte_pci_device *pci_dev;
2416
2417         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2418         rte_eth_link_get_nowait(dev->data->port_id, &link);
2419
2420         if (vf >= pci_dev->max_vfs)
2421                 return -EINVAL;
2422
2423         if (tx_rate > link.link_speed)
2424                 return -EINVAL;
2425
2426         if (q_msk == 0)
2427                 return 0;
2428
2429         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2431         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2432         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2433         queue_idx = vf * queue_stride;
2434         queue_end = queue_idx + nb_q_per_pool - 1;
2435         if (queue_end >= hw->mac.max_tx_queues)
2436                 return -EINVAL;
2437
2438         if (vfinfo) {
2439                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2440                         if (vf_idx == vf)
2441                                 continue;
2442                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2443                                 idx++)
2444                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2445                 }
2446         } else {
2447                 return -EINVAL;
2448         }
2449
2450         /* Store tx_rate for this vf. */
2451         for (idx = 0; idx < nb_q_per_pool; idx++) {
2452                 if (((uint64_t)0x1 << idx) & q_msk) {
2453                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2454                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2455                         total_rate += tx_rate;
2456                 }
2457         }
2458
2459         if (total_rate > dev->data->dev_link.link_speed) {
2460                 /* Reset stored TX rate of the VF if it causes exceed
2461                  * link speed.
2462                  */
2463                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2464                 return -EINVAL;
2465         }
2466
2467         /* Set RTTBCNRC of each queue/pool for vf X  */
2468         for (; queue_idx <= queue_end; queue_idx++) {
2469                 if (0x1 & q_msk)
2470                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2471                 q_msk = q_msk >> 1;
2472         }
2473
2474         return 0;
2475 }
2476
2477 /*
2478  * Configure device link speed and setup link.
2479  * It returns 0 on success.
2480  */
2481 static int
2482 ixgbe_dev_start(struct rte_eth_dev *dev)
2483 {
2484         struct ixgbe_hw *hw =
2485                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486         struct ixgbe_vf_info *vfinfo =
2487                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2488         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2489         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2490         uint32_t intr_vector = 0;
2491         int err, link_up = 0, negotiate = 0;
2492         uint32_t speed = 0;
2493         int mask = 0;
2494         int status;
2495         uint16_t vf, idx;
2496         uint32_t *link_speeds;
2497
2498         PMD_INIT_FUNC_TRACE();
2499
2500         /* IXGBE devices don't support:
2501         *    - half duplex (checked afterwards for valid speeds)
2502         *    - fixed speed: TODO implement
2503         */
2504         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2505                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2506                              dev->data->port_id);
2507                 return -EINVAL;
2508         }
2509
2510         /* disable uio/vfio intr/eventfd mapping */
2511         rte_intr_disable(intr_handle);
2512
2513         /* stop adapter */
2514         hw->adapter_stopped = 0;
2515         ixgbe_stop_adapter(hw);
2516
2517         /* reinitialize adapter
2518          * this calls reset and start
2519          */
2520         status = ixgbe_pf_reset_hw(hw);
2521         if (status != 0)
2522                 return -1;
2523         hw->mac.ops.start_hw(hw);
2524         hw->mac.get_link_status = true;
2525
2526         /* configure PF module if SRIOV enabled */
2527         ixgbe_pf_host_configure(dev);
2528
2529         ixgbe_dev_phy_intr_setup(dev);
2530
2531         /* check and configure queue intr-vector mapping */
2532         if ((rte_intr_cap_multiple(intr_handle) ||
2533              !RTE_ETH_DEV_SRIOV(dev).active) &&
2534             dev->data->dev_conf.intr_conf.rxq != 0) {
2535                 intr_vector = dev->data->nb_rx_queues;
2536                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2537                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2538                                         IXGBE_MAX_INTR_QUEUE_NUM);
2539                         return -ENOTSUP;
2540                 }
2541                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2542                         return -1;
2543         }
2544
2545         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2546                 intr_handle->intr_vec =
2547                         rte_zmalloc("intr_vec",
2548                                     dev->data->nb_rx_queues * sizeof(int), 0);
2549                 if (intr_handle->intr_vec == NULL) {
2550                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2551                                      " intr_vec", dev->data->nb_rx_queues);
2552                         return -ENOMEM;
2553                 }
2554         }
2555
2556         /* confiugre msix for sleep until rx interrupt */
2557         ixgbe_configure_msix(dev);
2558
2559         /* initialize transmission unit */
2560         ixgbe_dev_tx_init(dev);
2561
2562         /* This can fail when allocating mbufs for descriptor rings */
2563         err = ixgbe_dev_rx_init(dev);
2564         if (err) {
2565                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2566                 goto error;
2567         }
2568
2569     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2570                 ETH_VLAN_EXTEND_MASK;
2571         ixgbe_vlan_offload_set(dev, mask);
2572
2573         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2574                 /* Enable vlan filtering for VMDq */
2575                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2576         }
2577
2578         /* Configure DCB hw */
2579         ixgbe_configure_dcb(dev);
2580
2581         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2582                 err = ixgbe_fdir_configure(dev);
2583                 if (err)
2584                         goto error;
2585         }
2586
2587         /* Restore vf rate limit */
2588         if (vfinfo != NULL) {
2589                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2590                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2591                                 if (vfinfo[vf].tx_rate[idx] != 0)
2592                                         ixgbe_set_vf_rate_limit(
2593                                                 dev, vf,
2594                                                 vfinfo[vf].tx_rate[idx],
2595                                                 1 << idx);
2596         }
2597
2598         ixgbe_restore_statistics_mapping(dev);
2599
2600         err = ixgbe_dev_rxtx_start(dev);
2601         if (err < 0) {
2602                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2603                 goto error;
2604         }
2605
2606         /* Skip link setup if loopback mode is enabled for 82599. */
2607         if (hw->mac.type == ixgbe_mac_82599EB &&
2608                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2609                 goto skip_link_setup;
2610
2611         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2612                 err = hw->mac.ops.setup_sfp(hw);
2613                 if (err)
2614                         goto error;
2615         }
2616
2617         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2618                 /* Turn on the copper */
2619                 ixgbe_set_phy_power(hw, true);
2620         } else {
2621                 /* Turn on the laser */
2622                 ixgbe_enable_tx_laser(hw);
2623         }
2624
2625         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2626         if (err)
2627                 goto error;
2628         dev->data->dev_link.link_status = link_up;
2629
2630         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2631         if (err)
2632                 goto error;
2633
2634         link_speeds = &dev->data->dev_conf.link_speeds;
2635         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2636                         ETH_LINK_SPEED_10G)) {
2637                 PMD_INIT_LOG(ERR, "Invalid link setting");
2638                 goto error;
2639         }
2640
2641         speed = 0x0;
2642         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2643                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2644                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2645                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2646         } else {
2647                 if (*link_speeds & ETH_LINK_SPEED_10G)
2648                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2649                 if (*link_speeds & ETH_LINK_SPEED_1G)
2650                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2651                 if (*link_speeds & ETH_LINK_SPEED_100M)
2652                         speed |= IXGBE_LINK_SPEED_100_FULL;
2653         }
2654
2655         err = ixgbe_setup_link(hw, speed, link_up);
2656         if (err)
2657                 goto error;
2658
2659 skip_link_setup:
2660
2661         if (rte_intr_allow_others(intr_handle)) {
2662                 /* check if lsc interrupt is enabled */
2663                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2664                         ixgbe_dev_lsc_interrupt_setup(dev);
2665                 ixgbe_dev_macsec_interrupt_setup(dev);
2666         } else {
2667                 rte_intr_callback_unregister(intr_handle,
2668                                              ixgbe_dev_interrupt_handler, dev);
2669                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2670                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2671                                      " no intr multiplex");
2672         }
2673
2674         /* check if rxq interrupt is enabled */
2675         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2676             rte_intr_dp_is_en(intr_handle))
2677                 ixgbe_dev_rxq_interrupt_setup(dev);
2678
2679         /* enable uio/vfio intr/eventfd mapping */
2680         rte_intr_enable(intr_handle);
2681
2682         /* resume enabled intr since hw reset */
2683         ixgbe_enable_intr(dev);
2684         ixgbe_l2_tunnel_conf(dev);
2685         ixgbe_filter_restore(dev);
2686
2687         return 0;
2688
2689 error:
2690         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2691         ixgbe_dev_clear_queues(dev);
2692         return -EIO;
2693 }
2694
2695 /*
2696  * Stop device: disable rx and tx functions to allow for reconfiguring.
2697  */
2698 static void
2699 ixgbe_dev_stop(struct rte_eth_dev *dev)
2700 {
2701         struct rte_eth_link link;
2702         struct ixgbe_hw *hw =
2703                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704         struct ixgbe_vf_info *vfinfo =
2705                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2706         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2707         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2708         int vf;
2709
2710         PMD_INIT_FUNC_TRACE();
2711
2712         /* disable interrupts */
2713         ixgbe_disable_intr(hw);
2714
2715         /* reset the NIC */
2716         ixgbe_pf_reset_hw(hw);
2717         hw->adapter_stopped = 0;
2718
2719         /* stop adapter */
2720         ixgbe_stop_adapter(hw);
2721
2722         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2723                 vfinfo[vf].clear_to_send = false;
2724
2725         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2726                 /* Turn off the copper */
2727                 ixgbe_set_phy_power(hw, false);
2728         } else {
2729                 /* Turn off the laser */
2730                 ixgbe_disable_tx_laser(hw);
2731         }
2732
2733         ixgbe_dev_clear_queues(dev);
2734
2735         /* Clear stored conf */
2736         dev->data->scattered_rx = 0;
2737         dev->data->lro = 0;
2738
2739         /* Clear recorded link status */
2740         memset(&link, 0, sizeof(link));
2741         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2742
2743         if (!rte_intr_allow_others(intr_handle))
2744                 /* resume to the default handler */
2745                 rte_intr_callback_register(intr_handle,
2746                                            ixgbe_dev_interrupt_handler,
2747                                            (void *)dev);
2748
2749         /* Clean datapath event and queue/vec mapping */
2750         rte_intr_efd_disable(intr_handle);
2751         if (intr_handle->intr_vec != NULL) {
2752                 rte_free(intr_handle->intr_vec);
2753                 intr_handle->intr_vec = NULL;
2754         }
2755 }
2756
2757 /*
2758  * Set device link up: enable tx.
2759  */
2760 static int
2761 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2762 {
2763         struct ixgbe_hw *hw =
2764                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2765         if (hw->mac.type == ixgbe_mac_82599EB) {
2766 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2767                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2768                         /* Not suported in bypass mode */
2769                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2770                                      "by device id 0x%x", hw->device_id);
2771                         return -ENOTSUP;
2772                 }
2773 #endif
2774         }
2775
2776         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2777                 /* Turn on the copper */
2778                 ixgbe_set_phy_power(hw, true);
2779         } else {
2780                 /* Turn on the laser */
2781                 ixgbe_enable_tx_laser(hw);
2782         }
2783
2784         return 0;
2785 }
2786
2787 /*
2788  * Set device link down: disable tx.
2789  */
2790 static int
2791 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2792 {
2793         struct ixgbe_hw *hw =
2794                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795         if (hw->mac.type == ixgbe_mac_82599EB) {
2796 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2797                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2798                         /* Not suported in bypass mode */
2799                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2800                                      "by device id 0x%x", hw->device_id);
2801                         return -ENOTSUP;
2802                 }
2803 #endif
2804         }
2805
2806         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2807                 /* Turn off the copper */
2808                 ixgbe_set_phy_power(hw, false);
2809         } else {
2810                 /* Turn off the laser */
2811                 ixgbe_disable_tx_laser(hw);
2812         }
2813
2814         return 0;
2815 }
2816
2817 /*
2818  * Reest and stop device.
2819  */
2820 static void
2821 ixgbe_dev_close(struct rte_eth_dev *dev)
2822 {
2823         struct ixgbe_hw *hw =
2824                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2825
2826         PMD_INIT_FUNC_TRACE();
2827
2828         ixgbe_pf_reset_hw(hw);
2829
2830         ixgbe_dev_stop(dev);
2831         hw->adapter_stopped = 1;
2832
2833         ixgbe_dev_free_queues(dev);
2834
2835         ixgbe_disable_pcie_master(hw);
2836
2837         /* reprogram the RAR[0] in case user changed it. */
2838         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2839 }
2840
2841 static void
2842 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2843                            struct ixgbe_hw_stats *hw_stats,
2844                            struct ixgbe_macsec_stats *macsec_stats,
2845                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2846                            uint64_t *total_qprc, uint64_t *total_qprdc)
2847 {
2848         uint32_t bprc, lxon, lxoff, total;
2849         uint32_t delta_gprc = 0;
2850         unsigned i;
2851         /* Workaround for RX byte count not including CRC bytes when CRC
2852          * strip is enabled. CRC bytes are removed from counters when crc_strip
2853          * is disabled.
2854          */
2855         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2856                         IXGBE_HLREG0_RXCRCSTRP);
2857
2858         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2859         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2860         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2861         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2862
2863         for (i = 0; i < 8; i++) {
2864                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2865
2866                 /* global total per queue */
2867                 hw_stats->mpc[i] += mp;
2868                 /* Running comprehensive total for stats display */
2869                 *total_missed_rx += hw_stats->mpc[i];
2870                 if (hw->mac.type == ixgbe_mac_82598EB) {
2871                         hw_stats->rnbc[i] +=
2872                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2873                         hw_stats->pxonrxc[i] +=
2874                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2875                         hw_stats->pxoffrxc[i] +=
2876                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2877                 } else {
2878                         hw_stats->pxonrxc[i] +=
2879                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2880                         hw_stats->pxoffrxc[i] +=
2881                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2882                         hw_stats->pxon2offc[i] +=
2883                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2884                 }
2885                 hw_stats->pxontxc[i] +=
2886                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2887                 hw_stats->pxofftxc[i] +=
2888                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2889         }
2890         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2891                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2892                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2893                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2894
2895                 delta_gprc += delta_qprc;
2896
2897                 hw_stats->qprc[i] += delta_qprc;
2898                 hw_stats->qptc[i] += delta_qptc;
2899
2900                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2901                 hw_stats->qbrc[i] +=
2902                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2903                 if (crc_strip == 0)
2904                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2905
2906                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2907                 hw_stats->qbtc[i] +=
2908                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2909
2910                 hw_stats->qprdc[i] += delta_qprdc;
2911                 *total_qprdc += hw_stats->qprdc[i];
2912
2913                 *total_qprc += hw_stats->qprc[i];
2914                 *total_qbrc += hw_stats->qbrc[i];
2915         }
2916         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2917         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2918         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2919
2920         /*
2921          * An errata states that gprc actually counts good + missed packets:
2922          * Workaround to set gprc to summated queue packet receives
2923          */
2924         hw_stats->gprc = *total_qprc;
2925
2926         if (hw->mac.type != ixgbe_mac_82598EB) {
2927                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2928                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2929                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2930                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2931                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2932                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2933                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2934                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2935         } else {
2936                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2937                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2938                 /* 82598 only has a counter in the high register */
2939                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2940                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2941                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2942         }
2943         uint64_t old_tpr = hw_stats->tpr;
2944
2945         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2946         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2947
2948         if (crc_strip == 0)
2949                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2950
2951         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2952         hw_stats->gptc += delta_gptc;
2953         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2954         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2955
2956         /*
2957          * Workaround: mprc hardware is incorrectly counting
2958          * broadcasts, so for now we subtract those.
2959          */
2960         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2961         hw_stats->bprc += bprc;
2962         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2963         if (hw->mac.type == ixgbe_mac_82598EB)
2964                 hw_stats->mprc -= bprc;
2965
2966         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2967         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2968         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2969         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2970         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2971         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2972
2973         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2974         hw_stats->lxontxc += lxon;
2975         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2976         hw_stats->lxofftxc += lxoff;
2977         total = lxon + lxoff;
2978
2979         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2980         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2981         hw_stats->gptc -= total;
2982         hw_stats->mptc -= total;
2983         hw_stats->ptc64 -= total;
2984         hw_stats->gotc -= total * ETHER_MIN_LEN;
2985
2986         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2987         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2988         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2989         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2990         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2991         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2992         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2993         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2994         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2995         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2996         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2997         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2998         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2999         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3000         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3001         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3002         /* Only read FCOE on 82599 */
3003         if (hw->mac.type != ixgbe_mac_82598EB) {
3004                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3005                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3006                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3007                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3008                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3009         }
3010
3011         /* Flow Director Stats registers */
3012         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3013         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3014
3015         /* MACsec Stats registers */
3016         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3017         macsec_stats->out_pkts_encrypted +=
3018                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3019         macsec_stats->out_pkts_protected +=
3020                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3021         macsec_stats->out_octets_encrypted +=
3022                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3023         macsec_stats->out_octets_protected +=
3024                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3025         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3026         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3027         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3028         macsec_stats->in_pkts_unknownsci +=
3029                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3030         macsec_stats->in_octets_decrypted +=
3031                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3032         macsec_stats->in_octets_validated +=
3033                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3034         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3035         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3036         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3037         for (i = 0; i < 2; i++) {
3038                 macsec_stats->in_pkts_ok +=
3039                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3040                 macsec_stats->in_pkts_invalid +=
3041                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3042                 macsec_stats->in_pkts_notvalid +=
3043                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3044         }
3045         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3046         macsec_stats->in_pkts_notusingsa +=
3047                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3048 }
3049
3050 /*
3051  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3052  */
3053 static void
3054 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3055 {
3056         struct ixgbe_hw *hw =
3057                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3058         struct ixgbe_hw_stats *hw_stats =
3059                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3060         struct ixgbe_macsec_stats *macsec_stats =
3061                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3062                                 dev->data->dev_private);
3063         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3064         unsigned i;
3065
3066         total_missed_rx = 0;
3067         total_qbrc = 0;
3068         total_qprc = 0;
3069         total_qprdc = 0;
3070
3071         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3072                         &total_qbrc, &total_qprc, &total_qprdc);
3073
3074         if (stats == NULL)
3075                 return;
3076
3077         /* Fill out the rte_eth_stats statistics structure */
3078         stats->ipackets = total_qprc;
3079         stats->ibytes = total_qbrc;
3080         stats->opackets = hw_stats->gptc;
3081         stats->obytes = hw_stats->gotc;
3082
3083         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3084                 stats->q_ipackets[i] = hw_stats->qprc[i];
3085                 stats->q_opackets[i] = hw_stats->qptc[i];
3086                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3087                 stats->q_obytes[i] = hw_stats->qbtc[i];
3088                 stats->q_errors[i] = hw_stats->qprdc[i];
3089         }
3090
3091         /* Rx Errors */
3092         stats->imissed  = total_missed_rx;
3093         stats->ierrors  = hw_stats->crcerrs +
3094                           hw_stats->mspdc +
3095                           hw_stats->rlec +
3096                           hw_stats->ruc +
3097                           hw_stats->roc +
3098                           hw_stats->illerrc +
3099                           hw_stats->errbc +
3100                           hw_stats->rfc +
3101                           hw_stats->fccrc +
3102                           hw_stats->fclast;
3103
3104         /* Tx Errors */
3105         stats->oerrors  = 0;
3106 }
3107
3108 static void
3109 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3110 {
3111         struct ixgbe_hw_stats *stats =
3112                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3113
3114         /* HW registers are cleared on read */
3115         ixgbe_dev_stats_get(dev, NULL);
3116
3117         /* Reset software totals */
3118         memset(stats, 0, sizeof(*stats));
3119 }
3120
3121 /* This function calculates the number of xstats based on the current config */
3122 static unsigned
3123 ixgbe_xstats_calc_num(void) {
3124         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3125                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3126                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3127 }
3128
3129 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3130         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3131 {
3132         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3133         unsigned stat, i, count;
3134
3135         if (xstats_names != NULL) {
3136                 count = 0;
3137
3138                 /* Note: limit >= cnt_stats checked upstream
3139                  * in rte_eth_xstats_names()
3140                  */
3141
3142                 /* Extended stats from ixgbe_hw_stats */
3143                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3144                         snprintf(xstats_names[count].name,
3145                                 sizeof(xstats_names[count].name),
3146                                 "%s",
3147                                 rte_ixgbe_stats_strings[i].name);
3148                         count++;
3149                 }
3150
3151                 /* MACsec Stats */
3152                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3153                         snprintf(xstats_names[count].name,
3154                                 sizeof(xstats_names[count].name),
3155                                 "%s",
3156                                 rte_ixgbe_macsec_strings[i].name);
3157                         count++;
3158                 }
3159
3160                 /* RX Priority Stats */
3161                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3162                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3163                                 snprintf(xstats_names[count].name,
3164                                         sizeof(xstats_names[count].name),
3165                                         "rx_priority%u_%s", i,
3166                                         rte_ixgbe_rxq_strings[stat].name);
3167                                 count++;
3168                         }
3169                 }
3170
3171                 /* TX Priority Stats */
3172                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3173                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3174                                 snprintf(xstats_names[count].name,
3175                                         sizeof(xstats_names[count].name),
3176                                         "tx_priority%u_%s", i,
3177                                         rte_ixgbe_txq_strings[stat].name);
3178                                 count++;
3179                         }
3180                 }
3181         }
3182         return cnt_stats;
3183 }
3184
3185 static int ixgbe_dev_xstats_get_names_by_id(
3186         struct rte_eth_dev *dev,
3187         struct rte_eth_xstat_name *xstats_names,
3188         const uint64_t *ids,
3189         unsigned int limit)
3190 {
3191         if (!ids) {
3192                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3193                 unsigned int stat, i, count;
3194
3195                 if (xstats_names != NULL) {
3196                         count = 0;
3197
3198                         /* Note: limit >= cnt_stats checked upstream
3199                          * in rte_eth_xstats_names()
3200                          */
3201
3202                         /* Extended stats from ixgbe_hw_stats */
3203                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3204                                 snprintf(xstats_names[count].name,
3205                                         sizeof(xstats_names[count].name),
3206                                         "%s",
3207                                         rte_ixgbe_stats_strings[i].name);
3208                                 count++;
3209                         }
3210
3211                         /* MACsec Stats */
3212                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3213                                 snprintf(xstats_names[count].name,
3214                                         sizeof(xstats_names[count].name),
3215                                         "%s",
3216                                         rte_ixgbe_macsec_strings[i].name);
3217                                 count++;
3218                         }
3219
3220                         /* RX Priority Stats */
3221                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3222                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3223                                         snprintf(xstats_names[count].name,
3224                                             sizeof(xstats_names[count].name),
3225                                             "rx_priority%u_%s", i,
3226                                             rte_ixgbe_rxq_strings[stat].name);
3227                                         count++;
3228                                 }
3229                         }
3230
3231                         /* TX Priority Stats */
3232                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3233                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3234                                         snprintf(xstats_names[count].name,
3235                                             sizeof(xstats_names[count].name),
3236                                             "tx_priority%u_%s", i,
3237                                             rte_ixgbe_txq_strings[stat].name);
3238                                         count++;
3239                                 }
3240                         }
3241                 }
3242                 return cnt_stats;
3243         }
3244
3245         uint16_t i;
3246         uint16_t size = ixgbe_xstats_calc_num();
3247         struct rte_eth_xstat_name xstats_names_copy[size];
3248
3249         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3250                         size);
3251
3252         for (i = 0; i < limit; i++) {
3253                 if (ids[i] >= size) {
3254                         PMD_INIT_LOG(ERR, "id value isn't valid");
3255                         return -1;
3256                 }
3257                 strcpy(xstats_names[i].name,
3258                                 xstats_names_copy[ids[i]].name);
3259         }
3260         return limit;
3261 }
3262
3263 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3264         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3265 {
3266         unsigned i;
3267
3268         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3269                 return -ENOMEM;
3270
3271         if (xstats_names != NULL)
3272                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3273                         snprintf(xstats_names[i].name,
3274                                 sizeof(xstats_names[i].name),
3275                                 "%s", rte_ixgbevf_stats_strings[i].name);
3276         return IXGBEVF_NB_XSTATS;
3277 }
3278
3279 static int
3280 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3281                                          unsigned n)
3282 {
3283         struct ixgbe_hw *hw =
3284                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3285         struct ixgbe_hw_stats *hw_stats =
3286                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3287         struct ixgbe_macsec_stats *macsec_stats =
3288                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3289                                 dev->data->dev_private);
3290         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3291         unsigned i, stat, count = 0;
3292
3293         count = ixgbe_xstats_calc_num();
3294
3295         if (n < count)
3296                 return count;
3297
3298         total_missed_rx = 0;
3299         total_qbrc = 0;
3300         total_qprc = 0;
3301         total_qprdc = 0;
3302
3303         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3304                         &total_qbrc, &total_qprc, &total_qprdc);
3305
3306         /* If this is a reset xstats is NULL, and we have cleared the
3307          * registers by reading them.
3308          */
3309         if (!xstats)
3310                 return 0;
3311
3312         /* Extended stats from ixgbe_hw_stats */
3313         count = 0;
3314         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3315                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3316                                 rte_ixgbe_stats_strings[i].offset);
3317                 xstats[count].id = count;
3318                 count++;
3319         }
3320
3321         /* MACsec Stats */
3322         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3323                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3324                                 rte_ixgbe_macsec_strings[i].offset);
3325                 xstats[count].id = count;
3326                 count++;
3327         }
3328
3329         /* RX Priority Stats */
3330         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3331                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3332                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3333                                         rte_ixgbe_rxq_strings[stat].offset +
3334                                         (sizeof(uint64_t) * i));
3335                         xstats[count].id = count;
3336                         count++;
3337                 }
3338         }
3339
3340         /* TX Priority Stats */
3341         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3342                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3343                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3344                                         rte_ixgbe_txq_strings[stat].offset +
3345                                         (sizeof(uint64_t) * i));
3346                         xstats[count].id = count;
3347                         count++;
3348                 }
3349         }
3350         return count;
3351 }
3352
3353 static int
3354 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3355                 uint64_t *values, unsigned int n)
3356 {
3357         if (!ids) {
3358                 struct ixgbe_hw *hw =
3359                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360                 struct ixgbe_hw_stats *hw_stats =
3361                                 IXGBE_DEV_PRIVATE_TO_STATS(
3362                                                 dev->data->dev_private);
3363                 struct ixgbe_macsec_stats *macsec_stats =
3364                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3365                                         dev->data->dev_private);
3366                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3367                 unsigned int i, stat, count = 0;
3368
3369                 count = ixgbe_xstats_calc_num();
3370
3371                 if (!ids && n < count)
3372                         return count;
3373
3374                 total_missed_rx = 0;
3375                 total_qbrc = 0;
3376                 total_qprc = 0;
3377                 total_qprdc = 0;
3378
3379                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3380                                 &total_missed_rx, &total_qbrc, &total_qprc,
3381                                 &total_qprdc);
3382
3383                 /* If this is a reset xstats is NULL, and we have cleared the
3384                  * registers by reading them.
3385                  */
3386                 if (!ids && !values)
3387                         return 0;
3388
3389                 /* Extended stats from ixgbe_hw_stats */
3390                 count = 0;
3391                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3392                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3393                                         rte_ixgbe_stats_strings[i].offset);
3394                         count++;
3395                 }
3396
3397                 /* MACsec Stats */
3398                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3399                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3400                                         rte_ixgbe_macsec_strings[i].offset);
3401                         count++;
3402                 }
3403
3404                 /* RX Priority Stats */
3405                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3406                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3407                                 values[count] =
3408                                         *(uint64_t *)(((char *)hw_stats) +
3409                                         rte_ixgbe_rxq_strings[stat].offset +
3410                                         (sizeof(uint64_t) * i));
3411                                 count++;
3412                         }
3413                 }
3414
3415                 /* TX Priority Stats */
3416                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3417                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3418                                 values[count] =
3419                                         *(uint64_t *)(((char *)hw_stats) +
3420                                         rte_ixgbe_txq_strings[stat].offset +
3421                                         (sizeof(uint64_t) * i));
3422                                 count++;
3423                         }
3424                 }
3425                 return count;
3426         }
3427
3428         uint16_t i;
3429         uint16_t size = ixgbe_xstats_calc_num();
3430         uint64_t values_copy[size];
3431
3432         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3433
3434         for (i = 0; i < n; i++) {
3435                 if (ids[i] >= size) {
3436                         PMD_INIT_LOG(ERR, "id value isn't valid");
3437                         return -1;
3438                 }
3439                 values[i] = values_copy[ids[i]];
3440         }
3441         return n;
3442 }
3443
3444 static void
3445 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3446 {
3447         struct ixgbe_hw_stats *stats =
3448                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3449         struct ixgbe_macsec_stats *macsec_stats =
3450                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3451                                 dev->data->dev_private);
3452
3453         unsigned count = ixgbe_xstats_calc_num();
3454
3455         /* HW registers are cleared on read */
3456         ixgbe_dev_xstats_get(dev, NULL, count);
3457
3458         /* Reset software totals */
3459         memset(stats, 0, sizeof(*stats));
3460         memset(macsec_stats, 0, sizeof(*macsec_stats));
3461 }
3462
3463 static void
3464 ixgbevf_update_stats(struct rte_eth_dev *dev)
3465 {
3466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3467         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3468                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3469
3470         /* Good Rx packet, include VF loopback */
3471         UPDATE_VF_STAT(IXGBE_VFGPRC,
3472             hw_stats->last_vfgprc, hw_stats->vfgprc);
3473
3474         /* Good Rx octets, include VF loopback */
3475         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3476             hw_stats->last_vfgorc, hw_stats->vfgorc);
3477
3478         /* Good Tx packet, include VF loopback */
3479         UPDATE_VF_STAT(IXGBE_VFGPTC,
3480             hw_stats->last_vfgptc, hw_stats->vfgptc);
3481
3482         /* Good Tx octets, include VF loopback */
3483         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3484             hw_stats->last_vfgotc, hw_stats->vfgotc);
3485
3486         /* Rx Multicst Packet */
3487         UPDATE_VF_STAT(IXGBE_VFMPRC,
3488             hw_stats->last_vfmprc, hw_stats->vfmprc);
3489 }
3490
3491 static int
3492 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3493                        unsigned n)
3494 {
3495         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3496                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3497         unsigned i;
3498
3499         if (n < IXGBEVF_NB_XSTATS)
3500                 return IXGBEVF_NB_XSTATS;
3501
3502         ixgbevf_update_stats(dev);
3503
3504         if (!xstats)
3505                 return 0;
3506
3507         /* Extended stats */
3508         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3509                 xstats[i].id = i;
3510                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3511                         rte_ixgbevf_stats_strings[i].offset);
3512         }
3513
3514         return IXGBEVF_NB_XSTATS;
3515 }
3516
3517 static void
3518 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3519 {
3520         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3521                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3522
3523         ixgbevf_update_stats(dev);
3524
3525         if (stats == NULL)
3526                 return;
3527
3528         stats->ipackets = hw_stats->vfgprc;
3529         stats->ibytes = hw_stats->vfgorc;
3530         stats->opackets = hw_stats->vfgptc;
3531         stats->obytes = hw_stats->vfgotc;
3532 }
3533
3534 static void
3535 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3536 {
3537         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3538                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3539
3540         /* Sync HW register to the last stats */
3541         ixgbevf_dev_stats_get(dev, NULL);
3542
3543         /* reset HW current stats*/
3544         hw_stats->vfgprc = 0;
3545         hw_stats->vfgorc = 0;
3546         hw_stats->vfgptc = 0;
3547         hw_stats->vfgotc = 0;
3548 }
3549
3550 static int
3551 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3552 {
3553         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3554         u16 eeprom_verh, eeprom_verl;
3555         u32 etrack_id;
3556         int ret;
3557
3558         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3559         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3560
3561         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3562         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3563
3564         ret += 1; /* add the size of '\0' */
3565         if (fw_size < (u32)ret)
3566                 return ret;
3567         else
3568                 return 0;
3569 }
3570
3571 static void
3572 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3573 {
3574         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3575         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3576         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3577
3578         dev_info->pci_dev = pci_dev;
3579         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3580         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3581         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3582                 /*
3583                  * When DCB/VT is off, maximum number of queues changes,
3584                  * except for 82598EB, which remains constant.
3585                  */
3586                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3587                                 hw->mac.type != ixgbe_mac_82598EB)
3588                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3589         }
3590         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3591         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3592         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3593         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3594         dev_info->max_vfs = pci_dev->max_vfs;
3595         if (hw->mac.type == ixgbe_mac_82598EB)
3596                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3597         else
3598                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3599         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3600         dev_info->rx_offload_capa =
3601                 DEV_RX_OFFLOAD_VLAN_STRIP |
3602                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3603                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3604                 DEV_RX_OFFLOAD_TCP_CKSUM;
3605
3606         /*
3607          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3608          * mode.
3609          */
3610         if ((hw->mac.type == ixgbe_mac_82599EB ||
3611              hw->mac.type == ixgbe_mac_X540) &&
3612             !RTE_ETH_DEV_SRIOV(dev).active)
3613                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3614
3615         if (hw->mac.type == ixgbe_mac_82599EB ||
3616             hw->mac.type == ixgbe_mac_X540)
3617                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3618
3619         if (hw->mac.type == ixgbe_mac_X550 ||
3620             hw->mac.type == ixgbe_mac_X550EM_x ||
3621             hw->mac.type == ixgbe_mac_X550EM_a)
3622                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3623
3624         dev_info->tx_offload_capa =
3625                 DEV_TX_OFFLOAD_VLAN_INSERT |
3626                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3627                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3628                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3629                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3630                 DEV_TX_OFFLOAD_TCP_TSO;
3631
3632         if (hw->mac.type == ixgbe_mac_82599EB ||
3633             hw->mac.type == ixgbe_mac_X540)
3634                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3635
3636         if (hw->mac.type == ixgbe_mac_X550 ||
3637             hw->mac.type == ixgbe_mac_X550EM_x ||
3638             hw->mac.type == ixgbe_mac_X550EM_a)
3639                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3640
3641         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3642                 .rx_thresh = {
3643                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3644                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3645                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3646                 },
3647                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3648                 .rx_drop_en = 0,
3649         };
3650
3651         dev_info->default_txconf = (struct rte_eth_txconf) {
3652                 .tx_thresh = {
3653                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3654                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3655                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3656                 },
3657                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3658                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3659                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3660                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3661         };
3662
3663         dev_info->rx_desc_lim = rx_desc_lim;
3664         dev_info->tx_desc_lim = tx_desc_lim;
3665
3666         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3667         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3668         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3669
3670         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3671         if (hw->mac.type == ixgbe_mac_X540 ||
3672             hw->mac.type == ixgbe_mac_X540_vf ||
3673             hw->mac.type == ixgbe_mac_X550 ||
3674             hw->mac.type == ixgbe_mac_X550_vf) {
3675                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3676         }
3677 }
3678
3679 static const uint32_t *
3680 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3681 {
3682         static const uint32_t ptypes[] = {
3683                 /* For non-vec functions,
3684                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3685                  * for vec functions,
3686                  * refers to _recv_raw_pkts_vec().
3687                  */
3688                 RTE_PTYPE_L2_ETHER,
3689                 RTE_PTYPE_L3_IPV4,
3690                 RTE_PTYPE_L3_IPV4_EXT,
3691                 RTE_PTYPE_L3_IPV6,
3692                 RTE_PTYPE_L3_IPV6_EXT,
3693                 RTE_PTYPE_L4_SCTP,
3694                 RTE_PTYPE_L4_TCP,
3695                 RTE_PTYPE_L4_UDP,
3696                 RTE_PTYPE_TUNNEL_IP,
3697                 RTE_PTYPE_INNER_L3_IPV6,
3698                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3699                 RTE_PTYPE_INNER_L4_TCP,
3700                 RTE_PTYPE_INNER_L4_UDP,
3701                 RTE_PTYPE_UNKNOWN
3702         };
3703
3704         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3705             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3706             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3707             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3708                 return ptypes;
3709         return NULL;
3710 }
3711
3712 static void
3713 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3714                      struct rte_eth_dev_info *dev_info)
3715 {
3716         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3718
3719         dev_info->pci_dev = pci_dev;
3720         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3721         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3722         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3723         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3724         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3725         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3726         dev_info->max_vfs = pci_dev->max_vfs;
3727         if (hw->mac.type == ixgbe_mac_82598EB)
3728                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3729         else
3730                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3731         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3732                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3733                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3734                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3735         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3736                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3737                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3738                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3739                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3740                                 DEV_TX_OFFLOAD_TCP_TSO;
3741
3742         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3743                 .rx_thresh = {
3744                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3745                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3746                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3747                 },
3748                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3749                 .rx_drop_en = 0,
3750         };
3751
3752         dev_info->default_txconf = (struct rte_eth_txconf) {
3753                 .tx_thresh = {
3754                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3755                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3756                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3757                 },
3758                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3759                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3760                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3761                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3762         };
3763
3764         dev_info->rx_desc_lim = rx_desc_lim;
3765         dev_info->tx_desc_lim = tx_desc_lim;
3766 }
3767
3768 /* return 0 means link status changed, -1 means not changed */
3769 static int
3770 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3771 {
3772         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3773         struct rte_eth_link link, old;
3774         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3775         struct ixgbe_interrupt *intr =
3776                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3777         int link_up;
3778         int diag;
3779         u32 speed = 0;
3780         bool autoneg = false;
3781
3782         link.link_status = ETH_LINK_DOWN;
3783         link.link_speed = 0;
3784         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3785         memset(&old, 0, sizeof(old));
3786         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3787
3788         hw->mac.get_link_status = true;
3789
3790         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3791                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3792                 speed = hw->phy.autoneg_advertised;
3793                 if (!speed)
3794                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3795                 ixgbe_setup_link(hw, speed, true);
3796         }
3797
3798         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3799         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3800                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3801         else
3802                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3803
3804         if (diag != 0) {
3805                 link.link_speed = ETH_SPEED_NUM_100M;
3806                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3807                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3808                 if (link.link_status == old.link_status)
3809                         return -1;
3810                 return 0;
3811         }
3812
3813         if (link_up == 0) {
3814                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3815                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3816                 if (link.link_status == old.link_status)
3817                         return -1;
3818                 return 0;
3819         }
3820         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3821         link.link_status = ETH_LINK_UP;
3822         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3823
3824         switch (link_speed) {
3825         default:
3826         case IXGBE_LINK_SPEED_UNKNOWN:
3827                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3828                 link.link_speed = ETH_SPEED_NUM_100M;
3829                 break;
3830
3831         case IXGBE_LINK_SPEED_100_FULL:
3832                 link.link_speed = ETH_SPEED_NUM_100M;
3833                 break;
3834
3835         case IXGBE_LINK_SPEED_1GB_FULL:
3836                 link.link_speed = ETH_SPEED_NUM_1G;
3837                 break;
3838
3839         case IXGBE_LINK_SPEED_10GB_FULL:
3840                 link.link_speed = ETH_SPEED_NUM_10G;
3841                 break;
3842         }
3843         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3844
3845         if (link.link_status == old.link_status)
3846                 return -1;
3847
3848         return 0;
3849 }
3850
3851 static void
3852 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3853 {
3854         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3855         uint32_t fctrl;
3856
3857         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3858         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3859         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3860 }
3861
3862 static void
3863 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3864 {
3865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3866         uint32_t fctrl;
3867
3868         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3869         fctrl &= (~IXGBE_FCTRL_UPE);
3870         if (dev->data->all_multicast == 1)
3871                 fctrl |= IXGBE_FCTRL_MPE;
3872         else
3873                 fctrl &= (~IXGBE_FCTRL_MPE);
3874         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3875 }
3876
3877 static void
3878 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3879 {
3880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3881         uint32_t fctrl;
3882
3883         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3884         fctrl |= IXGBE_FCTRL_MPE;
3885         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3886 }
3887
3888 static void
3889 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3890 {
3891         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3892         uint32_t fctrl;
3893
3894         if (dev->data->promiscuous == 1)
3895                 return; /* must remain in all_multicast mode */
3896
3897         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3898         fctrl &= (~IXGBE_FCTRL_MPE);
3899         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3900 }
3901
3902 /**
3903  * It clears the interrupt causes and enables the interrupt.
3904  * It will be called once only during nic initialized.
3905  *
3906  * @param dev
3907  *  Pointer to struct rte_eth_dev.
3908  *
3909  * @return
3910  *  - On success, zero.
3911  *  - On failure, a negative value.
3912  */
3913 static int
3914 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3915 {
3916         struct ixgbe_interrupt *intr =
3917                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3918
3919         ixgbe_dev_link_status_print(dev);
3920         intr->mask |= IXGBE_EICR_LSC;
3921
3922         return 0;
3923 }
3924
3925 /**
3926  * It clears the interrupt causes and enables the interrupt.
3927  * It will be called once only during nic initialized.
3928  *
3929  * @param dev
3930  *  Pointer to struct rte_eth_dev.
3931  *
3932  * @return
3933  *  - On success, zero.
3934  *  - On failure, a negative value.
3935  */
3936 static int
3937 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3938 {
3939         struct ixgbe_interrupt *intr =
3940                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3941
3942         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3943
3944         return 0;
3945 }
3946
3947 /**
3948  * It clears the interrupt causes and enables the interrupt.
3949  * It will be called once only during nic initialized.
3950  *
3951  * @param dev
3952  *  Pointer to struct rte_eth_dev.
3953  *
3954  * @return
3955  *  - On success, zero.
3956  *  - On failure, a negative value.
3957  */
3958 static int
3959 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3960 {
3961         struct ixgbe_interrupt *intr =
3962                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3963
3964         intr->mask |= IXGBE_EICR_LINKSEC;
3965
3966         return 0;
3967 }
3968
3969 /*
3970  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3971  *
3972  * @param dev
3973  *  Pointer to struct rte_eth_dev.
3974  *
3975  * @return
3976  *  - On success, zero.
3977  *  - On failure, a negative value.
3978  */
3979 static int
3980 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3981 {
3982         uint32_t eicr;
3983         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3984         struct ixgbe_interrupt *intr =
3985                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3986
3987         /* clear all cause mask */
3988         ixgbe_disable_intr(hw);
3989
3990         /* read-on-clear nic registers here */
3991         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3992         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3993
3994         intr->flags = 0;
3995
3996         /* set flag for async link update */
3997         if (eicr & IXGBE_EICR_LSC)
3998                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3999
4000         if (eicr & IXGBE_EICR_MAILBOX)
4001                 intr->flags |= IXGBE_FLAG_MAILBOX;
4002
4003         if (eicr & IXGBE_EICR_LINKSEC)
4004                 intr->flags |= IXGBE_FLAG_MACSEC;
4005
4006         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4007             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4008             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4009                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4010
4011         return 0;
4012 }
4013
4014 /**
4015  * It gets and then prints the link status.
4016  *
4017  * @param dev
4018  *  Pointer to struct rte_eth_dev.
4019  *
4020  * @return
4021  *  - On success, zero.
4022  *  - On failure, a negative value.
4023  */
4024 static void
4025 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4026 {
4027         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4028         struct rte_eth_link link;
4029
4030         memset(&link, 0, sizeof(link));
4031         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4032         if (link.link_status) {
4033                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4034                                         (int)(dev->data->port_id),
4035                                         (unsigned)link.link_speed,
4036                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4037                                         "full-duplex" : "half-duplex");
4038         } else {
4039                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4040                                 (int)(dev->data->port_id));
4041         }
4042         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4043                                 pci_dev->addr.domain,
4044                                 pci_dev->addr.bus,
4045                                 pci_dev->addr.devid,
4046                                 pci_dev->addr.function);
4047 }
4048
4049 /*
4050  * It executes link_update after knowing an interrupt occurred.
4051  *
4052  * @param dev
4053  *  Pointer to struct rte_eth_dev.
4054  *
4055  * @return
4056  *  - On success, zero.
4057  *  - On failure, a negative value.
4058  */
4059 static int
4060 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4061                            struct rte_intr_handle *intr_handle)
4062 {
4063         struct ixgbe_interrupt *intr =
4064                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4065         int64_t timeout;
4066         struct rte_eth_link link;
4067         struct ixgbe_hw *hw =
4068                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4069
4070         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4071
4072         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4073                 ixgbe_pf_mbx_process(dev);
4074                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4075         }
4076
4077         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4078                 ixgbe_handle_lasi(hw);
4079                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4080         }
4081
4082         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4083                 /* get the link status before link update, for predicting later */
4084                 memset(&link, 0, sizeof(link));
4085                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4086
4087                 ixgbe_dev_link_update(dev, 0);
4088
4089                 /* likely to up */
4090                 if (!link.link_status)
4091                         /* handle it 1 sec later, wait it being stable */
4092                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4093                 /* likely to down */
4094                 else
4095                         /* handle it 4 sec later, wait it being stable */
4096                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4097
4098                 ixgbe_dev_link_status_print(dev);
4099                 if (rte_eal_alarm_set(timeout * 1000,
4100                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4101                         PMD_DRV_LOG(ERR, "Error setting alarm");
4102                 else {
4103                         /* remember original mask */
4104                         intr->mask_original = intr->mask;
4105                         /* only disable lsc interrupt */
4106                         intr->mask &= ~IXGBE_EIMS_LSC;
4107                 }
4108         }
4109
4110         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4111         ixgbe_enable_intr(dev);
4112         rte_intr_enable(intr_handle);
4113
4114         return 0;
4115 }
4116
4117 /**
4118  * Interrupt handler which shall be registered for alarm callback for delayed
4119  * handling specific interrupt to wait for the stable nic state. As the
4120  * NIC interrupt state is not stable for ixgbe after link is just down,
4121  * it needs to wait 4 seconds to get the stable status.
4122  *
4123  * @param handle
4124  *  Pointer to interrupt handle.
4125  * @param param
4126  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4127  *
4128  * @return
4129  *  void
4130  */
4131 static void
4132 ixgbe_dev_interrupt_delayed_handler(void *param)
4133 {
4134         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4135         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4136         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4137         struct ixgbe_interrupt *intr =
4138                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4139         struct ixgbe_hw *hw =
4140                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4141         uint32_t eicr;
4142
4143         ixgbe_disable_intr(hw);
4144
4145         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4146         if (eicr & IXGBE_EICR_MAILBOX)
4147                 ixgbe_pf_mbx_process(dev);
4148
4149         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4150                 ixgbe_handle_lasi(hw);
4151                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4152         }
4153
4154         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4155                 ixgbe_dev_link_update(dev, 0);
4156                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4157                 ixgbe_dev_link_status_print(dev);
4158                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4159         }
4160
4161         if (intr->flags & IXGBE_FLAG_MACSEC) {
4162                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4163                                               NULL);
4164                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4165         }
4166
4167         /* restore original mask */
4168         intr->mask = intr->mask_original;
4169         intr->mask_original = 0;
4170
4171         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4172         ixgbe_enable_intr(dev);
4173         rte_intr_enable(intr_handle);
4174 }
4175
4176 /**
4177  * Interrupt handler triggered by NIC  for handling
4178  * specific interrupt.
4179  *
4180  * @param handle
4181  *  Pointer to interrupt handle.
4182  * @param param
4183  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4184  *
4185  * @return
4186  *  void
4187  */
4188 static void
4189 ixgbe_dev_interrupt_handler(void *param)
4190 {
4191         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4192
4193         ixgbe_dev_interrupt_get_status(dev);
4194         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4195 }
4196
4197 static int
4198 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4199 {
4200         struct ixgbe_hw *hw;
4201
4202         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4203         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4204 }
4205
4206 static int
4207 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4208 {
4209         struct ixgbe_hw *hw;
4210
4211         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4212         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4213 }
4214
4215 static int
4216 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4217 {
4218         struct ixgbe_hw *hw;
4219         uint32_t mflcn_reg;
4220         uint32_t fccfg_reg;
4221         int rx_pause;
4222         int tx_pause;
4223
4224         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4225
4226         fc_conf->pause_time = hw->fc.pause_time;
4227         fc_conf->high_water = hw->fc.high_water[0];
4228         fc_conf->low_water = hw->fc.low_water[0];
4229         fc_conf->send_xon = hw->fc.send_xon;
4230         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4231
4232         /*
4233          * Return rx_pause status according to actual setting of
4234          * MFLCN register.
4235          */
4236         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4237         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4238                 rx_pause = 1;
4239         else
4240                 rx_pause = 0;
4241
4242         /*
4243          * Return tx_pause status according to actual setting of
4244          * FCCFG register.
4245          */
4246         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4247         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4248                 tx_pause = 1;
4249         else
4250                 tx_pause = 0;
4251
4252         if (rx_pause && tx_pause)
4253                 fc_conf->mode = RTE_FC_FULL;
4254         else if (rx_pause)
4255                 fc_conf->mode = RTE_FC_RX_PAUSE;
4256         else if (tx_pause)
4257                 fc_conf->mode = RTE_FC_TX_PAUSE;
4258         else
4259                 fc_conf->mode = RTE_FC_NONE;
4260
4261         return 0;
4262 }
4263
4264 static int
4265 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4266 {
4267         struct ixgbe_hw *hw;
4268         int err;
4269         uint32_t rx_buf_size;
4270         uint32_t max_high_water;
4271         uint32_t mflcn;
4272         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4273                 ixgbe_fc_none,
4274                 ixgbe_fc_rx_pause,
4275                 ixgbe_fc_tx_pause,
4276                 ixgbe_fc_full
4277         };
4278
4279         PMD_INIT_FUNC_TRACE();
4280
4281         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4282         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4283         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4284
4285         /*
4286          * At least reserve one Ethernet frame for watermark
4287          * high_water/low_water in kilo bytes for ixgbe
4288          */
4289         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4290         if ((fc_conf->high_water > max_high_water) ||
4291                 (fc_conf->high_water < fc_conf->low_water)) {
4292                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4293                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4294                 return -EINVAL;
4295         }
4296
4297         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4298         hw->fc.pause_time     = fc_conf->pause_time;
4299         hw->fc.high_water[0]  = fc_conf->high_water;
4300         hw->fc.low_water[0]   = fc_conf->low_water;
4301         hw->fc.send_xon       = fc_conf->send_xon;
4302         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4303
4304         err = ixgbe_fc_enable(hw);
4305
4306         /* Not negotiated is not an error case */
4307         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4308
4309                 /* check if we want to forward MAC frames - driver doesn't have native
4310                  * capability to do that, so we'll write the registers ourselves */
4311
4312                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4313
4314                 /* set or clear MFLCN.PMCF bit depending on configuration */
4315                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4316                         mflcn |= IXGBE_MFLCN_PMCF;
4317                 else
4318                         mflcn &= ~IXGBE_MFLCN_PMCF;
4319
4320                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4321                 IXGBE_WRITE_FLUSH(hw);
4322
4323                 return 0;
4324         }
4325
4326         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4327         return -EIO;
4328 }
4329
4330 /**
4331  *  ixgbe_pfc_enable_generic - Enable flow control
4332  *  @hw: pointer to hardware structure
4333  *  @tc_num: traffic class number
4334  *  Enable flow control according to the current settings.
4335  */
4336 static int
4337 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4338 {
4339         int ret_val = 0;
4340         uint32_t mflcn_reg, fccfg_reg;
4341         uint32_t reg;
4342         uint32_t fcrtl, fcrth;
4343         uint8_t i;
4344         uint8_t nb_rx_en;
4345
4346         /* Validate the water mark configuration */
4347         if (!hw->fc.pause_time) {
4348                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4349                 goto out;
4350         }
4351
4352         /* Low water mark of zero causes XOFF floods */
4353         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4354                  /* High/Low water can not be 0 */
4355                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4356                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4357                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4358                         goto out;
4359                 }
4360
4361                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4362                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4363                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4364                         goto out;
4365                 }
4366         }
4367         /* Negotiate the fc mode to use */
4368         ixgbe_fc_autoneg(hw);
4369
4370         /* Disable any previous flow control settings */
4371         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4372         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4373
4374         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4375         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4376
4377         switch (hw->fc.current_mode) {
4378         case ixgbe_fc_none:
4379                 /*
4380                  * If the count of enabled RX Priority Flow control >1,
4381                  * and the TX pause can not be disabled
4382                  */
4383                 nb_rx_en = 0;
4384                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4385                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4386                         if (reg & IXGBE_FCRTH_FCEN)
4387                                 nb_rx_en++;
4388                 }
4389                 if (nb_rx_en > 1)
4390                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4391                 break;
4392         case ixgbe_fc_rx_pause:
4393                 /*
4394                  * Rx Flow control is enabled and Tx Flow control is
4395                  * disabled by software override. Since there really
4396                  * isn't a way to advertise that we are capable of RX
4397                  * Pause ONLY, we will advertise that we support both
4398                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4399                  * disable the adapter's ability to send PAUSE frames.
4400                  */
4401                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4402                 /*
4403                  * If the count of enabled RX Priority Flow control >1,
4404                  * and the TX pause can not be disabled
4405                  */
4406                 nb_rx_en = 0;
4407                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4408                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4409                         if (reg & IXGBE_FCRTH_FCEN)
4410                                 nb_rx_en++;
4411                 }
4412                 if (nb_rx_en > 1)
4413                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4414                 break;
4415         case ixgbe_fc_tx_pause:
4416                 /*
4417                  * Tx Flow control is enabled, and Rx Flow control is
4418                  * disabled by software override.
4419                  */
4420                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4421                 break;
4422         case ixgbe_fc_full:
4423                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4424                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4425                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4426                 break;
4427         default:
4428                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4429                 ret_val = IXGBE_ERR_CONFIG;
4430                 goto out;
4431         }
4432
4433         /* Set 802.3x based flow control settings. */
4434         mflcn_reg |= IXGBE_MFLCN_DPF;
4435         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4436         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4437
4438         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4439         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4440                 hw->fc.high_water[tc_num]) {
4441                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4442                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4443                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4444         } else {
4445                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4446                 /*
4447                  * In order to prevent Tx hangs when the internal Tx
4448                  * switch is enabled we must set the high water mark
4449                  * to the maximum FCRTH value.  This allows the Tx
4450                  * switch to function even under heavy Rx workloads.
4451                  */
4452                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4453         }
4454         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4455
4456         /* Configure pause time (2 TCs per register) */
4457         reg = hw->fc.pause_time * 0x00010001;
4458         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4459                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4460
4461         /* Configure flow control refresh threshold value */
4462         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4463
4464 out:
4465         return ret_val;
4466 }
4467
4468 static int
4469 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4470 {
4471         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4472         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4473
4474         if (hw->mac.type != ixgbe_mac_82598EB) {
4475                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4476         }
4477         return ret_val;
4478 }
4479
4480 static int
4481 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4482 {
4483         int err;
4484         uint32_t rx_buf_size;
4485         uint32_t max_high_water;
4486         uint8_t tc_num;
4487         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4488         struct ixgbe_hw *hw =
4489                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4490         struct ixgbe_dcb_config *dcb_config =
4491                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4492
4493         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4494                 ixgbe_fc_none,
4495                 ixgbe_fc_rx_pause,
4496                 ixgbe_fc_tx_pause,
4497                 ixgbe_fc_full
4498         };
4499
4500         PMD_INIT_FUNC_TRACE();
4501
4502         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4503         tc_num = map[pfc_conf->priority];
4504         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4505         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4506         /*
4507          * At least reserve one Ethernet frame for watermark
4508          * high_water/low_water in kilo bytes for ixgbe
4509          */
4510         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4511         if ((pfc_conf->fc.high_water > max_high_water) ||
4512             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4513                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4514                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4515                 return -EINVAL;
4516         }
4517
4518         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4519         hw->fc.pause_time = pfc_conf->fc.pause_time;
4520         hw->fc.send_xon = pfc_conf->fc.send_xon;
4521         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4522         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4523
4524         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4525
4526         /* Not negotiated is not an error case */
4527         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4528                 return 0;
4529
4530         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4531         return -EIO;
4532 }
4533
4534 static int
4535 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4536                           struct rte_eth_rss_reta_entry64 *reta_conf,
4537                           uint16_t reta_size)
4538 {
4539         uint16_t i, sp_reta_size;
4540         uint8_t j, mask;
4541         uint32_t reta, r;
4542         uint16_t idx, shift;
4543         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4544         uint32_t reta_reg;
4545
4546         PMD_INIT_FUNC_TRACE();
4547
4548         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4549                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4550                         "NIC.");
4551                 return -ENOTSUP;
4552         }
4553
4554         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4555         if (reta_size != sp_reta_size) {
4556                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4557                         "(%d) doesn't match the number hardware can supported "
4558                         "(%d)", reta_size, sp_reta_size);
4559                 return -EINVAL;
4560         }
4561
4562         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4563                 idx = i / RTE_RETA_GROUP_SIZE;
4564                 shift = i % RTE_RETA_GROUP_SIZE;
4565                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4566                                                 IXGBE_4_BIT_MASK);
4567                 if (!mask)
4568                         continue;
4569                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4570                 if (mask == IXGBE_4_BIT_MASK)
4571                         r = 0;
4572                 else
4573                         r = IXGBE_READ_REG(hw, reta_reg);
4574                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4575                         if (mask & (0x1 << j))
4576                                 reta |= reta_conf[idx].reta[shift + j] <<
4577                                                         (CHAR_BIT * j);
4578                         else
4579                                 reta |= r & (IXGBE_8_BIT_MASK <<
4580                                                 (CHAR_BIT * j));
4581                 }
4582                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4583         }
4584
4585         return 0;
4586 }
4587
4588 static int
4589 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4590                          struct rte_eth_rss_reta_entry64 *reta_conf,
4591                          uint16_t reta_size)
4592 {
4593         uint16_t i, sp_reta_size;
4594         uint8_t j, mask;
4595         uint32_t reta;
4596         uint16_t idx, shift;
4597         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4598         uint32_t reta_reg;
4599
4600         PMD_INIT_FUNC_TRACE();
4601         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4602         if (reta_size != sp_reta_size) {
4603                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4604                         "(%d) doesn't match the number hardware can supported "
4605                         "(%d)", reta_size, sp_reta_size);
4606                 return -EINVAL;
4607         }
4608
4609         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4610                 idx = i / RTE_RETA_GROUP_SIZE;
4611                 shift = i % RTE_RETA_GROUP_SIZE;
4612                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4613                                                 IXGBE_4_BIT_MASK);
4614                 if (!mask)
4615                         continue;
4616
4617                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4618                 reta = IXGBE_READ_REG(hw, reta_reg);
4619                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4620                         if (mask & (0x1 << j))
4621                                 reta_conf[idx].reta[shift + j] =
4622                                         ((reta >> (CHAR_BIT * j)) &
4623                                                 IXGBE_8_BIT_MASK);
4624                 }
4625         }
4626
4627         return 0;
4628 }
4629
4630 static int
4631 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4632                                 uint32_t index, uint32_t pool)
4633 {
4634         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4635         uint32_t enable_addr = 1;
4636
4637         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4638                              pool, enable_addr);
4639 }
4640
4641 static void
4642 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4643 {
4644         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4645
4646         ixgbe_clear_rar(hw, index);
4647 }
4648
4649 static void
4650 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4651 {
4652         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4653
4654         ixgbe_remove_rar(dev, 0);
4655
4656         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4657 }
4658
4659 static bool
4660 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4661 {
4662         if (strcmp(dev->device->driver->name, drv->driver.name))
4663                 return false;
4664
4665         return true;
4666 }
4667
4668 bool
4669 is_ixgbe_supported(struct rte_eth_dev *dev)
4670 {
4671         return is_device_supported(dev, &rte_ixgbe_pmd);
4672 }
4673
4674 static int
4675 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4676 {
4677         uint32_t hlreg0;
4678         uint32_t maxfrs;
4679         struct ixgbe_hw *hw;
4680         struct rte_eth_dev_info dev_info;
4681         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4682         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4683
4684         ixgbe_dev_info_get(dev, &dev_info);
4685
4686         /* check that mtu is within the allowed range */
4687         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4688                 return -EINVAL;
4689
4690         /* refuse mtu that requires the support of scattered packets when this
4691          * feature has not been enabled before.
4692          */
4693         if (!rx_conf->enable_scatter &&
4694             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4695              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4696                 return -EINVAL;
4697
4698         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4699         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4700
4701         /* switch to jumbo mode if needed */
4702         if (frame_size > ETHER_MAX_LEN) {
4703                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4704                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4705         } else {
4706                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4707                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4708         }
4709         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4710
4711         /* update max frame size */
4712         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4713
4714         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4715         maxfrs &= 0x0000FFFF;
4716         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4717         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4718
4719         return 0;
4720 }
4721
4722 /*
4723  * Virtual Function operations
4724  */
4725 static void
4726 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4727 {
4728         PMD_INIT_FUNC_TRACE();
4729
4730         /* Clear interrupt mask to stop from interrupts being generated */
4731         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4732
4733         IXGBE_WRITE_FLUSH(hw);
4734 }
4735
4736 static void
4737 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4738 {
4739         PMD_INIT_FUNC_TRACE();
4740
4741         /* VF enable interrupt autoclean */
4742         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4743         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4744         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4745
4746         IXGBE_WRITE_FLUSH(hw);
4747 }
4748
4749 static int
4750 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4751 {
4752         struct rte_eth_conf *conf = &dev->data->dev_conf;
4753         struct ixgbe_adapter *adapter =
4754                         (struct ixgbe_adapter *)dev->data->dev_private;
4755
4756         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4757                      dev->data->port_id);
4758
4759         /*
4760          * VF has no ability to enable/disable HW CRC
4761          * Keep the persistent behavior the same as Host PF
4762          */
4763 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4764         if (!conf->rxmode.hw_strip_crc) {
4765                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4766                 conf->rxmode.hw_strip_crc = 1;
4767         }
4768 #else
4769         if (conf->rxmode.hw_strip_crc) {
4770                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4771                 conf->rxmode.hw_strip_crc = 0;
4772         }
4773 #endif
4774
4775         /*
4776          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4777          * allocation or vector Rx preconditions we will reset it.
4778          */
4779         adapter->rx_bulk_alloc_allowed = true;
4780         adapter->rx_vec_allowed = true;
4781
4782         return 0;
4783 }
4784
4785 static int
4786 ixgbevf_dev_start(struct rte_eth_dev *dev)
4787 {
4788         struct ixgbe_hw *hw =
4789                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4790         uint32_t intr_vector = 0;
4791         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4792         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4793
4794         int err, mask = 0;
4795
4796         PMD_INIT_FUNC_TRACE();
4797
4798         hw->mac.ops.reset_hw(hw);
4799         hw->mac.get_link_status = true;
4800
4801         /* negotiate mailbox API version to use with the PF. */
4802         ixgbevf_negotiate_api(hw);
4803
4804         ixgbevf_dev_tx_init(dev);
4805
4806         /* This can fail when allocating mbufs for descriptor rings */
4807         err = ixgbevf_dev_rx_init(dev);
4808         if (err) {
4809                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4810                 ixgbe_dev_clear_queues(dev);
4811                 return err;
4812         }
4813
4814         /* Set vfta */
4815         ixgbevf_set_vfta_all(dev, 1);
4816
4817         /* Set HW strip */
4818         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4819                 ETH_VLAN_EXTEND_MASK;
4820         ixgbevf_vlan_offload_set(dev, mask);
4821
4822         ixgbevf_dev_rxtx_start(dev);
4823
4824         /* check and configure queue intr-vector mapping */
4825         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4826                 intr_vector = dev->data->nb_rx_queues;
4827                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4828                         return -1;
4829         }
4830
4831         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4832                 intr_handle->intr_vec =
4833                         rte_zmalloc("intr_vec",
4834                                     dev->data->nb_rx_queues * sizeof(int), 0);
4835                 if (intr_handle->intr_vec == NULL) {
4836                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4837                                      " intr_vec", dev->data->nb_rx_queues);
4838                         return -ENOMEM;
4839                 }
4840         }
4841         ixgbevf_configure_msix(dev);
4842
4843         rte_intr_enable(intr_handle);
4844
4845         /* Re-enable interrupt for VF */
4846         ixgbevf_intr_enable(hw);
4847
4848         return 0;
4849 }
4850
4851 static void
4852 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4853 {
4854         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4855         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4856         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4857
4858         PMD_INIT_FUNC_TRACE();
4859
4860         ixgbevf_intr_disable(hw);
4861
4862         hw->adapter_stopped = 1;
4863         ixgbe_stop_adapter(hw);
4864
4865         /*
4866           * Clear what we set, but we still keep shadow_vfta to
4867           * restore after device starts
4868           */
4869         ixgbevf_set_vfta_all(dev, 0);
4870
4871         /* Clear stored conf */
4872         dev->data->scattered_rx = 0;
4873
4874         ixgbe_dev_clear_queues(dev);
4875
4876         /* Clean datapath event and queue/vec mapping */
4877         rte_intr_efd_disable(intr_handle);
4878         if (intr_handle->intr_vec != NULL) {
4879                 rte_free(intr_handle->intr_vec);
4880                 intr_handle->intr_vec = NULL;
4881         }
4882 }
4883
4884 static void
4885 ixgbevf_dev_close(struct rte_eth_dev *dev)
4886 {
4887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4888
4889         PMD_INIT_FUNC_TRACE();
4890
4891         ixgbe_reset_hw(hw);
4892
4893         ixgbevf_dev_stop(dev);
4894
4895         ixgbe_dev_free_queues(dev);
4896
4897         /**
4898          * Remove the VF MAC address ro ensure
4899          * that the VF traffic goes to the PF
4900          * after stop, close and detach of the VF
4901          **/
4902         ixgbevf_remove_mac_addr(dev, 0);
4903 }
4904
4905 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4906 {
4907         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4908         struct ixgbe_vfta *shadow_vfta =
4909                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4910         int i = 0, j = 0, vfta = 0, mask = 1;
4911
4912         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4913                 vfta = shadow_vfta->vfta[i];
4914                 if (vfta) {
4915                         mask = 1;
4916                         for (j = 0; j < 32; j++) {
4917                                 if (vfta & mask)
4918                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4919                                                        on, false);
4920                                 mask <<= 1;
4921                         }
4922                 }
4923         }
4924
4925 }
4926
4927 static int
4928 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4929 {
4930         struct ixgbe_hw *hw =
4931                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4932         struct ixgbe_vfta *shadow_vfta =
4933                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4934         uint32_t vid_idx = 0;
4935         uint32_t vid_bit = 0;
4936         int ret = 0;
4937
4938         PMD_INIT_FUNC_TRACE();
4939
4940         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4941         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4942         if (ret) {
4943                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4944                 return ret;
4945         }
4946         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4947         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4948
4949         /* Save what we set and retore it after device reset */
4950         if (on)
4951                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4952         else
4953                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4954
4955         return 0;
4956 }
4957
4958 static void
4959 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4960 {
4961         struct ixgbe_hw *hw =
4962                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4963         uint32_t ctrl;
4964
4965         PMD_INIT_FUNC_TRACE();
4966
4967         if (queue >= hw->mac.max_rx_queues)
4968                 return;
4969
4970         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4971         if (on)
4972                 ctrl |= IXGBE_RXDCTL_VME;
4973         else
4974                 ctrl &= ~IXGBE_RXDCTL_VME;
4975         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4976
4977         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4978 }
4979
4980 static void
4981 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4982 {
4983         struct ixgbe_hw *hw =
4984                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4985         uint16_t i;
4986         int on = 0;
4987
4988         /* VF function only support hw strip feature, others are not support */
4989         if (mask & ETH_VLAN_STRIP_MASK) {
4990                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4991
4992                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4993                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4994         }
4995 }
4996
4997 int
4998 ixgbe_vt_check(struct ixgbe_hw *hw)
4999 {
5000         uint32_t reg_val;
5001
5002         /* if Virtualization Technology is enabled */
5003         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5004         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5005                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5006                 return -1;
5007         }
5008
5009         return 0;
5010 }
5011
5012 static uint32_t
5013 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5014 {
5015         uint32_t vector = 0;
5016
5017         switch (hw->mac.mc_filter_type) {
5018         case 0:   /* use bits [47:36] of the address */
5019                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5020                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5021                 break;
5022         case 1:   /* use bits [46:35] of the address */
5023                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5024                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5025                 break;
5026         case 2:   /* use bits [45:34] of the address */
5027                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5028                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5029                 break;
5030         case 3:   /* use bits [43:32] of the address */
5031                 vector = ((uc_addr->addr_bytes[4]) |
5032                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5033                 break;
5034         default:  /* Invalid mc_filter_type */
5035                 break;
5036         }
5037
5038         /* vector can only be 12-bits or boundary will be exceeded */
5039         vector &= 0xFFF;
5040         return vector;
5041 }
5042
5043 static int
5044 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5045                         uint8_t on)
5046 {
5047         uint32_t vector;
5048         uint32_t uta_idx;
5049         uint32_t reg_val;
5050         uint32_t uta_shift;
5051         uint32_t rc;
5052         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5053         const uint32_t ixgbe_uta_bit_shift = 5;
5054         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5055         const uint32_t bit1 = 0x1;
5056
5057         struct ixgbe_hw *hw =
5058                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5059         struct ixgbe_uta_info *uta_info =
5060                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5061
5062         /* The UTA table only exists on 82599 hardware and newer */
5063         if (hw->mac.type < ixgbe_mac_82599EB)
5064                 return -ENOTSUP;
5065
5066         vector = ixgbe_uta_vector(hw, mac_addr);
5067         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5068         uta_shift = vector & ixgbe_uta_bit_mask;
5069
5070         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5071         if (rc == on)
5072                 return 0;
5073
5074         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5075         if (on) {
5076                 uta_info->uta_in_use++;
5077                 reg_val |= (bit1 << uta_shift);
5078                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5079         } else {
5080                 uta_info->uta_in_use--;
5081                 reg_val &= ~(bit1 << uta_shift);
5082                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5083         }
5084
5085         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5086
5087         if (uta_info->uta_in_use > 0)
5088                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5089                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5090         else
5091                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5092
5093         return 0;
5094 }
5095
5096 static int
5097 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5098 {
5099         int i;
5100         struct ixgbe_hw *hw =
5101                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5102         struct ixgbe_uta_info *uta_info =
5103                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5104
5105         /* The UTA table only exists on 82599 hardware and newer */
5106         if (hw->mac.type < ixgbe_mac_82599EB)
5107                 return -ENOTSUP;
5108
5109         if (on) {
5110                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5111                         uta_info->uta_shadow[i] = ~0;
5112                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5113                 }
5114         } else {
5115                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5116                         uta_info->uta_shadow[i] = 0;
5117                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5118                 }
5119         }
5120         return 0;
5121
5122 }
5123
5124 uint32_t
5125 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5126 {
5127         uint32_t new_val = orig_val;
5128
5129         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5130                 new_val |= IXGBE_VMOLR_AUPE;
5131         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5132                 new_val |= IXGBE_VMOLR_ROMPE;
5133         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5134                 new_val |= IXGBE_VMOLR_ROPE;
5135         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5136                 new_val |= IXGBE_VMOLR_BAM;
5137         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5138                 new_val |= IXGBE_VMOLR_MPE;
5139
5140         return new_val;
5141 }
5142
5143 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5144 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5145 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5146 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5147 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5148         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5149         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5150
5151 static int
5152 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5153                       struct rte_eth_mirror_conf *mirror_conf,
5154                       uint8_t rule_id, uint8_t on)
5155 {
5156         uint32_t mr_ctl, vlvf;
5157         uint32_t mp_lsb = 0;
5158         uint32_t mv_msb = 0;
5159         uint32_t mv_lsb = 0;
5160         uint32_t mp_msb = 0;
5161         uint8_t i = 0;
5162         int reg_index = 0;
5163         uint64_t vlan_mask = 0;
5164
5165         const uint8_t pool_mask_offset = 32;
5166         const uint8_t vlan_mask_offset = 32;
5167         const uint8_t dst_pool_offset = 8;
5168         const uint8_t rule_mr_offset  = 4;
5169         const uint8_t mirror_rule_mask = 0x0F;
5170
5171         struct ixgbe_mirror_info *mr_info =
5172                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5173         struct ixgbe_hw *hw =
5174                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5175         uint8_t mirror_type = 0;
5176
5177         if (ixgbe_vt_check(hw) < 0)
5178                 return -ENOTSUP;
5179
5180         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5181                 return -EINVAL;
5182
5183         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5184                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5185                             mirror_conf->rule_type);
5186                 return -EINVAL;
5187         }
5188
5189         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5190                 mirror_type |= IXGBE_MRCTL_VLME;
5191                 /* Check if vlan id is valid and find conresponding VLAN ID
5192                  * index in VLVF
5193                  */
5194                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5195                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5196                                 /* search vlan id related pool vlan filter
5197                                  * index
5198                                  */
5199                                 reg_index = ixgbe_find_vlvf_slot(
5200                                                 hw,
5201                                                 mirror_conf->vlan.vlan_id[i],
5202                                                 false);
5203                                 if (reg_index < 0)
5204                                         return -EINVAL;
5205                                 vlvf = IXGBE_READ_REG(hw,
5206                                                       IXGBE_VLVF(reg_index));
5207                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5208                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5209                                       mirror_conf->vlan.vlan_id[i]))
5210                                         vlan_mask |= (1ULL << reg_index);
5211                                 else
5212                                         return -EINVAL;
5213                         }
5214                 }
5215
5216                 if (on) {
5217                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5218                         mv_msb = vlan_mask >> vlan_mask_offset;
5219
5220                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5221                                                 mirror_conf->vlan.vlan_mask;
5222                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5223                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5224                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5225                                                 mirror_conf->vlan.vlan_id[i];
5226                         }
5227                 } else {
5228                         mv_lsb = 0;
5229                         mv_msb = 0;
5230                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5231                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5232                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5233                 }
5234         }
5235
5236         /**
5237          * if enable pool mirror, write related pool mask register,if disable
5238          * pool mirror, clear PFMRVM register
5239          */
5240         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5241                 mirror_type |= IXGBE_MRCTL_VPME;
5242                 if (on) {
5243                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5244                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5245                         mr_info->mr_conf[rule_id].pool_mask =
5246                                         mirror_conf->pool_mask;
5247
5248                 } else {
5249                         mp_lsb = 0;
5250                         mp_msb = 0;
5251                         mr_info->mr_conf[rule_id].pool_mask = 0;
5252                 }
5253         }
5254         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5255                 mirror_type |= IXGBE_MRCTL_UPME;
5256         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5257                 mirror_type |= IXGBE_MRCTL_DPME;
5258
5259         /* read  mirror control register and recalculate it */
5260         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5261
5262         if (on) {
5263                 mr_ctl |= mirror_type;
5264                 mr_ctl &= mirror_rule_mask;
5265                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5266         } else {
5267                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5268         }
5269
5270         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5271         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5272
5273         /* write mirrror control  register */
5274         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5275
5276         /* write pool mirrror control  register */
5277         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5278                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5279                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5280                                 mp_msb);
5281         }
5282         /* write VLAN mirrror control  register */
5283         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5284                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5285                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5286                                 mv_msb);
5287         }
5288
5289         return 0;
5290 }
5291
5292 static int
5293 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5294 {
5295         int mr_ctl = 0;
5296         uint32_t lsb_val = 0;
5297         uint32_t msb_val = 0;
5298         const uint8_t rule_mr_offset = 4;
5299
5300         struct ixgbe_hw *hw =
5301                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5302         struct ixgbe_mirror_info *mr_info =
5303                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5304
5305         if (ixgbe_vt_check(hw) < 0)
5306                 return -ENOTSUP;
5307
5308         memset(&mr_info->mr_conf[rule_id], 0,
5309                sizeof(struct rte_eth_mirror_conf));
5310
5311         /* clear PFVMCTL register */
5312         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5313
5314         /* clear pool mask register */
5315         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5316         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5317
5318         /* clear vlan mask register */
5319         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5320         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5321
5322         return 0;
5323 }
5324
5325 static int
5326 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5327 {
5328         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5329         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5330         uint32_t mask;
5331         struct ixgbe_hw *hw =
5332                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5333
5334         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5335         mask |= (1 << IXGBE_MISC_VEC_ID);
5336         RTE_SET_USED(queue_id);
5337         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5338
5339         rte_intr_enable(intr_handle);
5340
5341         return 0;
5342 }
5343
5344 static int
5345 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5346 {
5347         uint32_t mask;
5348         struct ixgbe_hw *hw =
5349                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5350
5351         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5352         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5353         RTE_SET_USED(queue_id);
5354         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5355
5356         return 0;
5357 }
5358
5359 static int
5360 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5361 {
5362         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5363         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5364         uint32_t mask;
5365         struct ixgbe_hw *hw =
5366                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5367         struct ixgbe_interrupt *intr =
5368                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5369
5370         if (queue_id < 16) {
5371                 ixgbe_disable_intr(hw);
5372                 intr->mask |= (1 << queue_id);
5373                 ixgbe_enable_intr(dev);
5374         } else if (queue_id < 32) {
5375                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5376                 mask &= (1 << queue_id);
5377                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5378         } else if (queue_id < 64) {
5379                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5380                 mask &= (1 << (queue_id - 32));
5381                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5382         }
5383         rte_intr_enable(intr_handle);
5384
5385         return 0;
5386 }
5387
5388 static int
5389 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5390 {
5391         uint32_t mask;
5392         struct ixgbe_hw *hw =
5393                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5394         struct ixgbe_interrupt *intr =
5395                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5396
5397         if (queue_id < 16) {
5398                 ixgbe_disable_intr(hw);
5399                 intr->mask &= ~(1 << queue_id);
5400                 ixgbe_enable_intr(dev);
5401         } else if (queue_id < 32) {
5402                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5403                 mask &= ~(1 << queue_id);
5404                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5405         } else if (queue_id < 64) {
5406                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5407                 mask &= ~(1 << (queue_id - 32));
5408                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5409         }
5410
5411         return 0;
5412 }
5413
5414 static void
5415 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5416                      uint8_t queue, uint8_t msix_vector)
5417 {
5418         uint32_t tmp, idx;
5419
5420         if (direction == -1) {
5421                 /* other causes */
5422                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5423                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5424                 tmp &= ~0xFF;
5425                 tmp |= msix_vector;
5426                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5427         } else {
5428                 /* rx or tx cause */
5429                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5430                 idx = ((16 * (queue & 1)) + (8 * direction));
5431                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5432                 tmp &= ~(0xFF << idx);
5433                 tmp |= (msix_vector << idx);
5434                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5435         }
5436 }
5437
5438 /**
5439  * set the IVAR registers, mapping interrupt causes to vectors
5440  * @param hw
5441  *  pointer to ixgbe_hw struct
5442  * @direction
5443  *  0 for Rx, 1 for Tx, -1 for other causes
5444  * @queue
5445  *  queue to map the corresponding interrupt to
5446  * @msix_vector
5447  *  the vector to map to the corresponding queue
5448  */
5449 static void
5450 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5451                    uint8_t queue, uint8_t msix_vector)
5452 {
5453         uint32_t tmp, idx;
5454
5455         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5456         if (hw->mac.type == ixgbe_mac_82598EB) {
5457                 if (direction == -1)
5458                         direction = 0;
5459                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5460                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5461                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5462                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5463                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5464         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5465                         (hw->mac.type == ixgbe_mac_X540)) {
5466                 if (direction == -1) {
5467                         /* other causes */
5468                         idx = ((queue & 1) * 8);
5469                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5470                         tmp &= ~(0xFF << idx);
5471                         tmp |= (msix_vector << idx);
5472                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5473                 } else {
5474                         /* rx or tx causes */
5475                         idx = ((16 * (queue & 1)) + (8 * direction));
5476                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5477                         tmp &= ~(0xFF << idx);
5478                         tmp |= (msix_vector << idx);
5479                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5480                 }
5481         }
5482 }
5483
5484 static void
5485 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5486 {
5487         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5488         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5489         struct ixgbe_hw *hw =
5490                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5491         uint32_t q_idx;
5492         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5493
5494         /* Configure VF other cause ivar */
5495         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5496
5497         /* won't configure msix register if no mapping is done
5498          * between intr vector and event fd.
5499          */
5500         if (!rte_intr_dp_is_en(intr_handle))
5501                 return;
5502
5503         /* Configure all RX queues of VF */
5504         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5505                 /* Force all queue use vector 0,
5506                  * as IXGBE_VF_MAXMSIVECOTR = 1
5507                  */
5508                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5509                 intr_handle->intr_vec[q_idx] = vector_idx;
5510         }
5511 }
5512
5513 /**
5514  * Sets up the hardware to properly generate MSI-X interrupts
5515  * @hw
5516  *  board private structure
5517  */
5518 static void
5519 ixgbe_configure_msix(struct rte_eth_dev *dev)
5520 {
5521         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5522         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5523         struct ixgbe_hw *hw =
5524                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5525         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5526         uint32_t vec = IXGBE_MISC_VEC_ID;
5527         uint32_t mask;
5528         uint32_t gpie;
5529
5530         /* won't configure msix register if no mapping is done
5531          * between intr vector and event fd
5532          */
5533         if (!rte_intr_dp_is_en(intr_handle))
5534                 return;
5535
5536         if (rte_intr_allow_others(intr_handle))
5537                 vec = base = IXGBE_RX_VEC_START;
5538
5539         /* setup GPIE for MSI-x mode */
5540         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5541         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5542                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5543         /* auto clearing and auto setting corresponding bits in EIMS
5544          * when MSI-X interrupt is triggered
5545          */
5546         if (hw->mac.type == ixgbe_mac_82598EB) {
5547                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5548         } else {
5549                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5550                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5551         }
5552         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5553
5554         /* Populate the IVAR table and set the ITR values to the
5555          * corresponding register.
5556          */
5557         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5558              queue_id++) {
5559                 /* by default, 1:1 mapping */
5560                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5561                 intr_handle->intr_vec[queue_id] = vec;
5562                 if (vec < base + intr_handle->nb_efd - 1)
5563                         vec++;
5564         }
5565
5566         switch (hw->mac.type) {
5567         case ixgbe_mac_82598EB:
5568                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5569                                    IXGBE_MISC_VEC_ID);
5570                 break;
5571         case ixgbe_mac_82599EB:
5572         case ixgbe_mac_X540:
5573                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5574                 break;
5575         default:
5576                 break;
5577         }
5578         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5579                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5580
5581         /* set up to autoclear timer, and the vectors */
5582         mask = IXGBE_EIMS_ENABLE_MASK;
5583         mask &= ~(IXGBE_EIMS_OTHER |
5584                   IXGBE_EIMS_MAILBOX |
5585                   IXGBE_EIMS_LSC);
5586
5587         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5588 }
5589
5590 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5591         uint16_t queue_idx, uint16_t tx_rate)
5592 {
5593         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5594         uint32_t rf_dec, rf_int;
5595         uint32_t bcnrc_val;
5596         uint16_t link_speed = dev->data->dev_link.link_speed;
5597
5598         if (queue_idx >= hw->mac.max_tx_queues)
5599                 return -EINVAL;
5600
5601         if (tx_rate != 0) {
5602                 /* Calculate the rate factor values to set */
5603                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5604                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5605                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5606
5607                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5608                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5609                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5610                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5611         } else {
5612                 bcnrc_val = 0;
5613         }
5614
5615         /*
5616          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5617          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5618          * set as 0x4.
5619          */
5620         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5621                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5622                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5623                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5624                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5625         else
5626                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5627                         IXGBE_MMW_SIZE_DEFAULT);
5628
5629         /* Set RTTBCNRC of queue X */
5630         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5631         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5632         IXGBE_WRITE_FLUSH(hw);
5633
5634         return 0;
5635 }
5636
5637 static int
5638 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5639                      __attribute__((unused)) uint32_t index,
5640                      __attribute__((unused)) uint32_t pool)
5641 {
5642         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5643         int diag;
5644
5645         /*
5646          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5647          * operation. Trap this case to avoid exhausting the [very limited]
5648          * set of PF resources used to store VF MAC addresses.
5649          */
5650         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5651                 return -1;
5652         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5653         if (diag != 0)
5654                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5655                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5656                             mac_addr->addr_bytes[0],
5657                             mac_addr->addr_bytes[1],
5658                             mac_addr->addr_bytes[2],
5659                             mac_addr->addr_bytes[3],
5660                             mac_addr->addr_bytes[4],
5661                             mac_addr->addr_bytes[5],
5662                             diag);
5663         return diag;
5664 }
5665
5666 static void
5667 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5668 {
5669         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5670         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5671         struct ether_addr *mac_addr;
5672         uint32_t i;
5673         int diag;
5674
5675         /*
5676          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5677          * not support the deletion of a given MAC address.
5678          * Instead, it imposes to delete all MAC addresses, then to add again
5679          * all MAC addresses with the exception of the one to be deleted.
5680          */
5681         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5682
5683         /*
5684          * Add again all MAC addresses, with the exception of the deleted one
5685          * and of the permanent MAC address.
5686          */
5687         for (i = 0, mac_addr = dev->data->mac_addrs;
5688              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5689                 /* Skip the deleted MAC address */
5690                 if (i == index)
5691                         continue;
5692                 /* Skip NULL MAC addresses */
5693                 if (is_zero_ether_addr(mac_addr))
5694                         continue;
5695                 /* Skip the permanent MAC address */
5696                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5697                         continue;
5698                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5699                 if (diag != 0)
5700                         PMD_DRV_LOG(ERR,
5701                                     "Adding again MAC address "
5702                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5703                                     "diag=%d",
5704                                     mac_addr->addr_bytes[0],
5705                                     mac_addr->addr_bytes[1],
5706                                     mac_addr->addr_bytes[2],
5707                                     mac_addr->addr_bytes[3],
5708                                     mac_addr->addr_bytes[4],
5709                                     mac_addr->addr_bytes[5],
5710                                     diag);
5711         }
5712 }
5713
5714 static void
5715 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5716 {
5717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5718
5719         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5720 }
5721
5722 int
5723 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5724                         struct rte_eth_syn_filter *filter,
5725                         bool add)
5726 {
5727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5728         struct ixgbe_filter_info *filter_info =
5729                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5730         uint32_t syn_info;
5731         uint32_t synqf;
5732
5733         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5734                 return -EINVAL;
5735
5736         syn_info = filter_info->syn_info;
5737
5738         if (add) {
5739                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5740                         return -EINVAL;
5741                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5742                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5743
5744                 if (filter->hig_pri)
5745                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5746                 else
5747                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5748         } else {
5749                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5750                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5751                         return -ENOENT;
5752                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5753         }
5754
5755         filter_info->syn_info = synqf;
5756         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5757         IXGBE_WRITE_FLUSH(hw);
5758         return 0;
5759 }
5760
5761 static int
5762 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5763                         struct rte_eth_syn_filter *filter)
5764 {
5765         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5766         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5767
5768         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5769                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5770                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5771                 return 0;
5772         }
5773         return -ENOENT;
5774 }
5775
5776 static int
5777 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5778                         enum rte_filter_op filter_op,
5779                         void *arg)
5780 {
5781         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5782         int ret;
5783
5784         MAC_TYPE_FILTER_SUP(hw->mac.type);
5785
5786         if (filter_op == RTE_ETH_FILTER_NOP)
5787                 return 0;
5788
5789         if (arg == NULL) {
5790                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5791                             filter_op);
5792                 return -EINVAL;
5793         }
5794
5795         switch (filter_op) {
5796         case RTE_ETH_FILTER_ADD:
5797                 ret = ixgbe_syn_filter_set(dev,
5798                                 (struct rte_eth_syn_filter *)arg,
5799                                 TRUE);
5800                 break;
5801         case RTE_ETH_FILTER_DELETE:
5802                 ret = ixgbe_syn_filter_set(dev,
5803                                 (struct rte_eth_syn_filter *)arg,
5804                                 FALSE);
5805                 break;
5806         case RTE_ETH_FILTER_GET:
5807                 ret = ixgbe_syn_filter_get(dev,
5808                                 (struct rte_eth_syn_filter *)arg);
5809                 break;
5810         default:
5811                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5812                 ret = -EINVAL;
5813                 break;
5814         }
5815
5816         return ret;
5817 }
5818
5819
5820 static inline enum ixgbe_5tuple_protocol
5821 convert_protocol_type(uint8_t protocol_value)
5822 {
5823         if (protocol_value == IPPROTO_TCP)
5824                 return IXGBE_FILTER_PROTOCOL_TCP;
5825         else if (protocol_value == IPPROTO_UDP)
5826                 return IXGBE_FILTER_PROTOCOL_UDP;
5827         else if (protocol_value == IPPROTO_SCTP)
5828                 return IXGBE_FILTER_PROTOCOL_SCTP;
5829         else
5830                 return IXGBE_FILTER_PROTOCOL_NONE;
5831 }
5832
5833 /* inject a 5-tuple filter to HW */
5834 static inline void
5835 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5836                            struct ixgbe_5tuple_filter *filter)
5837 {
5838         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5839         int i;
5840         uint32_t ftqf, sdpqf;
5841         uint32_t l34timir = 0;
5842         uint8_t mask = 0xff;
5843
5844         i = filter->index;
5845
5846         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5847                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5848         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5849
5850         ftqf = (uint32_t)(filter->filter_info.proto &
5851                 IXGBE_FTQF_PROTOCOL_MASK);
5852         ftqf |= (uint32_t)((filter->filter_info.priority &
5853                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5854         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5855                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5856         if (filter->filter_info.dst_ip_mask == 0)
5857                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5858         if (filter->filter_info.src_port_mask == 0)
5859                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5860         if (filter->filter_info.dst_port_mask == 0)
5861                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5862         if (filter->filter_info.proto_mask == 0)
5863                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5864         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5865         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5866         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5867
5868         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5869         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5870         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5871         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5872
5873         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5874         l34timir |= (uint32_t)(filter->queue <<
5875                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5876         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5877 }
5878
5879 /*
5880  * add a 5tuple filter
5881  *
5882  * @param
5883  * dev: Pointer to struct rte_eth_dev.
5884  * index: the index the filter allocates.
5885  * filter: ponter to the filter that will be added.
5886  * rx_queue: the queue id the filter assigned to.
5887  *
5888  * @return
5889  *    - On success, zero.
5890  *    - On failure, a negative value.
5891  */
5892 static int
5893 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5894                         struct ixgbe_5tuple_filter *filter)
5895 {
5896         struct ixgbe_filter_info *filter_info =
5897                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5898         int i, idx, shift;
5899
5900         /*
5901          * look for an unused 5tuple filter index,
5902          * and insert the filter to list.
5903          */
5904         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5905                 idx = i / (sizeof(uint32_t) * NBBY);
5906                 shift = i % (sizeof(uint32_t) * NBBY);
5907                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5908                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5909                         filter->index = i;
5910                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5911                                           filter,
5912                                           entries);
5913                         break;
5914                 }
5915         }
5916         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5917                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5918                 return -ENOSYS;
5919         }
5920
5921         ixgbe_inject_5tuple_filter(dev, filter);
5922
5923         return 0;
5924 }
5925
5926 /*
5927  * remove a 5tuple filter
5928  *
5929  * @param
5930  * dev: Pointer to struct rte_eth_dev.
5931  * filter: the pointer of the filter will be removed.
5932  */
5933 static void
5934 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5935                         struct ixgbe_5tuple_filter *filter)
5936 {
5937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5938         struct ixgbe_filter_info *filter_info =
5939                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5940         uint16_t index = filter->index;
5941
5942         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5943                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5944         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5945         rte_free(filter);
5946
5947         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5948         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5949         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5950         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5951         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5952 }
5953
5954 static int
5955 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5956 {
5957         struct ixgbe_hw *hw;
5958         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5959         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
5960
5961         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5962
5963         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5964                 return -EINVAL;
5965
5966         /* refuse mtu that requires the support of scattered packets when this
5967          * feature has not been enabled before.
5968          */
5969         if (!rx_conf->enable_scatter &&
5970             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5971              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5972                 return -EINVAL;
5973
5974         /*
5975          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5976          * request of the version 2.0 of the mailbox API.
5977          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5978          * of the mailbox API.
5979          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5980          * prior to 3.11.33 which contains the following change:
5981          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5982          */
5983         ixgbevf_rlpml_set_vf(hw, max_frame);
5984
5985         /* update max frame size */
5986         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5987         return 0;
5988 }
5989
5990 static inline struct ixgbe_5tuple_filter *
5991 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5992                         struct ixgbe_5tuple_filter_info *key)
5993 {
5994         struct ixgbe_5tuple_filter *it;
5995
5996         TAILQ_FOREACH(it, filter_list, entries) {
5997                 if (memcmp(key, &it->filter_info,
5998                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5999                         return it;
6000                 }
6001         }
6002         return NULL;
6003 }
6004
6005 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6006 static inline int
6007 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6008                         struct ixgbe_5tuple_filter_info *filter_info)
6009 {
6010         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6011                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6012                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6013                 return -EINVAL;
6014
6015         switch (filter->dst_ip_mask) {
6016         case UINT32_MAX:
6017                 filter_info->dst_ip_mask = 0;
6018                 filter_info->dst_ip = filter->dst_ip;
6019                 break;
6020         case 0:
6021                 filter_info->dst_ip_mask = 1;
6022                 break;
6023         default:
6024                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6025                 return -EINVAL;
6026         }
6027
6028         switch (filter->src_ip_mask) {
6029         case UINT32_MAX:
6030                 filter_info->src_ip_mask = 0;
6031                 filter_info->src_ip = filter->src_ip;
6032                 break;
6033         case 0:
6034                 filter_info->src_ip_mask = 1;
6035                 break;
6036         default:
6037                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6038                 return -EINVAL;
6039         }
6040
6041         switch (filter->dst_port_mask) {
6042         case UINT16_MAX:
6043                 filter_info->dst_port_mask = 0;
6044                 filter_info->dst_port = filter->dst_port;
6045                 break;
6046         case 0:
6047                 filter_info->dst_port_mask = 1;
6048                 break;
6049         default:
6050                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6051                 return -EINVAL;
6052         }
6053
6054         switch (filter->src_port_mask) {
6055         case UINT16_MAX:
6056                 filter_info->src_port_mask = 0;
6057                 filter_info->src_port = filter->src_port;
6058                 break;
6059         case 0:
6060                 filter_info->src_port_mask = 1;
6061                 break;
6062         default:
6063                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6064                 return -EINVAL;
6065         }
6066
6067         switch (filter->proto_mask) {
6068         case UINT8_MAX:
6069                 filter_info->proto_mask = 0;
6070                 filter_info->proto =
6071                         convert_protocol_type(filter->proto);
6072                 break;
6073         case 0:
6074                 filter_info->proto_mask = 1;
6075                 break;
6076         default:
6077                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6078                 return -EINVAL;
6079         }
6080
6081         filter_info->priority = (uint8_t)filter->priority;
6082         return 0;
6083 }
6084
6085 /*
6086  * add or delete a ntuple filter
6087  *
6088  * @param
6089  * dev: Pointer to struct rte_eth_dev.
6090  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6091  * add: if true, add filter, if false, remove filter
6092  *
6093  * @return
6094  *    - On success, zero.
6095  *    - On failure, a negative value.
6096  */
6097 int
6098 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6099                         struct rte_eth_ntuple_filter *ntuple_filter,
6100                         bool add)
6101 {
6102         struct ixgbe_filter_info *filter_info =
6103                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6104         struct ixgbe_5tuple_filter_info filter_5tuple;
6105         struct ixgbe_5tuple_filter *filter;
6106         int ret;
6107
6108         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6109                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6110                 return -EINVAL;
6111         }
6112
6113         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6114         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6115         if (ret < 0)
6116                 return ret;
6117
6118         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6119                                          &filter_5tuple);
6120         if (filter != NULL && add) {
6121                 PMD_DRV_LOG(ERR, "filter exists.");
6122                 return -EEXIST;
6123         }
6124         if (filter == NULL && !add) {
6125                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6126                 return -ENOENT;
6127         }
6128
6129         if (add) {
6130                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6131                                 sizeof(struct ixgbe_5tuple_filter), 0);
6132                 if (filter == NULL)
6133                         return -ENOMEM;
6134                 (void)rte_memcpy(&filter->filter_info,
6135                                  &filter_5tuple,
6136                                  sizeof(struct ixgbe_5tuple_filter_info));
6137                 filter->queue = ntuple_filter->queue;
6138                 ret = ixgbe_add_5tuple_filter(dev, filter);
6139                 if (ret < 0) {
6140                         rte_free(filter);
6141                         return ret;
6142                 }
6143         } else
6144                 ixgbe_remove_5tuple_filter(dev, filter);
6145
6146         return 0;
6147 }
6148
6149 /*
6150  * get a ntuple filter
6151  *
6152  * @param
6153  * dev: Pointer to struct rte_eth_dev.
6154  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6155  *
6156  * @return
6157  *    - On success, zero.
6158  *    - On failure, a negative value.
6159  */
6160 static int
6161 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6162                         struct rte_eth_ntuple_filter *ntuple_filter)
6163 {
6164         struct ixgbe_filter_info *filter_info =
6165                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6166         struct ixgbe_5tuple_filter_info filter_5tuple;
6167         struct ixgbe_5tuple_filter *filter;
6168         int ret;
6169
6170         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6171                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6172                 return -EINVAL;
6173         }
6174
6175         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6176         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6177         if (ret < 0)
6178                 return ret;
6179
6180         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6181                                          &filter_5tuple);
6182         if (filter == NULL) {
6183                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6184                 return -ENOENT;
6185         }
6186         ntuple_filter->queue = filter->queue;
6187         return 0;
6188 }
6189
6190 /*
6191  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6192  * @dev: pointer to rte_eth_dev structure
6193  * @filter_op:operation will be taken.
6194  * @arg: a pointer to specific structure corresponding to the filter_op
6195  *
6196  * @return
6197  *    - On success, zero.
6198  *    - On failure, a negative value.
6199  */
6200 static int
6201 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6202                                 enum rte_filter_op filter_op,
6203                                 void *arg)
6204 {
6205         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6206         int ret;
6207
6208         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6209
6210         if (filter_op == RTE_ETH_FILTER_NOP)
6211                 return 0;
6212
6213         if (arg == NULL) {
6214                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6215                             filter_op);
6216                 return -EINVAL;
6217         }
6218
6219         switch (filter_op) {
6220         case RTE_ETH_FILTER_ADD:
6221                 ret = ixgbe_add_del_ntuple_filter(dev,
6222                         (struct rte_eth_ntuple_filter *)arg,
6223                         TRUE);
6224                 break;
6225         case RTE_ETH_FILTER_DELETE:
6226                 ret = ixgbe_add_del_ntuple_filter(dev,
6227                         (struct rte_eth_ntuple_filter *)arg,
6228                         FALSE);
6229                 break;
6230         case RTE_ETH_FILTER_GET:
6231                 ret = ixgbe_get_ntuple_filter(dev,
6232                         (struct rte_eth_ntuple_filter *)arg);
6233                 break;
6234         default:
6235                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6236                 ret = -EINVAL;
6237                 break;
6238         }
6239         return ret;
6240 }
6241
6242 int
6243 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6244                         struct rte_eth_ethertype_filter *filter,
6245                         bool add)
6246 {
6247         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6248         struct ixgbe_filter_info *filter_info =
6249                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6250         uint32_t etqf = 0;
6251         uint32_t etqs = 0;
6252         int ret;
6253         struct ixgbe_ethertype_filter ethertype_filter;
6254
6255         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6256                 return -EINVAL;
6257
6258         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6259                 filter->ether_type == ETHER_TYPE_IPv6) {
6260                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6261                         " ethertype filter.", filter->ether_type);
6262                 return -EINVAL;
6263         }
6264
6265         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6266                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6267                 return -EINVAL;
6268         }
6269         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6270                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6271                 return -EINVAL;
6272         }
6273
6274         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6275         if (ret >= 0 && add) {
6276                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6277                             filter->ether_type);
6278                 return -EEXIST;
6279         }
6280         if (ret < 0 && !add) {
6281                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6282                             filter->ether_type);
6283                 return -ENOENT;
6284         }
6285
6286         if (add) {
6287                 etqf = IXGBE_ETQF_FILTER_EN;
6288                 etqf |= (uint32_t)filter->ether_type;
6289                 etqs |= (uint32_t)((filter->queue <<
6290                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6291                                     IXGBE_ETQS_RX_QUEUE);
6292                 etqs |= IXGBE_ETQS_QUEUE_EN;
6293
6294                 ethertype_filter.ethertype = filter->ether_type;
6295                 ethertype_filter.etqf = etqf;
6296                 ethertype_filter.etqs = etqs;
6297                 ethertype_filter.conf = FALSE;
6298                 ret = ixgbe_ethertype_filter_insert(filter_info,
6299                                                     &ethertype_filter);
6300                 if (ret < 0) {
6301                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6302                         return -ENOSPC;
6303                 }
6304         } else {
6305                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6306                 if (ret < 0)
6307                         return -ENOSYS;
6308         }
6309         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6310         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6311         IXGBE_WRITE_FLUSH(hw);
6312
6313         return 0;
6314 }
6315
6316 static int
6317 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6318                         struct rte_eth_ethertype_filter *filter)
6319 {
6320         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6321         struct ixgbe_filter_info *filter_info =
6322                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6323         uint32_t etqf, etqs;
6324         int ret;
6325
6326         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6327         if (ret < 0) {
6328                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6329                             filter->ether_type);
6330                 return -ENOENT;
6331         }
6332
6333         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6334         if (etqf & IXGBE_ETQF_FILTER_EN) {
6335                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6336                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6337                 filter->flags = 0;
6338                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6339                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6340                 return 0;
6341         }
6342         return -ENOENT;
6343 }
6344
6345 /*
6346  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6347  * @dev: pointer to rte_eth_dev structure
6348  * @filter_op:operation will be taken.
6349  * @arg: a pointer to specific structure corresponding to the filter_op
6350  */
6351 static int
6352 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6353                                 enum rte_filter_op filter_op,
6354                                 void *arg)
6355 {
6356         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6357         int ret;
6358
6359         MAC_TYPE_FILTER_SUP(hw->mac.type);
6360
6361         if (filter_op == RTE_ETH_FILTER_NOP)
6362                 return 0;
6363
6364         if (arg == NULL) {
6365                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6366                             filter_op);
6367                 return -EINVAL;
6368         }
6369
6370         switch (filter_op) {
6371         case RTE_ETH_FILTER_ADD:
6372                 ret = ixgbe_add_del_ethertype_filter(dev,
6373                         (struct rte_eth_ethertype_filter *)arg,
6374                         TRUE);
6375                 break;
6376         case RTE_ETH_FILTER_DELETE:
6377                 ret = ixgbe_add_del_ethertype_filter(dev,
6378                         (struct rte_eth_ethertype_filter *)arg,
6379                         FALSE);
6380                 break;
6381         case RTE_ETH_FILTER_GET:
6382                 ret = ixgbe_get_ethertype_filter(dev,
6383                         (struct rte_eth_ethertype_filter *)arg);
6384                 break;
6385         default:
6386                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6387                 ret = -EINVAL;
6388                 break;
6389         }
6390         return ret;
6391 }
6392
6393 static int
6394 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6395                      enum rte_filter_type filter_type,
6396                      enum rte_filter_op filter_op,
6397                      void *arg)
6398 {
6399         int ret = 0;
6400
6401         switch (filter_type) {
6402         case RTE_ETH_FILTER_NTUPLE:
6403                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6404                 break;
6405         case RTE_ETH_FILTER_ETHERTYPE:
6406                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6407                 break;
6408         case RTE_ETH_FILTER_SYN:
6409                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6410                 break;
6411         case RTE_ETH_FILTER_FDIR:
6412                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6413                 break;
6414         case RTE_ETH_FILTER_L2_TUNNEL:
6415                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6416                 break;
6417         case RTE_ETH_FILTER_GENERIC:
6418                 if (filter_op != RTE_ETH_FILTER_GET)
6419                         return -EINVAL;
6420                 *(const void **)arg = &ixgbe_flow_ops;
6421                 break;
6422         default:
6423                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6424                                                         filter_type);
6425                 ret = -EINVAL;
6426                 break;
6427         }
6428
6429         return ret;
6430 }
6431
6432 static u8 *
6433 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6434                         u8 **mc_addr_ptr, u32 *vmdq)
6435 {
6436         u8 *mc_addr;
6437
6438         *vmdq = 0;
6439         mc_addr = *mc_addr_ptr;
6440         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6441         return mc_addr;
6442 }
6443
6444 static int
6445 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6446                           struct ether_addr *mc_addr_set,
6447                           uint32_t nb_mc_addr)
6448 {
6449         struct ixgbe_hw *hw;
6450         u8 *mc_addr_list;
6451
6452         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6453         mc_addr_list = (u8 *)mc_addr_set;
6454         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6455                                          ixgbe_dev_addr_list_itr, TRUE);
6456 }
6457
6458 static uint64_t
6459 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6460 {
6461         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6462         uint64_t systime_cycles;
6463
6464         switch (hw->mac.type) {
6465         case ixgbe_mac_X550:
6466         case ixgbe_mac_X550EM_x:
6467         case ixgbe_mac_X550EM_a:
6468                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6469                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6470                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6471                                 * NSEC_PER_SEC;
6472                 break;
6473         default:
6474                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6475                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6476                                 << 32;
6477         }
6478
6479         return systime_cycles;
6480 }
6481
6482 static uint64_t
6483 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6484 {
6485         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6486         uint64_t rx_tstamp_cycles;
6487
6488         switch (hw->mac.type) {
6489         case ixgbe_mac_X550:
6490         case ixgbe_mac_X550EM_x:
6491         case ixgbe_mac_X550EM_a:
6492                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6493                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6494                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6495                                 * NSEC_PER_SEC;
6496                 break;
6497         default:
6498                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6499                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6500                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6501                                 << 32;
6502         }
6503
6504         return rx_tstamp_cycles;
6505 }
6506
6507 static uint64_t
6508 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6509 {
6510         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6511         uint64_t tx_tstamp_cycles;
6512
6513         switch (hw->mac.type) {
6514         case ixgbe_mac_X550:
6515         case ixgbe_mac_X550EM_x:
6516         case ixgbe_mac_X550EM_a:
6517                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6518                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6519                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6520                                 * NSEC_PER_SEC;
6521                 break;
6522         default:
6523                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6524                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6525                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6526                                 << 32;
6527         }
6528
6529         return tx_tstamp_cycles;
6530 }
6531
6532 static void
6533 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6534 {
6535         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6536         struct ixgbe_adapter *adapter =
6537                 (struct ixgbe_adapter *)dev->data->dev_private;
6538         struct rte_eth_link link;
6539         uint32_t incval = 0;
6540         uint32_t shift = 0;
6541
6542         /* Get current link speed. */
6543         memset(&link, 0, sizeof(link));
6544         ixgbe_dev_link_update(dev, 1);
6545         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6546
6547         switch (link.link_speed) {
6548         case ETH_SPEED_NUM_100M:
6549                 incval = IXGBE_INCVAL_100;
6550                 shift = IXGBE_INCVAL_SHIFT_100;
6551                 break;
6552         case ETH_SPEED_NUM_1G:
6553                 incval = IXGBE_INCVAL_1GB;
6554                 shift = IXGBE_INCVAL_SHIFT_1GB;
6555                 break;
6556         case ETH_SPEED_NUM_10G:
6557         default:
6558                 incval = IXGBE_INCVAL_10GB;
6559                 shift = IXGBE_INCVAL_SHIFT_10GB;
6560                 break;
6561         }
6562
6563         switch (hw->mac.type) {
6564         case ixgbe_mac_X550:
6565         case ixgbe_mac_X550EM_x:
6566         case ixgbe_mac_X550EM_a:
6567                 /* Independent of link speed. */
6568                 incval = 1;
6569                 /* Cycles read will be interpreted as ns. */
6570                 shift = 0;
6571                 /* Fall-through */
6572         case ixgbe_mac_X540:
6573                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6574                 break;
6575         case ixgbe_mac_82599EB:
6576                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6577                 shift -= IXGBE_INCVAL_SHIFT_82599;
6578                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6579                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6580                 break;
6581         default:
6582                 /* Not supported. */
6583                 return;
6584         }
6585
6586         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6587         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6588         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6589
6590         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6591         adapter->systime_tc.cc_shift = shift;
6592         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6593
6594         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6595         adapter->rx_tstamp_tc.cc_shift = shift;
6596         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6597
6598         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6599         adapter->tx_tstamp_tc.cc_shift = shift;
6600         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6601 }
6602
6603 static int
6604 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6605 {
6606         struct ixgbe_adapter *adapter =
6607                         (struct ixgbe_adapter *)dev->data->dev_private;
6608
6609         adapter->systime_tc.nsec += delta;
6610         adapter->rx_tstamp_tc.nsec += delta;
6611         adapter->tx_tstamp_tc.nsec += delta;
6612
6613         return 0;
6614 }
6615
6616 static int
6617 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6618 {
6619         uint64_t ns;
6620         struct ixgbe_adapter *adapter =
6621                         (struct ixgbe_adapter *)dev->data->dev_private;
6622
6623         ns = rte_timespec_to_ns(ts);
6624         /* Set the timecounters to a new value. */
6625         adapter->systime_tc.nsec = ns;
6626         adapter->rx_tstamp_tc.nsec = ns;
6627         adapter->tx_tstamp_tc.nsec = ns;
6628
6629         return 0;
6630 }
6631
6632 static int
6633 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6634 {
6635         uint64_t ns, systime_cycles;
6636         struct ixgbe_adapter *adapter =
6637                         (struct ixgbe_adapter *)dev->data->dev_private;
6638
6639         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6640         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6641         *ts = rte_ns_to_timespec(ns);
6642
6643         return 0;
6644 }
6645
6646 static int
6647 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6648 {
6649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6650         uint32_t tsync_ctl;
6651         uint32_t tsauxc;
6652
6653         /* Stop the timesync system time. */
6654         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6655         /* Reset the timesync system time value. */
6656         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6657         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6658
6659         /* Enable system time for platforms where it isn't on by default. */
6660         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6661         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6662         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6663
6664         ixgbe_start_timecounters(dev);
6665
6666         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6667         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6668                         (ETHER_TYPE_1588 |
6669                          IXGBE_ETQF_FILTER_EN |
6670                          IXGBE_ETQF_1588));
6671
6672         /* Enable timestamping of received PTP packets. */
6673         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6674         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6675         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6676
6677         /* Enable timestamping of transmitted PTP packets. */
6678         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6679         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6680         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6681
6682         IXGBE_WRITE_FLUSH(hw);
6683
6684         return 0;
6685 }
6686
6687 static int
6688 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6689 {
6690         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6691         uint32_t tsync_ctl;
6692
6693         /* Disable timestamping of transmitted PTP packets. */
6694         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6695         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6696         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6697
6698         /* Disable timestamping of received PTP packets. */
6699         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6700         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6701         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6702
6703         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6704         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6705
6706         /* Stop incrementating the System Time registers. */
6707         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6708
6709         return 0;
6710 }
6711
6712 static int
6713 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6714                                  struct timespec *timestamp,
6715                                  uint32_t flags __rte_unused)
6716 {
6717         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6718         struct ixgbe_adapter *adapter =
6719                 (struct ixgbe_adapter *)dev->data->dev_private;
6720         uint32_t tsync_rxctl;
6721         uint64_t rx_tstamp_cycles;
6722         uint64_t ns;
6723
6724         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6725         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6726                 return -EINVAL;
6727
6728         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6729         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6730         *timestamp = rte_ns_to_timespec(ns);
6731
6732         return  0;
6733 }
6734
6735 static int
6736 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6737                                  struct timespec *timestamp)
6738 {
6739         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6740         struct ixgbe_adapter *adapter =
6741                 (struct ixgbe_adapter *)dev->data->dev_private;
6742         uint32_t tsync_txctl;
6743         uint64_t tx_tstamp_cycles;
6744         uint64_t ns;
6745
6746         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6747         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6748                 return -EINVAL;
6749
6750         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6751         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6752         *timestamp = rte_ns_to_timespec(ns);
6753
6754         return 0;
6755 }
6756
6757 static int
6758 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6759 {
6760         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6761         int count = 0;
6762         int g_ind = 0;
6763         const struct reg_info *reg_group;
6764         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6765                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6766
6767         while ((reg_group = reg_set[g_ind++]))
6768                 count += ixgbe_regs_group_count(reg_group);
6769
6770         return count;
6771 }
6772
6773 static int
6774 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6775 {
6776         int count = 0;
6777         int g_ind = 0;
6778         const struct reg_info *reg_group;
6779
6780         while ((reg_group = ixgbevf_regs[g_ind++]))
6781                 count += ixgbe_regs_group_count(reg_group);
6782
6783         return count;
6784 }
6785
6786 static int
6787 ixgbe_get_regs(struct rte_eth_dev *dev,
6788               struct rte_dev_reg_info *regs)
6789 {
6790         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6791         uint32_t *data = regs->data;
6792         int g_ind = 0;
6793         int count = 0;
6794         const struct reg_info *reg_group;
6795         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6796                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6797
6798         if (data == NULL) {
6799                 regs->length = ixgbe_get_reg_length(dev);
6800                 regs->width = sizeof(uint32_t);
6801                 return 0;
6802         }
6803
6804         /* Support only full register dump */
6805         if ((regs->length == 0) ||
6806             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6807                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6808                         hw->device_id;
6809                 while ((reg_group = reg_set[g_ind++]))
6810                         count += ixgbe_read_regs_group(dev, &data[count],
6811                                 reg_group);
6812                 return 0;
6813         }
6814
6815         return -ENOTSUP;
6816 }
6817
6818 static int
6819 ixgbevf_get_regs(struct rte_eth_dev *dev,
6820                 struct rte_dev_reg_info *regs)
6821 {
6822         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6823         uint32_t *data = regs->data;
6824         int g_ind = 0;
6825         int count = 0;
6826         const struct reg_info *reg_group;
6827
6828         if (data == NULL) {
6829                 regs->length = ixgbevf_get_reg_length(dev);
6830                 regs->width = sizeof(uint32_t);
6831                 return 0;
6832         }
6833
6834         /* Support only full register dump */
6835         if ((regs->length == 0) ||
6836             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6837                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6838                         hw->device_id;
6839                 while ((reg_group = ixgbevf_regs[g_ind++]))
6840                         count += ixgbe_read_regs_group(dev, &data[count],
6841                                                       reg_group);
6842                 return 0;
6843         }
6844
6845         return -ENOTSUP;
6846 }
6847
6848 static int
6849 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6850 {
6851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6852
6853         /* Return unit is byte count */
6854         return hw->eeprom.word_size * 2;
6855 }
6856
6857 static int
6858 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6859                 struct rte_dev_eeprom_info *in_eeprom)
6860 {
6861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6862         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6863         uint16_t *data = in_eeprom->data;
6864         int first, length;
6865
6866         first = in_eeprom->offset >> 1;
6867         length = in_eeprom->length >> 1;
6868         if ((first > hw->eeprom.word_size) ||
6869             ((first + length) > hw->eeprom.word_size))
6870                 return -EINVAL;
6871
6872         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6873
6874         return eeprom->ops.read_buffer(hw, first, length, data);
6875 }
6876
6877 static int
6878 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6879                 struct rte_dev_eeprom_info *in_eeprom)
6880 {
6881         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6882         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6883         uint16_t *data = in_eeprom->data;
6884         int first, length;
6885
6886         first = in_eeprom->offset >> 1;
6887         length = in_eeprom->length >> 1;
6888         if ((first > hw->eeprom.word_size) ||
6889             ((first + length) > hw->eeprom.word_size))
6890                 return -EINVAL;
6891
6892         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6893
6894         return eeprom->ops.write_buffer(hw,  first, length, data);
6895 }
6896
6897 uint16_t
6898 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6899         switch (mac_type) {
6900         case ixgbe_mac_X550:
6901         case ixgbe_mac_X550EM_x:
6902         case ixgbe_mac_X550EM_a:
6903                 return ETH_RSS_RETA_SIZE_512;
6904         case ixgbe_mac_X550_vf:
6905         case ixgbe_mac_X550EM_x_vf:
6906         case ixgbe_mac_X550EM_a_vf:
6907                 return ETH_RSS_RETA_SIZE_64;
6908         default:
6909                 return ETH_RSS_RETA_SIZE_128;
6910         }
6911 }
6912
6913 uint32_t
6914 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6915         switch (mac_type) {
6916         case ixgbe_mac_X550:
6917         case ixgbe_mac_X550EM_x:
6918         case ixgbe_mac_X550EM_a:
6919                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6920                         return IXGBE_RETA(reta_idx >> 2);
6921                 else
6922                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6923         case ixgbe_mac_X550_vf:
6924         case ixgbe_mac_X550EM_x_vf:
6925         case ixgbe_mac_X550EM_a_vf:
6926                 return IXGBE_VFRETA(reta_idx >> 2);
6927         default:
6928                 return IXGBE_RETA(reta_idx >> 2);
6929         }
6930 }
6931
6932 uint32_t
6933 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6934         switch (mac_type) {
6935         case ixgbe_mac_X550_vf:
6936         case ixgbe_mac_X550EM_x_vf:
6937         case ixgbe_mac_X550EM_a_vf:
6938                 return IXGBE_VFMRQC;
6939         default:
6940                 return IXGBE_MRQC;
6941         }
6942 }
6943
6944 uint32_t
6945 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6946         switch (mac_type) {
6947         case ixgbe_mac_X550_vf:
6948         case ixgbe_mac_X550EM_x_vf:
6949         case ixgbe_mac_X550EM_a_vf:
6950                 return IXGBE_VFRSSRK(i);
6951         default:
6952                 return IXGBE_RSSRK(i);
6953         }
6954 }
6955
6956 bool
6957 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6958         switch (mac_type) {
6959         case ixgbe_mac_82599_vf:
6960         case ixgbe_mac_X540_vf:
6961                 return 0;
6962         default:
6963                 return 1;
6964         }
6965 }
6966
6967 static int
6968 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6969                         struct rte_eth_dcb_info *dcb_info)
6970 {
6971         struct ixgbe_dcb_config *dcb_config =
6972                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6973         struct ixgbe_dcb_tc_config *tc;
6974         uint8_t i, j;
6975
6976         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6977                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6978         else
6979                 dcb_info->nb_tcs = 1;
6980
6981         if (dcb_config->vt_mode) { /* vt is enabled*/
6982                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6983                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6984                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6985                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6986                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6987                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6988                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6989                                                 i * dcb_info->nb_tcs + j;
6990                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6991                                 dcb_info->tc_queue.tc_txq[i][j].base =
6992                                                 i * dcb_info->nb_tcs + j;
6993                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6994                         }
6995                 }
6996         } else { /* vt is disabled*/
6997                 struct rte_eth_dcb_rx_conf *rx_conf =
6998                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6999                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7000                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7001                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7002                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7003                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7004                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7005                         }
7006                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7007                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7008                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7009                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7010                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7011                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7012                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7013                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7014                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7015                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7016                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7017                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7018                         }
7019                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7020                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7021                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7022                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7023                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7024                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7025                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7026                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7027                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7028                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7029                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7030                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7031                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7032                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7033                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7034                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7035                 }
7036         }
7037         for (i = 0; i < dcb_info->nb_tcs; i++) {
7038                 tc = &dcb_config->tc_config[i];
7039                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7040         }
7041         return 0;
7042 }
7043
7044 /* Update e-tag ether type */
7045 static int
7046 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7047                             uint16_t ether_type)
7048 {
7049         uint32_t etag_etype;
7050
7051         if (hw->mac.type != ixgbe_mac_X550 &&
7052             hw->mac.type != ixgbe_mac_X550EM_x &&
7053             hw->mac.type != ixgbe_mac_X550EM_a) {
7054                 return -ENOTSUP;
7055         }
7056
7057         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7058         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7059         etag_etype |= ether_type;
7060         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7061         IXGBE_WRITE_FLUSH(hw);
7062
7063         return 0;
7064 }
7065
7066 /* Config l2 tunnel ether type */
7067 static int
7068 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7069                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7070 {
7071         int ret = 0;
7072         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7073         struct ixgbe_l2_tn_info *l2_tn_info =
7074                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7075
7076         if (l2_tunnel == NULL)
7077                 return -EINVAL;
7078
7079         switch (l2_tunnel->l2_tunnel_type) {
7080         case RTE_L2_TUNNEL_TYPE_E_TAG:
7081                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7082                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7083                 break;
7084         default:
7085                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7086                 ret = -EINVAL;
7087                 break;
7088         }
7089
7090         return ret;
7091 }
7092
7093 /* Enable e-tag tunnel */
7094 static int
7095 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7096 {
7097         uint32_t etag_etype;
7098
7099         if (hw->mac.type != ixgbe_mac_X550 &&
7100             hw->mac.type != ixgbe_mac_X550EM_x &&
7101             hw->mac.type != ixgbe_mac_X550EM_a) {
7102                 return -ENOTSUP;
7103         }
7104
7105         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7106         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7107         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7108         IXGBE_WRITE_FLUSH(hw);
7109
7110         return 0;
7111 }
7112
7113 /* Enable l2 tunnel */
7114 static int
7115 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7116                            enum rte_eth_tunnel_type l2_tunnel_type)
7117 {
7118         int ret = 0;
7119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7120         struct ixgbe_l2_tn_info *l2_tn_info =
7121                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7122
7123         switch (l2_tunnel_type) {
7124         case RTE_L2_TUNNEL_TYPE_E_TAG:
7125                 l2_tn_info->e_tag_en = TRUE;
7126                 ret = ixgbe_e_tag_enable(hw);
7127                 break;
7128         default:
7129                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7130                 ret = -EINVAL;
7131                 break;
7132         }
7133
7134         return ret;
7135 }
7136
7137 /* Disable e-tag tunnel */
7138 static int
7139 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7140 {
7141         uint32_t etag_etype;
7142
7143         if (hw->mac.type != ixgbe_mac_X550 &&
7144             hw->mac.type != ixgbe_mac_X550EM_x &&
7145             hw->mac.type != ixgbe_mac_X550EM_a) {
7146                 return -ENOTSUP;
7147         }
7148
7149         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7150         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7151         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7152         IXGBE_WRITE_FLUSH(hw);
7153
7154         return 0;
7155 }
7156
7157 /* Disable l2 tunnel */
7158 static int
7159 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7160                             enum rte_eth_tunnel_type l2_tunnel_type)
7161 {
7162         int ret = 0;
7163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7164         struct ixgbe_l2_tn_info *l2_tn_info =
7165                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7166
7167         switch (l2_tunnel_type) {
7168         case RTE_L2_TUNNEL_TYPE_E_TAG:
7169                 l2_tn_info->e_tag_en = FALSE;
7170                 ret = ixgbe_e_tag_disable(hw);
7171                 break;
7172         default:
7173                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7174                 ret = -EINVAL;
7175                 break;
7176         }
7177
7178         return ret;
7179 }
7180
7181 static int
7182 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7183                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7184 {
7185         int ret = 0;
7186         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7187         uint32_t i, rar_entries;
7188         uint32_t rar_low, rar_high;
7189
7190         if (hw->mac.type != ixgbe_mac_X550 &&
7191             hw->mac.type != ixgbe_mac_X550EM_x &&
7192             hw->mac.type != ixgbe_mac_X550EM_a) {
7193                 return -ENOTSUP;
7194         }
7195
7196         rar_entries = ixgbe_get_num_rx_addrs(hw);
7197
7198         for (i = 1; i < rar_entries; i++) {
7199                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7200                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7201                 if ((rar_high & IXGBE_RAH_AV) &&
7202                     (rar_high & IXGBE_RAH_ADTYPE) &&
7203                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7204                      l2_tunnel->tunnel_id)) {
7205                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7206                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7207
7208                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7209
7210                         return ret;
7211                 }
7212         }
7213
7214         return ret;
7215 }
7216
7217 static int
7218 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7219                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7220 {
7221         int ret = 0;
7222         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7223         uint32_t i, rar_entries;
7224         uint32_t rar_low, rar_high;
7225
7226         if (hw->mac.type != ixgbe_mac_X550 &&
7227             hw->mac.type != ixgbe_mac_X550EM_x &&
7228             hw->mac.type != ixgbe_mac_X550EM_a) {
7229                 return -ENOTSUP;
7230         }
7231
7232         /* One entry for one tunnel. Try to remove potential existing entry. */
7233         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7234
7235         rar_entries = ixgbe_get_num_rx_addrs(hw);
7236
7237         for (i = 1; i < rar_entries; i++) {
7238                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7239                 if (rar_high & IXGBE_RAH_AV) {
7240                         continue;
7241                 } else {
7242                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7243                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7244                         rar_low = l2_tunnel->tunnel_id;
7245
7246                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7247                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7248
7249                         return ret;
7250                 }
7251         }
7252
7253         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7254                      " Please remove a rule before adding a new one.");
7255         return -EINVAL;
7256 }
7257
7258 static inline struct ixgbe_l2_tn_filter *
7259 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7260                           struct ixgbe_l2_tn_key *key)
7261 {
7262         int ret;
7263
7264         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7265         if (ret < 0)
7266                 return NULL;
7267
7268         return l2_tn_info->hash_map[ret];
7269 }
7270
7271 static inline int
7272 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7273                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7274 {
7275         int ret;
7276
7277         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7278                                &l2_tn_filter->key);
7279
7280         if (ret < 0) {
7281                 PMD_DRV_LOG(ERR,
7282                             "Failed to insert L2 tunnel filter"
7283                             " to hash table %d!",
7284                             ret);
7285                 return ret;
7286         }
7287
7288         l2_tn_info->hash_map[ret] = l2_tn_filter;
7289
7290         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7291
7292         return 0;
7293 }
7294
7295 static inline int
7296 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7297                           struct ixgbe_l2_tn_key *key)
7298 {
7299         int ret;
7300         struct ixgbe_l2_tn_filter *l2_tn_filter;
7301
7302         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7303
7304         if (ret < 0) {
7305                 PMD_DRV_LOG(ERR,
7306                             "No such L2 tunnel filter to delete %d!",
7307                             ret);
7308                 return ret;
7309         }
7310
7311         l2_tn_filter = l2_tn_info->hash_map[ret];
7312         l2_tn_info->hash_map[ret] = NULL;
7313
7314         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7315         rte_free(l2_tn_filter);
7316
7317         return 0;
7318 }
7319
7320 /* Add l2 tunnel filter */
7321 int
7322 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7323                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7324                                bool restore)
7325 {
7326         int ret;
7327         struct ixgbe_l2_tn_info *l2_tn_info =
7328                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7329         struct ixgbe_l2_tn_key key;
7330         struct ixgbe_l2_tn_filter *node;
7331
7332         if (!restore) {
7333                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7334                 key.tn_id = l2_tunnel->tunnel_id;
7335
7336                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7337
7338                 if (node) {
7339                         PMD_DRV_LOG(ERR,
7340                                     "The L2 tunnel filter already exists!");
7341                         return -EINVAL;
7342                 }
7343
7344                 node = rte_zmalloc("ixgbe_l2_tn",
7345                                    sizeof(struct ixgbe_l2_tn_filter),
7346                                    0);
7347                 if (!node)
7348                         return -ENOMEM;
7349
7350                 (void)rte_memcpy(&node->key,
7351                                  &key,
7352                                  sizeof(struct ixgbe_l2_tn_key));
7353                 node->pool = l2_tunnel->pool;
7354                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7355                 if (ret < 0) {
7356                         rte_free(node);
7357                         return ret;
7358                 }
7359         }
7360
7361         switch (l2_tunnel->l2_tunnel_type) {
7362         case RTE_L2_TUNNEL_TYPE_E_TAG:
7363                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7364                 break;
7365         default:
7366                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7367                 ret = -EINVAL;
7368                 break;
7369         }
7370
7371         if ((!restore) && (ret < 0))
7372                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7373
7374         return ret;
7375 }
7376
7377 /* Delete l2 tunnel filter */
7378 int
7379 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7380                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7381 {
7382         int ret;
7383         struct ixgbe_l2_tn_info *l2_tn_info =
7384                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7385         struct ixgbe_l2_tn_key key;
7386
7387         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7388         key.tn_id = l2_tunnel->tunnel_id;
7389         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7390         if (ret < 0)
7391                 return ret;
7392
7393         switch (l2_tunnel->l2_tunnel_type) {
7394         case RTE_L2_TUNNEL_TYPE_E_TAG:
7395                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7396                 break;
7397         default:
7398                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7399                 ret = -EINVAL;
7400                 break;
7401         }
7402
7403         return ret;
7404 }
7405
7406 /**
7407  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7408  * @dev: pointer to rte_eth_dev structure
7409  * @filter_op:operation will be taken.
7410  * @arg: a pointer to specific structure corresponding to the filter_op
7411  */
7412 static int
7413 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7414                                   enum rte_filter_op filter_op,
7415                                   void *arg)
7416 {
7417         int ret;
7418
7419         if (filter_op == RTE_ETH_FILTER_NOP)
7420                 return 0;
7421
7422         if (arg == NULL) {
7423                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7424                             filter_op);
7425                 return -EINVAL;
7426         }
7427
7428         switch (filter_op) {
7429         case RTE_ETH_FILTER_ADD:
7430                 ret = ixgbe_dev_l2_tunnel_filter_add
7431                         (dev,
7432                          (struct rte_eth_l2_tunnel_conf *)arg,
7433                          FALSE);
7434                 break;
7435         case RTE_ETH_FILTER_DELETE:
7436                 ret = ixgbe_dev_l2_tunnel_filter_del
7437                         (dev,
7438                          (struct rte_eth_l2_tunnel_conf *)arg);
7439                 break;
7440         default:
7441                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7442                 ret = -EINVAL;
7443                 break;
7444         }
7445         return ret;
7446 }
7447
7448 static int
7449 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7450 {
7451         int ret = 0;
7452         uint32_t ctrl;
7453         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7454
7455         if (hw->mac.type != ixgbe_mac_X550 &&
7456             hw->mac.type != ixgbe_mac_X550EM_x &&
7457             hw->mac.type != ixgbe_mac_X550EM_a) {
7458                 return -ENOTSUP;
7459         }
7460
7461         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7462         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7463         if (en)
7464                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7465         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7466
7467         return ret;
7468 }
7469
7470 /* Enable l2 tunnel forwarding */
7471 static int
7472 ixgbe_dev_l2_tunnel_forwarding_enable
7473         (struct rte_eth_dev *dev,
7474          enum rte_eth_tunnel_type l2_tunnel_type)
7475 {
7476         struct ixgbe_l2_tn_info *l2_tn_info =
7477                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7478         int ret = 0;
7479
7480         switch (l2_tunnel_type) {
7481         case RTE_L2_TUNNEL_TYPE_E_TAG:
7482                 l2_tn_info->e_tag_fwd_en = TRUE;
7483                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7484                 break;
7485         default:
7486                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7487                 ret = -EINVAL;
7488                 break;
7489         }
7490
7491         return ret;
7492 }
7493
7494 /* Disable l2 tunnel forwarding */
7495 static int
7496 ixgbe_dev_l2_tunnel_forwarding_disable
7497         (struct rte_eth_dev *dev,
7498          enum rte_eth_tunnel_type l2_tunnel_type)
7499 {
7500         struct ixgbe_l2_tn_info *l2_tn_info =
7501                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7502         int ret = 0;
7503
7504         switch (l2_tunnel_type) {
7505         case RTE_L2_TUNNEL_TYPE_E_TAG:
7506                 l2_tn_info->e_tag_fwd_en = FALSE;
7507                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7508                 break;
7509         default:
7510                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7511                 ret = -EINVAL;
7512                 break;
7513         }
7514
7515         return ret;
7516 }
7517
7518 static int
7519 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7520                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7521                              bool en)
7522 {
7523         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7524         int ret = 0;
7525         uint32_t vmtir, vmvir;
7526         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7527
7528         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7529                 PMD_DRV_LOG(ERR,
7530                             "VF id %u should be less than %u",
7531                             l2_tunnel->vf_id,
7532                             pci_dev->max_vfs);
7533                 return -EINVAL;
7534         }
7535
7536         if (hw->mac.type != ixgbe_mac_X550 &&
7537             hw->mac.type != ixgbe_mac_X550EM_x &&
7538             hw->mac.type != ixgbe_mac_X550EM_a) {
7539                 return -ENOTSUP;
7540         }
7541
7542         if (en)
7543                 vmtir = l2_tunnel->tunnel_id;
7544         else
7545                 vmtir = 0;
7546
7547         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7548
7549         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7550         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7551         if (en)
7552                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7553         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7554
7555         return ret;
7556 }
7557
7558 /* Enable l2 tunnel tag insertion */
7559 static int
7560 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7561                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7562 {
7563         int ret = 0;
7564
7565         switch (l2_tunnel->l2_tunnel_type) {
7566         case RTE_L2_TUNNEL_TYPE_E_TAG:
7567                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7568                 break;
7569         default:
7570                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7571                 ret = -EINVAL;
7572                 break;
7573         }
7574
7575         return ret;
7576 }
7577
7578 /* Disable l2 tunnel tag insertion */
7579 static int
7580 ixgbe_dev_l2_tunnel_insertion_disable
7581         (struct rte_eth_dev *dev,
7582          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7583 {
7584         int ret = 0;
7585
7586         switch (l2_tunnel->l2_tunnel_type) {
7587         case RTE_L2_TUNNEL_TYPE_E_TAG:
7588                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7589                 break;
7590         default:
7591                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7592                 ret = -EINVAL;
7593                 break;
7594         }
7595
7596         return ret;
7597 }
7598
7599 static int
7600 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7601                              bool en)
7602 {
7603         int ret = 0;
7604         uint32_t qde;
7605         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7606
7607         if (hw->mac.type != ixgbe_mac_X550 &&
7608             hw->mac.type != ixgbe_mac_X550EM_x &&
7609             hw->mac.type != ixgbe_mac_X550EM_a) {
7610                 return -ENOTSUP;
7611         }
7612
7613         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7614         if (en)
7615                 qde |= IXGBE_QDE_STRIP_TAG;
7616         else
7617                 qde &= ~IXGBE_QDE_STRIP_TAG;
7618         qde &= ~IXGBE_QDE_READ;
7619         qde |= IXGBE_QDE_WRITE;
7620         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7621
7622         return ret;
7623 }
7624
7625 /* Enable l2 tunnel tag stripping */
7626 static int
7627 ixgbe_dev_l2_tunnel_stripping_enable
7628         (struct rte_eth_dev *dev,
7629          enum rte_eth_tunnel_type l2_tunnel_type)
7630 {
7631         int ret = 0;
7632
7633         switch (l2_tunnel_type) {
7634         case RTE_L2_TUNNEL_TYPE_E_TAG:
7635                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7636                 break;
7637         default:
7638                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7639                 ret = -EINVAL;
7640                 break;
7641         }
7642
7643         return ret;
7644 }
7645
7646 /* Disable l2 tunnel tag stripping */
7647 static int
7648 ixgbe_dev_l2_tunnel_stripping_disable
7649         (struct rte_eth_dev *dev,
7650          enum rte_eth_tunnel_type l2_tunnel_type)
7651 {
7652         int ret = 0;
7653
7654         switch (l2_tunnel_type) {
7655         case RTE_L2_TUNNEL_TYPE_E_TAG:
7656                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7657                 break;
7658         default:
7659                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7660                 ret = -EINVAL;
7661                 break;
7662         }
7663
7664         return ret;
7665 }
7666
7667 /* Enable/disable l2 tunnel offload functions */
7668 static int
7669 ixgbe_dev_l2_tunnel_offload_set
7670         (struct rte_eth_dev *dev,
7671          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7672          uint32_t mask,
7673          uint8_t en)
7674 {
7675         int ret = 0;
7676
7677         if (l2_tunnel == NULL)
7678                 return -EINVAL;
7679
7680         ret = -EINVAL;
7681         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7682                 if (en)
7683                         ret = ixgbe_dev_l2_tunnel_enable(
7684                                 dev,
7685                                 l2_tunnel->l2_tunnel_type);
7686                 else
7687                         ret = ixgbe_dev_l2_tunnel_disable(
7688                                 dev,
7689                                 l2_tunnel->l2_tunnel_type);
7690         }
7691
7692         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7693                 if (en)
7694                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7695                                 dev,
7696                                 l2_tunnel);
7697                 else
7698                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7699                                 dev,
7700                                 l2_tunnel);
7701         }
7702
7703         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7704                 if (en)
7705                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7706                                 dev,
7707                                 l2_tunnel->l2_tunnel_type);
7708                 else
7709                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7710                                 dev,
7711                                 l2_tunnel->l2_tunnel_type);
7712         }
7713
7714         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7715                 if (en)
7716                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7717                                 dev,
7718                                 l2_tunnel->l2_tunnel_type);
7719                 else
7720                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7721                                 dev,
7722                                 l2_tunnel->l2_tunnel_type);
7723         }
7724
7725         return ret;
7726 }
7727
7728 static int
7729 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7730                         uint16_t port)
7731 {
7732         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7733         IXGBE_WRITE_FLUSH(hw);
7734
7735         return 0;
7736 }
7737
7738 /* There's only one register for VxLAN UDP port.
7739  * So, we cannot add several ports. Will update it.
7740  */
7741 static int
7742 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7743                      uint16_t port)
7744 {
7745         if (port == 0) {
7746                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7747                 return -EINVAL;
7748         }
7749
7750         return ixgbe_update_vxlan_port(hw, port);
7751 }
7752
7753 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7754  * UDP port, it must have a value.
7755  * So, will reset it to the original value 0.
7756  */
7757 static int
7758 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7759                      uint16_t port)
7760 {
7761         uint16_t cur_port;
7762
7763         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7764
7765         if (cur_port != port) {
7766                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7767                 return -EINVAL;
7768         }
7769
7770         return ixgbe_update_vxlan_port(hw, 0);
7771 }
7772
7773 /* Add UDP tunneling port */
7774 static int
7775 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7776                               struct rte_eth_udp_tunnel *udp_tunnel)
7777 {
7778         int ret = 0;
7779         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7780
7781         if (hw->mac.type != ixgbe_mac_X550 &&
7782             hw->mac.type != ixgbe_mac_X550EM_x &&
7783             hw->mac.type != ixgbe_mac_X550EM_a) {
7784                 return -ENOTSUP;
7785         }
7786
7787         if (udp_tunnel == NULL)
7788                 return -EINVAL;
7789
7790         switch (udp_tunnel->prot_type) {
7791         case RTE_TUNNEL_TYPE_VXLAN:
7792                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7793                 break;
7794
7795         case RTE_TUNNEL_TYPE_GENEVE:
7796         case RTE_TUNNEL_TYPE_TEREDO:
7797                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7798                 ret = -EINVAL;
7799                 break;
7800
7801         default:
7802                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7803                 ret = -EINVAL;
7804                 break;
7805         }
7806
7807         return ret;
7808 }
7809
7810 /* Remove UDP tunneling port */
7811 static int
7812 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7813                               struct rte_eth_udp_tunnel *udp_tunnel)
7814 {
7815         int ret = 0;
7816         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7817
7818         if (hw->mac.type != ixgbe_mac_X550 &&
7819             hw->mac.type != ixgbe_mac_X550EM_x &&
7820             hw->mac.type != ixgbe_mac_X550EM_a) {
7821                 return -ENOTSUP;
7822         }
7823
7824         if (udp_tunnel == NULL)
7825                 return -EINVAL;
7826
7827         switch (udp_tunnel->prot_type) {
7828         case RTE_TUNNEL_TYPE_VXLAN:
7829                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7830                 break;
7831         case RTE_TUNNEL_TYPE_GENEVE:
7832         case RTE_TUNNEL_TYPE_TEREDO:
7833                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7834                 ret = -EINVAL;
7835                 break;
7836         default:
7837                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7838                 ret = -EINVAL;
7839                 break;
7840         }
7841
7842         return ret;
7843 }
7844
7845 static void
7846 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7847 {
7848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7849
7850         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7851 }
7852
7853 static void
7854 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7855 {
7856         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7857
7858         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
7859 }
7860
7861 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7862 {
7863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7864         u32 in_msg = 0;
7865
7866         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7867                 return;
7868
7869         /* PF reset VF event */
7870         if (in_msg == IXGBE_PF_CONTROL_MSG)
7871                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7872 }
7873
7874 static int
7875 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7876 {
7877         uint32_t eicr;
7878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7879         struct ixgbe_interrupt *intr =
7880                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7881         ixgbevf_intr_disable(hw);
7882
7883         /* read-on-clear nic registers here */
7884         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7885         intr->flags = 0;
7886
7887         /* only one misc vector supported - mailbox */
7888         eicr &= IXGBE_VTEICR_MASK;
7889         if (eicr == IXGBE_MISC_VEC_ID)
7890                 intr->flags |= IXGBE_FLAG_MAILBOX;
7891
7892         return 0;
7893 }
7894
7895 static int
7896 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7897 {
7898         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7899         struct ixgbe_interrupt *intr =
7900                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7901
7902         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7903                 ixgbevf_mbx_process(dev);
7904                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7905         }
7906
7907         ixgbevf_intr_enable(hw);
7908
7909         return 0;
7910 }
7911
7912 static void
7913 ixgbevf_dev_interrupt_handler(void *param)
7914 {
7915         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7916
7917         ixgbevf_dev_interrupt_get_status(dev);
7918         ixgbevf_dev_interrupt_action(dev);
7919 }
7920
7921 /**
7922  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7923  *  @hw: pointer to hardware structure
7924  *
7925  *  Stops the transmit data path and waits for the HW to internally empty
7926  *  the Tx security block
7927  **/
7928 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7929 {
7930 #define IXGBE_MAX_SECTX_POLL 40
7931
7932         int i;
7933         int sectxreg;
7934
7935         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7936         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7937         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7938         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7939                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7940                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7941                         break;
7942                 /* Use interrupt-safe sleep just in case */
7943                 usec_delay(1000);
7944         }
7945
7946         /* For informational purposes only */
7947         if (i >= IXGBE_MAX_SECTX_POLL)
7948                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7949                          "path fully disabled.  Continuing with init.");
7950
7951         return IXGBE_SUCCESS;
7952 }
7953
7954 /**
7955  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7956  *  @hw: pointer to hardware structure
7957  *
7958  *  Enables the transmit data path.
7959  **/
7960 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7961 {
7962         uint32_t sectxreg;
7963
7964         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7965         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7966         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7967         IXGBE_WRITE_FLUSH(hw);
7968
7969         return IXGBE_SUCCESS;
7970 }
7971
7972 /* restore n-tuple filter */
7973 static inline void
7974 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
7975 {
7976         struct ixgbe_filter_info *filter_info =
7977                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7978         struct ixgbe_5tuple_filter *node;
7979
7980         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
7981                 ixgbe_inject_5tuple_filter(dev, node);
7982         }
7983 }
7984
7985 /* restore ethernet type filter */
7986 static inline void
7987 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
7988 {
7989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7990         struct ixgbe_filter_info *filter_info =
7991                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7992         int i;
7993
7994         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
7995                 if (filter_info->ethertype_mask & (1 << i)) {
7996                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
7997                                         filter_info->ethertype_filters[i].etqf);
7998                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
7999                                         filter_info->ethertype_filters[i].etqs);
8000                         IXGBE_WRITE_FLUSH(hw);
8001                 }
8002         }
8003 }
8004
8005 /* restore SYN filter */
8006 static inline void
8007 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8008 {
8009         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8010         struct ixgbe_filter_info *filter_info =
8011                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8012         uint32_t synqf;
8013
8014         synqf = filter_info->syn_info;
8015
8016         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8017                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8018                 IXGBE_WRITE_FLUSH(hw);
8019         }
8020 }
8021
8022 /* restore L2 tunnel filter */
8023 static inline void
8024 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8025 {
8026         struct ixgbe_l2_tn_info *l2_tn_info =
8027                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8028         struct ixgbe_l2_tn_filter *node;
8029         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8030
8031         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8032                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8033                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8034                 l2_tn_conf.pool           = node->pool;
8035                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8036         }
8037 }
8038
8039 static int
8040 ixgbe_filter_restore(struct rte_eth_dev *dev)
8041 {
8042         ixgbe_ntuple_filter_restore(dev);
8043         ixgbe_ethertype_filter_restore(dev);
8044         ixgbe_syn_filter_restore(dev);
8045         ixgbe_fdir_filter_restore(dev);
8046         ixgbe_l2_tn_filter_restore(dev);
8047
8048         return 0;
8049 }
8050
8051 static void
8052 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8053 {
8054         struct ixgbe_l2_tn_info *l2_tn_info =
8055                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8057
8058         if (l2_tn_info->e_tag_en)
8059                 (void)ixgbe_e_tag_enable(hw);
8060
8061         if (l2_tn_info->e_tag_fwd_en)
8062                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8063
8064         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8065 }
8066
8067 /* remove all the n-tuple filters */
8068 void
8069 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8070 {
8071         struct ixgbe_filter_info *filter_info =
8072                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8073         struct ixgbe_5tuple_filter *p_5tuple;
8074
8075         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8076                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8077 }
8078
8079 /* remove all the ether type filters */
8080 void
8081 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8082 {
8083         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8084         struct ixgbe_filter_info *filter_info =
8085                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8086         int i;
8087
8088         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8089                 if (filter_info->ethertype_mask & (1 << i) &&
8090                     !filter_info->ethertype_filters[i].conf) {
8091                         (void)ixgbe_ethertype_filter_remove(filter_info,
8092                                                             (uint8_t)i);
8093                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8094                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8095                         IXGBE_WRITE_FLUSH(hw);
8096                 }
8097         }
8098 }
8099
8100 /* remove the SYN filter */
8101 void
8102 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8103 {
8104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8105         struct ixgbe_filter_info *filter_info =
8106                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8107
8108         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8109                 filter_info->syn_info = 0;
8110
8111                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8112                 IXGBE_WRITE_FLUSH(hw);
8113         }
8114 }
8115
8116 /* remove all the L2 tunnel filters */
8117 int
8118 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8119 {
8120         struct ixgbe_l2_tn_info *l2_tn_info =
8121                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8122         struct ixgbe_l2_tn_filter *l2_tn_filter;
8123         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8124         int ret = 0;
8125
8126         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8127                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8128                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8129                 l2_tn_conf.pool           = l2_tn_filter->pool;
8130                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8131                 if (ret < 0)
8132                         return ret;
8133         }
8134
8135         return 0;
8136 }
8137
8138 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8139 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8140 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8141 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8142 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8143 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");