drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 enum ixgbevf_xcast_modes {
 158         IXGBEVF_XCAST_MODE_NONE = 0,
 159         IXGBEVF_XCAST_MODE_MULTI,
 160         IXGBEVF_XCAST_MODE_ALLMULTI,
 161 };
 162
 163 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 164 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 165
 166 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 167 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 197                                struct rte_eth_dev_info *dev_info);
 198 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 199 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 200                                  struct rte_eth_dev_info *dev_info);
 201 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 202
 203 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 204                 uint16_t vlan_id, int on);
 205 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 206                                enum rte_vlan_type vlan_type,
 207                                uint16_t tpid_id);
 208 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 209                 uint16_t queue, bool on);
 210 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 211                 int on);
 212 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 213 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 214 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 215 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 216 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 217
 218 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 220 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 221                                struct rte_eth_fc_conf *fc_conf);
 222 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 225                 struct rte_eth_pfc_conf *pfc_conf);
 226 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 227                         struct rte_eth_rss_reta_entry64 *reta_conf,
 228                         uint16_t reta_size);
 229 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 230                         struct rte_eth_rss_reta_entry64 *reta_conf,
 231                         uint16_t reta_size);
 232 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 233 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 237                                       struct rte_intr_handle *handle);
 238 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 239                 void *param);
 240 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 241 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 242                 uint32_t index, uint32_t pool);
 243 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 244 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 245                                            struct ether_addr *mac_addr);
 246 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 247
 248 /* For Virtual Function support */
 249 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 250 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 251 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 252 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 256 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 257 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 258                 struct rte_eth_stats *stats);
 259 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 260 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 261                 uint16_t vlan_id, int on);
 262 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 263                 uint16_t queue, int on);
 264 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id);
 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 269                                              uint16_t queue_id);
 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 271                                  uint8_t queue, uint8_t msix_vector);
 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 273 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 274 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 275
 276 /* For Eth VMDQ APIs support */
 277 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 278                 ether_addr * mac_addr, uint8_t on);
 279 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 280 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 281                 uint16_t rx_mask, uint8_t on);
 282 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 283 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 284 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 285                 uint64_t pool_mask, uint8_t vlan_on);
 286 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 287                 struct rte_eth_mirror_conf *mirror_conf,
 288                 uint8_t rule_id, uint8_t on);
 289 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 290                 uint8_t rule_id);
 291 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 292                                           uint16_t queue_id);
 293 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 294                                            uint16_t queue_id);
 295 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 296                                uint8_t queue, uint8_t msix_vector);
 297 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 298
 299 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 300                 uint16_t queue_idx, uint16_t tx_rate);
 301 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 302                 uint16_t tx_rate, uint64_t q_msk);
 303
 304 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 305                                  struct ether_addr *mac_addr,
 306                                  uint32_t index, uint32_t pool);
 307 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 308 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 309                                              struct ether_addr *mac_addr);
 310 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 311                         struct rte_eth_syn_filter *filter,
 312                         bool add);
 313 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 314                         struct rte_eth_syn_filter *filter);
 315 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 316                         enum rte_filter_op filter_op,
 317                         void *arg);
 318 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 319                         struct ixgbe_5tuple_filter *filter);
 320 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 321                         struct ixgbe_5tuple_filter *filter);
 322 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 323                         struct rte_eth_ntuple_filter *filter,
 324                         bool add);
 325 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 326                                 enum rte_filter_op filter_op,
 327                                 void *arg);
 328 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 329                         struct rte_eth_ntuple_filter *filter);
 330 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 331                         struct rte_eth_ethertype_filter *filter,
 332                         bool add);
 333 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 334                                 enum rte_filter_op filter_op,
 335                                 void *arg);
 336 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 337                         struct rte_eth_ethertype_filter *filter);
 338 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 339                      enum rte_filter_type filter_type,
 340                      enum rte_filter_op filter_op,
 341                      void *arg);
 342 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 343
 344 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 345                                       struct ether_addr *mc_addr_set,
 346                                       uint32_t nb_mc_addr);
 347 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 348                                    struct rte_eth_dcb_info *dcb_info);
 349
 350 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 351 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 352                             struct rte_dev_reg_info *regs);
 353 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 354 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 355                                 struct rte_dev_eeprom_info *eeprom);
 356 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 357                                 struct rte_dev_eeprom_info *eeprom);
 358
 359 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 360 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 361                                 struct rte_dev_reg_info *regs);
 362
 363 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 364 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 365 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 366                                             struct timespec *timestamp,
 367                                             uint32_t flags);
 368 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 369                                             struct timespec *timestamp);
 370 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 371 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 372                                    struct timespec *timestamp);
 373 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 374                                    const struct timespec *timestamp);
 375 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 376                                           void *param);
 377
 378 static int ixgbe_dev_l2_tunnel_eth_type_conf
 379         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 380 static int ixgbe_dev_l2_tunnel_offload_set
 381         (struct rte_eth_dev *dev,
 382          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 383          uint32_t mask,
 384          uint8_t en);
 385 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 386                                              enum rte_filter_op filter_op,
 387                                              void *arg);
 388
 389 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 390                                          struct rte_eth_udp_tunnel *udp_tunnel);
 391 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 392                                          struct rte_eth_udp_tunnel *udp_tunnel);
 393
 394 /*
 395  * Define VF Stats MACRO for Non "cleared on read" register
 396  */
 397 #define UPDATE_VF_STAT(reg, last, cur)                          \
 398 {                                                               \
 399         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 400         cur += (latest - last) & UINT_MAX;                      \
 401         last = latest;                                          \
 402 }
 403
 404 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 405 {                                                                \
 406         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 407         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 408         u64 latest = ((new_msb << 32) | new_lsb);                \
 409         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 410         last = latest;                                           \
 411 }
 412
 413 #define IXGBE_SET_HWSTRIP(h, q) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (h)->bitmap[idx] |= 1 << bit;\
 417         } while (0)
 418
 419 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 420                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 421                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 422                 (h)->bitmap[idx] &= ~(1 << bit);\
 423         } while (0)
 424
 425 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 426                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 427                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 428                 (r) = (h)->bitmap[idx] >> bit & 1;\
 429         } while (0)
 430
 431 /*
 432  * The set of PCI devices this driver supports
 433  */
 434 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 488 #ifdef RTE_NIC_BYPASS
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 490 #endif
 491         { .vendor_id = 0, /* sentinel */ },
 492 };
 493
 494 /*
 495  * The set of PCI devices this driver supports (for 82599 VF)
 496  */
 497 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 507         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 508         { .vendor_id = 0, /* sentinel */ },
 509 };
 510
 511 static const struct rte_eth_desc_lim rx_desc_lim = {
 512         .nb_max = IXGBE_MAX_RING_DESC,
 513         .nb_min = IXGBE_MIN_RING_DESC,
 514         .nb_align = IXGBE_RXD_ALIGN,
 515 };
 516
 517 static const struct rte_eth_desc_lim tx_desc_lim = {
 518         .nb_max = IXGBE_MAX_RING_DESC,
 519         .nb_min = IXGBE_MIN_RING_DESC,
 520         .nb_align = IXGBE_TXD_ALIGN,
 521 };
 522
 523 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 524         .dev_configure        = ixgbe_dev_configure,
 525         .dev_start            = ixgbe_dev_start,
 526         .dev_stop             = ixgbe_dev_stop,
 527         .dev_set_link_up    = ixgbe_dev_set_link_up,
 528         .dev_set_link_down  = ixgbe_dev_set_link_down,
 529         .dev_close            = ixgbe_dev_close,
 530         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 531         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 532         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 533         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 534         .link_update          = ixgbe_dev_link_update,
 535         .stats_get            = ixgbe_dev_stats_get,
 536         .xstats_get           = ixgbe_dev_xstats_get,
 537         .stats_reset          = ixgbe_dev_stats_reset,
 538         .xstats_reset         = ixgbe_dev_xstats_reset,
 539         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 540         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 541         .dev_infos_get        = ixgbe_dev_info_get,
 542         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 543         .mtu_set              = ixgbe_dev_mtu_set,
 544         .vlan_filter_set      = ixgbe_vlan_filter_set,
 545         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 546         .vlan_offload_set     = ixgbe_vlan_offload_set,
 547         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 548         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 549         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 550         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 551         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 552         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 553         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 554         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 555         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 556         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 557         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 558         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 559         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 560         .dev_led_on           = ixgbe_dev_led_on,
 561         .dev_led_off          = ixgbe_dev_led_off,
 562         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 563         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 564         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 565         .mac_addr_add         = ixgbe_add_rar,
 566         .mac_addr_remove      = ixgbe_remove_rar,
 567         .mac_addr_set         = ixgbe_set_default_mac_addr,
 568         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 569         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 570         .mirror_rule_set      = ixgbe_mirror_rule_set,
 571         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 572         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 573         .set_vf_rx            = ixgbe_set_pool_rx,
 574         .set_vf_tx            = ixgbe_set_pool_tx,
 575         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 576         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 577         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 578         .reta_update          = ixgbe_dev_rss_reta_update,
 579         .reta_query           = ixgbe_dev_rss_reta_query,
 580 #ifdef RTE_NIC_BYPASS
 581         .bypass_init          = ixgbe_bypass_init,
 582         .bypass_state_set     = ixgbe_bypass_state_store,
 583         .bypass_state_show    = ixgbe_bypass_state_show,
 584         .bypass_event_set     = ixgbe_bypass_event_store,
 585         .bypass_event_show    = ixgbe_bypass_event_show,
 586         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 587         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 588         .bypass_ver_show      = ixgbe_bypass_ver_show,
 589         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 590 #endif /* RTE_NIC_BYPASS */
 591         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 592         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 593         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 594         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 595         .rxq_info_get         = ixgbe_rxq_info_get,
 596         .txq_info_get         = ixgbe_txq_info_get,
 597         .timesync_enable      = ixgbe_timesync_enable,
 598         .timesync_disable     = ixgbe_timesync_disable,
 599         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 600         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 601         .get_reg              = ixgbe_get_regs,
 602         .get_eeprom_length    = ixgbe_get_eeprom_length,
 603         .get_eeprom           = ixgbe_get_eeprom,
 604         .set_eeprom           = ixgbe_set_eeprom,
 605         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 606         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 607         .timesync_read_time   = ixgbe_timesync_read_time,
 608         .timesync_write_time  = ixgbe_timesync_write_time,
 609         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 610         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 611         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 612         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 613 };
 614
 615 /*
 616  * dev_ops for virtual function, bare necessities for basic vf
 617  * operation have been implemented
 618  */
 619 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 620         .dev_configure        = ixgbevf_dev_configure,
 621         .dev_start            = ixgbevf_dev_start,
 622         .dev_stop             = ixgbevf_dev_stop,
 623         .link_update          = ixgbe_dev_link_update,
 624         .stats_get            = ixgbevf_dev_stats_get,
 625         .xstats_get           = ixgbevf_dev_xstats_get,
 626         .stats_reset          = ixgbevf_dev_stats_reset,
 627         .xstats_reset         = ixgbevf_dev_stats_reset,
 628         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 629         .dev_close            = ixgbevf_dev_close,
 630         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 631         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 632         .dev_infos_get        = ixgbevf_dev_info_get,
 633         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 634         .mtu_set              = ixgbevf_dev_set_mtu,
 635         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 636         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 637         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 638         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 639         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 640         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 641         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 642         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 643         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 644         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 645         .mac_addr_add         = ixgbevf_add_mac_addr,
 646         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 647         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 648         .rxq_info_get         = ixgbe_rxq_info_get,
 649         .txq_info_get         = ixgbe_txq_info_get,
 650         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 651         .get_reg              = ixgbevf_get_regs,
 652         .reta_update          = ixgbe_dev_rss_reta_update,
 653         .reta_query           = ixgbe_dev_rss_reta_query,
 654         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 655         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 656 };
 657
 658 /* store statistics names and its offset in stats structure */
 659 struct rte_ixgbe_xstats_name_off {
 660         char name[RTE_ETH_XSTATS_NAME_SIZE];
 661         unsigned offset;
 662 };
 663
 664 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 665         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 666         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 667         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 668         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 669         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 670         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 671         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 672         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 673         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 674         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 675         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 676         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 677         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 678         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 679         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 680                 prc1023)},
 681         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 682                 prc1522)},
 683         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 684         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 685         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 686         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 687         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 688         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 689         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 690         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 691         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 692         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 693         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 694         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 695         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 696         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 697         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 698         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 699         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 700                 ptc1023)},
 701         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 702                 ptc1522)},
 703         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 704         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 705         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 706         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 707
 708         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 709                 fdirustat_add)},
 710         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirustat_remove)},
 712         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 713                 fdirfstat_fadd)},
 714         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 715                 fdirfstat_fremove)},
 716         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 717                 fdirmatch)},
 718         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 719                 fdirmiss)},
 720
 721         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 722         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 723         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 724                 fclast)},
 725         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 726         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 727         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 728         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 729         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 730                 fcoe_noddp)},
 731         {"rx_fcoe_no_direct_data_placement_ext_buff",
 732                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 733
 734         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 735                 lxontxc)},
 736         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxonrxc)},
 738         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 739                 lxofftxc)},
 740         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxoffrxc)},
 742         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 743 };
 744
 745 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 746                            sizeof(rte_ixgbe_stats_strings[0]))
 747
 748 /* Per-queue statistics */
 749 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 750         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 751         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 752         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 753         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 754 };
 755
 756 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 757                            sizeof(rte_ixgbe_rxq_strings[0]))
 758 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 759
 760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 761         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 762         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 763         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 764                 pxon2offc)},
 765 };
 766
 767 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 768                            sizeof(rte_ixgbe_txq_strings[0]))
 769 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 770
 771 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 772         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 773 };
 774
 775 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 776                 sizeof(rte_ixgbevf_stats_strings[0]))
 777
 778 /**
 779  * Atomically reads the link status information from global
 780  * structure rte_eth_dev.
 781  *
 782  * @param dev
 783  *   - Pointer to the structure rte_eth_dev to read from.
 784  *   - Pointer to the buffer to be saved with the link status.
 785  *
 786  * @return
 787  *   - On success, zero.
 788  *   - On failure, negative value.
 789  */
 790 static inline int
 791 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 792                                 struct rte_eth_link *link)
 793 {
 794         struct rte_eth_link *dst = link;
 795         struct rte_eth_link *src = &(dev->data->dev_link);
 796
 797         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 798                                         *(uint64_t *)src) == 0)
 799                 return -1;
 800
 801         return 0;
 802 }
 803
 804 /**
 805  * Atomically writes the link status information into global
 806  * structure rte_eth_dev.
 807  *
 808  * @param dev
 809  *   - Pointer to the structure rte_eth_dev to read from.
 810  *   - Pointer to the buffer to be saved with the link status.
 811  *
 812  * @return
 813  *   - On success, zero.
 814  *   - On failure, negative value.
 815  */
 816 static inline int
 817 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 818                                 struct rte_eth_link *link)
 819 {
 820         struct rte_eth_link *dst = &(dev->data->dev_link);
 821         struct rte_eth_link *src = link;
 822
 823         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 824                                         *(uint64_t *)src) == 0)
 825                 return -1;
 826
 827         return 0;
 828 }
 829
 830 /*
 831  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 832  */
 833 static inline int
 834 ixgbe_is_sfp(struct ixgbe_hw *hw)
 835 {
 836         switch (hw->phy.type) {
 837         case ixgbe_phy_sfp_avago:
 838         case ixgbe_phy_sfp_ftl:
 839         case ixgbe_phy_sfp_intel:
 840         case ixgbe_phy_sfp_unknown:
 841         case ixgbe_phy_sfp_passive_tyco:
 842         case ixgbe_phy_sfp_passive_unknown:
 843                 return 1;
 844         default:
 845                 return 0;
 846         }
 847 }
 848
 849 static inline int32_t
 850 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 851 {
 852         uint32_t ctrl_ext;
 853         int32_t status;
 854
 855         status = ixgbe_reset_hw(hw);
 856
 857         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 858         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 859         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 860         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 861         IXGBE_WRITE_FLUSH(hw);
 862
 863         return status;
 864 }
 865
 866 static inline void
 867 ixgbe_enable_intr(struct rte_eth_dev *dev)
 868 {
 869         struct ixgbe_interrupt *intr =
 870                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 871         struct ixgbe_hw *hw =
 872                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 873
 874         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 875         IXGBE_WRITE_FLUSH(hw);
 876 }
 877
 878 /*
 879  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 880  */
 881 static void
 882 ixgbe_disable_intr(struct ixgbe_hw *hw)
 883 {
 884         PMD_INIT_FUNC_TRACE();
 885
 886         if (hw->mac.type == ixgbe_mac_82598EB) {
 887                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 888         } else {
 889                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 890                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 891                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 892         }
 893         IXGBE_WRITE_FLUSH(hw);
 894 }
 895
 896 /*
 897  * This function resets queue statistics mapping registers.
 898  * From Niantic datasheet, Initialization of Statistics section:
 899  * "...if software requires the queue counters, the RQSMR and TQSM registers
 900  * must be re-programmed following a device reset.
 901  */
 902 static void
 903 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 904 {
 905         uint32_t i;
 906
 907         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 908                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 909                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 910         }
 911 }
 912
 913
 914 static int
 915 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 916                                   uint16_t queue_id,
 917                                   uint8_t stat_idx,
 918                                   uint8_t is_rx)
 919 {
 920 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 921 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 922 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 923
 924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 925         struct ixgbe_stat_mapping_registers *stat_mappings =
 926                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 927         uint32_t qsmr_mask = 0;
 928         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 929         uint32_t q_map;
 930         uint8_t n, offset;
 931
 932         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 933                 (hw->mac.type != ixgbe_mac_X540) &&
 934                 (hw->mac.type != ixgbe_mac_X550) &&
 935                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 936                 (hw->mac.type != ixgbe_mac_X550EM_a))
 937                 return -ENOSYS;
 938
 939         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 940                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 941                      queue_id, stat_idx);
 942
 943         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 944         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 945                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 946                 return -EIO;
 947         }
 948         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 949
 950         /* Now clear any previous stat_idx set */
 951         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 952         if (!is_rx)
 953                 stat_mappings->tqsm[n] &= ~clearing_mask;
 954         else
 955                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 956
 957         q_map = (uint32_t)stat_idx;
 958         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 959         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 960         if (!is_rx)
 961                 stat_mappings->tqsm[n] |= qsmr_mask;
 962         else
 963                 stat_mappings->rqsmr[n] |= qsmr_mask;
 964
 965         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 966                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 967                      queue_id, stat_idx);
 968         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 969                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 970
 971         /* Now write the mapping in the appropriate register */
 972         if (is_rx) {
 973                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 974                              stat_mappings->rqsmr[n], n);
 975                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 976         } else {
 977                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 978                              stat_mappings->tqsm[n], n);
 979                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 980         }
 981         return 0;
 982 }
 983
 984 static void
 985 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 986 {
 987         struct ixgbe_stat_mapping_registers *stat_mappings =
 988                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 990         int i;
 991
 992         /* write whatever was in stat mapping table to the NIC */
 993         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 994                 /* rx */
 995                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 996
 997                 /* tx */
 998                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 999         }
1000 }
1001
1002 static void
1003 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1004 {
1005         uint8_t i;
1006         struct ixgbe_dcb_tc_config *tc;
1007         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1008
1009         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1010         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1011         for (i = 0; i < dcb_max_tc; i++) {
1012                 tc = &dcb_config->tc_config[i];
1013                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1014                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1015                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1016                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1017                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1018                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1019                 tc->pfc = ixgbe_dcb_pfc_disabled;
1020         }
1021
1022         /* Initialize default user to priority mapping, UPx->TC0 */
1023         tc = &dcb_config->tc_config[0];
1024         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1025         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1026         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1027                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1028                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1029         }
1030         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1031         dcb_config->pfc_mode_enable = false;
1032         dcb_config->vt_mode = true;
1033         dcb_config->round_robin_enable = false;
1034         /* support all DCB capabilities in 82599 */
1035         dcb_config->support.capabilities = 0xFF;
1036
1037         /*we only support 4 Tcs for X540, X550 */
1038         if (hw->mac.type == ixgbe_mac_X540 ||
1039                 hw->mac.type == ixgbe_mac_X550 ||
1040                 hw->mac.type == ixgbe_mac_X550EM_x ||
1041                 hw->mac.type == ixgbe_mac_X550EM_a) {
1042                 dcb_config->num_tcs.pg_tcs = 4;
1043                 dcb_config->num_tcs.pfc_tcs = 4;
1044         }
1045 }
1046
1047 /*
1048  * Ensure that all locks are released before first NVM or PHY access
1049  */
1050 static void
1051 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1052 {
1053         uint16_t mask;
1054
1055         /*
1056          * Phy lock should not fail in this early stage. If this is the case,
1057          * it is due to an improper exit of the application.
1058          * So force the release of the faulty lock. Release of common lock
1059          * is done automatically by swfw_sync function.
1060          */
1061         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1062         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1063                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1064         }
1065         ixgbe_release_swfw_semaphore(hw, mask);
1066
1067         /*
1068          * These ones are more tricky since they are common to all ports; but
1069          * swfw_sync retries last long enough (1s) to be almost sure that if
1070          * lock can not be taken it is due to an improper lock of the
1071          * semaphore.
1072          */
1073         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1074         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1075                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1076         }
1077         ixgbe_release_swfw_semaphore(hw, mask);
1078 }
1079
1080 /*
1081  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1082  * It returns 0 on success.
1083  */
1084 static int
1085 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1086 {
1087         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1088         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1089         struct ixgbe_hw *hw =
1090                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1091         struct ixgbe_vfta *shadow_vfta =
1092                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1093         struct ixgbe_hwstrip *hwstrip =
1094                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1095         struct ixgbe_dcb_config *dcb_config =
1096                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1097         struct ixgbe_filter_info *filter_info =
1098                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1099         uint32_t ctrl_ext;
1100         uint16_t csum;
1101         int diag, i;
1102
1103         PMD_INIT_FUNC_TRACE();
1104
1105         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1106         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1107         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1108
1109         /*
1110          * For secondary processes, we don't initialise any further as primary
1111          * has already done this work. Only check we don't need a different
1112          * RX and TX function.
1113          */
1114         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1115                 struct ixgbe_tx_queue *txq;
1116                 /* TX queue function in primary, set by last queue initialized
1117                  * Tx queue may not initialized by primary process
1118                  */
1119                 if (eth_dev->data->tx_queues) {
1120                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1121                         ixgbe_set_tx_function(eth_dev, txq);
1122                 } else {
1123                         /* Use default TX function if we get here */
1124                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1125                                      "Using default TX function.");
1126                 }
1127
1128                 ixgbe_set_rx_function(eth_dev);
1129
1130                 return 0;
1131         }
1132
1133         rte_eth_copy_pci_info(eth_dev, pci_dev);
1134
1135         /* Vendor and Device ID need to be set before init of shared code */
1136         hw->device_id = pci_dev->id.device_id;
1137         hw->vendor_id = pci_dev->id.vendor_id;
1138         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1139         hw->allow_unsupported_sfp = 1;
1140
1141         /* Initialize the shared code (base driver) */
1142 #ifdef RTE_NIC_BYPASS
1143         diag = ixgbe_bypass_init_shared_code(hw);
1144 #else
1145         diag = ixgbe_init_shared_code(hw);
1146 #endif /* RTE_NIC_BYPASS */
1147
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1150                 return -EIO;
1151         }
1152
1153         /* pick up the PCI bus settings for reporting later */
1154         ixgbe_get_bus_info(hw);
1155
1156         /* Unlock any pending hardware semaphore */
1157         ixgbe_swfw_lock_reset(hw);
1158
1159         /* Initialize DCB configuration*/
1160         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1161         ixgbe_dcb_init(hw, dcb_config);
1162         /* Get Hardware Flow Control setting */
1163         hw->fc.requested_mode = ixgbe_fc_full;
1164         hw->fc.current_mode = ixgbe_fc_full;
1165         hw->fc.pause_time = IXGBE_FC_PAUSE;
1166         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1167                 hw->fc.low_water[i] = IXGBE_FC_LO;
1168                 hw->fc.high_water[i] = IXGBE_FC_HI;
1169         }
1170         hw->fc.send_xon = 1;
1171
1172         /* Make sure we have a good EEPROM before we read from it */
1173         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1174         if (diag != IXGBE_SUCCESS) {
1175                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1176                 return -EIO;
1177         }
1178
1179 #ifdef RTE_NIC_BYPASS
1180         diag = ixgbe_bypass_init_hw(hw);
1181 #else
1182         diag = ixgbe_init_hw(hw);
1183 #endif /* RTE_NIC_BYPASS */
1184
1185         /*
1186          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1187          * is called too soon after the kernel driver unbinding/binding occurs.
1188          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1189          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1190          * also called. See ixgbe_identify_phy_82599(). The reason for the
1191          * failure is not known, and only occuts when virtualisation features
1192          * are disabled in the bios. A delay of 100ms  was found to be enough by
1193          * trial-and-error, and is doubled to be safe.
1194          */
1195         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1196                 rte_delay_ms(200);
1197                 diag = ixgbe_init_hw(hw);
1198         }
1199
1200         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1201                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1202                              "LOM.  Please be aware there may be issues associated "
1203                              "with your hardware.");
1204                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1205                              "please contact your Intel or hardware representative "
1206                              "who provided you with this hardware.");
1207         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1208                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1209         if (diag) {
1210                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1211                 return -EIO;
1212         }
1213
1214         /* Reset the hw statistics */
1215         ixgbe_dev_stats_reset(eth_dev);
1216
1217         /* disable interrupt */
1218         ixgbe_disable_intr(hw);
1219
1220         /* reset mappings for queue statistics hw counters*/
1221         ixgbe_reset_qstat_mappings(hw);
1222
1223         /* Allocate memory for storing MAC addresses */
1224         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1225                                                hw->mac.num_rar_entries, 0);
1226         if (eth_dev->data->mac_addrs == NULL) {
1227                 PMD_INIT_LOG(ERR,
1228                              "Failed to allocate %u bytes needed to store "
1229                              "MAC addresses",
1230                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1231                 return -ENOMEM;
1232         }
1233         /* Copy the permanent MAC address */
1234         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1235                         &eth_dev->data->mac_addrs[0]);
1236
1237         /* Allocate memory for storing hash filter MAC addresses */
1238         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1239                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1240         if (eth_dev->data->hash_mac_addrs == NULL) {
1241                 PMD_INIT_LOG(ERR,
1242                              "Failed to allocate %d bytes needed to store MAC addresses",
1243                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1244                 return -ENOMEM;
1245         }
1246
1247         /* initialize the vfta */
1248         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1249
1250         /* initialize the hw strip bitmap*/
1251         memset(hwstrip, 0, sizeof(*hwstrip));
1252
1253         /* initialize PF if max_vfs not zero */
1254         ixgbe_pf_host_init(eth_dev);
1255
1256         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1257         /* let hardware know driver is loaded */
1258         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1259         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1260         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1261         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1262         IXGBE_WRITE_FLUSH(hw);
1263
1264         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1265                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1266                              (int) hw->mac.type, (int) hw->phy.type,
1267                              (int) hw->phy.sfp_type);
1268         else
1269                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1270                              (int) hw->mac.type, (int) hw->phy.type);
1271
1272         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1273                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1274                      pci_dev->id.device_id);
1275
1276         rte_intr_callback_register(intr_handle,
1277                                    ixgbe_dev_interrupt_handler, eth_dev);
1278
1279         /* enable uio/vfio intr/eventfd mapping */
1280         rte_intr_enable(intr_handle);
1281
1282         /* enable support intr */
1283         ixgbe_enable_intr(eth_dev);
1284
1285         /* initialize 5tuple filter list */
1286         TAILQ_INIT(&filter_info->fivetuple_list);
1287         memset(filter_info->fivetuple_mask, 0,
1288                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1289
1290         return 0;
1291 }
1292
1293 static int
1294 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1295 {
1296         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1297         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1298         struct ixgbe_hw *hw;
1299
1300         PMD_INIT_FUNC_TRACE();
1301
1302         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1303                 return -EPERM;
1304
1305         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1306
1307         if (hw->adapter_stopped == 0)
1308                 ixgbe_dev_close(eth_dev);
1309
1310         eth_dev->dev_ops = NULL;
1311         eth_dev->rx_pkt_burst = NULL;
1312         eth_dev->tx_pkt_burst = NULL;
1313
1314         /* Unlock any pending hardware semaphore */
1315         ixgbe_swfw_lock_reset(hw);
1316
1317         /* disable uio intr before callback unregister */
1318         rte_intr_disable(intr_handle);
1319         rte_intr_callback_unregister(intr_handle,
1320                                      ixgbe_dev_interrupt_handler, eth_dev);
1321
1322         /* uninitialize PF if max_vfs not zero */
1323         ixgbe_pf_host_uninit(eth_dev);
1324
1325         rte_free(eth_dev->data->mac_addrs);
1326         eth_dev->data->mac_addrs = NULL;
1327
1328         rte_free(eth_dev->data->hash_mac_addrs);
1329         eth_dev->data->hash_mac_addrs = NULL;
1330
1331         return 0;
1332 }
1333
1334 /*
1335  * Negotiate mailbox API version with the PF.
1336  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1337  * Then we try to negotiate starting with the most recent one.
1338  * If all negotiation attempts fail, then we will proceed with
1339  * the default one (ixgbe_mbox_api_10).
1340  */
1341 static void
1342 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1343 {
1344         int32_t i;
1345
1346         /* start with highest supported, proceed down */
1347         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1348                 ixgbe_mbox_api_12,
1349                 ixgbe_mbox_api_11,
1350                 ixgbe_mbox_api_10,
1351         };
1352
1353         for (i = 0;
1354                         i != RTE_DIM(sup_ver) &&
1355                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1356                         i++)
1357                 ;
1358 }
1359
1360 static void
1361 generate_random_mac_addr(struct ether_addr *mac_addr)
1362 {
1363         uint64_t random;
1364
1365         /* Set Organizationally Unique Identifier (OUI) prefix. */
1366         mac_addr->addr_bytes[0] = 0x00;
1367         mac_addr->addr_bytes[1] = 0x09;
1368         mac_addr->addr_bytes[2] = 0xC0;
1369         /* Force indication of locally assigned MAC address. */
1370         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1371         /* Generate the last 3 bytes of the MAC address with a random number. */
1372         random = rte_rand();
1373         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1374 }
1375
1376 /*
1377  * Virtual Function device init
1378  */
1379 static int
1380 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1381 {
1382         int diag;
1383         uint32_t tc, tcs;
1384         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1385         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1386         struct ixgbe_hw *hw =
1387                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1388         struct ixgbe_vfta *shadow_vfta =
1389                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1390         struct ixgbe_hwstrip *hwstrip =
1391                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1392         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1393
1394         PMD_INIT_FUNC_TRACE();
1395
1396         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1397         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1398         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1399
1400         /* for secondary processes, we don't initialise any further as primary
1401          * has already done this work. Only check we don't need a different
1402          * RX function
1403          */
1404         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1405                 struct ixgbe_tx_queue *txq;
1406                 /* TX queue function in primary, set by last queue initialized
1407                  * Tx queue may not initialized by primary process
1408                  */
1409                 if (eth_dev->data->tx_queues) {
1410                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1411                         ixgbe_set_tx_function(eth_dev, txq);
1412                 } else {
1413                         /* Use default TX function if we get here */
1414                         PMD_INIT_LOG(NOTICE,
1415                                      "No TX queues configured yet. Using default TX function.");
1416                 }
1417
1418                 ixgbe_set_rx_function(eth_dev);
1419
1420                 return 0;
1421         }
1422
1423         rte_eth_copy_pci_info(eth_dev, pci_dev);
1424
1425         hw->device_id = pci_dev->id.device_id;
1426         hw->vendor_id = pci_dev->id.vendor_id;
1427         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1428
1429         /* initialize the vfta */
1430         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1431
1432         /* initialize the hw strip bitmap*/
1433         memset(hwstrip, 0, sizeof(*hwstrip));
1434
1435         /* Initialize the shared code (base driver) */
1436         diag = ixgbe_init_shared_code(hw);
1437         if (diag != IXGBE_SUCCESS) {
1438                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1439                 return -EIO;
1440         }
1441
1442         /* init_mailbox_params */
1443         hw->mbx.ops.init_params(hw);
1444
1445         /* Reset the hw statistics */
1446         ixgbevf_dev_stats_reset(eth_dev);
1447
1448         /* Disable the interrupts for VF */
1449         ixgbevf_intr_disable(hw);
1450
1451         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1452         diag = hw->mac.ops.reset_hw(hw);
1453
1454         /*
1455          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1456          * the underlying PF driver has not assigned a MAC address to the VF.
1457          * In this case, assign a random MAC address.
1458          */
1459         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1460                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1461                 return diag;
1462         }
1463
1464         /* negotiate mailbox API version to use with the PF. */
1465         ixgbevf_negotiate_api(hw);
1466
1467         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1468         ixgbevf_get_queues(hw, &tcs, &tc);
1469
1470         /* Allocate memory for storing MAC addresses */
1471         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1472                                                hw->mac.num_rar_entries, 0);
1473         if (eth_dev->data->mac_addrs == NULL) {
1474                 PMD_INIT_LOG(ERR,
1475                              "Failed to allocate %u bytes needed to store "
1476                              "MAC addresses",
1477                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1478                 return -ENOMEM;
1479         }
1480
1481         /* Generate a random MAC address, if none was assigned by PF. */
1482         if (is_zero_ether_addr(perm_addr)) {
1483                 generate_random_mac_addr(perm_addr);
1484                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1485                 if (diag) {
1486                         rte_free(eth_dev->data->mac_addrs);
1487                         eth_dev->data->mac_addrs = NULL;
1488                         return diag;
1489                 }
1490                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1491                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1492                              "%02x:%02x:%02x:%02x:%02x:%02x",
1493                              perm_addr->addr_bytes[0],
1494                              perm_addr->addr_bytes[1],
1495                              perm_addr->addr_bytes[2],
1496                              perm_addr->addr_bytes[3],
1497                              perm_addr->addr_bytes[4],
1498                              perm_addr->addr_bytes[5]);
1499         }
1500
1501         /* Copy the permanent MAC address */
1502         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1503
1504         /* reset the hardware with the new settings */
1505         diag = hw->mac.ops.start_hw(hw);
1506         switch (diag) {
1507         case  0:
1508                 break;
1509
1510         default:
1511                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1512                 return -EIO;
1513         }
1514
1515         rte_intr_callback_register(intr_handle,
1516                                    ixgbevf_dev_interrupt_handler, eth_dev);
1517         rte_intr_enable(intr_handle);
1518         ixgbevf_intr_enable(hw);
1519
1520         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1521                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1522                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1523
1524         return 0;
1525 }
1526
1527 /* Virtual Function device uninit */
1528
1529 static int
1530 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1531 {
1532         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1533         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1534         struct ixgbe_hw *hw;
1535
1536         PMD_INIT_FUNC_TRACE();
1537
1538         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1539                 return -EPERM;
1540
1541         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1542
1543         if (hw->adapter_stopped == 0)
1544                 ixgbevf_dev_close(eth_dev);
1545
1546         eth_dev->dev_ops = NULL;
1547         eth_dev->rx_pkt_burst = NULL;
1548         eth_dev->tx_pkt_burst = NULL;
1549
1550         /* Disable the interrupts for VF */
1551         ixgbevf_intr_disable(hw);
1552
1553         rte_free(eth_dev->data->mac_addrs);
1554         eth_dev->data->mac_addrs = NULL;
1555
1556         rte_intr_disable(intr_handle);
1557         rte_intr_callback_unregister(intr_handle,
1558                                      ixgbevf_dev_interrupt_handler, eth_dev);
1559
1560         return 0;
1561 }
1562
1563 static struct eth_driver rte_ixgbe_pmd = {
1564         .pci_drv = {
1565                 .id_table = pci_id_ixgbe_map,
1566                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1567                         RTE_PCI_DRV_DETACHABLE,
1568                 .probe = rte_eth_dev_pci_probe,
1569                 .remove = rte_eth_dev_pci_remove,
1570         },
1571         .eth_dev_init = eth_ixgbe_dev_init,
1572         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1573         .dev_private_size = sizeof(struct ixgbe_adapter),
1574 };
1575
1576 /*
1577  * virtual function driver struct
1578  */
1579 static struct eth_driver rte_ixgbevf_pmd = {
1580         .pci_drv = {
1581                 .id_table = pci_id_ixgbevf_map,
1582                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1583                 .probe = rte_eth_dev_pci_probe,
1584                 .remove = rte_eth_dev_pci_remove,
1585         },
1586         .eth_dev_init = eth_ixgbevf_dev_init,
1587         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1588         .dev_private_size = sizeof(struct ixgbe_adapter),
1589 };
1590
1591 static int
1592 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1593 {
1594         struct ixgbe_hw *hw =
1595                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596         struct ixgbe_vfta *shadow_vfta =
1597                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1598         uint32_t vfta;
1599         uint32_t vid_idx;
1600         uint32_t vid_bit;
1601
1602         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1603         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1604         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1605         if (on)
1606                 vfta |= vid_bit;
1607         else
1608                 vfta &= ~vid_bit;
1609         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1610
1611         /* update local VFTA copy */
1612         shadow_vfta->vfta[vid_idx] = vfta;
1613
1614         return 0;
1615 }
1616
1617 static void
1618 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1619 {
1620         if (on)
1621                 ixgbe_vlan_hw_strip_enable(dev, queue);
1622         else
1623                 ixgbe_vlan_hw_strip_disable(dev, queue);
1624 }
1625
1626 static int
1627 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1628                     enum rte_vlan_type vlan_type,
1629                     uint16_t tpid)
1630 {
1631         struct ixgbe_hw *hw =
1632                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         int ret = 0;
1634         uint32_t reg;
1635         uint32_t qinq;
1636
1637         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1638         qinq &= IXGBE_DMATXCTL_GDV;
1639
1640         switch (vlan_type) {
1641         case ETH_VLAN_TYPE_INNER:
1642                 if (qinq) {
1643                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1644                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1645                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1646                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1647                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1648                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1649                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1650                 } else {
1651                         ret = -ENOTSUP;
1652                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1653                                     " by single VLAN");
1654                 }
1655                 break;
1656         case ETH_VLAN_TYPE_OUTER:
1657                 if (qinq) {
1658                         /* Only the high 16-bits is valid */
1659                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1660                                         IXGBE_EXVET_VET_EXT_SHIFT);
1661                 } else {
1662                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1663                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1664                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1665                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1666                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1667                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1668                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1669                 }
1670
1671                 break;
1672         default:
1673                 ret = -EINVAL;
1674                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1675                 break;
1676         }
1677
1678         return ret;
1679 }
1680
1681 void
1682 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1683 {
1684         struct ixgbe_hw *hw =
1685                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686         uint32_t vlnctrl;
1687
1688         PMD_INIT_FUNC_TRACE();
1689
1690         /* Filter Table Disable */
1691         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1692         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1693
1694         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1695 }
1696
1697 void
1698 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1699 {
1700         struct ixgbe_hw *hw =
1701                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1702         struct ixgbe_vfta *shadow_vfta =
1703                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1704         uint32_t vlnctrl;
1705         uint16_t i;
1706
1707         PMD_INIT_FUNC_TRACE();
1708
1709         /* Filter Table Enable */
1710         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1711         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1712         vlnctrl |= IXGBE_VLNCTRL_VFE;
1713
1714         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1715
1716         /* write whatever is in local vfta copy */
1717         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1718                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1719 }
1720
1721 static void
1722 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1723 {
1724         struct ixgbe_hwstrip *hwstrip =
1725                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1726         struct ixgbe_rx_queue *rxq;
1727
1728         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1729                 return;
1730
1731         if (on)
1732                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1733         else
1734                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1735
1736         if (queue >= dev->data->nb_rx_queues)
1737                 return;
1738
1739         rxq = dev->data->rx_queues[queue];
1740
1741         if (on)
1742                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1743         else
1744                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1745 }
1746
1747 static void
1748 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1749 {
1750         struct ixgbe_hw *hw =
1751                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752         uint32_t ctrl;
1753
1754         PMD_INIT_FUNC_TRACE();
1755
1756         if (hw->mac.type == ixgbe_mac_82598EB) {
1757                 /* No queue level support */
1758                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1759                 return;
1760         }
1761
1762         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1763         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1764         ctrl &= ~IXGBE_RXDCTL_VME;
1765         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1766
1767         /* record those setting for HW strip per queue */
1768         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1769 }
1770
1771 static void
1772 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1773 {
1774         struct ixgbe_hw *hw =
1775                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1776         uint32_t ctrl;
1777
1778         PMD_INIT_FUNC_TRACE();
1779
1780         if (hw->mac.type == ixgbe_mac_82598EB) {
1781                 /* No queue level supported */
1782                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1783                 return;
1784         }
1785
1786         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1787         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1788         ctrl |= IXGBE_RXDCTL_VME;
1789         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1790
1791         /* record those setting for HW strip per queue */
1792         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1793 }
1794
1795 void
1796 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1797 {
1798         struct ixgbe_hw *hw =
1799                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800         uint32_t ctrl;
1801         uint16_t i;
1802         struct ixgbe_rx_queue *rxq;
1803
1804         PMD_INIT_FUNC_TRACE();
1805
1806         if (hw->mac.type == ixgbe_mac_82598EB) {
1807                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1808                 ctrl &= ~IXGBE_VLNCTRL_VME;
1809                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1810         } else {
1811                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1812                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1813                         rxq = dev->data->rx_queues[i];
1814                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1815                         ctrl &= ~IXGBE_RXDCTL_VME;
1816                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1817
1818                         /* record those setting for HW strip per queue */
1819                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1820                 }
1821         }
1822 }
1823
1824 void
1825 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1826 {
1827         struct ixgbe_hw *hw =
1828                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829         uint32_t ctrl;
1830         uint16_t i;
1831         struct ixgbe_rx_queue *rxq;
1832
1833         PMD_INIT_FUNC_TRACE();
1834
1835         if (hw->mac.type == ixgbe_mac_82598EB) {
1836                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1837                 ctrl |= IXGBE_VLNCTRL_VME;
1838                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1839         } else {
1840                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1841                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1842                         rxq = dev->data->rx_queues[i];
1843                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1844                         ctrl |= IXGBE_RXDCTL_VME;
1845                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1846
1847                         /* record those setting for HW strip per queue */
1848                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1849                 }
1850         }
1851 }
1852
1853 static void
1854 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1855 {
1856         struct ixgbe_hw *hw =
1857                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858         uint32_t ctrl;
1859
1860         PMD_INIT_FUNC_TRACE();
1861
1862         /* DMATXCTRL: Geric Double VLAN Disable */
1863         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1864         ctrl &= ~IXGBE_DMATXCTL_GDV;
1865         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1866
1867         /* CTRL_EXT: Global Double VLAN Disable */
1868         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1869         ctrl &= ~IXGBE_EXTENDED_VLAN;
1870         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1871
1872 }
1873
1874 static void
1875 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1876 {
1877         struct ixgbe_hw *hw =
1878                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         uint32_t ctrl;
1880
1881         PMD_INIT_FUNC_TRACE();
1882
1883         /* DMATXCTRL: Geric Double VLAN Enable */
1884         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1885         ctrl |= IXGBE_DMATXCTL_GDV;
1886         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1887
1888         /* CTRL_EXT: Global Double VLAN Enable */
1889         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1890         ctrl |= IXGBE_EXTENDED_VLAN;
1891         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1892
1893         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1894         if (hw->mac.type == ixgbe_mac_X550 ||
1895             hw->mac.type == ixgbe_mac_X550EM_x ||
1896             hw->mac.type == ixgbe_mac_X550EM_a) {
1897                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1898                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1899                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1900         }
1901
1902         /*
1903          * VET EXT field in the EXVET register = 0x8100 by default
1904          * So no need to change. Same to VT field of DMATXCTL register
1905          */
1906 }
1907
1908 static void
1909 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1910 {
1911         if (mask & ETH_VLAN_STRIP_MASK) {
1912                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1913                         ixgbe_vlan_hw_strip_enable_all(dev);
1914                 else
1915                         ixgbe_vlan_hw_strip_disable_all(dev);
1916         }
1917
1918         if (mask & ETH_VLAN_FILTER_MASK) {
1919                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1920                         ixgbe_vlan_hw_filter_enable(dev);
1921                 else
1922                         ixgbe_vlan_hw_filter_disable(dev);
1923         }
1924
1925         if (mask & ETH_VLAN_EXTEND_MASK) {
1926                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1927                         ixgbe_vlan_hw_extend_enable(dev);
1928                 else
1929                         ixgbe_vlan_hw_extend_disable(dev);
1930         }
1931 }
1932
1933 static void
1934 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1935 {
1936         struct ixgbe_hw *hw =
1937                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1939         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1940
1941         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1942         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1943 }
1944
1945 static int
1946 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1947 {
1948         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
1949
1950         switch (nb_rx_q) {
1951         case 1:
1952         case 2:
1953                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1954                 break;
1955         case 4:
1956                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1957                 break;
1958         default:
1959                 return -EINVAL;
1960         }
1961
1962         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1963         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
1964
1965         return 0;
1966 }
1967
1968 static int
1969 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1970 {
1971         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1974         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1975
1976         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1977                 /* check multi-queue mode */
1978                 switch (dev_conf->rxmode.mq_mode) {
1979                 case ETH_MQ_RX_VMDQ_DCB:
1980                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1981                         break;
1982                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1983                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1984                         PMD_INIT_LOG(ERR, "SRIOV active,"
1985                                         " unsupported mq_mode rx %d.",
1986                                         dev_conf->rxmode.mq_mode);
1987                         return -EINVAL;
1988                 case ETH_MQ_RX_RSS:
1989                 case ETH_MQ_RX_VMDQ_RSS:
1990                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1991                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1992                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1993                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1994                                                 " invalid queue number"
1995                                                 " for VMDQ RSS, allowed"
1996                                                 " value are 1, 2 or 4.");
1997                                         return -EINVAL;
1998                                 }
1999                         break;
2000                 case ETH_MQ_RX_VMDQ_ONLY:
2001                 case ETH_MQ_RX_NONE:
2002                         /* if nothing mq mode configure, use default scheme */
2003                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2004                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2005                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2006                         break;
2007                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2008                         /* SRIOV only works in VMDq enable mode */
2009                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2010                                         " wrong mq_mode rx %d.",
2011                                         dev_conf->rxmode.mq_mode);
2012                         return -EINVAL;
2013                 }
2014
2015                 switch (dev_conf->txmode.mq_mode) {
2016                 case ETH_MQ_TX_VMDQ_DCB:
2017                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2018                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2019                         break;
2020                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2021                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2022                         break;
2023                 }
2024
2025                 /* check valid queue number */
2026                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2027                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2028                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2029                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2030                                         " must be less than or equal to %d.",
2031                                         nb_rx_q, nb_tx_q,
2032                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2033                         return -EINVAL;
2034                 }
2035         } else {
2036                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2037                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2038                                           " not supported.");
2039                         return -EINVAL;
2040                 }
2041                 /* check configuration for vmdb+dcb mode */
2042                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2043                         const struct rte_eth_vmdq_dcb_conf *conf;
2044
2045                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2046                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2047                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2048                                 return -EINVAL;
2049                         }
2050                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2051                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2052                                conf->nb_queue_pools == ETH_32_POOLS)) {
2053                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2054                                                 " nb_queue_pools must be %d or %d.",
2055                                                 ETH_16_POOLS, ETH_32_POOLS);
2056                                 return -EINVAL;
2057                         }
2058                 }
2059                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2060                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2061
2062                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2063                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2064                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2065                                 return -EINVAL;
2066                         }
2067                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2068                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2069                                conf->nb_queue_pools == ETH_32_POOLS)) {
2070                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2071                                                 " nb_queue_pools != %d and"
2072                                                 " nb_queue_pools != %d.",
2073                                                 ETH_16_POOLS, ETH_32_POOLS);
2074                                 return -EINVAL;
2075                         }
2076                 }
2077
2078                 /* For DCB mode check our configuration before we go further */
2079                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2080                         const struct rte_eth_dcb_rx_conf *conf;
2081
2082                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2083                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2084                                                  IXGBE_DCB_NB_QUEUES);
2085                                 return -EINVAL;
2086                         }
2087                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2088                         if (!(conf->nb_tcs == ETH_4_TCS ||
2089                                conf->nb_tcs == ETH_8_TCS)) {
2090                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2091                                                 " and nb_tcs != %d.",
2092                                                 ETH_4_TCS, ETH_8_TCS);
2093                                 return -EINVAL;
2094                         }
2095                 }
2096
2097                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2098                         const struct rte_eth_dcb_tx_conf *conf;
2099
2100                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2101                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2102                                                  IXGBE_DCB_NB_QUEUES);
2103                                 return -EINVAL;
2104                         }
2105                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2106                         if (!(conf->nb_tcs == ETH_4_TCS ||
2107                                conf->nb_tcs == ETH_8_TCS)) {
2108                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2109                                                 " and nb_tcs != %d.",
2110                                                 ETH_4_TCS, ETH_8_TCS);
2111                                 return -EINVAL;
2112                         }
2113                 }
2114
2115                 /*
2116                  * When DCB/VT is off, maximum number of queues changes,
2117                  * except for 82598EB, which remains constant.
2118                  */
2119                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2120                                 hw->mac.type != ixgbe_mac_82598EB) {
2121                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2122                                 PMD_INIT_LOG(ERR,
2123                                              "Neither VT nor DCB are enabled, "
2124                                              "nb_tx_q > %d.",
2125                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2126                                 return -EINVAL;
2127                         }
2128                 }
2129         }
2130         return 0;
2131 }
2132
2133 static int
2134 ixgbe_dev_configure(struct rte_eth_dev *dev)
2135 {
2136         struct ixgbe_interrupt *intr =
2137                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2138         struct ixgbe_adapter *adapter =
2139                 (struct ixgbe_adapter *)dev->data->dev_private;
2140         int ret;
2141
2142         PMD_INIT_FUNC_TRACE();
2143         /* multipe queue mode checking */
2144         ret  = ixgbe_check_mq_mode(dev);
2145         if (ret != 0) {
2146                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2147                             ret);
2148                 return ret;
2149         }
2150
2151         /* set flag to update link status after init */
2152         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2153
2154         /*
2155          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2156          * allocation or vector Rx preconditions we will reset it.
2157          */
2158         adapter->rx_bulk_alloc_allowed = true;
2159         adapter->rx_vec_allowed = true;
2160
2161         return 0;
2162 }
2163
2164 static void
2165 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2166 {
2167         struct ixgbe_hw *hw =
2168                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169         struct ixgbe_interrupt *intr =
2170                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2171         uint32_t gpie;
2172
2173         /* only set up it on X550EM_X */
2174         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2175                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2176                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2177                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2178                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2179                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2180         }
2181 }
2182
2183 /*
2184  * Configure device link speed and setup link.
2185  * It returns 0 on success.
2186  */
2187 static int
2188 ixgbe_dev_start(struct rte_eth_dev *dev)
2189 {
2190         struct ixgbe_hw *hw =
2191                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192         struct ixgbe_vf_info *vfinfo =
2193                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2194         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2195         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2196         uint32_t intr_vector = 0;
2197         int err, link_up = 0, negotiate = 0;
2198         uint32_t speed = 0;
2199         int mask = 0;
2200         int status;
2201         uint16_t vf, idx;
2202         uint32_t *link_speeds;
2203
2204         PMD_INIT_FUNC_TRACE();
2205
2206         /* IXGBE devices don't support:
2207         *    - half duplex (checked afterwards for valid speeds)
2208         *    - fixed speed: TODO implement
2209         */
2210         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2211                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2212                              dev->data->port_id);
2213                 return -EINVAL;
2214         }
2215
2216         /* disable uio/vfio intr/eventfd mapping */
2217         rte_intr_disable(intr_handle);
2218
2219         /* stop adapter */
2220         hw->adapter_stopped = 0;
2221         ixgbe_stop_adapter(hw);
2222
2223         /* reinitialize adapter
2224          * this calls reset and start
2225          */
2226         status = ixgbe_pf_reset_hw(hw);
2227         if (status != 0)
2228                 return -1;
2229         hw->mac.ops.start_hw(hw);
2230         hw->mac.get_link_status = true;
2231
2232         /* configure PF module if SRIOV enabled */
2233         ixgbe_pf_host_configure(dev);
2234
2235         ixgbe_dev_phy_intr_setup(dev);
2236
2237         /* check and configure queue intr-vector mapping */
2238         if ((rte_intr_cap_multiple(intr_handle) ||
2239              !RTE_ETH_DEV_SRIOV(dev).active) &&
2240             dev->data->dev_conf.intr_conf.rxq != 0) {
2241                 intr_vector = dev->data->nb_rx_queues;
2242                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2243                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2244                                         IXGBE_MAX_INTR_QUEUE_NUM);
2245                         return -ENOTSUP;
2246                 }
2247                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2248                         return -1;
2249         }
2250
2251         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2252                 intr_handle->intr_vec =
2253                         rte_zmalloc("intr_vec",
2254                                     dev->data->nb_rx_queues * sizeof(int), 0);
2255                 if (intr_handle->intr_vec == NULL) {
2256                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2257                                      " intr_vec\n", dev->data->nb_rx_queues);
2258                         return -ENOMEM;
2259                 }
2260         }
2261
2262         /* confiugre msix for sleep until rx interrupt */
2263         ixgbe_configure_msix(dev);
2264
2265         /* initialize transmission unit */
2266         ixgbe_dev_tx_init(dev);
2267
2268         /* This can fail when allocating mbufs for descriptor rings */
2269         err = ixgbe_dev_rx_init(dev);
2270         if (err) {
2271                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2272                 goto error;
2273         }
2274
2275     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2276                 ETH_VLAN_EXTEND_MASK;
2277         ixgbe_vlan_offload_set(dev, mask);
2278
2279         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2280                 /* Enable vlan filtering for VMDq */
2281                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2282         }
2283
2284         /* Configure DCB hw */
2285         ixgbe_configure_dcb(dev);
2286
2287         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2288                 err = ixgbe_fdir_configure(dev);
2289                 if (err)
2290                         goto error;
2291         }
2292
2293         /* Restore vf rate limit */
2294         if (vfinfo != NULL) {
2295                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2296                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2297                                 if (vfinfo[vf].tx_rate[idx] != 0)
2298                                         ixgbe_set_vf_rate_limit(dev, vf,
2299                                                 vfinfo[vf].tx_rate[idx],
2300                                                 1 << idx);
2301         }
2302
2303         ixgbe_restore_statistics_mapping(dev);
2304
2305         err = ixgbe_dev_rxtx_start(dev);
2306         if (err < 0) {
2307                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2308                 goto error;
2309         }
2310
2311         /* Skip link setup if loopback mode is enabled for 82599. */
2312         if (hw->mac.type == ixgbe_mac_82599EB &&
2313                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2314                 goto skip_link_setup;
2315
2316         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2317                 err = hw->mac.ops.setup_sfp(hw);
2318                 if (err)
2319                         goto error;
2320         }
2321
2322         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2323                 /* Turn on the copper */
2324                 ixgbe_set_phy_power(hw, true);
2325         } else {
2326                 /* Turn on the laser */
2327                 ixgbe_enable_tx_laser(hw);
2328         }
2329
2330         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2331         if (err)
2332                 goto error;
2333         dev->data->dev_link.link_status = link_up;
2334
2335         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2336         if (err)
2337                 goto error;
2338
2339         link_speeds = &dev->data->dev_conf.link_speeds;
2340         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2341                         ETH_LINK_SPEED_10G)) {
2342                 PMD_INIT_LOG(ERR, "Invalid link setting");
2343                 goto error;
2344         }
2345
2346         speed = 0x0;
2347         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2348                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2349                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2350                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2351         } else {
2352                 if (*link_speeds & ETH_LINK_SPEED_10G)
2353                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2354                 if (*link_speeds & ETH_LINK_SPEED_1G)
2355                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2356                 if (*link_speeds & ETH_LINK_SPEED_100M)
2357                         speed |= IXGBE_LINK_SPEED_100_FULL;
2358         }
2359
2360         err = ixgbe_setup_link(hw, speed, link_up);
2361         if (err)
2362                 goto error;
2363
2364 skip_link_setup:
2365
2366         if (rte_intr_allow_others(intr_handle)) {
2367                 /* check if lsc interrupt is enabled */
2368                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2369                         ixgbe_dev_lsc_interrupt_setup(dev);
2370         } else {
2371                 rte_intr_callback_unregister(intr_handle,
2372                                              ixgbe_dev_interrupt_handler, dev);
2373                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2374                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2375                                      " no intr multiplex\n");
2376         }
2377
2378         /* check if rxq interrupt is enabled */
2379         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2380             rte_intr_dp_is_en(intr_handle))
2381                 ixgbe_dev_rxq_interrupt_setup(dev);
2382
2383         /* enable uio/vfio intr/eventfd mapping */
2384         rte_intr_enable(intr_handle);
2385
2386         /* resume enabled intr since hw reset */
2387         ixgbe_enable_intr(dev);
2388
2389         return 0;
2390
2391 error:
2392         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2393         ixgbe_dev_clear_queues(dev);
2394         return -EIO;
2395 }
2396
2397 /*
2398  * Stop device: disable rx and tx functions to allow for reconfiguring.
2399  */
2400 static void
2401 ixgbe_dev_stop(struct rte_eth_dev *dev)
2402 {
2403         struct rte_eth_link link;
2404         struct ixgbe_hw *hw =
2405                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406         struct ixgbe_vf_info *vfinfo =
2407                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2408         struct ixgbe_filter_info *filter_info =
2409                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2410         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2411         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2412         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2413         int vf;
2414
2415         PMD_INIT_FUNC_TRACE();
2416
2417         /* disable interrupts */
2418         ixgbe_disable_intr(hw);
2419
2420         /* reset the NIC */
2421         ixgbe_pf_reset_hw(hw);
2422         hw->adapter_stopped = 0;
2423
2424         /* stop adapter */
2425         ixgbe_stop_adapter(hw);
2426
2427         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2428                 vfinfo[vf].clear_to_send = false;
2429
2430         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2431                 /* Turn off the copper */
2432                 ixgbe_set_phy_power(hw, false);
2433         } else {
2434                 /* Turn off the laser */
2435                 ixgbe_disable_tx_laser(hw);
2436         }
2437
2438         ixgbe_dev_clear_queues(dev);
2439
2440         /* Clear stored conf */
2441         dev->data->scattered_rx = 0;
2442         dev->data->lro = 0;
2443
2444         /* Clear recorded link status */
2445         memset(&link, 0, sizeof(link));
2446         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2447
2448         /* Remove all ntuple filters of the device */
2449         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2450              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2451                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2452                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2453                              p_5tuple, entries);
2454                 rte_free(p_5tuple);
2455         }
2456         memset(filter_info->fivetuple_mask, 0,
2457                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2458
2459         if (!rte_intr_allow_others(intr_handle))
2460                 /* resume to the default handler */
2461                 rte_intr_callback_register(intr_handle,
2462                                            ixgbe_dev_interrupt_handler,
2463                                            (void *)dev);
2464
2465         /* Clean datapath event and queue/vec mapping */
2466         rte_intr_efd_disable(intr_handle);
2467         if (intr_handle->intr_vec != NULL) {
2468                 rte_free(intr_handle->intr_vec);
2469                 intr_handle->intr_vec = NULL;
2470         }
2471 }
2472
2473 /*
2474  * Set device link up: enable tx.
2475  */
2476 static int
2477 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2478 {
2479         struct ixgbe_hw *hw =
2480                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481         if (hw->mac.type == ixgbe_mac_82599EB) {
2482 #ifdef RTE_NIC_BYPASS
2483                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2484                         /* Not suported in bypass mode */
2485                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2486                                      "by device id 0x%x", hw->device_id);
2487                         return -ENOTSUP;
2488                 }
2489 #endif
2490         }
2491
2492         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2493                 /* Turn on the copper */
2494                 ixgbe_set_phy_power(hw, true);
2495         } else {
2496                 /* Turn on the laser */
2497                 ixgbe_enable_tx_laser(hw);
2498         }
2499
2500         return 0;
2501 }
2502
2503 /*
2504  * Set device link down: disable tx.
2505  */
2506 static int
2507 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2508 {
2509         struct ixgbe_hw *hw =
2510                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511         if (hw->mac.type == ixgbe_mac_82599EB) {
2512 #ifdef RTE_NIC_BYPASS
2513                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2514                         /* Not suported in bypass mode */
2515                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2516                                      "by device id 0x%x", hw->device_id);
2517                         return -ENOTSUP;
2518                 }
2519 #endif
2520         }
2521
2522         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2523                 /* Turn off the copper */
2524                 ixgbe_set_phy_power(hw, false);
2525         } else {
2526                 /* Turn off the laser */
2527                 ixgbe_disable_tx_laser(hw);
2528         }
2529
2530         return 0;
2531 }
2532
2533 /*
2534  * Reest and stop device.
2535  */
2536 static void
2537 ixgbe_dev_close(struct rte_eth_dev *dev)
2538 {
2539         struct ixgbe_hw *hw =
2540                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541
2542         PMD_INIT_FUNC_TRACE();
2543
2544         ixgbe_pf_reset_hw(hw);
2545
2546         ixgbe_dev_stop(dev);
2547         hw->adapter_stopped = 1;
2548
2549         ixgbe_dev_free_queues(dev);
2550
2551         ixgbe_disable_pcie_master(hw);
2552
2553         /* reprogram the RAR[0] in case user changed it. */
2554         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2555 }
2556
2557 static void
2558 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2559                            struct ixgbe_hw_stats *hw_stats,
2560                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2561                            uint64_t *total_qprc, uint64_t *total_qprdc)
2562 {
2563         uint32_t bprc, lxon, lxoff, total;
2564         uint32_t delta_gprc = 0;
2565         unsigned i;
2566         /* Workaround for RX byte count not including CRC bytes when CRC
2567 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2568          * is disabled.
2569 +        */
2570         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2571                         IXGBE_HLREG0_RXCRCSTRP);
2572
2573         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2574         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2575         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2576         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2577
2578         for (i = 0; i < 8; i++) {
2579                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2580
2581                 /* global total per queue */
2582                 hw_stats->mpc[i] += mp;
2583                 /* Running comprehensive total for stats display */
2584                 *total_missed_rx += hw_stats->mpc[i];
2585                 if (hw->mac.type == ixgbe_mac_82598EB) {
2586                         hw_stats->rnbc[i] +=
2587                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2588                         hw_stats->pxonrxc[i] +=
2589                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2590                         hw_stats->pxoffrxc[i] +=
2591                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2592                 } else {
2593                         hw_stats->pxonrxc[i] +=
2594                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2595                         hw_stats->pxoffrxc[i] +=
2596                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2597                         hw_stats->pxon2offc[i] +=
2598                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2599                 }
2600                 hw_stats->pxontxc[i] +=
2601                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2602                 hw_stats->pxofftxc[i] +=
2603                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2604         }
2605         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2606                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2607                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2608                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2609
2610                 delta_gprc += delta_qprc;
2611
2612                 hw_stats->qprc[i] += delta_qprc;
2613                 hw_stats->qptc[i] += delta_qptc;
2614
2615                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2616                 hw_stats->qbrc[i] +=
2617                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2618                 if (crc_strip == 0)
2619                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2620
2621                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2622                 hw_stats->qbtc[i] +=
2623                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2624
2625                 hw_stats->qprdc[i] += delta_qprdc;
2626                 *total_qprdc += hw_stats->qprdc[i];
2627
2628                 *total_qprc += hw_stats->qprc[i];
2629                 *total_qbrc += hw_stats->qbrc[i];
2630         }
2631         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2632         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2633         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2634
2635         /*
2636          * An errata states that gprc actually counts good + missed packets:
2637          * Workaround to set gprc to summated queue packet receives
2638          */
2639         hw_stats->gprc = *total_qprc;
2640
2641         if (hw->mac.type != ixgbe_mac_82598EB) {
2642                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2643                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2644                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2645                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2646                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2647                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2648                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2649                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2650         } else {
2651                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2652                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2653                 /* 82598 only has a counter in the high register */
2654                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2655                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2656                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2657         }
2658         uint64_t old_tpr = hw_stats->tpr;
2659
2660         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2661         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2662
2663         if (crc_strip == 0)
2664                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2665
2666         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2667         hw_stats->gptc += delta_gptc;
2668         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2669         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2670
2671         /*
2672          * Workaround: mprc hardware is incorrectly counting
2673          * broadcasts, so for now we subtract those.
2674          */
2675         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2676         hw_stats->bprc += bprc;
2677         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2678         if (hw->mac.type == ixgbe_mac_82598EB)
2679                 hw_stats->mprc -= bprc;
2680
2681         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2682         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2683         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2684         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2685         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2686         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2687
2688         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2689         hw_stats->lxontxc += lxon;
2690         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2691         hw_stats->lxofftxc += lxoff;
2692         total = lxon + lxoff;
2693
2694         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2695         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2696         hw_stats->gptc -= total;
2697         hw_stats->mptc -= total;
2698         hw_stats->ptc64 -= total;
2699         hw_stats->gotc -= total * ETHER_MIN_LEN;
2700
2701         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2702         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2703         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2704         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2705         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2706         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2707         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2708         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2709         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2710         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2711         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2712         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2713         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2714         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2715         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2716         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2717         /* Only read FCOE on 82599 */
2718         if (hw->mac.type != ixgbe_mac_82598EB) {
2719                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2720                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2721                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2722                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2723                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2724         }
2725
2726         /* Flow Director Stats registers */
2727         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2728         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2729 }
2730
2731 /*
2732  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2733  */
2734 static void
2735 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2736 {
2737         struct ixgbe_hw *hw =
2738                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2739         struct ixgbe_hw_stats *hw_stats =
2740                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2741         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2742         unsigned i;
2743
2744         total_missed_rx = 0;
2745         total_qbrc = 0;
2746         total_qprc = 0;
2747         total_qprdc = 0;
2748
2749         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2750                         &total_qprc, &total_qprdc);
2751
2752         if (stats == NULL)
2753                 return;
2754
2755         /* Fill out the rte_eth_stats statistics structure */
2756         stats->ipackets = total_qprc;
2757         stats->ibytes = total_qbrc;
2758         stats->opackets = hw_stats->gptc;
2759         stats->obytes = hw_stats->gotc;
2760
2761         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2762                 stats->q_ipackets[i] = hw_stats->qprc[i];
2763                 stats->q_opackets[i] = hw_stats->qptc[i];
2764                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2765                 stats->q_obytes[i] = hw_stats->qbtc[i];
2766                 stats->q_errors[i] = hw_stats->qprdc[i];
2767         }
2768
2769         /* Rx Errors */
2770         stats->imissed  = total_missed_rx;
2771         stats->ierrors  = hw_stats->crcerrs +
2772                           hw_stats->mspdc +
2773                           hw_stats->rlec +
2774                           hw_stats->ruc +
2775                           hw_stats->roc +
2776                           hw_stats->illerrc +
2777                           hw_stats->errbc +
2778                           hw_stats->rfc +
2779                           hw_stats->fccrc +
2780                           hw_stats->fclast;
2781
2782         /* Tx Errors */
2783         stats->oerrors  = 0;
2784 }
2785
2786 static void
2787 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2788 {
2789         struct ixgbe_hw_stats *stats =
2790                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2791
2792         /* HW registers are cleared on read */
2793         ixgbe_dev_stats_get(dev, NULL);
2794
2795         /* Reset software totals */
2796         memset(stats, 0, sizeof(*stats));
2797 }
2798
2799 /* This function calculates the number of xstats based on the current config */
2800 static unsigned
2801 ixgbe_xstats_calc_num(void) {
2802         return IXGBE_NB_HW_STATS +
2803                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2804                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2805 }
2806
2807 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2808         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2809 {
2810         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2811         unsigned stat, i, count;
2812
2813         if (xstats_names != NULL) {
2814                 count = 0;
2815
2816                 /* Note: limit >= cnt_stats checked upstream
2817                  * in rte_eth_xstats_names()
2818                  */
2819
2820                 /* Extended stats from ixgbe_hw_stats */
2821                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2822                         snprintf(xstats_names[count].name,
2823                                 sizeof(xstats_names[count].name),
2824                                 "%s",
2825                                 rte_ixgbe_stats_strings[i].name);
2826                         count++;
2827                 }
2828
2829                 /* RX Priority Stats */
2830                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2831                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2832                                 snprintf(xstats_names[count].name,
2833                                         sizeof(xstats_names[count].name),
2834                                         "rx_priority%u_%s", i,
2835                                         rte_ixgbe_rxq_strings[stat].name);
2836                                 count++;
2837                         }
2838                 }
2839
2840                 /* TX Priority Stats */
2841                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2842                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2843                                 snprintf(xstats_names[count].name,
2844                                         sizeof(xstats_names[count].name),
2845                                         "tx_priority%u_%s", i,
2846                                         rte_ixgbe_txq_strings[stat].name);
2847                                 count++;
2848                         }
2849                 }
2850         }
2851         return cnt_stats;
2852 }
2853
2854 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2855         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2856 {
2857         unsigned i;
2858
2859         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2860                 return -ENOMEM;
2861
2862         if (xstats_names != NULL)
2863                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2864                         snprintf(xstats_names[i].name,
2865                                 sizeof(xstats_names[i].name),
2866                                 "%s", rte_ixgbevf_stats_strings[i].name);
2867         return IXGBEVF_NB_XSTATS;
2868 }
2869
2870 static int
2871 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2872                                          unsigned n)
2873 {
2874         struct ixgbe_hw *hw =
2875                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         struct ixgbe_hw_stats *hw_stats =
2877                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2878         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2879         unsigned i, stat, count = 0;
2880
2881         count = ixgbe_xstats_calc_num();
2882
2883         if (n < count)
2884                 return count;
2885
2886         total_missed_rx = 0;
2887         total_qbrc = 0;
2888         total_qprc = 0;
2889         total_qprdc = 0;
2890
2891         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2892                                    &total_qprc, &total_qprdc);
2893
2894         /* If this is a reset xstats is NULL, and we have cleared the
2895          * registers by reading them.
2896          */
2897         if (!xstats)
2898                 return 0;
2899
2900         /* Extended stats from ixgbe_hw_stats */
2901         count = 0;
2902         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2903                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2904                                 rte_ixgbe_stats_strings[i].offset);
2905                 count++;
2906         }
2907
2908         /* RX Priority Stats */
2909         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2910                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2911                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2912                                         rte_ixgbe_rxq_strings[stat].offset +
2913                                         (sizeof(uint64_t) * i));
2914                         count++;
2915                 }
2916         }
2917
2918         /* TX Priority Stats */
2919         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2920                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2921                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2922                                         rte_ixgbe_txq_strings[stat].offset +
2923                                         (sizeof(uint64_t) * i));
2924                         count++;
2925                 }
2926         }
2927         return count;
2928 }
2929
2930 static void
2931 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2932 {
2933         struct ixgbe_hw_stats *stats =
2934                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2935
2936         unsigned count = ixgbe_xstats_calc_num();
2937
2938         /* HW registers are cleared on read */
2939         ixgbe_dev_xstats_get(dev, NULL, count);
2940
2941         /* Reset software totals */
2942         memset(stats, 0, sizeof(*stats));
2943 }
2944
2945 static void
2946 ixgbevf_update_stats(struct rte_eth_dev *dev)
2947 {
2948         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2949         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2950                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2951
2952         /* Good Rx packet, include VF loopback */
2953         UPDATE_VF_STAT(IXGBE_VFGPRC,
2954             hw_stats->last_vfgprc, hw_stats->vfgprc);
2955
2956         /* Good Rx octets, include VF loopback */
2957         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2958             hw_stats->last_vfgorc, hw_stats->vfgorc);
2959
2960         /* Good Tx packet, include VF loopback */
2961         UPDATE_VF_STAT(IXGBE_VFGPTC,
2962             hw_stats->last_vfgptc, hw_stats->vfgptc);
2963
2964         /* Good Tx octets, include VF loopback */
2965         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2966             hw_stats->last_vfgotc, hw_stats->vfgotc);
2967
2968         /* Rx Multicst Packet */
2969         UPDATE_VF_STAT(IXGBE_VFMPRC,
2970             hw_stats->last_vfmprc, hw_stats->vfmprc);
2971 }
2972
2973 static int
2974 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2975                        unsigned n)
2976 {
2977         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2978                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2979         unsigned i;
2980
2981         if (n < IXGBEVF_NB_XSTATS)
2982                 return IXGBEVF_NB_XSTATS;
2983
2984         ixgbevf_update_stats(dev);
2985
2986         if (!xstats)
2987                 return 0;
2988
2989         /* Extended stats */
2990         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2991                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2992                         rte_ixgbevf_stats_strings[i].offset);
2993         }
2994
2995         return IXGBEVF_NB_XSTATS;
2996 }
2997
2998 static void
2999 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3000 {
3001         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3002                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3003
3004         ixgbevf_update_stats(dev);
3005
3006         if (stats == NULL)
3007                 return;
3008
3009         stats->ipackets = hw_stats->vfgprc;
3010         stats->ibytes = hw_stats->vfgorc;
3011         stats->opackets = hw_stats->vfgptc;
3012         stats->obytes = hw_stats->vfgotc;
3013 }
3014
3015 static void
3016 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3017 {
3018         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3019                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3020
3021         /* Sync HW register to the last stats */
3022         ixgbevf_dev_stats_get(dev, NULL);
3023
3024         /* reset HW current stats*/
3025         hw_stats->vfgprc = 0;
3026         hw_stats->vfgorc = 0;
3027         hw_stats->vfgptc = 0;
3028         hw_stats->vfgotc = 0;
3029 }
3030
3031 static void
3032 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3033 {
3034         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3036         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3037
3038         dev_info->pci_dev = pci_dev;
3039         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3040         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3041         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3042                 /*
3043                  * When DCB/VT is off, maximum number of queues changes,
3044                  * except for 82598EB, which remains constant.
3045                  */
3046                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3047                                 hw->mac.type != ixgbe_mac_82598EB)
3048                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3049         }
3050         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3051         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3052         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3053         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3054         dev_info->max_vfs = pci_dev->max_vfs;
3055         if (hw->mac.type == ixgbe_mac_82598EB)
3056                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3057         else
3058                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3059         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3060         dev_info->rx_offload_capa =
3061                 DEV_RX_OFFLOAD_VLAN_STRIP |
3062                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3063                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3064                 DEV_RX_OFFLOAD_TCP_CKSUM;
3065
3066         /*
3067          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3068          * mode.
3069          */
3070         if ((hw->mac.type == ixgbe_mac_82599EB ||
3071              hw->mac.type == ixgbe_mac_X540) &&
3072             !RTE_ETH_DEV_SRIOV(dev).active)
3073                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3074
3075         if (hw->mac.type == ixgbe_mac_X550 ||
3076             hw->mac.type == ixgbe_mac_X550EM_x ||
3077             hw->mac.type == ixgbe_mac_X550EM_a)
3078                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3079
3080         dev_info->tx_offload_capa =
3081                 DEV_TX_OFFLOAD_VLAN_INSERT |
3082                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3083                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3084                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3085                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3086                 DEV_TX_OFFLOAD_TCP_TSO;
3087
3088         if (hw->mac.type == ixgbe_mac_X550 ||
3089             hw->mac.type == ixgbe_mac_X550EM_x ||
3090             hw->mac.type == ixgbe_mac_X550EM_a)
3091                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3092
3093         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3094                 .rx_thresh = {
3095                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3096                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3097                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3098                 },
3099                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3100                 .rx_drop_en = 0,
3101         };
3102
3103         dev_info->default_txconf = (struct rte_eth_txconf) {
3104                 .tx_thresh = {
3105                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3106                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3107                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3108                 },
3109                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3110                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3111                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3112                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3113         };
3114
3115         dev_info->rx_desc_lim = rx_desc_lim;
3116         dev_info->tx_desc_lim = tx_desc_lim;
3117
3118         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3119         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3120         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3121
3122         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3123         if (hw->mac.type == ixgbe_mac_X540 ||
3124             hw->mac.type == ixgbe_mac_X540_vf ||
3125             hw->mac.type == ixgbe_mac_X550 ||
3126             hw->mac.type == ixgbe_mac_X550_vf) {
3127                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3128         }
3129 }
3130
3131 static const uint32_t *
3132 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3133 {
3134         static const uint32_t ptypes[] = {
3135                 /* For non-vec functions,
3136                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3137                  * for vec functions,
3138                  * refers to _recv_raw_pkts_vec().
3139                  */
3140                 RTE_PTYPE_L2_ETHER,
3141                 RTE_PTYPE_L3_IPV4,
3142                 RTE_PTYPE_L3_IPV4_EXT,
3143                 RTE_PTYPE_L3_IPV6,
3144                 RTE_PTYPE_L3_IPV6_EXT,
3145                 RTE_PTYPE_L4_SCTP,
3146                 RTE_PTYPE_L4_TCP,
3147                 RTE_PTYPE_L4_UDP,
3148                 RTE_PTYPE_TUNNEL_IP,
3149                 RTE_PTYPE_INNER_L3_IPV6,
3150                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3151                 RTE_PTYPE_INNER_L4_TCP,
3152                 RTE_PTYPE_INNER_L4_UDP,
3153                 RTE_PTYPE_UNKNOWN
3154         };
3155
3156         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3157             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3158             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3159             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3160                 return ptypes;
3161         return NULL;
3162 }
3163
3164 static void
3165 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3166                      struct rte_eth_dev_info *dev_info)
3167 {
3168         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3169         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3170
3171         dev_info->pci_dev = pci_dev;
3172         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3173         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3174         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3175         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3176         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3177         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3178         dev_info->max_vfs = pci_dev->max_vfs;
3179         if (hw->mac.type == ixgbe_mac_82598EB)
3180                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3181         else
3182                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3183         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3184                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3185                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3186                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3187         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3188                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3189                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3190                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3191                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3192                                 DEV_TX_OFFLOAD_TCP_TSO;
3193
3194         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3195                 .rx_thresh = {
3196                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3197                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3198                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3199                 },
3200                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3201                 .rx_drop_en = 0,
3202         };
3203
3204         dev_info->default_txconf = (struct rte_eth_txconf) {
3205                 .tx_thresh = {
3206                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3207                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3208                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3209                 },
3210                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3211                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3212                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3213                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3214         };
3215
3216         dev_info->rx_desc_lim = rx_desc_lim;
3217         dev_info->tx_desc_lim = tx_desc_lim;
3218 }
3219
3220 /* return 0 means link status changed, -1 means not changed */
3221 static int
3222 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3223 {
3224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3225         struct rte_eth_link link, old;
3226         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3227         int link_up;
3228         int diag;
3229
3230         link.link_status = ETH_LINK_DOWN;
3231         link.link_speed = 0;
3232         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3233         memset(&old, 0, sizeof(old));
3234         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3235
3236         hw->mac.get_link_status = true;
3237
3238         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3239         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3240                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3241         else
3242                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3243
3244         if (diag != 0) {
3245                 link.link_speed = ETH_SPEED_NUM_100M;
3246                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3247                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3248                 if (link.link_status == old.link_status)
3249                         return -1;
3250                 return 0;
3251         }
3252
3253         if (link_up == 0) {
3254                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3255                 if (link.link_status == old.link_status)
3256                         return -1;
3257                 return 0;
3258         }
3259         link.link_status = ETH_LINK_UP;
3260         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3261
3262         switch (link_speed) {
3263         default:
3264         case IXGBE_LINK_SPEED_UNKNOWN:
3265                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3266                 link.link_speed = ETH_SPEED_NUM_100M;
3267                 break;
3268
3269         case IXGBE_LINK_SPEED_100_FULL:
3270                 link.link_speed = ETH_SPEED_NUM_100M;
3271                 break;
3272
3273         case IXGBE_LINK_SPEED_1GB_FULL:
3274                 link.link_speed = ETH_SPEED_NUM_1G;
3275                 break;
3276
3277         case IXGBE_LINK_SPEED_10GB_FULL:
3278                 link.link_speed = ETH_SPEED_NUM_10G;
3279                 break;
3280         }
3281         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3282
3283         if (link.link_status == old.link_status)
3284                 return -1;
3285
3286         return 0;
3287 }
3288
3289 static void
3290 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3291 {
3292         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3293         uint32_t fctrl;
3294
3295         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3296         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3297         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3298 }
3299
3300 static void
3301 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3302 {
3303         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3304         uint32_t fctrl;
3305
3306         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3307         fctrl &= (~IXGBE_FCTRL_UPE);
3308         if (dev->data->all_multicast == 1)
3309                 fctrl |= IXGBE_FCTRL_MPE;
3310         else
3311                 fctrl &= (~IXGBE_FCTRL_MPE);
3312         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3313 }
3314
3315 static void
3316 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3317 {
3318         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3319         uint32_t fctrl;
3320
3321         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3322         fctrl |= IXGBE_FCTRL_MPE;
3323         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3324 }
3325
3326 static void
3327 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3328 {
3329         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3330         uint32_t fctrl;
3331
3332         if (dev->data->promiscuous == 1)
3333                 return; /* must remain in all_multicast mode */
3334
3335         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3336         fctrl &= (~IXGBE_FCTRL_MPE);
3337         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3338 }
3339
3340 /**
3341  * It clears the interrupt causes and enables the interrupt.
3342  * It will be called once only during nic initialized.
3343  *
3344  * @param dev
3345  *  Pointer to struct rte_eth_dev.
3346  *
3347  * @return
3348  *  - On success, zero.
3349  *  - On failure, a negative value.
3350  */
3351 static int
3352 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3353 {
3354         struct ixgbe_interrupt *intr =
3355                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3356
3357         ixgbe_dev_link_status_print(dev);
3358         intr->mask |= IXGBE_EICR_LSC;
3359
3360         return 0;
3361 }
3362
3363 /**
3364  * It clears the interrupt causes and enables the interrupt.
3365  * It will be called once only during nic initialized.
3366  *
3367  * @param dev
3368  *  Pointer to struct rte_eth_dev.
3369  *
3370  * @return
3371  *  - On success, zero.
3372  *  - On failure, a negative value.
3373  */
3374 static int
3375 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3376 {
3377         struct ixgbe_interrupt *intr =
3378                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3379
3380         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3381
3382         return 0;
3383 }
3384
3385 /*
3386  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3387  *
3388  * @param dev
3389  *  Pointer to struct rte_eth_dev.
3390  *
3391  * @return
3392  *  - On success, zero.
3393  *  - On failure, a negative value.
3394  */
3395 static int
3396 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3397 {
3398         uint32_t eicr;
3399         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3400         struct ixgbe_interrupt *intr =
3401                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3402
3403         /* clear all cause mask */
3404         ixgbe_disable_intr(hw);
3405
3406         /* read-on-clear nic registers here */
3407         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3408         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3409
3410         intr->flags = 0;
3411
3412         /* set flag for async link update */
3413         if (eicr & IXGBE_EICR_LSC)
3414                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3415
3416         if (eicr & IXGBE_EICR_MAILBOX)
3417                 intr->flags |= IXGBE_FLAG_MAILBOX;
3418
3419         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3420             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3421             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3422                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3423
3424         return 0;
3425 }
3426
3427 /**
3428  * It gets and then prints the link status.
3429  *
3430  * @param dev
3431  *  Pointer to struct rte_eth_dev.
3432  *
3433  * @return
3434  *  - On success, zero.
3435  *  - On failure, a negative value.
3436  */
3437 static void
3438 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3439 {
3440         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3441         struct rte_eth_link link;
3442
3443         memset(&link, 0, sizeof(link));
3444         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3445         if (link.link_status) {
3446                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3447                                         (int)(dev->data->port_id),
3448                                         (unsigned)link.link_speed,
3449                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3450                                         "full-duplex" : "half-duplex");
3451         } else {
3452                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3453                                 (int)(dev->data->port_id));
3454         }
3455         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3456                                 pci_dev->addr.domain,
3457                                 pci_dev->addr.bus,
3458                                 pci_dev->addr.devid,
3459                                 pci_dev->addr.function);
3460 }
3461
3462 /*
3463  * It executes link_update after knowing an interrupt occurred.
3464  *
3465  * @param dev
3466  *  Pointer to struct rte_eth_dev.
3467  *
3468  * @return
3469  *  - On success, zero.
3470  *  - On failure, a negative value.
3471  */
3472 static int
3473 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3474                            struct rte_intr_handle *intr_handle)
3475 {
3476         struct ixgbe_interrupt *intr =
3477                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3478         int64_t timeout;
3479         struct rte_eth_link link;
3480         int intr_enable_delay = false;
3481         struct ixgbe_hw *hw =
3482                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3483
3484         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3485
3486         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3487                 ixgbe_pf_mbx_process(dev);
3488                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3489         }
3490
3491         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3492                 ixgbe_handle_lasi(hw);
3493                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3494         }
3495
3496         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3497                 /* get the link status before link update, for predicting later */
3498                 memset(&link, 0, sizeof(link));
3499                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3500
3501                 ixgbe_dev_link_update(dev, 0);
3502
3503                 /* likely to up */
3504                 if (!link.link_status)
3505                         /* handle it 1 sec later, wait it being stable */
3506                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3507                 /* likely to down */
3508                 else
3509                         /* handle it 4 sec later, wait it being stable */
3510                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3511
3512                 ixgbe_dev_link_status_print(dev);
3513
3514                 intr_enable_delay = true;
3515         }
3516
3517         if (intr_enable_delay) {
3518                 if (rte_eal_alarm_set(timeout * 1000,
3519                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3520                         PMD_DRV_LOG(ERR, "Error setting alarm");
3521         } else {
3522                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3523                 ixgbe_enable_intr(dev);
3524                 rte_intr_enable(intr_handle);
3525         }
3526
3527
3528         return 0;
3529 }
3530
3531 /**
3532  * Interrupt handler which shall be registered for alarm callback for delayed
3533  * handling specific interrupt to wait for the stable nic state. As the
3534  * NIC interrupt state is not stable for ixgbe after link is just down,
3535  * it needs to wait 4 seconds to get the stable status.
3536  *
3537  * @param handle
3538  *  Pointer to interrupt handle.
3539  * @param param
3540  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3541  *
3542  * @return
3543  *  void
3544  */
3545 static void
3546 ixgbe_dev_interrupt_delayed_handler(void *param)
3547 {
3548         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3549         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3550         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3551         struct ixgbe_interrupt *intr =
3552                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3553         struct ixgbe_hw *hw =
3554                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3555         uint32_t eicr;
3556
3557         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3558         if (eicr & IXGBE_EICR_MAILBOX)
3559                 ixgbe_pf_mbx_process(dev);
3560
3561         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3562                 ixgbe_handle_lasi(hw);
3563                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3564         }
3565
3566         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3567                 ixgbe_dev_link_update(dev, 0);
3568                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3569                 ixgbe_dev_link_status_print(dev);
3570                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3571         }
3572
3573         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3574         ixgbe_enable_intr(dev);
3575         rte_intr_enable(intr_handle);
3576 }
3577
3578 /**
3579  * Interrupt handler triggered by NIC  for handling
3580  * specific interrupt.
3581  *
3582  * @param handle
3583  *  Pointer to interrupt handle.
3584  * @param param
3585  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3586  *
3587  * @return
3588  *  void
3589  */
3590 static void
3591 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3592                             void *param)
3593 {
3594         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3595
3596         ixgbe_dev_interrupt_get_status(dev);
3597         ixgbe_dev_interrupt_action(dev, handle);
3598 }
3599
3600 static int
3601 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3602 {
3603         struct ixgbe_hw *hw;
3604
3605         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3606         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3607 }
3608
3609 static int
3610 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3611 {
3612         struct ixgbe_hw *hw;
3613
3614         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3615         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3616 }
3617
3618 static int
3619 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3620 {
3621         struct ixgbe_hw *hw;
3622         uint32_t mflcn_reg;
3623         uint32_t fccfg_reg;
3624         int rx_pause;
3625         int tx_pause;
3626
3627         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3628
3629         fc_conf->pause_time = hw->fc.pause_time;
3630         fc_conf->high_water = hw->fc.high_water[0];
3631         fc_conf->low_water = hw->fc.low_water[0];
3632         fc_conf->send_xon = hw->fc.send_xon;
3633         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3634
3635         /*
3636          * Return rx_pause status according to actual setting of
3637          * MFLCN register.
3638          */
3639         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3640         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3641                 rx_pause = 1;
3642         else
3643                 rx_pause = 0;
3644
3645         /*
3646          * Return tx_pause status according to actual setting of
3647          * FCCFG register.
3648          */
3649         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3650         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3651                 tx_pause = 1;
3652         else
3653                 tx_pause = 0;
3654
3655         if (rx_pause && tx_pause)
3656                 fc_conf->mode = RTE_FC_FULL;
3657         else if (rx_pause)
3658                 fc_conf->mode = RTE_FC_RX_PAUSE;
3659         else if (tx_pause)
3660                 fc_conf->mode = RTE_FC_TX_PAUSE;
3661         else
3662                 fc_conf->mode = RTE_FC_NONE;
3663
3664         return 0;
3665 }
3666
3667 static int
3668 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3669 {
3670         struct ixgbe_hw *hw;
3671         int err;
3672         uint32_t rx_buf_size;
3673         uint32_t max_high_water;
3674         uint32_t mflcn;
3675         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3676                 ixgbe_fc_none,
3677                 ixgbe_fc_rx_pause,
3678                 ixgbe_fc_tx_pause,
3679                 ixgbe_fc_full
3680         };
3681
3682         PMD_INIT_FUNC_TRACE();
3683
3684         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3685         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3686         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3687
3688         /*
3689          * At least reserve one Ethernet frame for watermark
3690          * high_water/low_water in kilo bytes for ixgbe
3691          */
3692         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3693         if ((fc_conf->high_water > max_high_water) ||
3694                 (fc_conf->high_water < fc_conf->low_water)) {
3695                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3696                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3697                 return -EINVAL;
3698         }
3699
3700         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3701         hw->fc.pause_time     = fc_conf->pause_time;
3702         hw->fc.high_water[0]  = fc_conf->high_water;
3703         hw->fc.low_water[0]   = fc_conf->low_water;
3704         hw->fc.send_xon       = fc_conf->send_xon;
3705         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3706
3707         err = ixgbe_fc_enable(hw);
3708
3709         /* Not negotiated is not an error case */
3710         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3711
3712                 /* check if we want to forward MAC frames - driver doesn't have native
3713                  * capability to do that, so we'll write the registers ourselves */
3714
3715                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3716
3717                 /* set or clear MFLCN.PMCF bit depending on configuration */
3718                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3719                         mflcn |= IXGBE_MFLCN_PMCF;
3720                 else
3721                         mflcn &= ~IXGBE_MFLCN_PMCF;
3722
3723                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3724                 IXGBE_WRITE_FLUSH(hw);
3725
3726                 return 0;
3727         }
3728
3729         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3730         return -EIO;
3731 }
3732
3733 /**
3734  *  ixgbe_pfc_enable_generic - Enable flow control
3735  *  @hw: pointer to hardware structure
3736  *  @tc_num: traffic class number
3737  *  Enable flow control according to the current settings.
3738  */
3739 static int
3740 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3741 {
3742         int ret_val = 0;
3743         uint32_t mflcn_reg, fccfg_reg;
3744         uint32_t reg;
3745         uint32_t fcrtl, fcrth;
3746         uint8_t i;
3747         uint8_t nb_rx_en;
3748
3749         /* Validate the water mark configuration */
3750         if (!hw->fc.pause_time) {
3751                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3752                 goto out;
3753         }
3754
3755         /* Low water mark of zero causes XOFF floods */
3756         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3757                  /* High/Low water can not be 0 */
3758                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3759                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3760                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3761                         goto out;
3762                 }
3763
3764                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3765                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3766                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3767                         goto out;
3768                 }
3769         }
3770         /* Negotiate the fc mode to use */
3771         ixgbe_fc_autoneg(hw);
3772
3773         /* Disable any previous flow control settings */
3774         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3775         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3776
3777         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3778         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3779
3780         switch (hw->fc.current_mode) {
3781         case ixgbe_fc_none:
3782                 /*
3783                  * If the count of enabled RX Priority Flow control >1,
3784                  * and the TX pause can not be disabled
3785                  */
3786                 nb_rx_en = 0;
3787                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3788                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3789                         if (reg & IXGBE_FCRTH_FCEN)
3790                                 nb_rx_en++;
3791                 }
3792                 if (nb_rx_en > 1)
3793                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3794                 break;
3795         case ixgbe_fc_rx_pause:
3796                 /*
3797                  * Rx Flow control is enabled and Tx Flow control is
3798                  * disabled by software override. Since there really
3799                  * isn't a way to advertise that we are capable of RX
3800                  * Pause ONLY, we will advertise that we support both
3801                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3802                  * disable the adapter's ability to send PAUSE frames.
3803                  */
3804                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3805                 /*
3806                  * If the count of enabled RX Priority Flow control >1,
3807                  * and the TX pause can not be disabled
3808                  */
3809                 nb_rx_en = 0;
3810                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3811                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3812                         if (reg & IXGBE_FCRTH_FCEN)
3813                                 nb_rx_en++;
3814                 }
3815                 if (nb_rx_en > 1)
3816                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3817                 break;
3818         case ixgbe_fc_tx_pause:
3819                 /*
3820                  * Tx Flow control is enabled, and Rx Flow control is
3821                  * disabled by software override.
3822                  */
3823                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3824                 break;
3825         case ixgbe_fc_full:
3826                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3827                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3828                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3829                 break;
3830         default:
3831                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3832                 ret_val = IXGBE_ERR_CONFIG;
3833                 goto out;
3834         }
3835
3836         /* Set 802.3x based flow control settings. */
3837         mflcn_reg |= IXGBE_MFLCN_DPF;
3838         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3839         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3840
3841         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3842         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3843                 hw->fc.high_water[tc_num]) {
3844                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3845                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3846                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3847         } else {
3848                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3849                 /*
3850                  * In order to prevent Tx hangs when the internal Tx
3851                  * switch is enabled we must set the high water mark
3852                  * to the maximum FCRTH value.  This allows the Tx
3853                  * switch to function even under heavy Rx workloads.
3854                  */
3855                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3856         }
3857         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3858
3859         /* Configure pause time (2 TCs per register) */
3860         reg = hw->fc.pause_time * 0x00010001;
3861         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3862                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3863
3864         /* Configure flow control refresh threshold value */
3865         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3866
3867 out:
3868         return ret_val;
3869 }
3870
3871 static int
3872 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3873 {
3874         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3875         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3876
3877         if (hw->mac.type != ixgbe_mac_82598EB) {
3878                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3879         }
3880         return ret_val;
3881 }
3882
3883 static int
3884 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3885 {
3886         int err;
3887         uint32_t rx_buf_size;
3888         uint32_t max_high_water;
3889         uint8_t tc_num;
3890         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3891         struct ixgbe_hw *hw =
3892                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3893         struct ixgbe_dcb_config *dcb_config =
3894                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3895
3896         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3897                 ixgbe_fc_none,
3898                 ixgbe_fc_rx_pause,
3899                 ixgbe_fc_tx_pause,
3900                 ixgbe_fc_full
3901         };
3902
3903         PMD_INIT_FUNC_TRACE();
3904
3905         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3906         tc_num = map[pfc_conf->priority];
3907         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3908         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3909         /*
3910          * At least reserve one Ethernet frame for watermark
3911          * high_water/low_water in kilo bytes for ixgbe
3912          */
3913         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3914         if ((pfc_conf->fc.high_water > max_high_water) ||
3915             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3916                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3917                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3918                 return -EINVAL;
3919         }
3920
3921         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3922         hw->fc.pause_time = pfc_conf->fc.pause_time;
3923         hw->fc.send_xon = pfc_conf->fc.send_xon;
3924         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3925         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3926
3927         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3928
3929         /* Not negotiated is not an error case */
3930         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3931                 return 0;
3932
3933         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3934         return -EIO;
3935 }
3936
3937 static int
3938 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3939                           struct rte_eth_rss_reta_entry64 *reta_conf,
3940                           uint16_t reta_size)
3941 {
3942         uint16_t i, sp_reta_size;
3943         uint8_t j, mask;
3944         uint32_t reta, r;
3945         uint16_t idx, shift;
3946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3947         uint32_t reta_reg;
3948
3949         PMD_INIT_FUNC_TRACE();
3950
3951         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3952                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3953                         "NIC.");
3954                 return -ENOTSUP;
3955         }
3956
3957         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3958         if (reta_size != sp_reta_size) {
3959                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3960                         "(%d) doesn't match the number hardware can supported "
3961                         "(%d)\n", reta_size, sp_reta_size);
3962                 return -EINVAL;
3963         }
3964
3965         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3966                 idx = i / RTE_RETA_GROUP_SIZE;
3967                 shift = i % RTE_RETA_GROUP_SIZE;
3968                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3969                                                 IXGBE_4_BIT_MASK);
3970                 if (!mask)
3971                         continue;
3972                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3973                 if (mask == IXGBE_4_BIT_MASK)
3974                         r = 0;
3975                 else
3976                         r = IXGBE_READ_REG(hw, reta_reg);
3977                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3978                         if (mask & (0x1 << j))
3979                                 reta |= reta_conf[idx].reta[shift + j] <<
3980                                                         (CHAR_BIT * j);
3981                         else
3982                                 reta |= r & (IXGBE_8_BIT_MASK <<
3983                                                 (CHAR_BIT * j));
3984                 }
3985                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3986         }
3987
3988         return 0;
3989 }
3990
3991 static int
3992 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3993                          struct rte_eth_rss_reta_entry64 *reta_conf,
3994                          uint16_t reta_size)
3995 {
3996         uint16_t i, sp_reta_size;
3997         uint8_t j, mask;
3998         uint32_t reta;
3999         uint16_t idx, shift;
4000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4001         uint32_t reta_reg;
4002
4003         PMD_INIT_FUNC_TRACE();
4004         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4005         if (reta_size != sp_reta_size) {
4006                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4007                         "(%d) doesn't match the number hardware can supported "
4008                         "(%d)\n", reta_size, sp_reta_size);
4009                 return -EINVAL;
4010         }
4011
4012         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4013                 idx = i / RTE_RETA_GROUP_SIZE;
4014                 shift = i % RTE_RETA_GROUP_SIZE;
4015                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4016                                                 IXGBE_4_BIT_MASK);
4017                 if (!mask)
4018                         continue;
4019
4020                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4021                 reta = IXGBE_READ_REG(hw, reta_reg);
4022                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4023                         if (mask & (0x1 << j))
4024                                 reta_conf[idx].reta[shift + j] =
4025                                         ((reta >> (CHAR_BIT * j)) &
4026                                                 IXGBE_8_BIT_MASK);
4027                 }
4028         }
4029
4030         return 0;
4031 }
4032
4033 static void
4034 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4035                                 uint32_t index, uint32_t pool)
4036 {
4037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4038         uint32_t enable_addr = 1;
4039
4040         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4041 }
4042
4043 static void
4044 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4045 {
4046         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4047
4048         ixgbe_clear_rar(hw, index);
4049 }
4050
4051 static void
4052 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4053 {
4054         ixgbe_remove_rar(dev, 0);
4055
4056         ixgbe_add_rar(dev, addr, 0, 0);
4057 }
4058
4059 int
4060 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4061                 struct ether_addr *mac_addr)
4062 {
4063         struct ixgbe_hw *hw;
4064         struct ixgbe_vf_info *vfinfo;
4065         int rar_entry;
4066         uint8_t *new_mac = (uint8_t *)(mac_addr);
4067         struct rte_eth_dev *dev;
4068         struct rte_eth_dev_info dev_info;
4069
4070         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4071
4072         dev = &rte_eth_devices[port];
4073         rte_eth_dev_info_get(port, &dev_info);
4074
4075         if (vf >= dev_info.max_vfs)
4076                 return -EINVAL;
4077
4078         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4079         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4080         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4081
4082         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4083                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4084                                 ETHER_ADDR_LEN);
4085                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4086                                 IXGBE_RAH_AV);
4087         }
4088         return -EINVAL;
4089 }
4090
4091 static int
4092 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4093 {
4094         uint32_t hlreg0;
4095         uint32_t maxfrs;
4096         struct ixgbe_hw *hw;
4097         struct rte_eth_dev_info dev_info;
4098         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4099
4100         ixgbe_dev_info_get(dev, &dev_info);
4101
4102         /* check that mtu is within the allowed range */
4103         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4104                 return -EINVAL;
4105
4106         /* refuse mtu that requires the support of scattered packets when this
4107          * feature has not been enabled before.
4108          */
4109         if (!dev->data->scattered_rx &&
4110             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4111              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4112                 return -EINVAL;
4113
4114         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4115         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4116
4117         /* switch to jumbo mode if needed */
4118         if (frame_size > ETHER_MAX_LEN) {
4119                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4120                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4121         } else {
4122                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4123                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4124         }
4125         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4126
4127         /* update max frame size */
4128         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4129
4130         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4131         maxfrs &= 0x0000FFFF;
4132         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4133         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4134
4135         return 0;
4136 }
4137
4138 /*
4139  * Virtual Function operations
4140  */
4141 static void
4142 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4143 {
4144         PMD_INIT_FUNC_TRACE();
4145
4146         /* Clear interrupt mask to stop from interrupts being generated */
4147         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4148
4149         IXGBE_WRITE_FLUSH(hw);
4150 }
4151
4152 static void
4153 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4154 {
4155         PMD_INIT_FUNC_TRACE();
4156
4157         /* VF enable interrupt autoclean */
4158         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4159         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4160         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4161
4162         IXGBE_WRITE_FLUSH(hw);
4163 }
4164
4165 static int
4166 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4167 {
4168         struct rte_eth_conf *conf = &dev->data->dev_conf;
4169         struct ixgbe_adapter *adapter =
4170                         (struct ixgbe_adapter *)dev->data->dev_private;
4171
4172         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4173                      dev->data->port_id);
4174
4175         /*
4176          * VF has no ability to enable/disable HW CRC
4177          * Keep the persistent behavior the same as Host PF
4178          */
4179 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4180         if (!conf->rxmode.hw_strip_crc) {
4181                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4182                 conf->rxmode.hw_strip_crc = 1;
4183         }
4184 #else
4185         if (conf->rxmode.hw_strip_crc) {
4186                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4187                 conf->rxmode.hw_strip_crc = 0;
4188         }
4189 #endif
4190
4191         /*
4192          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4193          * allocation or vector Rx preconditions we will reset it.
4194          */
4195         adapter->rx_bulk_alloc_allowed = true;
4196         adapter->rx_vec_allowed = true;
4197
4198         return 0;
4199 }
4200
4201 static int
4202 ixgbevf_dev_start(struct rte_eth_dev *dev)
4203 {
4204         struct ixgbe_hw *hw =
4205                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4206         uint32_t intr_vector = 0;
4207         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4208         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4209
4210         int err, mask = 0;
4211
4212         PMD_INIT_FUNC_TRACE();
4213
4214         hw->mac.ops.reset_hw(hw);
4215         hw->mac.get_link_status = true;
4216
4217         /* negotiate mailbox API version to use with the PF. */
4218         ixgbevf_negotiate_api(hw);
4219
4220         ixgbevf_dev_tx_init(dev);
4221
4222         /* This can fail when allocating mbufs for descriptor rings */
4223         err = ixgbevf_dev_rx_init(dev);
4224         if (err) {
4225                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4226                 ixgbe_dev_clear_queues(dev);
4227                 return err;
4228         }
4229
4230         /* Set vfta */
4231         ixgbevf_set_vfta_all(dev, 1);
4232
4233         /* Set HW strip */
4234         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4235                 ETH_VLAN_EXTEND_MASK;
4236         ixgbevf_vlan_offload_set(dev, mask);
4237
4238         ixgbevf_dev_rxtx_start(dev);
4239
4240         /* check and configure queue intr-vector mapping */
4241         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4242                 intr_vector = dev->data->nb_rx_queues;
4243                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4244                         return -1;
4245         }
4246
4247         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4248                 intr_handle->intr_vec =
4249                         rte_zmalloc("intr_vec",
4250                                     dev->data->nb_rx_queues * sizeof(int), 0);
4251                 if (intr_handle->intr_vec == NULL) {
4252                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4253                                      " intr_vec\n", dev->data->nb_rx_queues);
4254                         return -ENOMEM;
4255                 }
4256         }
4257         ixgbevf_configure_msix(dev);
4258
4259         rte_intr_enable(intr_handle);
4260
4261         /* Re-enable interrupt for VF */
4262         ixgbevf_intr_enable(hw);
4263
4264         return 0;
4265 }
4266
4267 static void
4268 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4269 {
4270         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4271         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4272         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4273
4274         PMD_INIT_FUNC_TRACE();
4275
4276         ixgbevf_intr_disable(hw);
4277
4278         hw->adapter_stopped = 1;
4279         ixgbe_stop_adapter(hw);
4280
4281         /*
4282           * Clear what we set, but we still keep shadow_vfta to
4283           * restore after device starts
4284           */
4285         ixgbevf_set_vfta_all(dev, 0);
4286
4287         /* Clear stored conf */
4288         dev->data->scattered_rx = 0;
4289
4290         ixgbe_dev_clear_queues(dev);
4291
4292         /* Clean datapath event and queue/vec mapping */
4293         rte_intr_efd_disable(intr_handle);
4294         if (intr_handle->intr_vec != NULL) {
4295                 rte_free(intr_handle->intr_vec);
4296                 intr_handle->intr_vec = NULL;
4297         }
4298 }
4299
4300 static void
4301 ixgbevf_dev_close(struct rte_eth_dev *dev)
4302 {
4303         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4304
4305         PMD_INIT_FUNC_TRACE();
4306
4307         ixgbe_reset_hw(hw);
4308
4309         ixgbevf_dev_stop(dev);
4310
4311         ixgbe_dev_free_queues(dev);
4312
4313         /**
4314          * Remove the VF MAC address ro ensure
4315          * that the VF traffic goes to the PF
4316          * after stop, close and detach of the VF
4317          **/
4318         ixgbevf_remove_mac_addr(dev, 0);
4319 }
4320
4321 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4322 {
4323         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4324         struct ixgbe_vfta *shadow_vfta =
4325                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4326         int i = 0, j = 0, vfta = 0, mask = 1;
4327
4328         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4329                 vfta = shadow_vfta->vfta[i];
4330                 if (vfta) {
4331                         mask = 1;
4332                         for (j = 0; j < 32; j++) {
4333                                 if (vfta & mask)
4334                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4335                                                        on, false);
4336                                 mask <<= 1;
4337                         }
4338                 }
4339         }
4340
4341 }
4342
4343 static int
4344 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4345 {
4346         struct ixgbe_hw *hw =
4347                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4348         struct ixgbe_vfta *shadow_vfta =
4349                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4350         uint32_t vid_idx = 0;
4351         uint32_t vid_bit = 0;
4352         int ret = 0;
4353
4354         PMD_INIT_FUNC_TRACE();
4355
4356         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4357         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4358         if (ret) {
4359                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4360                 return ret;
4361         }
4362         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4363         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4364
4365         /* Save what we set and retore it after device reset */
4366         if (on)
4367                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4368         else
4369                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4370
4371         return 0;
4372 }
4373
4374 static void
4375 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4376 {
4377         struct ixgbe_hw *hw =
4378                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4379         uint32_t ctrl;
4380
4381         PMD_INIT_FUNC_TRACE();
4382
4383         if (queue >= hw->mac.max_rx_queues)
4384                 return;
4385
4386         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4387         if (on)
4388                 ctrl |= IXGBE_RXDCTL_VME;
4389         else
4390                 ctrl &= ~IXGBE_RXDCTL_VME;
4391         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4392
4393         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4394 }
4395
4396 static void
4397 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4398 {
4399         struct ixgbe_hw *hw =
4400                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4401         uint16_t i;
4402         int on = 0;
4403
4404         /* VF function only support hw strip feature, others are not support */
4405         if (mask & ETH_VLAN_STRIP_MASK) {
4406                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4407
4408                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4409                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4410         }
4411 }
4412
4413 static int
4414 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4415 {
4416         uint32_t reg_val;
4417
4418         /* we only need to do this if VMDq is enabled */
4419         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4420         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4421                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4422                 return -1;
4423         }
4424
4425         return 0;
4426 }
4427
4428 static uint32_t
4429 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4430 {
4431         uint32_t vector = 0;
4432
4433         switch (hw->mac.mc_filter_type) {
4434         case 0:   /* use bits [47:36] of the address */
4435                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4436                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4437                 break;
4438         case 1:   /* use bits [46:35] of the address */
4439                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4440                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4441                 break;
4442         case 2:   /* use bits [45:34] of the address */
4443                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4444                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4445                 break;
4446         case 3:   /* use bits [43:32] of the address */
4447                 vector = ((uc_addr->addr_bytes[4]) |
4448                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4449                 break;
4450         default:  /* Invalid mc_filter_type */
4451                 break;
4452         }
4453
4454         /* vector can only be 12-bits or boundary will be exceeded */
4455         vector &= 0xFFF;
4456         return vector;
4457 }
4458
4459 static int
4460 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4461                         uint8_t on)
4462 {
4463         uint32_t vector;
4464         uint32_t uta_idx;
4465         uint32_t reg_val;
4466         uint32_t uta_shift;
4467         uint32_t rc;
4468         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4469         const uint32_t ixgbe_uta_bit_shift = 5;
4470         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4471         const uint32_t bit1 = 0x1;
4472
4473         struct ixgbe_hw *hw =
4474                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4475         struct ixgbe_uta_info *uta_info =
4476                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4477
4478         /* The UTA table only exists on 82599 hardware and newer */
4479         if (hw->mac.type < ixgbe_mac_82599EB)
4480                 return -ENOTSUP;
4481
4482         vector = ixgbe_uta_vector(hw, mac_addr);
4483         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4484         uta_shift = vector & ixgbe_uta_bit_mask;
4485
4486         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4487         if (rc == on)
4488                 return 0;
4489
4490         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4491         if (on) {
4492                 uta_info->uta_in_use++;
4493                 reg_val |= (bit1 << uta_shift);
4494                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4495         } else {
4496                 uta_info->uta_in_use--;
4497                 reg_val &= ~(bit1 << uta_shift);
4498                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4499         }
4500
4501         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4502
4503         if (uta_info->uta_in_use > 0)
4504                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4505                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4506         else
4507                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4508
4509         return 0;
4510 }
4511
4512 static int
4513 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4514 {
4515         int i;
4516         struct ixgbe_hw *hw =
4517                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4518         struct ixgbe_uta_info *uta_info =
4519                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4520
4521         /* The UTA table only exists on 82599 hardware and newer */
4522         if (hw->mac.type < ixgbe_mac_82599EB)
4523                 return -ENOTSUP;
4524
4525         if (on) {
4526                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4527                         uta_info->uta_shadow[i] = ~0;
4528                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4529                 }
4530         } else {
4531                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4532                         uta_info->uta_shadow[i] = 0;
4533                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4534                 }
4535         }
4536         return 0;
4537
4538 }
4539
4540 uint32_t
4541 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4542 {
4543         uint32_t new_val = orig_val;
4544
4545         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4546                 new_val |= IXGBE_VMOLR_AUPE;
4547         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4548                 new_val |= IXGBE_VMOLR_ROMPE;
4549         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4550                 new_val |= IXGBE_VMOLR_ROPE;
4551         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4552                 new_val |= IXGBE_VMOLR_BAM;
4553         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4554                 new_val |= IXGBE_VMOLR_MPE;
4555
4556         return new_val;
4557 }
4558
4559 static int
4560 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4561                                uint16_t rx_mask, uint8_t on)
4562 {
4563         int val = 0;
4564
4565         struct ixgbe_hw *hw =
4566                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4567         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4568
4569         if (hw->mac.type == ixgbe_mac_82598EB) {
4570                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4571                              " on 82599 hardware and newer");
4572                 return -ENOTSUP;
4573         }
4574         if (ixgbe_vmdq_mode_check(hw) < 0)
4575                 return -ENOTSUP;
4576
4577         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4578
4579         if (on)
4580                 vmolr |= val;
4581         else
4582                 vmolr &= ~val;
4583
4584         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4585
4586         return 0;
4587 }
4588
4589 static int
4590 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4591 {
4592         uint32_t reg, addr;
4593         uint32_t val;
4594         const uint8_t bit1 = 0x1;
4595
4596         struct ixgbe_hw *hw =
4597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4598
4599         if (ixgbe_vmdq_mode_check(hw) < 0)
4600                 return -ENOTSUP;
4601
4602         if (pool >= ETH_64_POOLS)
4603                 return -EINVAL;
4604
4605         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4606         if (pool >= 32) {
4607                 addr = IXGBE_VFRE(1);
4608                 val = bit1 << (pool - 32);
4609         } else {
4610                 addr = IXGBE_VFRE(0);
4611                 val = bit1 << pool;
4612         }
4613
4614         reg = IXGBE_READ_REG(hw, addr);
4615
4616         if (on)
4617                 reg |= val;
4618         else
4619                 reg &= ~val;
4620
4621         IXGBE_WRITE_REG(hw, addr, reg);
4622
4623         return 0;
4624 }
4625
4626 static int
4627 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4628 {
4629         uint32_t reg, addr;
4630         uint32_t val;
4631         const uint8_t bit1 = 0x1;
4632
4633         struct ixgbe_hw *hw =
4634                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4635
4636         if (ixgbe_vmdq_mode_check(hw) < 0)
4637                 return -ENOTSUP;
4638
4639         if (pool >= ETH_64_POOLS)
4640                 return -EINVAL;
4641
4642         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4643         if (pool >= 32) {
4644                 addr = IXGBE_VFTE(1);
4645                 val = bit1 << (pool - 32);
4646         } else {
4647                 addr = IXGBE_VFTE(0);
4648                 val = bit1 << pool;
4649         }
4650
4651         reg = IXGBE_READ_REG(hw, addr);
4652
4653         if (on)
4654                 reg |= val;
4655         else
4656                 reg &= ~val;
4657
4658         IXGBE_WRITE_REG(hw, addr, reg);
4659
4660         return 0;
4661 }
4662
4663 static int
4664 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4665                         uint64_t pool_mask, uint8_t vlan_on)
4666 {
4667         int ret = 0;
4668         uint16_t pool_idx;
4669         struct ixgbe_hw *hw =
4670                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4671
4672         if (ixgbe_vmdq_mode_check(hw) < 0)
4673                 return -ENOTSUP;
4674         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4675                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4676                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4677                                                    vlan_on, false);
4678                         if (ret < 0)
4679                                 return ret;
4680                 }
4681         }
4682
4683         return ret;
4684 }
4685
4686 int
4687 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4688 {
4689         struct ixgbe_hw *hw;
4690         struct ixgbe_mac_info *mac;
4691         struct rte_eth_dev *dev;
4692         struct rte_eth_dev_info dev_info;
4693
4694         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4695
4696         dev = &rte_eth_devices[port];
4697         rte_eth_dev_info_get(port, &dev_info);
4698
4699         if (vf >= dev_info.max_vfs)
4700                 return -EINVAL;
4701
4702         if (on > 1)
4703                 return -EINVAL;
4704
4705         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4706         mac = &hw->mac;
4707
4708         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4709
4710         return 0;
4711 }
4712
4713 int
4714 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4715 {
4716         struct ixgbe_hw *hw;
4717         struct ixgbe_mac_info *mac;
4718         struct rte_eth_dev *dev;
4719         struct rte_eth_dev_info dev_info;
4720
4721         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4722
4723         dev = &rte_eth_devices[port];
4724         rte_eth_dev_info_get(port, &dev_info);
4725
4726         if (vf >= dev_info.max_vfs)
4727                 return -EINVAL;
4728
4729         if (on > 1)
4730                 return -EINVAL;
4731
4732         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4733         mac = &hw->mac;
4734         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4735
4736         return 0;
4737 }
4738
4739 int
4740 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4741 {
4742         struct ixgbe_hw *hw;
4743         uint32_t ctrl;
4744         struct rte_eth_dev *dev;
4745         struct rte_eth_dev_info dev_info;
4746
4747         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4748
4749         dev = &rte_eth_devices[port];
4750         rte_eth_dev_info_get(port, &dev_info);
4751
4752         if (vf >= dev_info.max_vfs)
4753                 return -EINVAL;
4754
4755         if (vlan_id > 4095)
4756                 return -EINVAL;
4757
4758         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4759         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4760         if (vlan_id) {
4761                 ctrl = vlan_id;
4762                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4763         } else {
4764                 ctrl = 0;
4765         }
4766
4767         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4768
4769         return 0;
4770 }
4771
4772 int
4773 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4774 {
4775         struct ixgbe_hw *hw;
4776         uint32_t ctrl;
4777         struct rte_eth_dev *dev;
4778
4779         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4780
4781         dev = &rte_eth_devices[port];
4782
4783         if (on > 1)
4784                 return -EINVAL;
4785
4786         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4787         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4788         /* enable or disable VMDQ loopback */
4789         if (on)
4790                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4791         else
4792                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4793
4794         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4795
4796         return 0;
4797 }
4798
4799 int
4800 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4801 {
4802         struct ixgbe_hw *hw;
4803         uint32_t reg_value;
4804         int i;
4805         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4806         struct rte_eth_dev *dev;
4807
4808         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4809
4810         dev = &rte_eth_devices[port];
4811
4812         if (on > 1)
4813                 return -EINVAL;
4814
4815         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4816         for (i = 0; i <= num_queues; i++) {
4817                 reg_value = IXGBE_QDE_WRITE |
4818                                 (i << IXGBE_QDE_IDX_SHIFT) |
4819                                 (on & IXGBE_QDE_ENABLE);
4820                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
4821         }
4822
4823         return 0;
4824 }
4825
4826 int
4827 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
4828 {
4829         struct ixgbe_hw *hw;
4830         uint32_t reg_value;
4831         struct rte_eth_dev *dev;
4832         struct rte_eth_dev_info dev_info;
4833
4834         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4835
4836         dev = &rte_eth_devices[port];
4837         rte_eth_dev_info_get(port, &dev_info);
4838
4839         /* only support VF's 0 to 63 */
4840         if ((vf >= dev_info.max_vfs) || (vf > 63))
4841                 return -EINVAL;
4842
4843         if (on > 1)
4844                 return -EINVAL;
4845
4846         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4847         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
4848         if (on)
4849                 reg_value |= IXGBE_SRRCTL_DROP_EN;
4850         else
4851                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
4852
4853         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
4854
4855         return 0;
4856 }
4857
4858 int
4859 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
4860 {
4861         struct rte_eth_dev *dev;
4862         struct rte_eth_dev_info dev_info;
4863         uint16_t queues_per_pool;
4864         uint32_t q;
4865
4866         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4867
4868         dev = &rte_eth_devices[port];
4869         rte_eth_dev_info_get(port, &dev_info);
4870
4871         if (vf >= dev_info.max_vfs)
4872                 return -EINVAL;
4873
4874         if (on > 1)
4875                 return -EINVAL;
4876
4877         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
4878
4879         /* The PF has 128 queue pairs and in SRIOV configuration
4880          * those queues will be assigned to VF's, so RXDCTL
4881          * registers will be dealing with queues which will be
4882          * assigned to VF's.
4883          * Let's say we have SRIOV configured with 31 VF's then the
4884          * first 124 queues 0-123 will be allocated to VF's and only
4885          * the last 4 queues 123-127 will be assigned to the PF.
4886          */
4887
4888         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
4889
4890         for (q = 0; q < queues_per_pool; q++)
4891                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
4892                                 q + vf * queues_per_pool, on);
4893         return 0;
4894 }
4895
4896 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4897 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4898 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4899 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4900 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4901         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4902         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4903
4904 static int
4905 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4906                         struct rte_eth_mirror_conf *mirror_conf,
4907                         uint8_t rule_id, uint8_t on)
4908 {
4909         uint32_t mr_ctl, vlvf;
4910         uint32_t mp_lsb = 0;
4911         uint32_t mv_msb = 0;
4912         uint32_t mv_lsb = 0;
4913         uint32_t mp_msb = 0;
4914         uint8_t i = 0;
4915         int reg_index = 0;
4916         uint64_t vlan_mask = 0;
4917
4918         const uint8_t pool_mask_offset = 32;
4919         const uint8_t vlan_mask_offset = 32;
4920         const uint8_t dst_pool_offset = 8;
4921         const uint8_t rule_mr_offset  = 4;
4922         const uint8_t mirror_rule_mask = 0x0F;
4923
4924         struct ixgbe_mirror_info *mr_info =
4925                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4926         struct ixgbe_hw *hw =
4927                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4928         uint8_t mirror_type = 0;
4929
4930         if (ixgbe_vmdq_mode_check(hw) < 0)
4931                 return -ENOTSUP;
4932
4933         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4934                 return -EINVAL;
4935
4936         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4937                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4938                         mirror_conf->rule_type);
4939                 return -EINVAL;
4940         }
4941
4942         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4943                 mirror_type |= IXGBE_MRCTL_VLME;
4944                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4945                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4946                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4947                                 /* search vlan id related pool vlan filter index */
4948                                 reg_index = ixgbe_find_vlvf_slot(hw,
4949                                                  mirror_conf->vlan.vlan_id[i],
4950                                                  false);
4951                                 if (reg_index < 0)
4952                                         return -EINVAL;
4953                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4954                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4955                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4956                                       mirror_conf->vlan.vlan_id[i]))
4957                                         vlan_mask |= (1ULL << reg_index);
4958                                 else
4959                                         return -EINVAL;
4960                         }
4961                 }
4962
4963                 if (on) {
4964                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4965                         mv_msb = vlan_mask >> vlan_mask_offset;
4966
4967                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4968                                                 mirror_conf->vlan.vlan_mask;
4969                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4970                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4971                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4972                                                 mirror_conf->vlan.vlan_id[i];
4973                         }
4974                 } else {
4975                         mv_lsb = 0;
4976                         mv_msb = 0;
4977                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4978                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4979                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4980                 }
4981         }
4982
4983         /*
4984          * if enable pool mirror, write related pool mask register,if disable
4985          * pool mirror, clear PFMRVM register
4986          */
4987         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4988                 mirror_type |= IXGBE_MRCTL_VPME;
4989                 if (on) {
4990                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4991                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4992                         mr_info->mr_conf[rule_id].pool_mask =
4993                                         mirror_conf->pool_mask;
4994
4995                 } else {
4996                         mp_lsb = 0;
4997                         mp_msb = 0;
4998                         mr_info->mr_conf[rule_id].pool_mask = 0;
4999                 }
5000         }
5001         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5002                 mirror_type |= IXGBE_MRCTL_UPME;
5003         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5004                 mirror_type |= IXGBE_MRCTL_DPME;
5005
5006         /* read  mirror control register and recalculate it */
5007         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5008
5009         if (on) {
5010                 mr_ctl |= mirror_type;
5011                 mr_ctl &= mirror_rule_mask;
5012                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5013         } else
5014                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5015
5016         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5017         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5018
5019         /* write mirrror control  register */
5020         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5021
5022         /* write pool mirrror control  register */
5023         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5024                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5025                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5026                                 mp_msb);
5027         }
5028         /* write VLAN mirrror control  register */
5029         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5030                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5031                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5032                                 mv_msb);
5033         }
5034
5035         return 0;
5036 }
5037
5038 static int
5039 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5040 {
5041         int mr_ctl = 0;
5042         uint32_t lsb_val = 0;
5043         uint32_t msb_val = 0;
5044         const uint8_t rule_mr_offset = 4;
5045
5046         struct ixgbe_hw *hw =
5047                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5048         struct ixgbe_mirror_info *mr_info =
5049                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5050
5051         if (ixgbe_vmdq_mode_check(hw) < 0)
5052                 return -ENOTSUP;
5053
5054         memset(&mr_info->mr_conf[rule_id], 0,
5055                 sizeof(struct rte_eth_mirror_conf));
5056
5057         /* clear PFVMCTL register */
5058         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5059
5060         /* clear pool mask register */
5061         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5062         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5063
5064         /* clear vlan mask register */
5065         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5066         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5067
5068         return 0;
5069 }
5070
5071 static int
5072 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5073 {
5074         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5075         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5076         uint32_t mask;
5077         struct ixgbe_hw *hw =
5078                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5079
5080         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5081         mask |= (1 << IXGBE_MISC_VEC_ID);
5082         RTE_SET_USED(queue_id);
5083         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5084
5085         rte_intr_enable(intr_handle);
5086
5087         return 0;
5088 }
5089
5090 static int
5091 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5092 {
5093         uint32_t mask;
5094         struct ixgbe_hw *hw =
5095                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5096
5097         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5098         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5099         RTE_SET_USED(queue_id);
5100         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5101
5102         return 0;
5103 }
5104
5105 static int
5106 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5107 {
5108         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5109         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5110         uint32_t mask;
5111         struct ixgbe_hw *hw =
5112                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5113         struct ixgbe_interrupt *intr =
5114                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5115
5116         if (queue_id < 16) {
5117                 ixgbe_disable_intr(hw);
5118                 intr->mask |= (1 << queue_id);
5119                 ixgbe_enable_intr(dev);
5120         } else if (queue_id < 32) {
5121                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5122                 mask &= (1 << queue_id);
5123                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5124         } else if (queue_id < 64) {
5125                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5126                 mask &= (1 << (queue_id - 32));
5127                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5128         }
5129         rte_intr_enable(intr_handle);
5130
5131         return 0;
5132 }
5133
5134 static int
5135 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5136 {
5137         uint32_t mask;
5138         struct ixgbe_hw *hw =
5139                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5140         struct ixgbe_interrupt *intr =
5141                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5142
5143         if (queue_id < 16) {
5144                 ixgbe_disable_intr(hw);
5145                 intr->mask &= ~(1 << queue_id);
5146                 ixgbe_enable_intr(dev);
5147         } else if (queue_id < 32) {
5148                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5149                 mask &= ~(1 << queue_id);
5150                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5151         } else if (queue_id < 64) {
5152                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5153                 mask &= ~(1 << (queue_id - 32));
5154                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5155         }
5156
5157         return 0;
5158 }
5159
5160 static void
5161 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5162                      uint8_t queue, uint8_t msix_vector)
5163 {
5164         uint32_t tmp, idx;
5165
5166         if (direction == -1) {
5167                 /* other causes */
5168                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5169                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5170                 tmp &= ~0xFF;
5171                 tmp |= msix_vector;
5172                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5173         } else {
5174                 /* rx or tx cause */
5175                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5176                 idx = ((16 * (queue & 1)) + (8 * direction));
5177                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5178                 tmp &= ~(0xFF << idx);
5179                 tmp |= (msix_vector << idx);
5180                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5181         }
5182 }
5183
5184 /**
5185  * set the IVAR registers, mapping interrupt causes to vectors
5186  * @param hw
5187  *  pointer to ixgbe_hw struct
5188  * @direction
5189  *  0 for Rx, 1 for Tx, -1 for other causes
5190  * @queue
5191  *  queue to map the corresponding interrupt to
5192  * @msix_vector
5193  *  the vector to map to the corresponding queue
5194  */
5195 static void
5196 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5197                    uint8_t queue, uint8_t msix_vector)
5198 {
5199         uint32_t tmp, idx;
5200
5201         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5202         if (hw->mac.type == ixgbe_mac_82598EB) {
5203                 if (direction == -1)
5204                         direction = 0;
5205                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5206                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5207                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5208                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5209                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5210         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5211                         (hw->mac.type == ixgbe_mac_X540)) {
5212                 if (direction == -1) {
5213                         /* other causes */
5214                         idx = ((queue & 1) * 8);
5215                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5216                         tmp &= ~(0xFF << idx);
5217                         tmp |= (msix_vector << idx);
5218                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5219                 } else {
5220                         /* rx or tx causes */
5221                         idx = ((16 * (queue & 1)) + (8 * direction));
5222                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5223                         tmp &= ~(0xFF << idx);
5224                         tmp |= (msix_vector << idx);
5225                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5226                 }
5227         }
5228 }
5229
5230 static void
5231 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5232 {
5233         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5234         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5235         struct ixgbe_hw *hw =
5236                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5237         uint32_t q_idx;
5238         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5239
5240         /* Configure VF other cause ivar */
5241         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5242
5243         /* won't configure msix register if no mapping is done
5244          * between intr vector and event fd.
5245          */
5246         if (!rte_intr_dp_is_en(intr_handle))
5247                 return;
5248
5249         /* Configure all RX queues of VF */
5250         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5251                 /* Force all queue use vector 0,
5252                  * as IXGBE_VF_MAXMSIVECOTR = 1
5253                  */
5254                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5255                 intr_handle->intr_vec[q_idx] = vector_idx;
5256         }
5257 }
5258
5259 /**
5260  * Sets up the hardware to properly generate MSI-X interrupts
5261  * @hw
5262  *  board private structure
5263  */
5264 static void
5265 ixgbe_configure_msix(struct rte_eth_dev *dev)
5266 {
5267         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5268         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5269         struct ixgbe_hw *hw =
5270                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5271         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5272         uint32_t vec = IXGBE_MISC_VEC_ID;
5273         uint32_t mask;
5274         uint32_t gpie;
5275
5276         /* won't configure msix register if no mapping is done
5277          * between intr vector and event fd
5278          */
5279         if (!rte_intr_dp_is_en(intr_handle))
5280                 return;
5281
5282         if (rte_intr_allow_others(intr_handle))
5283                 vec = base = IXGBE_RX_VEC_START;
5284
5285         /* setup GPIE for MSI-x mode */
5286         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5287         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5288                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5289         /* auto clearing and auto setting corresponding bits in EIMS
5290          * when MSI-X interrupt is triggered
5291          */
5292         if (hw->mac.type == ixgbe_mac_82598EB) {
5293                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5294         } else {
5295                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5296                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5297         }
5298         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5299
5300         /* Populate the IVAR table and set the ITR values to the
5301          * corresponding register.
5302          */
5303         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5304              queue_id++) {
5305                 /* by default, 1:1 mapping */
5306                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5307                 intr_handle->intr_vec[queue_id] = vec;
5308                 if (vec < base + intr_handle->nb_efd - 1)
5309                         vec++;
5310         }
5311
5312         switch (hw->mac.type) {
5313         case ixgbe_mac_82598EB:
5314                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5315                                    IXGBE_MISC_VEC_ID);
5316                 break;
5317         case ixgbe_mac_82599EB:
5318         case ixgbe_mac_X540:
5319                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5320                 break;
5321         default:
5322                 break;
5323         }
5324         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5325                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5326
5327         /* set up to autoclear timer, and the vectors */
5328         mask = IXGBE_EIMS_ENABLE_MASK;
5329         mask &= ~(IXGBE_EIMS_OTHER |
5330                   IXGBE_EIMS_MAILBOX |
5331                   IXGBE_EIMS_LSC);
5332
5333         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5334 }
5335
5336 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5337         uint16_t queue_idx, uint16_t tx_rate)
5338 {
5339         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5340         uint32_t rf_dec, rf_int;
5341         uint32_t bcnrc_val;
5342         uint16_t link_speed = dev->data->dev_link.link_speed;
5343
5344         if (queue_idx >= hw->mac.max_tx_queues)
5345                 return -EINVAL;
5346
5347         if (tx_rate != 0) {
5348                 /* Calculate the rate factor values to set */
5349                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5350                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5351                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5352
5353                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5354                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5355                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5356                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5357         } else {
5358                 bcnrc_val = 0;
5359         }
5360
5361         /*
5362          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5363          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5364          * set as 0x4.
5365          */
5366         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5367                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5368                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5369                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5370                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5371         else
5372                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5373                         IXGBE_MMW_SIZE_DEFAULT);
5374
5375         /* Set RTTBCNRC of queue X */
5376         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5377         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5378         IXGBE_WRITE_FLUSH(hw);
5379
5380         return 0;
5381 }
5382
5383 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5384         uint16_t tx_rate, uint64_t q_msk)
5385 {
5386         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5387         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5388         struct ixgbe_vf_info *vfinfo =
5389                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5390         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5391         uint32_t queue_stride =
5392                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5393         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5394         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5395         uint16_t total_rate = 0;
5396
5397         if (queue_end >= hw->mac.max_tx_queues)
5398                 return -EINVAL;
5399
5400         if (vfinfo != NULL) {
5401                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5402                         if (vf_idx == vf)
5403                                 continue;
5404                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5405                                 idx++)
5406                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5407                 }
5408         } else
5409                 return -EINVAL;
5410
5411         /* Store tx_rate for this vf. */
5412         for (idx = 0; idx < nb_q_per_pool; idx++) {
5413                 if (((uint64_t)0x1 << idx) & q_msk) {
5414                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5415                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5416                         total_rate += tx_rate;
5417                 }
5418         }
5419
5420         if (total_rate > dev->data->dev_link.link_speed) {
5421                 /*
5422                  * Reset stored TX rate of the VF if it causes exceed
5423                  * link speed.
5424                  */
5425                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5426                 return -EINVAL;
5427         }
5428
5429         /* Set RTTBCNRC of each queue/pool for vf X  */
5430         for (; queue_idx <= queue_end; queue_idx++) {
5431                 if (0x1 & q_msk)
5432                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5433                 q_msk = q_msk >> 1;
5434         }
5435
5436         return 0;
5437 }
5438
5439 static void
5440 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5441                      __attribute__((unused)) uint32_t index,
5442                      __attribute__((unused)) uint32_t pool)
5443 {
5444         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5445         int diag;
5446
5447         /*
5448          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5449          * operation. Trap this case to avoid exhausting the [very limited]
5450          * set of PF resources used to store VF MAC addresses.
5451          */
5452         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5453                 return;
5454         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5455         if (diag == 0)
5456                 return;
5457         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5458 }
5459
5460 static void
5461 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5462 {
5463         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5464         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5465         struct ether_addr *mac_addr;
5466         uint32_t i;
5467         int diag;
5468
5469         /*
5470          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5471          * not support the deletion of a given MAC address.
5472          * Instead, it imposes to delete all MAC addresses, then to add again
5473          * all MAC addresses with the exception of the one to be deleted.
5474          */
5475         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5476
5477         /*
5478          * Add again all MAC addresses, with the exception of the deleted one
5479          * and of the permanent MAC address.
5480          */
5481         for (i = 0, mac_addr = dev->data->mac_addrs;
5482              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5483                 /* Skip the deleted MAC address */
5484                 if (i == index)
5485                         continue;
5486                 /* Skip NULL MAC addresses */
5487                 if (is_zero_ether_addr(mac_addr))
5488                         continue;
5489                 /* Skip the permanent MAC address */
5490                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5491                         continue;
5492                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5493                 if (diag != 0)
5494                         PMD_DRV_LOG(ERR,
5495                                     "Adding again MAC address "
5496                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5497                                     "diag=%d",
5498                                     mac_addr->addr_bytes[0],
5499                                     mac_addr->addr_bytes[1],
5500                                     mac_addr->addr_bytes[2],
5501                                     mac_addr->addr_bytes[3],
5502                                     mac_addr->addr_bytes[4],
5503                                     mac_addr->addr_bytes[5],
5504                                     diag);
5505         }
5506 }
5507
5508 static void
5509 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5510 {
5511         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5512
5513         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5514 }
5515
5516 #define MAC_TYPE_FILTER_SUP(type)    do {\
5517         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5518                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5519                 (type) != ixgbe_mac_X550EM_a)\
5520                 return -ENOTSUP;\
5521 } while (0)
5522
5523 static int
5524 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5525                         struct rte_eth_syn_filter *filter,
5526                         bool add)
5527 {
5528         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5529         uint32_t synqf;
5530
5531         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5532                 return -EINVAL;
5533
5534         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5535
5536         if (add) {
5537                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5538                         return -EINVAL;
5539                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5540                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5541
5542                 if (filter->hig_pri)
5543                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5544                 else
5545                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5546         } else {
5547                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5548                         return -ENOENT;
5549                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5550         }
5551         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5552         IXGBE_WRITE_FLUSH(hw);
5553         return 0;
5554 }
5555
5556 static int
5557 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5558                         struct rte_eth_syn_filter *filter)
5559 {
5560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5561         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5562
5563         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5564                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5565                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5566                 return 0;
5567         }
5568         return -ENOENT;
5569 }
5570
5571 static int
5572 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5573                         enum rte_filter_op filter_op,
5574                         void *arg)
5575 {
5576         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5577         int ret;
5578
5579         MAC_TYPE_FILTER_SUP(hw->mac.type);
5580
5581         if (filter_op == RTE_ETH_FILTER_NOP)
5582                 return 0;
5583
5584         if (arg == NULL) {
5585                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5586                             filter_op);
5587                 return -EINVAL;
5588         }
5589
5590         switch (filter_op) {
5591         case RTE_ETH_FILTER_ADD:
5592                 ret = ixgbe_syn_filter_set(dev,
5593                                 (struct rte_eth_syn_filter *)arg,
5594                                 TRUE);
5595                 break;
5596         case RTE_ETH_FILTER_DELETE:
5597                 ret = ixgbe_syn_filter_set(dev,
5598                                 (struct rte_eth_syn_filter *)arg,
5599                                 FALSE);
5600                 break;
5601         case RTE_ETH_FILTER_GET:
5602                 ret = ixgbe_syn_filter_get(dev,
5603                                 (struct rte_eth_syn_filter *)arg);
5604                 break;
5605         default:
5606                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5607                 ret = -EINVAL;
5608                 break;
5609         }
5610
5611         return ret;
5612 }
5613
5614
5615 static inline enum ixgbe_5tuple_protocol
5616 convert_protocol_type(uint8_t protocol_value)
5617 {
5618         if (protocol_value == IPPROTO_TCP)
5619                 return IXGBE_FILTER_PROTOCOL_TCP;
5620         else if (protocol_value == IPPROTO_UDP)
5621                 return IXGBE_FILTER_PROTOCOL_UDP;
5622         else if (protocol_value == IPPROTO_SCTP)
5623                 return IXGBE_FILTER_PROTOCOL_SCTP;
5624         else
5625                 return IXGBE_FILTER_PROTOCOL_NONE;
5626 }
5627
5628 /*
5629  * add a 5tuple filter
5630  *
5631  * @param
5632  * dev: Pointer to struct rte_eth_dev.
5633  * index: the index the filter allocates.
5634  * filter: ponter to the filter that will be added.
5635  * rx_queue: the queue id the filter assigned to.
5636  *
5637  * @return
5638  *    - On success, zero.
5639  *    - On failure, a negative value.
5640  */
5641 static int
5642 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5643                         struct ixgbe_5tuple_filter *filter)
5644 {
5645         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5646         struct ixgbe_filter_info *filter_info =
5647                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5648         int i, idx, shift;
5649         uint32_t ftqf, sdpqf;
5650         uint32_t l34timir = 0;
5651         uint8_t mask = 0xff;
5652
5653         /*
5654          * look for an unused 5tuple filter index,
5655          * and insert the filter to list.
5656          */
5657         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5658                 idx = i / (sizeof(uint32_t) * NBBY);
5659                 shift = i % (sizeof(uint32_t) * NBBY);
5660                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5661                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5662                         filter->index = i;
5663                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5664                                           filter,
5665                                           entries);
5666                         break;
5667                 }
5668         }
5669         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5670                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5671                 return -ENOSYS;
5672         }
5673
5674         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5675                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5676         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5677
5678         ftqf = (uint32_t)(filter->filter_info.proto &
5679                 IXGBE_FTQF_PROTOCOL_MASK);
5680         ftqf |= (uint32_t)((filter->filter_info.priority &
5681                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5682         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5683                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5684         if (filter->filter_info.dst_ip_mask == 0)
5685                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5686         if (filter->filter_info.src_port_mask == 0)
5687                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5688         if (filter->filter_info.dst_port_mask == 0)
5689                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5690         if (filter->filter_info.proto_mask == 0)
5691                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5692         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5693         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5694         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5695
5696         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5697         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5698         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5699         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5700
5701         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5702         l34timir |= (uint32_t)(filter->queue <<
5703                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5704         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5705         return 0;
5706 }
5707
5708 /*
5709  * remove a 5tuple filter
5710  *
5711  * @param
5712  * dev: Pointer to struct rte_eth_dev.
5713  * filter: the pointer of the filter will be removed.
5714  */
5715 static void
5716 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5717                         struct ixgbe_5tuple_filter *filter)
5718 {
5719         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5720         struct ixgbe_filter_info *filter_info =
5721                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5722         uint16_t index = filter->index;
5723
5724         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5725                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5726         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5727         rte_free(filter);
5728
5729         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5730         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5731         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5732         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5733         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5734 }
5735
5736 static int
5737 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5738 {
5739         struct ixgbe_hw *hw;
5740         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5741
5742         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5743
5744         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5745                 return -EINVAL;
5746
5747         /* refuse mtu that requires the support of scattered packets when this
5748          * feature has not been enabled before.
5749          */
5750         if (!dev->data->scattered_rx &&
5751             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5752              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5753                 return -EINVAL;
5754
5755         /*
5756          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5757          * request of the version 2.0 of the mailbox API.
5758          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5759          * of the mailbox API.
5760          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5761          * prior to 3.11.33 which contains the following change:
5762          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5763          */
5764         ixgbevf_rlpml_set_vf(hw, max_frame);
5765
5766         /* update max frame size */
5767         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5768         return 0;
5769 }
5770
5771 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5772         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5773                 return -ENOTSUP;\
5774 } while (0)
5775
5776 static inline struct ixgbe_5tuple_filter *
5777 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5778                         struct ixgbe_5tuple_filter_info *key)
5779 {
5780         struct ixgbe_5tuple_filter *it;
5781
5782         TAILQ_FOREACH(it, filter_list, entries) {
5783                 if (memcmp(key, &it->filter_info,
5784                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5785                         return it;
5786                 }
5787         }
5788         return NULL;
5789 }
5790
5791 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5792 static inline int
5793 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5794                         struct ixgbe_5tuple_filter_info *filter_info)
5795 {
5796         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5797                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5798                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5799                 return -EINVAL;
5800
5801         switch (filter->dst_ip_mask) {
5802         case UINT32_MAX:
5803                 filter_info->dst_ip_mask = 0;
5804                 filter_info->dst_ip = filter->dst_ip;
5805                 break;
5806         case 0:
5807                 filter_info->dst_ip_mask = 1;
5808                 break;
5809         default:
5810                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5811                 return -EINVAL;
5812         }
5813
5814         switch (filter->src_ip_mask) {
5815         case UINT32_MAX:
5816                 filter_info->src_ip_mask = 0;
5817                 filter_info->src_ip = filter->src_ip;
5818                 break;
5819         case 0:
5820                 filter_info->src_ip_mask = 1;
5821                 break;
5822         default:
5823                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5824                 return -EINVAL;
5825         }
5826
5827         switch (filter->dst_port_mask) {
5828         case UINT16_MAX:
5829                 filter_info->dst_port_mask = 0;
5830                 filter_info->dst_port = filter->dst_port;
5831                 break;
5832         case 0:
5833                 filter_info->dst_port_mask = 1;
5834                 break;
5835         default:
5836                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5837                 return -EINVAL;
5838         }
5839
5840         switch (filter->src_port_mask) {
5841         case UINT16_MAX:
5842                 filter_info->src_port_mask = 0;
5843                 filter_info->src_port = filter->src_port;
5844                 break;
5845         case 0:
5846                 filter_info->src_port_mask = 1;
5847                 break;
5848         default:
5849                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5850                 return -EINVAL;
5851         }
5852
5853         switch (filter->proto_mask) {
5854         case UINT8_MAX:
5855                 filter_info->proto_mask = 0;
5856                 filter_info->proto =
5857                         convert_protocol_type(filter->proto);
5858                 break;
5859         case 0:
5860                 filter_info->proto_mask = 1;
5861                 break;
5862         default:
5863                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5864                 return -EINVAL;
5865         }
5866
5867         filter_info->priority = (uint8_t)filter->priority;
5868         return 0;
5869 }
5870
5871 /*
5872  * add or delete a ntuple filter
5873  *
5874  * @param
5875  * dev: Pointer to struct rte_eth_dev.
5876  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5877  * add: if true, add filter, if false, remove filter
5878  *
5879  * @return
5880  *    - On success, zero.
5881  *    - On failure, a negative value.
5882  */
5883 static int
5884 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5885                         struct rte_eth_ntuple_filter *ntuple_filter,
5886                         bool add)
5887 {
5888         struct ixgbe_filter_info *filter_info =
5889                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5890         struct ixgbe_5tuple_filter_info filter_5tuple;
5891         struct ixgbe_5tuple_filter *filter;
5892         int ret;
5893
5894         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5895                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5896                 return -EINVAL;
5897         }
5898
5899         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5900         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5901         if (ret < 0)
5902                 return ret;
5903
5904         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5905                                          &filter_5tuple);
5906         if (filter != NULL && add) {
5907                 PMD_DRV_LOG(ERR, "filter exists.");
5908                 return -EEXIST;
5909         }
5910         if (filter == NULL && !add) {
5911                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5912                 return -ENOENT;
5913         }
5914
5915         if (add) {
5916                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5917                                 sizeof(struct ixgbe_5tuple_filter), 0);
5918                 if (filter == NULL)
5919                         return -ENOMEM;
5920                 (void)rte_memcpy(&filter->filter_info,
5921                                  &filter_5tuple,
5922                                  sizeof(struct ixgbe_5tuple_filter_info));
5923                 filter->queue = ntuple_filter->queue;
5924                 ret = ixgbe_add_5tuple_filter(dev, filter);
5925                 if (ret < 0) {
5926                         rte_free(filter);
5927                         return ret;
5928                 }
5929         } else
5930                 ixgbe_remove_5tuple_filter(dev, filter);
5931
5932         return 0;
5933 }
5934
5935 /*
5936  * get a ntuple filter
5937  *
5938  * @param
5939  * dev: Pointer to struct rte_eth_dev.
5940  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5941  *
5942  * @return
5943  *    - On success, zero.
5944  *    - On failure, a negative value.
5945  */
5946 static int
5947 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5948                         struct rte_eth_ntuple_filter *ntuple_filter)
5949 {
5950         struct ixgbe_filter_info *filter_info =
5951                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5952         struct ixgbe_5tuple_filter_info filter_5tuple;
5953         struct ixgbe_5tuple_filter *filter;
5954         int ret;
5955
5956         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5957                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5958                 return -EINVAL;
5959         }
5960
5961         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5962         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5963         if (ret < 0)
5964                 return ret;
5965
5966         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5967                                          &filter_5tuple);
5968         if (filter == NULL) {
5969                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5970                 return -ENOENT;
5971         }
5972         ntuple_filter->queue = filter->queue;
5973         return 0;
5974 }
5975
5976 /*
5977  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5978  * @dev: pointer to rte_eth_dev structure
5979  * @filter_op:operation will be taken.
5980  * @arg: a pointer to specific structure corresponding to the filter_op
5981  *
5982  * @return
5983  *    - On success, zero.
5984  *    - On failure, a negative value.
5985  */
5986 static int
5987 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5988                                 enum rte_filter_op filter_op,
5989                                 void *arg)
5990 {
5991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5992         int ret;
5993
5994         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5995
5996         if (filter_op == RTE_ETH_FILTER_NOP)
5997                 return 0;
5998
5999         if (arg == NULL) {
6000                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6001                             filter_op);
6002                 return -EINVAL;
6003         }
6004
6005         switch (filter_op) {
6006         case RTE_ETH_FILTER_ADD:
6007                 ret = ixgbe_add_del_ntuple_filter(dev,
6008                         (struct rte_eth_ntuple_filter *)arg,
6009                         TRUE);
6010                 break;
6011         case RTE_ETH_FILTER_DELETE:
6012                 ret = ixgbe_add_del_ntuple_filter(dev,
6013                         (struct rte_eth_ntuple_filter *)arg,
6014                         FALSE);
6015                 break;
6016         case RTE_ETH_FILTER_GET:
6017                 ret = ixgbe_get_ntuple_filter(dev,
6018                         (struct rte_eth_ntuple_filter *)arg);
6019                 break;
6020         default:
6021                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6022                 ret = -EINVAL;
6023                 break;
6024         }
6025         return ret;
6026 }
6027
6028 static inline int
6029 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6030                         uint16_t ethertype)
6031 {
6032         int i;
6033
6034         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6035                 if (filter_info->ethertype_filters[i] == ethertype &&
6036                     (filter_info->ethertype_mask & (1 << i)))
6037                         return i;
6038         }
6039         return -1;
6040 }
6041
6042 static inline int
6043 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6044                         uint16_t ethertype)
6045 {
6046         int i;
6047
6048         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6049                 if (!(filter_info->ethertype_mask & (1 << i))) {
6050                         filter_info->ethertype_mask |= 1 << i;
6051                         filter_info->ethertype_filters[i] = ethertype;
6052                         return i;
6053                 }
6054         }
6055         return -1;
6056 }
6057
6058 static inline int
6059 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6060                         uint8_t idx)
6061 {
6062         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6063                 return -1;
6064         filter_info->ethertype_mask &= ~(1 << idx);
6065         filter_info->ethertype_filters[idx] = 0;
6066         return idx;
6067 }
6068
6069 static int
6070 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6071                         struct rte_eth_ethertype_filter *filter,
6072                         bool add)
6073 {
6074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6075         struct ixgbe_filter_info *filter_info =
6076                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6077         uint32_t etqf = 0;
6078         uint32_t etqs = 0;
6079         int ret;
6080
6081         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6082                 return -EINVAL;
6083
6084         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6085                 filter->ether_type == ETHER_TYPE_IPv6) {
6086                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6087                         " ethertype filter.", filter->ether_type);
6088                 return -EINVAL;
6089         }
6090
6091         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6092                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6093                 return -EINVAL;
6094         }
6095         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6096                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6097                 return -EINVAL;
6098         }
6099
6100         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6101         if (ret >= 0 && add) {
6102                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6103                             filter->ether_type);
6104                 return -EEXIST;
6105         }
6106         if (ret < 0 && !add) {
6107                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6108                             filter->ether_type);
6109                 return -ENOENT;
6110         }
6111
6112         if (add) {
6113                 ret = ixgbe_ethertype_filter_insert(filter_info,
6114                         filter->ether_type);
6115                 if (ret < 0) {
6116                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6117                         return -ENOSYS;
6118                 }
6119                 etqf = IXGBE_ETQF_FILTER_EN;
6120                 etqf |= (uint32_t)filter->ether_type;
6121                 etqs |= (uint32_t)((filter->queue <<
6122                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6123                                     IXGBE_ETQS_RX_QUEUE);
6124                 etqs |= IXGBE_ETQS_QUEUE_EN;
6125         } else {
6126                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6127                 if (ret < 0)
6128                         return -ENOSYS;
6129         }
6130         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6131         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6132         IXGBE_WRITE_FLUSH(hw);
6133
6134         return 0;
6135 }
6136
6137 static int
6138 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6139                         struct rte_eth_ethertype_filter *filter)
6140 {
6141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6142         struct ixgbe_filter_info *filter_info =
6143                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6144         uint32_t etqf, etqs;
6145         int ret;
6146
6147         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6148         if (ret < 0) {
6149                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6150                             filter->ether_type);
6151                 return -ENOENT;
6152         }
6153
6154         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6155         if (etqf & IXGBE_ETQF_FILTER_EN) {
6156                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6157                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6158                 filter->flags = 0;
6159                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6160                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6161                 return 0;
6162         }
6163         return -ENOENT;
6164 }
6165
6166 /*
6167  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6168  * @dev: pointer to rte_eth_dev structure
6169  * @filter_op:operation will be taken.
6170  * @arg: a pointer to specific structure corresponding to the filter_op
6171  */
6172 static int
6173 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6174                                 enum rte_filter_op filter_op,
6175                                 void *arg)
6176 {
6177         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6178         int ret;
6179
6180         MAC_TYPE_FILTER_SUP(hw->mac.type);
6181
6182         if (filter_op == RTE_ETH_FILTER_NOP)
6183                 return 0;
6184
6185         if (arg == NULL) {
6186                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6187                             filter_op);
6188                 return -EINVAL;
6189         }
6190
6191         switch (filter_op) {
6192         case RTE_ETH_FILTER_ADD:
6193                 ret = ixgbe_add_del_ethertype_filter(dev,
6194                         (struct rte_eth_ethertype_filter *)arg,
6195                         TRUE);
6196                 break;
6197         case RTE_ETH_FILTER_DELETE:
6198                 ret = ixgbe_add_del_ethertype_filter(dev,
6199                         (struct rte_eth_ethertype_filter *)arg,
6200                         FALSE);
6201                 break;
6202         case RTE_ETH_FILTER_GET:
6203                 ret = ixgbe_get_ethertype_filter(dev,
6204                         (struct rte_eth_ethertype_filter *)arg);
6205                 break;
6206         default:
6207                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6208                 ret = -EINVAL;
6209                 break;
6210         }
6211         return ret;
6212 }
6213
6214 static int
6215 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6216                      enum rte_filter_type filter_type,
6217                      enum rte_filter_op filter_op,
6218                      void *arg)
6219 {
6220         int ret = -EINVAL;
6221
6222         switch (filter_type) {
6223         case RTE_ETH_FILTER_NTUPLE:
6224                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6225                 break;
6226         case RTE_ETH_FILTER_ETHERTYPE:
6227                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6228                 break;
6229         case RTE_ETH_FILTER_SYN:
6230                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6231                 break;
6232         case RTE_ETH_FILTER_FDIR:
6233                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6234                 break;
6235         case RTE_ETH_FILTER_L2_TUNNEL:
6236                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6237                 break;
6238         default:
6239                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6240                                                         filter_type);
6241                 break;
6242         }
6243
6244         return ret;
6245 }
6246
6247 static u8 *
6248 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6249                         u8 **mc_addr_ptr, u32 *vmdq)
6250 {
6251         u8 *mc_addr;
6252
6253         *vmdq = 0;
6254         mc_addr = *mc_addr_ptr;
6255         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6256         return mc_addr;
6257 }
6258
6259 static int
6260 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6261                           struct ether_addr *mc_addr_set,
6262                           uint32_t nb_mc_addr)
6263 {
6264         struct ixgbe_hw *hw;
6265         u8 *mc_addr_list;
6266
6267         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6268         mc_addr_list = (u8 *)mc_addr_set;
6269         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6270                                          ixgbe_dev_addr_list_itr, TRUE);
6271 }
6272
6273 static uint64_t
6274 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6275 {
6276         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6277         uint64_t systime_cycles;
6278
6279         switch (hw->mac.type) {
6280         case ixgbe_mac_X550:
6281         case ixgbe_mac_X550EM_x:
6282         case ixgbe_mac_X550EM_a:
6283                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6284                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6285                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6286                                 * NSEC_PER_SEC;
6287                 break;
6288         default:
6289                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6290                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6291                                 << 32;
6292         }
6293
6294         return systime_cycles;
6295 }
6296
6297 static uint64_t
6298 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6299 {
6300         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6301         uint64_t rx_tstamp_cycles;
6302
6303         switch (hw->mac.type) {
6304         case ixgbe_mac_X550:
6305         case ixgbe_mac_X550EM_x:
6306         case ixgbe_mac_X550EM_a:
6307                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6308                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6309                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6310                                 * NSEC_PER_SEC;
6311                 break;
6312         default:
6313                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6314                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6315                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6316                                 << 32;
6317         }
6318
6319         return rx_tstamp_cycles;
6320 }
6321
6322 static uint64_t
6323 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6324 {
6325         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6326         uint64_t tx_tstamp_cycles;
6327
6328         switch (hw->mac.type) {
6329         case ixgbe_mac_X550:
6330         case ixgbe_mac_X550EM_x:
6331         case ixgbe_mac_X550EM_a:
6332                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6333                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6334                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6335                                 * NSEC_PER_SEC;
6336                 break;
6337         default:
6338                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6339                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6340                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6341                                 << 32;
6342         }
6343
6344         return tx_tstamp_cycles;
6345 }
6346
6347 static void
6348 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6349 {
6350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6351         struct ixgbe_adapter *adapter =
6352                 (struct ixgbe_adapter *)dev->data->dev_private;
6353         struct rte_eth_link link;
6354         uint32_t incval = 0;
6355         uint32_t shift = 0;
6356
6357         /* Get current link speed. */
6358         memset(&link, 0, sizeof(link));
6359         ixgbe_dev_link_update(dev, 1);
6360         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6361
6362         switch (link.link_speed) {
6363         case ETH_SPEED_NUM_100M:
6364                 incval = IXGBE_INCVAL_100;
6365                 shift = IXGBE_INCVAL_SHIFT_100;
6366                 break;
6367         case ETH_SPEED_NUM_1G:
6368                 incval = IXGBE_INCVAL_1GB;
6369                 shift = IXGBE_INCVAL_SHIFT_1GB;
6370                 break;
6371         case ETH_SPEED_NUM_10G:
6372         default:
6373                 incval = IXGBE_INCVAL_10GB;
6374                 shift = IXGBE_INCVAL_SHIFT_10GB;
6375                 break;
6376         }
6377
6378         switch (hw->mac.type) {
6379         case ixgbe_mac_X550:
6380         case ixgbe_mac_X550EM_x:
6381         case ixgbe_mac_X550EM_a:
6382                 /* Independent of link speed. */
6383                 incval = 1;
6384                 /* Cycles read will be interpreted as ns. */
6385                 shift = 0;
6386                 /* Fall-through */
6387         case ixgbe_mac_X540:
6388                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6389                 break;
6390         case ixgbe_mac_82599EB:
6391                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6392                 shift -= IXGBE_INCVAL_SHIFT_82599;
6393                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6394                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6395                 break;
6396         default:
6397                 /* Not supported. */
6398                 return;
6399         }
6400
6401         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6402         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6403         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6404
6405         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6406         adapter->systime_tc.cc_shift = shift;
6407         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6408
6409         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6410         adapter->rx_tstamp_tc.cc_shift = shift;
6411         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6412
6413         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6414         adapter->tx_tstamp_tc.cc_shift = shift;
6415         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6416 }
6417
6418 static int
6419 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6420 {
6421         struct ixgbe_adapter *adapter =
6422                         (struct ixgbe_adapter *)dev->data->dev_private;
6423
6424         adapter->systime_tc.nsec += delta;
6425         adapter->rx_tstamp_tc.nsec += delta;
6426         adapter->tx_tstamp_tc.nsec += delta;
6427
6428         return 0;
6429 }
6430
6431 static int
6432 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6433 {
6434         uint64_t ns;
6435         struct ixgbe_adapter *adapter =
6436                         (struct ixgbe_adapter *)dev->data->dev_private;
6437
6438         ns = rte_timespec_to_ns(ts);
6439         /* Set the timecounters to a new value. */
6440         adapter->systime_tc.nsec = ns;
6441         adapter->rx_tstamp_tc.nsec = ns;
6442         adapter->tx_tstamp_tc.nsec = ns;
6443
6444         return 0;
6445 }
6446
6447 static int
6448 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6449 {
6450         uint64_t ns, systime_cycles;
6451         struct ixgbe_adapter *adapter =
6452                         (struct ixgbe_adapter *)dev->data->dev_private;
6453
6454         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6455         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6456         *ts = rte_ns_to_timespec(ns);
6457
6458         return 0;
6459 }
6460
6461 static int
6462 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6463 {
6464         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6465         uint32_t tsync_ctl;
6466         uint32_t tsauxc;
6467
6468         /* Stop the timesync system time. */
6469         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6470         /* Reset the timesync system time value. */
6471         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6472         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6473
6474         /* Enable system time for platforms where it isn't on by default. */
6475         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6476         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6477         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6478
6479         ixgbe_start_timecounters(dev);
6480
6481         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6482         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6483                         (ETHER_TYPE_1588 |
6484                          IXGBE_ETQF_FILTER_EN |
6485                          IXGBE_ETQF_1588));
6486
6487         /* Enable timestamping of received PTP packets. */
6488         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6489         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6490         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6491
6492         /* Enable timestamping of transmitted PTP packets. */
6493         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6494         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6495         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6496
6497         IXGBE_WRITE_FLUSH(hw);
6498
6499         return 0;
6500 }
6501
6502 static int
6503 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6504 {
6505         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6506         uint32_t tsync_ctl;
6507
6508         /* Disable timestamping of transmitted PTP packets. */
6509         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6510         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6511         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6512
6513         /* Disable timestamping of received PTP packets. */
6514         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6515         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6516         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6517
6518         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6519         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6520
6521         /* Stop incrementating the System Time registers. */
6522         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6523
6524         return 0;
6525 }
6526
6527 static int
6528 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6529                                  struct timespec *timestamp,
6530                                  uint32_t flags __rte_unused)
6531 {
6532         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6533         struct ixgbe_adapter *adapter =
6534                 (struct ixgbe_adapter *)dev->data->dev_private;
6535         uint32_t tsync_rxctl;
6536         uint64_t rx_tstamp_cycles;
6537         uint64_t ns;
6538
6539         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6540         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6541                 return -EINVAL;
6542
6543         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6544         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6545         *timestamp = rte_ns_to_timespec(ns);
6546
6547         return  0;
6548 }
6549
6550 static int
6551 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6552                                  struct timespec *timestamp)
6553 {
6554         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6555         struct ixgbe_adapter *adapter =
6556                 (struct ixgbe_adapter *)dev->data->dev_private;
6557         uint32_t tsync_txctl;
6558         uint64_t tx_tstamp_cycles;
6559         uint64_t ns;
6560
6561         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6562         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6563                 return -EINVAL;
6564
6565         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6566         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6567         *timestamp = rte_ns_to_timespec(ns);
6568
6569         return 0;
6570 }
6571
6572 static int
6573 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6574 {
6575         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6576         int count = 0;
6577         int g_ind = 0;
6578         const struct reg_info *reg_group;
6579         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6580                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6581
6582         while ((reg_group = reg_set[g_ind++]))
6583                 count += ixgbe_regs_group_count(reg_group);
6584
6585         return count;
6586 }
6587
6588 static int
6589 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6590 {
6591         int count = 0;
6592         int g_ind = 0;
6593         const struct reg_info *reg_group;
6594
6595         while ((reg_group = ixgbevf_regs[g_ind++]))
6596                 count += ixgbe_regs_group_count(reg_group);
6597
6598         return count;
6599 }
6600
6601 static int
6602 ixgbe_get_regs(struct rte_eth_dev *dev,
6603               struct rte_dev_reg_info *regs)
6604 {
6605         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6606         uint32_t *data = regs->data;
6607         int g_ind = 0;
6608         int count = 0;
6609         const struct reg_info *reg_group;
6610         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6611                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6612
6613         if (data == NULL) {
6614                 regs->length = ixgbe_get_reg_length(dev);
6615                 regs->width = sizeof(uint32_t);
6616                 return 0;
6617         }
6618
6619         /* Support only full register dump */
6620         if ((regs->length == 0) ||
6621             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6622                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6623                         hw->device_id;
6624                 while ((reg_group = reg_set[g_ind++]))
6625                         count += ixgbe_read_regs_group(dev, &data[count],
6626                                 reg_group);
6627                 return 0;
6628         }
6629
6630         return -ENOTSUP;
6631 }
6632
6633 static int
6634 ixgbevf_get_regs(struct rte_eth_dev *dev,
6635                 struct rte_dev_reg_info *regs)
6636 {
6637         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6638         uint32_t *data = regs->data;
6639         int g_ind = 0;
6640         int count = 0;
6641         const struct reg_info *reg_group;
6642
6643         if (data == NULL) {
6644                 regs->length = ixgbevf_get_reg_length(dev);
6645                 regs->width = sizeof(uint32_t);
6646                 return 0;
6647         }
6648
6649         /* Support only full register dump */
6650         if ((regs->length == 0) ||
6651             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6652                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6653                         hw->device_id;
6654                 while ((reg_group = ixgbevf_regs[g_ind++]))
6655                         count += ixgbe_read_regs_group(dev, &data[count],
6656                                                       reg_group);
6657                 return 0;
6658         }
6659
6660         return -ENOTSUP;
6661 }
6662
6663 static int
6664 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6665 {
6666         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6667
6668         /* Return unit is byte count */
6669         return hw->eeprom.word_size * 2;
6670 }
6671
6672 static int
6673 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6674                 struct rte_dev_eeprom_info *in_eeprom)
6675 {
6676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6677         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6678         uint16_t *data = in_eeprom->data;
6679         int first, length;
6680
6681         first = in_eeprom->offset >> 1;
6682         length = in_eeprom->length >> 1;
6683         if ((first > hw->eeprom.word_size) ||
6684             ((first + length) > hw->eeprom.word_size))
6685                 return -EINVAL;
6686
6687         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6688
6689         return eeprom->ops.read_buffer(hw, first, length, data);
6690 }
6691
6692 static int
6693 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6694                 struct rte_dev_eeprom_info *in_eeprom)
6695 {
6696         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6697         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6698         uint16_t *data = in_eeprom->data;
6699         int first, length;
6700
6701         first = in_eeprom->offset >> 1;
6702         length = in_eeprom->length >> 1;
6703         if ((first > hw->eeprom.word_size) ||
6704             ((first + length) > hw->eeprom.word_size))
6705                 return -EINVAL;
6706
6707         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6708
6709         return eeprom->ops.write_buffer(hw,  first, length, data);
6710 }
6711
6712 uint16_t
6713 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6714         switch (mac_type) {
6715         case ixgbe_mac_X550:
6716         case ixgbe_mac_X550EM_x:
6717         case ixgbe_mac_X550EM_a:
6718                 return ETH_RSS_RETA_SIZE_512;
6719         case ixgbe_mac_X550_vf:
6720         case ixgbe_mac_X550EM_x_vf:
6721         case ixgbe_mac_X550EM_a_vf:
6722                 return ETH_RSS_RETA_SIZE_64;
6723         default:
6724                 return ETH_RSS_RETA_SIZE_128;
6725         }
6726 }
6727
6728 uint32_t
6729 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6730         switch (mac_type) {
6731         case ixgbe_mac_X550:
6732         case ixgbe_mac_X550EM_x:
6733         case ixgbe_mac_X550EM_a:
6734                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6735                         return IXGBE_RETA(reta_idx >> 2);
6736                 else
6737                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6738         case ixgbe_mac_X550_vf:
6739         case ixgbe_mac_X550EM_x_vf:
6740         case ixgbe_mac_X550EM_a_vf:
6741                 return IXGBE_VFRETA(reta_idx >> 2);
6742         default:
6743                 return IXGBE_RETA(reta_idx >> 2);
6744         }
6745 }
6746
6747 uint32_t
6748 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6749         switch (mac_type) {
6750         case ixgbe_mac_X550_vf:
6751         case ixgbe_mac_X550EM_x_vf:
6752         case ixgbe_mac_X550EM_a_vf:
6753                 return IXGBE_VFMRQC;
6754         default:
6755                 return IXGBE_MRQC;
6756         }
6757 }
6758
6759 uint32_t
6760 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6761         switch (mac_type) {
6762         case ixgbe_mac_X550_vf:
6763         case ixgbe_mac_X550EM_x_vf:
6764         case ixgbe_mac_X550EM_a_vf:
6765                 return IXGBE_VFRSSRK(i);
6766         default:
6767                 return IXGBE_RSSRK(i);
6768         }
6769 }
6770
6771 bool
6772 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6773         switch (mac_type) {
6774         case ixgbe_mac_82599_vf:
6775         case ixgbe_mac_X540_vf:
6776                 return 0;
6777         default:
6778                 return 1;
6779         }
6780 }
6781
6782 static int
6783 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6784                         struct rte_eth_dcb_info *dcb_info)
6785 {
6786         struct ixgbe_dcb_config *dcb_config =
6787                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6788         struct ixgbe_dcb_tc_config *tc;
6789         uint8_t i, j;
6790
6791         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6792                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6793         else
6794                 dcb_info->nb_tcs = 1;
6795
6796         if (dcb_config->vt_mode) { /* vt is enabled*/
6797                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6798                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6799                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6800                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6801                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6802                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6803                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6804                                                 i * dcb_info->nb_tcs + j;
6805                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6806                                 dcb_info->tc_queue.tc_txq[i][j].base =
6807                                                 i * dcb_info->nb_tcs + j;
6808                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6809                         }
6810                 }
6811         } else { /* vt is disabled*/
6812                 struct rte_eth_dcb_rx_conf *rx_conf =
6813                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6814                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6815                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6816                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6817                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6818                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6819                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6820                         }
6821                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6822                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6823                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6824                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6825                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6826                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6827                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6828                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6829                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6830                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6831                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6832                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6833                         }
6834                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6835                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6836                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6837                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6838                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6839                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6840                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6841                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6842                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6843                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6844                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6845                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6846                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6847                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6848                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6849                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6850                 }
6851         }
6852         for (i = 0; i < dcb_info->nb_tcs; i++) {
6853                 tc = &dcb_config->tc_config[i];
6854                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6855         }
6856         return 0;
6857 }
6858
6859 /* Update e-tag ether type */
6860 static int
6861 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6862                             uint16_t ether_type)
6863 {
6864         uint32_t etag_etype;
6865
6866         if (hw->mac.type != ixgbe_mac_X550 &&
6867             hw->mac.type != ixgbe_mac_X550EM_x &&
6868             hw->mac.type != ixgbe_mac_X550EM_a) {
6869                 return -ENOTSUP;
6870         }
6871
6872         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6873         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6874         etag_etype |= ether_type;
6875         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6876         IXGBE_WRITE_FLUSH(hw);
6877
6878         return 0;
6879 }
6880
6881 /* Config l2 tunnel ether type */
6882 static int
6883 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6884                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6885 {
6886         int ret = 0;
6887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6888
6889         if (l2_tunnel == NULL)
6890                 return -EINVAL;
6891
6892         switch (l2_tunnel->l2_tunnel_type) {
6893         case RTE_L2_TUNNEL_TYPE_E_TAG:
6894                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6895                 break;
6896         default:
6897                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6898                 ret = -EINVAL;
6899                 break;
6900         }
6901
6902         return ret;
6903 }
6904
6905 /* Enable e-tag tunnel */
6906 static int
6907 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6908 {
6909         uint32_t etag_etype;
6910
6911         if (hw->mac.type != ixgbe_mac_X550 &&
6912             hw->mac.type != ixgbe_mac_X550EM_x &&
6913             hw->mac.type != ixgbe_mac_X550EM_a) {
6914                 return -ENOTSUP;
6915         }
6916
6917         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6918         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6919         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6920         IXGBE_WRITE_FLUSH(hw);
6921
6922         return 0;
6923 }
6924
6925 /* Enable l2 tunnel */
6926 static int
6927 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6928                            enum rte_eth_tunnel_type l2_tunnel_type)
6929 {
6930         int ret = 0;
6931         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6932
6933         switch (l2_tunnel_type) {
6934         case RTE_L2_TUNNEL_TYPE_E_TAG:
6935                 ret = ixgbe_e_tag_enable(hw);
6936                 break;
6937         default:
6938                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6939                 ret = -EINVAL;
6940                 break;
6941         }
6942
6943         return ret;
6944 }
6945
6946 /* Disable e-tag tunnel */
6947 static int
6948 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6949 {
6950         uint32_t etag_etype;
6951
6952         if (hw->mac.type != ixgbe_mac_X550 &&
6953             hw->mac.type != ixgbe_mac_X550EM_x &&
6954             hw->mac.type != ixgbe_mac_X550EM_a) {
6955                 return -ENOTSUP;
6956         }
6957
6958         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6959         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6960         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6961         IXGBE_WRITE_FLUSH(hw);
6962
6963         return 0;
6964 }
6965
6966 /* Disable l2 tunnel */
6967 static int
6968 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6969                             enum rte_eth_tunnel_type l2_tunnel_type)
6970 {
6971         int ret = 0;
6972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6973
6974         switch (l2_tunnel_type) {
6975         case RTE_L2_TUNNEL_TYPE_E_TAG:
6976                 ret = ixgbe_e_tag_disable(hw);
6977                 break;
6978         default:
6979                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6980                 ret = -EINVAL;
6981                 break;
6982         }
6983
6984         return ret;
6985 }
6986
6987 static int
6988 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6989                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6990 {
6991         int ret = 0;
6992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6993         uint32_t i, rar_entries;
6994         uint32_t rar_low, rar_high;
6995
6996         if (hw->mac.type != ixgbe_mac_X550 &&
6997             hw->mac.type != ixgbe_mac_X550EM_x &&
6998             hw->mac.type != ixgbe_mac_X550EM_a) {
6999                 return -ENOTSUP;
7000         }
7001
7002         rar_entries = ixgbe_get_num_rx_addrs(hw);
7003
7004         for (i = 1; i < rar_entries; i++) {
7005                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7006                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7007                 if ((rar_high & IXGBE_RAH_AV) &&
7008                     (rar_high & IXGBE_RAH_ADTYPE) &&
7009                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7010                      l2_tunnel->tunnel_id)) {
7011                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7012                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7013
7014                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7015
7016                         return ret;
7017                 }
7018         }
7019
7020         return ret;
7021 }
7022
7023 static int
7024 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7025                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7026 {
7027         int ret = 0;
7028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7029         uint32_t i, rar_entries;
7030         uint32_t rar_low, rar_high;
7031
7032         if (hw->mac.type != ixgbe_mac_X550 &&
7033             hw->mac.type != ixgbe_mac_X550EM_x &&
7034             hw->mac.type != ixgbe_mac_X550EM_a) {
7035                 return -ENOTSUP;
7036         }
7037
7038         /* One entry for one tunnel. Try to remove potential existing entry. */
7039         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7040
7041         rar_entries = ixgbe_get_num_rx_addrs(hw);
7042
7043         for (i = 1; i < rar_entries; i++) {
7044                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7045                 if (rar_high & IXGBE_RAH_AV) {
7046                         continue;
7047                 } else {
7048                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7049                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7050                         rar_low = l2_tunnel->tunnel_id;
7051
7052                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7053                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7054
7055                         return ret;
7056                 }
7057         }
7058
7059         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7060                      " Please remove a rule before adding a new one.");
7061         return -EINVAL;
7062 }
7063
7064 /* Add l2 tunnel filter */
7065 static int
7066 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7067                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7068 {
7069         int ret = 0;
7070
7071         switch (l2_tunnel->l2_tunnel_type) {
7072         case RTE_L2_TUNNEL_TYPE_E_TAG:
7073                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7074                 break;
7075         default:
7076                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7077                 ret = -EINVAL;
7078                 break;
7079         }
7080
7081         return ret;
7082 }
7083
7084 /* Delete l2 tunnel filter */
7085 static int
7086 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7087                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7088 {
7089         int ret = 0;
7090
7091         switch (l2_tunnel->l2_tunnel_type) {
7092         case RTE_L2_TUNNEL_TYPE_E_TAG:
7093                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7094                 break;
7095         default:
7096                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7097                 ret = -EINVAL;
7098                 break;
7099         }
7100
7101         return ret;
7102 }
7103
7104 /**
7105  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7106  * @dev: pointer to rte_eth_dev structure
7107  * @filter_op:operation will be taken.
7108  * @arg: a pointer to specific structure corresponding to the filter_op
7109  */
7110 static int
7111 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7112                                   enum rte_filter_op filter_op,
7113                                   void *arg)
7114 {
7115         int ret = 0;
7116
7117         if (filter_op == RTE_ETH_FILTER_NOP)
7118                 return 0;
7119
7120         if (arg == NULL) {
7121                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7122                             filter_op);
7123                 return -EINVAL;
7124         }
7125
7126         switch (filter_op) {
7127         case RTE_ETH_FILTER_ADD:
7128                 ret = ixgbe_dev_l2_tunnel_filter_add
7129                         (dev,
7130                          (struct rte_eth_l2_tunnel_conf *)arg);
7131                 break;
7132         case RTE_ETH_FILTER_DELETE:
7133                 ret = ixgbe_dev_l2_tunnel_filter_del
7134                         (dev,
7135                          (struct rte_eth_l2_tunnel_conf *)arg);
7136                 break;
7137         default:
7138                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7139                 ret = -EINVAL;
7140                 break;
7141         }
7142         return ret;
7143 }
7144
7145 static int
7146 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7147 {
7148         int ret = 0;
7149         uint32_t ctrl;
7150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7151
7152         if (hw->mac.type != ixgbe_mac_X550 &&
7153             hw->mac.type != ixgbe_mac_X550EM_x &&
7154             hw->mac.type != ixgbe_mac_X550EM_a) {
7155                 return -ENOTSUP;
7156         }
7157
7158         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7159         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7160         if (en)
7161                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7162         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7163
7164         return ret;
7165 }
7166
7167 /* Enable l2 tunnel forwarding */
7168 static int
7169 ixgbe_dev_l2_tunnel_forwarding_enable
7170         (struct rte_eth_dev *dev,
7171          enum rte_eth_tunnel_type l2_tunnel_type)
7172 {
7173         int ret = 0;
7174
7175         switch (l2_tunnel_type) {
7176         case RTE_L2_TUNNEL_TYPE_E_TAG:
7177                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7178                 break;
7179         default:
7180                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7181                 ret = -EINVAL;
7182                 break;
7183         }
7184
7185         return ret;
7186 }
7187
7188 /* Disable l2 tunnel forwarding */
7189 static int
7190 ixgbe_dev_l2_tunnel_forwarding_disable
7191         (struct rte_eth_dev *dev,
7192          enum rte_eth_tunnel_type l2_tunnel_type)
7193 {
7194         int ret = 0;
7195
7196         switch (l2_tunnel_type) {
7197         case RTE_L2_TUNNEL_TYPE_E_TAG:
7198                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7199                 break;
7200         default:
7201                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7202                 ret = -EINVAL;
7203                 break;
7204         }
7205
7206         return ret;
7207 }
7208
7209 static int
7210 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7211                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7212                              bool en)
7213 {
7214         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7215         int ret = 0;
7216         uint32_t vmtir, vmvir;
7217         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7218
7219         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7220                 PMD_DRV_LOG(ERR,
7221                             "VF id %u should be less than %u",
7222                             l2_tunnel->vf_id,
7223                             pci_dev->max_vfs);
7224                 return -EINVAL;
7225         }
7226
7227         if (hw->mac.type != ixgbe_mac_X550 &&
7228             hw->mac.type != ixgbe_mac_X550EM_x &&
7229             hw->mac.type != ixgbe_mac_X550EM_a) {
7230                 return -ENOTSUP;
7231         }
7232
7233         if (en)
7234                 vmtir = l2_tunnel->tunnel_id;
7235         else
7236                 vmtir = 0;
7237
7238         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7239
7240         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7241         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7242         if (en)
7243                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7244         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7245
7246         return ret;
7247 }
7248
7249 /* Enable l2 tunnel tag insertion */
7250 static int
7251 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7252                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7253 {
7254         int ret = 0;
7255
7256         switch (l2_tunnel->l2_tunnel_type) {
7257         case RTE_L2_TUNNEL_TYPE_E_TAG:
7258                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7259                 break;
7260         default:
7261                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7262                 ret = -EINVAL;
7263                 break;
7264         }
7265
7266         return ret;
7267 }
7268
7269 /* Disable l2 tunnel tag insertion */
7270 static int
7271 ixgbe_dev_l2_tunnel_insertion_disable
7272         (struct rte_eth_dev *dev,
7273          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7274 {
7275         int ret = 0;
7276
7277         switch (l2_tunnel->l2_tunnel_type) {
7278         case RTE_L2_TUNNEL_TYPE_E_TAG:
7279                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7280                 break;
7281         default:
7282                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7283                 ret = -EINVAL;
7284                 break;
7285         }
7286
7287         return ret;
7288 }
7289
7290 static int
7291 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7292                              bool en)
7293 {
7294         int ret = 0;
7295         uint32_t qde;
7296         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7297
7298         if (hw->mac.type != ixgbe_mac_X550 &&
7299             hw->mac.type != ixgbe_mac_X550EM_x &&
7300             hw->mac.type != ixgbe_mac_X550EM_a) {
7301                 return -ENOTSUP;
7302         }
7303
7304         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7305         if (en)
7306                 qde |= IXGBE_QDE_STRIP_TAG;
7307         else
7308                 qde &= ~IXGBE_QDE_STRIP_TAG;
7309         qde &= ~IXGBE_QDE_READ;
7310         qde |= IXGBE_QDE_WRITE;
7311         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7312
7313         return ret;
7314 }
7315
7316 /* Enable l2 tunnel tag stripping */
7317 static int
7318 ixgbe_dev_l2_tunnel_stripping_enable
7319         (struct rte_eth_dev *dev,
7320          enum rte_eth_tunnel_type l2_tunnel_type)
7321 {
7322         int ret = 0;
7323
7324         switch (l2_tunnel_type) {
7325         case RTE_L2_TUNNEL_TYPE_E_TAG:
7326                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7327                 break;
7328         default:
7329                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7330                 ret = -EINVAL;
7331                 break;
7332         }
7333
7334         return ret;
7335 }
7336
7337 /* Disable l2 tunnel tag stripping */
7338 static int
7339 ixgbe_dev_l2_tunnel_stripping_disable
7340         (struct rte_eth_dev *dev,
7341          enum rte_eth_tunnel_type l2_tunnel_type)
7342 {
7343         int ret = 0;
7344
7345         switch (l2_tunnel_type) {
7346         case RTE_L2_TUNNEL_TYPE_E_TAG:
7347                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7348                 break;
7349         default:
7350                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7351                 ret = -EINVAL;
7352                 break;
7353         }
7354
7355         return ret;
7356 }
7357
7358 /* Enable/disable l2 tunnel offload functions */
7359 static int
7360 ixgbe_dev_l2_tunnel_offload_set
7361         (struct rte_eth_dev *dev,
7362          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7363          uint32_t mask,
7364          uint8_t en)
7365 {
7366         int ret = 0;
7367
7368         if (l2_tunnel == NULL)
7369                 return -EINVAL;
7370
7371         ret = -EINVAL;
7372         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7373                 if (en)
7374                         ret = ixgbe_dev_l2_tunnel_enable(
7375                                 dev,
7376                                 l2_tunnel->l2_tunnel_type);
7377                 else
7378                         ret = ixgbe_dev_l2_tunnel_disable(
7379                                 dev,
7380                                 l2_tunnel->l2_tunnel_type);
7381         }
7382
7383         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7384                 if (en)
7385                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7386                                 dev,
7387                                 l2_tunnel);
7388                 else
7389                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7390                                 dev,
7391                                 l2_tunnel);
7392         }
7393
7394         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7395                 if (en)
7396                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7397                                 dev,
7398                                 l2_tunnel->l2_tunnel_type);
7399                 else
7400                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7401                                 dev,
7402                                 l2_tunnel->l2_tunnel_type);
7403         }
7404
7405         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7406                 if (en)
7407                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7408                                 dev,
7409                                 l2_tunnel->l2_tunnel_type);
7410                 else
7411                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7412                                 dev,
7413                                 l2_tunnel->l2_tunnel_type);
7414         }
7415
7416         return ret;
7417 }
7418
7419 static int
7420 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7421                         uint16_t port)
7422 {
7423         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7424         IXGBE_WRITE_FLUSH(hw);
7425
7426         return 0;
7427 }
7428
7429 /* There's only one register for VxLAN UDP port.
7430  * So, we cannot add several ports. Will update it.
7431  */
7432 static int
7433 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7434                      uint16_t port)
7435 {
7436         if (port == 0) {
7437                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7438                 return -EINVAL;
7439         }
7440
7441         return ixgbe_update_vxlan_port(hw, port);
7442 }
7443
7444 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7445  * UDP port, it must have a value.
7446  * So, will reset it to the original value 0.
7447  */
7448 static int
7449 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7450                      uint16_t port)
7451 {
7452         uint16_t cur_port;
7453
7454         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7455
7456         if (cur_port != port) {
7457                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7458                 return -EINVAL;
7459         }
7460
7461         return ixgbe_update_vxlan_port(hw, 0);
7462 }
7463
7464 /* Add UDP tunneling port */
7465 static int
7466 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7467                               struct rte_eth_udp_tunnel *udp_tunnel)
7468 {
7469         int ret = 0;
7470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7471
7472         if (hw->mac.type != ixgbe_mac_X550 &&
7473             hw->mac.type != ixgbe_mac_X550EM_x &&
7474             hw->mac.type != ixgbe_mac_X550EM_a) {
7475                 return -ENOTSUP;
7476         }
7477
7478         if (udp_tunnel == NULL)
7479                 return -EINVAL;
7480
7481         switch (udp_tunnel->prot_type) {
7482         case RTE_TUNNEL_TYPE_VXLAN:
7483                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7484                 break;
7485
7486         case RTE_TUNNEL_TYPE_GENEVE:
7487         case RTE_TUNNEL_TYPE_TEREDO:
7488                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7489                 ret = -EINVAL;
7490                 break;
7491
7492         default:
7493                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7494                 ret = -EINVAL;
7495                 break;
7496         }
7497
7498         return ret;
7499 }
7500
7501 /* Remove UDP tunneling port */
7502 static int
7503 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7504                               struct rte_eth_udp_tunnel *udp_tunnel)
7505 {
7506         int ret = 0;
7507         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7508
7509         if (hw->mac.type != ixgbe_mac_X550 &&
7510             hw->mac.type != ixgbe_mac_X550EM_x &&
7511             hw->mac.type != ixgbe_mac_X550EM_a) {
7512                 return -ENOTSUP;
7513         }
7514
7515         if (udp_tunnel == NULL)
7516                 return -EINVAL;
7517
7518         switch (udp_tunnel->prot_type) {
7519         case RTE_TUNNEL_TYPE_VXLAN:
7520                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7521                 break;
7522         case RTE_TUNNEL_TYPE_GENEVE:
7523         case RTE_TUNNEL_TYPE_TEREDO:
7524                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7525                 ret = -EINVAL;
7526                 break;
7527         default:
7528                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7529                 ret = -EINVAL;
7530                 break;
7531         }
7532
7533         return ret;
7534 }
7535
7536 static void
7537 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7538 {
7539         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7540
7541         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7542 }
7543
7544 static void
7545 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7546 {
7547         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7548
7549         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7550 }
7551
7552 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7553 {
7554         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7555         u32 in_msg = 0;
7556
7557         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7558                 return;
7559
7560         /* PF reset VF event */
7561         if (in_msg == IXGBE_PF_CONTROL_MSG)
7562                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
7563 }
7564
7565 static int
7566 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7567 {
7568         uint32_t eicr;
7569         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7570         struct ixgbe_interrupt *intr =
7571                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7572         ixgbevf_intr_disable(hw);
7573
7574         /* read-on-clear nic registers here */
7575         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7576         intr->flags = 0;
7577
7578         /* only one misc vector supported - mailbox */
7579         eicr &= IXGBE_VTEICR_MASK;
7580         if (eicr == IXGBE_MISC_VEC_ID)
7581                 intr->flags |= IXGBE_FLAG_MAILBOX;
7582
7583         return 0;
7584 }
7585
7586 static int
7587 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7588 {
7589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7590         struct ixgbe_interrupt *intr =
7591                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7592
7593         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7594                 ixgbevf_mbx_process(dev);
7595                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7596         }
7597
7598         ixgbevf_intr_enable(hw);
7599
7600         return 0;
7601 }
7602
7603 static void
7604 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7605                               void *param)
7606 {
7607         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7608
7609         ixgbevf_dev_interrupt_get_status(dev);
7610         ixgbevf_dev_interrupt_action(dev);
7611 }
7612
7613 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
7614 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
7615 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
7616 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
7617 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
7618 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");