drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 #include "rte_pmd_ixgbe.h"
  77
  78 /*
  79  * High threshold controlling when to start sending XOFF frames. Must be at
  80  * least 8 bytes less than receive packet buffer size. This value is in units
  81  * of 1024 bytes.
  82  */
  83 #define IXGBE_FC_HI    0x80
  84
  85 /*
  86  * Low threshold controlling when to start sending XON frames. This value is
  87  * in units of 1024 bytes.
  88  */
  89 #define IXGBE_FC_LO    0x40
  90
  91 /* Default minimum inter-interrupt interval for EITR configuration */
  92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  93
  94 /* Timer value included in XOFF frames. */
  95 #define IXGBE_FC_PAUSE 0x680
  96
  97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  98 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  99 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 100
 101 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 102 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 103 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 104
 105 /*
 106  *  Default values for RX/TX configuration
 107  */
 108 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 109 #define IXGBE_DEFAULT_RX_PTHRESH      8
 110 #define IXGBE_DEFAULT_RX_HTHRESH      8
 111 #define IXGBE_DEFAULT_RX_WTHRESH      0
 112
 113 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 114 #define IXGBE_DEFAULT_TX_PTHRESH      32
 115 #define IXGBE_DEFAULT_TX_HTHRESH      0
 116 #define IXGBE_DEFAULT_TX_WTHRESH      0
 117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 118
 119 /* Bit shift and mask */
 120 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 121 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 122 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 123 #define IXGBE_8_BIT_MASK   UINT8_MAX
 124
 125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 126
 127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 128
 129 #define IXGBE_HKEY_MAX_INDEX 10
 130
 131 /* Additional timesync values. */
 132 #define NSEC_PER_SEC             1000000000L
 133 #define IXGBE_INCVAL_10GB        0x66666666
 134 #define IXGBE_INCVAL_1GB         0x40000000
 135 #define IXGBE_INCVAL_100         0x50000000
 136 #define IXGBE_INCVAL_SHIFT_10GB  28
 137 #define IXGBE_INCVAL_SHIFT_1GB   24
 138 #define IXGBE_INCVAL_SHIFT_100   21
 139 #define IXGBE_INCVAL_SHIFT_82599 7
 140 #define IXGBE_INCPER_SHIFT_82599 24
 141
 142 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 143
 144 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 146 #define DEFAULT_ETAG_ETYPE                     0x893f
 147 #define IXGBE_ETAG_ETYPE                       0x00005084
 148 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 149 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 150 #define IXGBE_RAH_ADTYPE                       0x40000000
 151 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 152 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 155 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 156 #define IXGBE_VTEICR_MASK                      0x07
 157
 158 enum ixgbevf_xcast_modes {
 159         IXGBEVF_XCAST_MODE_NONE = 0,
 160         IXGBEVF_XCAST_MODE_MULTI,
 161         IXGBEVF_XCAST_MODE_ALLMULTI,
 162 };
 163
 164 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 165 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 166
 167 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 168 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 169 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 170 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 171 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 172 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 173 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 174 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 175 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 177 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 178 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 179 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 180 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 182 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 183 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 184 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 185                                 int wait_to_complete);
 186 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 187                                 struct rte_eth_stats *stats);
 188 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_xstat *xstats, unsigned n);
 190 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 191                                   struct rte_eth_xstat *xstats, unsigned n);
 192 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 193 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 194 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 195         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 196 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 198 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 199                                              uint16_t queue_id,
 200                                              uint8_t stat_idx,
 201                                              uint8_t is_rx);
 202 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 203                                  size_t fw_size);
 204 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 205                                struct rte_eth_dev_info *dev_info);
 206 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 207 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 208                                  struct rte_eth_dev_info *dev_info);
 209 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 210
 211 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 212                 uint16_t vlan_id, int on);
 213 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 214                                enum rte_vlan_type vlan_type,
 215                                uint16_t tpid_id);
 216 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 217                 uint16_t queue, bool on);
 218 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 219                 int on);
 220 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 221 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 222 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 223 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 224 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 225
 226 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 228 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 229                                struct rte_eth_fc_conf *fc_conf);
 230 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 233                 struct rte_eth_pfc_conf *pfc_conf);
 234 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 235                         struct rte_eth_rss_reta_entry64 *reta_conf,
 236                         uint16_t reta_size);
 237 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 238                         struct rte_eth_rss_reta_entry64 *reta_conf,
 239                         uint16_t reta_size);
 240 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 241 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 242 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 246                                       struct rte_intr_handle *handle);
 247 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 248                 void *param);
 249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 250 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 251                 uint32_t index, uint32_t pool);
 252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 254                                            struct ether_addr *mac_addr);
 255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 256 static int is_ixgbe_pmd(const char *driver_name);
 257
 258 /* For Virtual Function support */
 259 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 260 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 261 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 262 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 265 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 266 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 267 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 268                 struct rte_eth_stats *stats);
 269 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 270 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 271                 uint16_t vlan_id, int on);
 272 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 273                 uint16_t queue, int on);
 274 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 275 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 276 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 277                                             uint16_t queue_id);
 278 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 279                                              uint16_t queue_id);
 280 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 281                                  uint8_t queue, uint8_t msix_vector);
 282 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 283 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 284 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 285
 286 /* For Eth VMDQ APIs support */
 287 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 288                 ether_addr * mac_addr, uint8_t on);
 289 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 290 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 291                 struct rte_eth_mirror_conf *mirror_conf,
 292                 uint8_t rule_id, uint8_t on);
 293 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 294                 uint8_t rule_id);
 295 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 296                                           uint16_t queue_id);
 297 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 298                                            uint16_t queue_id);
 299 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 300                                uint8_t queue, uint8_t msix_vector);
 301 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 302
 303 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 304                 uint16_t queue_idx, uint16_t tx_rate);
 305
 306 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 307                                  struct ether_addr *mac_addr,
 308                                  uint32_t index, uint32_t pool);
 309 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 310 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 311                                              struct ether_addr *mac_addr);
 312 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 313                         struct rte_eth_syn_filter *filter);
 314 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 315                         enum rte_filter_op filter_op,
 316                         void *arg);
 317 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 318                         struct ixgbe_5tuple_filter *filter);
 319 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ntuple_filter *filter);
 326 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 327                                 enum rte_filter_op filter_op,
 328                                 void *arg);
 329 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 330                         struct rte_eth_ethertype_filter *filter);
 331 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 332                      enum rte_filter_type filter_type,
 333                      enum rte_filter_op filter_op,
 334                      void *arg);
 335 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 336
 337 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 338                                       struct ether_addr *mc_addr_set,
 339                                       uint32_t nb_mc_addr);
 340 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 341                                    struct rte_eth_dcb_info *dcb_info);
 342
 343 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 344 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 345                             struct rte_dev_reg_info *regs);
 346 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 347 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 348                                 struct rte_dev_eeprom_info *eeprom);
 349 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351
 352 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 353 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 354                                 struct rte_dev_reg_info *regs);
 355
 356 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 357 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 358 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 359                                             struct timespec *timestamp,
 360                                             uint32_t flags);
 361 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 362                                             struct timespec *timestamp);
 363 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 364 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 365                                    struct timespec *timestamp);
 366 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 367                                    const struct timespec *timestamp);
 368 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 369                                           void *param);
 370
 371 static int ixgbe_dev_l2_tunnel_eth_type_conf
 372         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 373 static int ixgbe_dev_l2_tunnel_offload_set
 374         (struct rte_eth_dev *dev,
 375          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 376          uint32_t mask,
 377          uint8_t en);
 378 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 379                                              enum rte_filter_op filter_op,
 380                                              void *arg);
 381
 382 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 383                                          struct rte_eth_udp_tunnel *udp_tunnel);
 384 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 385                                          struct rte_eth_udp_tunnel *udp_tunnel);
 386 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 387 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 388
 389 /*
 390  * Define VF Stats MACRO for Non "cleared on read" register
 391  */
 392 #define UPDATE_VF_STAT(reg, last, cur)                          \
 393 {                                                               \
 394         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 395         cur += (latest - last) & UINT_MAX;                      \
 396         last = latest;                                          \
 397 }
 398
 399 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 400 {                                                                \
 401         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 402         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 403         u64 latest = ((new_msb << 32) | new_lsb);                \
 404         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 405         last = latest;                                           \
 406 }
 407
 408 #define IXGBE_SET_HWSTRIP(h, q) do {\
 409                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 410                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 411                 (h)->bitmap[idx] |= 1 << bit;\
 412         } while (0)
 413
 414 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 415                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 416                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 417                 (h)->bitmap[idx] &= ~(1 << bit);\
 418         } while (0)
 419
 420 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 421                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 422                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 423                 (r) = (h)->bitmap[idx] >> bit & 1;\
 424         } while (0)
 425
 426 /*
 427  * The set of PCI devices this driver supports
 428  */
 429 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 483 #ifdef RTE_NIC_BYPASS
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 485 #endif
 486         { .vendor_id = 0, /* sentinel */ },
 487 };
 488
 489 /*
 490  * The set of PCI devices this driver supports (for 82599 VF)
 491  */
 492 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 503         { .vendor_id = 0, /* sentinel */ },
 504 };
 505
 506 static const struct rte_eth_desc_lim rx_desc_lim = {
 507         .nb_max = IXGBE_MAX_RING_DESC,
 508         .nb_min = IXGBE_MIN_RING_DESC,
 509         .nb_align = IXGBE_RXD_ALIGN,
 510 };
 511
 512 static const struct rte_eth_desc_lim tx_desc_lim = {
 513         .nb_max = IXGBE_MAX_RING_DESC,
 514         .nb_min = IXGBE_MIN_RING_DESC,
 515         .nb_align = IXGBE_TXD_ALIGN,
 516         .nb_seg_max = IXGBE_TX_MAX_SEG,
 517         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 518 };
 519
 520 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 521         .dev_configure        = ixgbe_dev_configure,
 522         .dev_start            = ixgbe_dev_start,
 523         .dev_stop             = ixgbe_dev_stop,
 524         .dev_set_link_up    = ixgbe_dev_set_link_up,
 525         .dev_set_link_down  = ixgbe_dev_set_link_down,
 526         .dev_close            = ixgbe_dev_close,
 527         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 528         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 529         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 530         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 531         .link_update          = ixgbe_dev_link_update,
 532         .stats_get            = ixgbe_dev_stats_get,
 533         .xstats_get           = ixgbe_dev_xstats_get,
 534         .stats_reset          = ixgbe_dev_stats_reset,
 535         .xstats_reset         = ixgbe_dev_xstats_reset,
 536         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 537         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 538         .fw_version_get       = ixgbe_fw_version_get,
 539         .dev_infos_get        = ixgbe_dev_info_get,
 540         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 541         .mtu_set              = ixgbe_dev_mtu_set,
 542         .vlan_filter_set      = ixgbe_vlan_filter_set,
 543         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 544         .vlan_offload_set     = ixgbe_vlan_offload_set,
 545         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 546         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 547         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 548         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 549         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 550         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 551         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 552         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 553         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 554         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 555         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 556         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 557         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 558         .dev_led_on           = ixgbe_dev_led_on,
 559         .dev_led_off          = ixgbe_dev_led_off,
 560         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 561         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 562         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 563         .mac_addr_add         = ixgbe_add_rar,
 564         .mac_addr_remove      = ixgbe_remove_rar,
 565         .mac_addr_set         = ixgbe_set_default_mac_addr,
 566         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 567         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 568         .mirror_rule_set      = ixgbe_mirror_rule_set,
 569         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 570         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 571         .reta_update          = ixgbe_dev_rss_reta_update,
 572         .reta_query           = ixgbe_dev_rss_reta_query,
 573 #ifdef RTE_NIC_BYPASS
 574         .bypass_init          = ixgbe_bypass_init,
 575         .bypass_state_set     = ixgbe_bypass_state_store,
 576         .bypass_state_show    = ixgbe_bypass_state_show,
 577         .bypass_event_set     = ixgbe_bypass_event_store,
 578         .bypass_event_show    = ixgbe_bypass_event_show,
 579         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 580         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 581         .bypass_ver_show      = ixgbe_bypass_ver_show,
 582         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 583 #endif /* RTE_NIC_BYPASS */
 584         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 585         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 586         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 587         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 588         .rxq_info_get         = ixgbe_rxq_info_get,
 589         .txq_info_get         = ixgbe_txq_info_get,
 590         .timesync_enable      = ixgbe_timesync_enable,
 591         .timesync_disable     = ixgbe_timesync_disable,
 592         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 593         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 594         .get_reg              = ixgbe_get_regs,
 595         .get_eeprom_length    = ixgbe_get_eeprom_length,
 596         .get_eeprom           = ixgbe_get_eeprom,
 597         .set_eeprom           = ixgbe_set_eeprom,
 598         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 599         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 600         .timesync_read_time   = ixgbe_timesync_read_time,
 601         .timesync_write_time  = ixgbe_timesync_write_time,
 602         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 603         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 604         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 605         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 606 };
 607
 608 /*
 609  * dev_ops for virtual function, bare necessities for basic vf
 610  * operation have been implemented
 611  */
 612 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 613         .dev_configure        = ixgbevf_dev_configure,
 614         .dev_start            = ixgbevf_dev_start,
 615         .dev_stop             = ixgbevf_dev_stop,
 616         .link_update          = ixgbe_dev_link_update,
 617         .stats_get            = ixgbevf_dev_stats_get,
 618         .xstats_get           = ixgbevf_dev_xstats_get,
 619         .stats_reset          = ixgbevf_dev_stats_reset,
 620         .xstats_reset         = ixgbevf_dev_stats_reset,
 621         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 622         .dev_close            = ixgbevf_dev_close,
 623         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 624         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 625         .dev_infos_get        = ixgbevf_dev_info_get,
 626         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 627         .mtu_set              = ixgbevf_dev_set_mtu,
 628         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 629         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 630         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 631         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 632         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 633         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 634         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 635         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 636         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 637         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 638         .mac_addr_add         = ixgbevf_add_mac_addr,
 639         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 640         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 641         .rxq_info_get         = ixgbe_rxq_info_get,
 642         .txq_info_get         = ixgbe_txq_info_get,
 643         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 644         .get_reg              = ixgbevf_get_regs,
 645         .reta_update          = ixgbe_dev_rss_reta_update,
 646         .reta_query           = ixgbe_dev_rss_reta_query,
 647         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 648         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 649 };
 650
 651 /* store statistics names and its offset in stats structure */
 652 struct rte_ixgbe_xstats_name_off {
 653         char name[RTE_ETH_XSTATS_NAME_SIZE];
 654         unsigned offset;
 655 };
 656
 657 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 658         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 659         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 660         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 661         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 662         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 663         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 664         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 665         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 666         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 667         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 668         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 669         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 670         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 671         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 672         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 673                 prc1023)},
 674         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 675                 prc1522)},
 676         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 677         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 678         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 679         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 680         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 681         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 682         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 683         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 684         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 685         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 686         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 687         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 688         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 689         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 690         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 691         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 692         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 693                 ptc1023)},
 694         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 695                 ptc1522)},
 696         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 697         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 698         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 699         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 700
 701         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 702                 fdirustat_add)},
 703         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 704                 fdirustat_remove)},
 705         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 706                 fdirfstat_fadd)},
 707         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 708                 fdirfstat_fremove)},
 709         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 710                 fdirmatch)},
 711         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 712                 fdirmiss)},
 713
 714         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 715         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 716         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 717                 fclast)},
 718         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 719         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 720         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 721         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 722         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 723                 fcoe_noddp)},
 724         {"rx_fcoe_no_direct_data_placement_ext_buff",
 725                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 726
 727         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 728                 lxontxc)},
 729         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 730                 lxonrxc)},
 731         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 732                 lxofftxc)},
 733         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 734                 lxoffrxc)},
 735         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 736 };
 737
 738 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 739                            sizeof(rte_ixgbe_stats_strings[0]))
 740
 741 /* MACsec statistics */
 742 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 743         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 744                 out_pkts_untagged)},
 745         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 746                 out_pkts_encrypted)},
 747         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 748                 out_pkts_protected)},
 749         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 750                 out_octets_encrypted)},
 751         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 752                 out_octets_protected)},
 753         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_untagged)},
 755         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_badtag)},
 757         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_nosci)},
 759         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_unknownsci)},
 761         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 762                 in_octets_decrypted)},
 763         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 764                 in_octets_validated)},
 765         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_unchecked)},
 767         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_delayed)},
 769         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_late)},
 771         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_ok)},
 773         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_invalid)},
 775         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_notvalid)},
 777         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 778                 in_pkts_unusedsa)},
 779         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 780                 in_pkts_notusingsa)},
 781 };
 782
 783 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 784                            sizeof(rte_ixgbe_macsec_strings[0]))
 785
 786 /* Per-queue statistics */
 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 788         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 789         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 790         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 791         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 792 };
 793
 794 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 795                            sizeof(rte_ixgbe_rxq_strings[0]))
 796 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 797
 798 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 799         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 800         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 801         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 802                 pxon2offc)},
 803 };
 804
 805 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 806                            sizeof(rte_ixgbe_txq_strings[0]))
 807 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 808
 809 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 810         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 811 };
 812
 813 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 814                 sizeof(rte_ixgbevf_stats_strings[0]))
 815
 816 /**
 817  * Atomically reads the link status information from global
 818  * structure rte_eth_dev.
 819  *
 820  * @param dev
 821  *   - Pointer to the structure rte_eth_dev to read from.
 822  *   - Pointer to the buffer to be saved with the link status.
 823  *
 824  * @return
 825  *   - On success, zero.
 826  *   - On failure, negative value.
 827  */
 828 static inline int
 829 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 830                                 struct rte_eth_link *link)
 831 {
 832         struct rte_eth_link *dst = link;
 833         struct rte_eth_link *src = &(dev->data->dev_link);
 834
 835         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 836                                         *(uint64_t *)src) == 0)
 837                 return -1;
 838
 839         return 0;
 840 }
 841
 842 /**
 843  * Atomically writes the link status information into global
 844  * structure rte_eth_dev.
 845  *
 846  * @param dev
 847  *   - Pointer to the structure rte_eth_dev to read from.
 848  *   - Pointer to the buffer to be saved with the link status.
 849  *
 850  * @return
 851  *   - On success, zero.
 852  *   - On failure, negative value.
 853  */
 854 static inline int
 855 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 856                                 struct rte_eth_link *link)
 857 {
 858         struct rte_eth_link *dst = &(dev->data->dev_link);
 859         struct rte_eth_link *src = link;
 860
 861         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 862                                         *(uint64_t *)src) == 0)
 863                 return -1;
 864
 865         return 0;
 866 }
 867
 868 /*
 869  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 870  */
 871 static inline int
 872 ixgbe_is_sfp(struct ixgbe_hw *hw)
 873 {
 874         switch (hw->phy.type) {
 875         case ixgbe_phy_sfp_avago:
 876         case ixgbe_phy_sfp_ftl:
 877         case ixgbe_phy_sfp_intel:
 878         case ixgbe_phy_sfp_unknown:
 879         case ixgbe_phy_sfp_passive_tyco:
 880         case ixgbe_phy_sfp_passive_unknown:
 881                 return 1;
 882         default:
 883                 return 0;
 884         }
 885 }
 886
 887 static inline int32_t
 888 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 889 {
 890         uint32_t ctrl_ext;
 891         int32_t status;
 892
 893         status = ixgbe_reset_hw(hw);
 894
 895         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 896         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 897         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 898         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 899         IXGBE_WRITE_FLUSH(hw);
 900
 901         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 902                 status = IXGBE_SUCCESS;
 903         return status;
 904 }
 905
 906 static inline void
 907 ixgbe_enable_intr(struct rte_eth_dev *dev)
 908 {
 909         struct ixgbe_interrupt *intr =
 910                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 911         struct ixgbe_hw *hw =
 912                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 913
 914         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 915         IXGBE_WRITE_FLUSH(hw);
 916 }
 917
 918 /*
 919  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 920  */
 921 static void
 922 ixgbe_disable_intr(struct ixgbe_hw *hw)
 923 {
 924         PMD_INIT_FUNC_TRACE();
 925
 926         if (hw->mac.type == ixgbe_mac_82598EB) {
 927                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 928         } else {
 929                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 930                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 931                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 932         }
 933         IXGBE_WRITE_FLUSH(hw);
 934 }
 935
 936 /*
 937  * This function resets queue statistics mapping registers.
 938  * From Niantic datasheet, Initialization of Statistics section:
 939  * "...if software requires the queue counters, the RQSMR and TQSM registers
 940  * must be re-programmed following a device reset.
 941  */
 942 static void
 943 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 944 {
 945         uint32_t i;
 946
 947         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 948                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 949                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 950         }
 951 }
 952
 953
 954 static int
 955 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 956                                   uint16_t queue_id,
 957                                   uint8_t stat_idx,
 958                                   uint8_t is_rx)
 959 {
 960 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 961 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 962 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 963
 964         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 965         struct ixgbe_stat_mapping_registers *stat_mappings =
 966                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 967         uint32_t qsmr_mask = 0;
 968         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 969         uint32_t q_map;
 970         uint8_t n, offset;
 971
 972         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 973                 (hw->mac.type != ixgbe_mac_X540) &&
 974                 (hw->mac.type != ixgbe_mac_X550) &&
 975                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 976                 (hw->mac.type != ixgbe_mac_X550EM_a))
 977                 return -ENOSYS;
 978
 979         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 980                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 981                      queue_id, stat_idx);
 982
 983         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 984         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 985                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 986                 return -EIO;
 987         }
 988         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 989
 990         /* Now clear any previous stat_idx set */
 991         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 992         if (!is_rx)
 993                 stat_mappings->tqsm[n] &= ~clearing_mask;
 994         else
 995                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 996
 997         q_map = (uint32_t)stat_idx;
 998         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 999         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1000         if (!is_rx)
1001                 stat_mappings->tqsm[n] |= qsmr_mask;
1002         else
1003                 stat_mappings->rqsmr[n] |= qsmr_mask;
1004
1005         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1006                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1007                      queue_id, stat_idx);
1008         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1009                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1010
1011         /* Now write the mapping in the appropriate register */
1012         if (is_rx) {
1013                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1014                              stat_mappings->rqsmr[n], n);
1015                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1016         } else {
1017                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1018                              stat_mappings->tqsm[n], n);
1019                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1020         }
1021         return 0;
1022 }
1023
1024 static void
1025 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1026 {
1027         struct ixgbe_stat_mapping_registers *stat_mappings =
1028                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030         int i;
1031
1032         /* write whatever was in stat mapping table to the NIC */
1033         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1034                 /* rx */
1035                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1036
1037                 /* tx */
1038                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1039         }
1040 }
1041
1042 static void
1043 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1044 {
1045         uint8_t i;
1046         struct ixgbe_dcb_tc_config *tc;
1047         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1048
1049         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1050         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1051         for (i = 0; i < dcb_max_tc; i++) {
1052                 tc = &dcb_config->tc_config[i];
1053                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1054                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1055                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1056                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1057                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1058                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1059                 tc->pfc = ixgbe_dcb_pfc_disabled;
1060         }
1061
1062         /* Initialize default user to priority mapping, UPx->TC0 */
1063         tc = &dcb_config->tc_config[0];
1064         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1065         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1066         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1067                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1068                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1069         }
1070         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1071         dcb_config->pfc_mode_enable = false;
1072         dcb_config->vt_mode = true;
1073         dcb_config->round_robin_enable = false;
1074         /* support all DCB capabilities in 82599 */
1075         dcb_config->support.capabilities = 0xFF;
1076
1077         /*we only support 4 Tcs for X540, X550 */
1078         if (hw->mac.type == ixgbe_mac_X540 ||
1079                 hw->mac.type == ixgbe_mac_X550 ||
1080                 hw->mac.type == ixgbe_mac_X550EM_x ||
1081                 hw->mac.type == ixgbe_mac_X550EM_a) {
1082                 dcb_config->num_tcs.pg_tcs = 4;
1083                 dcb_config->num_tcs.pfc_tcs = 4;
1084         }
1085 }
1086
1087 /*
1088  * Ensure that all locks are released before first NVM or PHY access
1089  */
1090 static void
1091 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1092 {
1093         uint16_t mask;
1094
1095         /*
1096          * Phy lock should not fail in this early stage. If this is the case,
1097          * it is due to an improper exit of the application.
1098          * So force the release of the faulty lock. Release of common lock
1099          * is done automatically by swfw_sync function.
1100          */
1101         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1102         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1103                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1104         }
1105         ixgbe_release_swfw_semaphore(hw, mask);
1106
1107         /*
1108          * These ones are more tricky since they are common to all ports; but
1109          * swfw_sync retries last long enough (1s) to be almost sure that if
1110          * lock can not be taken it is due to an improper lock of the
1111          * semaphore.
1112          */
1113         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1114         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1115                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1116         }
1117         ixgbe_release_swfw_semaphore(hw, mask);
1118 }
1119
1120 /*
1121  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1122  * It returns 0 on success.
1123  */
1124 static int
1125 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1126 {
1127         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1128         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1129         struct ixgbe_hw *hw =
1130                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1131         struct ixgbe_vfta *shadow_vfta =
1132                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1133         struct ixgbe_hwstrip *hwstrip =
1134                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1135         struct ixgbe_dcb_config *dcb_config =
1136                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1137         struct ixgbe_filter_info *filter_info =
1138                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1139         uint32_t ctrl_ext;
1140         uint16_t csum;
1141         int diag, i;
1142
1143         PMD_INIT_FUNC_TRACE();
1144
1145         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1146         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1147         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1148         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1149
1150         /*
1151          * For secondary processes, we don't initialise any further as primary
1152          * has already done this work. Only check we don't need a different
1153          * RX and TX function.
1154          */
1155         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1156                 struct ixgbe_tx_queue *txq;
1157                 /* TX queue function in primary, set by last queue initialized
1158                  * Tx queue may not initialized by primary process
1159                  */
1160                 if (eth_dev->data->tx_queues) {
1161                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1162                         ixgbe_set_tx_function(eth_dev, txq);
1163                 } else {
1164                         /* Use default TX function if we get here */
1165                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1166                                      "Using default TX function.");
1167                 }
1168
1169                 ixgbe_set_rx_function(eth_dev);
1170
1171                 return 0;
1172         }
1173
1174         rte_eth_copy_pci_info(eth_dev, pci_dev);
1175         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1176
1177         /* Vendor and Device ID need to be set before init of shared code */
1178         hw->device_id = pci_dev->id.device_id;
1179         hw->vendor_id = pci_dev->id.vendor_id;
1180         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1181         hw->allow_unsupported_sfp = 1;
1182
1183         /* Initialize the shared code (base driver) */
1184 #ifdef RTE_NIC_BYPASS
1185         diag = ixgbe_bypass_init_shared_code(hw);
1186 #else
1187         diag = ixgbe_init_shared_code(hw);
1188 #endif /* RTE_NIC_BYPASS */
1189
1190         if (diag != IXGBE_SUCCESS) {
1191                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1192                 return -EIO;
1193         }
1194
1195         /* pick up the PCI bus settings for reporting later */
1196         ixgbe_get_bus_info(hw);
1197
1198         /* Unlock any pending hardware semaphore */
1199         ixgbe_swfw_lock_reset(hw);
1200
1201         /* Initialize DCB configuration*/
1202         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1203         ixgbe_dcb_init(hw, dcb_config);
1204         /* Get Hardware Flow Control setting */
1205         hw->fc.requested_mode = ixgbe_fc_full;
1206         hw->fc.current_mode = ixgbe_fc_full;
1207         hw->fc.pause_time = IXGBE_FC_PAUSE;
1208         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1209                 hw->fc.low_water[i] = IXGBE_FC_LO;
1210                 hw->fc.high_water[i] = IXGBE_FC_HI;
1211         }
1212         hw->fc.send_xon = 1;
1213
1214         /* Make sure we have a good EEPROM before we read from it */
1215         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1216         if (diag != IXGBE_SUCCESS) {
1217                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1218                 return -EIO;
1219         }
1220
1221 #ifdef RTE_NIC_BYPASS
1222         diag = ixgbe_bypass_init_hw(hw);
1223 #else
1224         diag = ixgbe_init_hw(hw);
1225 #endif /* RTE_NIC_BYPASS */
1226
1227         /*
1228          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1229          * is called too soon after the kernel driver unbinding/binding occurs.
1230          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1231          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1232          * also called. See ixgbe_identify_phy_82599(). The reason for the
1233          * failure is not known, and only occuts when virtualisation features
1234          * are disabled in the bios. A delay of 100ms  was found to be enough by
1235          * trial-and-error, and is doubled to be safe.
1236          */
1237         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1238                 rte_delay_ms(200);
1239                 diag = ixgbe_init_hw(hw);
1240         }
1241
1242         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1243                 diag = IXGBE_SUCCESS;
1244
1245         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1246                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1247                              "LOM.  Please be aware there may be issues associated "
1248                              "with your hardware.");
1249                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1250                              "please contact your Intel or hardware representative "
1251                              "who provided you with this hardware.");
1252         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1253                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1254         if (diag) {
1255                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1256                 return -EIO;
1257         }
1258
1259         /* Reset the hw statistics */
1260         ixgbe_dev_stats_reset(eth_dev);
1261
1262         /* disable interrupt */
1263         ixgbe_disable_intr(hw);
1264
1265         /* reset mappings for queue statistics hw counters*/
1266         ixgbe_reset_qstat_mappings(hw);
1267
1268         /* Allocate memory for storing MAC addresses */
1269         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1270                                                hw->mac.num_rar_entries, 0);
1271         if (eth_dev->data->mac_addrs == NULL) {
1272                 PMD_INIT_LOG(ERR,
1273                              "Failed to allocate %u bytes needed to store "
1274                              "MAC addresses",
1275                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1276                 return -ENOMEM;
1277         }
1278         /* Copy the permanent MAC address */
1279         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1280                         &eth_dev->data->mac_addrs[0]);
1281
1282         /* Allocate memory for storing hash filter MAC addresses */
1283         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1284                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1285         if (eth_dev->data->hash_mac_addrs == NULL) {
1286                 PMD_INIT_LOG(ERR,
1287                              "Failed to allocate %d bytes needed to store MAC addresses",
1288                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1289                 return -ENOMEM;
1290         }
1291
1292         /* initialize the vfta */
1293         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1294
1295         /* initialize the hw strip bitmap*/
1296         memset(hwstrip, 0, sizeof(*hwstrip));
1297
1298         /* initialize PF if max_vfs not zero */
1299         ixgbe_pf_host_init(eth_dev);
1300
1301         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1302         /* let hardware know driver is loaded */
1303         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1304         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1305         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1306         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1307         IXGBE_WRITE_FLUSH(hw);
1308
1309         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1310                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1311                              (int) hw->mac.type, (int) hw->phy.type,
1312                              (int) hw->phy.sfp_type);
1313         else
1314                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1315                              (int) hw->mac.type, (int) hw->phy.type);
1316
1317         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1318                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1319                      pci_dev->id.device_id);
1320
1321         rte_intr_callback_register(intr_handle,
1322                                    ixgbe_dev_interrupt_handler, eth_dev);
1323
1324         /* enable uio/vfio intr/eventfd mapping */
1325         rte_intr_enable(intr_handle);
1326
1327         /* enable support intr */
1328         ixgbe_enable_intr(eth_dev);
1329
1330         /* initialize filter info */
1331         memset(filter_info, 0,
1332                sizeof(struct ixgbe_filter_info));
1333
1334         /* initialize 5tuple filter list */
1335         TAILQ_INIT(&filter_info->fivetuple_list);
1336
1337         /* initialize flow director filter list & hash */
1338         ixgbe_fdir_filter_init(eth_dev);
1339
1340         /* initialize l2 tunnel filter list & hash */
1341         ixgbe_l2_tn_filter_init(eth_dev);
1342
1343         TAILQ_INIT(&filter_ntuple_list);
1344         TAILQ_INIT(&filter_ethertype_list);
1345         TAILQ_INIT(&filter_syn_list);
1346         TAILQ_INIT(&filter_fdir_list);
1347         TAILQ_INIT(&filter_l2_tunnel_list);
1348         TAILQ_INIT(&ixgbe_flow_list);
1349
1350         return 0;
1351 }
1352
1353 static int
1354 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1355 {
1356         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1357         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1358         struct ixgbe_hw *hw;
1359
1360         PMD_INIT_FUNC_TRACE();
1361
1362         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1363                 return -EPERM;
1364
1365         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1366
1367         if (hw->adapter_stopped == 0)
1368                 ixgbe_dev_close(eth_dev);
1369
1370         eth_dev->dev_ops = NULL;
1371         eth_dev->rx_pkt_burst = NULL;
1372         eth_dev->tx_pkt_burst = NULL;
1373
1374         /* Unlock any pending hardware semaphore */
1375         ixgbe_swfw_lock_reset(hw);
1376
1377         /* disable uio intr before callback unregister */
1378         rte_intr_disable(intr_handle);
1379         rte_intr_callback_unregister(intr_handle,
1380                                      ixgbe_dev_interrupt_handler, eth_dev);
1381
1382         /* uninitialize PF if max_vfs not zero */
1383         ixgbe_pf_host_uninit(eth_dev);
1384
1385         rte_free(eth_dev->data->mac_addrs);
1386         eth_dev->data->mac_addrs = NULL;
1387
1388         rte_free(eth_dev->data->hash_mac_addrs);
1389         eth_dev->data->hash_mac_addrs = NULL;
1390
1391         /* remove all the fdir filters & hash */
1392         ixgbe_fdir_filter_uninit(eth_dev);
1393
1394         /* remove all the L2 tunnel filters & hash */
1395         ixgbe_l2_tn_filter_uninit(eth_dev);
1396
1397         /* Remove all ntuple filters of the device */
1398         ixgbe_ntuple_filter_uninit(eth_dev);
1399
1400         /* clear all the filters list */
1401         ixgbe_filterlist_flush();
1402
1403         return 0;
1404 }
1405
1406 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1407 {
1408         struct ixgbe_filter_info *filter_info =
1409                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1410         struct ixgbe_5tuple_filter *p_5tuple;
1411
1412         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1413                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1414                              p_5tuple,
1415                              entries);
1416                 rte_free(p_5tuple);
1417         }
1418         memset(filter_info->fivetuple_mask, 0,
1419                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1420
1421         return 0;
1422 }
1423
1424 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1425 {
1426         struct ixgbe_hw_fdir_info *fdir_info =
1427                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1428         struct ixgbe_fdir_filter *fdir_filter;
1429
1430                 if (fdir_info->hash_map)
1431                 rte_free(fdir_info->hash_map);
1432         if (fdir_info->hash_handle)
1433                 rte_hash_free(fdir_info->hash_handle);
1434
1435         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1436                 TAILQ_REMOVE(&fdir_info->fdir_list,
1437                              fdir_filter,
1438                              entries);
1439                 rte_free(fdir_filter);
1440         }
1441
1442         return 0;
1443 }
1444
1445 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1446 {
1447         struct ixgbe_l2_tn_info *l2_tn_info =
1448                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1449         struct ixgbe_l2_tn_filter *l2_tn_filter;
1450
1451         if (l2_tn_info->hash_map)
1452                 rte_free(l2_tn_info->hash_map);
1453         if (l2_tn_info->hash_handle)
1454                 rte_hash_free(l2_tn_info->hash_handle);
1455
1456         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1457                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1458                              l2_tn_filter,
1459                              entries);
1460                 rte_free(l2_tn_filter);
1461         }
1462
1463         return 0;
1464 }
1465
1466 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1467 {
1468         struct ixgbe_hw_fdir_info *fdir_info =
1469                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1470         char fdir_hash_name[RTE_HASH_NAMESIZE];
1471         struct rte_hash_parameters fdir_hash_params = {
1472                 .name = fdir_hash_name,
1473                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1474                 .key_len = sizeof(union ixgbe_atr_input),
1475                 .hash_func = rte_hash_crc,
1476                 .hash_func_init_val = 0,
1477                 .socket_id = rte_socket_id(),
1478         };
1479
1480         TAILQ_INIT(&fdir_info->fdir_list);
1481         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1482                  "fdir_%s", eth_dev->data->name);
1483         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1484         if (!fdir_info->hash_handle) {
1485                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1486                 return -EINVAL;
1487         }
1488         fdir_info->hash_map = rte_zmalloc("ixgbe",
1489                                           sizeof(struct ixgbe_fdir_filter *) *
1490                                           IXGBE_MAX_FDIR_FILTER_NUM,
1491                                           0);
1492         if (!fdir_info->hash_map) {
1493                 PMD_INIT_LOG(ERR,
1494                              "Failed to allocate memory for fdir hash map!");
1495                 return -ENOMEM;
1496         }
1497         fdir_info->mask_added = FALSE;
1498
1499         return 0;
1500 }
1501
1502 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1503 {
1504         struct ixgbe_l2_tn_info *l2_tn_info =
1505                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1506         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1507         struct rte_hash_parameters l2_tn_hash_params = {
1508                 .name = l2_tn_hash_name,
1509                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1510                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1511                 .hash_func = rte_hash_crc,
1512                 .hash_func_init_val = 0,
1513                 .socket_id = rte_socket_id(),
1514         };
1515
1516         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1517         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1518                  "l2_tn_%s", eth_dev->data->name);
1519         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1520         if (!l2_tn_info->hash_handle) {
1521                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1522                 return -EINVAL;
1523         }
1524         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1525                                    sizeof(struct ixgbe_l2_tn_filter *) *
1526                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1527                                    0);
1528         if (!l2_tn_info->hash_map) {
1529                 PMD_INIT_LOG(ERR,
1530                         "Failed to allocate memory for L2 TN hash map!");
1531                 return -ENOMEM;
1532         }
1533         l2_tn_info->e_tag_en = FALSE;
1534         l2_tn_info->e_tag_fwd_en = FALSE;
1535         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1536
1537         return 0;
1538 }
1539 /*
1540  * Negotiate mailbox API version with the PF.
1541  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1542  * Then we try to negotiate starting with the most recent one.
1543  * If all negotiation attempts fail, then we will proceed with
1544  * the default one (ixgbe_mbox_api_10).
1545  */
1546 static void
1547 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1548 {
1549         int32_t i;
1550
1551         /* start with highest supported, proceed down */
1552         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1553                 ixgbe_mbox_api_12,
1554                 ixgbe_mbox_api_11,
1555                 ixgbe_mbox_api_10,
1556         };
1557
1558         for (i = 0;
1559                         i != RTE_DIM(sup_ver) &&
1560                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1561                         i++)
1562                 ;
1563 }
1564
1565 static void
1566 generate_random_mac_addr(struct ether_addr *mac_addr)
1567 {
1568         uint64_t random;
1569
1570         /* Set Organizationally Unique Identifier (OUI) prefix. */
1571         mac_addr->addr_bytes[0] = 0x00;
1572         mac_addr->addr_bytes[1] = 0x09;
1573         mac_addr->addr_bytes[2] = 0xC0;
1574         /* Force indication of locally assigned MAC address. */
1575         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1576         /* Generate the last 3 bytes of the MAC address with a random number. */
1577         random = rte_rand();
1578         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1579 }
1580
1581 /*
1582  * Virtual Function device init
1583  */
1584 static int
1585 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1586 {
1587         int diag;
1588         uint32_t tc, tcs;
1589         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1590         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1591         struct ixgbe_hw *hw =
1592                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1593         struct ixgbe_vfta *shadow_vfta =
1594                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1595         struct ixgbe_hwstrip *hwstrip =
1596                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1597         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1598
1599         PMD_INIT_FUNC_TRACE();
1600
1601         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1602         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1603         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1604
1605         /* for secondary processes, we don't initialise any further as primary
1606          * has already done this work. Only check we don't need a different
1607          * RX function
1608          */
1609         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1610                 struct ixgbe_tx_queue *txq;
1611                 /* TX queue function in primary, set by last queue initialized
1612                  * Tx queue may not initialized by primary process
1613                  */
1614                 if (eth_dev->data->tx_queues) {
1615                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1616                         ixgbe_set_tx_function(eth_dev, txq);
1617                 } else {
1618                         /* Use default TX function if we get here */
1619                         PMD_INIT_LOG(NOTICE,
1620                                      "No TX queues configured yet. Using default TX function.");
1621                 }
1622
1623                 ixgbe_set_rx_function(eth_dev);
1624
1625                 return 0;
1626         }
1627
1628         rte_eth_copy_pci_info(eth_dev, pci_dev);
1629         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1630
1631         hw->device_id = pci_dev->id.device_id;
1632         hw->vendor_id = pci_dev->id.vendor_id;
1633         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1634
1635         /* initialize the vfta */
1636         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1637
1638         /* initialize the hw strip bitmap*/
1639         memset(hwstrip, 0, sizeof(*hwstrip));
1640
1641         /* Initialize the shared code (base driver) */
1642         diag = ixgbe_init_shared_code(hw);
1643         if (diag != IXGBE_SUCCESS) {
1644                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1645                 return -EIO;
1646         }
1647
1648         /* init_mailbox_params */
1649         hw->mbx.ops.init_params(hw);
1650
1651         /* Reset the hw statistics */
1652         ixgbevf_dev_stats_reset(eth_dev);
1653
1654         /* Disable the interrupts for VF */
1655         ixgbevf_intr_disable(hw);
1656
1657         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1658         diag = hw->mac.ops.reset_hw(hw);
1659
1660         /*
1661          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1662          * the underlying PF driver has not assigned a MAC address to the VF.
1663          * In this case, assign a random MAC address.
1664          */
1665         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1666                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1667                 return diag;
1668         }
1669
1670         /* negotiate mailbox API version to use with the PF. */
1671         ixgbevf_negotiate_api(hw);
1672
1673         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1674         ixgbevf_get_queues(hw, &tcs, &tc);
1675
1676         /* Allocate memory for storing MAC addresses */
1677         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1678                                                hw->mac.num_rar_entries, 0);
1679         if (eth_dev->data->mac_addrs == NULL) {
1680                 PMD_INIT_LOG(ERR,
1681                              "Failed to allocate %u bytes needed to store "
1682                              "MAC addresses",
1683                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1684                 return -ENOMEM;
1685         }
1686
1687         /* Generate a random MAC address, if none was assigned by PF. */
1688         if (is_zero_ether_addr(perm_addr)) {
1689                 generate_random_mac_addr(perm_addr);
1690                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1691                 if (diag) {
1692                         rte_free(eth_dev->data->mac_addrs);
1693                         eth_dev->data->mac_addrs = NULL;
1694                         return diag;
1695                 }
1696                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1697                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1698                              "%02x:%02x:%02x:%02x:%02x:%02x",
1699                              perm_addr->addr_bytes[0],
1700                              perm_addr->addr_bytes[1],
1701                              perm_addr->addr_bytes[2],
1702                              perm_addr->addr_bytes[3],
1703                              perm_addr->addr_bytes[4],
1704                              perm_addr->addr_bytes[5]);
1705         }
1706
1707         /* Copy the permanent MAC address */
1708         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1709
1710         /* reset the hardware with the new settings */
1711         diag = hw->mac.ops.start_hw(hw);
1712         switch (diag) {
1713         case  0:
1714                 break;
1715
1716         default:
1717                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1718                 return -EIO;
1719         }
1720
1721         rte_intr_callback_register(intr_handle,
1722                                    ixgbevf_dev_interrupt_handler, eth_dev);
1723         rte_intr_enable(intr_handle);
1724         ixgbevf_intr_enable(hw);
1725
1726         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1727                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1728                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1729
1730         return 0;
1731 }
1732
1733 /* Virtual Function device uninit */
1734
1735 static int
1736 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1737 {
1738         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1739         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1740         struct ixgbe_hw *hw;
1741
1742         PMD_INIT_FUNC_TRACE();
1743
1744         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1745                 return -EPERM;
1746
1747         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1748
1749         if (hw->adapter_stopped == 0)
1750                 ixgbevf_dev_close(eth_dev);
1751
1752         eth_dev->dev_ops = NULL;
1753         eth_dev->rx_pkt_burst = NULL;
1754         eth_dev->tx_pkt_burst = NULL;
1755
1756         /* Disable the interrupts for VF */
1757         ixgbevf_intr_disable(hw);
1758
1759         rte_free(eth_dev->data->mac_addrs);
1760         eth_dev->data->mac_addrs = NULL;
1761
1762         rte_intr_disable(intr_handle);
1763         rte_intr_callback_unregister(intr_handle,
1764                                      ixgbevf_dev_interrupt_handler, eth_dev);
1765
1766         return 0;
1767 }
1768
1769 static struct eth_driver rte_ixgbe_pmd = {
1770         .pci_drv = {
1771                 .id_table = pci_id_ixgbe_map,
1772                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1773                 .probe = rte_eth_dev_pci_probe,
1774                 .remove = rte_eth_dev_pci_remove,
1775         },
1776         .eth_dev_init = eth_ixgbe_dev_init,
1777         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1778         .dev_private_size = sizeof(struct ixgbe_adapter),
1779 };
1780
1781 /*
1782  * virtual function driver struct
1783  */
1784 static struct eth_driver rte_ixgbevf_pmd = {
1785         .pci_drv = {
1786                 .id_table = pci_id_ixgbevf_map,
1787                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1788                 .probe = rte_eth_dev_pci_probe,
1789                 .remove = rte_eth_dev_pci_remove,
1790         },
1791         .eth_dev_init = eth_ixgbevf_dev_init,
1792         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1793         .dev_private_size = sizeof(struct ixgbe_adapter),
1794 };
1795
1796 static int
1797 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1798 {
1799         struct ixgbe_hw *hw =
1800                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1801         struct ixgbe_vfta *shadow_vfta =
1802                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1803         uint32_t vfta;
1804         uint32_t vid_idx;
1805         uint32_t vid_bit;
1806
1807         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1808         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1809         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1810         if (on)
1811                 vfta |= vid_bit;
1812         else
1813                 vfta &= ~vid_bit;
1814         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1815
1816         /* update local VFTA copy */
1817         shadow_vfta->vfta[vid_idx] = vfta;
1818
1819         return 0;
1820 }
1821
1822 static void
1823 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1824 {
1825         if (on)
1826                 ixgbe_vlan_hw_strip_enable(dev, queue);
1827         else
1828                 ixgbe_vlan_hw_strip_disable(dev, queue);
1829 }
1830
1831 static int
1832 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1833                     enum rte_vlan_type vlan_type,
1834                     uint16_t tpid)
1835 {
1836         struct ixgbe_hw *hw =
1837                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1838         int ret = 0;
1839         uint32_t reg;
1840         uint32_t qinq;
1841
1842         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1843         qinq &= IXGBE_DMATXCTL_GDV;
1844
1845         switch (vlan_type) {
1846         case ETH_VLAN_TYPE_INNER:
1847                 if (qinq) {
1848                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1849                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1850                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1851                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1852                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1853                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1854                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1855                 } else {
1856                         ret = -ENOTSUP;
1857                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1858                                     " by single VLAN");
1859                 }
1860                 break;
1861         case ETH_VLAN_TYPE_OUTER:
1862                 if (qinq) {
1863                         /* Only the high 16-bits is valid */
1864                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1865                                         IXGBE_EXVET_VET_EXT_SHIFT);
1866                 } else {
1867                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1868                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1869                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1870                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1871                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1872                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1873                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1874                 }
1875
1876                 break;
1877         default:
1878                 ret = -EINVAL;
1879                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1880                 break;
1881         }
1882
1883         return ret;
1884 }
1885
1886 void
1887 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1888 {
1889         struct ixgbe_hw *hw =
1890                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1891         uint32_t vlnctrl;
1892
1893         PMD_INIT_FUNC_TRACE();
1894
1895         /* Filter Table Disable */
1896         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1897         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1898
1899         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1900 }
1901
1902 void
1903 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1904 {
1905         struct ixgbe_hw *hw =
1906                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1907         struct ixgbe_vfta *shadow_vfta =
1908                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1909         uint32_t vlnctrl;
1910         uint16_t i;
1911
1912         PMD_INIT_FUNC_TRACE();
1913
1914         /* Filter Table Enable */
1915         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1916         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1917         vlnctrl |= IXGBE_VLNCTRL_VFE;
1918
1919         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1920
1921         /* write whatever is in local vfta copy */
1922         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1923                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1924 }
1925
1926 static void
1927 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1928 {
1929         struct ixgbe_hwstrip *hwstrip =
1930                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1931         struct ixgbe_rx_queue *rxq;
1932
1933         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1934                 return;
1935
1936         if (on)
1937                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1938         else
1939                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1940
1941         if (queue >= dev->data->nb_rx_queues)
1942                 return;
1943
1944         rxq = dev->data->rx_queues[queue];
1945
1946         if (on)
1947                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1948         else
1949                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1950 }
1951
1952 static void
1953 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1954 {
1955         struct ixgbe_hw *hw =
1956                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1957         uint32_t ctrl;
1958
1959         PMD_INIT_FUNC_TRACE();
1960
1961         if (hw->mac.type == ixgbe_mac_82598EB) {
1962                 /* No queue level support */
1963                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1964                 return;
1965         }
1966
1967         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1968         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1969         ctrl &= ~IXGBE_RXDCTL_VME;
1970         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1971
1972         /* record those setting for HW strip per queue */
1973         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1974 }
1975
1976 static void
1977 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1978 {
1979         struct ixgbe_hw *hw =
1980                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1981         uint32_t ctrl;
1982
1983         PMD_INIT_FUNC_TRACE();
1984
1985         if (hw->mac.type == ixgbe_mac_82598EB) {
1986                 /* No queue level supported */
1987                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1988                 return;
1989         }
1990
1991         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1992         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1993         ctrl |= IXGBE_RXDCTL_VME;
1994         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1995
1996         /* record those setting for HW strip per queue */
1997         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1998 }
1999
2000 void
2001 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2002 {
2003         struct ixgbe_hw *hw =
2004                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005         uint32_t ctrl;
2006         uint16_t i;
2007         struct ixgbe_rx_queue *rxq;
2008
2009         PMD_INIT_FUNC_TRACE();
2010
2011         if (hw->mac.type == ixgbe_mac_82598EB) {
2012                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2013                 ctrl &= ~IXGBE_VLNCTRL_VME;
2014                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2015         } else {
2016                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2017                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2018                         rxq = dev->data->rx_queues[i];
2019                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2020                         ctrl &= ~IXGBE_RXDCTL_VME;
2021                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2022
2023                         /* record those setting for HW strip per queue */
2024                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2025                 }
2026         }
2027 }
2028
2029 void
2030 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2031 {
2032         struct ixgbe_hw *hw =
2033                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2034         uint32_t ctrl;
2035         uint16_t i;
2036         struct ixgbe_rx_queue *rxq;
2037
2038         PMD_INIT_FUNC_TRACE();
2039
2040         if (hw->mac.type == ixgbe_mac_82598EB) {
2041                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2042                 ctrl |= IXGBE_VLNCTRL_VME;
2043                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2044         } else {
2045                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2046                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2047                         rxq = dev->data->rx_queues[i];
2048                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2049                         ctrl |= IXGBE_RXDCTL_VME;
2050                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2051
2052                         /* record those setting for HW strip per queue */
2053                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2054                 }
2055         }
2056 }
2057
2058 static void
2059 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2060 {
2061         struct ixgbe_hw *hw =
2062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2063         uint32_t ctrl;
2064
2065         PMD_INIT_FUNC_TRACE();
2066
2067         /* DMATXCTRL: Geric Double VLAN Disable */
2068         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2069         ctrl &= ~IXGBE_DMATXCTL_GDV;
2070         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2071
2072         /* CTRL_EXT: Global Double VLAN Disable */
2073         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2074         ctrl &= ~IXGBE_EXTENDED_VLAN;
2075         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2076
2077 }
2078
2079 static void
2080 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2081 {
2082         struct ixgbe_hw *hw =
2083                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084         uint32_t ctrl;
2085
2086         PMD_INIT_FUNC_TRACE();
2087
2088         /* DMATXCTRL: Geric Double VLAN Enable */
2089         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2090         ctrl |= IXGBE_DMATXCTL_GDV;
2091         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2092
2093         /* CTRL_EXT: Global Double VLAN Enable */
2094         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2095         ctrl |= IXGBE_EXTENDED_VLAN;
2096         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2097
2098         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2099         if (hw->mac.type == ixgbe_mac_X550 ||
2100             hw->mac.type == ixgbe_mac_X550EM_x ||
2101             hw->mac.type == ixgbe_mac_X550EM_a) {
2102                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2103                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2104                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2105         }
2106
2107         /*
2108          * VET EXT field in the EXVET register = 0x8100 by default
2109          * So no need to change. Same to VT field of DMATXCTL register
2110          */
2111 }
2112
2113 static void
2114 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2115 {
2116         if (mask & ETH_VLAN_STRIP_MASK) {
2117                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2118                         ixgbe_vlan_hw_strip_enable_all(dev);
2119                 else
2120                         ixgbe_vlan_hw_strip_disable_all(dev);
2121         }
2122
2123         if (mask & ETH_VLAN_FILTER_MASK) {
2124                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2125                         ixgbe_vlan_hw_filter_enable(dev);
2126                 else
2127                         ixgbe_vlan_hw_filter_disable(dev);
2128         }
2129
2130         if (mask & ETH_VLAN_EXTEND_MASK) {
2131                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2132                         ixgbe_vlan_hw_extend_enable(dev);
2133                 else
2134                         ixgbe_vlan_hw_extend_disable(dev);
2135         }
2136 }
2137
2138 static void
2139 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2140 {
2141         struct ixgbe_hw *hw =
2142                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2143         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2144         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2145
2146         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2147         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2148 }
2149
2150 static int
2151 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2152 {
2153         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2154
2155         switch (nb_rx_q) {
2156         case 1:
2157         case 2:
2158                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2159                 break;
2160         case 4:
2161                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2162                 break;
2163         default:
2164                 return -EINVAL;
2165         }
2166
2167         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2168         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2169
2170         return 0;
2171 }
2172
2173 static int
2174 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2175 {
2176         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2177         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2178         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2179         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2180
2181         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2182                 /* check multi-queue mode */
2183                 switch (dev_conf->rxmode.mq_mode) {
2184                 case ETH_MQ_RX_VMDQ_DCB:
2185                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2186                         break;
2187                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2188                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2189                         PMD_INIT_LOG(ERR, "SRIOV active,"
2190                                         " unsupported mq_mode rx %d.",
2191                                         dev_conf->rxmode.mq_mode);
2192                         return -EINVAL;
2193                 case ETH_MQ_RX_RSS:
2194                 case ETH_MQ_RX_VMDQ_RSS:
2195                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2196                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2197                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2198                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2199                                                 " invalid queue number"
2200                                                 " for VMDQ RSS, allowed"
2201                                                 " value are 1, 2 or 4.");
2202                                         return -EINVAL;
2203                                 }
2204                         break;
2205                 case ETH_MQ_RX_VMDQ_ONLY:
2206                 case ETH_MQ_RX_NONE:
2207                         /* if nothing mq mode configure, use default scheme */
2208                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2209                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2210                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2211                         break;
2212                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2213                         /* SRIOV only works in VMDq enable mode */
2214                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2215                                         " wrong mq_mode rx %d.",
2216                                         dev_conf->rxmode.mq_mode);
2217                         return -EINVAL;
2218                 }
2219
2220                 switch (dev_conf->txmode.mq_mode) {
2221                 case ETH_MQ_TX_VMDQ_DCB:
2222                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2223                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2224                         break;
2225                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2226                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2227                         break;
2228                 }
2229
2230                 /* check valid queue number */
2231                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2232                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2233                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2234                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2235                                         " must be less than or equal to %d.",
2236                                         nb_rx_q, nb_tx_q,
2237                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2238                         return -EINVAL;
2239                 }
2240         } else {
2241                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2242                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2243                                           " not supported.");
2244                         return -EINVAL;
2245                 }
2246                 /* check configuration for vmdb+dcb mode */
2247                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2248                         const struct rte_eth_vmdq_dcb_conf *conf;
2249
2250                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2251                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2252                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2253                                 return -EINVAL;
2254                         }
2255                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2256                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2257                                conf->nb_queue_pools == ETH_32_POOLS)) {
2258                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2259                                                 " nb_queue_pools must be %d or %d.",
2260                                                 ETH_16_POOLS, ETH_32_POOLS);
2261                                 return -EINVAL;
2262                         }
2263                 }
2264                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2265                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2266
2267                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2268                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2269                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2270                                 return -EINVAL;
2271                         }
2272                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2273                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2274                                conf->nb_queue_pools == ETH_32_POOLS)) {
2275                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2276                                                 " nb_queue_pools != %d and"
2277                                                 " nb_queue_pools != %d.",
2278                                                 ETH_16_POOLS, ETH_32_POOLS);
2279                                 return -EINVAL;
2280                         }
2281                 }
2282
2283                 /* For DCB mode check our configuration before we go further */
2284                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2285                         const struct rte_eth_dcb_rx_conf *conf;
2286
2287                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2288                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2289                                                  IXGBE_DCB_NB_QUEUES);
2290                                 return -EINVAL;
2291                         }
2292                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2293                         if (!(conf->nb_tcs == ETH_4_TCS ||
2294                                conf->nb_tcs == ETH_8_TCS)) {
2295                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2296                                                 " and nb_tcs != %d.",
2297                                                 ETH_4_TCS, ETH_8_TCS);
2298                                 return -EINVAL;
2299                         }
2300                 }
2301
2302                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2303                         const struct rte_eth_dcb_tx_conf *conf;
2304
2305                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2306                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2307                                                  IXGBE_DCB_NB_QUEUES);
2308                                 return -EINVAL;
2309                         }
2310                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2311                         if (!(conf->nb_tcs == ETH_4_TCS ||
2312                                conf->nb_tcs == ETH_8_TCS)) {
2313                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2314                                                 " and nb_tcs != %d.",
2315                                                 ETH_4_TCS, ETH_8_TCS);
2316                                 return -EINVAL;
2317                         }
2318                 }
2319
2320                 /*
2321                  * When DCB/VT is off, maximum number of queues changes,
2322                  * except for 82598EB, which remains constant.
2323                  */
2324                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2325                                 hw->mac.type != ixgbe_mac_82598EB) {
2326                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2327                                 PMD_INIT_LOG(ERR,
2328                                              "Neither VT nor DCB are enabled, "
2329                                              "nb_tx_q > %d.",
2330                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2331                                 return -EINVAL;
2332                         }
2333                 }
2334         }
2335         return 0;
2336 }
2337
2338 static int
2339 ixgbe_dev_configure(struct rte_eth_dev *dev)
2340 {
2341         struct ixgbe_interrupt *intr =
2342                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2343         struct ixgbe_adapter *adapter =
2344                 (struct ixgbe_adapter *)dev->data->dev_private;
2345         int ret;
2346
2347         PMD_INIT_FUNC_TRACE();
2348         /* multipe queue mode checking */
2349         ret  = ixgbe_check_mq_mode(dev);
2350         if (ret != 0) {
2351                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2352                             ret);
2353                 return ret;
2354         }
2355
2356         /* set flag to update link status after init */
2357         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2358
2359         /*
2360          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2361          * allocation or vector Rx preconditions we will reset it.
2362          */
2363         adapter->rx_bulk_alloc_allowed = true;
2364         adapter->rx_vec_allowed = true;
2365
2366         return 0;
2367 }
2368
2369 static void
2370 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2371 {
2372         struct ixgbe_hw *hw =
2373                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2374         struct ixgbe_interrupt *intr =
2375                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2376         uint32_t gpie;
2377
2378         /* only set up it on X550EM_X */
2379         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2380                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2381                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2382                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2383                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2384                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2385         }
2386 }
2387
2388 /*
2389  * Configure device link speed and setup link.
2390  * It returns 0 on success.
2391  */
2392 static int
2393 ixgbe_dev_start(struct rte_eth_dev *dev)
2394 {
2395         struct ixgbe_hw *hw =
2396                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397         struct ixgbe_vf_info *vfinfo =
2398                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2399         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2400         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2401         uint32_t intr_vector = 0;
2402         int err, link_up = 0, negotiate = 0;
2403         uint32_t speed = 0;
2404         int mask = 0;
2405         int status;
2406         uint16_t vf, idx;
2407         uint32_t *link_speeds;
2408
2409         PMD_INIT_FUNC_TRACE();
2410
2411         /* IXGBE devices don't support:
2412         *    - half duplex (checked afterwards for valid speeds)
2413         *    - fixed speed: TODO implement
2414         */
2415         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2416                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2417                              dev->data->port_id);
2418                 return -EINVAL;
2419         }
2420
2421         /* disable uio/vfio intr/eventfd mapping */
2422         rte_intr_disable(intr_handle);
2423
2424         /* stop adapter */
2425         hw->adapter_stopped = 0;
2426         ixgbe_stop_adapter(hw);
2427
2428         /* reinitialize adapter
2429          * this calls reset and start
2430          */
2431         status = ixgbe_pf_reset_hw(hw);
2432         if (status != 0)
2433                 return -1;
2434         hw->mac.ops.start_hw(hw);
2435         hw->mac.get_link_status = true;
2436
2437         /* configure PF module if SRIOV enabled */
2438         ixgbe_pf_host_configure(dev);
2439
2440         ixgbe_dev_phy_intr_setup(dev);
2441
2442         /* check and configure queue intr-vector mapping */
2443         if ((rte_intr_cap_multiple(intr_handle) ||
2444              !RTE_ETH_DEV_SRIOV(dev).active) &&
2445             dev->data->dev_conf.intr_conf.rxq != 0) {
2446                 intr_vector = dev->data->nb_rx_queues;
2447                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2448                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2449                                         IXGBE_MAX_INTR_QUEUE_NUM);
2450                         return -ENOTSUP;
2451                 }
2452                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2453                         return -1;
2454         }
2455
2456         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2457                 intr_handle->intr_vec =
2458                         rte_zmalloc("intr_vec",
2459                                     dev->data->nb_rx_queues * sizeof(int), 0);
2460                 if (intr_handle->intr_vec == NULL) {
2461                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2462                                      " intr_vec\n", dev->data->nb_rx_queues);
2463                         return -ENOMEM;
2464                 }
2465         }
2466
2467         /* confiugre msix for sleep until rx interrupt */
2468         ixgbe_configure_msix(dev);
2469
2470         /* initialize transmission unit */
2471         ixgbe_dev_tx_init(dev);
2472
2473         /* This can fail when allocating mbufs for descriptor rings */
2474         err = ixgbe_dev_rx_init(dev);
2475         if (err) {
2476                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2477                 goto error;
2478         }
2479
2480     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2481                 ETH_VLAN_EXTEND_MASK;
2482         ixgbe_vlan_offload_set(dev, mask);
2483
2484         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2485                 /* Enable vlan filtering for VMDq */
2486                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2487         }
2488
2489         /* Configure DCB hw */
2490         ixgbe_configure_dcb(dev);
2491
2492         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2493                 err = ixgbe_fdir_configure(dev);
2494                 if (err)
2495                         goto error;
2496         }
2497
2498         /* Restore vf rate limit */
2499         if (vfinfo != NULL) {
2500                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2501                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2502                                 if (vfinfo[vf].tx_rate[idx] != 0)
2503                                         rte_pmd_ixgbe_set_vf_rate_limit(
2504                                                 dev->data->port_id, vf,
2505                                                 vfinfo[vf].tx_rate[idx],
2506                                                 1 << idx);
2507         }
2508
2509         ixgbe_restore_statistics_mapping(dev);
2510
2511         err = ixgbe_dev_rxtx_start(dev);
2512         if (err < 0) {
2513                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2514                 goto error;
2515         }
2516
2517         /* Skip link setup if loopback mode is enabled for 82599. */
2518         if (hw->mac.type == ixgbe_mac_82599EB &&
2519                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2520                 goto skip_link_setup;
2521
2522         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2523                 err = hw->mac.ops.setup_sfp(hw);
2524                 if (err)
2525                         goto error;
2526         }
2527
2528         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2529                 /* Turn on the copper */
2530                 ixgbe_set_phy_power(hw, true);
2531         } else {
2532                 /* Turn on the laser */
2533                 ixgbe_enable_tx_laser(hw);
2534         }
2535
2536         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2537         if (err)
2538                 goto error;
2539         dev->data->dev_link.link_status = link_up;
2540
2541         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2542         if (err)
2543                 goto error;
2544
2545         link_speeds = &dev->data->dev_conf.link_speeds;
2546         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2547                         ETH_LINK_SPEED_10G)) {
2548                 PMD_INIT_LOG(ERR, "Invalid link setting");
2549                 goto error;
2550         }
2551
2552         speed = 0x0;
2553         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2554                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2555                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2556                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2557         } else {
2558                 if (*link_speeds & ETH_LINK_SPEED_10G)
2559                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2560                 if (*link_speeds & ETH_LINK_SPEED_1G)
2561                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2562                 if (*link_speeds & ETH_LINK_SPEED_100M)
2563                         speed |= IXGBE_LINK_SPEED_100_FULL;
2564         }
2565
2566         err = ixgbe_setup_link(hw, speed, link_up);
2567         if (err)
2568                 goto error;
2569
2570 skip_link_setup:
2571
2572         if (rte_intr_allow_others(intr_handle)) {
2573                 /* check if lsc interrupt is enabled */
2574                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2575                         ixgbe_dev_lsc_interrupt_setup(dev);
2576                 ixgbe_dev_macsec_interrupt_setup(dev);
2577         } else {
2578                 rte_intr_callback_unregister(intr_handle,
2579                                              ixgbe_dev_interrupt_handler, dev);
2580                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2581                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2582                                      " no intr multiplex\n");
2583         }
2584
2585         /* check if rxq interrupt is enabled */
2586         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2587             rte_intr_dp_is_en(intr_handle))
2588                 ixgbe_dev_rxq_interrupt_setup(dev);
2589
2590         /* enable uio/vfio intr/eventfd mapping */
2591         rte_intr_enable(intr_handle);
2592
2593         /* resume enabled intr since hw reset */
2594         ixgbe_enable_intr(dev);
2595         ixgbe_l2_tunnel_conf(dev);
2596         ixgbe_filter_restore(dev);
2597
2598         return 0;
2599
2600 error:
2601         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2602         ixgbe_dev_clear_queues(dev);
2603         return -EIO;
2604 }
2605
2606 /*
2607  * Stop device: disable rx and tx functions to allow for reconfiguring.
2608  */
2609 static void
2610 ixgbe_dev_stop(struct rte_eth_dev *dev)
2611 {
2612         struct rte_eth_link link;
2613         struct ixgbe_hw *hw =
2614                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615         struct ixgbe_vf_info *vfinfo =
2616                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2617         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2618         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2619         int vf;
2620
2621         PMD_INIT_FUNC_TRACE();
2622
2623         /* disable interrupts */
2624         ixgbe_disable_intr(hw);
2625
2626         /* reset the NIC */
2627         ixgbe_pf_reset_hw(hw);
2628         hw->adapter_stopped = 0;
2629
2630         /* stop adapter */
2631         ixgbe_stop_adapter(hw);
2632
2633         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2634                 vfinfo[vf].clear_to_send = false;
2635
2636         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2637                 /* Turn off the copper */
2638                 ixgbe_set_phy_power(hw, false);
2639         } else {
2640                 /* Turn off the laser */
2641                 ixgbe_disable_tx_laser(hw);
2642         }
2643
2644         ixgbe_dev_clear_queues(dev);
2645
2646         /* Clear stored conf */
2647         dev->data->scattered_rx = 0;
2648         dev->data->lro = 0;
2649
2650         /* Clear recorded link status */
2651         memset(&link, 0, sizeof(link));
2652         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2653
2654         if (!rte_intr_allow_others(intr_handle))
2655                 /* resume to the default handler */
2656                 rte_intr_callback_register(intr_handle,
2657                                            ixgbe_dev_interrupt_handler,
2658                                            (void *)dev);
2659
2660         /* Clean datapath event and queue/vec mapping */
2661         rte_intr_efd_disable(intr_handle);
2662         if (intr_handle->intr_vec != NULL) {
2663                 rte_free(intr_handle->intr_vec);
2664                 intr_handle->intr_vec = NULL;
2665         }
2666 }
2667
2668 /*
2669  * Set device link up: enable tx.
2670  */
2671 static int
2672 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2673 {
2674         struct ixgbe_hw *hw =
2675                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2676         if (hw->mac.type == ixgbe_mac_82599EB) {
2677 #ifdef RTE_NIC_BYPASS
2678                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2679                         /* Not suported in bypass mode */
2680                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2681                                      "by device id 0x%x", hw->device_id);
2682                         return -ENOTSUP;
2683                 }
2684 #endif
2685         }
2686
2687         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2688                 /* Turn on the copper */
2689                 ixgbe_set_phy_power(hw, true);
2690         } else {
2691                 /* Turn on the laser */
2692                 ixgbe_enable_tx_laser(hw);
2693         }
2694
2695         return 0;
2696 }
2697
2698 /*
2699  * Set device link down: disable tx.
2700  */
2701 static int
2702 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2703 {
2704         struct ixgbe_hw *hw =
2705                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2706         if (hw->mac.type == ixgbe_mac_82599EB) {
2707 #ifdef RTE_NIC_BYPASS
2708                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2709                         /* Not suported in bypass mode */
2710                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2711                                      "by device id 0x%x", hw->device_id);
2712                         return -ENOTSUP;
2713                 }
2714 #endif
2715         }
2716
2717         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2718                 /* Turn off the copper */
2719                 ixgbe_set_phy_power(hw, false);
2720         } else {
2721                 /* Turn off the laser */
2722                 ixgbe_disable_tx_laser(hw);
2723         }
2724
2725         return 0;
2726 }
2727
2728 /*
2729  * Reest and stop device.
2730  */
2731 static void
2732 ixgbe_dev_close(struct rte_eth_dev *dev)
2733 {
2734         struct ixgbe_hw *hw =
2735                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2736
2737         PMD_INIT_FUNC_TRACE();
2738
2739         ixgbe_pf_reset_hw(hw);
2740
2741         ixgbe_dev_stop(dev);
2742         hw->adapter_stopped = 1;
2743
2744         ixgbe_dev_free_queues(dev);
2745
2746         ixgbe_disable_pcie_master(hw);
2747
2748         /* reprogram the RAR[0] in case user changed it. */
2749         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2750 }
2751
2752 static void
2753 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2754                            struct ixgbe_hw_stats *hw_stats,
2755                            struct ixgbe_macsec_stats *macsec_stats,
2756                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2757                            uint64_t *total_qprc, uint64_t *total_qprdc)
2758 {
2759         uint32_t bprc, lxon, lxoff, total;
2760         uint32_t delta_gprc = 0;
2761         unsigned i;
2762         /* Workaround for RX byte count not including CRC bytes when CRC
2763          * strip is enabled. CRC bytes are removed from counters when crc_strip
2764          * is disabled.
2765          */
2766         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2767                         IXGBE_HLREG0_RXCRCSTRP);
2768
2769         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2770         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2771         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2772         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2773
2774         for (i = 0; i < 8; i++) {
2775                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2776
2777                 /* global total per queue */
2778                 hw_stats->mpc[i] += mp;
2779                 /* Running comprehensive total for stats display */
2780                 *total_missed_rx += hw_stats->mpc[i];
2781                 if (hw->mac.type == ixgbe_mac_82598EB) {
2782                         hw_stats->rnbc[i] +=
2783                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2784                         hw_stats->pxonrxc[i] +=
2785                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2786                         hw_stats->pxoffrxc[i] +=
2787                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2788                 } else {
2789                         hw_stats->pxonrxc[i] +=
2790                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2791                         hw_stats->pxoffrxc[i] +=
2792                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2793                         hw_stats->pxon2offc[i] +=
2794                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2795                 }
2796                 hw_stats->pxontxc[i] +=
2797                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2798                 hw_stats->pxofftxc[i] +=
2799                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2800         }
2801         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2802                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2803                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2804                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2805
2806                 delta_gprc += delta_qprc;
2807
2808                 hw_stats->qprc[i] += delta_qprc;
2809                 hw_stats->qptc[i] += delta_qptc;
2810
2811                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2812                 hw_stats->qbrc[i] +=
2813                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2814                 if (crc_strip == 0)
2815                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2816
2817                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2818                 hw_stats->qbtc[i] +=
2819                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2820
2821                 hw_stats->qprdc[i] += delta_qprdc;
2822                 *total_qprdc += hw_stats->qprdc[i];
2823
2824                 *total_qprc += hw_stats->qprc[i];
2825                 *total_qbrc += hw_stats->qbrc[i];
2826         }
2827         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2828         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2829         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2830
2831         /*
2832          * An errata states that gprc actually counts good + missed packets:
2833          * Workaround to set gprc to summated queue packet receives
2834          */
2835         hw_stats->gprc = *total_qprc;
2836
2837         if (hw->mac.type != ixgbe_mac_82598EB) {
2838                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2839                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2840                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2841                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2842                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2843                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2844                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2845                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2846         } else {
2847                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2848                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2849                 /* 82598 only has a counter in the high register */
2850                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2851                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2852                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2853         }
2854         uint64_t old_tpr = hw_stats->tpr;
2855
2856         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2857         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2858
2859         if (crc_strip == 0)
2860                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2861
2862         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2863         hw_stats->gptc += delta_gptc;
2864         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2865         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2866
2867         /*
2868          * Workaround: mprc hardware is incorrectly counting
2869          * broadcasts, so for now we subtract those.
2870          */
2871         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2872         hw_stats->bprc += bprc;
2873         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2874         if (hw->mac.type == ixgbe_mac_82598EB)
2875                 hw_stats->mprc -= bprc;
2876
2877         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2878         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2879         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2880         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2881         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2882         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2883
2884         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2885         hw_stats->lxontxc += lxon;
2886         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2887         hw_stats->lxofftxc += lxoff;
2888         total = lxon + lxoff;
2889
2890         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2891         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2892         hw_stats->gptc -= total;
2893         hw_stats->mptc -= total;
2894         hw_stats->ptc64 -= total;
2895         hw_stats->gotc -= total * ETHER_MIN_LEN;
2896
2897         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2898         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2899         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2900         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2901         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2902         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2903         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2904         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2905         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2906         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2907         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2908         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2909         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2910         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2911         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2912         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2913         /* Only read FCOE on 82599 */
2914         if (hw->mac.type != ixgbe_mac_82598EB) {
2915                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2916                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2917                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2918                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2919                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2920         }
2921
2922         /* Flow Director Stats registers */
2923         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2924         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2925
2926         /* MACsec Stats registers */
2927         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2928         macsec_stats->out_pkts_encrypted +=
2929                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2930         macsec_stats->out_pkts_protected +=
2931                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2932         macsec_stats->out_octets_encrypted +=
2933                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2934         macsec_stats->out_octets_protected +=
2935                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2936         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2937         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2938         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2939         macsec_stats->in_pkts_unknownsci +=
2940                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2941         macsec_stats->in_octets_decrypted +=
2942                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2943         macsec_stats->in_octets_validated +=
2944                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2945         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2946         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2947         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2948         for (i = 0; i < 2; i++) {
2949                 macsec_stats->in_pkts_ok +=
2950                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2951                 macsec_stats->in_pkts_invalid +=
2952                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2953                 macsec_stats->in_pkts_notvalid +=
2954                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2955         }
2956         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2957         macsec_stats->in_pkts_notusingsa +=
2958                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2959 }
2960
2961 /*
2962  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2963  */
2964 static void
2965 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2966 {
2967         struct ixgbe_hw *hw =
2968                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969         struct ixgbe_hw_stats *hw_stats =
2970                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2971         struct ixgbe_macsec_stats *macsec_stats =
2972                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2973                                 dev->data->dev_private);
2974         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2975         unsigned i;
2976
2977         total_missed_rx = 0;
2978         total_qbrc = 0;
2979         total_qprc = 0;
2980         total_qprdc = 0;
2981
2982         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2983                         &total_qbrc, &total_qprc, &total_qprdc);
2984
2985         if (stats == NULL)
2986                 return;
2987
2988         /* Fill out the rte_eth_stats statistics structure */
2989         stats->ipackets = total_qprc;
2990         stats->ibytes = total_qbrc;
2991         stats->opackets = hw_stats->gptc;
2992         stats->obytes = hw_stats->gotc;
2993
2994         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2995                 stats->q_ipackets[i] = hw_stats->qprc[i];
2996                 stats->q_opackets[i] = hw_stats->qptc[i];
2997                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2998                 stats->q_obytes[i] = hw_stats->qbtc[i];
2999                 stats->q_errors[i] = hw_stats->qprdc[i];
3000         }
3001
3002         /* Rx Errors */
3003         stats->imissed  = total_missed_rx;
3004         stats->ierrors  = hw_stats->crcerrs +
3005                           hw_stats->mspdc +
3006                           hw_stats->rlec +
3007                           hw_stats->ruc +
3008                           hw_stats->roc +
3009                           hw_stats->illerrc +
3010                           hw_stats->errbc +
3011                           hw_stats->rfc +
3012                           hw_stats->fccrc +
3013                           hw_stats->fclast;
3014
3015         /* Tx Errors */
3016         stats->oerrors  = 0;
3017 }
3018
3019 static void
3020 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3021 {
3022         struct ixgbe_hw_stats *stats =
3023                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3024
3025         /* HW registers are cleared on read */
3026         ixgbe_dev_stats_get(dev, NULL);
3027
3028         /* Reset software totals */
3029         memset(stats, 0, sizeof(*stats));
3030 }
3031
3032 /* This function calculates the number of xstats based on the current config */
3033 static unsigned
3034 ixgbe_xstats_calc_num(void) {
3035         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3036                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3037                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3038 }
3039
3040 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3041         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3042 {
3043         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3044         unsigned stat, i, count;
3045
3046         if (xstats_names != NULL) {
3047                 count = 0;
3048
3049                 /* Note: limit >= cnt_stats checked upstream
3050                  * in rte_eth_xstats_names()
3051                  */
3052
3053                 /* Extended stats from ixgbe_hw_stats */
3054                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3055                         snprintf(xstats_names[count].name,
3056                                 sizeof(xstats_names[count].name),
3057                                 "%s",
3058                                 rte_ixgbe_stats_strings[i].name);
3059                         count++;
3060                 }
3061
3062                 /* MACsec Stats */
3063                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3064                         snprintf(xstats_names[count].name,
3065                                 sizeof(xstats_names[count].name),
3066                                 "%s",
3067                                 rte_ixgbe_macsec_strings[i].name);
3068                         count++;
3069                 }
3070
3071                 /* RX Priority Stats */
3072                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3073                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3074                                 snprintf(xstats_names[count].name,
3075                                         sizeof(xstats_names[count].name),
3076                                         "rx_priority%u_%s", i,
3077                                         rte_ixgbe_rxq_strings[stat].name);
3078                                 count++;
3079                         }
3080                 }
3081
3082                 /* TX Priority Stats */
3083                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3084                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3085                                 snprintf(xstats_names[count].name,
3086                                         sizeof(xstats_names[count].name),
3087                                         "tx_priority%u_%s", i,
3088                                         rte_ixgbe_txq_strings[stat].name);
3089                                 count++;
3090                         }
3091                 }
3092         }
3093         return cnt_stats;
3094 }
3095
3096 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3097         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3098 {
3099         unsigned i;
3100
3101         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3102                 return -ENOMEM;
3103
3104         if (xstats_names != NULL)
3105                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3106                         snprintf(xstats_names[i].name,
3107                                 sizeof(xstats_names[i].name),
3108                                 "%s", rte_ixgbevf_stats_strings[i].name);
3109         return IXGBEVF_NB_XSTATS;
3110 }
3111
3112 static int
3113 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3114                                          unsigned n)
3115 {
3116         struct ixgbe_hw *hw =
3117                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3118         struct ixgbe_hw_stats *hw_stats =
3119                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3120         struct ixgbe_macsec_stats *macsec_stats =
3121                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3122                                 dev->data->dev_private);
3123         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3124         unsigned i, stat, count = 0;
3125
3126         count = ixgbe_xstats_calc_num();
3127
3128         if (n < count)
3129                 return count;
3130
3131         total_missed_rx = 0;
3132         total_qbrc = 0;
3133         total_qprc = 0;
3134         total_qprdc = 0;
3135
3136         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3137                         &total_qbrc, &total_qprc, &total_qprdc);
3138
3139         /* If this is a reset xstats is NULL, and we have cleared the
3140          * registers by reading them.
3141          */
3142         if (!xstats)
3143                 return 0;
3144
3145         /* Extended stats from ixgbe_hw_stats */
3146         count = 0;
3147         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3148                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3149                                 rte_ixgbe_stats_strings[i].offset);
3150                 xstats[count].id = count;
3151                 count++;
3152         }
3153
3154         /* MACsec Stats */
3155         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3156                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3157                                 rte_ixgbe_macsec_strings[i].offset);
3158                 xstats[count].id = count;
3159                 count++;
3160         }
3161
3162         /* RX Priority Stats */
3163         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3164                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3165                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3166                                         rte_ixgbe_rxq_strings[stat].offset +
3167                                         (sizeof(uint64_t) * i));
3168                         xstats[count].id = count;
3169                         count++;
3170                 }
3171         }
3172
3173         /* TX Priority Stats */
3174         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3175                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3176                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3177                                         rte_ixgbe_txq_strings[stat].offset +
3178                                         (sizeof(uint64_t) * i));
3179                         xstats[count].id = count;
3180                         count++;
3181                 }
3182         }
3183         return count;
3184 }
3185
3186 static void
3187 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3188 {
3189         struct ixgbe_hw_stats *stats =
3190                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3191         struct ixgbe_macsec_stats *macsec_stats =
3192                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3193                                 dev->data->dev_private);
3194
3195         unsigned count = ixgbe_xstats_calc_num();
3196
3197         /* HW registers are cleared on read */
3198         ixgbe_dev_xstats_get(dev, NULL, count);
3199
3200         /* Reset software totals */
3201         memset(stats, 0, sizeof(*stats));
3202         memset(macsec_stats, 0, sizeof(*macsec_stats));
3203 }
3204
3205 static void
3206 ixgbevf_update_stats(struct rte_eth_dev *dev)
3207 {
3208         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3209         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3210                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3211
3212         /* Good Rx packet, include VF loopback */
3213         UPDATE_VF_STAT(IXGBE_VFGPRC,
3214             hw_stats->last_vfgprc, hw_stats->vfgprc);
3215
3216         /* Good Rx octets, include VF loopback */
3217         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3218             hw_stats->last_vfgorc, hw_stats->vfgorc);
3219
3220         /* Good Tx packet, include VF loopback */
3221         UPDATE_VF_STAT(IXGBE_VFGPTC,
3222             hw_stats->last_vfgptc, hw_stats->vfgptc);
3223
3224         /* Good Tx octets, include VF loopback */
3225         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3226             hw_stats->last_vfgotc, hw_stats->vfgotc);
3227
3228         /* Rx Multicst Packet */
3229         UPDATE_VF_STAT(IXGBE_VFMPRC,
3230             hw_stats->last_vfmprc, hw_stats->vfmprc);
3231 }
3232
3233 static int
3234 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3235                        unsigned n)
3236 {
3237         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3238                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3239         unsigned i;
3240
3241         if (n < IXGBEVF_NB_XSTATS)
3242                 return IXGBEVF_NB_XSTATS;
3243
3244         ixgbevf_update_stats(dev);
3245
3246         if (!xstats)
3247                 return 0;
3248
3249         /* Extended stats */
3250         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3251                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3252                         rte_ixgbevf_stats_strings[i].offset);
3253         }
3254
3255         return IXGBEVF_NB_XSTATS;
3256 }
3257
3258 static void
3259 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3260 {
3261         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3262                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3263
3264         ixgbevf_update_stats(dev);
3265
3266         if (stats == NULL)
3267                 return;
3268
3269         stats->ipackets = hw_stats->vfgprc;
3270         stats->ibytes = hw_stats->vfgorc;
3271         stats->opackets = hw_stats->vfgptc;
3272         stats->obytes = hw_stats->vfgotc;
3273 }
3274
3275 static void
3276 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3277 {
3278         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3279                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3280
3281         /* Sync HW register to the last stats */
3282         ixgbevf_dev_stats_get(dev, NULL);
3283
3284         /* reset HW current stats*/
3285         hw_stats->vfgprc = 0;
3286         hw_stats->vfgorc = 0;
3287         hw_stats->vfgptc = 0;
3288         hw_stats->vfgotc = 0;
3289 }
3290
3291 static int
3292 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3293 {
3294         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3295         u16 eeprom_verh, eeprom_verl;
3296         u32 etrack_id;
3297         int ret;
3298
3299         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3300         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3301
3302         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3303         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3304
3305         ret += 1; /* add the size of '\0' */
3306         if (fw_size < (u32)ret)
3307                 return ret;
3308         else
3309                 return 0;
3310 }
3311
3312 static void
3313 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3314 {
3315         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3316         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3317         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3318
3319         dev_info->pci_dev = pci_dev;
3320         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3321         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3322         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3323                 /*
3324                  * When DCB/VT is off, maximum number of queues changes,
3325                  * except for 82598EB, which remains constant.
3326                  */
3327                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3328                                 hw->mac.type != ixgbe_mac_82598EB)
3329                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3330         }
3331         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3332         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3333         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3334         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3335         dev_info->max_vfs = pci_dev->max_vfs;
3336         if (hw->mac.type == ixgbe_mac_82598EB)
3337                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3338         else
3339                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3340         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3341         dev_info->rx_offload_capa =
3342                 DEV_RX_OFFLOAD_VLAN_STRIP |
3343                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3344                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3345                 DEV_RX_OFFLOAD_TCP_CKSUM;
3346
3347         /*
3348          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3349          * mode.
3350          */
3351         if ((hw->mac.type == ixgbe_mac_82599EB ||
3352              hw->mac.type == ixgbe_mac_X540) &&
3353             !RTE_ETH_DEV_SRIOV(dev).active)
3354                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3355
3356         if (hw->mac.type == ixgbe_mac_82599EB ||
3357             hw->mac.type == ixgbe_mac_X540)
3358                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3359
3360         if (hw->mac.type == ixgbe_mac_X550 ||
3361             hw->mac.type == ixgbe_mac_X550EM_x ||
3362             hw->mac.type == ixgbe_mac_X550EM_a)
3363                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3364
3365         dev_info->tx_offload_capa =
3366                 DEV_TX_OFFLOAD_VLAN_INSERT |
3367                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3368                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3369                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3370                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3371                 DEV_TX_OFFLOAD_TCP_TSO;
3372
3373         if (hw->mac.type == ixgbe_mac_82599EB ||
3374             hw->mac.type == ixgbe_mac_X540)
3375                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3376
3377         if (hw->mac.type == ixgbe_mac_X550 ||
3378             hw->mac.type == ixgbe_mac_X550EM_x ||
3379             hw->mac.type == ixgbe_mac_X550EM_a)
3380                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3381
3382         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3383                 .rx_thresh = {
3384                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3385                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3386                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3387                 },
3388                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3389                 .rx_drop_en = 0,
3390         };
3391
3392         dev_info->default_txconf = (struct rte_eth_txconf) {
3393                 .tx_thresh = {
3394                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3395                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3396                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3397                 },
3398                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3399                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3400                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3401                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3402         };
3403
3404         dev_info->rx_desc_lim = rx_desc_lim;
3405         dev_info->tx_desc_lim = tx_desc_lim;
3406
3407         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3408         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3409         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3410
3411         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3412         if (hw->mac.type == ixgbe_mac_X540 ||
3413             hw->mac.type == ixgbe_mac_X540_vf ||
3414             hw->mac.type == ixgbe_mac_X550 ||
3415             hw->mac.type == ixgbe_mac_X550_vf) {
3416                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3417         }
3418 }
3419
3420 static const uint32_t *
3421 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3422 {
3423         static const uint32_t ptypes[] = {
3424                 /* For non-vec functions,
3425                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3426                  * for vec functions,
3427                  * refers to _recv_raw_pkts_vec().
3428                  */
3429                 RTE_PTYPE_L2_ETHER,
3430                 RTE_PTYPE_L3_IPV4,
3431                 RTE_PTYPE_L3_IPV4_EXT,
3432                 RTE_PTYPE_L3_IPV6,
3433                 RTE_PTYPE_L3_IPV6_EXT,
3434                 RTE_PTYPE_L4_SCTP,
3435                 RTE_PTYPE_L4_TCP,
3436                 RTE_PTYPE_L4_UDP,
3437                 RTE_PTYPE_TUNNEL_IP,
3438                 RTE_PTYPE_INNER_L3_IPV6,
3439                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3440                 RTE_PTYPE_INNER_L4_TCP,
3441                 RTE_PTYPE_INNER_L4_UDP,
3442                 RTE_PTYPE_UNKNOWN
3443         };
3444
3445         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3446             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3447             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3448             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3449                 return ptypes;
3450         return NULL;
3451 }
3452
3453 static void
3454 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3455                      struct rte_eth_dev_info *dev_info)
3456 {
3457         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3458         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3459
3460         dev_info->pci_dev = pci_dev;
3461         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3462         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3463         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3464         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3465         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3466         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3467         dev_info->max_vfs = pci_dev->max_vfs;
3468         if (hw->mac.type == ixgbe_mac_82598EB)
3469                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3470         else
3471                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3472         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3473                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3474                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3475                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3476         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3477                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3478                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3479                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3480                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3481                                 DEV_TX_OFFLOAD_TCP_TSO;
3482
3483         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3484                 .rx_thresh = {
3485                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3486                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3487                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3488                 },
3489                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3490                 .rx_drop_en = 0,
3491         };
3492
3493         dev_info->default_txconf = (struct rte_eth_txconf) {
3494                 .tx_thresh = {
3495                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3496                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3497                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3498                 },
3499                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3500                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3501                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3502                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3503         };
3504
3505         dev_info->rx_desc_lim = rx_desc_lim;
3506         dev_info->tx_desc_lim = tx_desc_lim;
3507 }
3508
3509 /* return 0 means link status changed, -1 means not changed */
3510 static int
3511 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3512 {
3513         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3514         struct rte_eth_link link, old;
3515         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3516         int link_up;
3517         int diag;
3518
3519         link.link_status = ETH_LINK_DOWN;
3520         link.link_speed = 0;
3521         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3522         memset(&old, 0, sizeof(old));
3523         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3524
3525         hw->mac.get_link_status = true;
3526
3527         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3528         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3529                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3530         else
3531                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3532
3533         if (diag != 0) {
3534                 link.link_speed = ETH_SPEED_NUM_100M;
3535                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3536                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3537                 if (link.link_status == old.link_status)
3538                         return -1;
3539                 return 0;
3540         }
3541
3542         if (link_up == 0) {
3543                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3544                 if (link.link_status == old.link_status)
3545                         return -1;
3546                 return 0;
3547         }
3548         link.link_status = ETH_LINK_UP;
3549         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3550
3551         switch (link_speed) {
3552         default:
3553         case IXGBE_LINK_SPEED_UNKNOWN:
3554                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3555                 link.link_speed = ETH_SPEED_NUM_100M;
3556                 break;
3557
3558         case IXGBE_LINK_SPEED_100_FULL:
3559                 link.link_speed = ETH_SPEED_NUM_100M;
3560                 break;
3561
3562         case IXGBE_LINK_SPEED_1GB_FULL:
3563                 link.link_speed = ETH_SPEED_NUM_1G;
3564                 break;
3565
3566         case IXGBE_LINK_SPEED_10GB_FULL:
3567                 link.link_speed = ETH_SPEED_NUM_10G;
3568                 break;
3569         }
3570         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3571
3572         if (link.link_status == old.link_status)
3573                 return -1;
3574
3575         return 0;
3576 }
3577
3578 static void
3579 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3580 {
3581         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3582         uint32_t fctrl;
3583
3584         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3585         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3586         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3587 }
3588
3589 static void
3590 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3591 {
3592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3593         uint32_t fctrl;
3594
3595         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3596         fctrl &= (~IXGBE_FCTRL_UPE);
3597         if (dev->data->all_multicast == 1)
3598                 fctrl |= IXGBE_FCTRL_MPE;
3599         else
3600                 fctrl &= (~IXGBE_FCTRL_MPE);
3601         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3602 }
3603
3604 static void
3605 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3606 {
3607         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608         uint32_t fctrl;
3609
3610         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3611         fctrl |= IXGBE_FCTRL_MPE;
3612         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3613 }
3614
3615 static void
3616 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3617 {
3618         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619         uint32_t fctrl;
3620
3621         if (dev->data->promiscuous == 1)
3622                 return; /* must remain in all_multicast mode */
3623
3624         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3625         fctrl &= (~IXGBE_FCTRL_MPE);
3626         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3627 }
3628
3629 /**
3630  * It clears the interrupt causes and enables the interrupt.
3631  * It will be called once only during nic initialized.
3632  *
3633  * @param dev
3634  *  Pointer to struct rte_eth_dev.
3635  *
3636  * @return
3637  *  - On success, zero.
3638  *  - On failure, a negative value.
3639  */
3640 static int
3641 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3642 {
3643         struct ixgbe_interrupt *intr =
3644                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3645
3646         ixgbe_dev_link_status_print(dev);
3647         intr->mask |= IXGBE_EICR_LSC;
3648
3649         return 0;
3650 }
3651
3652 /**
3653  * It clears the interrupt causes and enables the interrupt.
3654  * It will be called once only during nic initialized.
3655  *
3656  * @param dev
3657  *  Pointer to struct rte_eth_dev.
3658  *
3659  * @return
3660  *  - On success, zero.
3661  *  - On failure, a negative value.
3662  */
3663 static int
3664 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3665 {
3666         struct ixgbe_interrupt *intr =
3667                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3668
3669         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3670
3671         return 0;
3672 }
3673
3674 /**
3675  * It clears the interrupt causes and enables the interrupt.
3676  * It will be called once only during nic initialized.
3677  *
3678  * @param dev
3679  *  Pointer to struct rte_eth_dev.
3680  *
3681  * @return
3682  *  - On success, zero.
3683  *  - On failure, a negative value.
3684  */
3685 static int
3686 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3687 {
3688         struct ixgbe_interrupt *intr =
3689                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3690
3691         intr->mask |= IXGBE_EICR_LINKSEC;
3692
3693         return 0;
3694 }
3695
3696 /*
3697  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3698  *
3699  * @param dev
3700  *  Pointer to struct rte_eth_dev.
3701  *
3702  * @return
3703  *  - On success, zero.
3704  *  - On failure, a negative value.
3705  */
3706 static int
3707 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3708 {
3709         uint32_t eicr;
3710         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3711         struct ixgbe_interrupt *intr =
3712                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3713
3714         /* clear all cause mask */
3715         ixgbe_disable_intr(hw);
3716
3717         /* read-on-clear nic registers here */
3718         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3719         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3720
3721         intr->flags = 0;
3722
3723         /* set flag for async link update */
3724         if (eicr & IXGBE_EICR_LSC)
3725                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3726
3727         if (eicr & IXGBE_EICR_MAILBOX)
3728                 intr->flags |= IXGBE_FLAG_MAILBOX;
3729
3730         if (eicr & IXGBE_EICR_LINKSEC)
3731                 intr->flags |= IXGBE_FLAG_MACSEC;
3732
3733         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3734             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3735             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3736                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3737
3738         return 0;
3739 }
3740
3741 /**
3742  * It gets and then prints the link status.
3743  *
3744  * @param dev
3745  *  Pointer to struct rte_eth_dev.
3746  *
3747  * @return
3748  *  - On success, zero.
3749  *  - On failure, a negative value.
3750  */
3751 static void
3752 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3753 {
3754         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3755         struct rte_eth_link link;
3756
3757         memset(&link, 0, sizeof(link));
3758         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3759         if (link.link_status) {
3760                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3761                                         (int)(dev->data->port_id),
3762                                         (unsigned)link.link_speed,
3763                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3764                                         "full-duplex" : "half-duplex");
3765         } else {
3766                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3767                                 (int)(dev->data->port_id));
3768         }
3769         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3770                                 pci_dev->addr.domain,
3771                                 pci_dev->addr.bus,
3772                                 pci_dev->addr.devid,
3773                                 pci_dev->addr.function);
3774 }
3775
3776 /*
3777  * It executes link_update after knowing an interrupt occurred.
3778  *
3779  * @param dev
3780  *  Pointer to struct rte_eth_dev.
3781  *
3782  * @return
3783  *  - On success, zero.
3784  *  - On failure, a negative value.
3785  */
3786 static int
3787 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3788                            struct rte_intr_handle *intr_handle)
3789 {
3790         struct ixgbe_interrupt *intr =
3791                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3792         int64_t timeout;
3793         struct rte_eth_link link;
3794         struct ixgbe_hw *hw =
3795                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796
3797         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3798
3799         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3800                 ixgbe_pf_mbx_process(dev);
3801                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3802         }
3803
3804         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3805                 ixgbe_handle_lasi(hw);
3806                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3807         }
3808
3809         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3810                 /* get the link status before link update, for predicting later */
3811                 memset(&link, 0, sizeof(link));
3812                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3813
3814                 ixgbe_dev_link_update(dev, 0);
3815
3816                 /* likely to up */
3817                 if (!link.link_status)
3818                         /* handle it 1 sec later, wait it being stable */
3819                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3820                 /* likely to down */
3821                 else
3822                         /* handle it 4 sec later, wait it being stable */
3823                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3824
3825                 ixgbe_dev_link_status_print(dev);
3826                 intr->mask_original = intr->mask;
3827                 /* only disable lsc interrupt */
3828                 intr->mask &= ~IXGBE_EIMS_LSC;
3829                 if (rte_eal_alarm_set(timeout * 1000,
3830                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3831                         PMD_DRV_LOG(ERR, "Error setting alarm");
3832                 else
3833                         intr->mask = intr->mask_original;
3834         }
3835
3836         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3837         ixgbe_enable_intr(dev);
3838         rte_intr_enable(intr_handle);
3839
3840         return 0;
3841 }
3842
3843 /**
3844  * Interrupt handler which shall be registered for alarm callback for delayed
3845  * handling specific interrupt to wait for the stable nic state. As the
3846  * NIC interrupt state is not stable for ixgbe after link is just down,
3847  * it needs to wait 4 seconds to get the stable status.
3848  *
3849  * @param handle
3850  *  Pointer to interrupt handle.
3851  * @param param
3852  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3853  *
3854  * @return
3855  *  void
3856  */
3857 static void
3858 ixgbe_dev_interrupt_delayed_handler(void *param)
3859 {
3860         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3861         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3862         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3863         struct ixgbe_interrupt *intr =
3864                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3865         struct ixgbe_hw *hw =
3866                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3867         uint32_t eicr;
3868
3869         ixgbe_disable_intr(hw);
3870
3871         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3872         if (eicr & IXGBE_EICR_MAILBOX)
3873                 ixgbe_pf_mbx_process(dev);
3874
3875         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3876                 ixgbe_handle_lasi(hw);
3877                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3878         }
3879
3880         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3881                 ixgbe_dev_link_update(dev, 0);
3882                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3883                 ixgbe_dev_link_status_print(dev);
3884                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3885         }
3886
3887         if (intr->flags & IXGBE_FLAG_MACSEC) {
3888                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3889                                               NULL);
3890                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3891         }
3892
3893         /* restore original mask */
3894         intr->mask = intr->mask_original;
3895         intr->mask_original = 0;
3896
3897         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3898         ixgbe_enable_intr(dev);
3899         rte_intr_enable(intr_handle);
3900 }
3901
3902 /**
3903  * Interrupt handler triggered by NIC  for handling
3904  * specific interrupt.
3905  *
3906  * @param handle
3907  *  Pointer to interrupt handle.
3908  * @param param
3909  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3910  *
3911  * @return
3912  *  void
3913  */
3914 static void
3915 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3916                             void *param)
3917 {
3918         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3919
3920         ixgbe_dev_interrupt_get_status(dev);
3921         ixgbe_dev_interrupt_action(dev, handle);
3922 }
3923
3924 static int
3925 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3926 {
3927         struct ixgbe_hw *hw;
3928
3929         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3930         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3931 }
3932
3933 static int
3934 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3935 {
3936         struct ixgbe_hw *hw;
3937
3938         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3939         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3940 }
3941
3942 static int
3943 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3944 {
3945         struct ixgbe_hw *hw;
3946         uint32_t mflcn_reg;
3947         uint32_t fccfg_reg;
3948         int rx_pause;
3949         int tx_pause;
3950
3951         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3952
3953         fc_conf->pause_time = hw->fc.pause_time;
3954         fc_conf->high_water = hw->fc.high_water[0];
3955         fc_conf->low_water = hw->fc.low_water[0];
3956         fc_conf->send_xon = hw->fc.send_xon;
3957         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3958
3959         /*
3960          * Return rx_pause status according to actual setting of
3961          * MFLCN register.
3962          */
3963         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3964         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3965                 rx_pause = 1;
3966         else
3967                 rx_pause = 0;
3968
3969         /*
3970          * Return tx_pause status according to actual setting of
3971          * FCCFG register.
3972          */
3973         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3974         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3975                 tx_pause = 1;
3976         else
3977                 tx_pause = 0;
3978
3979         if (rx_pause && tx_pause)
3980                 fc_conf->mode = RTE_FC_FULL;
3981         else if (rx_pause)
3982                 fc_conf->mode = RTE_FC_RX_PAUSE;
3983         else if (tx_pause)
3984                 fc_conf->mode = RTE_FC_TX_PAUSE;
3985         else
3986                 fc_conf->mode = RTE_FC_NONE;
3987
3988         return 0;
3989 }
3990
3991 static int
3992 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3993 {
3994         struct ixgbe_hw *hw;
3995         int err;
3996         uint32_t rx_buf_size;
3997         uint32_t max_high_water;
3998         uint32_t mflcn;
3999         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4000                 ixgbe_fc_none,
4001                 ixgbe_fc_rx_pause,
4002                 ixgbe_fc_tx_pause,
4003                 ixgbe_fc_full
4004         };
4005
4006         PMD_INIT_FUNC_TRACE();
4007
4008         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4009         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4010         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4011
4012         /*
4013          * At least reserve one Ethernet frame for watermark
4014          * high_water/low_water in kilo bytes for ixgbe
4015          */
4016         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4017         if ((fc_conf->high_water > max_high_water) ||
4018                 (fc_conf->high_water < fc_conf->low_water)) {
4019                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4020                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4021                 return -EINVAL;
4022         }
4023
4024         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4025         hw->fc.pause_time     = fc_conf->pause_time;
4026         hw->fc.high_water[0]  = fc_conf->high_water;
4027         hw->fc.low_water[0]   = fc_conf->low_water;
4028         hw->fc.send_xon       = fc_conf->send_xon;
4029         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4030
4031         err = ixgbe_fc_enable(hw);
4032
4033         /* Not negotiated is not an error case */
4034         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4035
4036                 /* check if we want to forward MAC frames - driver doesn't have native
4037                  * capability to do that, so we'll write the registers ourselves */
4038
4039                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4040
4041                 /* set or clear MFLCN.PMCF bit depending on configuration */
4042                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4043                         mflcn |= IXGBE_MFLCN_PMCF;
4044                 else
4045                         mflcn &= ~IXGBE_MFLCN_PMCF;
4046
4047                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4048                 IXGBE_WRITE_FLUSH(hw);
4049
4050                 return 0;
4051         }
4052
4053         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4054         return -EIO;
4055 }
4056
4057 /**
4058  *  ixgbe_pfc_enable_generic - Enable flow control
4059  *  @hw: pointer to hardware structure
4060  *  @tc_num: traffic class number
4061  *  Enable flow control according to the current settings.
4062  */
4063 static int
4064 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4065 {
4066         int ret_val = 0;
4067         uint32_t mflcn_reg, fccfg_reg;
4068         uint32_t reg;
4069         uint32_t fcrtl, fcrth;
4070         uint8_t i;
4071         uint8_t nb_rx_en;
4072
4073         /* Validate the water mark configuration */
4074         if (!hw->fc.pause_time) {
4075                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4076                 goto out;
4077         }
4078
4079         /* Low water mark of zero causes XOFF floods */
4080         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4081                  /* High/Low water can not be 0 */
4082                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4083                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4084                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4085                         goto out;
4086                 }
4087
4088                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4089                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4090                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4091                         goto out;
4092                 }
4093         }
4094         /* Negotiate the fc mode to use */
4095         ixgbe_fc_autoneg(hw);
4096
4097         /* Disable any previous flow control settings */
4098         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4099         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4100
4101         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4102         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4103
4104         switch (hw->fc.current_mode) {
4105         case ixgbe_fc_none:
4106                 /*
4107                  * If the count of enabled RX Priority Flow control >1,
4108                  * and the TX pause can not be disabled
4109                  */
4110                 nb_rx_en = 0;
4111                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4112                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4113                         if (reg & IXGBE_FCRTH_FCEN)
4114                                 nb_rx_en++;
4115                 }
4116                 if (nb_rx_en > 1)
4117                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4118                 break;
4119         case ixgbe_fc_rx_pause:
4120                 /*
4121                  * Rx Flow control is enabled and Tx Flow control is
4122                  * disabled by software override. Since there really
4123                  * isn't a way to advertise that we are capable of RX
4124                  * Pause ONLY, we will advertise that we support both
4125                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4126                  * disable the adapter's ability to send PAUSE frames.
4127                  */
4128                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4129                 /*
4130                  * If the count of enabled RX Priority Flow control >1,
4131                  * and the TX pause can not be disabled
4132                  */
4133                 nb_rx_en = 0;
4134                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4135                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4136                         if (reg & IXGBE_FCRTH_FCEN)
4137                                 nb_rx_en++;
4138                 }
4139                 if (nb_rx_en > 1)
4140                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4141                 break;
4142         case ixgbe_fc_tx_pause:
4143                 /*
4144                  * Tx Flow control is enabled, and Rx Flow control is
4145                  * disabled by software override.
4146                  */
4147                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4148                 break;
4149         case ixgbe_fc_full:
4150                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4151                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4152                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4153                 break;
4154         default:
4155                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4156                 ret_val = IXGBE_ERR_CONFIG;
4157                 goto out;
4158         }
4159
4160         /* Set 802.3x based flow control settings. */
4161         mflcn_reg |= IXGBE_MFLCN_DPF;
4162         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4163         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4164
4165         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4166         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4167                 hw->fc.high_water[tc_num]) {
4168                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4169                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4170                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4171         } else {
4172                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4173                 /*
4174                  * In order to prevent Tx hangs when the internal Tx
4175                  * switch is enabled we must set the high water mark
4176                  * to the maximum FCRTH value.  This allows the Tx
4177                  * switch to function even under heavy Rx workloads.
4178                  */
4179                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4180         }
4181         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4182
4183         /* Configure pause time (2 TCs per register) */
4184         reg = hw->fc.pause_time * 0x00010001;
4185         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4186                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4187
4188         /* Configure flow control refresh threshold value */
4189         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4190
4191 out:
4192         return ret_val;
4193 }
4194
4195 static int
4196 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4197 {
4198         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4200
4201         if (hw->mac.type != ixgbe_mac_82598EB) {
4202                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4203         }
4204         return ret_val;
4205 }
4206
4207 static int
4208 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4209 {
4210         int err;
4211         uint32_t rx_buf_size;
4212         uint32_t max_high_water;
4213         uint8_t tc_num;
4214         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4215         struct ixgbe_hw *hw =
4216                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4217         struct ixgbe_dcb_config *dcb_config =
4218                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4219
4220         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4221                 ixgbe_fc_none,
4222                 ixgbe_fc_rx_pause,
4223                 ixgbe_fc_tx_pause,
4224                 ixgbe_fc_full
4225         };
4226
4227         PMD_INIT_FUNC_TRACE();
4228
4229         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4230         tc_num = map[pfc_conf->priority];
4231         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4232         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4233         /*
4234          * At least reserve one Ethernet frame for watermark
4235          * high_water/low_water in kilo bytes for ixgbe
4236          */
4237         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4238         if ((pfc_conf->fc.high_water > max_high_water) ||
4239             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4240                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4241                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4242                 return -EINVAL;
4243         }
4244
4245         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4246         hw->fc.pause_time = pfc_conf->fc.pause_time;
4247         hw->fc.send_xon = pfc_conf->fc.send_xon;
4248         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4249         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4250
4251         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4252
4253         /* Not negotiated is not an error case */
4254         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4255                 return 0;
4256
4257         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4258         return -EIO;
4259 }
4260
4261 static int
4262 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4263                           struct rte_eth_rss_reta_entry64 *reta_conf,
4264                           uint16_t reta_size)
4265 {
4266         uint16_t i, sp_reta_size;
4267         uint8_t j, mask;
4268         uint32_t reta, r;
4269         uint16_t idx, shift;
4270         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4271         uint32_t reta_reg;
4272
4273         PMD_INIT_FUNC_TRACE();
4274
4275         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4276                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4277                         "NIC.");
4278                 return -ENOTSUP;
4279         }
4280
4281         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4282         if (reta_size != sp_reta_size) {
4283                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4284                         "(%d) doesn't match the number hardware can supported "
4285                         "(%d)\n", reta_size, sp_reta_size);
4286                 return -EINVAL;
4287         }
4288
4289         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4290                 idx = i / RTE_RETA_GROUP_SIZE;
4291                 shift = i % RTE_RETA_GROUP_SIZE;
4292                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4293                                                 IXGBE_4_BIT_MASK);
4294                 if (!mask)
4295                         continue;
4296                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4297                 if (mask == IXGBE_4_BIT_MASK)
4298                         r = 0;
4299                 else
4300                         r = IXGBE_READ_REG(hw, reta_reg);
4301                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4302                         if (mask & (0x1 << j))
4303                                 reta |= reta_conf[idx].reta[shift + j] <<
4304                                                         (CHAR_BIT * j);
4305                         else
4306                                 reta |= r & (IXGBE_8_BIT_MASK <<
4307                                                 (CHAR_BIT * j));
4308                 }
4309                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4310         }
4311
4312         return 0;
4313 }
4314
4315 static int
4316 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4317                          struct rte_eth_rss_reta_entry64 *reta_conf,
4318                          uint16_t reta_size)
4319 {
4320         uint16_t i, sp_reta_size;
4321         uint8_t j, mask;
4322         uint32_t reta;
4323         uint16_t idx, shift;
4324         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4325         uint32_t reta_reg;
4326
4327         PMD_INIT_FUNC_TRACE();
4328         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4329         if (reta_size != sp_reta_size) {
4330                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4331                         "(%d) doesn't match the number hardware can supported "
4332                         "(%d)\n", reta_size, sp_reta_size);
4333                 return -EINVAL;
4334         }
4335
4336         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4337                 idx = i / RTE_RETA_GROUP_SIZE;
4338                 shift = i % RTE_RETA_GROUP_SIZE;
4339                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4340                                                 IXGBE_4_BIT_MASK);
4341                 if (!mask)
4342                         continue;
4343
4344                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4345                 reta = IXGBE_READ_REG(hw, reta_reg);
4346                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4347                         if (mask & (0x1 << j))
4348                                 reta_conf[idx].reta[shift + j] =
4349                                         ((reta >> (CHAR_BIT * j)) &
4350                                                 IXGBE_8_BIT_MASK);
4351                 }
4352         }
4353
4354         return 0;
4355 }
4356
4357 static void
4358 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4359                                 uint32_t index, uint32_t pool)
4360 {
4361         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362         uint32_t enable_addr = 1;
4363
4364         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4365 }
4366
4367 static void
4368 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4369 {
4370         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4371
4372         ixgbe_clear_rar(hw, index);
4373 }
4374
4375 static void
4376 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4377 {
4378         ixgbe_remove_rar(dev, 0);
4379
4380         ixgbe_add_rar(dev, addr, 0, 0);
4381 }
4382
4383 static int
4384 is_ixgbe_pmd(const char *driver_name)
4385 {
4386         if (!strstr(driver_name, "ixgbe"))
4387                 return -ENOTSUP;
4388
4389         if (strstr(driver_name, "ixgbe_vf"))
4390                 return -ENOTSUP;
4391
4392         return 0;
4393 }
4394
4395 int
4396 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4397                 struct ether_addr *mac_addr)
4398 {
4399         struct ixgbe_hw *hw;
4400         struct ixgbe_vf_info *vfinfo;
4401         int rar_entry;
4402         uint8_t *new_mac = (uint8_t *)(mac_addr);
4403         struct rte_eth_dev *dev;
4404         struct rte_eth_dev_info dev_info;
4405
4406         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4407
4408         dev = &rte_eth_devices[port];
4409         rte_eth_dev_info_get(port, &dev_info);
4410
4411         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4412                 return -ENOTSUP;
4413
4414         if (vf >= dev_info.max_vfs)
4415                 return -EINVAL;
4416
4417         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4418         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4419         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4420
4421         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4422                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4423                                 ETHER_ADDR_LEN);
4424                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4425                                 IXGBE_RAH_AV);
4426         }
4427         return -EINVAL;
4428 }
4429
4430 static int
4431 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4432 {
4433         uint32_t hlreg0;
4434         uint32_t maxfrs;
4435         struct ixgbe_hw *hw;
4436         struct rte_eth_dev_info dev_info;
4437         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4438
4439         ixgbe_dev_info_get(dev, &dev_info);
4440
4441         /* check that mtu is within the allowed range */
4442         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4443                 return -EINVAL;
4444
4445         /* refuse mtu that requires the support of scattered packets when this
4446          * feature has not been enabled before.
4447          */
4448         if (!dev->data->scattered_rx &&
4449             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4450              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4451                 return -EINVAL;
4452
4453         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4454         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4455
4456         /* switch to jumbo mode if needed */
4457         if (frame_size > ETHER_MAX_LEN) {
4458                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4459                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4460         } else {
4461                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4462                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4463         }
4464         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4465
4466         /* update max frame size */
4467         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4468
4469         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4470         maxfrs &= 0x0000FFFF;
4471         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4472         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4473
4474         return 0;
4475 }
4476
4477 /*
4478  * Virtual Function operations
4479  */
4480 static void
4481 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4482 {
4483         PMD_INIT_FUNC_TRACE();
4484
4485         /* Clear interrupt mask to stop from interrupts being generated */
4486         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4487
4488         IXGBE_WRITE_FLUSH(hw);
4489 }
4490
4491 static void
4492 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4493 {
4494         PMD_INIT_FUNC_TRACE();
4495
4496         /* VF enable interrupt autoclean */
4497         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4498         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4499         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4500
4501         IXGBE_WRITE_FLUSH(hw);
4502 }
4503
4504 static int
4505 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4506 {
4507         struct rte_eth_conf *conf = &dev->data->dev_conf;
4508         struct ixgbe_adapter *adapter =
4509                         (struct ixgbe_adapter *)dev->data->dev_private;
4510
4511         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4512                      dev->data->port_id);
4513
4514         /*
4515          * VF has no ability to enable/disable HW CRC
4516          * Keep the persistent behavior the same as Host PF
4517          */
4518 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4519         if (!conf->rxmode.hw_strip_crc) {
4520                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4521                 conf->rxmode.hw_strip_crc = 1;
4522         }
4523 #else
4524         if (conf->rxmode.hw_strip_crc) {
4525                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4526                 conf->rxmode.hw_strip_crc = 0;
4527         }
4528 #endif
4529
4530         /*
4531          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4532          * allocation or vector Rx preconditions we will reset it.
4533          */
4534         adapter->rx_bulk_alloc_allowed = true;
4535         adapter->rx_vec_allowed = true;
4536
4537         return 0;
4538 }
4539
4540 static int
4541 ixgbevf_dev_start(struct rte_eth_dev *dev)
4542 {
4543         struct ixgbe_hw *hw =
4544                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4545         uint32_t intr_vector = 0;
4546         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4547         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4548
4549         int err, mask = 0;
4550
4551         PMD_INIT_FUNC_TRACE();
4552
4553         hw->mac.ops.reset_hw(hw);
4554         hw->mac.get_link_status = true;
4555
4556         /* negotiate mailbox API version to use with the PF. */
4557         ixgbevf_negotiate_api(hw);
4558
4559         ixgbevf_dev_tx_init(dev);
4560
4561         /* This can fail when allocating mbufs for descriptor rings */
4562         err = ixgbevf_dev_rx_init(dev);
4563         if (err) {
4564                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4565                 ixgbe_dev_clear_queues(dev);
4566                 return err;
4567         }
4568
4569         /* Set vfta */
4570         ixgbevf_set_vfta_all(dev, 1);
4571
4572         /* Set HW strip */
4573         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4574                 ETH_VLAN_EXTEND_MASK;
4575         ixgbevf_vlan_offload_set(dev, mask);
4576
4577         ixgbevf_dev_rxtx_start(dev);
4578
4579         /* check and configure queue intr-vector mapping */
4580         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4581                 intr_vector = dev->data->nb_rx_queues;
4582                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4583                         return -1;
4584         }
4585
4586         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4587                 intr_handle->intr_vec =
4588                         rte_zmalloc("intr_vec",
4589                                     dev->data->nb_rx_queues * sizeof(int), 0);
4590                 if (intr_handle->intr_vec == NULL) {
4591                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4592                                      " intr_vec\n", dev->data->nb_rx_queues);
4593                         return -ENOMEM;
4594                 }
4595         }
4596         ixgbevf_configure_msix(dev);
4597
4598         rte_intr_enable(intr_handle);
4599
4600         /* Re-enable interrupt for VF */
4601         ixgbevf_intr_enable(hw);
4602
4603         return 0;
4604 }
4605
4606 static void
4607 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4608 {
4609         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4610         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4611         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4612
4613         PMD_INIT_FUNC_TRACE();
4614
4615         ixgbevf_intr_disable(hw);
4616
4617         hw->adapter_stopped = 1;
4618         ixgbe_stop_adapter(hw);
4619
4620         /*
4621           * Clear what we set, but we still keep shadow_vfta to
4622           * restore after device starts
4623           */
4624         ixgbevf_set_vfta_all(dev, 0);
4625
4626         /* Clear stored conf */
4627         dev->data->scattered_rx = 0;
4628
4629         ixgbe_dev_clear_queues(dev);
4630
4631         /* Clean datapath event and queue/vec mapping */
4632         rte_intr_efd_disable(intr_handle);
4633         if (intr_handle->intr_vec != NULL) {
4634                 rte_free(intr_handle->intr_vec);
4635                 intr_handle->intr_vec = NULL;
4636         }
4637 }
4638
4639 static void
4640 ixgbevf_dev_close(struct rte_eth_dev *dev)
4641 {
4642         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4643
4644         PMD_INIT_FUNC_TRACE();
4645
4646         ixgbe_reset_hw(hw);
4647
4648         ixgbevf_dev_stop(dev);
4649
4650         ixgbe_dev_free_queues(dev);
4651
4652         /**
4653          * Remove the VF MAC address ro ensure
4654          * that the VF traffic goes to the PF
4655          * after stop, close and detach of the VF
4656          **/
4657         ixgbevf_remove_mac_addr(dev, 0);
4658 }
4659
4660 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4661 {
4662         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4663         struct ixgbe_vfta *shadow_vfta =
4664                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4665         int i = 0, j = 0, vfta = 0, mask = 1;
4666
4667         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4668                 vfta = shadow_vfta->vfta[i];
4669                 if (vfta) {
4670                         mask = 1;
4671                         for (j = 0; j < 32; j++) {
4672                                 if (vfta & mask)
4673                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4674                                                        on, false);
4675                                 mask <<= 1;
4676                         }
4677                 }
4678         }
4679
4680 }
4681
4682 static int
4683 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4684 {
4685         struct ixgbe_hw *hw =
4686                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4687         struct ixgbe_vfta *shadow_vfta =
4688                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4689         uint32_t vid_idx = 0;
4690         uint32_t vid_bit = 0;
4691         int ret = 0;
4692
4693         PMD_INIT_FUNC_TRACE();
4694
4695         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4696         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4697         if (ret) {
4698                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4699                 return ret;
4700         }
4701         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4702         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4703
4704         /* Save what we set and retore it after device reset */
4705         if (on)
4706                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4707         else
4708                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4709
4710         return 0;
4711 }
4712
4713 static void
4714 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4715 {
4716         struct ixgbe_hw *hw =
4717                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4718         uint32_t ctrl;
4719
4720         PMD_INIT_FUNC_TRACE();
4721
4722         if (queue >= hw->mac.max_rx_queues)
4723                 return;
4724
4725         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4726         if (on)
4727                 ctrl |= IXGBE_RXDCTL_VME;
4728         else
4729                 ctrl &= ~IXGBE_RXDCTL_VME;
4730         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4731
4732         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4733 }
4734
4735 static void
4736 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4737 {
4738         struct ixgbe_hw *hw =
4739                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4740         uint16_t i;
4741         int on = 0;
4742
4743         /* VF function only support hw strip feature, others are not support */
4744         if (mask & ETH_VLAN_STRIP_MASK) {
4745                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4746
4747                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4748                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4749         }
4750 }
4751
4752 static int
4753 ixgbe_vt_check(struct ixgbe_hw *hw)
4754 {
4755         uint32_t reg_val;
4756
4757         /* if Virtualization Technology is enabled */
4758         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4759         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4760                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4761                 return -1;
4762         }
4763
4764         return 0;
4765 }
4766
4767 static uint32_t
4768 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4769 {
4770         uint32_t vector = 0;
4771
4772         switch (hw->mac.mc_filter_type) {
4773         case 0:   /* use bits [47:36] of the address */
4774                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4775                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4776                 break;
4777         case 1:   /* use bits [46:35] of the address */
4778                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4779                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4780                 break;
4781         case 2:   /* use bits [45:34] of the address */
4782                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4783                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4784                 break;
4785         case 3:   /* use bits [43:32] of the address */
4786                 vector = ((uc_addr->addr_bytes[4]) |
4787                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4788                 break;
4789         default:  /* Invalid mc_filter_type */
4790                 break;
4791         }
4792
4793         /* vector can only be 12-bits or boundary will be exceeded */
4794         vector &= 0xFFF;
4795         return vector;
4796 }
4797
4798 static int
4799 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4800                         uint8_t on)
4801 {
4802         uint32_t vector;
4803         uint32_t uta_idx;
4804         uint32_t reg_val;
4805         uint32_t uta_shift;
4806         uint32_t rc;
4807         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4808         const uint32_t ixgbe_uta_bit_shift = 5;
4809         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4810         const uint32_t bit1 = 0x1;
4811
4812         struct ixgbe_hw *hw =
4813                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4814         struct ixgbe_uta_info *uta_info =
4815                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4816
4817         /* The UTA table only exists on 82599 hardware and newer */
4818         if (hw->mac.type < ixgbe_mac_82599EB)
4819                 return -ENOTSUP;
4820
4821         vector = ixgbe_uta_vector(hw, mac_addr);
4822         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4823         uta_shift = vector & ixgbe_uta_bit_mask;
4824
4825         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4826         if (rc == on)
4827                 return 0;
4828
4829         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4830         if (on) {
4831                 uta_info->uta_in_use++;
4832                 reg_val |= (bit1 << uta_shift);
4833                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4834         } else {
4835                 uta_info->uta_in_use--;
4836                 reg_val &= ~(bit1 << uta_shift);
4837                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4838         }
4839
4840         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4841
4842         if (uta_info->uta_in_use > 0)
4843                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4844                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4845         else
4846                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4847
4848         return 0;
4849 }
4850
4851 static int
4852 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4853 {
4854         int i;
4855         struct ixgbe_hw *hw =
4856                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4857         struct ixgbe_uta_info *uta_info =
4858                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4859
4860         /* The UTA table only exists on 82599 hardware and newer */
4861         if (hw->mac.type < ixgbe_mac_82599EB)
4862                 return -ENOTSUP;
4863
4864         if (on) {
4865                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4866                         uta_info->uta_shadow[i] = ~0;
4867                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4868                 }
4869         } else {
4870                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4871                         uta_info->uta_shadow[i] = 0;
4872                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4873                 }
4874         }
4875         return 0;
4876
4877 }
4878
4879 uint32_t
4880 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4881 {
4882         uint32_t new_val = orig_val;
4883
4884         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4885                 new_val |= IXGBE_VMOLR_AUPE;
4886         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4887                 new_val |= IXGBE_VMOLR_ROMPE;
4888         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4889                 new_val |= IXGBE_VMOLR_ROPE;
4890         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4891                 new_val |= IXGBE_VMOLR_BAM;
4892         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4893                 new_val |= IXGBE_VMOLR_MPE;
4894
4895         return new_val;
4896 }
4897
4898
4899 int
4900 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4901 {
4902         struct ixgbe_hw *hw;
4903         struct ixgbe_mac_info *mac;
4904         struct rte_eth_dev *dev;
4905         struct rte_eth_dev_info dev_info;
4906
4907         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4908
4909         dev = &rte_eth_devices[port];
4910         rte_eth_dev_info_get(port, &dev_info);
4911
4912         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4913                 return -ENOTSUP;
4914
4915         if (vf >= dev_info.max_vfs)
4916                 return -EINVAL;
4917
4918         if (on > 1)
4919                 return -EINVAL;
4920
4921         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4922         mac = &hw->mac;
4923
4924         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4925
4926         return 0;
4927 }
4928
4929 int
4930 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4931 {
4932         struct ixgbe_hw *hw;
4933         struct ixgbe_mac_info *mac;
4934         struct rte_eth_dev *dev;
4935         struct rte_eth_dev_info dev_info;
4936
4937         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4938
4939         dev = &rte_eth_devices[port];
4940         rte_eth_dev_info_get(port, &dev_info);
4941
4942         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4943                 return -ENOTSUP;
4944
4945         if (vf >= dev_info.max_vfs)
4946                 return -EINVAL;
4947
4948         if (on > 1)
4949                 return -EINVAL;
4950
4951         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4952         mac = &hw->mac;
4953         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4954
4955         return 0;
4956 }
4957
4958 int
4959 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4960 {
4961         struct ixgbe_hw *hw;
4962         uint32_t ctrl;
4963         struct rte_eth_dev *dev;
4964         struct rte_eth_dev_info dev_info;
4965
4966         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4967
4968         dev = &rte_eth_devices[port];
4969         rte_eth_dev_info_get(port, &dev_info);
4970
4971         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4972                 return -ENOTSUP;
4973
4974         if (vf >= dev_info.max_vfs)
4975                 return -EINVAL;
4976
4977         if (vlan_id > ETHER_MAX_VLAN_ID)
4978                 return -EINVAL;
4979
4980         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4981         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4982         if (vlan_id) {
4983                 ctrl = vlan_id;
4984                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4985         } else {
4986                 ctrl = 0;
4987         }
4988
4989         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4990
4991         return 0;
4992 }
4993
4994 int
4995 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4996 {
4997         struct ixgbe_hw *hw;
4998         uint32_t ctrl;
4999         struct rte_eth_dev *dev;
5000         struct rte_eth_dev_info dev_info;
5001
5002         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5003
5004         dev = &rte_eth_devices[port];
5005         rte_eth_dev_info_get(port, &dev_info);
5006
5007         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5008                 return -ENOTSUP;
5009
5010         if (on > 1)
5011                 return -EINVAL;
5012
5013         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5014         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5015         /* enable or disable VMDQ loopback */
5016         if (on)
5017                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5018         else
5019                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5020
5021         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5022
5023         return 0;
5024 }
5025
5026 int
5027 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5028 {
5029         struct ixgbe_hw *hw;
5030         uint32_t reg_value;
5031         int i;
5032         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5033         struct rte_eth_dev *dev;
5034         struct rte_eth_dev_info dev_info;
5035
5036         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5037
5038         dev = &rte_eth_devices[port];
5039         rte_eth_dev_info_get(port, &dev_info);
5040
5041         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5042                 return -ENOTSUP;
5043
5044         if (on > 1)
5045                 return -EINVAL;
5046
5047         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5048         for (i = 0; i <= num_queues; i++) {
5049                 reg_value = IXGBE_QDE_WRITE |
5050                                 (i << IXGBE_QDE_IDX_SHIFT) |
5051                                 (on & IXGBE_QDE_ENABLE);
5052                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5053         }
5054
5055         return 0;
5056 }
5057
5058 int
5059 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5060 {
5061         struct ixgbe_hw *hw;
5062         uint32_t reg_value;
5063         struct rte_eth_dev *dev;
5064         struct rte_eth_dev_info dev_info;
5065
5066         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5067
5068         dev = &rte_eth_devices[port];
5069         rte_eth_dev_info_get(port, &dev_info);
5070
5071         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5072                 return -ENOTSUP;
5073
5074         /* only support VF's 0 to 63 */
5075         if ((vf >= dev_info.max_vfs) || (vf > 63))
5076                 return -EINVAL;
5077
5078         if (on > 1)
5079                 return -EINVAL;
5080
5081         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5082         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5083         if (on)
5084                 reg_value |= IXGBE_SRRCTL_DROP_EN;
5085         else
5086                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5087
5088         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5089
5090         return 0;
5091 }
5092
5093 int
5094 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5095 {
5096         struct rte_eth_dev *dev;
5097         struct rte_eth_dev_info dev_info;
5098         uint16_t queues_per_pool;
5099         uint32_t q;
5100
5101         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5102
5103         dev = &rte_eth_devices[port];
5104         rte_eth_dev_info_get(port, &dev_info);
5105
5106         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5107                 return -ENOTSUP;
5108
5109         if (vf >= dev_info.max_vfs)
5110                 return -EINVAL;
5111
5112         if (on > 1)
5113                 return -EINVAL;
5114
5115         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5116
5117         /* The PF has 128 queue pairs and in SRIOV configuration
5118          * those queues will be assigned to VF's, so RXDCTL
5119          * registers will be dealing with queues which will be
5120          * assigned to VF's.
5121          * Let's say we have SRIOV configured with 31 VF's then the
5122          * first 124 queues 0-123 will be allocated to VF's and only
5123          * the last 4 queues 123-127 will be assigned to the PF.
5124          */
5125
5126         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5127
5128         for (q = 0; q < queues_per_pool; q++)
5129                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5130                                 q + vf * queues_per_pool, on);
5131         return 0;
5132 }
5133
5134 int
5135 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5136 {
5137         int val = 0;
5138         struct rte_eth_dev *dev;
5139         struct rte_eth_dev_info dev_info;
5140         struct ixgbe_hw *hw;
5141         uint32_t vmolr;
5142
5143         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5144
5145         dev = &rte_eth_devices[port];
5146         rte_eth_dev_info_get(port, &dev_info);
5147
5148         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5149                 return -ENOTSUP;
5150
5151         if (vf >= dev_info.max_vfs)
5152                 return -EINVAL;
5153
5154         if (on > 1)
5155                 return -EINVAL;
5156
5157         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5158         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5159
5160         if (hw->mac.type == ixgbe_mac_82598EB) {
5161                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5162                              " on 82599 hardware and newer");
5163                 return -ENOTSUP;
5164         }
5165         if (ixgbe_vt_check(hw) < 0)
5166                 return -ENOTSUP;
5167
5168         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5169
5170         if (on)
5171                 vmolr |= val;
5172         else
5173                 vmolr &= ~val;
5174
5175         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5176
5177         return 0;
5178 }
5179
5180 int
5181 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5182 {
5183         struct rte_eth_dev *dev;
5184         struct rte_eth_dev_info dev_info;
5185         uint32_t reg, addr;
5186         uint32_t val;
5187         const uint8_t bit1 = 0x1;
5188         struct ixgbe_hw *hw;
5189
5190         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5191
5192         dev = &rte_eth_devices[port];
5193         rte_eth_dev_info_get(port, &dev_info);
5194
5195         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5196                 return -ENOTSUP;
5197
5198         if (vf >= dev_info.max_vfs)
5199                 return -EINVAL;
5200
5201         if (on > 1)
5202                 return -EINVAL;
5203
5204         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205
5206         if (ixgbe_vt_check(hw) < 0)
5207                 return -ENOTSUP;
5208
5209         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5210         if (vf >= 32) {
5211                 addr = IXGBE_VFRE(1);
5212                 val = bit1 << (vf - 32);
5213         } else {
5214                 addr = IXGBE_VFRE(0);
5215                 val = bit1 << vf;
5216         }
5217
5218         reg = IXGBE_READ_REG(hw, addr);
5219
5220         if (on)
5221                 reg |= val;
5222         else
5223                 reg &= ~val;
5224
5225         IXGBE_WRITE_REG(hw, addr, reg);
5226
5227         return 0;
5228 }
5229
5230 int
5231 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5232 {
5233         struct rte_eth_dev *dev;
5234         struct rte_eth_dev_info dev_info;
5235         uint32_t reg, addr;
5236         uint32_t val;
5237         const uint8_t bit1 = 0x1;
5238
5239         struct ixgbe_hw *hw;
5240
5241         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5242
5243         dev = &rte_eth_devices[port];
5244         rte_eth_dev_info_get(port, &dev_info);
5245
5246         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5247                 return -ENOTSUP;
5248
5249         if (vf >= dev_info.max_vfs)
5250                 return -EINVAL;
5251
5252         if (on > 1)
5253                 return -EINVAL;
5254
5255         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5256         if (ixgbe_vt_check(hw) < 0)
5257                 return -ENOTSUP;
5258
5259         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5260         if (vf >= 32) {
5261                 addr = IXGBE_VFTE(1);
5262                 val = bit1 << (vf - 32);
5263         } else {
5264                 addr = IXGBE_VFTE(0);
5265                 val = bit1 << vf;
5266         }
5267
5268         reg = IXGBE_READ_REG(hw, addr);
5269
5270         if (on)
5271                 reg |= val;
5272         else
5273                 reg &= ~val;
5274
5275         IXGBE_WRITE_REG(hw, addr, reg);
5276
5277         return 0;
5278 }
5279
5280 int
5281 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5282                         uint64_t vf_mask, uint8_t vlan_on)
5283 {
5284         struct rte_eth_dev *dev;
5285         struct rte_eth_dev_info dev_info;
5286         int ret = 0;
5287         uint16_t vf_idx;
5288         struct ixgbe_hw *hw;
5289
5290         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5291
5292         dev = &rte_eth_devices[port];
5293         rte_eth_dev_info_get(port, &dev_info);
5294
5295         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5296                 return -ENOTSUP;
5297
5298         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5299                 return -EINVAL;
5300
5301         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5302         if (ixgbe_vt_check(hw) < 0)
5303                 return -ENOTSUP;
5304
5305         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5306                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5307                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5308                                                    vlan_on, false);
5309                         if (ret < 0)
5310                                 return ret;
5311                 }
5312         }
5313
5314         return ret;
5315 }
5316
5317 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5318         uint16_t tx_rate, uint64_t q_msk)
5319 {
5320         struct rte_eth_dev *dev;
5321         struct rte_eth_dev_info dev_info;
5322         struct ixgbe_hw *hw;
5323         struct ixgbe_vf_info *vfinfo;
5324         struct rte_eth_link link;
5325         uint8_t  nb_q_per_pool;
5326         uint32_t queue_stride;
5327         uint32_t queue_idx, idx = 0, vf_idx;
5328         uint32_t queue_end;
5329         uint16_t total_rate = 0;
5330         struct rte_pci_device *pci_dev;
5331
5332         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5333
5334         dev = &rte_eth_devices[port];
5335         rte_eth_dev_info_get(port, &dev_info);
5336         rte_eth_link_get_nowait(port, &link);
5337
5338         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5339                 return -ENOTSUP;
5340
5341         if (vf >= dev_info.max_vfs)
5342                 return -EINVAL;
5343
5344         if (tx_rate > link.link_speed)
5345                 return -EINVAL;
5346
5347         if (q_msk == 0)
5348                 return 0;
5349
5350         pci_dev = IXGBE_DEV_TO_PCI(dev);
5351         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5352         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5353         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5354         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5355         queue_idx = vf * queue_stride;
5356         queue_end = queue_idx + nb_q_per_pool - 1;
5357         if (queue_end >= hw->mac.max_tx_queues)
5358                 return -EINVAL;
5359
5360         if (vfinfo) {
5361                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5362                         if (vf_idx == vf)
5363                                 continue;
5364                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5365                                 idx++)
5366                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5367                 }
5368         } else {
5369                 return -EINVAL;
5370         }
5371
5372         /* Store tx_rate for this vf. */
5373         for (idx = 0; idx < nb_q_per_pool; idx++) {
5374                 if (((uint64_t)0x1 << idx) & q_msk) {
5375                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5376                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5377                         total_rate += tx_rate;
5378                 }
5379         }
5380
5381         if (total_rate > dev->data->dev_link.link_speed) {
5382                 /* Reset stored TX rate of the VF if it causes exceed
5383                  * link speed.
5384                  */
5385                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5386                 return -EINVAL;
5387         }
5388
5389         /* Set RTTBCNRC of each queue/pool for vf X  */
5390         for (; queue_idx <= queue_end; queue_idx++) {
5391                 if (0x1 & q_msk)
5392                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5393                 q_msk = q_msk >> 1;
5394         }
5395
5396         return 0;
5397 }
5398
5399 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5400 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5401 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5402 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5403 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5404         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5405         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5406
5407 static int
5408 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5409                         struct rte_eth_mirror_conf *mirror_conf,
5410                         uint8_t rule_id, uint8_t on)
5411 {
5412         uint32_t mr_ctl, vlvf;
5413         uint32_t mp_lsb = 0;
5414         uint32_t mv_msb = 0;
5415         uint32_t mv_lsb = 0;
5416         uint32_t mp_msb = 0;
5417         uint8_t i = 0;
5418         int reg_index = 0;
5419         uint64_t vlan_mask = 0;
5420
5421         const uint8_t pool_mask_offset = 32;
5422         const uint8_t vlan_mask_offset = 32;
5423         const uint8_t dst_pool_offset = 8;
5424         const uint8_t rule_mr_offset  = 4;
5425         const uint8_t mirror_rule_mask = 0x0F;
5426
5427         struct ixgbe_mirror_info *mr_info =
5428                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5429         struct ixgbe_hw *hw =
5430                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5431         uint8_t mirror_type = 0;
5432
5433         if (ixgbe_vt_check(hw) < 0)
5434                 return -ENOTSUP;
5435
5436         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5437                 return -EINVAL;
5438
5439         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5440                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5441                         mirror_conf->rule_type);
5442                 return -EINVAL;
5443         }
5444
5445         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5446                 mirror_type |= IXGBE_MRCTL_VLME;
5447                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5448                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5449                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5450                                 /* search vlan id related pool vlan filter index */
5451                                 reg_index = ixgbe_find_vlvf_slot(hw,
5452                                                  mirror_conf->vlan.vlan_id[i],
5453                                                  false);
5454                                 if (reg_index < 0)
5455                                         return -EINVAL;
5456                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5457                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5458                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5459                                       mirror_conf->vlan.vlan_id[i]))
5460                                         vlan_mask |= (1ULL << reg_index);
5461                                 else
5462                                         return -EINVAL;
5463                         }
5464                 }
5465
5466                 if (on) {
5467                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5468                         mv_msb = vlan_mask >> vlan_mask_offset;
5469
5470                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5471                                                 mirror_conf->vlan.vlan_mask;
5472                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5473                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5474                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5475                                                 mirror_conf->vlan.vlan_id[i];
5476                         }
5477                 } else {
5478                         mv_lsb = 0;
5479                         mv_msb = 0;
5480                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5481                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5482                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5483                 }
5484         }
5485
5486         /*
5487          * if enable pool mirror, write related pool mask register,if disable
5488          * pool mirror, clear PFMRVM register
5489          */
5490         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5491                 mirror_type |= IXGBE_MRCTL_VPME;
5492                 if (on) {
5493                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5494                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5495                         mr_info->mr_conf[rule_id].pool_mask =
5496                                         mirror_conf->pool_mask;
5497
5498                 } else {
5499                         mp_lsb = 0;
5500                         mp_msb = 0;
5501                         mr_info->mr_conf[rule_id].pool_mask = 0;
5502                 }
5503         }
5504         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5505                 mirror_type |= IXGBE_MRCTL_UPME;
5506         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5507                 mirror_type |= IXGBE_MRCTL_DPME;
5508
5509         /* read  mirror control register and recalculate it */
5510         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5511
5512         if (on) {
5513                 mr_ctl |= mirror_type;
5514                 mr_ctl &= mirror_rule_mask;
5515                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5516         } else
5517                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5518
5519         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5520         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5521
5522         /* write mirrror control  register */
5523         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5524
5525         /* write pool mirrror control  register */
5526         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5527                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5528                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5529                                 mp_msb);
5530         }
5531         /* write VLAN mirrror control  register */
5532         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5533                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5534                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5535                                 mv_msb);
5536         }
5537
5538         return 0;
5539 }
5540
5541 static int
5542 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5543 {
5544         int mr_ctl = 0;
5545         uint32_t lsb_val = 0;
5546         uint32_t msb_val = 0;
5547         const uint8_t rule_mr_offset = 4;
5548
5549         struct ixgbe_hw *hw =
5550                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5551         struct ixgbe_mirror_info *mr_info =
5552                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5553
5554         if (ixgbe_vt_check(hw) < 0)
5555                 return -ENOTSUP;
5556
5557         memset(&mr_info->mr_conf[rule_id], 0,
5558                 sizeof(struct rte_eth_mirror_conf));
5559
5560         /* clear PFVMCTL register */
5561         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5562
5563         /* clear pool mask register */
5564         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5565         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5566
5567         /* clear vlan mask register */
5568         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5569         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5570
5571         return 0;
5572 }
5573
5574 static int
5575 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5576 {
5577         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5578         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5579         uint32_t mask;
5580         struct ixgbe_hw *hw =
5581                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5582
5583         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5584         mask |= (1 << IXGBE_MISC_VEC_ID);
5585         RTE_SET_USED(queue_id);
5586         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5587
5588         rte_intr_enable(intr_handle);
5589
5590         return 0;
5591 }
5592
5593 static int
5594 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5595 {
5596         uint32_t mask;
5597         struct ixgbe_hw *hw =
5598                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5599
5600         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5601         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5602         RTE_SET_USED(queue_id);
5603         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5604
5605         return 0;
5606 }
5607
5608 static int
5609 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5610 {
5611         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5612         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5613         uint32_t mask;
5614         struct ixgbe_hw *hw =
5615                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5616         struct ixgbe_interrupt *intr =
5617                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5618
5619         if (queue_id < 16) {
5620                 ixgbe_disable_intr(hw);
5621                 intr->mask |= (1 << queue_id);
5622                 ixgbe_enable_intr(dev);
5623         } else if (queue_id < 32) {
5624                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5625                 mask &= (1 << queue_id);
5626                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5627         } else if (queue_id < 64) {
5628                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5629                 mask &= (1 << (queue_id - 32));
5630                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5631         }
5632         rte_intr_enable(intr_handle);
5633
5634         return 0;
5635 }
5636
5637 static int
5638 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5639 {
5640         uint32_t mask;
5641         struct ixgbe_hw *hw =
5642                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5643         struct ixgbe_interrupt *intr =
5644                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5645
5646         if (queue_id < 16) {
5647                 ixgbe_disable_intr(hw);
5648                 intr->mask &= ~(1 << queue_id);
5649                 ixgbe_enable_intr(dev);
5650         } else if (queue_id < 32) {
5651                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5652                 mask &= ~(1 << queue_id);
5653                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5654         } else if (queue_id < 64) {
5655                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5656                 mask &= ~(1 << (queue_id - 32));
5657                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5658         }
5659
5660         return 0;
5661 }
5662
5663 static void
5664 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5665                      uint8_t queue, uint8_t msix_vector)
5666 {
5667         uint32_t tmp, idx;
5668
5669         if (direction == -1) {
5670                 /* other causes */
5671                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5672                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5673                 tmp &= ~0xFF;
5674                 tmp |= msix_vector;
5675                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5676         } else {
5677                 /* rx or tx cause */
5678                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5679                 idx = ((16 * (queue & 1)) + (8 * direction));
5680                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5681                 tmp &= ~(0xFF << idx);
5682                 tmp |= (msix_vector << idx);
5683                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5684         }
5685 }
5686
5687 /**
5688  * set the IVAR registers, mapping interrupt causes to vectors
5689  * @param hw
5690  *  pointer to ixgbe_hw struct
5691  * @direction
5692  *  0 for Rx, 1 for Tx, -1 for other causes
5693  * @queue
5694  *  queue to map the corresponding interrupt to
5695  * @msix_vector
5696  *  the vector to map to the corresponding queue
5697  */
5698 static void
5699 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5700                    uint8_t queue, uint8_t msix_vector)
5701 {
5702         uint32_t tmp, idx;
5703
5704         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5705         if (hw->mac.type == ixgbe_mac_82598EB) {
5706                 if (direction == -1)
5707                         direction = 0;
5708                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5709                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5710                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5711                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5712                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5713         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5714                         (hw->mac.type == ixgbe_mac_X540)) {
5715                 if (direction == -1) {
5716                         /* other causes */
5717                         idx = ((queue & 1) * 8);
5718                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5719                         tmp &= ~(0xFF << idx);
5720                         tmp |= (msix_vector << idx);
5721                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5722                 } else {
5723                         /* rx or tx causes */
5724                         idx = ((16 * (queue & 1)) + (8 * direction));
5725                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5726                         tmp &= ~(0xFF << idx);
5727                         tmp |= (msix_vector << idx);
5728                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5729                 }
5730         }
5731 }
5732
5733 static void
5734 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5735 {
5736         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5737         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5738         struct ixgbe_hw *hw =
5739                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5740         uint32_t q_idx;
5741         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5742
5743         /* Configure VF other cause ivar */
5744         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5745
5746         /* won't configure msix register if no mapping is done
5747          * between intr vector and event fd.
5748          */
5749         if (!rte_intr_dp_is_en(intr_handle))
5750                 return;
5751
5752         /* Configure all RX queues of VF */
5753         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5754                 /* Force all queue use vector 0,
5755                  * as IXGBE_VF_MAXMSIVECOTR = 1
5756                  */
5757                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5758                 intr_handle->intr_vec[q_idx] = vector_idx;
5759         }
5760 }
5761
5762 /**
5763  * Sets up the hardware to properly generate MSI-X interrupts
5764  * @hw
5765  *  board private structure
5766  */
5767 static void
5768 ixgbe_configure_msix(struct rte_eth_dev *dev)
5769 {
5770         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5771         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5772         struct ixgbe_hw *hw =
5773                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5774         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5775         uint32_t vec = IXGBE_MISC_VEC_ID;
5776         uint32_t mask;
5777         uint32_t gpie;
5778
5779         /* won't configure msix register if no mapping is done
5780          * between intr vector and event fd
5781          */
5782         if (!rte_intr_dp_is_en(intr_handle))
5783                 return;
5784
5785         if (rte_intr_allow_others(intr_handle))
5786                 vec = base = IXGBE_RX_VEC_START;
5787
5788         /* setup GPIE for MSI-x mode */
5789         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5790         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5791                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5792         /* auto clearing and auto setting corresponding bits in EIMS
5793          * when MSI-X interrupt is triggered
5794          */
5795         if (hw->mac.type == ixgbe_mac_82598EB) {
5796                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5797         } else {
5798                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5799                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5800         }
5801         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5802
5803         /* Populate the IVAR table and set the ITR values to the
5804          * corresponding register.
5805          */
5806         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5807              queue_id++) {
5808                 /* by default, 1:1 mapping */
5809                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5810                 intr_handle->intr_vec[queue_id] = vec;
5811                 if (vec < base + intr_handle->nb_efd - 1)
5812                         vec++;
5813         }
5814
5815         switch (hw->mac.type) {
5816         case ixgbe_mac_82598EB:
5817                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5818                                    IXGBE_MISC_VEC_ID);
5819                 break;
5820         case ixgbe_mac_82599EB:
5821         case ixgbe_mac_X540:
5822                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5823                 break;
5824         default:
5825                 break;
5826         }
5827         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5828                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5829
5830         /* set up to autoclear timer, and the vectors */
5831         mask = IXGBE_EIMS_ENABLE_MASK;
5832         mask &= ~(IXGBE_EIMS_OTHER |
5833                   IXGBE_EIMS_MAILBOX |
5834                   IXGBE_EIMS_LSC);
5835
5836         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5837 }
5838
5839 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5840         uint16_t queue_idx, uint16_t tx_rate)
5841 {
5842         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5843         uint32_t rf_dec, rf_int;
5844         uint32_t bcnrc_val;
5845         uint16_t link_speed = dev->data->dev_link.link_speed;
5846
5847         if (queue_idx >= hw->mac.max_tx_queues)
5848                 return -EINVAL;
5849
5850         if (tx_rate != 0) {
5851                 /* Calculate the rate factor values to set */
5852                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5853                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5854                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5855
5856                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5857                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5858                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5859                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5860         } else {
5861                 bcnrc_val = 0;
5862         }
5863
5864         /*
5865          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5866          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5867          * set as 0x4.
5868          */
5869         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5870                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5871                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5872                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5873                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5874         else
5875                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5876                         IXGBE_MMW_SIZE_DEFAULT);
5877
5878         /* Set RTTBCNRC of queue X */
5879         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5880         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5881         IXGBE_WRITE_FLUSH(hw);
5882
5883         return 0;
5884 }
5885
5886 static void
5887 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5888                      __attribute__((unused)) uint32_t index,
5889                      __attribute__((unused)) uint32_t pool)
5890 {
5891         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5892         int diag;
5893
5894         /*
5895          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5896          * operation. Trap this case to avoid exhausting the [very limited]
5897          * set of PF resources used to store VF MAC addresses.
5898          */
5899         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5900                 return;
5901         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5902         if (diag == 0)
5903                 return;
5904         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5905 }
5906
5907 static void
5908 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5909 {
5910         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5911         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5912         struct ether_addr *mac_addr;
5913         uint32_t i;
5914         int diag;
5915
5916         /*
5917          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5918          * not support the deletion of a given MAC address.
5919          * Instead, it imposes to delete all MAC addresses, then to add again
5920          * all MAC addresses with the exception of the one to be deleted.
5921          */
5922         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5923
5924         /*
5925          * Add again all MAC addresses, with the exception of the deleted one
5926          * and of the permanent MAC address.
5927          */
5928         for (i = 0, mac_addr = dev->data->mac_addrs;
5929              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5930                 /* Skip the deleted MAC address */
5931                 if (i == index)
5932                         continue;
5933                 /* Skip NULL MAC addresses */
5934                 if (is_zero_ether_addr(mac_addr))
5935                         continue;
5936                 /* Skip the permanent MAC address */
5937                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5938                         continue;
5939                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5940                 if (diag != 0)
5941                         PMD_DRV_LOG(ERR,
5942                                     "Adding again MAC address "
5943                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5944                                     "diag=%d",
5945                                     mac_addr->addr_bytes[0],
5946                                     mac_addr->addr_bytes[1],
5947                                     mac_addr->addr_bytes[2],
5948                                     mac_addr->addr_bytes[3],
5949                                     mac_addr->addr_bytes[4],
5950                                     mac_addr->addr_bytes[5],
5951                                     diag);
5952         }
5953 }
5954
5955 static void
5956 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5957 {
5958         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5959
5960         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5961 }
5962
5963 #define MAC_TYPE_FILTER_SUP(type)    do {\
5964         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5965                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5966                 (type) != ixgbe_mac_X550EM_a)\
5967                 return -ENOTSUP;\
5968 } while (0)
5969
5970 int
5971 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5972                         struct rte_eth_syn_filter *filter,
5973                         bool add)
5974 {
5975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5976         struct ixgbe_filter_info *filter_info =
5977                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5978         uint32_t syn_info;
5979         uint32_t synqf;
5980
5981         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5982                 return -EINVAL;
5983
5984         syn_info = filter_info->syn_info;
5985
5986         if (add) {
5987                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5988                         return -EINVAL;
5989                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5990                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5991
5992                 if (filter->hig_pri)
5993                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5994                 else
5995                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5996         } else {
5997                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5998                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5999                         return -ENOENT;
6000                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6001         }
6002
6003         filter_info->syn_info = synqf;
6004         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6005         IXGBE_WRITE_FLUSH(hw);
6006         return 0;
6007 }
6008
6009 static int
6010 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6011                         struct rte_eth_syn_filter *filter)
6012 {
6013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6014         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6015
6016         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6017                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6018                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6019                 return 0;
6020         }
6021         return -ENOENT;
6022 }
6023
6024 static int
6025 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6026                         enum rte_filter_op filter_op,
6027                         void *arg)
6028 {
6029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6030         int ret;
6031
6032         MAC_TYPE_FILTER_SUP(hw->mac.type);
6033
6034         if (filter_op == RTE_ETH_FILTER_NOP)
6035                 return 0;
6036
6037         if (arg == NULL) {
6038                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6039                             filter_op);
6040                 return -EINVAL;
6041         }
6042
6043         switch (filter_op) {
6044         case RTE_ETH_FILTER_ADD:
6045                 ret = ixgbe_syn_filter_set(dev,
6046                                 (struct rte_eth_syn_filter *)arg,
6047                                 TRUE);
6048                 break;
6049         case RTE_ETH_FILTER_DELETE:
6050                 ret = ixgbe_syn_filter_set(dev,
6051                                 (struct rte_eth_syn_filter *)arg,
6052                                 FALSE);
6053                 break;
6054         case RTE_ETH_FILTER_GET:
6055                 ret = ixgbe_syn_filter_get(dev,
6056                                 (struct rte_eth_syn_filter *)arg);
6057                 break;
6058         default:
6059                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6060                 ret = -EINVAL;
6061                 break;
6062         }
6063
6064         return ret;
6065 }
6066
6067
6068 static inline enum ixgbe_5tuple_protocol
6069 convert_protocol_type(uint8_t protocol_value)
6070 {
6071         if (protocol_value == IPPROTO_TCP)
6072                 return IXGBE_FILTER_PROTOCOL_TCP;
6073         else if (protocol_value == IPPROTO_UDP)
6074                 return IXGBE_FILTER_PROTOCOL_UDP;
6075         else if (protocol_value == IPPROTO_SCTP)
6076                 return IXGBE_FILTER_PROTOCOL_SCTP;
6077         else
6078                 return IXGBE_FILTER_PROTOCOL_NONE;
6079 }
6080
6081 /* inject a 5-tuple filter to HW */
6082 static inline void
6083 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6084                            struct ixgbe_5tuple_filter *filter)
6085 {
6086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6087         int i;
6088         uint32_t ftqf, sdpqf;
6089         uint32_t l34timir = 0;
6090         uint8_t mask = 0xff;
6091
6092         i = filter->index;
6093
6094         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6095                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6096         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6097
6098         ftqf = (uint32_t)(filter->filter_info.proto &
6099                 IXGBE_FTQF_PROTOCOL_MASK);
6100         ftqf |= (uint32_t)((filter->filter_info.priority &
6101                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6102         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6103                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6104         if (filter->filter_info.dst_ip_mask == 0)
6105                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6106         if (filter->filter_info.src_port_mask == 0)
6107                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6108         if (filter->filter_info.dst_port_mask == 0)
6109                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6110         if (filter->filter_info.proto_mask == 0)
6111                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6112         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6113         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6114         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6115
6116         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6117         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6118         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6119         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6120
6121         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6122         l34timir |= (uint32_t)(filter->queue <<
6123                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6124         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6125 }
6126
6127 /*
6128  * add a 5tuple filter
6129  *
6130  * @param
6131  * dev: Pointer to struct rte_eth_dev.
6132  * index: the index the filter allocates.
6133  * filter: ponter to the filter that will be added.
6134  * rx_queue: the queue id the filter assigned to.
6135  *
6136  * @return
6137  *    - On success, zero.
6138  *    - On failure, a negative value.
6139  */
6140 static int
6141 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6142                         struct ixgbe_5tuple_filter *filter)
6143 {
6144         struct ixgbe_filter_info *filter_info =
6145                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6146         int i, idx, shift;
6147
6148         /*
6149          * look for an unused 5tuple filter index,
6150          * and insert the filter to list.
6151          */
6152         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6153                 idx = i / (sizeof(uint32_t) * NBBY);
6154                 shift = i % (sizeof(uint32_t) * NBBY);
6155                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6156                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6157                         filter->index = i;
6158                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6159                                           filter,
6160                                           entries);
6161                         break;
6162                 }
6163         }
6164         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6165                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6166                 return -ENOSYS;
6167         }
6168
6169         ixgbe_inject_5tuple_filter(dev, filter);
6170
6171         return 0;
6172 }
6173
6174 /*
6175  * remove a 5tuple filter
6176  *
6177  * @param
6178  * dev: Pointer to struct rte_eth_dev.
6179  * filter: the pointer of the filter will be removed.
6180  */
6181 static void
6182 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6183                         struct ixgbe_5tuple_filter *filter)
6184 {
6185         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6186         struct ixgbe_filter_info *filter_info =
6187                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6188         uint16_t index = filter->index;
6189
6190         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6191                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6192         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6193         rte_free(filter);
6194
6195         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6196         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6197         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6198         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6199         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6200 }
6201
6202 static int
6203 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6204 {
6205         struct ixgbe_hw *hw;
6206         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6207
6208         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6209
6210         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6211                 return -EINVAL;
6212
6213         /* refuse mtu that requires the support of scattered packets when this
6214          * feature has not been enabled before.
6215          */
6216         if (!dev->data->scattered_rx &&
6217             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6218              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6219                 return -EINVAL;
6220
6221         /*
6222          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6223          * request of the version 2.0 of the mailbox API.
6224          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6225          * of the mailbox API.
6226          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6227          * prior to 3.11.33 which contains the following change:
6228          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6229          */
6230         ixgbevf_rlpml_set_vf(hw, max_frame);
6231
6232         /* update max frame size */
6233         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6234         return 0;
6235 }
6236
6237 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
6238         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6239                 return -ENOTSUP;\
6240 } while (0)
6241
6242 static inline struct ixgbe_5tuple_filter *
6243 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6244                         struct ixgbe_5tuple_filter_info *key)
6245 {
6246         struct ixgbe_5tuple_filter *it;
6247
6248         TAILQ_FOREACH(it, filter_list, entries) {
6249                 if (memcmp(key, &it->filter_info,
6250                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6251                         return it;
6252                 }
6253         }
6254         return NULL;
6255 }
6256
6257 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6258 static inline int
6259 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6260                         struct ixgbe_5tuple_filter_info *filter_info)
6261 {
6262         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6263                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6264                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6265                 return -EINVAL;
6266
6267         switch (filter->dst_ip_mask) {
6268         case UINT32_MAX:
6269                 filter_info->dst_ip_mask = 0;
6270                 filter_info->dst_ip = filter->dst_ip;
6271                 break;
6272         case 0:
6273                 filter_info->dst_ip_mask = 1;
6274                 break;
6275         default:
6276                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6277                 return -EINVAL;
6278         }
6279
6280         switch (filter->src_ip_mask) {
6281         case UINT32_MAX:
6282                 filter_info->src_ip_mask = 0;
6283                 filter_info->src_ip = filter->src_ip;
6284                 break;
6285         case 0:
6286                 filter_info->src_ip_mask = 1;
6287                 break;
6288         default:
6289                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6290                 return -EINVAL;
6291         }
6292
6293         switch (filter->dst_port_mask) {
6294         case UINT16_MAX:
6295                 filter_info->dst_port_mask = 0;
6296                 filter_info->dst_port = filter->dst_port;
6297                 break;
6298         case 0:
6299                 filter_info->dst_port_mask = 1;
6300                 break;
6301         default:
6302                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6303                 return -EINVAL;
6304         }
6305
6306         switch (filter->src_port_mask) {
6307         case UINT16_MAX:
6308                 filter_info->src_port_mask = 0;
6309                 filter_info->src_port = filter->src_port;
6310                 break;
6311         case 0:
6312                 filter_info->src_port_mask = 1;
6313                 break;
6314         default:
6315                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6316                 return -EINVAL;
6317         }
6318
6319         switch (filter->proto_mask) {
6320         case UINT8_MAX:
6321                 filter_info->proto_mask = 0;
6322                 filter_info->proto =
6323                         convert_protocol_type(filter->proto);
6324                 break;
6325         case 0:
6326                 filter_info->proto_mask = 1;
6327                 break;
6328         default:
6329                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6330                 return -EINVAL;
6331         }
6332
6333         filter_info->priority = (uint8_t)filter->priority;
6334         return 0;
6335 }
6336
6337 /*
6338  * add or delete a ntuple filter
6339  *
6340  * @param
6341  * dev: Pointer to struct rte_eth_dev.
6342  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6343  * add: if true, add filter, if false, remove filter
6344  *
6345  * @return
6346  *    - On success, zero.
6347  *    - On failure, a negative value.
6348  */
6349 int
6350 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6351                         struct rte_eth_ntuple_filter *ntuple_filter,
6352                         bool add)
6353 {
6354         struct ixgbe_filter_info *filter_info =
6355                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6356         struct ixgbe_5tuple_filter_info filter_5tuple;
6357         struct ixgbe_5tuple_filter *filter;
6358         int ret;
6359
6360         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6361                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6362                 return -EINVAL;
6363         }
6364
6365         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6366         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6367         if (ret < 0)
6368                 return ret;
6369
6370         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6371                                          &filter_5tuple);
6372         if (filter != NULL && add) {
6373                 PMD_DRV_LOG(ERR, "filter exists.");
6374                 return -EEXIST;
6375         }
6376         if (filter == NULL && !add) {
6377                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6378                 return -ENOENT;
6379         }
6380
6381         if (add) {
6382                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6383                                 sizeof(struct ixgbe_5tuple_filter), 0);
6384                 if (filter == NULL)
6385                         return -ENOMEM;
6386                 (void)rte_memcpy(&filter->filter_info,
6387                                  &filter_5tuple,
6388                                  sizeof(struct ixgbe_5tuple_filter_info));
6389                 filter->queue = ntuple_filter->queue;
6390                 ret = ixgbe_add_5tuple_filter(dev, filter);
6391                 if (ret < 0) {
6392                         rte_free(filter);
6393                         return ret;
6394                 }
6395         } else
6396                 ixgbe_remove_5tuple_filter(dev, filter);
6397
6398         return 0;
6399 }
6400
6401 /*
6402  * get a ntuple filter
6403  *
6404  * @param
6405  * dev: Pointer to struct rte_eth_dev.
6406  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6407  *
6408  * @return
6409  *    - On success, zero.
6410  *    - On failure, a negative value.
6411  */
6412 static int
6413 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6414                         struct rte_eth_ntuple_filter *ntuple_filter)
6415 {
6416         struct ixgbe_filter_info *filter_info =
6417                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6418         struct ixgbe_5tuple_filter_info filter_5tuple;
6419         struct ixgbe_5tuple_filter *filter;
6420         int ret;
6421
6422         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6423                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6424                 return -EINVAL;
6425         }
6426
6427         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6428         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6429         if (ret < 0)
6430                 return ret;
6431
6432         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6433                                          &filter_5tuple);
6434         if (filter == NULL) {
6435                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6436                 return -ENOENT;
6437         }
6438         ntuple_filter->queue = filter->queue;
6439         return 0;
6440 }
6441
6442 /*
6443  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6444  * @dev: pointer to rte_eth_dev structure
6445  * @filter_op:operation will be taken.
6446  * @arg: a pointer to specific structure corresponding to the filter_op
6447  *
6448  * @return
6449  *    - On success, zero.
6450  *    - On failure, a negative value.
6451  */
6452 static int
6453 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6454                                 enum rte_filter_op filter_op,
6455                                 void *arg)
6456 {
6457         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6458         int ret;
6459
6460         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6461
6462         if (filter_op == RTE_ETH_FILTER_NOP)
6463                 return 0;
6464
6465         if (arg == NULL) {
6466                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6467                             filter_op);
6468                 return -EINVAL;
6469         }
6470
6471         switch (filter_op) {
6472         case RTE_ETH_FILTER_ADD:
6473                 ret = ixgbe_add_del_ntuple_filter(dev,
6474                         (struct rte_eth_ntuple_filter *)arg,
6475                         TRUE);
6476                 break;
6477         case RTE_ETH_FILTER_DELETE:
6478                 ret = ixgbe_add_del_ntuple_filter(dev,
6479                         (struct rte_eth_ntuple_filter *)arg,
6480                         FALSE);
6481                 break;
6482         case RTE_ETH_FILTER_GET:
6483                 ret = ixgbe_get_ntuple_filter(dev,
6484                         (struct rte_eth_ntuple_filter *)arg);
6485                 break;
6486         default:
6487                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6488                 ret = -EINVAL;
6489                 break;
6490         }
6491         return ret;
6492 }
6493
6494 int
6495 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6496                         struct rte_eth_ethertype_filter *filter,
6497                         bool add)
6498 {
6499         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6500         struct ixgbe_filter_info *filter_info =
6501                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6502         uint32_t etqf = 0;
6503         uint32_t etqs = 0;
6504         int ret;
6505         struct ixgbe_ethertype_filter ethertype_filter;
6506
6507         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6508                 return -EINVAL;
6509
6510         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6511                 filter->ether_type == ETHER_TYPE_IPv6) {
6512                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6513                         " ethertype filter.", filter->ether_type);
6514                 return -EINVAL;
6515         }
6516
6517         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6518                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6519                 return -EINVAL;
6520         }
6521         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6522                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6523                 return -EINVAL;
6524         }
6525
6526         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6527         if (ret >= 0 && add) {
6528                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6529                             filter->ether_type);
6530                 return -EEXIST;
6531         }
6532         if (ret < 0 && !add) {
6533                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6534                             filter->ether_type);
6535                 return -ENOENT;
6536         }
6537
6538         if (add) {
6539                 etqf = IXGBE_ETQF_FILTER_EN;
6540                 etqf |= (uint32_t)filter->ether_type;
6541                 etqs |= (uint32_t)((filter->queue <<
6542                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6543                                     IXGBE_ETQS_RX_QUEUE);
6544                 etqs |= IXGBE_ETQS_QUEUE_EN;
6545
6546                 ethertype_filter.ethertype = filter->ether_type;
6547                 ethertype_filter.etqf = etqf;
6548                 ethertype_filter.etqs = etqs;
6549                 ethertype_filter.conf = FALSE;
6550                 ret = ixgbe_ethertype_filter_insert(filter_info,
6551                                                     &ethertype_filter);
6552                 if (ret < 0) {
6553                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6554                         return -ENOSPC;
6555                 }
6556         } else {
6557                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6558                 if (ret < 0)
6559                         return -ENOSYS;
6560         }
6561         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6562         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6563         IXGBE_WRITE_FLUSH(hw);
6564
6565         return 0;
6566 }
6567
6568 static int
6569 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6570                         struct rte_eth_ethertype_filter *filter)
6571 {
6572         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6573         struct ixgbe_filter_info *filter_info =
6574                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6575         uint32_t etqf, etqs;
6576         int ret;
6577
6578         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6579         if (ret < 0) {
6580                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6581                             filter->ether_type);
6582                 return -ENOENT;
6583         }
6584
6585         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6586         if (etqf & IXGBE_ETQF_FILTER_EN) {
6587                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6588                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6589                 filter->flags = 0;
6590                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6591                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6592                 return 0;
6593         }
6594         return -ENOENT;
6595 }
6596
6597 /*
6598  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6599  * @dev: pointer to rte_eth_dev structure
6600  * @filter_op:operation will be taken.
6601  * @arg: a pointer to specific structure corresponding to the filter_op
6602  */
6603 static int
6604 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6605                                 enum rte_filter_op filter_op,
6606                                 void *arg)
6607 {
6608         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6609         int ret;
6610
6611         MAC_TYPE_FILTER_SUP(hw->mac.type);
6612
6613         if (filter_op == RTE_ETH_FILTER_NOP)
6614                 return 0;
6615
6616         if (arg == NULL) {
6617                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6618                             filter_op);
6619                 return -EINVAL;
6620         }
6621
6622         switch (filter_op) {
6623         case RTE_ETH_FILTER_ADD:
6624                 ret = ixgbe_add_del_ethertype_filter(dev,
6625                         (struct rte_eth_ethertype_filter *)arg,
6626                         TRUE);
6627                 break;
6628         case RTE_ETH_FILTER_DELETE:
6629                 ret = ixgbe_add_del_ethertype_filter(dev,
6630                         (struct rte_eth_ethertype_filter *)arg,
6631                         FALSE);
6632                 break;
6633         case RTE_ETH_FILTER_GET:
6634                 ret = ixgbe_get_ethertype_filter(dev,
6635                         (struct rte_eth_ethertype_filter *)arg);
6636                 break;
6637         default:
6638                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6639                 ret = -EINVAL;
6640                 break;
6641         }
6642         return ret;
6643 }
6644
6645 static int
6646 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6647                      enum rte_filter_type filter_type,
6648                      enum rte_filter_op filter_op,
6649                      void *arg)
6650 {
6651         int ret = 0;
6652
6653         switch (filter_type) {
6654         case RTE_ETH_FILTER_NTUPLE:
6655                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6656                 break;
6657         case RTE_ETH_FILTER_ETHERTYPE:
6658                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6659                 break;
6660         case RTE_ETH_FILTER_SYN:
6661                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6662                 break;
6663         case RTE_ETH_FILTER_FDIR:
6664                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6665                 break;
6666         case RTE_ETH_FILTER_L2_TUNNEL:
6667                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6668                 break;
6669         case RTE_ETH_FILTER_GENERIC:
6670                 if (filter_op != RTE_ETH_FILTER_GET)
6671                         return -EINVAL;
6672                 *(const void **)arg = &ixgbe_flow_ops;
6673                 break;
6674         default:
6675                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6676                                                         filter_type);
6677                 ret = -EINVAL;
6678                 break;
6679         }
6680
6681         return ret;
6682 }
6683
6684 static u8 *
6685 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6686                         u8 **mc_addr_ptr, u32 *vmdq)
6687 {
6688         u8 *mc_addr;
6689
6690         *vmdq = 0;
6691         mc_addr = *mc_addr_ptr;
6692         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6693         return mc_addr;
6694 }
6695
6696 static int
6697 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6698                           struct ether_addr *mc_addr_set,
6699                           uint32_t nb_mc_addr)
6700 {
6701         struct ixgbe_hw *hw;
6702         u8 *mc_addr_list;
6703
6704         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6705         mc_addr_list = (u8 *)mc_addr_set;
6706         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6707                                          ixgbe_dev_addr_list_itr, TRUE);
6708 }
6709
6710 static uint64_t
6711 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6712 {
6713         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6714         uint64_t systime_cycles;
6715
6716         switch (hw->mac.type) {
6717         case ixgbe_mac_X550:
6718         case ixgbe_mac_X550EM_x:
6719         case ixgbe_mac_X550EM_a:
6720                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6721                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6722                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6723                                 * NSEC_PER_SEC;
6724                 break;
6725         default:
6726                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6727                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6728                                 << 32;
6729         }
6730
6731         return systime_cycles;
6732 }
6733
6734 static uint64_t
6735 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6736 {
6737         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6738         uint64_t rx_tstamp_cycles;
6739
6740         switch (hw->mac.type) {
6741         case ixgbe_mac_X550:
6742         case ixgbe_mac_X550EM_x:
6743         case ixgbe_mac_X550EM_a:
6744                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6745                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6746                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6747                                 * NSEC_PER_SEC;
6748                 break;
6749         default:
6750                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6751                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6752                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6753                                 << 32;
6754         }
6755
6756         return rx_tstamp_cycles;
6757 }
6758
6759 static uint64_t
6760 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6761 {
6762         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6763         uint64_t tx_tstamp_cycles;
6764
6765         switch (hw->mac.type) {
6766         case ixgbe_mac_X550:
6767         case ixgbe_mac_X550EM_x:
6768         case ixgbe_mac_X550EM_a:
6769                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6770                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6771                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6772                                 * NSEC_PER_SEC;
6773                 break;
6774         default:
6775                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6776                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6777                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6778                                 << 32;
6779         }
6780
6781         return tx_tstamp_cycles;
6782 }
6783
6784 static void
6785 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6786 {
6787         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6788         struct ixgbe_adapter *adapter =
6789                 (struct ixgbe_adapter *)dev->data->dev_private;
6790         struct rte_eth_link link;
6791         uint32_t incval = 0;
6792         uint32_t shift = 0;
6793
6794         /* Get current link speed. */
6795         memset(&link, 0, sizeof(link));
6796         ixgbe_dev_link_update(dev, 1);
6797         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6798
6799         switch (link.link_speed) {
6800         case ETH_SPEED_NUM_100M:
6801                 incval = IXGBE_INCVAL_100;
6802                 shift = IXGBE_INCVAL_SHIFT_100;
6803                 break;
6804         case ETH_SPEED_NUM_1G:
6805                 incval = IXGBE_INCVAL_1GB;
6806                 shift = IXGBE_INCVAL_SHIFT_1GB;
6807                 break;
6808         case ETH_SPEED_NUM_10G:
6809         default:
6810                 incval = IXGBE_INCVAL_10GB;
6811                 shift = IXGBE_INCVAL_SHIFT_10GB;
6812                 break;
6813         }
6814
6815         switch (hw->mac.type) {
6816         case ixgbe_mac_X550:
6817         case ixgbe_mac_X550EM_x:
6818         case ixgbe_mac_X550EM_a:
6819                 /* Independent of link speed. */
6820                 incval = 1;
6821                 /* Cycles read will be interpreted as ns. */
6822                 shift = 0;
6823                 /* Fall-through */
6824         case ixgbe_mac_X540:
6825                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6826                 break;
6827         case ixgbe_mac_82599EB:
6828                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6829                 shift -= IXGBE_INCVAL_SHIFT_82599;
6830                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6831                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6832                 break;
6833         default:
6834                 /* Not supported. */
6835                 return;
6836         }
6837
6838         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6839         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6840         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6841
6842         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6843         adapter->systime_tc.cc_shift = shift;
6844         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6845
6846         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6847         adapter->rx_tstamp_tc.cc_shift = shift;
6848         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6849
6850         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6851         adapter->tx_tstamp_tc.cc_shift = shift;
6852         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6853 }
6854
6855 static int
6856 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6857 {
6858         struct ixgbe_adapter *adapter =
6859                         (struct ixgbe_adapter *)dev->data->dev_private;
6860
6861         adapter->systime_tc.nsec += delta;
6862         adapter->rx_tstamp_tc.nsec += delta;
6863         adapter->tx_tstamp_tc.nsec += delta;
6864
6865         return 0;
6866 }
6867
6868 static int
6869 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6870 {
6871         uint64_t ns;
6872         struct ixgbe_adapter *adapter =
6873                         (struct ixgbe_adapter *)dev->data->dev_private;
6874
6875         ns = rte_timespec_to_ns(ts);
6876         /* Set the timecounters to a new value. */
6877         adapter->systime_tc.nsec = ns;
6878         adapter->rx_tstamp_tc.nsec = ns;
6879         adapter->tx_tstamp_tc.nsec = ns;
6880
6881         return 0;
6882 }
6883
6884 static int
6885 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6886 {
6887         uint64_t ns, systime_cycles;
6888         struct ixgbe_adapter *adapter =
6889                         (struct ixgbe_adapter *)dev->data->dev_private;
6890
6891         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6892         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6893         *ts = rte_ns_to_timespec(ns);
6894
6895         return 0;
6896 }
6897
6898 static int
6899 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6900 {
6901         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6902         uint32_t tsync_ctl;
6903         uint32_t tsauxc;
6904
6905         /* Stop the timesync system time. */
6906         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6907         /* Reset the timesync system time value. */
6908         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6909         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6910
6911         /* Enable system time for platforms where it isn't on by default. */
6912         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6913         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6914         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6915
6916         ixgbe_start_timecounters(dev);
6917
6918         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6919         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6920                         (ETHER_TYPE_1588 |
6921                          IXGBE_ETQF_FILTER_EN |
6922                          IXGBE_ETQF_1588));
6923
6924         /* Enable timestamping of received PTP packets. */
6925         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6926         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6927         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6928
6929         /* Enable timestamping of transmitted PTP packets. */
6930         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6931         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6932         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6933
6934         IXGBE_WRITE_FLUSH(hw);
6935
6936         return 0;
6937 }
6938
6939 static int
6940 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6941 {
6942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6943         uint32_t tsync_ctl;
6944
6945         /* Disable timestamping of transmitted PTP packets. */
6946         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6947         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6948         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6949
6950         /* Disable timestamping of received PTP packets. */
6951         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6952         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6953         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6954
6955         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6956         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6957
6958         /* Stop incrementating the System Time registers. */
6959         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6960
6961         return 0;
6962 }
6963
6964 static int
6965 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6966                                  struct timespec *timestamp,
6967                                  uint32_t flags __rte_unused)
6968 {
6969         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6970         struct ixgbe_adapter *adapter =
6971                 (struct ixgbe_adapter *)dev->data->dev_private;
6972         uint32_t tsync_rxctl;
6973         uint64_t rx_tstamp_cycles;
6974         uint64_t ns;
6975
6976         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6977         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6978                 return -EINVAL;
6979
6980         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6981         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6982         *timestamp = rte_ns_to_timespec(ns);
6983
6984         return  0;
6985 }
6986
6987 static int
6988 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6989                                  struct timespec *timestamp)
6990 {
6991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6992         struct ixgbe_adapter *adapter =
6993                 (struct ixgbe_adapter *)dev->data->dev_private;
6994         uint32_t tsync_txctl;
6995         uint64_t tx_tstamp_cycles;
6996         uint64_t ns;
6997
6998         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6999         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7000                 return -EINVAL;
7001
7002         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7003         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7004         *timestamp = rte_ns_to_timespec(ns);
7005
7006         return 0;
7007 }
7008
7009 static int
7010 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7011 {
7012         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7013         int count = 0;
7014         int g_ind = 0;
7015         const struct reg_info *reg_group;
7016         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7017                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7018
7019         while ((reg_group = reg_set[g_ind++]))
7020                 count += ixgbe_regs_group_count(reg_group);
7021
7022         return count;
7023 }
7024
7025 static int
7026 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7027 {
7028         int count = 0;
7029         int g_ind = 0;
7030         const struct reg_info *reg_group;
7031
7032         while ((reg_group = ixgbevf_regs[g_ind++]))
7033                 count += ixgbe_regs_group_count(reg_group);
7034
7035         return count;
7036 }
7037
7038 static int
7039 ixgbe_get_regs(struct rte_eth_dev *dev,
7040               struct rte_dev_reg_info *regs)
7041 {
7042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7043         uint32_t *data = regs->data;
7044         int g_ind = 0;
7045         int count = 0;
7046         const struct reg_info *reg_group;
7047         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7048                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7049
7050         if (data == NULL) {
7051                 regs->length = ixgbe_get_reg_length(dev);
7052                 regs->width = sizeof(uint32_t);
7053                 return 0;
7054         }
7055
7056         /* Support only full register dump */
7057         if ((regs->length == 0) ||
7058             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7059                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7060                         hw->device_id;
7061                 while ((reg_group = reg_set[g_ind++]))
7062                         count += ixgbe_read_regs_group(dev, &data[count],
7063                                 reg_group);
7064                 return 0;
7065         }
7066
7067         return -ENOTSUP;
7068 }
7069
7070 static int
7071 ixgbevf_get_regs(struct rte_eth_dev *dev,
7072                 struct rte_dev_reg_info *regs)
7073 {
7074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7075         uint32_t *data = regs->data;
7076         int g_ind = 0;
7077         int count = 0;
7078         const struct reg_info *reg_group;
7079
7080         if (data == NULL) {
7081                 regs->length = ixgbevf_get_reg_length(dev);
7082                 regs->width = sizeof(uint32_t);
7083                 return 0;
7084         }
7085
7086         /* Support only full register dump */
7087         if ((regs->length == 0) ||
7088             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7089                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7090                         hw->device_id;
7091                 while ((reg_group = ixgbevf_regs[g_ind++]))
7092                         count += ixgbe_read_regs_group(dev, &data[count],
7093                                                       reg_group);
7094                 return 0;
7095         }
7096
7097         return -ENOTSUP;
7098 }
7099
7100 static int
7101 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7102 {
7103         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7104
7105         /* Return unit is byte count */
7106         return hw->eeprom.word_size * 2;
7107 }
7108
7109 static int
7110 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7111                 struct rte_dev_eeprom_info *in_eeprom)
7112 {
7113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7114         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7115         uint16_t *data = in_eeprom->data;
7116         int first, length;
7117
7118         first = in_eeprom->offset >> 1;
7119         length = in_eeprom->length >> 1;
7120         if ((first > hw->eeprom.word_size) ||
7121             ((first + length) > hw->eeprom.word_size))
7122                 return -EINVAL;
7123
7124         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7125
7126         return eeprom->ops.read_buffer(hw, first, length, data);
7127 }
7128
7129 static int
7130 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7131                 struct rte_dev_eeprom_info *in_eeprom)
7132 {
7133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7134         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7135         uint16_t *data = in_eeprom->data;
7136         int first, length;
7137
7138         first = in_eeprom->offset >> 1;
7139         length = in_eeprom->length >> 1;
7140         if ((first > hw->eeprom.word_size) ||
7141             ((first + length) > hw->eeprom.word_size))
7142                 return -EINVAL;
7143
7144         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7145
7146         return eeprom->ops.write_buffer(hw,  first, length, data);
7147 }
7148
7149 uint16_t
7150 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7151         switch (mac_type) {
7152         case ixgbe_mac_X550:
7153         case ixgbe_mac_X550EM_x:
7154         case ixgbe_mac_X550EM_a:
7155                 return ETH_RSS_RETA_SIZE_512;
7156         case ixgbe_mac_X550_vf:
7157         case ixgbe_mac_X550EM_x_vf:
7158         case ixgbe_mac_X550EM_a_vf:
7159                 return ETH_RSS_RETA_SIZE_64;
7160         default:
7161                 return ETH_RSS_RETA_SIZE_128;
7162         }
7163 }
7164
7165 uint32_t
7166 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7167         switch (mac_type) {
7168         case ixgbe_mac_X550:
7169         case ixgbe_mac_X550EM_x:
7170         case ixgbe_mac_X550EM_a:
7171                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7172                         return IXGBE_RETA(reta_idx >> 2);
7173                 else
7174                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7175         case ixgbe_mac_X550_vf:
7176         case ixgbe_mac_X550EM_x_vf:
7177         case ixgbe_mac_X550EM_a_vf:
7178                 return IXGBE_VFRETA(reta_idx >> 2);
7179         default:
7180                 return IXGBE_RETA(reta_idx >> 2);
7181         }
7182 }
7183
7184 uint32_t
7185 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7186         switch (mac_type) {
7187         case ixgbe_mac_X550_vf:
7188         case ixgbe_mac_X550EM_x_vf:
7189         case ixgbe_mac_X550EM_a_vf:
7190                 return IXGBE_VFMRQC;
7191         default:
7192                 return IXGBE_MRQC;
7193         }
7194 }
7195
7196 uint32_t
7197 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7198         switch (mac_type) {
7199         case ixgbe_mac_X550_vf:
7200         case ixgbe_mac_X550EM_x_vf:
7201         case ixgbe_mac_X550EM_a_vf:
7202                 return IXGBE_VFRSSRK(i);
7203         default:
7204                 return IXGBE_RSSRK(i);
7205         }
7206 }
7207
7208 bool
7209 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7210         switch (mac_type) {
7211         case ixgbe_mac_82599_vf:
7212         case ixgbe_mac_X540_vf:
7213                 return 0;
7214         default:
7215                 return 1;
7216         }
7217 }
7218
7219 static int
7220 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7221                         struct rte_eth_dcb_info *dcb_info)
7222 {
7223         struct ixgbe_dcb_config *dcb_config =
7224                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7225         struct ixgbe_dcb_tc_config *tc;
7226         uint8_t i, j;
7227
7228         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7229                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7230         else
7231                 dcb_info->nb_tcs = 1;
7232
7233         if (dcb_config->vt_mode) { /* vt is enabled*/
7234                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7235                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7236                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7237                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7238                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7239                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7240                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7241                                                 i * dcb_info->nb_tcs + j;
7242                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7243                                 dcb_info->tc_queue.tc_txq[i][j].base =
7244                                                 i * dcb_info->nb_tcs + j;
7245                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7246                         }
7247                 }
7248         } else { /* vt is disabled*/
7249                 struct rte_eth_dcb_rx_conf *rx_conf =
7250                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7251                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7252                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7253                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7254                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7255                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7256                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7257                         }
7258                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7259                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7260                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7261                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7262                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7263                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7264                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7265                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7266                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7267                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7268                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7269                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7270                         }
7271                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7272                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7273                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7274                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7275                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7276                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7277                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7278                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7279                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7280                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7281                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7282                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7283                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7284                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7285                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7286                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7287                 }
7288         }
7289         for (i = 0; i < dcb_info->nb_tcs; i++) {
7290                 tc = &dcb_config->tc_config[i];
7291                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7292         }
7293         return 0;
7294 }
7295
7296 /* Update e-tag ether type */
7297 static int
7298 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7299                             uint16_t ether_type)
7300 {
7301         uint32_t etag_etype;
7302
7303         if (hw->mac.type != ixgbe_mac_X550 &&
7304             hw->mac.type != ixgbe_mac_X550EM_x &&
7305             hw->mac.type != ixgbe_mac_X550EM_a) {
7306                 return -ENOTSUP;
7307         }
7308
7309         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7310         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7311         etag_etype |= ether_type;
7312         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7313         IXGBE_WRITE_FLUSH(hw);
7314
7315         return 0;
7316 }
7317
7318 /* Config l2 tunnel ether type */
7319 static int
7320 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7321                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7322 {
7323         int ret = 0;
7324         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7325         struct ixgbe_l2_tn_info *l2_tn_info =
7326                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7327
7328         if (l2_tunnel == NULL)
7329                 return -EINVAL;
7330
7331         switch (l2_tunnel->l2_tunnel_type) {
7332         case RTE_L2_TUNNEL_TYPE_E_TAG:
7333                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7334                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7335                 break;
7336         default:
7337                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7338                 ret = -EINVAL;
7339                 break;
7340         }
7341
7342         return ret;
7343 }
7344
7345 /* Enable e-tag tunnel */
7346 static int
7347 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7348 {
7349         uint32_t etag_etype;
7350
7351         if (hw->mac.type != ixgbe_mac_X550 &&
7352             hw->mac.type != ixgbe_mac_X550EM_x &&
7353             hw->mac.type != ixgbe_mac_X550EM_a) {
7354                 return -ENOTSUP;
7355         }
7356
7357         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7358         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7359         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7360         IXGBE_WRITE_FLUSH(hw);
7361
7362         return 0;
7363 }
7364
7365 /* Enable l2 tunnel */
7366 static int
7367 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7368                            enum rte_eth_tunnel_type l2_tunnel_type)
7369 {
7370         int ret = 0;
7371         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7372         struct ixgbe_l2_tn_info *l2_tn_info =
7373                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7374
7375         switch (l2_tunnel_type) {
7376         case RTE_L2_TUNNEL_TYPE_E_TAG:
7377                 l2_tn_info->e_tag_en = TRUE;
7378                 ret = ixgbe_e_tag_enable(hw);
7379                 break;
7380         default:
7381                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7382                 ret = -EINVAL;
7383                 break;
7384         }
7385
7386         return ret;
7387 }
7388
7389 /* Disable e-tag tunnel */
7390 static int
7391 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7392 {
7393         uint32_t etag_etype;
7394
7395         if (hw->mac.type != ixgbe_mac_X550 &&
7396             hw->mac.type != ixgbe_mac_X550EM_x &&
7397             hw->mac.type != ixgbe_mac_X550EM_a) {
7398                 return -ENOTSUP;
7399         }
7400
7401         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7402         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7403         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7404         IXGBE_WRITE_FLUSH(hw);
7405
7406         return 0;
7407 }
7408
7409 /* Disable l2 tunnel */
7410 static int
7411 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7412                             enum rte_eth_tunnel_type l2_tunnel_type)
7413 {
7414         int ret = 0;
7415         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7416         struct ixgbe_l2_tn_info *l2_tn_info =
7417                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7418
7419         switch (l2_tunnel_type) {
7420         case RTE_L2_TUNNEL_TYPE_E_TAG:
7421                 l2_tn_info->e_tag_en = FALSE;
7422                 ret = ixgbe_e_tag_disable(hw);
7423                 break;
7424         default:
7425                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7426                 ret = -EINVAL;
7427                 break;
7428         }
7429
7430         return ret;
7431 }
7432
7433 static int
7434 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7435                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7436 {
7437         int ret = 0;
7438         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7439         uint32_t i, rar_entries;
7440         uint32_t rar_low, rar_high;
7441
7442         if (hw->mac.type != ixgbe_mac_X550 &&
7443             hw->mac.type != ixgbe_mac_X550EM_x &&
7444             hw->mac.type != ixgbe_mac_X550EM_a) {
7445                 return -ENOTSUP;
7446         }
7447
7448         rar_entries = ixgbe_get_num_rx_addrs(hw);
7449
7450         for (i = 1; i < rar_entries; i++) {
7451                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7452                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7453                 if ((rar_high & IXGBE_RAH_AV) &&
7454                     (rar_high & IXGBE_RAH_ADTYPE) &&
7455                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7456                      l2_tunnel->tunnel_id)) {
7457                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7458                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7459
7460                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7461
7462                         return ret;
7463                 }
7464         }
7465
7466         return ret;
7467 }
7468
7469 static int
7470 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7471                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7472 {
7473         int ret = 0;
7474         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7475         uint32_t i, rar_entries;
7476         uint32_t rar_low, rar_high;
7477
7478         if (hw->mac.type != ixgbe_mac_X550 &&
7479             hw->mac.type != ixgbe_mac_X550EM_x &&
7480             hw->mac.type != ixgbe_mac_X550EM_a) {
7481                 return -ENOTSUP;
7482         }
7483
7484         /* One entry for one tunnel. Try to remove potential existing entry. */
7485         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7486
7487         rar_entries = ixgbe_get_num_rx_addrs(hw);
7488
7489         for (i = 1; i < rar_entries; i++) {
7490                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7491                 if (rar_high & IXGBE_RAH_AV) {
7492                         continue;
7493                 } else {
7494                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7495                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7496                         rar_low = l2_tunnel->tunnel_id;
7497
7498                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7499                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7500
7501                         return ret;
7502                 }
7503         }
7504
7505         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7506                      " Please remove a rule before adding a new one.");
7507         return -EINVAL;
7508 }
7509
7510 static inline struct ixgbe_l2_tn_filter *
7511 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7512                           struct ixgbe_l2_tn_key *key)
7513 {
7514         int ret;
7515
7516         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7517         if (ret < 0)
7518                 return NULL;
7519
7520         return l2_tn_info->hash_map[ret];
7521 }
7522
7523 static inline int
7524 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7525                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7526 {
7527         int ret;
7528
7529         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7530                                &l2_tn_filter->key);
7531
7532         if (ret < 0) {
7533                 PMD_DRV_LOG(ERR,
7534                             "Failed to insert L2 tunnel filter"
7535                             " to hash table %d!",
7536                             ret);
7537                 return ret;
7538         }
7539
7540         l2_tn_info->hash_map[ret] = l2_tn_filter;
7541
7542         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7543
7544         return 0;
7545 }
7546
7547 static inline int
7548 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7549                           struct ixgbe_l2_tn_key *key)
7550 {
7551         int ret;
7552         struct ixgbe_l2_tn_filter *l2_tn_filter;
7553
7554         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7555
7556         if (ret < 0) {
7557                 PMD_DRV_LOG(ERR,
7558                             "No such L2 tunnel filter to delete %d!",
7559                             ret);
7560                 return ret;
7561         }
7562
7563         l2_tn_filter = l2_tn_info->hash_map[ret];
7564         l2_tn_info->hash_map[ret] = NULL;
7565
7566         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7567         rte_free(l2_tn_filter);
7568
7569         return 0;
7570 }
7571
7572 /* Add l2 tunnel filter */
7573 int
7574 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7575                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7576                                bool restore)
7577 {
7578         int ret;
7579         struct ixgbe_l2_tn_info *l2_tn_info =
7580                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7581         struct ixgbe_l2_tn_key key;
7582         struct ixgbe_l2_tn_filter *node;
7583
7584         if (!restore) {
7585                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7586                 key.tn_id = l2_tunnel->tunnel_id;
7587
7588                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7589
7590                 if (node) {
7591                         PMD_DRV_LOG(ERR,
7592                                     "The L2 tunnel filter already exists!");
7593                         return -EINVAL;
7594                 }
7595
7596                 node = rte_zmalloc("ixgbe_l2_tn",
7597                                    sizeof(struct ixgbe_l2_tn_filter),
7598                                    0);
7599                 if (!node)
7600                         return -ENOMEM;
7601
7602                 (void)rte_memcpy(&node->key,
7603                                  &key,
7604                                  sizeof(struct ixgbe_l2_tn_key));
7605                 node->pool = l2_tunnel->pool;
7606                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7607                 if (ret < 0) {
7608                         rte_free(node);
7609                         return ret;
7610                 }
7611         }
7612
7613         switch (l2_tunnel->l2_tunnel_type) {
7614         case RTE_L2_TUNNEL_TYPE_E_TAG:
7615                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7616                 break;
7617         default:
7618                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7619                 ret = -EINVAL;
7620                 break;
7621         }
7622
7623         if ((!restore) && (ret < 0))
7624                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7625
7626         return ret;
7627 }
7628
7629 /* Delete l2 tunnel filter */
7630 int
7631 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7632                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7633 {
7634         int ret;
7635         struct ixgbe_l2_tn_info *l2_tn_info =
7636                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7637         struct ixgbe_l2_tn_key key;
7638
7639         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7640         key.tn_id = l2_tunnel->tunnel_id;
7641         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7642         if (ret < 0)
7643                 return ret;
7644
7645         switch (l2_tunnel->l2_tunnel_type) {
7646         case RTE_L2_TUNNEL_TYPE_E_TAG:
7647                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7648                 break;
7649         default:
7650                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7651                 ret = -EINVAL;
7652                 break;
7653         }
7654
7655         return ret;
7656 }
7657
7658 /**
7659  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7660  * @dev: pointer to rte_eth_dev structure
7661  * @filter_op:operation will be taken.
7662  * @arg: a pointer to specific structure corresponding to the filter_op
7663  */
7664 static int
7665 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7666                                   enum rte_filter_op filter_op,
7667                                   void *arg)
7668 {
7669         int ret;
7670
7671         if (filter_op == RTE_ETH_FILTER_NOP)
7672                 return 0;
7673
7674         if (arg == NULL) {
7675                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7676                             filter_op);
7677                 return -EINVAL;
7678         }
7679
7680         switch (filter_op) {
7681         case RTE_ETH_FILTER_ADD:
7682                 ret = ixgbe_dev_l2_tunnel_filter_add
7683                         (dev,
7684                          (struct rte_eth_l2_tunnel_conf *)arg,
7685                          FALSE);
7686                 break;
7687         case RTE_ETH_FILTER_DELETE:
7688                 ret = ixgbe_dev_l2_tunnel_filter_del
7689                         (dev,
7690                          (struct rte_eth_l2_tunnel_conf *)arg);
7691                 break;
7692         default:
7693                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7694                 ret = -EINVAL;
7695                 break;
7696         }
7697         return ret;
7698 }
7699
7700 static int
7701 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7702 {
7703         int ret = 0;
7704         uint32_t ctrl;
7705         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7706
7707         if (hw->mac.type != ixgbe_mac_X550 &&
7708             hw->mac.type != ixgbe_mac_X550EM_x &&
7709             hw->mac.type != ixgbe_mac_X550EM_a) {
7710                 return -ENOTSUP;
7711         }
7712
7713         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7714         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7715         if (en)
7716                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7717         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7718
7719         return ret;
7720 }
7721
7722 /* Enable l2 tunnel forwarding */
7723 static int
7724 ixgbe_dev_l2_tunnel_forwarding_enable
7725         (struct rte_eth_dev *dev,
7726          enum rte_eth_tunnel_type l2_tunnel_type)
7727 {
7728         struct ixgbe_l2_tn_info *l2_tn_info =
7729                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7730         int ret = 0;
7731
7732         switch (l2_tunnel_type) {
7733         case RTE_L2_TUNNEL_TYPE_E_TAG:
7734                 l2_tn_info->e_tag_fwd_en = TRUE;
7735                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7736                 break;
7737         default:
7738                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7739                 ret = -EINVAL;
7740                 break;
7741         }
7742
7743         return ret;
7744 }
7745
7746 /* Disable l2 tunnel forwarding */
7747 static int
7748 ixgbe_dev_l2_tunnel_forwarding_disable
7749         (struct rte_eth_dev *dev,
7750          enum rte_eth_tunnel_type l2_tunnel_type)
7751 {
7752         struct ixgbe_l2_tn_info *l2_tn_info =
7753                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7754         int ret = 0;
7755
7756         switch (l2_tunnel_type) {
7757         case RTE_L2_TUNNEL_TYPE_E_TAG:
7758                 l2_tn_info->e_tag_fwd_en = FALSE;
7759                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7760                 break;
7761         default:
7762                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7763                 ret = -EINVAL;
7764                 break;
7765         }
7766
7767         return ret;
7768 }
7769
7770 static int
7771 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7772                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7773                              bool en)
7774 {
7775         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7776         int ret = 0;
7777         uint32_t vmtir, vmvir;
7778         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7779
7780         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7781                 PMD_DRV_LOG(ERR,
7782                             "VF id %u should be less than %u",
7783                             l2_tunnel->vf_id,
7784                             pci_dev->max_vfs);
7785                 return -EINVAL;
7786         }
7787
7788         if (hw->mac.type != ixgbe_mac_X550 &&
7789             hw->mac.type != ixgbe_mac_X550EM_x &&
7790             hw->mac.type != ixgbe_mac_X550EM_a) {
7791                 return -ENOTSUP;
7792         }
7793
7794         if (en)
7795                 vmtir = l2_tunnel->tunnel_id;
7796         else
7797                 vmtir = 0;
7798
7799         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7800
7801         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7802         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7803         if (en)
7804                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7805         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7806
7807         return ret;
7808 }
7809
7810 /* Enable l2 tunnel tag insertion */
7811 static int
7812 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7813                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7814 {
7815         int ret = 0;
7816
7817         switch (l2_tunnel->l2_tunnel_type) {
7818         case RTE_L2_TUNNEL_TYPE_E_TAG:
7819                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7820                 break;
7821         default:
7822                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7823                 ret = -EINVAL;
7824                 break;
7825         }
7826
7827         return ret;
7828 }
7829
7830 /* Disable l2 tunnel tag insertion */
7831 static int
7832 ixgbe_dev_l2_tunnel_insertion_disable
7833         (struct rte_eth_dev *dev,
7834          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7835 {
7836         int ret = 0;
7837
7838         switch (l2_tunnel->l2_tunnel_type) {
7839         case RTE_L2_TUNNEL_TYPE_E_TAG:
7840                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7841                 break;
7842         default:
7843                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7844                 ret = -EINVAL;
7845                 break;
7846         }
7847
7848         return ret;
7849 }
7850
7851 static int
7852 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7853                              bool en)
7854 {
7855         int ret = 0;
7856         uint32_t qde;
7857         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7858
7859         if (hw->mac.type != ixgbe_mac_X550 &&
7860             hw->mac.type != ixgbe_mac_X550EM_x &&
7861             hw->mac.type != ixgbe_mac_X550EM_a) {
7862                 return -ENOTSUP;
7863         }
7864
7865         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7866         if (en)
7867                 qde |= IXGBE_QDE_STRIP_TAG;
7868         else
7869                 qde &= ~IXGBE_QDE_STRIP_TAG;
7870         qde &= ~IXGBE_QDE_READ;
7871         qde |= IXGBE_QDE_WRITE;
7872         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7873
7874         return ret;
7875 }
7876
7877 /* Enable l2 tunnel tag stripping */
7878 static int
7879 ixgbe_dev_l2_tunnel_stripping_enable
7880         (struct rte_eth_dev *dev,
7881          enum rte_eth_tunnel_type l2_tunnel_type)
7882 {
7883         int ret = 0;
7884
7885         switch (l2_tunnel_type) {
7886         case RTE_L2_TUNNEL_TYPE_E_TAG:
7887                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7888                 break;
7889         default:
7890                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7891                 ret = -EINVAL;
7892                 break;
7893         }
7894
7895         return ret;
7896 }
7897
7898 /* Disable l2 tunnel tag stripping */
7899 static int
7900 ixgbe_dev_l2_tunnel_stripping_disable
7901         (struct rte_eth_dev *dev,
7902          enum rte_eth_tunnel_type l2_tunnel_type)
7903 {
7904         int ret = 0;
7905
7906         switch (l2_tunnel_type) {
7907         case RTE_L2_TUNNEL_TYPE_E_TAG:
7908                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7909                 break;
7910         default:
7911                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7912                 ret = -EINVAL;
7913                 break;
7914         }
7915
7916         return ret;
7917 }
7918
7919 /* Enable/disable l2 tunnel offload functions */
7920 static int
7921 ixgbe_dev_l2_tunnel_offload_set
7922         (struct rte_eth_dev *dev,
7923          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7924          uint32_t mask,
7925          uint8_t en)
7926 {
7927         int ret = 0;
7928
7929         if (l2_tunnel == NULL)
7930                 return -EINVAL;
7931
7932         ret = -EINVAL;
7933         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7934                 if (en)
7935                         ret = ixgbe_dev_l2_tunnel_enable(
7936                                 dev,
7937                                 l2_tunnel->l2_tunnel_type);
7938                 else
7939                         ret = ixgbe_dev_l2_tunnel_disable(
7940                                 dev,
7941                                 l2_tunnel->l2_tunnel_type);
7942         }
7943
7944         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7945                 if (en)
7946                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7947                                 dev,
7948                                 l2_tunnel);
7949                 else
7950                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7951                                 dev,
7952                                 l2_tunnel);
7953         }
7954
7955         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7956                 if (en)
7957                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7958                                 dev,
7959                                 l2_tunnel->l2_tunnel_type);
7960                 else
7961                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7962                                 dev,
7963                                 l2_tunnel->l2_tunnel_type);
7964         }
7965
7966         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7967                 if (en)
7968                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7969                                 dev,
7970                                 l2_tunnel->l2_tunnel_type);
7971                 else
7972                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7973                                 dev,
7974                                 l2_tunnel->l2_tunnel_type);
7975         }
7976
7977         return ret;
7978 }
7979
7980 static int
7981 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7982                         uint16_t port)
7983 {
7984         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7985         IXGBE_WRITE_FLUSH(hw);
7986
7987         return 0;
7988 }
7989
7990 /* There's only one register for VxLAN UDP port.
7991  * So, we cannot add several ports. Will update it.
7992  */
7993 static int
7994 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7995                      uint16_t port)
7996 {
7997         if (port == 0) {
7998                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7999                 return -EINVAL;
8000         }
8001
8002         return ixgbe_update_vxlan_port(hw, port);
8003 }
8004
8005 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8006  * UDP port, it must have a value.
8007  * So, will reset it to the original value 0.
8008  */
8009 static int
8010 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8011                      uint16_t port)
8012 {
8013         uint16_t cur_port;
8014
8015         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8016
8017         if (cur_port != port) {
8018                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8019                 return -EINVAL;
8020         }
8021
8022         return ixgbe_update_vxlan_port(hw, 0);
8023 }
8024
8025 /* Add UDP tunneling port */
8026 static int
8027 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8028                               struct rte_eth_udp_tunnel *udp_tunnel)
8029 {
8030         int ret = 0;
8031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8032
8033         if (hw->mac.type != ixgbe_mac_X550 &&
8034             hw->mac.type != ixgbe_mac_X550EM_x &&
8035             hw->mac.type != ixgbe_mac_X550EM_a) {
8036                 return -ENOTSUP;
8037         }
8038
8039         if (udp_tunnel == NULL)
8040                 return -EINVAL;
8041
8042         switch (udp_tunnel->prot_type) {
8043         case RTE_TUNNEL_TYPE_VXLAN:
8044                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8045                 break;
8046
8047         case RTE_TUNNEL_TYPE_GENEVE:
8048         case RTE_TUNNEL_TYPE_TEREDO:
8049                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8050                 ret = -EINVAL;
8051                 break;
8052
8053         default:
8054                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8055                 ret = -EINVAL;
8056                 break;
8057         }
8058
8059         return ret;
8060 }
8061
8062 /* Remove UDP tunneling port */
8063 static int
8064 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8065                               struct rte_eth_udp_tunnel *udp_tunnel)
8066 {
8067         int ret = 0;
8068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8069
8070         if (hw->mac.type != ixgbe_mac_X550 &&
8071             hw->mac.type != ixgbe_mac_X550EM_x &&
8072             hw->mac.type != ixgbe_mac_X550EM_a) {
8073                 return -ENOTSUP;
8074         }
8075
8076         if (udp_tunnel == NULL)
8077                 return -EINVAL;
8078
8079         switch (udp_tunnel->prot_type) {
8080         case RTE_TUNNEL_TYPE_VXLAN:
8081                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8082                 break;
8083         case RTE_TUNNEL_TYPE_GENEVE:
8084         case RTE_TUNNEL_TYPE_TEREDO:
8085                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8086                 ret = -EINVAL;
8087                 break;
8088         default:
8089                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8090                 ret = -EINVAL;
8091                 break;
8092         }
8093
8094         return ret;
8095 }
8096
8097 static void
8098 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8099 {
8100         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8101
8102         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8103 }
8104
8105 static void
8106 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8107 {
8108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8109
8110         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8111 }
8112
8113 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8114 {
8115         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8116         u32 in_msg = 0;
8117
8118         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8119                 return;
8120
8121         /* PF reset VF event */
8122         if (in_msg == IXGBE_PF_CONTROL_MSG)
8123                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8124 }
8125
8126 static int
8127 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8128 {
8129         uint32_t eicr;
8130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8131         struct ixgbe_interrupt *intr =
8132                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8133         ixgbevf_intr_disable(hw);
8134
8135         /* read-on-clear nic registers here */
8136         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8137         intr->flags = 0;
8138
8139         /* only one misc vector supported - mailbox */
8140         eicr &= IXGBE_VTEICR_MASK;
8141         if (eicr == IXGBE_MISC_VEC_ID)
8142                 intr->flags |= IXGBE_FLAG_MAILBOX;
8143
8144         return 0;
8145 }
8146
8147 static int
8148 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8149 {
8150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8151         struct ixgbe_interrupt *intr =
8152                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8153
8154         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8155                 ixgbevf_mbx_process(dev);
8156                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8157         }
8158
8159         ixgbevf_intr_enable(hw);
8160
8161         return 0;
8162 }
8163
8164 static void
8165 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8166                               void *param)
8167 {
8168         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8169
8170         ixgbevf_dev_interrupt_get_status(dev);
8171         ixgbevf_dev_interrupt_action(dev);
8172 }
8173
8174 /**
8175  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8176  *  @hw: pointer to hardware structure
8177  *
8178  *  Stops the transmit data path and waits for the HW to internally empty
8179  *  the Tx security block
8180  **/
8181 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8182 {
8183 #define IXGBE_MAX_SECTX_POLL 40
8184
8185         int i;
8186         int sectxreg;
8187
8188         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8189         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8190         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8191         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8192                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8193                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8194                         break;
8195                 /* Use interrupt-safe sleep just in case */
8196                 usec_delay(1000);
8197         }
8198
8199         /* For informational purposes only */
8200         if (i >= IXGBE_MAX_SECTX_POLL)
8201                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8202                          "path fully disabled.  Continuing with init.\n");
8203
8204         return IXGBE_SUCCESS;
8205 }
8206
8207 /**
8208  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8209  *  @hw: pointer to hardware structure
8210  *
8211  *  Enables the transmit data path.
8212  **/
8213 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8214 {
8215         uint32_t sectxreg;
8216
8217         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8218         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8219         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8220         IXGBE_WRITE_FLUSH(hw);
8221
8222         return IXGBE_SUCCESS;
8223 }
8224
8225 int
8226 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8227 {
8228         struct ixgbe_hw *hw;
8229         struct rte_eth_dev *dev;
8230         struct rte_eth_dev_info dev_info;
8231         uint32_t ctrl;
8232
8233         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8234
8235         rte_eth_dev_info_get(port, &dev_info);
8236         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
8237                 return -ENOTSUP;
8238
8239         dev = &rte_eth_devices[port];
8240         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8241
8242         /* Stop the data paths */
8243         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8244                 return -ENOTSUP;
8245         /*
8246          * Workaround:
8247          * As no ixgbe_disable_sec_rx_path equivalent is
8248          * implemented for tx in the base code, and we are
8249          * not allowed to modify the base code in DPDK, so
8250          * just call the hand-written one directly for now.
8251          * The hardware support has been checked by
8252          * ixgbe_disable_sec_rx_path().
8253          */
8254         ixgbe_disable_sec_tx_path_generic(hw);
8255
8256         /* Enable Ethernet CRC (required by MACsec offload) */
8257         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8258         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8259         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8260
8261         /* Enable the TX and RX crypto engines */
8262         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8263         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8264         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8265
8266         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8267         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8268         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8269
8270         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8271         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8272         ctrl |= 0x3;
8273         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8274
8275         /* Enable SA lookup */
8276         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8277         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8278         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8279                      IXGBE_LSECTXCTRL_AUTH;
8280         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8281         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8282         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8283         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8284
8285         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8286         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8287         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8288         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8289         if (rp)
8290                 ctrl |= IXGBE_LSECRXCTRL_RP;
8291         else
8292                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8293         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8294
8295         /* Start the data paths */
8296         ixgbe_enable_sec_rx_path(hw);
8297         /*
8298          * Workaround:
8299          * As no ixgbe_enable_sec_rx_path equivalent is
8300          * implemented for tx in the base code, and we are
8301          * not allowed to modify the base code in DPDK, so
8302          * just call the hand-written one directly for now.
8303          */
8304         ixgbe_enable_sec_tx_path_generic(hw);
8305
8306         return 0;
8307 }
8308
8309 int
8310 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8311 {
8312         struct ixgbe_hw *hw;
8313         struct rte_eth_dev *dev;
8314         struct rte_eth_dev_info dev_info;
8315         uint32_t ctrl;
8316
8317         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8318
8319         rte_eth_dev_info_get(port, &dev_info);
8320         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
8321                 return -ENOTSUP;
8322
8323         dev = &rte_eth_devices[port];
8324         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8325
8326         /* Stop the data paths */
8327         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8328                 return -ENOTSUP;
8329         /*
8330          * Workaround:
8331          * As no ixgbe_disable_sec_rx_path equivalent is
8332          * implemented for tx in the base code, and we are
8333          * not allowed to modify the base code in DPDK, so
8334          * just call the hand-written one directly for now.
8335          * The hardware support has been checked by
8336          * ixgbe_disable_sec_rx_path().
8337          */
8338         ixgbe_disable_sec_tx_path_generic(hw);
8339
8340         /* Disable the TX and RX crypto engines */
8341         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8342         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8343         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8344
8345         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8346         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8347         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8348
8349         /* Disable SA lookup */
8350         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8351         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8352         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8353         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8354
8355         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8356         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8357         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8358         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8359
8360         /* Start the data paths */
8361         ixgbe_enable_sec_rx_path(hw);
8362         /*
8363          * Workaround:
8364          * As no ixgbe_enable_sec_rx_path equivalent is
8365          * implemented for tx in the base code, and we are
8366          * not allowed to modify the base code in DPDK, so
8367          * just call the hand-written one directly for now.
8368          */
8369         ixgbe_enable_sec_tx_path_generic(hw);
8370
8371         return 0;
8372 }
8373
8374 int
8375 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8376 {
8377         struct ixgbe_hw *hw;
8378         struct rte_eth_dev *dev;
8379         struct rte_eth_dev_info dev_info;
8380         uint32_t ctrl;
8381
8382         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8383
8384         rte_eth_dev_info_get(port, &dev_info);
8385         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
8386                 return -ENOTSUP;
8387
8388         dev = &rte_eth_devices[port];
8389         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8390
8391         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8392         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8393
8394         ctrl = mac[4] | (mac[5] << 8);
8395         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8396
8397         return 0;
8398 }
8399
8400 int
8401 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8402 {
8403         struct ixgbe_hw *hw;
8404         struct rte_eth_dev *dev;
8405         struct rte_eth_dev_info dev_info;
8406         uint32_t ctrl;
8407
8408         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8409
8410         rte_eth_dev_info_get(port, &dev_info);
8411         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
8412                 return -ENOTSUP;
8413
8414         dev = &rte_eth_devices[port];
8415         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8416
8417         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8418         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8419
8420         pi = rte_cpu_to_be_16(pi);
8421         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8422         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8423
8424         return 0;
8425 }
8426
8427 int
8428 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8429                                  uint32_t pn, uint8_t *key)
8430 {
8431         struct ixgbe_hw *hw;
8432         struct rte_eth_dev *dev;
8433         struct rte_eth_dev_info dev_info;
8434         uint32_t ctrl, i;
8435
8436         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8437
8438         rte_eth_dev_info_get(port, &dev_info);
8439         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
8440                 return -ENOTSUP;
8441
8442         dev = &rte_eth_devices[port];
8443         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8444
8445         if (idx != 0 && idx != 1)
8446                 return -EINVAL;
8447
8448         if (an >= 4)
8449                 return -EINVAL;
8450
8451         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8452
8453         /* Set the PN and key */
8454         pn = rte_cpu_to_be_32(pn);
8455         if (idx == 0) {
8456                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8457
8458                 for (i = 0; i < 4; i++) {
8459                         ctrl = (key[i * 4 + 0] <<  0) |
8460                                (key[i * 4 + 1] <<  8) |
8461                                (key[i * 4 + 2] << 16) |
8462                                (key[i * 4 + 3] << 24);
8463                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8464                 }
8465         } else {
8466                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8467
8468                 for (i = 0; i < 4; i++) {
8469                         ctrl = (key[i * 4 + 0] <<  0) |
8470                                (key[i * 4 + 1] <<  8) |
8471                                (key[i * 4 + 2] << 16) |
8472                                (key[i * 4 + 3] << 24);
8473                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8474                 }
8475         }
8476
8477         /* Set AN and select the SA */
8478         ctrl = (an << idx * 2) | (idx << 4);
8479         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8480
8481         return 0;
8482 }
8483
8484 int
8485 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8486                                  uint32_t pn, uint8_t *key)
8487 {
8488         struct ixgbe_hw *hw;
8489         struct rte_eth_dev *dev;
8490         struct rte_eth_dev_info dev_info;
8491         uint32_t ctrl, i;
8492
8493         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8494
8495         rte_eth_dev_info_get(port, &dev_info);
8496         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
8497                 return -ENOTSUP;
8498
8499         dev = &rte_eth_devices[port];
8500         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8501
8502         if (idx != 0 && idx != 1)
8503                 return -EINVAL;
8504
8505         if (an >= 4)
8506                 return -EINVAL;
8507
8508         /* Set the PN */
8509         pn = rte_cpu_to_be_32(pn);
8510         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8511
8512         /* Set the key */
8513         for (i = 0; i < 4; i++) {
8514                 ctrl = (key[i * 4 + 0] <<  0) |
8515                        (key[i * 4 + 1] <<  8) |
8516                        (key[i * 4 + 2] << 16) |
8517                        (key[i * 4 + 3] << 24);
8518                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8519         }
8520
8521         /* Set the AN and validate the SA */
8522         ctrl = an | (1 << 2);
8523         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8524
8525         return 0;
8526 }
8527
8528 /* restore n-tuple filter */
8529 static inline void
8530 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8531 {
8532         struct ixgbe_filter_info *filter_info =
8533                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8534         struct ixgbe_5tuple_filter *node;
8535
8536         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8537                 ixgbe_inject_5tuple_filter(dev, node);
8538         }
8539 }
8540
8541 /* restore ethernet type filter */
8542 static inline void
8543 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8544 {
8545         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8546         struct ixgbe_filter_info *filter_info =
8547                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8548         int i;
8549
8550         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8551                 if (filter_info->ethertype_mask & (1 << i)) {
8552                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8553                                         filter_info->ethertype_filters[i].etqf);
8554                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8555                                         filter_info->ethertype_filters[i].etqs);
8556                         IXGBE_WRITE_FLUSH(hw);
8557                 }
8558         }
8559 }
8560
8561 /* restore SYN filter */
8562 static inline void
8563 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8564 {
8565         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8566         struct ixgbe_filter_info *filter_info =
8567                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8568         uint32_t synqf;
8569
8570         synqf = filter_info->syn_info;
8571
8572         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8573                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8574                 IXGBE_WRITE_FLUSH(hw);
8575         }
8576 }
8577
8578 /* restore L2 tunnel filter */
8579 static inline void
8580 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8581 {
8582         struct ixgbe_l2_tn_info *l2_tn_info =
8583                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8584         struct ixgbe_l2_tn_filter *node;
8585         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8586
8587         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8588                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8589                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8590                 l2_tn_conf.pool           = node->pool;
8591                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8592         }
8593 }
8594
8595 static int
8596 ixgbe_filter_restore(struct rte_eth_dev *dev)
8597 {
8598         ixgbe_ntuple_filter_restore(dev);
8599         ixgbe_ethertype_filter_restore(dev);
8600         ixgbe_syn_filter_restore(dev);
8601         ixgbe_fdir_filter_restore(dev);
8602         ixgbe_l2_tn_filter_restore(dev);
8603
8604         return 0;
8605 }
8606
8607 static void
8608 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8609 {
8610         struct ixgbe_l2_tn_info *l2_tn_info =
8611                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8612         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8613
8614         if (l2_tn_info->e_tag_en)
8615                 (void)ixgbe_e_tag_enable(hw);
8616
8617         if (l2_tn_info->e_tag_fwd_en)
8618                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8619
8620         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8621 }
8622
8623 /* remove all the n-tuple filters */
8624 void
8625 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8626 {
8627         struct ixgbe_filter_info *filter_info =
8628                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8629         struct ixgbe_5tuple_filter *p_5tuple;
8630
8631         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8632                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8633 }
8634
8635 /* remove all the ether type filters */
8636 void
8637 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8638 {
8639         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8640         struct ixgbe_filter_info *filter_info =
8641                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8642         int i;
8643
8644         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8645                 if (filter_info->ethertype_mask & (1 << i) &&
8646                     !filter_info->ethertype_filters[i].conf) {
8647                         (void)ixgbe_ethertype_filter_remove(filter_info,
8648                                                             (uint8_t)i);
8649                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8650                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8651                         IXGBE_WRITE_FLUSH(hw);
8652                 }
8653         }
8654 }
8655
8656 /* remove the SYN filter */
8657 void
8658 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8659 {
8660         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8661         struct ixgbe_filter_info *filter_info =
8662                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8663
8664         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8665                 filter_info->syn_info = 0;
8666
8667                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8668                 IXGBE_WRITE_FLUSH(hw);
8669         }
8670 }
8671
8672 /* remove all the L2 tunnel filters */
8673 int
8674 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8675 {
8676         struct ixgbe_l2_tn_info *l2_tn_info =
8677                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8678         struct ixgbe_l2_tn_filter *l2_tn_filter;
8679         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8680         int ret = 0;
8681
8682         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8683                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8684                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8685                 l2_tn_conf.pool           = l2_tn_filter->pool;
8686                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8687                 if (ret < 0)
8688                         return ret;
8689         }
8690
8691         return 0;
8692 }
8693
8694 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8695 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8696 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8697 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8698 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8699 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");