drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64 #include <rte_hash_crc.h>
  65
  66 #include "ixgbe_logs.h"
  67 #include "base/ixgbe_api.h"
  68 #include "base/ixgbe_vf.h"
  69 #include "base/ixgbe_common.h"
  70 #include "ixgbe_ethdev.h"
  71 #include "ixgbe_bypass.h"
  72 #include "ixgbe_rxtx.h"
  73 #include "base/ixgbe_type.h"
  74 #include "base/ixgbe_phy.h"
  75 #include "ixgbe_regs.h"
  76
  77 #include "rte_pmd_ixgbe.h"
  78
  79 /*
  80  * High threshold controlling when to start sending XOFF frames. Must be at
  81  * least 8 bytes less than receive packet buffer size. This value is in units
  82  * of 1024 bytes.
  83  */
  84 #define IXGBE_FC_HI    0x80
  85
  86 /*
  87  * Low threshold controlling when to start sending XON frames. This value is
  88  * in units of 1024 bytes.
  89  */
  90 #define IXGBE_FC_LO    0x40
  91
  92 /* Default minimum inter-interrupt interval for EITR configuration */
  93 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  94
  95 /* Timer value included in XOFF frames. */
  96 #define IXGBE_FC_PAUSE 0x680
  97
  98 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  99 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
 100 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 101
 102 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 103 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 104 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 105
 106 /*
 107  *  Default values for RX/TX configuration
 108  */
 109 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 110 #define IXGBE_DEFAULT_RX_PTHRESH      8
 111 #define IXGBE_DEFAULT_RX_HTHRESH      8
 112 #define IXGBE_DEFAULT_RX_WTHRESH      0
 113
 114 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 115 #define IXGBE_DEFAULT_TX_PTHRESH      32
 116 #define IXGBE_DEFAULT_TX_HTHRESH      0
 117 #define IXGBE_DEFAULT_TX_WTHRESH      0
 118 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 119
 120 /* Bit shift and mask */
 121 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 122 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 123 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 124 #define IXGBE_8_BIT_MASK   UINT8_MAX
 125
 126 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 127
 128 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 129
 130 #define IXGBE_HKEY_MAX_INDEX 10
 131
 132 /* Additional timesync values. */
 133 #define NSEC_PER_SEC             1000000000L
 134 #define IXGBE_INCVAL_10GB        0x66666666
 135 #define IXGBE_INCVAL_1GB         0x40000000
 136 #define IXGBE_INCVAL_100         0x50000000
 137 #define IXGBE_INCVAL_SHIFT_10GB  28
 138 #define IXGBE_INCVAL_SHIFT_1GB   24
 139 #define IXGBE_INCVAL_SHIFT_100   21
 140 #define IXGBE_INCVAL_SHIFT_82599 7
 141 #define IXGBE_INCPER_SHIFT_82599 24
 142
 143 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 144
 145 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 146 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 147 #define DEFAULT_ETAG_ETYPE                     0x893f
 148 #define IXGBE_ETAG_ETYPE                       0x00005084
 149 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 150 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 151 #define IXGBE_RAH_ADTYPE                       0x40000000
 152 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 153 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 154 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 155 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 156 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 157 #define IXGBE_VTEICR_MASK                      0x07
 158
 159 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 160 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 161
 162 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 163 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 167 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 168 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 169 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 173 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 178 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 179 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 180                                 int wait_to_complete);
 181 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 182                                 struct rte_eth_stats *stats);
 183 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 184                                 struct rte_eth_xstat *xstats, unsigned n);
 185 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 186                                   struct rte_eth_xstat *xstats, unsigned n);
 187 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 188 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 189 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 190         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 191 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 192         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 193 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 194                                              uint16_t queue_id,
 195                                              uint8_t stat_idx,
 196                                              uint8_t is_rx);
 197 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 198                                  size_t fw_size);
 199 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 200                                struct rte_eth_dev_info *dev_info);
 201 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 202 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 203                                  struct rte_eth_dev_info *dev_info);
 204 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 205
 206 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 207                 uint16_t vlan_id, int on);
 208 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 209                                enum rte_vlan_type vlan_type,
 210                                uint16_t tpid_id);
 211 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 212                 uint16_t queue, bool on);
 213 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 214                 int on);
 215 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 216 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 217 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 218 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 219 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 220
 221 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 223 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 224                                struct rte_eth_fc_conf *fc_conf);
 225 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 226                                struct rte_eth_fc_conf *fc_conf);
 227 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 228                 struct rte_eth_pfc_conf *pfc_conf);
 229 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 230                         struct rte_eth_rss_reta_entry64 *reta_conf,
 231                         uint16_t reta_size);
 232 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 233                         struct rte_eth_rss_reta_entry64 *reta_conf,
 234                         uint16_t reta_size);
 235 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 239 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 240 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 241                                       struct rte_intr_handle *handle);
 242 static void ixgbe_dev_interrupt_handler(void *param);
 243 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 244 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 245                 uint32_t index, uint32_t pool);
 246 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 247 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 248                                            struct ether_addr *mac_addr);
 249 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 250 static bool is_device_supported(struct rte_eth_dev *dev,
 251                                 struct rte_pci_driver *drv);
 252
 253 /* For Virtual Function support */
 254 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 255 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 256 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 257 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 258 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 259 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 260 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 261 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 262 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 263                 struct rte_eth_stats *stats);
 264 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 265 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 266                 uint16_t vlan_id, int on);
 267 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 268                 uint16_t queue, int on);
 269 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 270 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 271 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                             uint16_t queue_id);
 273 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                              uint16_t queue_id);
 275 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 276                                  uint8_t queue, uint8_t msix_vector);
 277 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 278 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 279 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 280
 281 /* For Eth VMDQ APIs support */
 282 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 283                 ether_addr * mac_addr, uint8_t on);
 284 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 285 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 286                 struct rte_eth_mirror_conf *mirror_conf,
 287                 uint8_t rule_id, uint8_t on);
 288 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 289                 uint8_t rule_id);
 290 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 291                                           uint16_t queue_id);
 292 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 293                                            uint16_t queue_id);
 294 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 295                                uint8_t queue, uint8_t msix_vector);
 296 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 297
 298 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 299                 uint16_t queue_idx, uint16_t tx_rate);
 300
 301 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 302                                  struct ether_addr *mac_addr,
 303                                  uint32_t index, uint32_t pool);
 304 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 305 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 306                                              struct ether_addr *mac_addr);
 307 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 308                         struct rte_eth_syn_filter *filter);
 309 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 310                         enum rte_filter_op filter_op,
 311                         void *arg);
 312 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 313                         struct ixgbe_5tuple_filter *filter);
 314 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 315                         struct ixgbe_5tuple_filter *filter);
 316 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 317                                 enum rte_filter_op filter_op,
 318                                 void *arg);
 319 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ntuple_filter *filter);
 321 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ethertype_filter *filter);
 326 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                      enum rte_filter_type filter_type,
 328                      enum rte_filter_op filter_op,
 329                      void *arg);
 330 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 331
 332 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 333                                       struct ether_addr *mc_addr_set,
 334                                       uint32_t nb_mc_addr);
 335 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 336                                    struct rte_eth_dcb_info *dcb_info);
 337
 338 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 339 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 340                             struct rte_dev_reg_info *regs);
 341 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 342 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 343                                 struct rte_dev_eeprom_info *eeprom);
 344 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 345                                 struct rte_dev_eeprom_info *eeprom);
 346
 347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 349                                 struct rte_dev_reg_info *regs);
 350
 351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 354                                             struct timespec *timestamp,
 355                                             uint32_t flags);
 356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 357                                             struct timespec *timestamp);
 358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 362                                    const struct timespec *timestamp);
 363 static void ixgbevf_dev_interrupt_handler(void *param);
 364
 365 static int ixgbe_dev_l2_tunnel_eth_type_conf
 366         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 367 static int ixgbe_dev_l2_tunnel_offload_set
 368         (struct rte_eth_dev *dev,
 369          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 370          uint32_t mask,
 371          uint8_t en);
 372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 373                                              enum rte_filter_op filter_op,
 374                                              void *arg);
 375
 376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 377                                          struct rte_eth_udp_tunnel *udp_tunnel);
 378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 379                                          struct rte_eth_udp_tunnel *udp_tunnel);
 380 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 381 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 382
 383 /*
 384  * Define VF Stats MACRO for Non "cleared on read" register
 385  */
 386 #define UPDATE_VF_STAT(reg, last, cur)                          \
 387 {                                                               \
 388         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 389         cur += (latest - last) & UINT_MAX;                      \
 390         last = latest;                                          \
 391 }
 392
 393 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 394 {                                                                \
 395         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 396         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 397         u64 latest = ((new_msb << 32) | new_lsb);                \
 398         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 399         last = latest;                                           \
 400 }
 401
 402 #define IXGBE_SET_HWSTRIP(h, q) do {\
 403                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 404                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 405                 (h)->bitmap[idx] |= 1 << bit;\
 406         } while (0)
 407
 408 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 409                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 410                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 411                 (h)->bitmap[idx] &= ~(1 << bit);\
 412         } while (0)
 413
 414 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 415                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 416                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 417                 (r) = (h)->bitmap[idx] >> bit & 1;\
 418         } while (0)
 419
 420 /*
 421  * The set of PCI devices this driver supports
 422  */
 423 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 477 #ifdef RTE_NIC_BYPASS
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 479 #endif
 480         { .vendor_id = 0, /* sentinel */ },
 481 };
 482
 483 /*
 484  * The set of PCI devices this driver supports (for 82599 VF)
 485  */
 486 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 497         { .vendor_id = 0, /* sentinel */ },
 498 };
 499
 500 static const struct rte_eth_desc_lim rx_desc_lim = {
 501         .nb_max = IXGBE_MAX_RING_DESC,
 502         .nb_min = IXGBE_MIN_RING_DESC,
 503         .nb_align = IXGBE_RXD_ALIGN,
 504 };
 505
 506 static const struct rte_eth_desc_lim tx_desc_lim = {
 507         .nb_max = IXGBE_MAX_RING_DESC,
 508         .nb_min = IXGBE_MIN_RING_DESC,
 509         .nb_align = IXGBE_TXD_ALIGN,
 510         .nb_seg_max = IXGBE_TX_MAX_SEG,
 511         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 512 };
 513
 514 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 515         .dev_configure        = ixgbe_dev_configure,
 516         .dev_start            = ixgbe_dev_start,
 517         .dev_stop             = ixgbe_dev_stop,
 518         .dev_set_link_up    = ixgbe_dev_set_link_up,
 519         .dev_set_link_down  = ixgbe_dev_set_link_down,
 520         .dev_close            = ixgbe_dev_close,
 521         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 522         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 523         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 524         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 525         .link_update          = ixgbe_dev_link_update,
 526         .stats_get            = ixgbe_dev_stats_get,
 527         .xstats_get           = ixgbe_dev_xstats_get,
 528         .stats_reset          = ixgbe_dev_stats_reset,
 529         .xstats_reset         = ixgbe_dev_xstats_reset,
 530         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 531         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 532         .fw_version_get       = ixgbe_fw_version_get,
 533         .dev_infos_get        = ixgbe_dev_info_get,
 534         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 535         .mtu_set              = ixgbe_dev_mtu_set,
 536         .vlan_filter_set      = ixgbe_vlan_filter_set,
 537         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 538         .vlan_offload_set     = ixgbe_vlan_offload_set,
 539         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 540         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 541         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 542         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 543         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 544         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 545         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 546         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 547         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 548         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 549         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 550         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 551         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 552         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 553         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 554         .dev_led_on           = ixgbe_dev_led_on,
 555         .dev_led_off          = ixgbe_dev_led_off,
 556         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 557         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 558         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 559         .mac_addr_add         = ixgbe_add_rar,
 560         .mac_addr_remove      = ixgbe_remove_rar,
 561         .mac_addr_set         = ixgbe_set_default_mac_addr,
 562         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 563         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 564         .mirror_rule_set      = ixgbe_mirror_rule_set,
 565         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 566         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 567         .reta_update          = ixgbe_dev_rss_reta_update,
 568         .reta_query           = ixgbe_dev_rss_reta_query,
 569 #ifdef RTE_NIC_BYPASS
 570         .bypass_init          = ixgbe_bypass_init,
 571         .bypass_state_set     = ixgbe_bypass_state_store,
 572         .bypass_state_show    = ixgbe_bypass_state_show,
 573         .bypass_event_set     = ixgbe_bypass_event_store,
 574         .bypass_event_show    = ixgbe_bypass_event_show,
 575         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 576         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 577         .bypass_ver_show      = ixgbe_bypass_ver_show,
 578         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 579 #endif /* RTE_NIC_BYPASS */
 580         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 581         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 582         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 583         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 584         .rxq_info_get         = ixgbe_rxq_info_get,
 585         .txq_info_get         = ixgbe_txq_info_get,
 586         .timesync_enable      = ixgbe_timesync_enable,
 587         .timesync_disable     = ixgbe_timesync_disable,
 588         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 589         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 590         .get_reg              = ixgbe_get_regs,
 591         .get_eeprom_length    = ixgbe_get_eeprom_length,
 592         .get_eeprom           = ixgbe_get_eeprom,
 593         .set_eeprom           = ixgbe_set_eeprom,
 594         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 595         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 596         .timesync_read_time   = ixgbe_timesync_read_time,
 597         .timesync_write_time  = ixgbe_timesync_write_time,
 598         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 599         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 600         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 601         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 602 };
 603
 604 /*
 605  * dev_ops for virtual function, bare necessities for basic vf
 606  * operation have been implemented
 607  */
 608 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 609         .dev_configure        = ixgbevf_dev_configure,
 610         .dev_start            = ixgbevf_dev_start,
 611         .dev_stop             = ixgbevf_dev_stop,
 612         .link_update          = ixgbe_dev_link_update,
 613         .stats_get            = ixgbevf_dev_stats_get,
 614         .xstats_get           = ixgbevf_dev_xstats_get,
 615         .stats_reset          = ixgbevf_dev_stats_reset,
 616         .xstats_reset         = ixgbevf_dev_stats_reset,
 617         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 618         .dev_close            = ixgbevf_dev_close,
 619         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 620         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 621         .dev_infos_get        = ixgbevf_dev_info_get,
 622         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 623         .mtu_set              = ixgbevf_dev_set_mtu,
 624         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 625         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 626         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 627         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 628         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 629         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 630         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 631         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 632         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 633         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 634         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 635         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 636         .mac_addr_add         = ixgbevf_add_mac_addr,
 637         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 638         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 639         .rxq_info_get         = ixgbe_rxq_info_get,
 640         .txq_info_get         = ixgbe_txq_info_get,
 641         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 642         .get_reg              = ixgbevf_get_regs,
 643         .reta_update          = ixgbe_dev_rss_reta_update,
 644         .reta_query           = ixgbe_dev_rss_reta_query,
 645         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 646         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 647 };
 648
 649 /* store statistics names and its offset in stats structure */
 650 struct rte_ixgbe_xstats_name_off {
 651         char name[RTE_ETH_XSTATS_NAME_SIZE];
 652         unsigned offset;
 653 };
 654
 655 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 656         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 657         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 658         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 659         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 660         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 661         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 662         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 663         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 664         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 665         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 666         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 667         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 668         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 669         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 670         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 671                 prc1023)},
 672         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 673                 prc1522)},
 674         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 675         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 676         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 677         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 678         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 679         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 680         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 681         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 682         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 683         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 684         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 685         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 686         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 687         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 688         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 689         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 690         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 691                 ptc1023)},
 692         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 693                 ptc1522)},
 694         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 695         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 696         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 697         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 698
 699         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 700                 fdirustat_add)},
 701         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 702                 fdirustat_remove)},
 703         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 704                 fdirfstat_fadd)},
 705         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 706                 fdirfstat_fremove)},
 707         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 708                 fdirmatch)},
 709         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 710                 fdirmiss)},
 711
 712         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 713         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 714         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 715                 fclast)},
 716         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 717         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 718         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 719         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 720         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 721                 fcoe_noddp)},
 722         {"rx_fcoe_no_direct_data_placement_ext_buff",
 723                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 724
 725         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 726                 lxontxc)},
 727         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 728                 lxonrxc)},
 729         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 730                 lxofftxc)},
 731         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 732                 lxoffrxc)},
 733         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 734 };
 735
 736 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 737                            sizeof(rte_ixgbe_stats_strings[0]))
 738
 739 /* MACsec statistics */
 740 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 741         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 742                 out_pkts_untagged)},
 743         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 744                 out_pkts_encrypted)},
 745         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 746                 out_pkts_protected)},
 747         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 748                 out_octets_encrypted)},
 749         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 750                 out_octets_protected)},
 751         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_untagged)},
 753         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_badtag)},
 755         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_nosci)},
 757         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_unknownsci)},
 759         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 760                 in_octets_decrypted)},
 761         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 762                 in_octets_validated)},
 763         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_unchecked)},
 765         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_delayed)},
 767         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_late)},
 769         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_ok)},
 771         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_invalid)},
 773         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_notvalid)},
 775         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_unusedsa)},
 777         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 778                 in_pkts_notusingsa)},
 779 };
 780
 781 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 782                            sizeof(rte_ixgbe_macsec_strings[0]))
 783
 784 /* Per-queue statistics */
 785 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 786         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 787         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 788         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 789         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 790 };
 791
 792 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 793                            sizeof(rte_ixgbe_rxq_strings[0]))
 794 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 795
 796 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 797         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 798         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 799         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 800                 pxon2offc)},
 801 };
 802
 803 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 804                            sizeof(rte_ixgbe_txq_strings[0]))
 805 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 806
 807 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 808         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 809 };
 810
 811 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 812                 sizeof(rte_ixgbevf_stats_strings[0]))
 813
 814 /**
 815  * Atomically reads the link status information from global
 816  * structure rte_eth_dev.
 817  *
 818  * @param dev
 819  *   - Pointer to the structure rte_eth_dev to read from.
 820  *   - Pointer to the buffer to be saved with the link status.
 821  *
 822  * @return
 823  *   - On success, zero.
 824  *   - On failure, negative value.
 825  */
 826 static inline int
 827 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 828                                 struct rte_eth_link *link)
 829 {
 830         struct rte_eth_link *dst = link;
 831         struct rte_eth_link *src = &(dev->data->dev_link);
 832
 833         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 834                                         *(uint64_t *)src) == 0)
 835                 return -1;
 836
 837         return 0;
 838 }
 839
 840 /**
 841  * Atomically writes the link status information into global
 842  * structure rte_eth_dev.
 843  *
 844  * @param dev
 845  *   - Pointer to the structure rte_eth_dev to read from.
 846  *   - Pointer to the buffer to be saved with the link status.
 847  *
 848  * @return
 849  *   - On success, zero.
 850  *   - On failure, negative value.
 851  */
 852 static inline int
 853 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 854                                 struct rte_eth_link *link)
 855 {
 856         struct rte_eth_link *dst = &(dev->data->dev_link);
 857         struct rte_eth_link *src = link;
 858
 859         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 860                                         *(uint64_t *)src) == 0)
 861                 return -1;
 862
 863         return 0;
 864 }
 865
 866 /*
 867  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 868  */
 869 static inline int
 870 ixgbe_is_sfp(struct ixgbe_hw *hw)
 871 {
 872         switch (hw->phy.type) {
 873         case ixgbe_phy_sfp_avago:
 874         case ixgbe_phy_sfp_ftl:
 875         case ixgbe_phy_sfp_intel:
 876         case ixgbe_phy_sfp_unknown:
 877         case ixgbe_phy_sfp_passive_tyco:
 878         case ixgbe_phy_sfp_passive_unknown:
 879                 return 1;
 880         default:
 881                 return 0;
 882         }
 883 }
 884
 885 static inline int32_t
 886 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 887 {
 888         uint32_t ctrl_ext;
 889         int32_t status;
 890
 891         status = ixgbe_reset_hw(hw);
 892
 893         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 894         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 895         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 896         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 897         IXGBE_WRITE_FLUSH(hw);
 898
 899         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 900                 status = IXGBE_SUCCESS;
 901         return status;
 902 }
 903
 904 static inline void
 905 ixgbe_enable_intr(struct rte_eth_dev *dev)
 906 {
 907         struct ixgbe_interrupt *intr =
 908                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 909         struct ixgbe_hw *hw =
 910                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 911
 912         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 913         IXGBE_WRITE_FLUSH(hw);
 914 }
 915
 916 /*
 917  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 918  */
 919 static void
 920 ixgbe_disable_intr(struct ixgbe_hw *hw)
 921 {
 922         PMD_INIT_FUNC_TRACE();
 923
 924         if (hw->mac.type == ixgbe_mac_82598EB) {
 925                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 926         } else {
 927                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 928                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 929                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 930         }
 931         IXGBE_WRITE_FLUSH(hw);
 932 }
 933
 934 /*
 935  * This function resets queue statistics mapping registers.
 936  * From Niantic datasheet, Initialization of Statistics section:
 937  * "...if software requires the queue counters, the RQSMR and TQSM registers
 938  * must be re-programmed following a device reset.
 939  */
 940 static void
 941 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 942 {
 943         uint32_t i;
 944
 945         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 946                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 947                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 948         }
 949 }
 950
 951
 952 static int
 953 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 954                                   uint16_t queue_id,
 955                                   uint8_t stat_idx,
 956                                   uint8_t is_rx)
 957 {
 958 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 959 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 960 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 961
 962         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 963         struct ixgbe_stat_mapping_registers *stat_mappings =
 964                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 965         uint32_t qsmr_mask = 0;
 966         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 967         uint32_t q_map;
 968         uint8_t n, offset;
 969
 970         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 971                 (hw->mac.type != ixgbe_mac_X540) &&
 972                 (hw->mac.type != ixgbe_mac_X550) &&
 973                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 974                 (hw->mac.type != ixgbe_mac_X550EM_a))
 975                 return -ENOSYS;
 976
 977         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 978                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 979                      queue_id, stat_idx);
 980
 981         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 982         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 983                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 984                 return -EIO;
 985         }
 986         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 987
 988         /* Now clear any previous stat_idx set */
 989         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 990         if (!is_rx)
 991                 stat_mappings->tqsm[n] &= ~clearing_mask;
 992         else
 993                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 994
 995         q_map = (uint32_t)stat_idx;
 996         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 997         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 998         if (!is_rx)
 999                 stat_mappings->tqsm[n] |= qsmr_mask;
1000         else
1001                 stat_mappings->rqsmr[n] |= qsmr_mask;
1002
1003         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1004                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1005                      queue_id, stat_idx);
1006         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1007                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1008
1009         /* Now write the mapping in the appropriate register */
1010         if (is_rx) {
1011                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1012                              stat_mappings->rqsmr[n], n);
1013                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1014         } else {
1015                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1016                              stat_mappings->tqsm[n], n);
1017                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1018         }
1019         return 0;
1020 }
1021
1022 static void
1023 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1024 {
1025         struct ixgbe_stat_mapping_registers *stat_mappings =
1026                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1028         int i;
1029
1030         /* write whatever was in stat mapping table to the NIC */
1031         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1032                 /* rx */
1033                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1034
1035                 /* tx */
1036                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1037         }
1038 }
1039
1040 static void
1041 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1042 {
1043         uint8_t i;
1044         struct ixgbe_dcb_tc_config *tc;
1045         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1046
1047         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1048         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1049         for (i = 0; i < dcb_max_tc; i++) {
1050                 tc = &dcb_config->tc_config[i];
1051                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1052                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1053                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1054                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1055                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1056                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1057                 tc->pfc = ixgbe_dcb_pfc_disabled;
1058         }
1059
1060         /* Initialize default user to priority mapping, UPx->TC0 */
1061         tc = &dcb_config->tc_config[0];
1062         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1063         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1064         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1065                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1066                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1067         }
1068         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1069         dcb_config->pfc_mode_enable = false;
1070         dcb_config->vt_mode = true;
1071         dcb_config->round_robin_enable = false;
1072         /* support all DCB capabilities in 82599 */
1073         dcb_config->support.capabilities = 0xFF;
1074
1075         /*we only support 4 Tcs for X540, X550 */
1076         if (hw->mac.type == ixgbe_mac_X540 ||
1077                 hw->mac.type == ixgbe_mac_X550 ||
1078                 hw->mac.type == ixgbe_mac_X550EM_x ||
1079                 hw->mac.type == ixgbe_mac_X550EM_a) {
1080                 dcb_config->num_tcs.pg_tcs = 4;
1081                 dcb_config->num_tcs.pfc_tcs = 4;
1082         }
1083 }
1084
1085 /*
1086  * Ensure that all locks are released before first NVM or PHY access
1087  */
1088 static void
1089 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1090 {
1091         uint16_t mask;
1092
1093         /*
1094          * Phy lock should not fail in this early stage. If this is the case,
1095          * it is due to an improper exit of the application.
1096          * So force the release of the faulty lock. Release of common lock
1097          * is done automatically by swfw_sync function.
1098          */
1099         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1100         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1101                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1102         }
1103         ixgbe_release_swfw_semaphore(hw, mask);
1104
1105         /*
1106          * These ones are more tricky since they are common to all ports; but
1107          * swfw_sync retries last long enough (1s) to be almost sure that if
1108          * lock can not be taken it is due to an improper lock of the
1109          * semaphore.
1110          */
1111         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1112         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1113                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1114         }
1115         ixgbe_release_swfw_semaphore(hw, mask);
1116 }
1117
1118 /*
1119  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1120  * It returns 0 on success.
1121  */
1122 static int
1123 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1124 {
1125         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1126         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1127         struct ixgbe_hw *hw =
1128                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1129         struct ixgbe_vfta *shadow_vfta =
1130                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1131         struct ixgbe_hwstrip *hwstrip =
1132                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1133         struct ixgbe_dcb_config *dcb_config =
1134                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1135         struct ixgbe_filter_info *filter_info =
1136                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1137         struct ixgbe_bw_conf *bw_conf =
1138                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1139         uint32_t ctrl_ext;
1140         uint16_t csum;
1141         int diag, i;
1142
1143         PMD_INIT_FUNC_TRACE();
1144
1145         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1146         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1147         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1148         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1149
1150         /*
1151          * For secondary processes, we don't initialise any further as primary
1152          * has already done this work. Only check we don't need a different
1153          * RX and TX function.
1154          */
1155         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1156                 struct ixgbe_tx_queue *txq;
1157                 /* TX queue function in primary, set by last queue initialized
1158                  * Tx queue may not initialized by primary process
1159                  */
1160                 if (eth_dev->data->tx_queues) {
1161                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1162                         ixgbe_set_tx_function(eth_dev, txq);
1163                 } else {
1164                         /* Use default TX function if we get here */
1165                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1166                                      "Using default TX function.");
1167                 }
1168
1169                 ixgbe_set_rx_function(eth_dev);
1170
1171                 return 0;
1172         }
1173
1174         rte_eth_copy_pci_info(eth_dev, pci_dev);
1175         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1176
1177         /* Vendor and Device ID need to be set before init of shared code */
1178         hw->device_id = pci_dev->id.device_id;
1179         hw->vendor_id = pci_dev->id.vendor_id;
1180         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1181         hw->allow_unsupported_sfp = 1;
1182
1183         /* Initialize the shared code (base driver) */
1184 #ifdef RTE_NIC_BYPASS
1185         diag = ixgbe_bypass_init_shared_code(hw);
1186 #else
1187         diag = ixgbe_init_shared_code(hw);
1188 #endif /* RTE_NIC_BYPASS */
1189
1190         if (diag != IXGBE_SUCCESS) {
1191                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1192                 return -EIO;
1193         }
1194
1195         /* pick up the PCI bus settings for reporting later */
1196         ixgbe_get_bus_info(hw);
1197
1198         /* Unlock any pending hardware semaphore */
1199         ixgbe_swfw_lock_reset(hw);
1200
1201         /* Initialize DCB configuration*/
1202         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1203         ixgbe_dcb_init(hw, dcb_config);
1204         /* Get Hardware Flow Control setting */
1205         hw->fc.requested_mode = ixgbe_fc_full;
1206         hw->fc.current_mode = ixgbe_fc_full;
1207         hw->fc.pause_time = IXGBE_FC_PAUSE;
1208         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1209                 hw->fc.low_water[i] = IXGBE_FC_LO;
1210                 hw->fc.high_water[i] = IXGBE_FC_HI;
1211         }
1212         hw->fc.send_xon = 1;
1213
1214         /* Make sure we have a good EEPROM before we read from it */
1215         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1216         if (diag != IXGBE_SUCCESS) {
1217                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1218                 return -EIO;
1219         }
1220
1221 #ifdef RTE_NIC_BYPASS
1222         diag = ixgbe_bypass_init_hw(hw);
1223 #else
1224         diag = ixgbe_init_hw(hw);
1225 #endif /* RTE_NIC_BYPASS */
1226
1227         /*
1228          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1229          * is called too soon after the kernel driver unbinding/binding occurs.
1230          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1231          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1232          * also called. See ixgbe_identify_phy_82599(). The reason for the
1233          * failure is not known, and only occuts when virtualisation features
1234          * are disabled in the bios. A delay of 100ms  was found to be enough by
1235          * trial-and-error, and is doubled to be safe.
1236          */
1237         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1238                 rte_delay_ms(200);
1239                 diag = ixgbe_init_hw(hw);
1240         }
1241
1242         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1243                 diag = IXGBE_SUCCESS;
1244
1245         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1246                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1247                              "LOM.  Please be aware there may be issues associated "
1248                              "with your hardware.");
1249                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1250                              "please contact your Intel or hardware representative "
1251                              "who provided you with this hardware.");
1252         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1253                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1254         if (diag) {
1255                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1256                 return -EIO;
1257         }
1258
1259         /* Reset the hw statistics */
1260         ixgbe_dev_stats_reset(eth_dev);
1261
1262         /* disable interrupt */
1263         ixgbe_disable_intr(hw);
1264
1265         /* reset mappings for queue statistics hw counters*/
1266         ixgbe_reset_qstat_mappings(hw);
1267
1268         /* Allocate memory for storing MAC addresses */
1269         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1270                                                hw->mac.num_rar_entries, 0);
1271         if (eth_dev->data->mac_addrs == NULL) {
1272                 PMD_INIT_LOG(ERR,
1273                              "Failed to allocate %u bytes needed to store "
1274                              "MAC addresses",
1275                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1276                 return -ENOMEM;
1277         }
1278         /* Copy the permanent MAC address */
1279         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1280                         &eth_dev->data->mac_addrs[0]);
1281
1282         /* Allocate memory for storing hash filter MAC addresses */
1283         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1284                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1285         if (eth_dev->data->hash_mac_addrs == NULL) {
1286                 PMD_INIT_LOG(ERR,
1287                              "Failed to allocate %d bytes needed to store MAC addresses",
1288                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1289                 return -ENOMEM;
1290         }
1291
1292         /* initialize the vfta */
1293         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1294
1295         /* initialize the hw strip bitmap*/
1296         memset(hwstrip, 0, sizeof(*hwstrip));
1297
1298         /* initialize PF if max_vfs not zero */
1299         ixgbe_pf_host_init(eth_dev);
1300
1301         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1302         /* let hardware know driver is loaded */
1303         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1304         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1305         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1306         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1307         IXGBE_WRITE_FLUSH(hw);
1308
1309         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1310                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1311                              (int) hw->mac.type, (int) hw->phy.type,
1312                              (int) hw->phy.sfp_type);
1313         else
1314                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1315                              (int) hw->mac.type, (int) hw->phy.type);
1316
1317         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1318                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1319                      pci_dev->id.device_id);
1320
1321         rte_intr_callback_register(intr_handle,
1322                                    ixgbe_dev_interrupt_handler, eth_dev);
1323
1324         /* enable uio/vfio intr/eventfd mapping */
1325         rte_intr_enable(intr_handle);
1326
1327         /* enable support intr */
1328         ixgbe_enable_intr(eth_dev);
1329
1330         /* initialize filter info */
1331         memset(filter_info, 0,
1332                sizeof(struct ixgbe_filter_info));
1333
1334         /* initialize 5tuple filter list */
1335         TAILQ_INIT(&filter_info->fivetuple_list);
1336
1337         /* initialize flow director filter list & hash */
1338         ixgbe_fdir_filter_init(eth_dev);
1339
1340         /* initialize l2 tunnel filter list & hash */
1341         ixgbe_l2_tn_filter_init(eth_dev);
1342
1343         TAILQ_INIT(&filter_ntuple_list);
1344         TAILQ_INIT(&filter_ethertype_list);
1345         TAILQ_INIT(&filter_syn_list);
1346         TAILQ_INIT(&filter_fdir_list);
1347         TAILQ_INIT(&filter_l2_tunnel_list);
1348         TAILQ_INIT(&ixgbe_flow_list);
1349
1350         /* initialize bandwidth configuration info */
1351         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1352
1353         return 0;
1354 }
1355
1356 static int
1357 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1358 {
1359         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1360         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1361         struct ixgbe_hw *hw;
1362
1363         PMD_INIT_FUNC_TRACE();
1364
1365         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1366                 return -EPERM;
1367
1368         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1369
1370         if (hw->adapter_stopped == 0)
1371                 ixgbe_dev_close(eth_dev);
1372
1373         eth_dev->dev_ops = NULL;
1374         eth_dev->rx_pkt_burst = NULL;
1375         eth_dev->tx_pkt_burst = NULL;
1376
1377         /* Unlock any pending hardware semaphore */
1378         ixgbe_swfw_lock_reset(hw);
1379
1380         /* disable uio intr before callback unregister */
1381         rte_intr_disable(intr_handle);
1382         rte_intr_callback_unregister(intr_handle,
1383                                      ixgbe_dev_interrupt_handler, eth_dev);
1384
1385         /* uninitialize PF if max_vfs not zero */
1386         ixgbe_pf_host_uninit(eth_dev);
1387
1388         rte_free(eth_dev->data->mac_addrs);
1389         eth_dev->data->mac_addrs = NULL;
1390
1391         rte_free(eth_dev->data->hash_mac_addrs);
1392         eth_dev->data->hash_mac_addrs = NULL;
1393
1394         /* remove all the fdir filters & hash */
1395         ixgbe_fdir_filter_uninit(eth_dev);
1396
1397         /* remove all the L2 tunnel filters & hash */
1398         ixgbe_l2_tn_filter_uninit(eth_dev);
1399
1400         /* Remove all ntuple filters of the device */
1401         ixgbe_ntuple_filter_uninit(eth_dev);
1402
1403         /* clear all the filters list */
1404         ixgbe_filterlist_flush();
1405
1406         return 0;
1407 }
1408
1409 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1410 {
1411         struct ixgbe_filter_info *filter_info =
1412                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1413         struct ixgbe_5tuple_filter *p_5tuple;
1414
1415         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1416                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1417                              p_5tuple,
1418                              entries);
1419                 rte_free(p_5tuple);
1420         }
1421         memset(filter_info->fivetuple_mask, 0,
1422                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1423
1424         return 0;
1425 }
1426
1427 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1428 {
1429         struct ixgbe_hw_fdir_info *fdir_info =
1430                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1431         struct ixgbe_fdir_filter *fdir_filter;
1432
1433                 if (fdir_info->hash_map)
1434                 rte_free(fdir_info->hash_map);
1435         if (fdir_info->hash_handle)
1436                 rte_hash_free(fdir_info->hash_handle);
1437
1438         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1439                 TAILQ_REMOVE(&fdir_info->fdir_list,
1440                              fdir_filter,
1441                              entries);
1442                 rte_free(fdir_filter);
1443         }
1444
1445         return 0;
1446 }
1447
1448 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1449 {
1450         struct ixgbe_l2_tn_info *l2_tn_info =
1451                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1452         struct ixgbe_l2_tn_filter *l2_tn_filter;
1453
1454         if (l2_tn_info->hash_map)
1455                 rte_free(l2_tn_info->hash_map);
1456         if (l2_tn_info->hash_handle)
1457                 rte_hash_free(l2_tn_info->hash_handle);
1458
1459         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1460                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1461                              l2_tn_filter,
1462                              entries);
1463                 rte_free(l2_tn_filter);
1464         }
1465
1466         return 0;
1467 }
1468
1469 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1470 {
1471         struct ixgbe_hw_fdir_info *fdir_info =
1472                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1473         char fdir_hash_name[RTE_HASH_NAMESIZE];
1474         struct rte_hash_parameters fdir_hash_params = {
1475                 .name = fdir_hash_name,
1476                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1477                 .key_len = sizeof(union ixgbe_atr_input),
1478                 .hash_func = rte_hash_crc,
1479                 .hash_func_init_val = 0,
1480                 .socket_id = rte_socket_id(),
1481         };
1482
1483         TAILQ_INIT(&fdir_info->fdir_list);
1484         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1485                  "fdir_%s", eth_dev->data->name);
1486         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1487         if (!fdir_info->hash_handle) {
1488                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1489                 return -EINVAL;
1490         }
1491         fdir_info->hash_map = rte_zmalloc("ixgbe",
1492                                           sizeof(struct ixgbe_fdir_filter *) *
1493                                           IXGBE_MAX_FDIR_FILTER_NUM,
1494                                           0);
1495         if (!fdir_info->hash_map) {
1496                 PMD_INIT_LOG(ERR,
1497                              "Failed to allocate memory for fdir hash map!");
1498                 return -ENOMEM;
1499         }
1500         fdir_info->mask_added = FALSE;
1501
1502         return 0;
1503 }
1504
1505 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1506 {
1507         struct ixgbe_l2_tn_info *l2_tn_info =
1508                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1509         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1510         struct rte_hash_parameters l2_tn_hash_params = {
1511                 .name = l2_tn_hash_name,
1512                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1513                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1514                 .hash_func = rte_hash_crc,
1515                 .hash_func_init_val = 0,
1516                 .socket_id = rte_socket_id(),
1517         };
1518
1519         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1520         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1521                  "l2_tn_%s", eth_dev->data->name);
1522         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1523         if (!l2_tn_info->hash_handle) {
1524                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1525                 return -EINVAL;
1526         }
1527         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1528                                    sizeof(struct ixgbe_l2_tn_filter *) *
1529                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1530                                    0);
1531         if (!l2_tn_info->hash_map) {
1532                 PMD_INIT_LOG(ERR,
1533                         "Failed to allocate memory for L2 TN hash map!");
1534                 return -ENOMEM;
1535         }
1536         l2_tn_info->e_tag_en = FALSE;
1537         l2_tn_info->e_tag_fwd_en = FALSE;
1538         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1539
1540         return 0;
1541 }
1542 /*
1543  * Negotiate mailbox API version with the PF.
1544  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1545  * Then we try to negotiate starting with the most recent one.
1546  * If all negotiation attempts fail, then we will proceed with
1547  * the default one (ixgbe_mbox_api_10).
1548  */
1549 static void
1550 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1551 {
1552         int32_t i;
1553
1554         /* start with highest supported, proceed down */
1555         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1556                 ixgbe_mbox_api_12,
1557                 ixgbe_mbox_api_11,
1558                 ixgbe_mbox_api_10,
1559         };
1560
1561         for (i = 0;
1562                         i != RTE_DIM(sup_ver) &&
1563                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1564                         i++)
1565                 ;
1566 }
1567
1568 static void
1569 generate_random_mac_addr(struct ether_addr *mac_addr)
1570 {
1571         uint64_t random;
1572
1573         /* Set Organizationally Unique Identifier (OUI) prefix. */
1574         mac_addr->addr_bytes[0] = 0x00;
1575         mac_addr->addr_bytes[1] = 0x09;
1576         mac_addr->addr_bytes[2] = 0xC0;
1577         /* Force indication of locally assigned MAC address. */
1578         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1579         /* Generate the last 3 bytes of the MAC address with a random number. */
1580         random = rte_rand();
1581         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1582 }
1583
1584 /*
1585  * Virtual Function device init
1586  */
1587 static int
1588 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1589 {
1590         int diag;
1591         uint32_t tc, tcs;
1592         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1593         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1594         struct ixgbe_hw *hw =
1595                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1596         struct ixgbe_vfta *shadow_vfta =
1597                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1598         struct ixgbe_hwstrip *hwstrip =
1599                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1600         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1601
1602         PMD_INIT_FUNC_TRACE();
1603
1604         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1605         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1606         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1607
1608         /* for secondary processes, we don't initialise any further as primary
1609          * has already done this work. Only check we don't need a different
1610          * RX function
1611          */
1612         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1613                 struct ixgbe_tx_queue *txq;
1614                 /* TX queue function in primary, set by last queue initialized
1615                  * Tx queue may not initialized by primary process
1616                  */
1617                 if (eth_dev->data->tx_queues) {
1618                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1619                         ixgbe_set_tx_function(eth_dev, txq);
1620                 } else {
1621                         /* Use default TX function if we get here */
1622                         PMD_INIT_LOG(NOTICE,
1623                                      "No TX queues configured yet. Using default TX function.");
1624                 }
1625
1626                 ixgbe_set_rx_function(eth_dev);
1627
1628                 return 0;
1629         }
1630
1631         rte_eth_copy_pci_info(eth_dev, pci_dev);
1632         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1633
1634         hw->device_id = pci_dev->id.device_id;
1635         hw->vendor_id = pci_dev->id.vendor_id;
1636         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1637
1638         /* initialize the vfta */
1639         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1640
1641         /* initialize the hw strip bitmap*/
1642         memset(hwstrip, 0, sizeof(*hwstrip));
1643
1644         /* Initialize the shared code (base driver) */
1645         diag = ixgbe_init_shared_code(hw);
1646         if (diag != IXGBE_SUCCESS) {
1647                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1648                 return -EIO;
1649         }
1650
1651         /* init_mailbox_params */
1652         hw->mbx.ops.init_params(hw);
1653
1654         /* Reset the hw statistics */
1655         ixgbevf_dev_stats_reset(eth_dev);
1656
1657         /* Disable the interrupts for VF */
1658         ixgbevf_intr_disable(hw);
1659
1660         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1661         diag = hw->mac.ops.reset_hw(hw);
1662
1663         /*
1664          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1665          * the underlying PF driver has not assigned a MAC address to the VF.
1666          * In this case, assign a random MAC address.
1667          */
1668         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1669                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1670                 return diag;
1671         }
1672
1673         /* negotiate mailbox API version to use with the PF. */
1674         ixgbevf_negotiate_api(hw);
1675
1676         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1677         ixgbevf_get_queues(hw, &tcs, &tc);
1678
1679         /* Allocate memory for storing MAC addresses */
1680         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1681                                                hw->mac.num_rar_entries, 0);
1682         if (eth_dev->data->mac_addrs == NULL) {
1683                 PMD_INIT_LOG(ERR,
1684                              "Failed to allocate %u bytes needed to store "
1685                              "MAC addresses",
1686                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1687                 return -ENOMEM;
1688         }
1689
1690         /* Generate a random MAC address, if none was assigned by PF. */
1691         if (is_zero_ether_addr(perm_addr)) {
1692                 generate_random_mac_addr(perm_addr);
1693                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1694                 if (diag) {
1695                         rte_free(eth_dev->data->mac_addrs);
1696                         eth_dev->data->mac_addrs = NULL;
1697                         return diag;
1698                 }
1699                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1700                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1701                              "%02x:%02x:%02x:%02x:%02x:%02x",
1702                              perm_addr->addr_bytes[0],
1703                              perm_addr->addr_bytes[1],
1704                              perm_addr->addr_bytes[2],
1705                              perm_addr->addr_bytes[3],
1706                              perm_addr->addr_bytes[4],
1707                              perm_addr->addr_bytes[5]);
1708         }
1709
1710         /* Copy the permanent MAC address */
1711         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1712
1713         /* reset the hardware with the new settings */
1714         diag = hw->mac.ops.start_hw(hw);
1715         switch (diag) {
1716         case  0:
1717                 break;
1718
1719         default:
1720                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1721                 return -EIO;
1722         }
1723
1724         rte_intr_callback_register(intr_handle,
1725                                    ixgbevf_dev_interrupt_handler, eth_dev);
1726         rte_intr_enable(intr_handle);
1727         ixgbevf_intr_enable(hw);
1728
1729         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1730                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1731                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1732
1733         return 0;
1734 }
1735
1736 /* Virtual Function device uninit */
1737
1738 static int
1739 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1740 {
1741         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1742         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1743         struct ixgbe_hw *hw;
1744
1745         PMD_INIT_FUNC_TRACE();
1746
1747         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1748                 return -EPERM;
1749
1750         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1751
1752         if (hw->adapter_stopped == 0)
1753                 ixgbevf_dev_close(eth_dev);
1754
1755         eth_dev->dev_ops = NULL;
1756         eth_dev->rx_pkt_burst = NULL;
1757         eth_dev->tx_pkt_burst = NULL;
1758
1759         /* Disable the interrupts for VF */
1760         ixgbevf_intr_disable(hw);
1761
1762         rte_free(eth_dev->data->mac_addrs);
1763         eth_dev->data->mac_addrs = NULL;
1764
1765         rte_intr_disable(intr_handle);
1766         rte_intr_callback_unregister(intr_handle,
1767                                      ixgbevf_dev_interrupt_handler, eth_dev);
1768
1769         return 0;
1770 }
1771
1772 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1773         struct rte_pci_device *pci_dev)
1774 {
1775         return rte_eth_dev_pci_generic_probe(pci_dev,
1776                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1777 }
1778
1779 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1780 {
1781         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1782 }
1783
1784 static struct rte_pci_driver rte_ixgbe_pmd = {
1785         .id_table = pci_id_ixgbe_map,
1786         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1787         .probe = eth_ixgbe_pci_probe,
1788         .remove = eth_ixgbe_pci_remove,
1789 };
1790
1791 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1792         struct rte_pci_device *pci_dev)
1793 {
1794         return rte_eth_dev_pci_generic_probe(pci_dev,
1795                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1796 }
1797
1798 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1799 {
1800         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1801 }
1802
1803 /*
1804  * virtual function driver struct
1805  */
1806 static struct rte_pci_driver rte_ixgbevf_pmd = {
1807         .id_table = pci_id_ixgbevf_map,
1808         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1809         .probe = eth_ixgbevf_pci_probe,
1810         .remove = eth_ixgbevf_pci_remove,
1811 };
1812
1813 static int
1814 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1815 {
1816         struct ixgbe_hw *hw =
1817                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818         struct ixgbe_vfta *shadow_vfta =
1819                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1820         uint32_t vfta;
1821         uint32_t vid_idx;
1822         uint32_t vid_bit;
1823
1824         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1825         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1826         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1827         if (on)
1828                 vfta |= vid_bit;
1829         else
1830                 vfta &= ~vid_bit;
1831         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1832
1833         /* update local VFTA copy */
1834         shadow_vfta->vfta[vid_idx] = vfta;
1835
1836         return 0;
1837 }
1838
1839 static void
1840 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1841 {
1842         if (on)
1843                 ixgbe_vlan_hw_strip_enable(dev, queue);
1844         else
1845                 ixgbe_vlan_hw_strip_disable(dev, queue);
1846 }
1847
1848 static int
1849 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1850                     enum rte_vlan_type vlan_type,
1851                     uint16_t tpid)
1852 {
1853         struct ixgbe_hw *hw =
1854                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855         int ret = 0;
1856         uint32_t reg;
1857         uint32_t qinq;
1858
1859         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1860         qinq &= IXGBE_DMATXCTL_GDV;
1861
1862         switch (vlan_type) {
1863         case ETH_VLAN_TYPE_INNER:
1864                 if (qinq) {
1865                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1866                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1867                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1868                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1869                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1870                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1871                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1872                 } else {
1873                         ret = -ENOTSUP;
1874                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1875                                     " by single VLAN");
1876                 }
1877                 break;
1878         case ETH_VLAN_TYPE_OUTER:
1879                 if (qinq) {
1880                         /* Only the high 16-bits is valid */
1881                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1882                                         IXGBE_EXVET_VET_EXT_SHIFT);
1883                 } else {
1884                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1885                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1886                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1887                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1888                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1889                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1890                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1891                 }
1892
1893                 break;
1894         default:
1895                 ret = -EINVAL;
1896                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1897                 break;
1898         }
1899
1900         return ret;
1901 }
1902
1903 void
1904 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1905 {
1906         struct ixgbe_hw *hw =
1907                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1908         uint32_t vlnctrl;
1909
1910         PMD_INIT_FUNC_TRACE();
1911
1912         /* Filter Table Disable */
1913         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1914         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1915
1916         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1917 }
1918
1919 void
1920 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1921 {
1922         struct ixgbe_hw *hw =
1923                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924         struct ixgbe_vfta *shadow_vfta =
1925                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1926         uint32_t vlnctrl;
1927         uint16_t i;
1928
1929         PMD_INIT_FUNC_TRACE();
1930
1931         /* Filter Table Enable */
1932         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1933         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1934         vlnctrl |= IXGBE_VLNCTRL_VFE;
1935
1936         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1937
1938         /* write whatever is in local vfta copy */
1939         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1940                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1941 }
1942
1943 static void
1944 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1945 {
1946         struct ixgbe_hwstrip *hwstrip =
1947                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1948         struct ixgbe_rx_queue *rxq;
1949
1950         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1951                 return;
1952
1953         if (on)
1954                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1955         else
1956                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1957
1958         if (queue >= dev->data->nb_rx_queues)
1959                 return;
1960
1961         rxq = dev->data->rx_queues[queue];
1962
1963         if (on)
1964                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1965         else
1966                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1967 }
1968
1969 static void
1970 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1971 {
1972         struct ixgbe_hw *hw =
1973                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974         uint32_t ctrl;
1975
1976         PMD_INIT_FUNC_TRACE();
1977
1978         if (hw->mac.type == ixgbe_mac_82598EB) {
1979                 /* No queue level support */
1980                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1981                 return;
1982         }
1983
1984         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1985         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1986         ctrl &= ~IXGBE_RXDCTL_VME;
1987         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1988
1989         /* record those setting for HW strip per queue */
1990         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1991 }
1992
1993 static void
1994 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1995 {
1996         struct ixgbe_hw *hw =
1997                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998         uint32_t ctrl;
1999
2000         PMD_INIT_FUNC_TRACE();
2001
2002         if (hw->mac.type == ixgbe_mac_82598EB) {
2003                 /* No queue level supported */
2004                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2005                 return;
2006         }
2007
2008         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2009         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2010         ctrl |= IXGBE_RXDCTL_VME;
2011         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2012
2013         /* record those setting for HW strip per queue */
2014         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2015 }
2016
2017 void
2018 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2019 {
2020         struct ixgbe_hw *hw =
2021                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022         uint32_t ctrl;
2023         uint16_t i;
2024         struct ixgbe_rx_queue *rxq;
2025
2026         PMD_INIT_FUNC_TRACE();
2027
2028         if (hw->mac.type == ixgbe_mac_82598EB) {
2029                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2030                 ctrl &= ~IXGBE_VLNCTRL_VME;
2031                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2032         } else {
2033                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2034                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2035                         rxq = dev->data->rx_queues[i];
2036                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2037                         ctrl &= ~IXGBE_RXDCTL_VME;
2038                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2039
2040                         /* record those setting for HW strip per queue */
2041                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2042                 }
2043         }
2044 }
2045
2046 void
2047 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2048 {
2049         struct ixgbe_hw *hw =
2050                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051         uint32_t ctrl;
2052         uint16_t i;
2053         struct ixgbe_rx_queue *rxq;
2054
2055         PMD_INIT_FUNC_TRACE();
2056
2057         if (hw->mac.type == ixgbe_mac_82598EB) {
2058                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2059                 ctrl |= IXGBE_VLNCTRL_VME;
2060                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2061         } else {
2062                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2063                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2064                         rxq = dev->data->rx_queues[i];
2065                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2066                         ctrl |= IXGBE_RXDCTL_VME;
2067                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2068
2069                         /* record those setting for HW strip per queue */
2070                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2071                 }
2072         }
2073 }
2074
2075 static void
2076 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2077 {
2078         struct ixgbe_hw *hw =
2079                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080         uint32_t ctrl;
2081
2082         PMD_INIT_FUNC_TRACE();
2083
2084         /* DMATXCTRL: Geric Double VLAN Disable */
2085         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2086         ctrl &= ~IXGBE_DMATXCTL_GDV;
2087         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2088
2089         /* CTRL_EXT: Global Double VLAN Disable */
2090         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2091         ctrl &= ~IXGBE_EXTENDED_VLAN;
2092         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2093
2094 }
2095
2096 static void
2097 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2098 {
2099         struct ixgbe_hw *hw =
2100                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101         uint32_t ctrl;
2102
2103         PMD_INIT_FUNC_TRACE();
2104
2105         /* DMATXCTRL: Geric Double VLAN Enable */
2106         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2107         ctrl |= IXGBE_DMATXCTL_GDV;
2108         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2109
2110         /* CTRL_EXT: Global Double VLAN Enable */
2111         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2112         ctrl |= IXGBE_EXTENDED_VLAN;
2113         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2114
2115         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2116         if (hw->mac.type == ixgbe_mac_X550 ||
2117             hw->mac.type == ixgbe_mac_X550EM_x ||
2118             hw->mac.type == ixgbe_mac_X550EM_a) {
2119                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2120                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2121                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2122         }
2123
2124         /*
2125          * VET EXT field in the EXVET register = 0x8100 by default
2126          * So no need to change. Same to VT field of DMATXCTL register
2127          */
2128 }
2129
2130 static void
2131 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2132 {
2133         if (mask & ETH_VLAN_STRIP_MASK) {
2134                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2135                         ixgbe_vlan_hw_strip_enable_all(dev);
2136                 else
2137                         ixgbe_vlan_hw_strip_disable_all(dev);
2138         }
2139
2140         if (mask & ETH_VLAN_FILTER_MASK) {
2141                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2142                         ixgbe_vlan_hw_filter_enable(dev);
2143                 else
2144                         ixgbe_vlan_hw_filter_disable(dev);
2145         }
2146
2147         if (mask & ETH_VLAN_EXTEND_MASK) {
2148                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2149                         ixgbe_vlan_hw_extend_enable(dev);
2150                 else
2151                         ixgbe_vlan_hw_extend_disable(dev);
2152         }
2153 }
2154
2155 static void
2156 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2157 {
2158         struct ixgbe_hw *hw =
2159                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2160         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2161         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2162
2163         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2164         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2165 }
2166
2167 static int
2168 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2169 {
2170         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2171
2172         switch (nb_rx_q) {
2173         case 1:
2174         case 2:
2175                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2176                 break;
2177         case 4:
2178                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2179                 break;
2180         default:
2181                 return -EINVAL;
2182         }
2183
2184         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2185         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2186
2187         return 0;
2188 }
2189
2190 static int
2191 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2192 {
2193         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2194         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2196         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2197
2198         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2199                 /* check multi-queue mode */
2200                 switch (dev_conf->rxmode.mq_mode) {
2201                 case ETH_MQ_RX_VMDQ_DCB:
2202                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2203                         break;
2204                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2205                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2206                         PMD_INIT_LOG(ERR, "SRIOV active,"
2207                                         " unsupported mq_mode rx %d.",
2208                                         dev_conf->rxmode.mq_mode);
2209                         return -EINVAL;
2210                 case ETH_MQ_RX_RSS:
2211                 case ETH_MQ_RX_VMDQ_RSS:
2212                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2213                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2214                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2215                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2216                                                 " invalid queue number"
2217                                                 " for VMDQ RSS, allowed"
2218                                                 " value are 1, 2 or 4.");
2219                                         return -EINVAL;
2220                                 }
2221                         break;
2222                 case ETH_MQ_RX_VMDQ_ONLY:
2223                 case ETH_MQ_RX_NONE:
2224                         /* if nothing mq mode configure, use default scheme */
2225                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2226                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2227                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2228                         break;
2229                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2230                         /* SRIOV only works in VMDq enable mode */
2231                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2232                                         " wrong mq_mode rx %d.",
2233                                         dev_conf->rxmode.mq_mode);
2234                         return -EINVAL;
2235                 }
2236
2237                 switch (dev_conf->txmode.mq_mode) {
2238                 case ETH_MQ_TX_VMDQ_DCB:
2239                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2240                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2241                         break;
2242                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2243                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2244                         break;
2245                 }
2246
2247                 /* check valid queue number */
2248                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2249                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2250                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2251                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2252                                         " must be less than or equal to %d.",
2253                                         nb_rx_q, nb_tx_q,
2254                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2255                         return -EINVAL;
2256                 }
2257         } else {
2258                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2259                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2260                                           " not supported.");
2261                         return -EINVAL;
2262                 }
2263                 /* check configuration for vmdb+dcb mode */
2264                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2265                         const struct rte_eth_vmdq_dcb_conf *conf;
2266
2267                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2268                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2269                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2270                                 return -EINVAL;
2271                         }
2272                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2273                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2274                                conf->nb_queue_pools == ETH_32_POOLS)) {
2275                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2276                                                 " nb_queue_pools must be %d or %d.",
2277                                                 ETH_16_POOLS, ETH_32_POOLS);
2278                                 return -EINVAL;
2279                         }
2280                 }
2281                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2282                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2283
2284                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2285                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2286                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2287                                 return -EINVAL;
2288                         }
2289                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2290                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2291                                conf->nb_queue_pools == ETH_32_POOLS)) {
2292                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2293                                                 " nb_queue_pools != %d and"
2294                                                 " nb_queue_pools != %d.",
2295                                                 ETH_16_POOLS, ETH_32_POOLS);
2296                                 return -EINVAL;
2297                         }
2298                 }
2299
2300                 /* For DCB mode check our configuration before we go further */
2301                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2302                         const struct rte_eth_dcb_rx_conf *conf;
2303
2304                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2305                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2306                                                  IXGBE_DCB_NB_QUEUES);
2307                                 return -EINVAL;
2308                         }
2309                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2310                         if (!(conf->nb_tcs == ETH_4_TCS ||
2311                                conf->nb_tcs == ETH_8_TCS)) {
2312                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2313                                                 " and nb_tcs != %d.",
2314                                                 ETH_4_TCS, ETH_8_TCS);
2315                                 return -EINVAL;
2316                         }
2317                 }
2318
2319                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2320                         const struct rte_eth_dcb_tx_conf *conf;
2321
2322                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2323                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2324                                                  IXGBE_DCB_NB_QUEUES);
2325                                 return -EINVAL;
2326                         }
2327                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2328                         if (!(conf->nb_tcs == ETH_4_TCS ||
2329                                conf->nb_tcs == ETH_8_TCS)) {
2330                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2331                                                 " and nb_tcs != %d.",
2332                                                 ETH_4_TCS, ETH_8_TCS);
2333                                 return -EINVAL;
2334                         }
2335                 }
2336
2337                 /*
2338                  * When DCB/VT is off, maximum number of queues changes,
2339                  * except for 82598EB, which remains constant.
2340                  */
2341                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2342                                 hw->mac.type != ixgbe_mac_82598EB) {
2343                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2344                                 PMD_INIT_LOG(ERR,
2345                                              "Neither VT nor DCB are enabled, "
2346                                              "nb_tx_q > %d.",
2347                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2348                                 return -EINVAL;
2349                         }
2350                 }
2351         }
2352         return 0;
2353 }
2354
2355 static int
2356 ixgbe_dev_configure(struct rte_eth_dev *dev)
2357 {
2358         struct ixgbe_interrupt *intr =
2359                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2360         struct ixgbe_adapter *adapter =
2361                 (struct ixgbe_adapter *)dev->data->dev_private;
2362         int ret;
2363
2364         PMD_INIT_FUNC_TRACE();
2365         /* multipe queue mode checking */
2366         ret  = ixgbe_check_mq_mode(dev);
2367         if (ret != 0) {
2368                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2369                             ret);
2370                 return ret;
2371         }
2372
2373         /* set flag to update link status after init */
2374         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2375
2376         /*
2377          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2378          * allocation or vector Rx preconditions we will reset it.
2379          */
2380         adapter->rx_bulk_alloc_allowed = true;
2381         adapter->rx_vec_allowed = true;
2382
2383         return 0;
2384 }
2385
2386 static void
2387 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2388 {
2389         struct ixgbe_hw *hw =
2390                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391         struct ixgbe_interrupt *intr =
2392                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2393         uint32_t gpie;
2394
2395         /* only set up it on X550EM_X */
2396         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2397                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2398                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2399                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2400                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2401                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2402         }
2403 }
2404
2405 /*
2406  * Configure device link speed and setup link.
2407  * It returns 0 on success.
2408  */
2409 static int
2410 ixgbe_dev_start(struct rte_eth_dev *dev)
2411 {
2412         struct ixgbe_hw *hw =
2413                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414         struct ixgbe_vf_info *vfinfo =
2415                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2416         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2417         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2418         uint32_t intr_vector = 0;
2419         int err, link_up = 0, negotiate = 0;
2420         uint32_t speed = 0;
2421         int mask = 0;
2422         int status;
2423         uint16_t vf, idx;
2424         uint32_t *link_speeds;
2425
2426         PMD_INIT_FUNC_TRACE();
2427
2428         /* IXGBE devices don't support:
2429         *    - half duplex (checked afterwards for valid speeds)
2430         *    - fixed speed: TODO implement
2431         */
2432         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2433                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2434                              dev->data->port_id);
2435                 return -EINVAL;
2436         }
2437
2438         /* disable uio/vfio intr/eventfd mapping */
2439         rte_intr_disable(intr_handle);
2440
2441         /* stop adapter */
2442         hw->adapter_stopped = 0;
2443         ixgbe_stop_adapter(hw);
2444
2445         /* reinitialize adapter
2446          * this calls reset and start
2447          */
2448         status = ixgbe_pf_reset_hw(hw);
2449         if (status != 0)
2450                 return -1;
2451         hw->mac.ops.start_hw(hw);
2452         hw->mac.get_link_status = true;
2453
2454         /* configure PF module if SRIOV enabled */
2455         ixgbe_pf_host_configure(dev);
2456
2457         ixgbe_dev_phy_intr_setup(dev);
2458
2459         /* check and configure queue intr-vector mapping */
2460         if ((rte_intr_cap_multiple(intr_handle) ||
2461              !RTE_ETH_DEV_SRIOV(dev).active) &&
2462             dev->data->dev_conf.intr_conf.rxq != 0) {
2463                 intr_vector = dev->data->nb_rx_queues;
2464                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2465                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2466                                         IXGBE_MAX_INTR_QUEUE_NUM);
2467                         return -ENOTSUP;
2468                 }
2469                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2470                         return -1;
2471         }
2472
2473         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2474                 intr_handle->intr_vec =
2475                         rte_zmalloc("intr_vec",
2476                                     dev->data->nb_rx_queues * sizeof(int), 0);
2477                 if (intr_handle->intr_vec == NULL) {
2478                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2479                                      " intr_vec", dev->data->nb_rx_queues);
2480                         return -ENOMEM;
2481                 }
2482         }
2483
2484         /* confiugre msix for sleep until rx interrupt */
2485         ixgbe_configure_msix(dev);
2486
2487         /* initialize transmission unit */
2488         ixgbe_dev_tx_init(dev);
2489
2490         /* This can fail when allocating mbufs for descriptor rings */
2491         err = ixgbe_dev_rx_init(dev);
2492         if (err) {
2493                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2494                 goto error;
2495         }
2496
2497     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2498                 ETH_VLAN_EXTEND_MASK;
2499         ixgbe_vlan_offload_set(dev, mask);
2500
2501         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2502                 /* Enable vlan filtering for VMDq */
2503                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2504         }
2505
2506         /* Configure DCB hw */
2507         ixgbe_configure_dcb(dev);
2508
2509         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2510                 err = ixgbe_fdir_configure(dev);
2511                 if (err)
2512                         goto error;
2513         }
2514
2515         /* Restore vf rate limit */
2516         if (vfinfo != NULL) {
2517                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2518                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2519                                 if (vfinfo[vf].tx_rate[idx] != 0)
2520                                         rte_pmd_ixgbe_set_vf_rate_limit(
2521                                                 dev->data->port_id, vf,
2522                                                 vfinfo[vf].tx_rate[idx],
2523                                                 1 << idx);
2524         }
2525
2526         ixgbe_restore_statistics_mapping(dev);
2527
2528         err = ixgbe_dev_rxtx_start(dev);
2529         if (err < 0) {
2530                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2531                 goto error;
2532         }
2533
2534         /* Skip link setup if loopback mode is enabled for 82599. */
2535         if (hw->mac.type == ixgbe_mac_82599EB &&
2536                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2537                 goto skip_link_setup;
2538
2539         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2540                 err = hw->mac.ops.setup_sfp(hw);
2541                 if (err)
2542                         goto error;
2543         }
2544
2545         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2546                 /* Turn on the copper */
2547                 ixgbe_set_phy_power(hw, true);
2548         } else {
2549                 /* Turn on the laser */
2550                 ixgbe_enable_tx_laser(hw);
2551         }
2552
2553         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2554         if (err)
2555                 goto error;
2556         dev->data->dev_link.link_status = link_up;
2557
2558         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2559         if (err)
2560                 goto error;
2561
2562         link_speeds = &dev->data->dev_conf.link_speeds;
2563         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2564                         ETH_LINK_SPEED_10G)) {
2565                 PMD_INIT_LOG(ERR, "Invalid link setting");
2566                 goto error;
2567         }
2568
2569         speed = 0x0;
2570         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2571                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2572                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2573                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2574         } else {
2575                 if (*link_speeds & ETH_LINK_SPEED_10G)
2576                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2577                 if (*link_speeds & ETH_LINK_SPEED_1G)
2578                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2579                 if (*link_speeds & ETH_LINK_SPEED_100M)
2580                         speed |= IXGBE_LINK_SPEED_100_FULL;
2581         }
2582
2583         err = ixgbe_setup_link(hw, speed, link_up);
2584         if (err)
2585                 goto error;
2586
2587 skip_link_setup:
2588
2589         if (rte_intr_allow_others(intr_handle)) {
2590                 /* check if lsc interrupt is enabled */
2591                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2592                         ixgbe_dev_lsc_interrupt_setup(dev);
2593                 ixgbe_dev_macsec_interrupt_setup(dev);
2594         } else {
2595                 rte_intr_callback_unregister(intr_handle,
2596                                              ixgbe_dev_interrupt_handler, dev);
2597                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2598                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2599                                      " no intr multiplex");
2600         }
2601
2602         /* check if rxq interrupt is enabled */
2603         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2604             rte_intr_dp_is_en(intr_handle))
2605                 ixgbe_dev_rxq_interrupt_setup(dev);
2606
2607         /* enable uio/vfio intr/eventfd mapping */
2608         rte_intr_enable(intr_handle);
2609
2610         /* resume enabled intr since hw reset */
2611         ixgbe_enable_intr(dev);
2612         ixgbe_l2_tunnel_conf(dev);
2613         ixgbe_filter_restore(dev);
2614
2615         return 0;
2616
2617 error:
2618         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2619         ixgbe_dev_clear_queues(dev);
2620         return -EIO;
2621 }
2622
2623 /*
2624  * Stop device: disable rx and tx functions to allow for reconfiguring.
2625  */
2626 static void
2627 ixgbe_dev_stop(struct rte_eth_dev *dev)
2628 {
2629         struct rte_eth_link link;
2630         struct ixgbe_hw *hw =
2631                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632         struct ixgbe_vf_info *vfinfo =
2633                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2634         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2635         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2636         int vf;
2637
2638         PMD_INIT_FUNC_TRACE();
2639
2640         /* disable interrupts */
2641         ixgbe_disable_intr(hw);
2642
2643         /* reset the NIC */
2644         ixgbe_pf_reset_hw(hw);
2645         hw->adapter_stopped = 0;
2646
2647         /* stop adapter */
2648         ixgbe_stop_adapter(hw);
2649
2650         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2651                 vfinfo[vf].clear_to_send = false;
2652
2653         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2654                 /* Turn off the copper */
2655                 ixgbe_set_phy_power(hw, false);
2656         } else {
2657                 /* Turn off the laser */
2658                 ixgbe_disable_tx_laser(hw);
2659         }
2660
2661         ixgbe_dev_clear_queues(dev);
2662
2663         /* Clear stored conf */
2664         dev->data->scattered_rx = 0;
2665         dev->data->lro = 0;
2666
2667         /* Clear recorded link status */
2668         memset(&link, 0, sizeof(link));
2669         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2670
2671         if (!rte_intr_allow_others(intr_handle))
2672                 /* resume to the default handler */
2673                 rte_intr_callback_register(intr_handle,
2674                                            ixgbe_dev_interrupt_handler,
2675                                            (void *)dev);
2676
2677         /* Clean datapath event and queue/vec mapping */
2678         rte_intr_efd_disable(intr_handle);
2679         if (intr_handle->intr_vec != NULL) {
2680                 rte_free(intr_handle->intr_vec);
2681                 intr_handle->intr_vec = NULL;
2682         }
2683 }
2684
2685 /*
2686  * Set device link up: enable tx.
2687  */
2688 static int
2689 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2690 {
2691         struct ixgbe_hw *hw =
2692                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2693         if (hw->mac.type == ixgbe_mac_82599EB) {
2694 #ifdef RTE_NIC_BYPASS
2695                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2696                         /* Not suported in bypass mode */
2697                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2698                                      "by device id 0x%x", hw->device_id);
2699                         return -ENOTSUP;
2700                 }
2701 #endif
2702         }
2703
2704         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2705                 /* Turn on the copper */
2706                 ixgbe_set_phy_power(hw, true);
2707         } else {
2708                 /* Turn on the laser */
2709                 ixgbe_enable_tx_laser(hw);
2710         }
2711
2712         return 0;
2713 }
2714
2715 /*
2716  * Set device link down: disable tx.
2717  */
2718 static int
2719 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2720 {
2721         struct ixgbe_hw *hw =
2722                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2723         if (hw->mac.type == ixgbe_mac_82599EB) {
2724 #ifdef RTE_NIC_BYPASS
2725                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2726                         /* Not suported in bypass mode */
2727                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2728                                      "by device id 0x%x", hw->device_id);
2729                         return -ENOTSUP;
2730                 }
2731 #endif
2732         }
2733
2734         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2735                 /* Turn off the copper */
2736                 ixgbe_set_phy_power(hw, false);
2737         } else {
2738                 /* Turn off the laser */
2739                 ixgbe_disable_tx_laser(hw);
2740         }
2741
2742         return 0;
2743 }
2744
2745 /*
2746  * Reest and stop device.
2747  */
2748 static void
2749 ixgbe_dev_close(struct rte_eth_dev *dev)
2750 {
2751         struct ixgbe_hw *hw =
2752                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2753
2754         PMD_INIT_FUNC_TRACE();
2755
2756         ixgbe_pf_reset_hw(hw);
2757
2758         ixgbe_dev_stop(dev);
2759         hw->adapter_stopped = 1;
2760
2761         ixgbe_dev_free_queues(dev);
2762
2763         ixgbe_disable_pcie_master(hw);
2764
2765         /* reprogram the RAR[0] in case user changed it. */
2766         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2767 }
2768
2769 static void
2770 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2771                            struct ixgbe_hw_stats *hw_stats,
2772                            struct ixgbe_macsec_stats *macsec_stats,
2773                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2774                            uint64_t *total_qprc, uint64_t *total_qprdc)
2775 {
2776         uint32_t bprc, lxon, lxoff, total;
2777         uint32_t delta_gprc = 0;
2778         unsigned i;
2779         /* Workaround for RX byte count not including CRC bytes when CRC
2780          * strip is enabled. CRC bytes are removed from counters when crc_strip
2781          * is disabled.
2782          */
2783         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2784                         IXGBE_HLREG0_RXCRCSTRP);
2785
2786         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2787         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2788         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2789         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2790
2791         for (i = 0; i < 8; i++) {
2792                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2793
2794                 /* global total per queue */
2795                 hw_stats->mpc[i] += mp;
2796                 /* Running comprehensive total for stats display */
2797                 *total_missed_rx += hw_stats->mpc[i];
2798                 if (hw->mac.type == ixgbe_mac_82598EB) {
2799                         hw_stats->rnbc[i] +=
2800                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2801                         hw_stats->pxonrxc[i] +=
2802                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2803                         hw_stats->pxoffrxc[i] +=
2804                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2805                 } else {
2806                         hw_stats->pxonrxc[i] +=
2807                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2808                         hw_stats->pxoffrxc[i] +=
2809                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2810                         hw_stats->pxon2offc[i] +=
2811                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2812                 }
2813                 hw_stats->pxontxc[i] +=
2814                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2815                 hw_stats->pxofftxc[i] +=
2816                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2817         }
2818         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2819                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2820                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2821                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2822
2823                 delta_gprc += delta_qprc;
2824
2825                 hw_stats->qprc[i] += delta_qprc;
2826                 hw_stats->qptc[i] += delta_qptc;
2827
2828                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2829                 hw_stats->qbrc[i] +=
2830                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2831                 if (crc_strip == 0)
2832                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2833
2834                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2835                 hw_stats->qbtc[i] +=
2836                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2837
2838                 hw_stats->qprdc[i] += delta_qprdc;
2839                 *total_qprdc += hw_stats->qprdc[i];
2840
2841                 *total_qprc += hw_stats->qprc[i];
2842                 *total_qbrc += hw_stats->qbrc[i];
2843         }
2844         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2845         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2846         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2847
2848         /*
2849          * An errata states that gprc actually counts good + missed packets:
2850          * Workaround to set gprc to summated queue packet receives
2851          */
2852         hw_stats->gprc = *total_qprc;
2853
2854         if (hw->mac.type != ixgbe_mac_82598EB) {
2855                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2856                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2857                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2858                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2859                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2860                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2861                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2862                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2863         } else {
2864                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2865                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2866                 /* 82598 only has a counter in the high register */
2867                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2868                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2869                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2870         }
2871         uint64_t old_tpr = hw_stats->tpr;
2872
2873         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2874         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2875
2876         if (crc_strip == 0)
2877                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2878
2879         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2880         hw_stats->gptc += delta_gptc;
2881         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2882         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2883
2884         /*
2885          * Workaround: mprc hardware is incorrectly counting
2886          * broadcasts, so for now we subtract those.
2887          */
2888         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2889         hw_stats->bprc += bprc;
2890         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2891         if (hw->mac.type == ixgbe_mac_82598EB)
2892                 hw_stats->mprc -= bprc;
2893
2894         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2895         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2896         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2897         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2898         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2899         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2900
2901         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2902         hw_stats->lxontxc += lxon;
2903         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2904         hw_stats->lxofftxc += lxoff;
2905         total = lxon + lxoff;
2906
2907         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2908         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2909         hw_stats->gptc -= total;
2910         hw_stats->mptc -= total;
2911         hw_stats->ptc64 -= total;
2912         hw_stats->gotc -= total * ETHER_MIN_LEN;
2913
2914         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2915         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2916         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2917         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2918         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2919         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2920         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2921         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2922         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2923         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2924         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2925         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2926         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2927         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2928         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2929         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2930         /* Only read FCOE on 82599 */
2931         if (hw->mac.type != ixgbe_mac_82598EB) {
2932                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2933                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2934                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2935                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2936                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2937         }
2938
2939         /* Flow Director Stats registers */
2940         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2941         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2942
2943         /* MACsec Stats registers */
2944         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2945         macsec_stats->out_pkts_encrypted +=
2946                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2947         macsec_stats->out_pkts_protected +=
2948                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2949         macsec_stats->out_octets_encrypted +=
2950                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2951         macsec_stats->out_octets_protected +=
2952                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2953         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2954         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2955         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2956         macsec_stats->in_pkts_unknownsci +=
2957                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2958         macsec_stats->in_octets_decrypted +=
2959                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2960         macsec_stats->in_octets_validated +=
2961                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2962         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2963         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2964         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2965         for (i = 0; i < 2; i++) {
2966                 macsec_stats->in_pkts_ok +=
2967                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2968                 macsec_stats->in_pkts_invalid +=
2969                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2970                 macsec_stats->in_pkts_notvalid +=
2971                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2972         }
2973         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2974         macsec_stats->in_pkts_notusingsa +=
2975                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2976 }
2977
2978 /*
2979  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2980  */
2981 static void
2982 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2983 {
2984         struct ixgbe_hw *hw =
2985                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2986         struct ixgbe_hw_stats *hw_stats =
2987                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2988         struct ixgbe_macsec_stats *macsec_stats =
2989                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2990                                 dev->data->dev_private);
2991         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2992         unsigned i;
2993
2994         total_missed_rx = 0;
2995         total_qbrc = 0;
2996         total_qprc = 0;
2997         total_qprdc = 0;
2998
2999         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3000                         &total_qbrc, &total_qprc, &total_qprdc);
3001
3002         if (stats == NULL)
3003                 return;
3004
3005         /* Fill out the rte_eth_stats statistics structure */
3006         stats->ipackets = total_qprc;
3007         stats->ibytes = total_qbrc;
3008         stats->opackets = hw_stats->gptc;
3009         stats->obytes = hw_stats->gotc;
3010
3011         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3012                 stats->q_ipackets[i] = hw_stats->qprc[i];
3013                 stats->q_opackets[i] = hw_stats->qptc[i];
3014                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3015                 stats->q_obytes[i] = hw_stats->qbtc[i];
3016                 stats->q_errors[i] = hw_stats->qprdc[i];
3017         }
3018
3019         /* Rx Errors */
3020         stats->imissed  = total_missed_rx;
3021         stats->ierrors  = hw_stats->crcerrs +
3022                           hw_stats->mspdc +
3023                           hw_stats->rlec +
3024                           hw_stats->ruc +
3025                           hw_stats->roc +
3026                           hw_stats->illerrc +
3027                           hw_stats->errbc +
3028                           hw_stats->rfc +
3029                           hw_stats->fccrc +
3030                           hw_stats->fclast;
3031
3032         /* Tx Errors */
3033         stats->oerrors  = 0;
3034 }
3035
3036 static void
3037 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3038 {
3039         struct ixgbe_hw_stats *stats =
3040                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3041
3042         /* HW registers are cleared on read */
3043         ixgbe_dev_stats_get(dev, NULL);
3044
3045         /* Reset software totals */
3046         memset(stats, 0, sizeof(*stats));
3047 }
3048
3049 /* This function calculates the number of xstats based on the current config */
3050 static unsigned
3051 ixgbe_xstats_calc_num(void) {
3052         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3053                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3054                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3055 }
3056
3057 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3058         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3059 {
3060         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3061         unsigned stat, i, count;
3062
3063         if (xstats_names != NULL) {
3064                 count = 0;
3065
3066                 /* Note: limit >= cnt_stats checked upstream
3067                  * in rte_eth_xstats_names()
3068                  */
3069
3070                 /* Extended stats from ixgbe_hw_stats */
3071                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3072                         snprintf(xstats_names[count].name,
3073                                 sizeof(xstats_names[count].name),
3074                                 "%s",
3075                                 rte_ixgbe_stats_strings[i].name);
3076                         count++;
3077                 }
3078
3079                 /* MACsec Stats */
3080                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3081                         snprintf(xstats_names[count].name,
3082                                 sizeof(xstats_names[count].name),
3083                                 "%s",
3084                                 rte_ixgbe_macsec_strings[i].name);
3085                         count++;
3086                 }
3087
3088                 /* RX Priority Stats */
3089                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3090                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3091                                 snprintf(xstats_names[count].name,
3092                                         sizeof(xstats_names[count].name),
3093                                         "rx_priority%u_%s", i,
3094                                         rte_ixgbe_rxq_strings[stat].name);
3095                                 count++;
3096                         }
3097                 }
3098
3099                 /* TX Priority Stats */
3100                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3101                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3102                                 snprintf(xstats_names[count].name,
3103                                         sizeof(xstats_names[count].name),
3104                                         "tx_priority%u_%s", i,
3105                                         rte_ixgbe_txq_strings[stat].name);
3106                                 count++;
3107                         }
3108                 }
3109         }
3110         return cnt_stats;
3111 }
3112
3113 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3114         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3115 {
3116         unsigned i;
3117
3118         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3119                 return -ENOMEM;
3120
3121         if (xstats_names != NULL)
3122                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3123                         snprintf(xstats_names[i].name,
3124                                 sizeof(xstats_names[i].name),
3125                                 "%s", rte_ixgbevf_stats_strings[i].name);
3126         return IXGBEVF_NB_XSTATS;
3127 }
3128
3129 static int
3130 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3131                                          unsigned n)
3132 {
3133         struct ixgbe_hw *hw =
3134                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3135         struct ixgbe_hw_stats *hw_stats =
3136                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3137         struct ixgbe_macsec_stats *macsec_stats =
3138                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3139                                 dev->data->dev_private);
3140         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3141         unsigned i, stat, count = 0;
3142
3143         count = ixgbe_xstats_calc_num();
3144
3145         if (n < count)
3146                 return count;
3147
3148         total_missed_rx = 0;
3149         total_qbrc = 0;
3150         total_qprc = 0;
3151         total_qprdc = 0;
3152
3153         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3154                         &total_qbrc, &total_qprc, &total_qprdc);
3155
3156         /* If this is a reset xstats is NULL, and we have cleared the
3157          * registers by reading them.
3158          */
3159         if (!xstats)
3160                 return 0;
3161
3162         /* Extended stats from ixgbe_hw_stats */
3163         count = 0;
3164         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3165                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3166                                 rte_ixgbe_stats_strings[i].offset);
3167                 xstats[count].id = count;
3168                 count++;
3169         }
3170
3171         /* MACsec Stats */
3172         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3173                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3174                                 rte_ixgbe_macsec_strings[i].offset);
3175                 xstats[count].id = count;
3176                 count++;
3177         }
3178
3179         /* RX Priority Stats */
3180         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3181                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3182                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3183                                         rte_ixgbe_rxq_strings[stat].offset +
3184                                         (sizeof(uint64_t) * i));
3185                         xstats[count].id = count;
3186                         count++;
3187                 }
3188         }
3189
3190         /* TX Priority Stats */
3191         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3192                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3193                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3194                                         rte_ixgbe_txq_strings[stat].offset +
3195                                         (sizeof(uint64_t) * i));
3196                         xstats[count].id = count;
3197                         count++;
3198                 }
3199         }
3200         return count;
3201 }
3202
3203 static void
3204 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3205 {
3206         struct ixgbe_hw_stats *stats =
3207                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3208         struct ixgbe_macsec_stats *macsec_stats =
3209                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3210                                 dev->data->dev_private);
3211
3212         unsigned count = ixgbe_xstats_calc_num();
3213
3214         /* HW registers are cleared on read */
3215         ixgbe_dev_xstats_get(dev, NULL, count);
3216
3217         /* Reset software totals */
3218         memset(stats, 0, sizeof(*stats));
3219         memset(macsec_stats, 0, sizeof(*macsec_stats));
3220 }
3221
3222 static void
3223 ixgbevf_update_stats(struct rte_eth_dev *dev)
3224 {
3225         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3226         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3227                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3228
3229         /* Good Rx packet, include VF loopback */
3230         UPDATE_VF_STAT(IXGBE_VFGPRC,
3231             hw_stats->last_vfgprc, hw_stats->vfgprc);
3232
3233         /* Good Rx octets, include VF loopback */
3234         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3235             hw_stats->last_vfgorc, hw_stats->vfgorc);
3236
3237         /* Good Tx packet, include VF loopback */
3238         UPDATE_VF_STAT(IXGBE_VFGPTC,
3239             hw_stats->last_vfgptc, hw_stats->vfgptc);
3240
3241         /* Good Tx octets, include VF loopback */
3242         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3243             hw_stats->last_vfgotc, hw_stats->vfgotc);
3244
3245         /* Rx Multicst Packet */
3246         UPDATE_VF_STAT(IXGBE_VFMPRC,
3247             hw_stats->last_vfmprc, hw_stats->vfmprc);
3248 }
3249
3250 static int
3251 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3252                        unsigned n)
3253 {
3254         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3255                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3256         unsigned i;
3257
3258         if (n < IXGBEVF_NB_XSTATS)
3259                 return IXGBEVF_NB_XSTATS;
3260
3261         ixgbevf_update_stats(dev);
3262
3263         if (!xstats)
3264                 return 0;
3265
3266         /* Extended stats */
3267         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3268                 xstats[i].id = i;
3269                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3270                         rte_ixgbevf_stats_strings[i].offset);
3271         }
3272
3273         return IXGBEVF_NB_XSTATS;
3274 }
3275
3276 static void
3277 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3278 {
3279         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3280                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3281
3282         ixgbevf_update_stats(dev);
3283
3284         if (stats == NULL)
3285                 return;
3286
3287         stats->ipackets = hw_stats->vfgprc;
3288         stats->ibytes = hw_stats->vfgorc;
3289         stats->opackets = hw_stats->vfgptc;
3290         stats->obytes = hw_stats->vfgotc;
3291 }
3292
3293 static void
3294 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3295 {
3296         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3297                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3298
3299         /* Sync HW register to the last stats */
3300         ixgbevf_dev_stats_get(dev, NULL);
3301
3302         /* reset HW current stats*/
3303         hw_stats->vfgprc = 0;
3304         hw_stats->vfgorc = 0;
3305         hw_stats->vfgptc = 0;
3306         hw_stats->vfgotc = 0;
3307 }
3308
3309 static int
3310 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3311 {
3312         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313         u16 eeprom_verh, eeprom_verl;
3314         u32 etrack_id;
3315         int ret;
3316
3317         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3318         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3319
3320         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3321         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3322
3323         ret += 1; /* add the size of '\0' */
3324         if (fw_size < (u32)ret)
3325                 return ret;
3326         else
3327                 return 0;
3328 }
3329
3330 static void
3331 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3332 {
3333         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3335         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3336
3337         dev_info->pci_dev = pci_dev;
3338         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3339         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3340         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3341                 /*
3342                  * When DCB/VT is off, maximum number of queues changes,
3343                  * except for 82598EB, which remains constant.
3344                  */
3345                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3346                                 hw->mac.type != ixgbe_mac_82598EB)
3347                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3348         }
3349         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3350         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3351         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3352         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3353         dev_info->max_vfs = pci_dev->max_vfs;
3354         if (hw->mac.type == ixgbe_mac_82598EB)
3355                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3356         else
3357                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3358         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3359         dev_info->rx_offload_capa =
3360                 DEV_RX_OFFLOAD_VLAN_STRIP |
3361                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3362                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3363                 DEV_RX_OFFLOAD_TCP_CKSUM;
3364
3365         /*
3366          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3367          * mode.
3368          */
3369         if ((hw->mac.type == ixgbe_mac_82599EB ||
3370              hw->mac.type == ixgbe_mac_X540) &&
3371             !RTE_ETH_DEV_SRIOV(dev).active)
3372                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3373
3374         if (hw->mac.type == ixgbe_mac_82599EB ||
3375             hw->mac.type == ixgbe_mac_X540)
3376                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3377
3378         if (hw->mac.type == ixgbe_mac_X550 ||
3379             hw->mac.type == ixgbe_mac_X550EM_x ||
3380             hw->mac.type == ixgbe_mac_X550EM_a)
3381                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3382
3383         dev_info->tx_offload_capa =
3384                 DEV_TX_OFFLOAD_VLAN_INSERT |
3385                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3386                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3387                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3388                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3389                 DEV_TX_OFFLOAD_TCP_TSO;
3390
3391         if (hw->mac.type == ixgbe_mac_82599EB ||
3392             hw->mac.type == ixgbe_mac_X540)
3393                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3394
3395         if (hw->mac.type == ixgbe_mac_X550 ||
3396             hw->mac.type == ixgbe_mac_X550EM_x ||
3397             hw->mac.type == ixgbe_mac_X550EM_a)
3398                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3399
3400         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3401                 .rx_thresh = {
3402                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3403                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3404                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3405                 },
3406                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3407                 .rx_drop_en = 0,
3408         };
3409
3410         dev_info->default_txconf = (struct rte_eth_txconf) {
3411                 .tx_thresh = {
3412                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3413                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3414                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3415                 },
3416                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3417                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3418                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3419                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3420         };
3421
3422         dev_info->rx_desc_lim = rx_desc_lim;
3423         dev_info->tx_desc_lim = tx_desc_lim;
3424
3425         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3426         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3427         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3428
3429         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3430         if (hw->mac.type == ixgbe_mac_X540 ||
3431             hw->mac.type == ixgbe_mac_X540_vf ||
3432             hw->mac.type == ixgbe_mac_X550 ||
3433             hw->mac.type == ixgbe_mac_X550_vf) {
3434                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3435         }
3436 }
3437
3438 static const uint32_t *
3439 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3440 {
3441         static const uint32_t ptypes[] = {
3442                 /* For non-vec functions,
3443                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3444                  * for vec functions,
3445                  * refers to _recv_raw_pkts_vec().
3446                  */
3447                 RTE_PTYPE_L2_ETHER,
3448                 RTE_PTYPE_L3_IPV4,
3449                 RTE_PTYPE_L3_IPV4_EXT,
3450                 RTE_PTYPE_L3_IPV6,
3451                 RTE_PTYPE_L3_IPV6_EXT,
3452                 RTE_PTYPE_L4_SCTP,
3453                 RTE_PTYPE_L4_TCP,
3454                 RTE_PTYPE_L4_UDP,
3455                 RTE_PTYPE_TUNNEL_IP,
3456                 RTE_PTYPE_INNER_L3_IPV6,
3457                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3458                 RTE_PTYPE_INNER_L4_TCP,
3459                 RTE_PTYPE_INNER_L4_UDP,
3460                 RTE_PTYPE_UNKNOWN
3461         };
3462
3463         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3464             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3465             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3466             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3467                 return ptypes;
3468         return NULL;
3469 }
3470
3471 static void
3472 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3473                      struct rte_eth_dev_info *dev_info)
3474 {
3475         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3476         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3477
3478         dev_info->pci_dev = pci_dev;
3479         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3480         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3481         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3482         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3483         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3484         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3485         dev_info->max_vfs = pci_dev->max_vfs;
3486         if (hw->mac.type == ixgbe_mac_82598EB)
3487                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3488         else
3489                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3490         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3491                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3492                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3493                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3494         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3495                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3496                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3497                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3498                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3499                                 DEV_TX_OFFLOAD_TCP_TSO;
3500
3501         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3502                 .rx_thresh = {
3503                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3504                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3505                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3506                 },
3507                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3508                 .rx_drop_en = 0,
3509         };
3510
3511         dev_info->default_txconf = (struct rte_eth_txconf) {
3512                 .tx_thresh = {
3513                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3514                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3515                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3516                 },
3517                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3518                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3519                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3520                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3521         };
3522
3523         dev_info->rx_desc_lim = rx_desc_lim;
3524         dev_info->tx_desc_lim = tx_desc_lim;
3525 }
3526
3527 /* return 0 means link status changed, -1 means not changed */
3528 static int
3529 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3530 {
3531         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3532         struct rte_eth_link link, old;
3533         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3534         int link_up;
3535         int diag;
3536
3537         link.link_status = ETH_LINK_DOWN;
3538         link.link_speed = 0;
3539         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3540         memset(&old, 0, sizeof(old));
3541         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3542
3543         hw->mac.get_link_status = true;
3544
3545         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3546         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3547                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3548         else
3549                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3550
3551         if (diag != 0) {
3552                 link.link_speed = ETH_SPEED_NUM_100M;
3553                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3554                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3555                 if (link.link_status == old.link_status)
3556                         return -1;
3557                 return 0;
3558         }
3559
3560         if (link_up == 0) {
3561                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3562                 if (link.link_status == old.link_status)
3563                         return -1;
3564                 return 0;
3565         }
3566         link.link_status = ETH_LINK_UP;
3567         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3568
3569         switch (link_speed) {
3570         default:
3571         case IXGBE_LINK_SPEED_UNKNOWN:
3572                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3573                 link.link_speed = ETH_SPEED_NUM_100M;
3574                 break;
3575
3576         case IXGBE_LINK_SPEED_100_FULL:
3577                 link.link_speed = ETH_SPEED_NUM_100M;
3578                 break;
3579
3580         case IXGBE_LINK_SPEED_1GB_FULL:
3581                 link.link_speed = ETH_SPEED_NUM_1G;
3582                 break;
3583
3584         case IXGBE_LINK_SPEED_10GB_FULL:
3585                 link.link_speed = ETH_SPEED_NUM_10G;
3586                 break;
3587         }
3588         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3589
3590         if (link.link_status == old.link_status)
3591                 return -1;
3592
3593         return 0;
3594 }
3595
3596 static void
3597 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3598 {
3599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3600         uint32_t fctrl;
3601
3602         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3603         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3604         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3605 }
3606
3607 static void
3608 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3609 {
3610         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3611         uint32_t fctrl;
3612
3613         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3614         fctrl &= (~IXGBE_FCTRL_UPE);
3615         if (dev->data->all_multicast == 1)
3616                 fctrl |= IXGBE_FCTRL_MPE;
3617         else
3618                 fctrl &= (~IXGBE_FCTRL_MPE);
3619         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3620 }
3621
3622 static void
3623 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3624 {
3625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3626         uint32_t fctrl;
3627
3628         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3629         fctrl |= IXGBE_FCTRL_MPE;
3630         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3631 }
3632
3633 static void
3634 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3635 {
3636         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3637         uint32_t fctrl;
3638
3639         if (dev->data->promiscuous == 1)
3640                 return; /* must remain in all_multicast mode */
3641
3642         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3643         fctrl &= (~IXGBE_FCTRL_MPE);
3644         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3645 }
3646
3647 /**
3648  * It clears the interrupt causes and enables the interrupt.
3649  * It will be called once only during nic initialized.
3650  *
3651  * @param dev
3652  *  Pointer to struct rte_eth_dev.
3653  *
3654  * @return
3655  *  - On success, zero.
3656  *  - On failure, a negative value.
3657  */
3658 static int
3659 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3660 {
3661         struct ixgbe_interrupt *intr =
3662                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3663
3664         ixgbe_dev_link_status_print(dev);
3665         intr->mask |= IXGBE_EICR_LSC;
3666
3667         return 0;
3668 }
3669
3670 /**
3671  * It clears the interrupt causes and enables the interrupt.
3672  * It will be called once only during nic initialized.
3673  *
3674  * @param dev
3675  *  Pointer to struct rte_eth_dev.
3676  *
3677  * @return
3678  *  - On success, zero.
3679  *  - On failure, a negative value.
3680  */
3681 static int
3682 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3683 {
3684         struct ixgbe_interrupt *intr =
3685                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3686
3687         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3688
3689         return 0;
3690 }
3691
3692 /**
3693  * It clears the interrupt causes and enables the interrupt.
3694  * It will be called once only during nic initialized.
3695  *
3696  * @param dev
3697  *  Pointer to struct rte_eth_dev.
3698  *
3699  * @return
3700  *  - On success, zero.
3701  *  - On failure, a negative value.
3702  */
3703 static int
3704 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3705 {
3706         struct ixgbe_interrupt *intr =
3707                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3708
3709         intr->mask |= IXGBE_EICR_LINKSEC;
3710
3711         return 0;
3712 }
3713
3714 /*
3715  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3716  *
3717  * @param dev
3718  *  Pointer to struct rte_eth_dev.
3719  *
3720  * @return
3721  *  - On success, zero.
3722  *  - On failure, a negative value.
3723  */
3724 static int
3725 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3726 {
3727         uint32_t eicr;
3728         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3729         struct ixgbe_interrupt *intr =
3730                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3731
3732         /* clear all cause mask */
3733         ixgbe_disable_intr(hw);
3734
3735         /* read-on-clear nic registers here */
3736         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3737         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3738
3739         intr->flags = 0;
3740
3741         /* set flag for async link update */
3742         if (eicr & IXGBE_EICR_LSC)
3743                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3744
3745         if (eicr & IXGBE_EICR_MAILBOX)
3746                 intr->flags |= IXGBE_FLAG_MAILBOX;
3747
3748         if (eicr & IXGBE_EICR_LINKSEC)
3749                 intr->flags |= IXGBE_FLAG_MACSEC;
3750
3751         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3752             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3753             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3754                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3755
3756         return 0;
3757 }
3758
3759 /**
3760  * It gets and then prints the link status.
3761  *
3762  * @param dev
3763  *  Pointer to struct rte_eth_dev.
3764  *
3765  * @return
3766  *  - On success, zero.
3767  *  - On failure, a negative value.
3768  */
3769 static void
3770 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3771 {
3772         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3773         struct rte_eth_link link;
3774
3775         memset(&link, 0, sizeof(link));
3776         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3777         if (link.link_status) {
3778                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3779                                         (int)(dev->data->port_id),
3780                                         (unsigned)link.link_speed,
3781                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3782                                         "full-duplex" : "half-duplex");
3783         } else {
3784                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3785                                 (int)(dev->data->port_id));
3786         }
3787         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3788                                 pci_dev->addr.domain,
3789                                 pci_dev->addr.bus,
3790                                 pci_dev->addr.devid,
3791                                 pci_dev->addr.function);
3792 }
3793
3794 /*
3795  * It executes link_update after knowing an interrupt occurred.
3796  *
3797  * @param dev
3798  *  Pointer to struct rte_eth_dev.
3799  *
3800  * @return
3801  *  - On success, zero.
3802  *  - On failure, a negative value.
3803  */
3804 static int
3805 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3806                            struct rte_intr_handle *intr_handle)
3807 {
3808         struct ixgbe_interrupt *intr =
3809                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3810         int64_t timeout;
3811         struct rte_eth_link link;
3812         struct ixgbe_hw *hw =
3813                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3814
3815         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3816
3817         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3818                 ixgbe_pf_mbx_process(dev);
3819                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3820         }
3821
3822         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3823                 ixgbe_handle_lasi(hw);
3824                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3825         }
3826
3827         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3828                 /* get the link status before link update, for predicting later */
3829                 memset(&link, 0, sizeof(link));
3830                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3831
3832                 ixgbe_dev_link_update(dev, 0);
3833
3834                 /* likely to up */
3835                 if (!link.link_status)
3836                         /* handle it 1 sec later, wait it being stable */
3837                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3838                 /* likely to down */
3839                 else
3840                         /* handle it 4 sec later, wait it being stable */
3841                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3842
3843                 ixgbe_dev_link_status_print(dev);
3844                 intr->mask_original = intr->mask;
3845                 /* only disable lsc interrupt */
3846                 intr->mask &= ~IXGBE_EIMS_LSC;
3847                 if (rte_eal_alarm_set(timeout * 1000,
3848                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3849                         PMD_DRV_LOG(ERR, "Error setting alarm");
3850                 else
3851                         intr->mask = intr->mask_original;
3852         }
3853
3854         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3855         ixgbe_enable_intr(dev);
3856         rte_intr_enable(intr_handle);
3857
3858         return 0;
3859 }
3860
3861 /**
3862  * Interrupt handler which shall be registered for alarm callback for delayed
3863  * handling specific interrupt to wait for the stable nic state. As the
3864  * NIC interrupt state is not stable for ixgbe after link is just down,
3865  * it needs to wait 4 seconds to get the stable status.
3866  *
3867  * @param handle
3868  *  Pointer to interrupt handle.
3869  * @param param
3870  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3871  *
3872  * @return
3873  *  void
3874  */
3875 static void
3876 ixgbe_dev_interrupt_delayed_handler(void *param)
3877 {
3878         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3879         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3880         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3881         struct ixgbe_interrupt *intr =
3882                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3883         struct ixgbe_hw *hw =
3884                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3885         uint32_t eicr;
3886
3887         ixgbe_disable_intr(hw);
3888
3889         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3890         if (eicr & IXGBE_EICR_MAILBOX)
3891                 ixgbe_pf_mbx_process(dev);
3892
3893         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3894                 ixgbe_handle_lasi(hw);
3895                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3896         }
3897
3898         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3899                 ixgbe_dev_link_update(dev, 0);
3900                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3901                 ixgbe_dev_link_status_print(dev);
3902                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3903         }
3904
3905         if (intr->flags & IXGBE_FLAG_MACSEC) {
3906                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3907                                               NULL);
3908                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3909         }
3910
3911         /* restore original mask */
3912         intr->mask = intr->mask_original;
3913         intr->mask_original = 0;
3914
3915         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3916         ixgbe_enable_intr(dev);
3917         rte_intr_enable(intr_handle);
3918 }
3919
3920 /**
3921  * Interrupt handler triggered by NIC  for handling
3922  * specific interrupt.
3923  *
3924  * @param handle
3925  *  Pointer to interrupt handle.
3926  * @param param
3927  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3928  *
3929  * @return
3930  *  void
3931  */
3932 static void
3933 ixgbe_dev_interrupt_handler(void *param)
3934 {
3935         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3936
3937         ixgbe_dev_interrupt_get_status(dev);
3938         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
3939 }
3940
3941 static int
3942 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3943 {
3944         struct ixgbe_hw *hw;
3945
3946         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3947         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3948 }
3949
3950 static int
3951 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3952 {
3953         struct ixgbe_hw *hw;
3954
3955         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3956         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3957 }
3958
3959 static int
3960 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3961 {
3962         struct ixgbe_hw *hw;
3963         uint32_t mflcn_reg;
3964         uint32_t fccfg_reg;
3965         int rx_pause;
3966         int tx_pause;
3967
3968         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3969
3970         fc_conf->pause_time = hw->fc.pause_time;
3971         fc_conf->high_water = hw->fc.high_water[0];
3972         fc_conf->low_water = hw->fc.low_water[0];
3973         fc_conf->send_xon = hw->fc.send_xon;
3974         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3975
3976         /*
3977          * Return rx_pause status according to actual setting of
3978          * MFLCN register.
3979          */
3980         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3981         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3982                 rx_pause = 1;
3983         else
3984                 rx_pause = 0;
3985
3986         /*
3987          * Return tx_pause status according to actual setting of
3988          * FCCFG register.
3989          */
3990         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3991         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3992                 tx_pause = 1;
3993         else
3994                 tx_pause = 0;
3995
3996         if (rx_pause && tx_pause)
3997                 fc_conf->mode = RTE_FC_FULL;
3998         else if (rx_pause)
3999                 fc_conf->mode = RTE_FC_RX_PAUSE;
4000         else if (tx_pause)
4001                 fc_conf->mode = RTE_FC_TX_PAUSE;
4002         else
4003                 fc_conf->mode = RTE_FC_NONE;
4004
4005         return 0;
4006 }
4007
4008 static int
4009 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4010 {
4011         struct ixgbe_hw *hw;
4012         int err;
4013         uint32_t rx_buf_size;
4014         uint32_t max_high_water;
4015         uint32_t mflcn;
4016         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4017                 ixgbe_fc_none,
4018                 ixgbe_fc_rx_pause,
4019                 ixgbe_fc_tx_pause,
4020                 ixgbe_fc_full
4021         };
4022
4023         PMD_INIT_FUNC_TRACE();
4024
4025         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4026         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4027         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4028
4029         /*
4030          * At least reserve one Ethernet frame for watermark
4031          * high_water/low_water in kilo bytes for ixgbe
4032          */
4033         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4034         if ((fc_conf->high_water > max_high_water) ||
4035                 (fc_conf->high_water < fc_conf->low_water)) {
4036                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4037                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4038                 return -EINVAL;
4039         }
4040
4041         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4042         hw->fc.pause_time     = fc_conf->pause_time;
4043         hw->fc.high_water[0]  = fc_conf->high_water;
4044         hw->fc.low_water[0]   = fc_conf->low_water;
4045         hw->fc.send_xon       = fc_conf->send_xon;
4046         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4047
4048         err = ixgbe_fc_enable(hw);
4049
4050         /* Not negotiated is not an error case */
4051         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4052
4053                 /* check if we want to forward MAC frames - driver doesn't have native
4054                  * capability to do that, so we'll write the registers ourselves */
4055
4056                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4057
4058                 /* set or clear MFLCN.PMCF bit depending on configuration */
4059                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4060                         mflcn |= IXGBE_MFLCN_PMCF;
4061                 else
4062                         mflcn &= ~IXGBE_MFLCN_PMCF;
4063
4064                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4065                 IXGBE_WRITE_FLUSH(hw);
4066
4067                 return 0;
4068         }
4069
4070         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4071         return -EIO;
4072 }
4073
4074 /**
4075  *  ixgbe_pfc_enable_generic - Enable flow control
4076  *  @hw: pointer to hardware structure
4077  *  @tc_num: traffic class number
4078  *  Enable flow control according to the current settings.
4079  */
4080 static int
4081 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4082 {
4083         int ret_val = 0;
4084         uint32_t mflcn_reg, fccfg_reg;
4085         uint32_t reg;
4086         uint32_t fcrtl, fcrth;
4087         uint8_t i;
4088         uint8_t nb_rx_en;
4089
4090         /* Validate the water mark configuration */
4091         if (!hw->fc.pause_time) {
4092                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4093                 goto out;
4094         }
4095
4096         /* Low water mark of zero causes XOFF floods */
4097         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4098                  /* High/Low water can not be 0 */
4099                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4100                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4101                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4102                         goto out;
4103                 }
4104
4105                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4106                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4107                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4108                         goto out;
4109                 }
4110         }
4111         /* Negotiate the fc mode to use */
4112         ixgbe_fc_autoneg(hw);
4113
4114         /* Disable any previous flow control settings */
4115         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4116         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4117
4118         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4119         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4120
4121         switch (hw->fc.current_mode) {
4122         case ixgbe_fc_none:
4123                 /*
4124                  * If the count of enabled RX Priority Flow control >1,
4125                  * and the TX pause can not be disabled
4126                  */
4127                 nb_rx_en = 0;
4128                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4129                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4130                         if (reg & IXGBE_FCRTH_FCEN)
4131                                 nb_rx_en++;
4132                 }
4133                 if (nb_rx_en > 1)
4134                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4135                 break;
4136         case ixgbe_fc_rx_pause:
4137                 /*
4138                  * Rx Flow control is enabled and Tx Flow control is
4139                  * disabled by software override. Since there really
4140                  * isn't a way to advertise that we are capable of RX
4141                  * Pause ONLY, we will advertise that we support both
4142                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4143                  * disable the adapter's ability to send PAUSE frames.
4144                  */
4145                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4146                 /*
4147                  * If the count of enabled RX Priority Flow control >1,
4148                  * and the TX pause can not be disabled
4149                  */
4150                 nb_rx_en = 0;
4151                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4152                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4153                         if (reg & IXGBE_FCRTH_FCEN)
4154                                 nb_rx_en++;
4155                 }
4156                 if (nb_rx_en > 1)
4157                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4158                 break;
4159         case ixgbe_fc_tx_pause:
4160                 /*
4161                  * Tx Flow control is enabled, and Rx Flow control is
4162                  * disabled by software override.
4163                  */
4164                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4165                 break;
4166         case ixgbe_fc_full:
4167                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4168                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4169                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4170                 break;
4171         default:
4172                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4173                 ret_val = IXGBE_ERR_CONFIG;
4174                 goto out;
4175         }
4176
4177         /* Set 802.3x based flow control settings. */
4178         mflcn_reg |= IXGBE_MFLCN_DPF;
4179         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4180         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4181
4182         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4183         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4184                 hw->fc.high_water[tc_num]) {
4185                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4186                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4187                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4188         } else {
4189                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4190                 /*
4191                  * In order to prevent Tx hangs when the internal Tx
4192                  * switch is enabled we must set the high water mark
4193                  * to the maximum FCRTH value.  This allows the Tx
4194                  * switch to function even under heavy Rx workloads.
4195                  */
4196                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4197         }
4198         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4199
4200         /* Configure pause time (2 TCs per register) */
4201         reg = hw->fc.pause_time * 0x00010001;
4202         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4203                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4204
4205         /* Configure flow control refresh threshold value */
4206         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4207
4208 out:
4209         return ret_val;
4210 }
4211
4212 static int
4213 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4214 {
4215         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4216         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4217
4218         if (hw->mac.type != ixgbe_mac_82598EB) {
4219                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4220         }
4221         return ret_val;
4222 }
4223
4224 static int
4225 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4226 {
4227         int err;
4228         uint32_t rx_buf_size;
4229         uint32_t max_high_water;
4230         uint8_t tc_num;
4231         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4232         struct ixgbe_hw *hw =
4233                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4234         struct ixgbe_dcb_config *dcb_config =
4235                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4236
4237         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4238                 ixgbe_fc_none,
4239                 ixgbe_fc_rx_pause,
4240                 ixgbe_fc_tx_pause,
4241                 ixgbe_fc_full
4242         };
4243
4244         PMD_INIT_FUNC_TRACE();
4245
4246         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4247         tc_num = map[pfc_conf->priority];
4248         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4249         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4250         /*
4251          * At least reserve one Ethernet frame for watermark
4252          * high_water/low_water in kilo bytes for ixgbe
4253          */
4254         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4255         if ((pfc_conf->fc.high_water > max_high_water) ||
4256             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4257                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4258                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4259                 return -EINVAL;
4260         }
4261
4262         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4263         hw->fc.pause_time = pfc_conf->fc.pause_time;
4264         hw->fc.send_xon = pfc_conf->fc.send_xon;
4265         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4266         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4267
4268         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4269
4270         /* Not negotiated is not an error case */
4271         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4272                 return 0;
4273
4274         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4275         return -EIO;
4276 }
4277
4278 static int
4279 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4280                           struct rte_eth_rss_reta_entry64 *reta_conf,
4281                           uint16_t reta_size)
4282 {
4283         uint16_t i, sp_reta_size;
4284         uint8_t j, mask;
4285         uint32_t reta, r;
4286         uint16_t idx, shift;
4287         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4288         uint32_t reta_reg;
4289
4290         PMD_INIT_FUNC_TRACE();
4291
4292         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4293                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4294                         "NIC.");
4295                 return -ENOTSUP;
4296         }
4297
4298         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4299         if (reta_size != sp_reta_size) {
4300                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4301                         "(%d) doesn't match the number hardware can supported "
4302                         "(%d)", reta_size, sp_reta_size);
4303                 return -EINVAL;
4304         }
4305
4306         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4307                 idx = i / RTE_RETA_GROUP_SIZE;
4308                 shift = i % RTE_RETA_GROUP_SIZE;
4309                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4310                                                 IXGBE_4_BIT_MASK);
4311                 if (!mask)
4312                         continue;
4313                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4314                 if (mask == IXGBE_4_BIT_MASK)
4315                         r = 0;
4316                 else
4317                         r = IXGBE_READ_REG(hw, reta_reg);
4318                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4319                         if (mask & (0x1 << j))
4320                                 reta |= reta_conf[idx].reta[shift + j] <<
4321                                                         (CHAR_BIT * j);
4322                         else
4323                                 reta |= r & (IXGBE_8_BIT_MASK <<
4324                                                 (CHAR_BIT * j));
4325                 }
4326                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4327         }
4328
4329         return 0;
4330 }
4331
4332 static int
4333 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4334                          struct rte_eth_rss_reta_entry64 *reta_conf,
4335                          uint16_t reta_size)
4336 {
4337         uint16_t i, sp_reta_size;
4338         uint8_t j, mask;
4339         uint32_t reta;
4340         uint16_t idx, shift;
4341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342         uint32_t reta_reg;
4343
4344         PMD_INIT_FUNC_TRACE();
4345         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4346         if (reta_size != sp_reta_size) {
4347                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4348                         "(%d) doesn't match the number hardware can supported "
4349                         "(%d)", reta_size, sp_reta_size);
4350                 return -EINVAL;
4351         }
4352
4353         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4354                 idx = i / RTE_RETA_GROUP_SIZE;
4355                 shift = i % RTE_RETA_GROUP_SIZE;
4356                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4357                                                 IXGBE_4_BIT_MASK);
4358                 if (!mask)
4359                         continue;
4360
4361                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4362                 reta = IXGBE_READ_REG(hw, reta_reg);
4363                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4364                         if (mask & (0x1 << j))
4365                                 reta_conf[idx].reta[shift + j] =
4366                                         ((reta >> (CHAR_BIT * j)) &
4367                                                 IXGBE_8_BIT_MASK);
4368                 }
4369         }
4370
4371         return 0;
4372 }
4373
4374 static void
4375 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4376                                 uint32_t index, uint32_t pool)
4377 {
4378         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4379         uint32_t enable_addr = 1;
4380
4381         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4382 }
4383
4384 static void
4385 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4386 {
4387         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4388
4389         ixgbe_clear_rar(hw, index);
4390 }
4391
4392 static void
4393 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4394 {
4395         ixgbe_remove_rar(dev, 0);
4396
4397         ixgbe_add_rar(dev, addr, 0, 0);
4398 }
4399
4400 static bool
4401 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4402 {
4403         if (strcmp(dev->data->drv_name, drv->driver.name))
4404                 return false;
4405
4406         return true;
4407 }
4408
4409 int
4410 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4411                 struct ether_addr *mac_addr)
4412 {
4413         struct ixgbe_hw *hw;
4414         struct ixgbe_vf_info *vfinfo;
4415         int rar_entry;
4416         uint8_t *new_mac = (uint8_t *)(mac_addr);
4417         struct rte_eth_dev *dev;
4418         struct rte_pci_device *pci_dev;
4419
4420         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4421
4422         dev = &rte_eth_devices[port];
4423         pci_dev = IXGBE_DEV_TO_PCI(dev);
4424
4425         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4426                 return -ENOTSUP;
4427
4428         if (vf >= pci_dev->max_vfs)
4429                 return -EINVAL;
4430
4431         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4432         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4433         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4434
4435         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4436                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4437                                 ETHER_ADDR_LEN);
4438                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4439                                 IXGBE_RAH_AV);
4440         }
4441         return -EINVAL;
4442 }
4443
4444 static int
4445 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4446 {
4447         uint32_t hlreg0;
4448         uint32_t maxfrs;
4449         struct ixgbe_hw *hw;
4450         struct rte_eth_dev_info dev_info;
4451         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4452
4453         ixgbe_dev_info_get(dev, &dev_info);
4454
4455         /* check that mtu is within the allowed range */
4456         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4457                 return -EINVAL;
4458
4459         /* refuse mtu that requires the support of scattered packets when this
4460          * feature has not been enabled before.
4461          */
4462         if (!dev->data->scattered_rx &&
4463             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4464              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4465                 return -EINVAL;
4466
4467         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4468         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4469
4470         /* switch to jumbo mode if needed */
4471         if (frame_size > ETHER_MAX_LEN) {
4472                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4473                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4474         } else {
4475                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4476                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4477         }
4478         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4479
4480         /* update max frame size */
4481         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4482
4483         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4484         maxfrs &= 0x0000FFFF;
4485         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4486         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4487
4488         return 0;
4489 }
4490
4491 /*
4492  * Virtual Function operations
4493  */
4494 static void
4495 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4496 {
4497         PMD_INIT_FUNC_TRACE();
4498
4499         /* Clear interrupt mask to stop from interrupts being generated */
4500         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4501
4502         IXGBE_WRITE_FLUSH(hw);
4503 }
4504
4505 static void
4506 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4507 {
4508         PMD_INIT_FUNC_TRACE();
4509
4510         /* VF enable interrupt autoclean */
4511         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4512         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4513         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4514
4515         IXGBE_WRITE_FLUSH(hw);
4516 }
4517
4518 static int
4519 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4520 {
4521         struct rte_eth_conf *conf = &dev->data->dev_conf;
4522         struct ixgbe_adapter *adapter =
4523                         (struct ixgbe_adapter *)dev->data->dev_private;
4524
4525         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4526                      dev->data->port_id);
4527
4528         /*
4529          * VF has no ability to enable/disable HW CRC
4530          * Keep the persistent behavior the same as Host PF
4531          */
4532 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4533         if (!conf->rxmode.hw_strip_crc) {
4534                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4535                 conf->rxmode.hw_strip_crc = 1;
4536         }
4537 #else
4538         if (conf->rxmode.hw_strip_crc) {
4539                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4540                 conf->rxmode.hw_strip_crc = 0;
4541         }
4542 #endif
4543
4544         /*
4545          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4546          * allocation or vector Rx preconditions we will reset it.
4547          */
4548         adapter->rx_bulk_alloc_allowed = true;
4549         adapter->rx_vec_allowed = true;
4550
4551         return 0;
4552 }
4553
4554 static int
4555 ixgbevf_dev_start(struct rte_eth_dev *dev)
4556 {
4557         struct ixgbe_hw *hw =
4558                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4559         uint32_t intr_vector = 0;
4560         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4561         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4562
4563         int err, mask = 0;
4564
4565         PMD_INIT_FUNC_TRACE();
4566
4567         hw->mac.ops.reset_hw(hw);
4568         hw->mac.get_link_status = true;
4569
4570         /* negotiate mailbox API version to use with the PF. */
4571         ixgbevf_negotiate_api(hw);
4572
4573         ixgbevf_dev_tx_init(dev);
4574
4575         /* This can fail when allocating mbufs for descriptor rings */
4576         err = ixgbevf_dev_rx_init(dev);
4577         if (err) {
4578                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4579                 ixgbe_dev_clear_queues(dev);
4580                 return err;
4581         }
4582
4583         /* Set vfta */
4584         ixgbevf_set_vfta_all(dev, 1);
4585
4586         /* Set HW strip */
4587         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4588                 ETH_VLAN_EXTEND_MASK;
4589         ixgbevf_vlan_offload_set(dev, mask);
4590
4591         ixgbevf_dev_rxtx_start(dev);
4592
4593         /* check and configure queue intr-vector mapping */
4594         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4595                 intr_vector = dev->data->nb_rx_queues;
4596                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4597                         return -1;
4598         }
4599
4600         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4601                 intr_handle->intr_vec =
4602                         rte_zmalloc("intr_vec",
4603                                     dev->data->nb_rx_queues * sizeof(int), 0);
4604                 if (intr_handle->intr_vec == NULL) {
4605                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4606                                      " intr_vec", dev->data->nb_rx_queues);
4607                         return -ENOMEM;
4608                 }
4609         }
4610         ixgbevf_configure_msix(dev);
4611
4612         rte_intr_enable(intr_handle);
4613
4614         /* Re-enable interrupt for VF */
4615         ixgbevf_intr_enable(hw);
4616
4617         return 0;
4618 }
4619
4620 static void
4621 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4622 {
4623         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4624         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4625         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4626
4627         PMD_INIT_FUNC_TRACE();
4628
4629         ixgbevf_intr_disable(hw);
4630
4631         hw->adapter_stopped = 1;
4632         ixgbe_stop_adapter(hw);
4633
4634         /*
4635           * Clear what we set, but we still keep shadow_vfta to
4636           * restore after device starts
4637           */
4638         ixgbevf_set_vfta_all(dev, 0);
4639
4640         /* Clear stored conf */
4641         dev->data->scattered_rx = 0;
4642
4643         ixgbe_dev_clear_queues(dev);
4644
4645         /* Clean datapath event and queue/vec mapping */
4646         rte_intr_efd_disable(intr_handle);
4647         if (intr_handle->intr_vec != NULL) {
4648                 rte_free(intr_handle->intr_vec);
4649                 intr_handle->intr_vec = NULL;
4650         }
4651 }
4652
4653 static void
4654 ixgbevf_dev_close(struct rte_eth_dev *dev)
4655 {
4656         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4657
4658         PMD_INIT_FUNC_TRACE();
4659
4660         ixgbe_reset_hw(hw);
4661
4662         ixgbevf_dev_stop(dev);
4663
4664         ixgbe_dev_free_queues(dev);
4665
4666         /**
4667          * Remove the VF MAC address ro ensure
4668          * that the VF traffic goes to the PF
4669          * after stop, close and detach of the VF
4670          **/
4671         ixgbevf_remove_mac_addr(dev, 0);
4672 }
4673
4674 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4675 {
4676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677         struct ixgbe_vfta *shadow_vfta =
4678                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4679         int i = 0, j = 0, vfta = 0, mask = 1;
4680
4681         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4682                 vfta = shadow_vfta->vfta[i];
4683                 if (vfta) {
4684                         mask = 1;
4685                         for (j = 0; j < 32; j++) {
4686                                 if (vfta & mask)
4687                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4688                                                        on, false);
4689                                 mask <<= 1;
4690                         }
4691                 }
4692         }
4693
4694 }
4695
4696 static int
4697 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4698 {
4699         struct ixgbe_hw *hw =
4700                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4701         struct ixgbe_vfta *shadow_vfta =
4702                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4703         uint32_t vid_idx = 0;
4704         uint32_t vid_bit = 0;
4705         int ret = 0;
4706
4707         PMD_INIT_FUNC_TRACE();
4708
4709         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4710         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4711         if (ret) {
4712                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4713                 return ret;
4714         }
4715         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4716         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4717
4718         /* Save what we set and retore it after device reset */
4719         if (on)
4720                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4721         else
4722                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4723
4724         return 0;
4725 }
4726
4727 static void
4728 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4729 {
4730         struct ixgbe_hw *hw =
4731                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4732         uint32_t ctrl;
4733
4734         PMD_INIT_FUNC_TRACE();
4735
4736         if (queue >= hw->mac.max_rx_queues)
4737                 return;
4738
4739         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4740         if (on)
4741                 ctrl |= IXGBE_RXDCTL_VME;
4742         else
4743                 ctrl &= ~IXGBE_RXDCTL_VME;
4744         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4745
4746         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4747 }
4748
4749 static void
4750 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4751 {
4752         struct ixgbe_hw *hw =
4753                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4754         uint16_t i;
4755         int on = 0;
4756
4757         /* VF function only support hw strip feature, others are not support */
4758         if (mask & ETH_VLAN_STRIP_MASK) {
4759                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4760
4761                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4762                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4763         }
4764 }
4765
4766 static int
4767 ixgbe_vt_check(struct ixgbe_hw *hw)
4768 {
4769         uint32_t reg_val;
4770
4771         /* if Virtualization Technology is enabled */
4772         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4773         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4774                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4775                 return -1;
4776         }
4777
4778         return 0;
4779 }
4780
4781 static uint32_t
4782 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4783 {
4784         uint32_t vector = 0;
4785
4786         switch (hw->mac.mc_filter_type) {
4787         case 0:   /* use bits [47:36] of the address */
4788                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4789                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4790                 break;
4791         case 1:   /* use bits [46:35] of the address */
4792                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4793                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4794                 break;
4795         case 2:   /* use bits [45:34] of the address */
4796                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4797                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4798                 break;
4799         case 3:   /* use bits [43:32] of the address */
4800                 vector = ((uc_addr->addr_bytes[4]) |
4801                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4802                 break;
4803         default:  /* Invalid mc_filter_type */
4804                 break;
4805         }
4806
4807         /* vector can only be 12-bits or boundary will be exceeded */
4808         vector &= 0xFFF;
4809         return vector;
4810 }
4811
4812 static int
4813 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4814                         uint8_t on)
4815 {
4816         uint32_t vector;
4817         uint32_t uta_idx;
4818         uint32_t reg_val;
4819         uint32_t uta_shift;
4820         uint32_t rc;
4821         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4822         const uint32_t ixgbe_uta_bit_shift = 5;
4823         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4824         const uint32_t bit1 = 0x1;
4825
4826         struct ixgbe_hw *hw =
4827                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4828         struct ixgbe_uta_info *uta_info =
4829                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4830
4831         /* The UTA table only exists on 82599 hardware and newer */
4832         if (hw->mac.type < ixgbe_mac_82599EB)
4833                 return -ENOTSUP;
4834
4835         vector = ixgbe_uta_vector(hw, mac_addr);
4836         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4837         uta_shift = vector & ixgbe_uta_bit_mask;
4838
4839         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4840         if (rc == on)
4841                 return 0;
4842
4843         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4844         if (on) {
4845                 uta_info->uta_in_use++;
4846                 reg_val |= (bit1 << uta_shift);
4847                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4848         } else {
4849                 uta_info->uta_in_use--;
4850                 reg_val &= ~(bit1 << uta_shift);
4851                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4852         }
4853
4854         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4855
4856         if (uta_info->uta_in_use > 0)
4857                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4858                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4859         else
4860                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4861
4862         return 0;
4863 }
4864
4865 static int
4866 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4867 {
4868         int i;
4869         struct ixgbe_hw *hw =
4870                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4871         struct ixgbe_uta_info *uta_info =
4872                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4873
4874         /* The UTA table only exists on 82599 hardware and newer */
4875         if (hw->mac.type < ixgbe_mac_82599EB)
4876                 return -ENOTSUP;
4877
4878         if (on) {
4879                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4880                         uta_info->uta_shadow[i] = ~0;
4881                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4882                 }
4883         } else {
4884                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4885                         uta_info->uta_shadow[i] = 0;
4886                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4887                 }
4888         }
4889         return 0;
4890
4891 }
4892
4893 uint32_t
4894 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4895 {
4896         uint32_t new_val = orig_val;
4897
4898         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4899                 new_val |= IXGBE_VMOLR_AUPE;
4900         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4901                 new_val |= IXGBE_VMOLR_ROMPE;
4902         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4903                 new_val |= IXGBE_VMOLR_ROPE;
4904         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4905                 new_val |= IXGBE_VMOLR_BAM;
4906         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4907                 new_val |= IXGBE_VMOLR_MPE;
4908
4909         return new_val;
4910 }
4911
4912 int
4913 rte_pmd_ixgbe_ping_vf(uint8_t port, uint16_t vf)
4914 {
4915         struct ixgbe_hw *hw;
4916         struct ixgbe_vf_info *vfinfo;
4917         struct rte_eth_dev *dev;
4918         struct rte_pci_device *pci_dev;
4919         uint32_t ctrl;
4920
4921         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4922
4923         dev = &rte_eth_devices[port];
4924         pci_dev = IXGBE_DEV_TO_PCI(dev);
4925
4926         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4927                 return -ENOTSUP;
4928
4929         if (vf >= pci_dev->max_vfs)
4930                 return -EINVAL;
4931
4932         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4933         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4934
4935         ctrl = IXGBE_PF_CONTROL_MSG;
4936         if (vfinfo[vf].clear_to_send)
4937                 ctrl |= IXGBE_VT_MSGTYPE_CTS;
4938
4939         ixgbe_write_mbx(hw, &ctrl, 1, vf);
4940
4941         return 0;
4942 }
4943
4944 int
4945 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4946 {
4947         struct ixgbe_hw *hw;
4948         struct ixgbe_mac_info *mac;
4949         struct rte_eth_dev *dev;
4950         struct rte_pci_device *pci_dev;
4951
4952         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4953
4954         dev = &rte_eth_devices[port];
4955         pci_dev = IXGBE_DEV_TO_PCI(dev);
4956
4957         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4958                 return -ENOTSUP;
4959
4960         if (vf >= pci_dev->max_vfs)
4961                 return -EINVAL;
4962
4963         if (on > 1)
4964                 return -EINVAL;
4965
4966         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4967         mac = &hw->mac;
4968
4969         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4970
4971         return 0;
4972 }
4973
4974 int
4975 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4976 {
4977         struct ixgbe_hw *hw;
4978         struct ixgbe_mac_info *mac;
4979         struct rte_eth_dev *dev;
4980         struct rte_pci_device *pci_dev;
4981
4982         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4983
4984         dev = &rte_eth_devices[port];
4985         pci_dev = IXGBE_DEV_TO_PCI(dev);
4986
4987         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4988                 return -ENOTSUP;
4989
4990         if (vf >= pci_dev->max_vfs)
4991                 return -EINVAL;
4992
4993         if (on > 1)
4994                 return -EINVAL;
4995
4996         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4997         mac = &hw->mac;
4998         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4999
5000         return 0;
5001 }
5002
5003 int
5004 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
5005 {
5006         struct ixgbe_hw *hw;
5007         uint32_t ctrl;
5008         struct rte_eth_dev *dev;
5009         struct rte_pci_device *pci_dev;
5010
5011         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5012
5013         dev = &rte_eth_devices[port];
5014         pci_dev = IXGBE_DEV_TO_PCI(dev);
5015
5016         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5017                 return -ENOTSUP;
5018
5019         if (vf >= pci_dev->max_vfs)
5020                 return -EINVAL;
5021
5022         if (vlan_id > ETHER_MAX_VLAN_ID)
5023                 return -EINVAL;
5024
5025         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5026         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
5027         if (vlan_id) {
5028                 ctrl = vlan_id;
5029                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
5030         } else {
5031                 ctrl = 0;
5032         }
5033
5034         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
5035
5036         return 0;
5037 }
5038
5039 int
5040 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
5041 {
5042         struct ixgbe_hw *hw;
5043         uint32_t ctrl;
5044         struct rte_eth_dev *dev;
5045
5046         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5047
5048         dev = &rte_eth_devices[port];
5049
5050         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5051                 return -ENOTSUP;
5052
5053         if (on > 1)
5054                 return -EINVAL;
5055
5056         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5058         /* enable or disable VMDQ loopback */
5059         if (on)
5060                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5061         else
5062                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5063
5064         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5065
5066         return 0;
5067 }
5068
5069 int
5070 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5071 {
5072         struct ixgbe_hw *hw;
5073         uint32_t reg_value;
5074         int i;
5075         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5076         struct rte_eth_dev *dev;
5077
5078         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5079
5080         dev = &rte_eth_devices[port];
5081
5082         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5083                 return -ENOTSUP;
5084
5085         if (on > 1)
5086                 return -EINVAL;
5087
5088         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5089         for (i = 0; i <= num_queues; i++) {
5090                 reg_value = IXGBE_QDE_WRITE |
5091                                 (i << IXGBE_QDE_IDX_SHIFT) |
5092                                 (on & IXGBE_QDE_ENABLE);
5093                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5094         }
5095
5096         return 0;
5097 }
5098
5099 int
5100 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5101 {
5102         struct ixgbe_hw *hw;
5103         uint32_t reg_value;
5104         struct rte_eth_dev *dev;
5105         struct rte_pci_device *pci_dev;
5106
5107         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5108
5109         dev = &rte_eth_devices[port];
5110         pci_dev = IXGBE_DEV_TO_PCI(dev);
5111
5112         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5113                 return -ENOTSUP;
5114
5115         /* only support VF's 0 to 63 */
5116         if ((vf >= pci_dev->max_vfs) || (vf > 63))
5117                 return -EINVAL;
5118
5119         if (on > 1)
5120                 return -EINVAL;
5121
5122         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5123         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5124         if (on)
5125                 reg_value |= IXGBE_SRRCTL_DROP_EN;
5126         else
5127                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5128
5129         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5130
5131         return 0;
5132 }
5133
5134 int
5135 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5136 {
5137         struct rte_eth_dev *dev;
5138         struct rte_pci_device *pci_dev;
5139         struct ixgbe_hw *hw;
5140         uint16_t queues_per_pool;
5141         uint32_t q;
5142
5143         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5144
5145         dev = &rte_eth_devices[port];
5146         pci_dev = IXGBE_DEV_TO_PCI(dev);
5147         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5148
5149         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5150                 return -ENOTSUP;
5151
5152         if (vf >= pci_dev->max_vfs)
5153                 return -EINVAL;
5154
5155         if (on > 1)
5156                 return -EINVAL;
5157
5158         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5159
5160         /* The PF has 128 queue pairs and in SRIOV configuration
5161          * those queues will be assigned to VF's, so RXDCTL
5162          * registers will be dealing with queues which will be
5163          * assigned to VF's.
5164          * Let's say we have SRIOV configured with 31 VF's then the
5165          * first 124 queues 0-123 will be allocated to VF's and only
5166          * the last 4 queues 123-127 will be assigned to the PF.
5167          */
5168         if (hw->mac.type == ixgbe_mac_82598EB)
5169                 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5170                                   ETH_16_POOLS;
5171         else
5172                 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5173                                   ETH_64_POOLS;
5174
5175         for (q = 0; q < queues_per_pool; q++)
5176                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5177                                 q + vf * queues_per_pool, on);
5178         return 0;
5179 }
5180
5181 int
5182 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5183 {
5184         int val = 0;
5185         struct rte_eth_dev *dev;
5186         struct rte_pci_device *pci_dev;
5187         struct ixgbe_hw *hw;
5188         uint32_t vmolr;
5189
5190         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5191
5192         dev = &rte_eth_devices[port];
5193         pci_dev = IXGBE_DEV_TO_PCI(dev);
5194
5195         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5196                 return -ENOTSUP;
5197
5198         if (vf >= pci_dev->max_vfs)
5199                 return -EINVAL;
5200
5201         if (on > 1)
5202                 return -EINVAL;
5203
5204         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5206
5207         if (hw->mac.type == ixgbe_mac_82598EB) {
5208                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5209                              " on 82599 hardware and newer");
5210                 return -ENOTSUP;
5211         }
5212         if (ixgbe_vt_check(hw) < 0)
5213                 return -ENOTSUP;
5214
5215         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5216
5217         if (on)
5218                 vmolr |= val;
5219         else
5220                 vmolr &= ~val;
5221
5222         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5223
5224         return 0;
5225 }
5226
5227 int
5228 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5229 {
5230         struct rte_eth_dev *dev;
5231         struct rte_pci_device *pci_dev;
5232         uint32_t reg, addr;
5233         uint32_t val;
5234         const uint8_t bit1 = 0x1;
5235         struct ixgbe_hw *hw;
5236
5237         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5238
5239         dev = &rte_eth_devices[port];
5240         pci_dev = IXGBE_DEV_TO_PCI(dev);
5241
5242         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5243                 return -ENOTSUP;
5244
5245         if (vf >= pci_dev->max_vfs)
5246                 return -EINVAL;
5247
5248         if (on > 1)
5249                 return -EINVAL;
5250
5251         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5252
5253         if (ixgbe_vt_check(hw) < 0)
5254                 return -ENOTSUP;
5255
5256         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5257         if (vf >= 32) {
5258                 addr = IXGBE_VFRE(1);
5259                 val = bit1 << (vf - 32);
5260         } else {
5261                 addr = IXGBE_VFRE(0);
5262                 val = bit1 << vf;
5263         }
5264
5265         reg = IXGBE_READ_REG(hw, addr);
5266
5267         if (on)
5268                 reg |= val;
5269         else
5270                 reg &= ~val;
5271
5272         IXGBE_WRITE_REG(hw, addr, reg);
5273
5274         return 0;
5275 }
5276
5277 int
5278 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5279 {
5280         struct rte_eth_dev *dev;
5281         struct rte_pci_device *pci_dev;
5282         uint32_t reg, addr;
5283         uint32_t val;
5284         const uint8_t bit1 = 0x1;
5285
5286         struct ixgbe_hw *hw;
5287
5288         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5289
5290         dev = &rte_eth_devices[port];
5291         pci_dev = IXGBE_DEV_TO_PCI(dev);
5292
5293         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5294                 return -ENOTSUP;
5295
5296         if (vf >= pci_dev->max_vfs)
5297                 return -EINVAL;
5298
5299         if (on > 1)
5300                 return -EINVAL;
5301
5302         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303         if (ixgbe_vt_check(hw) < 0)
5304                 return -ENOTSUP;
5305
5306         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5307         if (vf >= 32) {
5308                 addr = IXGBE_VFTE(1);
5309                 val = bit1 << (vf - 32);
5310         } else {
5311                 addr = IXGBE_VFTE(0);
5312                 val = bit1 << vf;
5313         }
5314
5315         reg = IXGBE_READ_REG(hw, addr);
5316
5317         if (on)
5318                 reg |= val;
5319         else
5320                 reg &= ~val;
5321
5322         IXGBE_WRITE_REG(hw, addr, reg);
5323
5324         return 0;
5325 }
5326
5327 int
5328 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5329                         uint64_t vf_mask, uint8_t vlan_on)
5330 {
5331         struct rte_eth_dev *dev;
5332         int ret = 0;
5333         uint16_t vf_idx;
5334         struct ixgbe_hw *hw;
5335
5336         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5337
5338         dev = &rte_eth_devices[port];
5339
5340         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5341                 return -ENOTSUP;
5342
5343         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5344                 return -EINVAL;
5345
5346         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5347         if (ixgbe_vt_check(hw) < 0)
5348                 return -ENOTSUP;
5349
5350         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5351                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5352                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5353                                                    vlan_on, false);
5354                         if (ret < 0)
5355                                 return ret;
5356                 }
5357         }
5358
5359         return ret;
5360 }
5361
5362 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5363         uint16_t tx_rate, uint64_t q_msk)
5364 {
5365         struct rte_eth_dev *dev;
5366         struct ixgbe_hw *hw;
5367         struct ixgbe_vf_info *vfinfo;
5368         struct rte_eth_link link;
5369         uint8_t  nb_q_per_pool;
5370         uint32_t queue_stride;
5371         uint32_t queue_idx, idx = 0, vf_idx;
5372         uint32_t queue_end;
5373         uint16_t total_rate = 0;
5374         struct rte_pci_device *pci_dev;
5375
5376         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5377
5378         dev = &rte_eth_devices[port];
5379         pci_dev = IXGBE_DEV_TO_PCI(dev);
5380         rte_eth_link_get_nowait(port, &link);
5381
5382         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5383                 return -ENOTSUP;
5384
5385         if (vf >= pci_dev->max_vfs)
5386                 return -EINVAL;
5387
5388         if (tx_rate > link.link_speed)
5389                 return -EINVAL;
5390
5391         if (q_msk == 0)
5392                 return 0;
5393
5394         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5395         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5396         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5397         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5398         queue_idx = vf * queue_stride;
5399         queue_end = queue_idx + nb_q_per_pool - 1;
5400         if (queue_end >= hw->mac.max_tx_queues)
5401                 return -EINVAL;
5402
5403         if (vfinfo) {
5404                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5405                         if (vf_idx == vf)
5406                                 continue;
5407                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5408                                 idx++)
5409                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5410                 }
5411         } else {
5412                 return -EINVAL;
5413         }
5414
5415         /* Store tx_rate for this vf. */
5416         for (idx = 0; idx < nb_q_per_pool; idx++) {
5417                 if (((uint64_t)0x1 << idx) & q_msk) {
5418                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5419                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5420                         total_rate += tx_rate;
5421                 }
5422         }
5423
5424         if (total_rate > dev->data->dev_link.link_speed) {
5425                 /* Reset stored TX rate of the VF if it causes exceed
5426                  * link speed.
5427                  */
5428                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5429                 return -EINVAL;
5430         }
5431
5432         /* Set RTTBCNRC of each queue/pool for vf X  */
5433         for (; queue_idx <= queue_end; queue_idx++) {
5434                 if (0x1 & q_msk)
5435                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5436                 q_msk = q_msk >> 1;
5437         }
5438
5439         return 0;
5440 }
5441
5442 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5443 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5444 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5445 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5446 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5447         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5448         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5449
5450 static int
5451 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5452                         struct rte_eth_mirror_conf *mirror_conf,
5453                         uint8_t rule_id, uint8_t on)
5454 {
5455         uint32_t mr_ctl, vlvf;
5456         uint32_t mp_lsb = 0;
5457         uint32_t mv_msb = 0;
5458         uint32_t mv_lsb = 0;
5459         uint32_t mp_msb = 0;
5460         uint8_t i = 0;
5461         int reg_index = 0;
5462         uint64_t vlan_mask = 0;
5463
5464         const uint8_t pool_mask_offset = 32;
5465         const uint8_t vlan_mask_offset = 32;
5466         const uint8_t dst_pool_offset = 8;
5467         const uint8_t rule_mr_offset  = 4;
5468         const uint8_t mirror_rule_mask = 0x0F;
5469
5470         struct ixgbe_mirror_info *mr_info =
5471                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5472         struct ixgbe_hw *hw =
5473                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5474         uint8_t mirror_type = 0;
5475
5476         if (ixgbe_vt_check(hw) < 0)
5477                 return -ENOTSUP;
5478
5479         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5480                 return -EINVAL;
5481
5482         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5483                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5484                         mirror_conf->rule_type);
5485                 return -EINVAL;
5486         }
5487
5488         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5489                 mirror_type |= IXGBE_MRCTL_VLME;
5490                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5491                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5492                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5493                                 /* search vlan id related pool vlan filter index */
5494                                 reg_index = ixgbe_find_vlvf_slot(hw,
5495                                                  mirror_conf->vlan.vlan_id[i],
5496                                                  false);
5497                                 if (reg_index < 0)
5498                                         return -EINVAL;
5499                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5500                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5501                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5502                                       mirror_conf->vlan.vlan_id[i]))
5503                                         vlan_mask |= (1ULL << reg_index);
5504                                 else
5505                                         return -EINVAL;
5506                         }
5507                 }
5508
5509                 if (on) {
5510                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5511                         mv_msb = vlan_mask >> vlan_mask_offset;
5512
5513                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5514                                                 mirror_conf->vlan.vlan_mask;
5515                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5516                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5517                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5518                                                 mirror_conf->vlan.vlan_id[i];
5519                         }
5520                 } else {
5521                         mv_lsb = 0;
5522                         mv_msb = 0;
5523                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5524                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5525                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5526                 }
5527         }
5528
5529         /*
5530          * if enable pool mirror, write related pool mask register,if disable
5531          * pool mirror, clear PFMRVM register
5532          */
5533         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5534                 mirror_type |= IXGBE_MRCTL_VPME;
5535                 if (on) {
5536                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5537                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5538                         mr_info->mr_conf[rule_id].pool_mask =
5539                                         mirror_conf->pool_mask;
5540
5541                 } else {
5542                         mp_lsb = 0;
5543                         mp_msb = 0;
5544                         mr_info->mr_conf[rule_id].pool_mask = 0;
5545                 }
5546         }
5547         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5548                 mirror_type |= IXGBE_MRCTL_UPME;
5549         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5550                 mirror_type |= IXGBE_MRCTL_DPME;
5551
5552         /* read  mirror control register and recalculate it */
5553         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5554
5555         if (on) {
5556                 mr_ctl |= mirror_type;
5557                 mr_ctl &= mirror_rule_mask;
5558                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5559         } else
5560                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5561
5562         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5563         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5564
5565         /* write mirrror control  register */
5566         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5567
5568         /* write pool mirrror control  register */
5569         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5570                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5571                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5572                                 mp_msb);
5573         }
5574         /* write VLAN mirrror control  register */
5575         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5576                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5577                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5578                                 mv_msb);
5579         }
5580
5581         return 0;
5582 }
5583
5584 static int
5585 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5586 {
5587         int mr_ctl = 0;
5588         uint32_t lsb_val = 0;
5589         uint32_t msb_val = 0;
5590         const uint8_t rule_mr_offset = 4;
5591
5592         struct ixgbe_hw *hw =
5593                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5594         struct ixgbe_mirror_info *mr_info =
5595                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5596
5597         if (ixgbe_vt_check(hw) < 0)
5598                 return -ENOTSUP;
5599
5600         memset(&mr_info->mr_conf[rule_id], 0,
5601                 sizeof(struct rte_eth_mirror_conf));
5602
5603         /* clear PFVMCTL register */
5604         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5605
5606         /* clear pool mask register */
5607         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5608         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5609
5610         /* clear vlan mask register */
5611         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5612         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5613
5614         return 0;
5615 }
5616
5617 static int
5618 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5619 {
5620         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5621         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5622         uint32_t mask;
5623         struct ixgbe_hw *hw =
5624                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5625
5626         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5627         mask |= (1 << IXGBE_MISC_VEC_ID);
5628         RTE_SET_USED(queue_id);
5629         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5630
5631         rte_intr_enable(intr_handle);
5632
5633         return 0;
5634 }
5635
5636 static int
5637 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5638 {
5639         uint32_t mask;
5640         struct ixgbe_hw *hw =
5641                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5642
5643         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5644         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5645         RTE_SET_USED(queue_id);
5646         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5647
5648         return 0;
5649 }
5650
5651 static int
5652 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5653 {
5654         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5655         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5656         uint32_t mask;
5657         struct ixgbe_hw *hw =
5658                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5659         struct ixgbe_interrupt *intr =
5660                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5661
5662         if (queue_id < 16) {
5663                 ixgbe_disable_intr(hw);
5664                 intr->mask |= (1 << queue_id);
5665                 ixgbe_enable_intr(dev);
5666         } else if (queue_id < 32) {
5667                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5668                 mask &= (1 << queue_id);
5669                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5670         } else if (queue_id < 64) {
5671                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5672                 mask &= (1 << (queue_id - 32));
5673                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5674         }
5675         rte_intr_enable(intr_handle);
5676
5677         return 0;
5678 }
5679
5680 static int
5681 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5682 {
5683         uint32_t mask;
5684         struct ixgbe_hw *hw =
5685                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5686         struct ixgbe_interrupt *intr =
5687                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5688
5689         if (queue_id < 16) {
5690                 ixgbe_disable_intr(hw);
5691                 intr->mask &= ~(1 << queue_id);
5692                 ixgbe_enable_intr(dev);
5693         } else if (queue_id < 32) {
5694                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5695                 mask &= ~(1 << queue_id);
5696                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5697         } else if (queue_id < 64) {
5698                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5699                 mask &= ~(1 << (queue_id - 32));
5700                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5701         }
5702
5703         return 0;
5704 }
5705
5706 static void
5707 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5708                      uint8_t queue, uint8_t msix_vector)
5709 {
5710         uint32_t tmp, idx;
5711
5712         if (direction == -1) {
5713                 /* other causes */
5714                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5715                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5716                 tmp &= ~0xFF;
5717                 tmp |= msix_vector;
5718                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5719         } else {
5720                 /* rx or tx cause */
5721                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5722                 idx = ((16 * (queue & 1)) + (8 * direction));
5723                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5724                 tmp &= ~(0xFF << idx);
5725                 tmp |= (msix_vector << idx);
5726                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5727         }
5728 }
5729
5730 /**
5731  * set the IVAR registers, mapping interrupt causes to vectors
5732  * @param hw
5733  *  pointer to ixgbe_hw struct
5734  * @direction
5735  *  0 for Rx, 1 for Tx, -1 for other causes
5736  * @queue
5737  *  queue to map the corresponding interrupt to
5738  * @msix_vector
5739  *  the vector to map to the corresponding queue
5740  */
5741 static void
5742 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5743                    uint8_t queue, uint8_t msix_vector)
5744 {
5745         uint32_t tmp, idx;
5746
5747         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5748         if (hw->mac.type == ixgbe_mac_82598EB) {
5749                 if (direction == -1)
5750                         direction = 0;
5751                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5752                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5753                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5754                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5755                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5756         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5757                         (hw->mac.type == ixgbe_mac_X540)) {
5758                 if (direction == -1) {
5759                         /* other causes */
5760                         idx = ((queue & 1) * 8);
5761                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5762                         tmp &= ~(0xFF << idx);
5763                         tmp |= (msix_vector << idx);
5764                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5765                 } else {
5766                         /* rx or tx causes */
5767                         idx = ((16 * (queue & 1)) + (8 * direction));
5768                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5769                         tmp &= ~(0xFF << idx);
5770                         tmp |= (msix_vector << idx);
5771                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5772                 }
5773         }
5774 }
5775
5776 static void
5777 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5778 {
5779         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5780         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5781         struct ixgbe_hw *hw =
5782                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5783         uint32_t q_idx;
5784         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5785
5786         /* Configure VF other cause ivar */
5787         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5788
5789         /* won't configure msix register if no mapping is done
5790          * between intr vector and event fd.
5791          */
5792         if (!rte_intr_dp_is_en(intr_handle))
5793                 return;
5794
5795         /* Configure all RX queues of VF */
5796         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5797                 /* Force all queue use vector 0,
5798                  * as IXGBE_VF_MAXMSIVECOTR = 1
5799                  */
5800                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5801                 intr_handle->intr_vec[q_idx] = vector_idx;
5802         }
5803 }
5804
5805 /**
5806  * Sets up the hardware to properly generate MSI-X interrupts
5807  * @hw
5808  *  board private structure
5809  */
5810 static void
5811 ixgbe_configure_msix(struct rte_eth_dev *dev)
5812 {
5813         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5814         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5815         struct ixgbe_hw *hw =
5816                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5817         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5818         uint32_t vec = IXGBE_MISC_VEC_ID;
5819         uint32_t mask;
5820         uint32_t gpie;
5821
5822         /* won't configure msix register if no mapping is done
5823          * between intr vector and event fd
5824          */
5825         if (!rte_intr_dp_is_en(intr_handle))
5826                 return;
5827
5828         if (rte_intr_allow_others(intr_handle))
5829                 vec = base = IXGBE_RX_VEC_START;
5830
5831         /* setup GPIE for MSI-x mode */
5832         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5833         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5834                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5835         /* auto clearing and auto setting corresponding bits in EIMS
5836          * when MSI-X interrupt is triggered
5837          */
5838         if (hw->mac.type == ixgbe_mac_82598EB) {
5839                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5840         } else {
5841                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5842                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5843         }
5844         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5845
5846         /* Populate the IVAR table and set the ITR values to the
5847          * corresponding register.
5848          */
5849         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5850              queue_id++) {
5851                 /* by default, 1:1 mapping */
5852                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5853                 intr_handle->intr_vec[queue_id] = vec;
5854                 if (vec < base + intr_handle->nb_efd - 1)
5855                         vec++;
5856         }
5857
5858         switch (hw->mac.type) {
5859         case ixgbe_mac_82598EB:
5860                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5861                                    IXGBE_MISC_VEC_ID);
5862                 break;
5863         case ixgbe_mac_82599EB:
5864         case ixgbe_mac_X540:
5865                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5866                 break;
5867         default:
5868                 break;
5869         }
5870         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5871                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5872
5873         /* set up to autoclear timer, and the vectors */
5874         mask = IXGBE_EIMS_ENABLE_MASK;
5875         mask &= ~(IXGBE_EIMS_OTHER |
5876                   IXGBE_EIMS_MAILBOX |
5877                   IXGBE_EIMS_LSC);
5878
5879         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5880 }
5881
5882 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5883         uint16_t queue_idx, uint16_t tx_rate)
5884 {
5885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5886         uint32_t rf_dec, rf_int;
5887         uint32_t bcnrc_val;
5888         uint16_t link_speed = dev->data->dev_link.link_speed;
5889
5890         if (queue_idx >= hw->mac.max_tx_queues)
5891                 return -EINVAL;
5892
5893         if (tx_rate != 0) {
5894                 /* Calculate the rate factor values to set */
5895                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5896                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5897                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5898
5899                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5900                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5901                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5902                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5903         } else {
5904                 bcnrc_val = 0;
5905         }
5906
5907         /*
5908          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5909          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5910          * set as 0x4.
5911          */
5912         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5913                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5914                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5915                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5916                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5917         else
5918                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5919                         IXGBE_MMW_SIZE_DEFAULT);
5920
5921         /* Set RTTBCNRC of queue X */
5922         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5923         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5924         IXGBE_WRITE_FLUSH(hw);
5925
5926         return 0;
5927 }
5928
5929 static void
5930 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5931                      __attribute__((unused)) uint32_t index,
5932                      __attribute__((unused)) uint32_t pool)
5933 {
5934         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5935         int diag;
5936
5937         /*
5938          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5939          * operation. Trap this case to avoid exhausting the [very limited]
5940          * set of PF resources used to store VF MAC addresses.
5941          */
5942         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5943                 return;
5944         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5945         if (diag == 0)
5946                 return;
5947         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5948 }
5949
5950 static void
5951 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5952 {
5953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5954         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5955         struct ether_addr *mac_addr;
5956         uint32_t i;
5957         int diag;
5958
5959         /*
5960          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5961          * not support the deletion of a given MAC address.
5962          * Instead, it imposes to delete all MAC addresses, then to add again
5963          * all MAC addresses with the exception of the one to be deleted.
5964          */
5965         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5966
5967         /*
5968          * Add again all MAC addresses, with the exception of the deleted one
5969          * and of the permanent MAC address.
5970          */
5971         for (i = 0, mac_addr = dev->data->mac_addrs;
5972              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5973                 /* Skip the deleted MAC address */
5974                 if (i == index)
5975                         continue;
5976                 /* Skip NULL MAC addresses */
5977                 if (is_zero_ether_addr(mac_addr))
5978                         continue;
5979                 /* Skip the permanent MAC address */
5980                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5981                         continue;
5982                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5983                 if (diag != 0)
5984                         PMD_DRV_LOG(ERR,
5985                                     "Adding again MAC address "
5986                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5987                                     "diag=%d",
5988                                     mac_addr->addr_bytes[0],
5989                                     mac_addr->addr_bytes[1],
5990                                     mac_addr->addr_bytes[2],
5991                                     mac_addr->addr_bytes[3],
5992                                     mac_addr->addr_bytes[4],
5993                                     mac_addr->addr_bytes[5],
5994                                     diag);
5995         }
5996 }
5997
5998 static void
5999 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6000 {
6001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6002
6003         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6004 }
6005
6006 int
6007 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6008                         struct rte_eth_syn_filter *filter,
6009                         bool add)
6010 {
6011         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6012         struct ixgbe_filter_info *filter_info =
6013                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6014         uint32_t syn_info;
6015         uint32_t synqf;
6016
6017         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6018                 return -EINVAL;
6019
6020         syn_info = filter_info->syn_info;
6021
6022         if (add) {
6023                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6024                         return -EINVAL;
6025                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6026                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6027
6028                 if (filter->hig_pri)
6029                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6030                 else
6031                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6032         } else {
6033                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6034                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6035                         return -ENOENT;
6036                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6037         }
6038
6039         filter_info->syn_info = synqf;
6040         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6041         IXGBE_WRITE_FLUSH(hw);
6042         return 0;
6043 }
6044
6045 static int
6046 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6047                         struct rte_eth_syn_filter *filter)
6048 {
6049         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6050         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6051
6052         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6053                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6054                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6055                 return 0;
6056         }
6057         return -ENOENT;
6058 }
6059
6060 static int
6061 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6062                         enum rte_filter_op filter_op,
6063                         void *arg)
6064 {
6065         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6066         int ret;
6067
6068         MAC_TYPE_FILTER_SUP(hw->mac.type);
6069
6070         if (filter_op == RTE_ETH_FILTER_NOP)
6071                 return 0;
6072
6073         if (arg == NULL) {
6074                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6075                             filter_op);
6076                 return -EINVAL;
6077         }
6078
6079         switch (filter_op) {
6080         case RTE_ETH_FILTER_ADD:
6081                 ret = ixgbe_syn_filter_set(dev,
6082                                 (struct rte_eth_syn_filter *)arg,
6083                                 TRUE);
6084                 break;
6085         case RTE_ETH_FILTER_DELETE:
6086                 ret = ixgbe_syn_filter_set(dev,
6087                                 (struct rte_eth_syn_filter *)arg,
6088                                 FALSE);
6089                 break;
6090         case RTE_ETH_FILTER_GET:
6091                 ret = ixgbe_syn_filter_get(dev,
6092                                 (struct rte_eth_syn_filter *)arg);
6093                 break;
6094         default:
6095                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6096                 ret = -EINVAL;
6097                 break;
6098         }
6099
6100         return ret;
6101 }
6102
6103
6104 static inline enum ixgbe_5tuple_protocol
6105 convert_protocol_type(uint8_t protocol_value)
6106 {
6107         if (protocol_value == IPPROTO_TCP)
6108                 return IXGBE_FILTER_PROTOCOL_TCP;
6109         else if (protocol_value == IPPROTO_UDP)
6110                 return IXGBE_FILTER_PROTOCOL_UDP;
6111         else if (protocol_value == IPPROTO_SCTP)
6112                 return IXGBE_FILTER_PROTOCOL_SCTP;
6113         else
6114                 return IXGBE_FILTER_PROTOCOL_NONE;
6115 }
6116
6117 /* inject a 5-tuple filter to HW */
6118 static inline void
6119 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6120                            struct ixgbe_5tuple_filter *filter)
6121 {
6122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6123         int i;
6124         uint32_t ftqf, sdpqf;
6125         uint32_t l34timir = 0;
6126         uint8_t mask = 0xff;
6127
6128         i = filter->index;
6129
6130         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6131                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6132         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6133
6134         ftqf = (uint32_t)(filter->filter_info.proto &
6135                 IXGBE_FTQF_PROTOCOL_MASK);
6136         ftqf |= (uint32_t)((filter->filter_info.priority &
6137                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6138         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6139                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6140         if (filter->filter_info.dst_ip_mask == 0)
6141                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6142         if (filter->filter_info.src_port_mask == 0)
6143                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6144         if (filter->filter_info.dst_port_mask == 0)
6145                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6146         if (filter->filter_info.proto_mask == 0)
6147                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6148         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6149         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6150         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6151
6152         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6153         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6154         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6155         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6156
6157         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6158         l34timir |= (uint32_t)(filter->queue <<
6159                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6160         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6161 }
6162
6163 /*
6164  * add a 5tuple filter
6165  *
6166  * @param
6167  * dev: Pointer to struct rte_eth_dev.
6168  * index: the index the filter allocates.
6169  * filter: ponter to the filter that will be added.
6170  * rx_queue: the queue id the filter assigned to.
6171  *
6172  * @return
6173  *    - On success, zero.
6174  *    - On failure, a negative value.
6175  */
6176 static int
6177 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6178                         struct ixgbe_5tuple_filter *filter)
6179 {
6180         struct ixgbe_filter_info *filter_info =
6181                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6182         int i, idx, shift;
6183
6184         /*
6185          * look for an unused 5tuple filter index,
6186          * and insert the filter to list.
6187          */
6188         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6189                 idx = i / (sizeof(uint32_t) * NBBY);
6190                 shift = i % (sizeof(uint32_t) * NBBY);
6191                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6192                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6193                         filter->index = i;
6194                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6195                                           filter,
6196                                           entries);
6197                         break;
6198                 }
6199         }
6200         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6201                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6202                 return -ENOSYS;
6203         }
6204
6205         ixgbe_inject_5tuple_filter(dev, filter);
6206
6207         return 0;
6208 }
6209
6210 /*
6211  * remove a 5tuple filter
6212  *
6213  * @param
6214  * dev: Pointer to struct rte_eth_dev.
6215  * filter: the pointer of the filter will be removed.
6216  */
6217 static void
6218 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6219                         struct ixgbe_5tuple_filter *filter)
6220 {
6221         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6222         struct ixgbe_filter_info *filter_info =
6223                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6224         uint16_t index = filter->index;
6225
6226         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6227                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6228         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6229         rte_free(filter);
6230
6231         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6232         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6233         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6234         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6235         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6236 }
6237
6238 static int
6239 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6240 {
6241         struct ixgbe_hw *hw;
6242         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6243
6244         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6245
6246         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6247                 return -EINVAL;
6248
6249         /* refuse mtu that requires the support of scattered packets when this
6250          * feature has not been enabled before.
6251          */
6252         if (!dev->data->scattered_rx &&
6253             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6254              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6255                 return -EINVAL;
6256
6257         /*
6258          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6259          * request of the version 2.0 of the mailbox API.
6260          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6261          * of the mailbox API.
6262          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6263          * prior to 3.11.33 which contains the following change:
6264          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6265          */
6266         ixgbevf_rlpml_set_vf(hw, max_frame);
6267
6268         /* update max frame size */
6269         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6270         return 0;
6271 }
6272
6273 static inline struct ixgbe_5tuple_filter *
6274 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6275                         struct ixgbe_5tuple_filter_info *key)
6276 {
6277         struct ixgbe_5tuple_filter *it;
6278
6279         TAILQ_FOREACH(it, filter_list, entries) {
6280                 if (memcmp(key, &it->filter_info,
6281                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6282                         return it;
6283                 }
6284         }
6285         return NULL;
6286 }
6287
6288 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6289 static inline int
6290 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6291                         struct ixgbe_5tuple_filter_info *filter_info)
6292 {
6293         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6294                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6295                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6296                 return -EINVAL;
6297
6298         switch (filter->dst_ip_mask) {
6299         case UINT32_MAX:
6300                 filter_info->dst_ip_mask = 0;
6301                 filter_info->dst_ip = filter->dst_ip;
6302                 break;
6303         case 0:
6304                 filter_info->dst_ip_mask = 1;
6305                 break;
6306         default:
6307                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6308                 return -EINVAL;
6309         }
6310
6311         switch (filter->src_ip_mask) {
6312         case UINT32_MAX:
6313                 filter_info->src_ip_mask = 0;
6314                 filter_info->src_ip = filter->src_ip;
6315                 break;
6316         case 0:
6317                 filter_info->src_ip_mask = 1;
6318                 break;
6319         default:
6320                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6321                 return -EINVAL;
6322         }
6323
6324         switch (filter->dst_port_mask) {
6325         case UINT16_MAX:
6326                 filter_info->dst_port_mask = 0;
6327                 filter_info->dst_port = filter->dst_port;
6328                 break;
6329         case 0:
6330                 filter_info->dst_port_mask = 1;
6331                 break;
6332         default:
6333                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6334                 return -EINVAL;
6335         }
6336
6337         switch (filter->src_port_mask) {
6338         case UINT16_MAX:
6339                 filter_info->src_port_mask = 0;
6340                 filter_info->src_port = filter->src_port;
6341                 break;
6342         case 0:
6343                 filter_info->src_port_mask = 1;
6344                 break;
6345         default:
6346                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6347                 return -EINVAL;
6348         }
6349
6350         switch (filter->proto_mask) {
6351         case UINT8_MAX:
6352                 filter_info->proto_mask = 0;
6353                 filter_info->proto =
6354                         convert_protocol_type(filter->proto);
6355                 break;
6356         case 0:
6357                 filter_info->proto_mask = 1;
6358                 break;
6359         default:
6360                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6361                 return -EINVAL;
6362         }
6363
6364         filter_info->priority = (uint8_t)filter->priority;
6365         return 0;
6366 }
6367
6368 /*
6369  * add or delete a ntuple filter
6370  *
6371  * @param
6372  * dev: Pointer to struct rte_eth_dev.
6373  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6374  * add: if true, add filter, if false, remove filter
6375  *
6376  * @return
6377  *    - On success, zero.
6378  *    - On failure, a negative value.
6379  */
6380 int
6381 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6382                         struct rte_eth_ntuple_filter *ntuple_filter,
6383                         bool add)
6384 {
6385         struct ixgbe_filter_info *filter_info =
6386                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6387         struct ixgbe_5tuple_filter_info filter_5tuple;
6388         struct ixgbe_5tuple_filter *filter;
6389         int ret;
6390
6391         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6392                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6393                 return -EINVAL;
6394         }
6395
6396         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6397         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6398         if (ret < 0)
6399                 return ret;
6400
6401         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6402                                          &filter_5tuple);
6403         if (filter != NULL && add) {
6404                 PMD_DRV_LOG(ERR, "filter exists.");
6405                 return -EEXIST;
6406         }
6407         if (filter == NULL && !add) {
6408                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6409                 return -ENOENT;
6410         }
6411
6412         if (add) {
6413                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6414                                 sizeof(struct ixgbe_5tuple_filter), 0);
6415                 if (filter == NULL)
6416                         return -ENOMEM;
6417                 (void)rte_memcpy(&filter->filter_info,
6418                                  &filter_5tuple,
6419                                  sizeof(struct ixgbe_5tuple_filter_info));
6420                 filter->queue = ntuple_filter->queue;
6421                 ret = ixgbe_add_5tuple_filter(dev, filter);
6422                 if (ret < 0) {
6423                         rte_free(filter);
6424                         return ret;
6425                 }
6426         } else
6427                 ixgbe_remove_5tuple_filter(dev, filter);
6428
6429         return 0;
6430 }
6431
6432 /*
6433  * get a ntuple filter
6434  *
6435  * @param
6436  * dev: Pointer to struct rte_eth_dev.
6437  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6438  *
6439  * @return
6440  *    - On success, zero.
6441  *    - On failure, a negative value.
6442  */
6443 static int
6444 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6445                         struct rte_eth_ntuple_filter *ntuple_filter)
6446 {
6447         struct ixgbe_filter_info *filter_info =
6448                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6449         struct ixgbe_5tuple_filter_info filter_5tuple;
6450         struct ixgbe_5tuple_filter *filter;
6451         int ret;
6452
6453         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6454                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6455                 return -EINVAL;
6456         }
6457
6458         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6459         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6460         if (ret < 0)
6461                 return ret;
6462
6463         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6464                                          &filter_5tuple);
6465         if (filter == NULL) {
6466                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6467                 return -ENOENT;
6468         }
6469         ntuple_filter->queue = filter->queue;
6470         return 0;
6471 }
6472
6473 /*
6474  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6475  * @dev: pointer to rte_eth_dev structure
6476  * @filter_op:operation will be taken.
6477  * @arg: a pointer to specific structure corresponding to the filter_op
6478  *
6479  * @return
6480  *    - On success, zero.
6481  *    - On failure, a negative value.
6482  */
6483 static int
6484 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6485                                 enum rte_filter_op filter_op,
6486                                 void *arg)
6487 {
6488         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6489         int ret;
6490
6491         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6492
6493         if (filter_op == RTE_ETH_FILTER_NOP)
6494                 return 0;
6495
6496         if (arg == NULL) {
6497                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6498                             filter_op);
6499                 return -EINVAL;
6500         }
6501
6502         switch (filter_op) {
6503         case RTE_ETH_FILTER_ADD:
6504                 ret = ixgbe_add_del_ntuple_filter(dev,
6505                         (struct rte_eth_ntuple_filter *)arg,
6506                         TRUE);
6507                 break;
6508         case RTE_ETH_FILTER_DELETE:
6509                 ret = ixgbe_add_del_ntuple_filter(dev,
6510                         (struct rte_eth_ntuple_filter *)arg,
6511                         FALSE);
6512                 break;
6513         case RTE_ETH_FILTER_GET:
6514                 ret = ixgbe_get_ntuple_filter(dev,
6515                         (struct rte_eth_ntuple_filter *)arg);
6516                 break;
6517         default:
6518                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6519                 ret = -EINVAL;
6520                 break;
6521         }
6522         return ret;
6523 }
6524
6525 int
6526 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6527                         struct rte_eth_ethertype_filter *filter,
6528                         bool add)
6529 {
6530         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6531         struct ixgbe_filter_info *filter_info =
6532                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6533         uint32_t etqf = 0;
6534         uint32_t etqs = 0;
6535         int ret;
6536         struct ixgbe_ethertype_filter ethertype_filter;
6537
6538         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6539                 return -EINVAL;
6540
6541         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6542                 filter->ether_type == ETHER_TYPE_IPv6) {
6543                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6544                         " ethertype filter.", filter->ether_type);
6545                 return -EINVAL;
6546         }
6547
6548         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6549                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6550                 return -EINVAL;
6551         }
6552         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6553                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6554                 return -EINVAL;
6555         }
6556
6557         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6558         if (ret >= 0 && add) {
6559                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6560                             filter->ether_type);
6561                 return -EEXIST;
6562         }
6563         if (ret < 0 && !add) {
6564                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6565                             filter->ether_type);
6566                 return -ENOENT;
6567         }
6568
6569         if (add) {
6570                 etqf = IXGBE_ETQF_FILTER_EN;
6571                 etqf |= (uint32_t)filter->ether_type;
6572                 etqs |= (uint32_t)((filter->queue <<
6573                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6574                                     IXGBE_ETQS_RX_QUEUE);
6575                 etqs |= IXGBE_ETQS_QUEUE_EN;
6576
6577                 ethertype_filter.ethertype = filter->ether_type;
6578                 ethertype_filter.etqf = etqf;
6579                 ethertype_filter.etqs = etqs;
6580                 ethertype_filter.conf = FALSE;
6581                 ret = ixgbe_ethertype_filter_insert(filter_info,
6582                                                     &ethertype_filter);
6583                 if (ret < 0) {
6584                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6585                         return -ENOSPC;
6586                 }
6587         } else {
6588                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6589                 if (ret < 0)
6590                         return -ENOSYS;
6591         }
6592         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6593         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6594         IXGBE_WRITE_FLUSH(hw);
6595
6596         return 0;
6597 }
6598
6599 static int
6600 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6601                         struct rte_eth_ethertype_filter *filter)
6602 {
6603         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6604         struct ixgbe_filter_info *filter_info =
6605                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6606         uint32_t etqf, etqs;
6607         int ret;
6608
6609         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6610         if (ret < 0) {
6611                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6612                             filter->ether_type);
6613                 return -ENOENT;
6614         }
6615
6616         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6617         if (etqf & IXGBE_ETQF_FILTER_EN) {
6618                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6619                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6620                 filter->flags = 0;
6621                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6622                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6623                 return 0;
6624         }
6625         return -ENOENT;
6626 }
6627
6628 /*
6629  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6630  * @dev: pointer to rte_eth_dev structure
6631  * @filter_op:operation will be taken.
6632  * @arg: a pointer to specific structure corresponding to the filter_op
6633  */
6634 static int
6635 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6636                                 enum rte_filter_op filter_op,
6637                                 void *arg)
6638 {
6639         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6640         int ret;
6641
6642         MAC_TYPE_FILTER_SUP(hw->mac.type);
6643
6644         if (filter_op == RTE_ETH_FILTER_NOP)
6645                 return 0;
6646
6647         if (arg == NULL) {
6648                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6649                             filter_op);
6650                 return -EINVAL;
6651         }
6652
6653         switch (filter_op) {
6654         case RTE_ETH_FILTER_ADD:
6655                 ret = ixgbe_add_del_ethertype_filter(dev,
6656                         (struct rte_eth_ethertype_filter *)arg,
6657                         TRUE);
6658                 break;
6659         case RTE_ETH_FILTER_DELETE:
6660                 ret = ixgbe_add_del_ethertype_filter(dev,
6661                         (struct rte_eth_ethertype_filter *)arg,
6662                         FALSE);
6663                 break;
6664         case RTE_ETH_FILTER_GET:
6665                 ret = ixgbe_get_ethertype_filter(dev,
6666                         (struct rte_eth_ethertype_filter *)arg);
6667                 break;
6668         default:
6669                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6670                 ret = -EINVAL;
6671                 break;
6672         }
6673         return ret;
6674 }
6675
6676 static int
6677 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6678                      enum rte_filter_type filter_type,
6679                      enum rte_filter_op filter_op,
6680                      void *arg)
6681 {
6682         int ret = 0;
6683
6684         switch (filter_type) {
6685         case RTE_ETH_FILTER_NTUPLE:
6686                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6687                 break;
6688         case RTE_ETH_FILTER_ETHERTYPE:
6689                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6690                 break;
6691         case RTE_ETH_FILTER_SYN:
6692                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6693                 break;
6694         case RTE_ETH_FILTER_FDIR:
6695                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6696                 break;
6697         case RTE_ETH_FILTER_L2_TUNNEL:
6698                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6699                 break;
6700         case RTE_ETH_FILTER_GENERIC:
6701                 if (filter_op != RTE_ETH_FILTER_GET)
6702                         return -EINVAL;
6703                 *(const void **)arg = &ixgbe_flow_ops;
6704                 break;
6705         default:
6706                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6707                                                         filter_type);
6708                 ret = -EINVAL;
6709                 break;
6710         }
6711
6712         return ret;
6713 }
6714
6715 static u8 *
6716 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6717                         u8 **mc_addr_ptr, u32 *vmdq)
6718 {
6719         u8 *mc_addr;
6720
6721         *vmdq = 0;
6722         mc_addr = *mc_addr_ptr;
6723         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6724         return mc_addr;
6725 }
6726
6727 static int
6728 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6729                           struct ether_addr *mc_addr_set,
6730                           uint32_t nb_mc_addr)
6731 {
6732         struct ixgbe_hw *hw;
6733         u8 *mc_addr_list;
6734
6735         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6736         mc_addr_list = (u8 *)mc_addr_set;
6737         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6738                                          ixgbe_dev_addr_list_itr, TRUE);
6739 }
6740
6741 static uint64_t
6742 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6743 {
6744         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6745         uint64_t systime_cycles;
6746
6747         switch (hw->mac.type) {
6748         case ixgbe_mac_X550:
6749         case ixgbe_mac_X550EM_x:
6750         case ixgbe_mac_X550EM_a:
6751                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6752                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6753                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6754                                 * NSEC_PER_SEC;
6755                 break;
6756         default:
6757                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6758                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6759                                 << 32;
6760         }
6761
6762         return systime_cycles;
6763 }
6764
6765 static uint64_t
6766 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6767 {
6768         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6769         uint64_t rx_tstamp_cycles;
6770
6771         switch (hw->mac.type) {
6772         case ixgbe_mac_X550:
6773         case ixgbe_mac_X550EM_x:
6774         case ixgbe_mac_X550EM_a:
6775                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6776                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6777                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6778                                 * NSEC_PER_SEC;
6779                 break;
6780         default:
6781                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6782                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6783                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6784                                 << 32;
6785         }
6786
6787         return rx_tstamp_cycles;
6788 }
6789
6790 static uint64_t
6791 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6792 {
6793         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6794         uint64_t tx_tstamp_cycles;
6795
6796         switch (hw->mac.type) {
6797         case ixgbe_mac_X550:
6798         case ixgbe_mac_X550EM_x:
6799         case ixgbe_mac_X550EM_a:
6800                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6801                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6802                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6803                                 * NSEC_PER_SEC;
6804                 break;
6805         default:
6806                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6807                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6808                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6809                                 << 32;
6810         }
6811
6812         return tx_tstamp_cycles;
6813 }
6814
6815 static void
6816 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6817 {
6818         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6819         struct ixgbe_adapter *adapter =
6820                 (struct ixgbe_adapter *)dev->data->dev_private;
6821         struct rte_eth_link link;
6822         uint32_t incval = 0;
6823         uint32_t shift = 0;
6824
6825         /* Get current link speed. */
6826         memset(&link, 0, sizeof(link));
6827         ixgbe_dev_link_update(dev, 1);
6828         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6829
6830         switch (link.link_speed) {
6831         case ETH_SPEED_NUM_100M:
6832                 incval = IXGBE_INCVAL_100;
6833                 shift = IXGBE_INCVAL_SHIFT_100;
6834                 break;
6835         case ETH_SPEED_NUM_1G:
6836                 incval = IXGBE_INCVAL_1GB;
6837                 shift = IXGBE_INCVAL_SHIFT_1GB;
6838                 break;
6839         case ETH_SPEED_NUM_10G:
6840         default:
6841                 incval = IXGBE_INCVAL_10GB;
6842                 shift = IXGBE_INCVAL_SHIFT_10GB;
6843                 break;
6844         }
6845
6846         switch (hw->mac.type) {
6847         case ixgbe_mac_X550:
6848         case ixgbe_mac_X550EM_x:
6849         case ixgbe_mac_X550EM_a:
6850                 /* Independent of link speed. */
6851                 incval = 1;
6852                 /* Cycles read will be interpreted as ns. */
6853                 shift = 0;
6854                 /* Fall-through */
6855         case ixgbe_mac_X540:
6856                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6857                 break;
6858         case ixgbe_mac_82599EB:
6859                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6860                 shift -= IXGBE_INCVAL_SHIFT_82599;
6861                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6862                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6863                 break;
6864         default:
6865                 /* Not supported. */
6866                 return;
6867         }
6868
6869         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6870         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6871         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6872
6873         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6874         adapter->systime_tc.cc_shift = shift;
6875         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6876
6877         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6878         adapter->rx_tstamp_tc.cc_shift = shift;
6879         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6880
6881         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6882         adapter->tx_tstamp_tc.cc_shift = shift;
6883         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6884 }
6885
6886 static int
6887 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6888 {
6889         struct ixgbe_adapter *adapter =
6890                         (struct ixgbe_adapter *)dev->data->dev_private;
6891
6892         adapter->systime_tc.nsec += delta;
6893         adapter->rx_tstamp_tc.nsec += delta;
6894         adapter->tx_tstamp_tc.nsec += delta;
6895
6896         return 0;
6897 }
6898
6899 static int
6900 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6901 {
6902         uint64_t ns;
6903         struct ixgbe_adapter *adapter =
6904                         (struct ixgbe_adapter *)dev->data->dev_private;
6905
6906         ns = rte_timespec_to_ns(ts);
6907         /* Set the timecounters to a new value. */
6908         adapter->systime_tc.nsec = ns;
6909         adapter->rx_tstamp_tc.nsec = ns;
6910         adapter->tx_tstamp_tc.nsec = ns;
6911
6912         return 0;
6913 }
6914
6915 static int
6916 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6917 {
6918         uint64_t ns, systime_cycles;
6919         struct ixgbe_adapter *adapter =
6920                         (struct ixgbe_adapter *)dev->data->dev_private;
6921
6922         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6923         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6924         *ts = rte_ns_to_timespec(ns);
6925
6926         return 0;
6927 }
6928
6929 static int
6930 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6931 {
6932         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6933         uint32_t tsync_ctl;
6934         uint32_t tsauxc;
6935
6936         /* Stop the timesync system time. */
6937         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6938         /* Reset the timesync system time value. */
6939         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6940         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6941
6942         /* Enable system time for platforms where it isn't on by default. */
6943         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6944         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6945         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6946
6947         ixgbe_start_timecounters(dev);
6948
6949         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6950         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6951                         (ETHER_TYPE_1588 |
6952                          IXGBE_ETQF_FILTER_EN |
6953                          IXGBE_ETQF_1588));
6954
6955         /* Enable timestamping of received PTP packets. */
6956         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6957         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6958         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6959
6960         /* Enable timestamping of transmitted PTP packets. */
6961         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6962         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6963         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6964
6965         IXGBE_WRITE_FLUSH(hw);
6966
6967         return 0;
6968 }
6969
6970 static int
6971 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6972 {
6973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6974         uint32_t tsync_ctl;
6975
6976         /* Disable timestamping of transmitted PTP packets. */
6977         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6978         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6979         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6980
6981         /* Disable timestamping of received PTP packets. */
6982         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6983         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6984         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6985
6986         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6987         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6988
6989         /* Stop incrementating the System Time registers. */
6990         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6991
6992         return 0;
6993 }
6994
6995 static int
6996 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6997                                  struct timespec *timestamp,
6998                                  uint32_t flags __rte_unused)
6999 {
7000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7001         struct ixgbe_adapter *adapter =
7002                 (struct ixgbe_adapter *)dev->data->dev_private;
7003         uint32_t tsync_rxctl;
7004         uint64_t rx_tstamp_cycles;
7005         uint64_t ns;
7006
7007         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7008         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7009                 return -EINVAL;
7010
7011         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7012         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7013         *timestamp = rte_ns_to_timespec(ns);
7014
7015         return  0;
7016 }
7017
7018 static int
7019 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7020                                  struct timespec *timestamp)
7021 {
7022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7023         struct ixgbe_adapter *adapter =
7024                 (struct ixgbe_adapter *)dev->data->dev_private;
7025         uint32_t tsync_txctl;
7026         uint64_t tx_tstamp_cycles;
7027         uint64_t ns;
7028
7029         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7030         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7031                 return -EINVAL;
7032
7033         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7034         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7035         *timestamp = rte_ns_to_timespec(ns);
7036
7037         return 0;
7038 }
7039
7040 static int
7041 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7042 {
7043         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7044         int count = 0;
7045         int g_ind = 0;
7046         const struct reg_info *reg_group;
7047         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7048                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7049
7050         while ((reg_group = reg_set[g_ind++]))
7051                 count += ixgbe_regs_group_count(reg_group);
7052
7053         return count;
7054 }
7055
7056 static int
7057 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7058 {
7059         int count = 0;
7060         int g_ind = 0;
7061         const struct reg_info *reg_group;
7062
7063         while ((reg_group = ixgbevf_regs[g_ind++]))
7064                 count += ixgbe_regs_group_count(reg_group);
7065
7066         return count;
7067 }
7068
7069 static int
7070 ixgbe_get_regs(struct rte_eth_dev *dev,
7071               struct rte_dev_reg_info *regs)
7072 {
7073         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7074         uint32_t *data = regs->data;
7075         int g_ind = 0;
7076         int count = 0;
7077         const struct reg_info *reg_group;
7078         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7079                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7080
7081         if (data == NULL) {
7082                 regs->length = ixgbe_get_reg_length(dev);
7083                 regs->width = sizeof(uint32_t);
7084                 return 0;
7085         }
7086
7087         /* Support only full register dump */
7088         if ((regs->length == 0) ||
7089             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7090                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7091                         hw->device_id;
7092                 while ((reg_group = reg_set[g_ind++]))
7093                         count += ixgbe_read_regs_group(dev, &data[count],
7094                                 reg_group);
7095                 return 0;
7096         }
7097
7098         return -ENOTSUP;
7099 }
7100
7101 static int
7102 ixgbevf_get_regs(struct rte_eth_dev *dev,
7103                 struct rte_dev_reg_info *regs)
7104 {
7105         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7106         uint32_t *data = regs->data;
7107         int g_ind = 0;
7108         int count = 0;
7109         const struct reg_info *reg_group;
7110
7111         if (data == NULL) {
7112                 regs->length = ixgbevf_get_reg_length(dev);
7113                 regs->width = sizeof(uint32_t);
7114                 return 0;
7115         }
7116
7117         /* Support only full register dump */
7118         if ((regs->length == 0) ||
7119             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7120                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7121                         hw->device_id;
7122                 while ((reg_group = ixgbevf_regs[g_ind++]))
7123                         count += ixgbe_read_regs_group(dev, &data[count],
7124                                                       reg_group);
7125                 return 0;
7126         }
7127
7128         return -ENOTSUP;
7129 }
7130
7131 static int
7132 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7133 {
7134         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7135
7136         /* Return unit is byte count */
7137         return hw->eeprom.word_size * 2;
7138 }
7139
7140 static int
7141 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7142                 struct rte_dev_eeprom_info *in_eeprom)
7143 {
7144         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7145         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7146         uint16_t *data = in_eeprom->data;
7147         int first, length;
7148
7149         first = in_eeprom->offset >> 1;
7150         length = in_eeprom->length >> 1;
7151         if ((first > hw->eeprom.word_size) ||
7152             ((first + length) > hw->eeprom.word_size))
7153                 return -EINVAL;
7154
7155         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7156
7157         return eeprom->ops.read_buffer(hw, first, length, data);
7158 }
7159
7160 static int
7161 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7162                 struct rte_dev_eeprom_info *in_eeprom)
7163 {
7164         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7165         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7166         uint16_t *data = in_eeprom->data;
7167         int first, length;
7168
7169         first = in_eeprom->offset >> 1;
7170         length = in_eeprom->length >> 1;
7171         if ((first > hw->eeprom.word_size) ||
7172             ((first + length) > hw->eeprom.word_size))
7173                 return -EINVAL;
7174
7175         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7176
7177         return eeprom->ops.write_buffer(hw,  first, length, data);
7178 }
7179
7180 uint16_t
7181 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7182         switch (mac_type) {
7183         case ixgbe_mac_X550:
7184         case ixgbe_mac_X550EM_x:
7185         case ixgbe_mac_X550EM_a:
7186                 return ETH_RSS_RETA_SIZE_512;
7187         case ixgbe_mac_X550_vf:
7188         case ixgbe_mac_X550EM_x_vf:
7189         case ixgbe_mac_X550EM_a_vf:
7190                 return ETH_RSS_RETA_SIZE_64;
7191         default:
7192                 return ETH_RSS_RETA_SIZE_128;
7193         }
7194 }
7195
7196 uint32_t
7197 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7198         switch (mac_type) {
7199         case ixgbe_mac_X550:
7200         case ixgbe_mac_X550EM_x:
7201         case ixgbe_mac_X550EM_a:
7202                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7203                         return IXGBE_RETA(reta_idx >> 2);
7204                 else
7205                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7206         case ixgbe_mac_X550_vf:
7207         case ixgbe_mac_X550EM_x_vf:
7208         case ixgbe_mac_X550EM_a_vf:
7209                 return IXGBE_VFRETA(reta_idx >> 2);
7210         default:
7211                 return IXGBE_RETA(reta_idx >> 2);
7212         }
7213 }
7214
7215 uint32_t
7216 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7217         switch (mac_type) {
7218         case ixgbe_mac_X550_vf:
7219         case ixgbe_mac_X550EM_x_vf:
7220         case ixgbe_mac_X550EM_a_vf:
7221                 return IXGBE_VFMRQC;
7222         default:
7223                 return IXGBE_MRQC;
7224         }
7225 }
7226
7227 uint32_t
7228 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7229         switch (mac_type) {
7230         case ixgbe_mac_X550_vf:
7231         case ixgbe_mac_X550EM_x_vf:
7232         case ixgbe_mac_X550EM_a_vf:
7233                 return IXGBE_VFRSSRK(i);
7234         default:
7235                 return IXGBE_RSSRK(i);
7236         }
7237 }
7238
7239 bool
7240 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7241         switch (mac_type) {
7242         case ixgbe_mac_82599_vf:
7243         case ixgbe_mac_X540_vf:
7244                 return 0;
7245         default:
7246                 return 1;
7247         }
7248 }
7249
7250 static int
7251 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7252                         struct rte_eth_dcb_info *dcb_info)
7253 {
7254         struct ixgbe_dcb_config *dcb_config =
7255                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7256         struct ixgbe_dcb_tc_config *tc;
7257         uint8_t i, j;
7258
7259         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7260                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7261         else
7262                 dcb_info->nb_tcs = 1;
7263
7264         if (dcb_config->vt_mode) { /* vt is enabled*/
7265                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7266                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7267                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7268                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7269                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7270                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7271                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7272                                                 i * dcb_info->nb_tcs + j;
7273                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7274                                 dcb_info->tc_queue.tc_txq[i][j].base =
7275                                                 i * dcb_info->nb_tcs + j;
7276                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7277                         }
7278                 }
7279         } else { /* vt is disabled*/
7280                 struct rte_eth_dcb_rx_conf *rx_conf =
7281                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7282                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7283                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7284                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7285                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7286                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7287                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7288                         }
7289                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7290                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7291                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7292                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7293                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7294                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7295                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7296                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7297                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7298                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7299                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7300                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7301                         }
7302                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7303                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7304                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7305                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7306                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7307                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7308                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7309                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7310                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7311                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7312                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7313                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7314                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7315                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7316                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7317                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7318                 }
7319         }
7320         for (i = 0; i < dcb_info->nb_tcs; i++) {
7321                 tc = &dcb_config->tc_config[i];
7322                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7323         }
7324         return 0;
7325 }
7326
7327 /* Update e-tag ether type */
7328 static int
7329 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7330                             uint16_t ether_type)
7331 {
7332         uint32_t etag_etype;
7333
7334         if (hw->mac.type != ixgbe_mac_X550 &&
7335             hw->mac.type != ixgbe_mac_X550EM_x &&
7336             hw->mac.type != ixgbe_mac_X550EM_a) {
7337                 return -ENOTSUP;
7338         }
7339
7340         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7341         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7342         etag_etype |= ether_type;
7343         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7344         IXGBE_WRITE_FLUSH(hw);
7345
7346         return 0;
7347 }
7348
7349 /* Config l2 tunnel ether type */
7350 static int
7351 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7352                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7353 {
7354         int ret = 0;
7355         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7356         struct ixgbe_l2_tn_info *l2_tn_info =
7357                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7358
7359         if (l2_tunnel == NULL)
7360                 return -EINVAL;
7361
7362         switch (l2_tunnel->l2_tunnel_type) {
7363         case RTE_L2_TUNNEL_TYPE_E_TAG:
7364                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7365                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7366                 break;
7367         default:
7368                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7369                 ret = -EINVAL;
7370                 break;
7371         }
7372
7373         return ret;
7374 }
7375
7376 /* Enable e-tag tunnel */
7377 static int
7378 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7379 {
7380         uint32_t etag_etype;
7381
7382         if (hw->mac.type != ixgbe_mac_X550 &&
7383             hw->mac.type != ixgbe_mac_X550EM_x &&
7384             hw->mac.type != ixgbe_mac_X550EM_a) {
7385                 return -ENOTSUP;
7386         }
7387
7388         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7389         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7390         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7391         IXGBE_WRITE_FLUSH(hw);
7392
7393         return 0;
7394 }
7395
7396 /* Enable l2 tunnel */
7397 static int
7398 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7399                            enum rte_eth_tunnel_type l2_tunnel_type)
7400 {
7401         int ret = 0;
7402         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7403         struct ixgbe_l2_tn_info *l2_tn_info =
7404                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7405
7406         switch (l2_tunnel_type) {
7407         case RTE_L2_TUNNEL_TYPE_E_TAG:
7408                 l2_tn_info->e_tag_en = TRUE;
7409                 ret = ixgbe_e_tag_enable(hw);
7410                 break;
7411         default:
7412                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7413                 ret = -EINVAL;
7414                 break;
7415         }
7416
7417         return ret;
7418 }
7419
7420 /* Disable e-tag tunnel */
7421 static int
7422 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7423 {
7424         uint32_t etag_etype;
7425
7426         if (hw->mac.type != ixgbe_mac_X550 &&
7427             hw->mac.type != ixgbe_mac_X550EM_x &&
7428             hw->mac.type != ixgbe_mac_X550EM_a) {
7429                 return -ENOTSUP;
7430         }
7431
7432         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7433         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7434         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7435         IXGBE_WRITE_FLUSH(hw);
7436
7437         return 0;
7438 }
7439
7440 /* Disable l2 tunnel */
7441 static int
7442 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7443                             enum rte_eth_tunnel_type l2_tunnel_type)
7444 {
7445         int ret = 0;
7446         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7447         struct ixgbe_l2_tn_info *l2_tn_info =
7448                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7449
7450         switch (l2_tunnel_type) {
7451         case RTE_L2_TUNNEL_TYPE_E_TAG:
7452                 l2_tn_info->e_tag_en = FALSE;
7453                 ret = ixgbe_e_tag_disable(hw);
7454                 break;
7455         default:
7456                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7457                 ret = -EINVAL;
7458                 break;
7459         }
7460
7461         return ret;
7462 }
7463
7464 static int
7465 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7466                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7467 {
7468         int ret = 0;
7469         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7470         uint32_t i, rar_entries;
7471         uint32_t rar_low, rar_high;
7472
7473         if (hw->mac.type != ixgbe_mac_X550 &&
7474             hw->mac.type != ixgbe_mac_X550EM_x &&
7475             hw->mac.type != ixgbe_mac_X550EM_a) {
7476                 return -ENOTSUP;
7477         }
7478
7479         rar_entries = ixgbe_get_num_rx_addrs(hw);
7480
7481         for (i = 1; i < rar_entries; i++) {
7482                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7483                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7484                 if ((rar_high & IXGBE_RAH_AV) &&
7485                     (rar_high & IXGBE_RAH_ADTYPE) &&
7486                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7487                      l2_tunnel->tunnel_id)) {
7488                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7489                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7490
7491                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7492
7493                         return ret;
7494                 }
7495         }
7496
7497         return ret;
7498 }
7499
7500 static int
7501 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7502                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7503 {
7504         int ret = 0;
7505         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7506         uint32_t i, rar_entries;
7507         uint32_t rar_low, rar_high;
7508
7509         if (hw->mac.type != ixgbe_mac_X550 &&
7510             hw->mac.type != ixgbe_mac_X550EM_x &&
7511             hw->mac.type != ixgbe_mac_X550EM_a) {
7512                 return -ENOTSUP;
7513         }
7514
7515         /* One entry for one tunnel. Try to remove potential existing entry. */
7516         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7517
7518         rar_entries = ixgbe_get_num_rx_addrs(hw);
7519
7520         for (i = 1; i < rar_entries; i++) {
7521                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7522                 if (rar_high & IXGBE_RAH_AV) {
7523                         continue;
7524                 } else {
7525                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7526                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7527                         rar_low = l2_tunnel->tunnel_id;
7528
7529                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7530                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7531
7532                         return ret;
7533                 }
7534         }
7535
7536         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7537                      " Please remove a rule before adding a new one.");
7538         return -EINVAL;
7539 }
7540
7541 static inline struct ixgbe_l2_tn_filter *
7542 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7543                           struct ixgbe_l2_tn_key *key)
7544 {
7545         int ret;
7546
7547         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7548         if (ret < 0)
7549                 return NULL;
7550
7551         return l2_tn_info->hash_map[ret];
7552 }
7553
7554 static inline int
7555 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7556                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7557 {
7558         int ret;
7559
7560         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7561                                &l2_tn_filter->key);
7562
7563         if (ret < 0) {
7564                 PMD_DRV_LOG(ERR,
7565                             "Failed to insert L2 tunnel filter"
7566                             " to hash table %d!",
7567                             ret);
7568                 return ret;
7569         }
7570
7571         l2_tn_info->hash_map[ret] = l2_tn_filter;
7572
7573         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7574
7575         return 0;
7576 }
7577
7578 static inline int
7579 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7580                           struct ixgbe_l2_tn_key *key)
7581 {
7582         int ret;
7583         struct ixgbe_l2_tn_filter *l2_tn_filter;
7584
7585         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7586
7587         if (ret < 0) {
7588                 PMD_DRV_LOG(ERR,
7589                             "No such L2 tunnel filter to delete %d!",
7590                             ret);
7591                 return ret;
7592         }
7593
7594         l2_tn_filter = l2_tn_info->hash_map[ret];
7595         l2_tn_info->hash_map[ret] = NULL;
7596
7597         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7598         rte_free(l2_tn_filter);
7599
7600         return 0;
7601 }
7602
7603 /* Add l2 tunnel filter */
7604 int
7605 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7606                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7607                                bool restore)
7608 {
7609         int ret;
7610         struct ixgbe_l2_tn_info *l2_tn_info =
7611                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7612         struct ixgbe_l2_tn_key key;
7613         struct ixgbe_l2_tn_filter *node;
7614
7615         if (!restore) {
7616                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7617                 key.tn_id = l2_tunnel->tunnel_id;
7618
7619                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7620
7621                 if (node) {
7622                         PMD_DRV_LOG(ERR,
7623                                     "The L2 tunnel filter already exists!");
7624                         return -EINVAL;
7625                 }
7626
7627                 node = rte_zmalloc("ixgbe_l2_tn",
7628                                    sizeof(struct ixgbe_l2_tn_filter),
7629                                    0);
7630                 if (!node)
7631                         return -ENOMEM;
7632
7633                 (void)rte_memcpy(&node->key,
7634                                  &key,
7635                                  sizeof(struct ixgbe_l2_tn_key));
7636                 node->pool = l2_tunnel->pool;
7637                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7638                 if (ret < 0) {
7639                         rte_free(node);
7640                         return ret;
7641                 }
7642         }
7643
7644         switch (l2_tunnel->l2_tunnel_type) {
7645         case RTE_L2_TUNNEL_TYPE_E_TAG:
7646                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7647                 break;
7648         default:
7649                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7650                 ret = -EINVAL;
7651                 break;
7652         }
7653
7654         if ((!restore) && (ret < 0))
7655                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7656
7657         return ret;
7658 }
7659
7660 /* Delete l2 tunnel filter */
7661 int
7662 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7663                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7664 {
7665         int ret;
7666         struct ixgbe_l2_tn_info *l2_tn_info =
7667                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7668         struct ixgbe_l2_tn_key key;
7669
7670         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7671         key.tn_id = l2_tunnel->tunnel_id;
7672         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7673         if (ret < 0)
7674                 return ret;
7675
7676         switch (l2_tunnel->l2_tunnel_type) {
7677         case RTE_L2_TUNNEL_TYPE_E_TAG:
7678                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7679                 break;
7680         default:
7681                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7682                 ret = -EINVAL;
7683                 break;
7684         }
7685
7686         return ret;
7687 }
7688
7689 /**
7690  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7691  * @dev: pointer to rte_eth_dev structure
7692  * @filter_op:operation will be taken.
7693  * @arg: a pointer to specific structure corresponding to the filter_op
7694  */
7695 static int
7696 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7697                                   enum rte_filter_op filter_op,
7698                                   void *arg)
7699 {
7700         int ret;
7701
7702         if (filter_op == RTE_ETH_FILTER_NOP)
7703                 return 0;
7704
7705         if (arg == NULL) {
7706                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7707                             filter_op);
7708                 return -EINVAL;
7709         }
7710
7711         switch (filter_op) {
7712         case RTE_ETH_FILTER_ADD:
7713                 ret = ixgbe_dev_l2_tunnel_filter_add
7714                         (dev,
7715                          (struct rte_eth_l2_tunnel_conf *)arg,
7716                          FALSE);
7717                 break;
7718         case RTE_ETH_FILTER_DELETE:
7719                 ret = ixgbe_dev_l2_tunnel_filter_del
7720                         (dev,
7721                          (struct rte_eth_l2_tunnel_conf *)arg);
7722                 break;
7723         default:
7724                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7725                 ret = -EINVAL;
7726                 break;
7727         }
7728         return ret;
7729 }
7730
7731 static int
7732 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7733 {
7734         int ret = 0;
7735         uint32_t ctrl;
7736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7737
7738         if (hw->mac.type != ixgbe_mac_X550 &&
7739             hw->mac.type != ixgbe_mac_X550EM_x &&
7740             hw->mac.type != ixgbe_mac_X550EM_a) {
7741                 return -ENOTSUP;
7742         }
7743
7744         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7745         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7746         if (en)
7747                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7748         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7749
7750         return ret;
7751 }
7752
7753 /* Enable l2 tunnel forwarding */
7754 static int
7755 ixgbe_dev_l2_tunnel_forwarding_enable
7756         (struct rte_eth_dev *dev,
7757          enum rte_eth_tunnel_type l2_tunnel_type)
7758 {
7759         struct ixgbe_l2_tn_info *l2_tn_info =
7760                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7761         int ret = 0;
7762
7763         switch (l2_tunnel_type) {
7764         case RTE_L2_TUNNEL_TYPE_E_TAG:
7765                 l2_tn_info->e_tag_fwd_en = TRUE;
7766                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7767                 break;
7768         default:
7769                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7770                 ret = -EINVAL;
7771                 break;
7772         }
7773
7774         return ret;
7775 }
7776
7777 /* Disable l2 tunnel forwarding */
7778 static int
7779 ixgbe_dev_l2_tunnel_forwarding_disable
7780         (struct rte_eth_dev *dev,
7781          enum rte_eth_tunnel_type l2_tunnel_type)
7782 {
7783         struct ixgbe_l2_tn_info *l2_tn_info =
7784                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7785         int ret = 0;
7786
7787         switch (l2_tunnel_type) {
7788         case RTE_L2_TUNNEL_TYPE_E_TAG:
7789                 l2_tn_info->e_tag_fwd_en = FALSE;
7790                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7791                 break;
7792         default:
7793                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7794                 ret = -EINVAL;
7795                 break;
7796         }
7797
7798         return ret;
7799 }
7800
7801 static int
7802 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7803                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7804                              bool en)
7805 {
7806         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7807         int ret = 0;
7808         uint32_t vmtir, vmvir;
7809         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7810
7811         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7812                 PMD_DRV_LOG(ERR,
7813                             "VF id %u should be less than %u",
7814                             l2_tunnel->vf_id,
7815                             pci_dev->max_vfs);
7816                 return -EINVAL;
7817         }
7818
7819         if (hw->mac.type != ixgbe_mac_X550 &&
7820             hw->mac.type != ixgbe_mac_X550EM_x &&
7821             hw->mac.type != ixgbe_mac_X550EM_a) {
7822                 return -ENOTSUP;
7823         }
7824
7825         if (en)
7826                 vmtir = l2_tunnel->tunnel_id;
7827         else
7828                 vmtir = 0;
7829
7830         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7831
7832         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7833         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7834         if (en)
7835                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7836         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7837
7838         return ret;
7839 }
7840
7841 /* Enable l2 tunnel tag insertion */
7842 static int
7843 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7844                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7845 {
7846         int ret = 0;
7847
7848         switch (l2_tunnel->l2_tunnel_type) {
7849         case RTE_L2_TUNNEL_TYPE_E_TAG:
7850                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7851                 break;
7852         default:
7853                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7854                 ret = -EINVAL;
7855                 break;
7856         }
7857
7858         return ret;
7859 }
7860
7861 /* Disable l2 tunnel tag insertion */
7862 static int
7863 ixgbe_dev_l2_tunnel_insertion_disable
7864         (struct rte_eth_dev *dev,
7865          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7866 {
7867         int ret = 0;
7868
7869         switch (l2_tunnel->l2_tunnel_type) {
7870         case RTE_L2_TUNNEL_TYPE_E_TAG:
7871                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7872                 break;
7873         default:
7874                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7875                 ret = -EINVAL;
7876                 break;
7877         }
7878
7879         return ret;
7880 }
7881
7882 static int
7883 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7884                              bool en)
7885 {
7886         int ret = 0;
7887         uint32_t qde;
7888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7889
7890         if (hw->mac.type != ixgbe_mac_X550 &&
7891             hw->mac.type != ixgbe_mac_X550EM_x &&
7892             hw->mac.type != ixgbe_mac_X550EM_a) {
7893                 return -ENOTSUP;
7894         }
7895
7896         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7897         if (en)
7898                 qde |= IXGBE_QDE_STRIP_TAG;
7899         else
7900                 qde &= ~IXGBE_QDE_STRIP_TAG;
7901         qde &= ~IXGBE_QDE_READ;
7902         qde |= IXGBE_QDE_WRITE;
7903         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7904
7905         return ret;
7906 }
7907
7908 /* Enable l2 tunnel tag stripping */
7909 static int
7910 ixgbe_dev_l2_tunnel_stripping_enable
7911         (struct rte_eth_dev *dev,
7912          enum rte_eth_tunnel_type l2_tunnel_type)
7913 {
7914         int ret = 0;
7915
7916         switch (l2_tunnel_type) {
7917         case RTE_L2_TUNNEL_TYPE_E_TAG:
7918                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7919                 break;
7920         default:
7921                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7922                 ret = -EINVAL;
7923                 break;
7924         }
7925
7926         return ret;
7927 }
7928
7929 /* Disable l2 tunnel tag stripping */
7930 static int
7931 ixgbe_dev_l2_tunnel_stripping_disable
7932         (struct rte_eth_dev *dev,
7933          enum rte_eth_tunnel_type l2_tunnel_type)
7934 {
7935         int ret = 0;
7936
7937         switch (l2_tunnel_type) {
7938         case RTE_L2_TUNNEL_TYPE_E_TAG:
7939                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7940                 break;
7941         default:
7942                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7943                 ret = -EINVAL;
7944                 break;
7945         }
7946
7947         return ret;
7948 }
7949
7950 /* Enable/disable l2 tunnel offload functions */
7951 static int
7952 ixgbe_dev_l2_tunnel_offload_set
7953         (struct rte_eth_dev *dev,
7954          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7955          uint32_t mask,
7956          uint8_t en)
7957 {
7958         int ret = 0;
7959
7960         if (l2_tunnel == NULL)
7961                 return -EINVAL;
7962
7963         ret = -EINVAL;
7964         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7965                 if (en)
7966                         ret = ixgbe_dev_l2_tunnel_enable(
7967                                 dev,
7968                                 l2_tunnel->l2_tunnel_type);
7969                 else
7970                         ret = ixgbe_dev_l2_tunnel_disable(
7971                                 dev,
7972                                 l2_tunnel->l2_tunnel_type);
7973         }
7974
7975         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7976                 if (en)
7977                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7978                                 dev,
7979                                 l2_tunnel);
7980                 else
7981                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7982                                 dev,
7983                                 l2_tunnel);
7984         }
7985
7986         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7987                 if (en)
7988                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7989                                 dev,
7990                                 l2_tunnel->l2_tunnel_type);
7991                 else
7992                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7993                                 dev,
7994                                 l2_tunnel->l2_tunnel_type);
7995         }
7996
7997         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7998                 if (en)
7999                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8000                                 dev,
8001                                 l2_tunnel->l2_tunnel_type);
8002                 else
8003                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8004                                 dev,
8005                                 l2_tunnel->l2_tunnel_type);
8006         }
8007
8008         return ret;
8009 }
8010
8011 static int
8012 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8013                         uint16_t port)
8014 {
8015         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8016         IXGBE_WRITE_FLUSH(hw);
8017
8018         return 0;
8019 }
8020
8021 /* There's only one register for VxLAN UDP port.
8022  * So, we cannot add several ports. Will update it.
8023  */
8024 static int
8025 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8026                      uint16_t port)
8027 {
8028         if (port == 0) {
8029                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8030                 return -EINVAL;
8031         }
8032
8033         return ixgbe_update_vxlan_port(hw, port);
8034 }
8035
8036 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8037  * UDP port, it must have a value.
8038  * So, will reset it to the original value 0.
8039  */
8040 static int
8041 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8042                      uint16_t port)
8043 {
8044         uint16_t cur_port;
8045
8046         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8047
8048         if (cur_port != port) {
8049                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8050                 return -EINVAL;
8051         }
8052
8053         return ixgbe_update_vxlan_port(hw, 0);
8054 }
8055
8056 /* Add UDP tunneling port */
8057 static int
8058 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8059                               struct rte_eth_udp_tunnel *udp_tunnel)
8060 {
8061         int ret = 0;
8062         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8063
8064         if (hw->mac.type != ixgbe_mac_X550 &&
8065             hw->mac.type != ixgbe_mac_X550EM_x &&
8066             hw->mac.type != ixgbe_mac_X550EM_a) {
8067                 return -ENOTSUP;
8068         }
8069
8070         if (udp_tunnel == NULL)
8071                 return -EINVAL;
8072
8073         switch (udp_tunnel->prot_type) {
8074         case RTE_TUNNEL_TYPE_VXLAN:
8075                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8076                 break;
8077
8078         case RTE_TUNNEL_TYPE_GENEVE:
8079         case RTE_TUNNEL_TYPE_TEREDO:
8080                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8081                 ret = -EINVAL;
8082                 break;
8083
8084         default:
8085                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8086                 ret = -EINVAL;
8087                 break;
8088         }
8089
8090         return ret;
8091 }
8092
8093 /* Remove UDP tunneling port */
8094 static int
8095 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8096                               struct rte_eth_udp_tunnel *udp_tunnel)
8097 {
8098         int ret = 0;
8099         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8100
8101         if (hw->mac.type != ixgbe_mac_X550 &&
8102             hw->mac.type != ixgbe_mac_X550EM_x &&
8103             hw->mac.type != ixgbe_mac_X550EM_a) {
8104                 return -ENOTSUP;
8105         }
8106
8107         if (udp_tunnel == NULL)
8108                 return -EINVAL;
8109
8110         switch (udp_tunnel->prot_type) {
8111         case RTE_TUNNEL_TYPE_VXLAN:
8112                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8113                 break;
8114         case RTE_TUNNEL_TYPE_GENEVE:
8115         case RTE_TUNNEL_TYPE_TEREDO:
8116                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8117                 ret = -EINVAL;
8118                 break;
8119         default:
8120                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8121                 ret = -EINVAL;
8122                 break;
8123         }
8124
8125         return ret;
8126 }
8127
8128 static void
8129 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8130 {
8131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8132
8133         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8134 }
8135
8136 static void
8137 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8138 {
8139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8140
8141         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8142 }
8143
8144 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8145 {
8146         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8147         u32 in_msg = 0;
8148
8149         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8150                 return;
8151
8152         /* PF reset VF event */
8153         if (in_msg == IXGBE_PF_CONTROL_MSG)
8154                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8155 }
8156
8157 static int
8158 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8159 {
8160         uint32_t eicr;
8161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8162         struct ixgbe_interrupt *intr =
8163                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8164         ixgbevf_intr_disable(hw);
8165
8166         /* read-on-clear nic registers here */
8167         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8168         intr->flags = 0;
8169
8170         /* only one misc vector supported - mailbox */
8171         eicr &= IXGBE_VTEICR_MASK;
8172         if (eicr == IXGBE_MISC_VEC_ID)
8173                 intr->flags |= IXGBE_FLAG_MAILBOX;
8174
8175         return 0;
8176 }
8177
8178 static int
8179 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8180 {
8181         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8182         struct ixgbe_interrupt *intr =
8183                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8184
8185         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8186                 ixgbevf_mbx_process(dev);
8187                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8188         }
8189
8190         ixgbevf_intr_enable(hw);
8191
8192         return 0;
8193 }
8194
8195 static void
8196 ixgbevf_dev_interrupt_handler(void *param)
8197 {
8198         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8199
8200         ixgbevf_dev_interrupt_get_status(dev);
8201         ixgbevf_dev_interrupt_action(dev);
8202 }
8203
8204 /**
8205  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8206  *  @hw: pointer to hardware structure
8207  *
8208  *  Stops the transmit data path and waits for the HW to internally empty
8209  *  the Tx security block
8210  **/
8211 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8212 {
8213 #define IXGBE_MAX_SECTX_POLL 40
8214
8215         int i;
8216         int sectxreg;
8217
8218         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8219         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8220         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8221         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8222                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8223                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8224                         break;
8225                 /* Use interrupt-safe sleep just in case */
8226                 usec_delay(1000);
8227         }
8228
8229         /* For informational purposes only */
8230         if (i >= IXGBE_MAX_SECTX_POLL)
8231                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8232                          "path fully disabled.  Continuing with init.");
8233
8234         return IXGBE_SUCCESS;
8235 }
8236
8237 /**
8238  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8239  *  @hw: pointer to hardware structure
8240  *
8241  *  Enables the transmit data path.
8242  **/
8243 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8244 {
8245         uint32_t sectxreg;
8246
8247         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8248         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8249         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8250         IXGBE_WRITE_FLUSH(hw);
8251
8252         return IXGBE_SUCCESS;
8253 }
8254
8255 int
8256 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8257 {
8258         struct ixgbe_hw *hw;
8259         struct rte_eth_dev *dev;
8260         uint32_t ctrl;
8261
8262         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8263
8264         dev = &rte_eth_devices[port];
8265
8266         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8267                 return -ENOTSUP;
8268
8269         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8270
8271         /* Stop the data paths */
8272         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8273                 return -ENOTSUP;
8274         /*
8275          * Workaround:
8276          * As no ixgbe_disable_sec_rx_path equivalent is
8277          * implemented for tx in the base code, and we are
8278          * not allowed to modify the base code in DPDK, so
8279          * just call the hand-written one directly for now.
8280          * The hardware support has been checked by
8281          * ixgbe_disable_sec_rx_path().
8282          */
8283         ixgbe_disable_sec_tx_path_generic(hw);
8284
8285         /* Enable Ethernet CRC (required by MACsec offload) */
8286         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8287         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8288         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8289
8290         /* Enable the TX and RX crypto engines */
8291         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8292         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8293         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8294
8295         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8296         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8297         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8298
8299         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8300         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8301         ctrl |= 0x3;
8302         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8303
8304         /* Enable SA lookup */
8305         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8306         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8307         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8308                      IXGBE_LSECTXCTRL_AUTH;
8309         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8310         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8311         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8312         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8313
8314         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8315         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8316         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8317         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8318         if (rp)
8319                 ctrl |= IXGBE_LSECRXCTRL_RP;
8320         else
8321                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8322         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8323
8324         /* Start the data paths */
8325         ixgbe_enable_sec_rx_path(hw);
8326         /*
8327          * Workaround:
8328          * As no ixgbe_enable_sec_rx_path equivalent is
8329          * implemented for tx in the base code, and we are
8330          * not allowed to modify the base code in DPDK, so
8331          * just call the hand-written one directly for now.
8332          */
8333         ixgbe_enable_sec_tx_path_generic(hw);
8334
8335         return 0;
8336 }
8337
8338 int
8339 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8340 {
8341         struct ixgbe_hw *hw;
8342         struct rte_eth_dev *dev;
8343         uint32_t ctrl;
8344
8345         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8346
8347         dev = &rte_eth_devices[port];
8348
8349         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8350                 return -ENOTSUP;
8351
8352         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8353
8354         /* Stop the data paths */
8355         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8356                 return -ENOTSUP;
8357         /*
8358          * Workaround:
8359          * As no ixgbe_disable_sec_rx_path equivalent is
8360          * implemented for tx in the base code, and we are
8361          * not allowed to modify the base code in DPDK, so
8362          * just call the hand-written one directly for now.
8363          * The hardware support has been checked by
8364          * ixgbe_disable_sec_rx_path().
8365          */
8366         ixgbe_disable_sec_tx_path_generic(hw);
8367
8368         /* Disable the TX and RX crypto engines */
8369         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8370         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8371         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8372
8373         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8374         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8375         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8376
8377         /* Disable SA lookup */
8378         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8379         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8380         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8381         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8382
8383         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8384         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8385         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8386         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8387
8388         /* Start the data paths */
8389         ixgbe_enable_sec_rx_path(hw);
8390         /*
8391          * Workaround:
8392          * As no ixgbe_enable_sec_rx_path equivalent is
8393          * implemented for tx in the base code, and we are
8394          * not allowed to modify the base code in DPDK, so
8395          * just call the hand-written one directly for now.
8396          */
8397         ixgbe_enable_sec_tx_path_generic(hw);
8398
8399         return 0;
8400 }
8401
8402 int
8403 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8404 {
8405         struct ixgbe_hw *hw;
8406         struct rte_eth_dev *dev;
8407         uint32_t ctrl;
8408
8409         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8410
8411         dev = &rte_eth_devices[port];
8412
8413         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8414                 return -ENOTSUP;
8415
8416         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8417
8418         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8419         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8420
8421         ctrl = mac[4] | (mac[5] << 8);
8422         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8423
8424         return 0;
8425 }
8426
8427 int
8428 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8429 {
8430         struct ixgbe_hw *hw;
8431         struct rte_eth_dev *dev;
8432         uint32_t ctrl;
8433
8434         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8435
8436         dev = &rte_eth_devices[port];
8437
8438         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8439                 return -ENOTSUP;
8440
8441         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8442
8443         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8444         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8445
8446         pi = rte_cpu_to_be_16(pi);
8447         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8448         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8449
8450         return 0;
8451 }
8452
8453 int
8454 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8455                                  uint32_t pn, uint8_t *key)
8456 {
8457         struct ixgbe_hw *hw;
8458         struct rte_eth_dev *dev;
8459         uint32_t ctrl, i;
8460
8461         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8462
8463         dev = &rte_eth_devices[port];
8464
8465         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8466                 return -ENOTSUP;
8467
8468         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8469
8470         if (idx != 0 && idx != 1)
8471                 return -EINVAL;
8472
8473         if (an >= 4)
8474                 return -EINVAL;
8475
8476         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8477
8478         /* Set the PN and key */
8479         pn = rte_cpu_to_be_32(pn);
8480         if (idx == 0) {
8481                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8482
8483                 for (i = 0; i < 4; i++) {
8484                         ctrl = (key[i * 4 + 0] <<  0) |
8485                                (key[i * 4 + 1] <<  8) |
8486                                (key[i * 4 + 2] << 16) |
8487                                (key[i * 4 + 3] << 24);
8488                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8489                 }
8490         } else {
8491                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8492
8493                 for (i = 0; i < 4; i++) {
8494                         ctrl = (key[i * 4 + 0] <<  0) |
8495                                (key[i * 4 + 1] <<  8) |
8496                                (key[i * 4 + 2] << 16) |
8497                                (key[i * 4 + 3] << 24);
8498                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8499                 }
8500         }
8501
8502         /* Set AN and select the SA */
8503         ctrl = (an << idx * 2) | (idx << 4);
8504         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8505
8506         return 0;
8507 }
8508
8509 int
8510 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8511                                  uint32_t pn, uint8_t *key)
8512 {
8513         struct ixgbe_hw *hw;
8514         struct rte_eth_dev *dev;
8515         uint32_t ctrl, i;
8516
8517         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8518
8519         dev = &rte_eth_devices[port];
8520
8521         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8522                 return -ENOTSUP;
8523
8524         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8525
8526         if (idx != 0 && idx != 1)
8527                 return -EINVAL;
8528
8529         if (an >= 4)
8530                 return -EINVAL;
8531
8532         /* Set the PN */
8533         pn = rte_cpu_to_be_32(pn);
8534         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8535
8536         /* Set the key */
8537         for (i = 0; i < 4; i++) {
8538                 ctrl = (key[i * 4 + 0] <<  0) |
8539                        (key[i * 4 + 1] <<  8) |
8540                        (key[i * 4 + 2] << 16) |
8541                        (key[i * 4 + 3] << 24);
8542                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8543         }
8544
8545         /* Set the AN and validate the SA */
8546         ctrl = an | (1 << 2);
8547         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8548
8549         return 0;
8550 }
8551
8552 /* restore n-tuple filter */
8553 static inline void
8554 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8555 {
8556         struct ixgbe_filter_info *filter_info =
8557                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8558         struct ixgbe_5tuple_filter *node;
8559
8560         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8561                 ixgbe_inject_5tuple_filter(dev, node);
8562         }
8563 }
8564
8565 /* restore ethernet type filter */
8566 static inline void
8567 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8568 {
8569         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8570         struct ixgbe_filter_info *filter_info =
8571                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8572         int i;
8573
8574         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8575                 if (filter_info->ethertype_mask & (1 << i)) {
8576                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8577                                         filter_info->ethertype_filters[i].etqf);
8578                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8579                                         filter_info->ethertype_filters[i].etqs);
8580                         IXGBE_WRITE_FLUSH(hw);
8581                 }
8582         }
8583 }
8584
8585 /* restore SYN filter */
8586 static inline void
8587 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8588 {
8589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8590         struct ixgbe_filter_info *filter_info =
8591                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8592         uint32_t synqf;
8593
8594         synqf = filter_info->syn_info;
8595
8596         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8597                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8598                 IXGBE_WRITE_FLUSH(hw);
8599         }
8600 }
8601
8602 /* restore L2 tunnel filter */
8603 static inline void
8604 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8605 {
8606         struct ixgbe_l2_tn_info *l2_tn_info =
8607                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8608         struct ixgbe_l2_tn_filter *node;
8609         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8610
8611         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8612                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8613                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8614                 l2_tn_conf.pool           = node->pool;
8615                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8616         }
8617 }
8618
8619 static int
8620 ixgbe_filter_restore(struct rte_eth_dev *dev)
8621 {
8622         ixgbe_ntuple_filter_restore(dev);
8623         ixgbe_ethertype_filter_restore(dev);
8624         ixgbe_syn_filter_restore(dev);
8625         ixgbe_fdir_filter_restore(dev);
8626         ixgbe_l2_tn_filter_restore(dev);
8627
8628         return 0;
8629 }
8630
8631 static void
8632 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8633 {
8634         struct ixgbe_l2_tn_info *l2_tn_info =
8635                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8636         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8637
8638         if (l2_tn_info->e_tag_en)
8639                 (void)ixgbe_e_tag_enable(hw);
8640
8641         if (l2_tn_info->e_tag_fwd_en)
8642                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8643
8644         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8645 }
8646
8647 /* remove all the n-tuple filters */
8648 void
8649 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8650 {
8651         struct ixgbe_filter_info *filter_info =
8652                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8653         struct ixgbe_5tuple_filter *p_5tuple;
8654
8655         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8656                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8657 }
8658
8659 /* remove all the ether type filters */
8660 void
8661 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8662 {
8663         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8664         struct ixgbe_filter_info *filter_info =
8665                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8666         int i;
8667
8668         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8669                 if (filter_info->ethertype_mask & (1 << i) &&
8670                     !filter_info->ethertype_filters[i].conf) {
8671                         (void)ixgbe_ethertype_filter_remove(filter_info,
8672                                                             (uint8_t)i);
8673                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8674                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8675                         IXGBE_WRITE_FLUSH(hw);
8676                 }
8677         }
8678 }
8679
8680 /* remove the SYN filter */
8681 void
8682 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8683 {
8684         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8685         struct ixgbe_filter_info *filter_info =
8686                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8687
8688         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8689                 filter_info->syn_info = 0;
8690
8691                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8692                 IXGBE_WRITE_FLUSH(hw);
8693         }
8694 }
8695
8696 /* remove all the L2 tunnel filters */
8697 int
8698 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8699 {
8700         struct ixgbe_l2_tn_info *l2_tn_info =
8701                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8702         struct ixgbe_l2_tn_filter *l2_tn_filter;
8703         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8704         int ret = 0;
8705
8706         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8707                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8708                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8709                 l2_tn_conf.pool           = l2_tn_filter->pool;
8710                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8711                 if (ret < 0)
8712                         return ret;
8713         }
8714
8715         return 0;
8716 }
8717
8718 int
8719 rte_pmd_ixgbe_set_tc_bw_alloc(uint8_t port,
8720                               uint8_t tc_num,
8721                               uint8_t *bw_weight)
8722 {
8723         struct rte_eth_dev *dev;
8724         struct ixgbe_dcb_config *dcb_config;
8725         struct ixgbe_dcb_tc_config *tc;
8726         struct rte_eth_conf *eth_conf;
8727         struct ixgbe_bw_conf *bw_conf;
8728         uint8_t i;
8729         uint8_t nb_tcs;
8730         uint16_t sum;
8731
8732         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8733
8734         dev = &rte_eth_devices[port];
8735
8736         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8737                 return -ENOTSUP;
8738
8739         if (tc_num > IXGBE_DCB_MAX_TRAFFIC_CLASS) {
8740                 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
8741                             IXGBE_DCB_MAX_TRAFFIC_CLASS);
8742                 return -EINVAL;
8743         }
8744
8745         dcb_config = IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
8746         bw_conf = IXGBE_DEV_PRIVATE_TO_BW_CONF(dev->data->dev_private);
8747         eth_conf = &dev->data->dev_conf;
8748
8749         if (eth_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
8750                 nb_tcs = eth_conf->tx_adv_conf.dcb_tx_conf.nb_tcs;
8751         } else if (eth_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
8752                 if (eth_conf->tx_adv_conf.vmdq_dcb_tx_conf.nb_queue_pools ==
8753                     ETH_32_POOLS)
8754                         nb_tcs = ETH_4_TCS;
8755                 else
8756                         nb_tcs = ETH_8_TCS;
8757         } else {
8758                 nb_tcs = 1;
8759         }
8760
8761         if (nb_tcs != tc_num) {
8762                 PMD_DRV_LOG(ERR,
8763                             "Weight should be set for all %d enabled TCs.",
8764                             nb_tcs);
8765                 return -EINVAL;
8766         }
8767
8768         sum = 0;
8769         for (i = 0; i < nb_tcs; i++)
8770                 sum += bw_weight[i];
8771         if (sum != 100) {
8772                 PMD_DRV_LOG(ERR,
8773                             "The summary of the TC weight should be 100.");
8774                 return -EINVAL;
8775         }
8776
8777         for (i = 0; i < nb_tcs; i++) {
8778                 tc = &dcb_config->tc_config[i];
8779                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = bw_weight[i];
8780         }
8781         for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
8782                 tc = &dcb_config->tc_config[i];
8783                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
8784         }
8785
8786         bw_conf->tc_num = nb_tcs;
8787
8788         return 0;
8789 }
8790
8791 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8792 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8793 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8794 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8795 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8796 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");