drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstats *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstats *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 183                                              uint16_t queue_id,
 184                                              uint8_t stat_idx,
 185                                              uint8_t is_rx);
 186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 187                                struct rte_eth_dev_info *dev_info);
 188 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 190                                  struct rte_eth_dev_info *dev_info);
 191 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 192
 193 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 194                 uint16_t vlan_id, int on);
 195 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 196                                enum rte_vlan_type vlan_type,
 197                                uint16_t tpid_id);
 198 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 199                 uint16_t queue, bool on);
 200 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 201                 int on);
 202 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 203 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 204 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 205 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 206 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 207
 208 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 209 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 210 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 211                                struct rte_eth_fc_conf *fc_conf);
 212 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 215                 struct rte_eth_pfc_conf *pfc_conf);
 216 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 217                         struct rte_eth_rss_reta_entry64 *reta_conf,
 218                         uint16_t reta_size);
 219 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 220                         struct rte_eth_rss_reta_entry64 *reta_conf,
 221                         uint16_t reta_size);
 222 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 226 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 227 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 228                 void *param);
 229 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 230 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 231                 uint32_t index, uint32_t pool);
 232 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 233 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 234                                            struct ether_addr *mac_addr);
 235 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 236
 237 /* For Virtual Function support */
 238 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 239 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 240 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 241 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 243 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 246 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 256                                             uint16_t queue_id);
 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 258                                              uint16_t queue_id);
 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 260                                  uint8_t queue, uint8_t msix_vector);
 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 264
 265 /* For Eth VMDQ APIs support */
 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 267                 ether_addr* mac_addr,uint8_t on);
 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 269 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 270                 uint16_t rx_mask, uint8_t on);
 271 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 272 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 273 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 274                 uint64_t pool_mask,uint8_t vlan_on);
 275 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 276                 struct rte_eth_mirror_conf *mirror_conf,
 277                 uint8_t rule_id, uint8_t on);
 278 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 279                 uint8_t rule_id);
 280 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 281                                           uint16_t queue_id);
 282 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 283                                            uint16_t queue_id);
 284 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 285                                uint8_t queue, uint8_t msix_vector);
 286 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 287
 288 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 289                 uint16_t queue_idx, uint16_t tx_rate);
 290 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 291                 uint16_t tx_rate, uint64_t q_msk);
 292
 293 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 294                                  struct ether_addr *mac_addr,
 295                                  uint32_t index, uint32_t pool);
 296 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 297 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 298                                              struct ether_addr *mac_addr);
 299 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 300                         struct rte_eth_syn_filter *filter,
 301                         bool add);
 302 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 303                         struct rte_eth_syn_filter *filter);
 304 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 305                         enum rte_filter_op filter_op,
 306                         void *arg);
 307 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 308                         struct ixgbe_5tuple_filter *filter);
 309 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 310                         struct ixgbe_5tuple_filter *filter);
 311 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 312                         struct rte_eth_ntuple_filter *filter,
 313                         bool add);
 314 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 315                                 enum rte_filter_op filter_op,
 316                                 void *arg);
 317 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 318                         struct rte_eth_ntuple_filter *filter);
 319 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ethertype_filter *filter,
 321                         bool add);
 322 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ethertype_filter *filter);
 327 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 328                      enum rte_filter_type filter_type,
 329                      enum rte_filter_op filter_op,
 330                      void *arg);
 331 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 332
 333 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 334                                       struct ether_addr *mc_addr_set,
 335                                       uint32_t nb_mc_addr);
 336 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 337                                    struct rte_eth_dcb_info *dcb_info);
 338
 339 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 340 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 341                             struct rte_dev_reg_info *regs);
 342 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 343 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 344                                 struct rte_dev_eeprom_info *eeprom);
 345 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 346                                 struct rte_dev_eeprom_info *eeprom);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364
 365 static int ixgbe_dev_l2_tunnel_eth_type_conf
 366         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 367 static int ixgbe_dev_l2_tunnel_offload_set
 368         (struct rte_eth_dev *dev,
 369          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 370          uint32_t mask,
 371          uint8_t en);
 372 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 373                                              enum rte_filter_op filter_op,
 374                                              void *arg);
 375
 376 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 377                                          struct rte_eth_udp_tunnel *udp_tunnel);
 378 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 379                                          struct rte_eth_udp_tunnel *udp_tunnel);
 380
 381 /*
 382  * Define VF Stats MACRO for Non "cleared on read" register
 383  */
 384 #define UPDATE_VF_STAT(reg, last, cur)                          \
 385 {                                                               \
 386         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 387         cur += (latest - last) & UINT_MAX;                      \
 388         last = latest;                                          \
 389 }
 390
 391 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 392 {                                                                \
 393         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 394         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 395         u64 latest = ((new_msb << 32) | new_lsb);                \
 396         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 397         last = latest;                                           \
 398 }
 399
 400 #define IXGBE_SET_HWSTRIP(h, q) do{\
 401                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 402                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 403                 (h)->bitmap[idx] |= 1 << bit;\
 404         } while (0)
 405
 406 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 407                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 408                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 409                 (h)->bitmap[idx] &= ~(1 << bit);\
 410         } while (0)
 411
 412 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 413                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 414                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 415                 (r) = (h)->bitmap[idx] >> bit & 1;\
 416         } while (0)
 417
 418 /*
 419  * The set of PCI devices this driver supports
 420  */
 421 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 422
 423 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 424 #include "rte_pci_dev_ids.h"
 425
 426 { .vendor_id = 0, /* sentinel */ },
 427 };
 428
 429
 430 /*
 431  * The set of PCI devices this driver supports (for 82599 VF)
 432  */
 433 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 434
 435 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 436 #include "rte_pci_dev_ids.h"
 437 { .vendor_id = 0, /* sentinel */ },
 438
 439 };
 440
 441 static const struct rte_eth_desc_lim rx_desc_lim = {
 442         .nb_max = IXGBE_MAX_RING_DESC,
 443         .nb_min = IXGBE_MIN_RING_DESC,
 444         .nb_align = IXGBE_RXD_ALIGN,
 445 };
 446
 447 static const struct rte_eth_desc_lim tx_desc_lim = {
 448         .nb_max = IXGBE_MAX_RING_DESC,
 449         .nb_min = IXGBE_MIN_RING_DESC,
 450         .nb_align = IXGBE_TXD_ALIGN,
 451 };
 452
 453 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 454         .dev_configure        = ixgbe_dev_configure,
 455         .dev_start            = ixgbe_dev_start,
 456         .dev_stop             = ixgbe_dev_stop,
 457         .dev_set_link_up    = ixgbe_dev_set_link_up,
 458         .dev_set_link_down  = ixgbe_dev_set_link_down,
 459         .dev_close            = ixgbe_dev_close,
 460         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 461         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 462         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 463         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 464         .link_update          = ixgbe_dev_link_update,
 465         .stats_get            = ixgbe_dev_stats_get,
 466         .xstats_get           = ixgbe_dev_xstats_get,
 467         .stats_reset          = ixgbe_dev_stats_reset,
 468         .xstats_reset         = ixgbe_dev_xstats_reset,
 469         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 470         .dev_infos_get        = ixgbe_dev_info_get,
 471         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 472         .mtu_set              = ixgbe_dev_mtu_set,
 473         .vlan_filter_set      = ixgbe_vlan_filter_set,
 474         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 475         .vlan_offload_set     = ixgbe_vlan_offload_set,
 476         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 477         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 478         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 479         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 480         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 481         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 482         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 483         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 484         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 485         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 486         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 487         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 488         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 489         .dev_led_on           = ixgbe_dev_led_on,
 490         .dev_led_off          = ixgbe_dev_led_off,
 491         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 492         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 493         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 494         .mac_addr_add         = ixgbe_add_rar,
 495         .mac_addr_remove      = ixgbe_remove_rar,
 496         .mac_addr_set         = ixgbe_set_default_mac_addr,
 497         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 498         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 499         .mirror_rule_set      = ixgbe_mirror_rule_set,
 500         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 501         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 502         .set_vf_rx            = ixgbe_set_pool_rx,
 503         .set_vf_tx            = ixgbe_set_pool_tx,
 504         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 505         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 506         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 507         .reta_update          = ixgbe_dev_rss_reta_update,
 508         .reta_query           = ixgbe_dev_rss_reta_query,
 509 #ifdef RTE_NIC_BYPASS
 510         .bypass_init          = ixgbe_bypass_init,
 511         .bypass_state_set     = ixgbe_bypass_state_store,
 512         .bypass_state_show    = ixgbe_bypass_state_show,
 513         .bypass_event_set     = ixgbe_bypass_event_store,
 514         .bypass_event_show    = ixgbe_bypass_event_show,
 515         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 516         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 517         .bypass_ver_show      = ixgbe_bypass_ver_show,
 518         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 519 #endif /* RTE_NIC_BYPASS */
 520         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 521         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 522         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 523         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 524         .rxq_info_get         = ixgbe_rxq_info_get,
 525         .txq_info_get         = ixgbe_txq_info_get,
 526         .timesync_enable      = ixgbe_timesync_enable,
 527         .timesync_disable     = ixgbe_timesync_disable,
 528         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 529         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 530         .get_reg_length       = ixgbe_get_reg_length,
 531         .get_reg              = ixgbe_get_regs,
 532         .get_eeprom_length    = ixgbe_get_eeprom_length,
 533         .get_eeprom           = ixgbe_get_eeprom,
 534         .set_eeprom           = ixgbe_set_eeprom,
 535         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 536         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 537         .timesync_read_time   = ixgbe_timesync_read_time,
 538         .timesync_write_time  = ixgbe_timesync_write_time,
 539         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 540         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 541         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 542         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 543 };
 544
 545 /*
 546  * dev_ops for virtual function, bare necessities for basic vf
 547  * operation have been implemented
 548  */
 549 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 550         .dev_configure        = ixgbevf_dev_configure,
 551         .dev_start            = ixgbevf_dev_start,
 552         .dev_stop             = ixgbevf_dev_stop,
 553         .link_update          = ixgbe_dev_link_update,
 554         .stats_get            = ixgbevf_dev_stats_get,
 555         .xstats_get           = ixgbevf_dev_xstats_get,
 556         .stats_reset          = ixgbevf_dev_stats_reset,
 557         .xstats_reset         = ixgbevf_dev_stats_reset,
 558         .dev_close            = ixgbevf_dev_close,
 559         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 560         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 561         .dev_infos_get        = ixgbevf_dev_info_get,
 562         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 563         .mtu_set              = ixgbevf_dev_set_mtu,
 564         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 565         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 566         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 567         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 568         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 569         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 570         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 571         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 572         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 573         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 574         .mac_addr_add         = ixgbevf_add_mac_addr,
 575         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 576         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 577         .rxq_info_get         = ixgbe_rxq_info_get,
 578         .txq_info_get         = ixgbe_txq_info_get,
 579         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 580         .get_reg_length       = ixgbevf_get_reg_length,
 581         .get_reg              = ixgbevf_get_regs,
 582         .reta_update          = ixgbe_dev_rss_reta_update,
 583         .reta_query           = ixgbe_dev_rss_reta_query,
 584         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 585         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 586 };
 587
 588 /* store statistics names and its offset in stats structure */
 589 struct rte_ixgbe_xstats_name_off {
 590         char name[RTE_ETH_XSTATS_NAME_SIZE];
 591         unsigned offset;
 592 };
 593
 594 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 595         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 596         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 597         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 598         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 599         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 600         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 601         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 602         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 603         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 604         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 605         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 606         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 607         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 608         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 609         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 610                 prc1023)},
 611         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 612                 prc1522)},
 613         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 614         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 615         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 616         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 617         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 618         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 619         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 620         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 621         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 622         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 623         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 624         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 625         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 626         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 627         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 628         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 629         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 630                 ptc1023)},
 631         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 632                 ptc1522)},
 633         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 634         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 635         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 636         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 637
 638         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 639                 fdirustat_add)},
 640         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 641                 fdirustat_remove)},
 642         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 643                 fdirfstat_fadd)},
 644         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 645                 fdirfstat_fremove)},
 646         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 647                 fdirmatch)},
 648         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 649                 fdirmiss)},
 650
 651         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 652         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 653         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 654                 fclast)},
 655         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 656         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 657         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 658         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 659         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 660                 fcoe_noddp)},
 661         {"rx_fcoe_no_direct_data_placement_ext_buff",
 662                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 663
 664         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 665                 lxontxc)},
 666         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 667                 lxonrxc)},
 668         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 669                 lxofftxc)},
 670         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 671                 lxoffrxc)},
 672         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 673 };
 674
 675 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 676                            sizeof(rte_ixgbe_stats_strings[0]))
 677
 678 /* Per-queue statistics */
 679 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 680         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 681         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 682         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 683         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 684 };
 685
 686 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 687                            sizeof(rte_ixgbe_rxq_strings[0]))
 688
 689 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 690         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 691         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 692         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 693                 pxon2offc)},
 694 };
 695
 696 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 697                            sizeof(rte_ixgbe_txq_strings[0]))
 698
 699 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 700         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 701 };
 702
 703 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 704                 sizeof(rte_ixgbevf_stats_strings[0]))
 705
 706 /**
 707  * Atomically reads the link status information from global
 708  * structure rte_eth_dev.
 709  *
 710  * @param dev
 711  *   - Pointer to the structure rte_eth_dev to read from.
 712  *   - Pointer to the buffer to be saved with the link status.
 713  *
 714  * @return
 715  *   - On success, zero.
 716  *   - On failure, negative value.
 717  */
 718 static inline int
 719 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 720                                 struct rte_eth_link *link)
 721 {
 722         struct rte_eth_link *dst = link;
 723         struct rte_eth_link *src = &(dev->data->dev_link);
 724
 725         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 726                                         *(uint64_t *)src) == 0)
 727                 return -1;
 728
 729         return 0;
 730 }
 731
 732 /**
 733  * Atomically writes the link status information into global
 734  * structure rte_eth_dev.
 735  *
 736  * @param dev
 737  *   - Pointer to the structure rte_eth_dev to read from.
 738  *   - Pointer to the buffer to be saved with the link status.
 739  *
 740  * @return
 741  *   - On success, zero.
 742  *   - On failure, negative value.
 743  */
 744 static inline int
 745 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 746                                 struct rte_eth_link *link)
 747 {
 748         struct rte_eth_link *dst = &(dev->data->dev_link);
 749         struct rte_eth_link *src = link;
 750
 751         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 752                                         *(uint64_t *)src) == 0)
 753                 return -1;
 754
 755         return 0;
 756 }
 757
 758 /*
 759  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 760  */
 761 static inline int
 762 ixgbe_is_sfp(struct ixgbe_hw *hw)
 763 {
 764         switch (hw->phy.type) {
 765         case ixgbe_phy_sfp_avago:
 766         case ixgbe_phy_sfp_ftl:
 767         case ixgbe_phy_sfp_intel:
 768         case ixgbe_phy_sfp_unknown:
 769         case ixgbe_phy_sfp_passive_tyco:
 770         case ixgbe_phy_sfp_passive_unknown:
 771                 return 1;
 772         default:
 773                 return 0;
 774         }
 775 }
 776
 777 static inline int32_t
 778 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 779 {
 780         uint32_t ctrl_ext;
 781         int32_t status;
 782
 783         status = ixgbe_reset_hw(hw);
 784
 785         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 786         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 787         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 788         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 789         IXGBE_WRITE_FLUSH(hw);
 790
 791         return status;
 792 }
 793
 794 static inline void
 795 ixgbe_enable_intr(struct rte_eth_dev *dev)
 796 {
 797         struct ixgbe_interrupt *intr =
 798                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 799         struct ixgbe_hw *hw =
 800                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 801
 802         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 803         IXGBE_WRITE_FLUSH(hw);
 804 }
 805
 806 /*
 807  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 808  */
 809 static void
 810 ixgbe_disable_intr(struct ixgbe_hw *hw)
 811 {
 812         PMD_INIT_FUNC_TRACE();
 813
 814         if (hw->mac.type == ixgbe_mac_82598EB) {
 815                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 816         } else {
 817                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 818                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 819                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 820         }
 821         IXGBE_WRITE_FLUSH(hw);
 822 }
 823
 824 /*
 825  * This function resets queue statistics mapping registers.
 826  * From Niantic datasheet, Initialization of Statistics section:
 827  * "...if software requires the queue counters, the RQSMR and TQSM registers
 828  * must be re-programmed following a device reset.
 829  */
 830 static void
 831 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 832 {
 833         uint32_t i;
 834
 835         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 836                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 837                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 838         }
 839 }
 840
 841
 842 static int
 843 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 844                                   uint16_t queue_id,
 845                                   uint8_t stat_idx,
 846                                   uint8_t is_rx)
 847 {
 848 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 849 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 850 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 851
 852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 853         struct ixgbe_stat_mapping_registers *stat_mappings =
 854                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 855         uint32_t qsmr_mask = 0;
 856         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 857         uint32_t q_map;
 858         uint8_t n, offset;
 859
 860         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 861                 (hw->mac.type != ixgbe_mac_X540) &&
 862                 (hw->mac.type != ixgbe_mac_X550) &&
 863                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 864                 (hw->mac.type != ixgbe_mac_X550EM_a))
 865                 return -ENOSYS;
 866
 867         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 868                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 869                      queue_id, stat_idx);
 870
 871         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 872         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 873                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 874                 return -EIO;
 875         }
 876         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 877
 878         /* Now clear any previous stat_idx set */
 879         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 880         if (!is_rx)
 881                 stat_mappings->tqsm[n] &= ~clearing_mask;
 882         else
 883                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 884
 885         q_map = (uint32_t)stat_idx;
 886         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 887         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 888         if (!is_rx)
 889                 stat_mappings->tqsm[n] |= qsmr_mask;
 890         else
 891                 stat_mappings->rqsmr[n] |= qsmr_mask;
 892
 893         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 894                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 895                      queue_id, stat_idx);
 896         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 897                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 898
 899         /* Now write the mapping in the appropriate register */
 900         if (is_rx) {
 901                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 902                              stat_mappings->rqsmr[n], n);
 903                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 904         }
 905         else {
 906                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 907                              stat_mappings->tqsm[n], n);
 908                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 909         }
 910         return 0;
 911 }
 912
 913 static void
 914 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 915 {
 916         struct ixgbe_stat_mapping_registers *stat_mappings =
 917                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 919         int i;
 920
 921         /* write whatever was in stat mapping table to the NIC */
 922         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 923                 /* rx */
 924                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 925
 926                 /* tx */
 927                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 928         }
 929 }
 930
 931 static void
 932 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 933 {
 934         uint8_t i;
 935         struct ixgbe_dcb_tc_config *tc;
 936         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 937
 938         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 939         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 940         for (i = 0; i < dcb_max_tc; i++) {
 941                 tc = &dcb_config->tc_config[i];
 942                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 943                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 944                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 945                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 946                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 947                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 948                 tc->pfc = ixgbe_dcb_pfc_disabled;
 949         }
 950
 951         /* Initialize default user to priority mapping, UPx->TC0 */
 952         tc = &dcb_config->tc_config[0];
 953         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 954         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 955         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 956                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 957                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 958         }
 959         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 960         dcb_config->pfc_mode_enable = false;
 961         dcb_config->vt_mode = true;
 962         dcb_config->round_robin_enable = false;
 963         /* support all DCB capabilities in 82599 */
 964         dcb_config->support.capabilities = 0xFF;
 965
 966         /*we only support 4 Tcs for X540, X550 */
 967         if (hw->mac.type == ixgbe_mac_X540 ||
 968                 hw->mac.type == ixgbe_mac_X550 ||
 969                 hw->mac.type == ixgbe_mac_X550EM_x ||
 970                 hw->mac.type == ixgbe_mac_X550EM_a) {
 971                 dcb_config->num_tcs.pg_tcs = 4;
 972                 dcb_config->num_tcs.pfc_tcs = 4;
 973         }
 974 }
 975
 976 /*
 977  * Ensure that all locks are released before first NVM or PHY access
 978  */
 979 static void
 980 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 981 {
 982         uint16_t mask;
 983
 984         /*
 985          * Phy lock should not fail in this early stage. If this is the case,
 986          * it is due to an improper exit of the application.
 987          * So force the release of the faulty lock. Release of common lock
 988          * is done automatically by swfw_sync function.
 989          */
 990         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 991         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 992                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 993         }
 994         ixgbe_release_swfw_semaphore(hw, mask);
 995
 996         /*
 997          * These ones are more tricky since they are common to all ports; but
 998          * swfw_sync retries last long enough (1s) to be almost sure that if
 999          * lock can not be taken it is due to an improper lock of the
1000          * semaphore.
1001          */
1002         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1003         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1004                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1005         }
1006         ixgbe_release_swfw_semaphore(hw, mask);
1007 }
1008
1009 /*
1010  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1011  * It returns 0 on success.
1012  */
1013 static int
1014 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1015 {
1016         struct rte_pci_device *pci_dev;
1017         struct ixgbe_hw *hw =
1018                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1019         struct ixgbe_vfta * shadow_vfta =
1020                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1021         struct ixgbe_hwstrip *hwstrip =
1022                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1023         struct ixgbe_dcb_config *dcb_config =
1024                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1025         struct ixgbe_filter_info *filter_info =
1026                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1027         uint32_t ctrl_ext;
1028         uint16_t csum;
1029         int diag, i;
1030
1031         PMD_INIT_FUNC_TRACE();
1032
1033         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1034         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1035         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1036
1037         /*
1038          * For secondary processes, we don't initialise any further as primary
1039          * has already done this work. Only check we don't need a different
1040          * RX and TX function.
1041          */
1042         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1043                 struct ixgbe_tx_queue *txq;
1044                 /* TX queue function in primary, set by last queue initialized
1045                  * Tx queue may not initialized by primary process */
1046                 if (eth_dev->data->tx_queues) {
1047                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1048                         ixgbe_set_tx_function(eth_dev, txq);
1049                 } else {
1050                         /* Use default TX function if we get here */
1051                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1052                                              "Using default TX function.");
1053                 }
1054
1055                 ixgbe_set_rx_function(eth_dev);
1056
1057                 return 0;
1058         }
1059         pci_dev = eth_dev->pci_dev;
1060
1061         rte_eth_copy_pci_info(eth_dev, pci_dev);
1062
1063         /* Vendor and Device ID need to be set before init of shared code */
1064         hw->device_id = pci_dev->id.device_id;
1065         hw->vendor_id = pci_dev->id.vendor_id;
1066         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1067         hw->allow_unsupported_sfp = 1;
1068
1069         /* Initialize the shared code (base driver) */
1070 #ifdef RTE_NIC_BYPASS
1071         diag = ixgbe_bypass_init_shared_code(hw);
1072 #else
1073         diag = ixgbe_init_shared_code(hw);
1074 #endif /* RTE_NIC_BYPASS */
1075
1076         if (diag != IXGBE_SUCCESS) {
1077                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1078                 return -EIO;
1079         }
1080
1081         /* pick up the PCI bus settings for reporting later */
1082         ixgbe_get_bus_info(hw);
1083
1084         /* Unlock any pending hardware semaphore */
1085         ixgbe_swfw_lock_reset(hw);
1086
1087         /* Initialize DCB configuration*/
1088         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1089         ixgbe_dcb_init(hw,dcb_config);
1090         /* Get Hardware Flow Control setting */
1091         hw->fc.requested_mode = ixgbe_fc_full;
1092         hw->fc.current_mode = ixgbe_fc_full;
1093         hw->fc.pause_time = IXGBE_FC_PAUSE;
1094         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1095                 hw->fc.low_water[i] = IXGBE_FC_LO;
1096                 hw->fc.high_water[i] = IXGBE_FC_HI;
1097         }
1098         hw->fc.send_xon = 1;
1099
1100         /* Make sure we have a good EEPROM before we read from it */
1101         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1102         if (diag != IXGBE_SUCCESS) {
1103                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1104                 return -EIO;
1105         }
1106
1107 #ifdef RTE_NIC_BYPASS
1108         diag = ixgbe_bypass_init_hw(hw);
1109 #else
1110         diag = ixgbe_init_hw(hw);
1111 #endif /* RTE_NIC_BYPASS */
1112
1113         /*
1114          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1115          * is called too soon after the kernel driver unbinding/binding occurs.
1116          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1117          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1118          * also called. See ixgbe_identify_phy_82599(). The reason for the
1119          * failure is not known, and only occuts when virtualisation features
1120          * are disabled in the bios. A delay of 100ms  was found to be enough by
1121          * trial-and-error, and is doubled to be safe.
1122          */
1123         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1124                 rte_delay_ms(200);
1125                 diag = ixgbe_init_hw(hw);
1126         }
1127
1128         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1129                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1130                     "LOM.  Please be aware there may be issues associated "
1131                     "with your hardware.");
1132                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1133                     "please contact your Intel or hardware representative "
1134                     "who provided you with this hardware.");
1135         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1136                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1137         if (diag) {
1138                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1139                 return -EIO;
1140         }
1141
1142         /* Reset the hw statistics */
1143         ixgbe_dev_stats_reset(eth_dev);
1144
1145         /* disable interrupt */
1146         ixgbe_disable_intr(hw);
1147
1148         /* reset mappings for queue statistics hw counters*/
1149         ixgbe_reset_qstat_mappings(hw);
1150
1151         /* Allocate memory for storing MAC addresses */
1152         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1153                         hw->mac.num_rar_entries, 0);
1154         if (eth_dev->data->mac_addrs == NULL) {
1155                 PMD_INIT_LOG(ERR,
1156                         "Failed to allocate %u bytes needed to store "
1157                         "MAC addresses",
1158                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1159                 return -ENOMEM;
1160         }
1161         /* Copy the permanent MAC address */
1162         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1163                         &eth_dev->data->mac_addrs[0]);
1164
1165         /* Allocate memory for storing hash filter MAC addresses */
1166         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1168         if (eth_dev->data->hash_mac_addrs == NULL) {
1169                 PMD_INIT_LOG(ERR,
1170                         "Failed to allocate %d bytes needed to store MAC addresses",
1171                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1172                 return -ENOMEM;
1173         }
1174
1175         /* initialize the vfta */
1176         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1177
1178         /* initialize the hw strip bitmap*/
1179         memset(hwstrip, 0, sizeof(*hwstrip));
1180
1181         /* initialize PF if max_vfs not zero */
1182         ixgbe_pf_host_init(eth_dev);
1183
1184         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1185         /* let hardware know driver is loaded */
1186         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1187         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1188         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1189         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1190         IXGBE_WRITE_FLUSH(hw);
1191
1192         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1193                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1194                              (int) hw->mac.type, (int) hw->phy.type,
1195                              (int) hw->phy.sfp_type);
1196         else
1197                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1198                              (int) hw->mac.type, (int) hw->phy.type);
1199
1200         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1201                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1202                         pci_dev->id.device_id);
1203
1204         rte_intr_callback_register(&pci_dev->intr_handle,
1205                                    ixgbe_dev_interrupt_handler,
1206                                    (void *)eth_dev);
1207
1208         /* enable uio/vfio intr/eventfd mapping */
1209         rte_intr_enable(&pci_dev->intr_handle);
1210
1211         /* enable support intr */
1212         ixgbe_enable_intr(eth_dev);
1213
1214         /* initialize 5tuple filter list */
1215         TAILQ_INIT(&filter_info->fivetuple_list);
1216         memset(filter_info->fivetuple_mask, 0,
1217                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1218
1219         return 0;
1220 }
1221
1222 static int
1223 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1224 {
1225         struct rte_pci_device *pci_dev;
1226         struct ixgbe_hw *hw;
1227
1228         PMD_INIT_FUNC_TRACE();
1229
1230         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1231                 return -EPERM;
1232
1233         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1234         pci_dev = eth_dev->pci_dev;
1235
1236         if (hw->adapter_stopped == 0)
1237                 ixgbe_dev_close(eth_dev);
1238
1239         eth_dev->dev_ops = NULL;
1240         eth_dev->rx_pkt_burst = NULL;
1241         eth_dev->tx_pkt_burst = NULL;
1242
1243         /* Unlock any pending hardware semaphore */
1244         ixgbe_swfw_lock_reset(hw);
1245
1246         /* disable uio intr before callback unregister */
1247         rte_intr_disable(&(pci_dev->intr_handle));
1248         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1249                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1250
1251         /* uninitialize PF if max_vfs not zero */
1252         ixgbe_pf_host_uninit(eth_dev);
1253
1254         rte_free(eth_dev->data->mac_addrs);
1255         eth_dev->data->mac_addrs = NULL;
1256
1257         rte_free(eth_dev->data->hash_mac_addrs);
1258         eth_dev->data->hash_mac_addrs = NULL;
1259
1260         return 0;
1261 }
1262
1263 /*
1264  * Negotiate mailbox API version with the PF.
1265  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1266  * Then we try to negotiate starting with the most recent one.
1267  * If all negotiation attempts fail, then we will proceed with
1268  * the default one (ixgbe_mbox_api_10).
1269  */
1270 static void
1271 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1272 {
1273         int32_t i;
1274
1275         /* start with highest supported, proceed down */
1276         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1277                 ixgbe_mbox_api_12,
1278                 ixgbe_mbox_api_11,
1279                 ixgbe_mbox_api_10,
1280         };
1281
1282         for (i = 0;
1283                         i != RTE_DIM(sup_ver) &&
1284                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1285                         i++)
1286                 ;
1287 }
1288
1289 static void
1290 generate_random_mac_addr(struct ether_addr *mac_addr)
1291 {
1292         uint64_t random;
1293
1294         /* Set Organizationally Unique Identifier (OUI) prefix. */
1295         mac_addr->addr_bytes[0] = 0x00;
1296         mac_addr->addr_bytes[1] = 0x09;
1297         mac_addr->addr_bytes[2] = 0xC0;
1298         /* Force indication of locally assigned MAC address. */
1299         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1300         /* Generate the last 3 bytes of the MAC address with a random number. */
1301         random = rte_rand();
1302         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1303 }
1304
1305 /*
1306  * Virtual Function device init
1307  */
1308 static int
1309 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1310 {
1311         int diag;
1312         uint32_t tc, tcs;
1313         struct rte_pci_device *pci_dev;
1314         struct ixgbe_hw *hw =
1315                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1316         struct ixgbe_vfta * shadow_vfta =
1317                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1318         struct ixgbe_hwstrip *hwstrip =
1319                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1320         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1321
1322         PMD_INIT_FUNC_TRACE();
1323
1324         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1325         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1326         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1327
1328         /* for secondary processes, we don't initialise any further as primary
1329          * has already done this work. Only check we don't need a different
1330          * RX function */
1331         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1332                 struct ixgbe_tx_queue *txq;
1333                 /* TX queue function in primary, set by last queue initialized
1334                  * Tx queue may not initialized by primary process
1335                  */
1336                 if (eth_dev->data->tx_queues) {
1337                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1338                         ixgbe_set_tx_function(eth_dev, txq);
1339                 } else {
1340                         /* Use default TX function if we get here */
1341                         PMD_INIT_LOG(NOTICE,
1342                                 "No TX queues configured yet. Using default TX function.");
1343                 }
1344
1345                 ixgbe_set_rx_function(eth_dev);
1346
1347                 return 0;
1348         }
1349
1350         pci_dev = eth_dev->pci_dev;
1351
1352         rte_eth_copy_pci_info(eth_dev, pci_dev);
1353
1354         hw->device_id = pci_dev->id.device_id;
1355         hw->vendor_id = pci_dev->id.vendor_id;
1356         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1357
1358         /* initialize the vfta */
1359         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1360
1361         /* initialize the hw strip bitmap*/
1362         memset(hwstrip, 0, sizeof(*hwstrip));
1363
1364         /* Initialize the shared code (base driver) */
1365         diag = ixgbe_init_shared_code(hw);
1366         if (diag != IXGBE_SUCCESS) {
1367                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1368                 return -EIO;
1369         }
1370
1371         /* init_mailbox_params */
1372         hw->mbx.ops.init_params(hw);
1373
1374         /* Reset the hw statistics */
1375         ixgbevf_dev_stats_reset(eth_dev);
1376
1377         /* Disable the interrupts for VF */
1378         ixgbevf_intr_disable(hw);
1379
1380         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1381         diag = hw->mac.ops.reset_hw(hw);
1382
1383         /*
1384          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1385          * the underlying PF driver has not assigned a MAC address to the VF.
1386          * In this case, assign a random MAC address.
1387          */
1388         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1389                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1390                 return diag;
1391         }
1392
1393         /* negotiate mailbox API version to use with the PF. */
1394         ixgbevf_negotiate_api(hw);
1395
1396         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1397         ixgbevf_get_queues(hw, &tcs, &tc);
1398
1399         /* Allocate memory for storing MAC addresses */
1400         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1401                         hw->mac.num_rar_entries, 0);
1402         if (eth_dev->data->mac_addrs == NULL) {
1403                 PMD_INIT_LOG(ERR,
1404                         "Failed to allocate %u bytes needed to store "
1405                         "MAC addresses",
1406                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1407                 return -ENOMEM;
1408         }
1409
1410         /* Generate a random MAC address, if none was assigned by PF. */
1411         if (is_zero_ether_addr(perm_addr)) {
1412                 generate_random_mac_addr(perm_addr);
1413                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1414                 if (diag) {
1415                         rte_free(eth_dev->data->mac_addrs);
1416                         eth_dev->data->mac_addrs = NULL;
1417                         return diag;
1418                 }
1419                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1420                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1421                              "%02x:%02x:%02x:%02x:%02x:%02x",
1422                              perm_addr->addr_bytes[0],
1423                              perm_addr->addr_bytes[1],
1424                              perm_addr->addr_bytes[2],
1425                              perm_addr->addr_bytes[3],
1426                              perm_addr->addr_bytes[4],
1427                              perm_addr->addr_bytes[5]);
1428         }
1429
1430         /* Copy the permanent MAC address */
1431         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1432
1433         /* reset the hardware with the new settings */
1434         diag = hw->mac.ops.start_hw(hw);
1435         switch (diag) {
1436                 case  0:
1437                         break;
1438
1439                 default:
1440                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1441                         return -EIO;
1442         }
1443
1444         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1445                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1446                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1447
1448         return 0;
1449 }
1450
1451 /* Virtual Function device uninit */
1452
1453 static int
1454 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1455 {
1456         struct ixgbe_hw *hw;
1457
1458         PMD_INIT_FUNC_TRACE();
1459
1460         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1461                 return -EPERM;
1462
1463         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1464
1465         if (hw->adapter_stopped == 0)
1466                 ixgbevf_dev_close(eth_dev);
1467
1468         eth_dev->dev_ops = NULL;
1469         eth_dev->rx_pkt_burst = NULL;
1470         eth_dev->tx_pkt_burst = NULL;
1471
1472         /* Disable the interrupts for VF */
1473         ixgbevf_intr_disable(hw);
1474
1475         rte_free(eth_dev->data->mac_addrs);
1476         eth_dev->data->mac_addrs = NULL;
1477
1478         return 0;
1479 }
1480
1481 static struct eth_driver rte_ixgbe_pmd = {
1482         .pci_drv = {
1483                 .name = "rte_ixgbe_pmd",
1484                 .id_table = pci_id_ixgbe_map,
1485                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1486                         RTE_PCI_DRV_DETACHABLE,
1487         },
1488         .eth_dev_init = eth_ixgbe_dev_init,
1489         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1490         .dev_private_size = sizeof(struct ixgbe_adapter),
1491 };
1492
1493 /*
1494  * virtual function driver struct
1495  */
1496 static struct eth_driver rte_ixgbevf_pmd = {
1497         .pci_drv = {
1498                 .name = "rte_ixgbevf_pmd",
1499                 .id_table = pci_id_ixgbevf_map,
1500                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1501         },
1502         .eth_dev_init = eth_ixgbevf_dev_init,
1503         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1504         .dev_private_size = sizeof(struct ixgbe_adapter),
1505 };
1506
1507 /*
1508  * Driver initialization routine.
1509  * Invoked once at EAL init time.
1510  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1511  */
1512 static int
1513 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1514 {
1515         PMD_INIT_FUNC_TRACE();
1516
1517         rte_eth_driver_register(&rte_ixgbe_pmd);
1518         return 0;
1519 }
1520
1521 /*
1522  * VF Driver initialization routine.
1523  * Invoked one at EAL init time.
1524  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1525  */
1526 static int
1527 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1528 {
1529         PMD_INIT_FUNC_TRACE();
1530
1531         rte_eth_driver_register(&rte_ixgbevf_pmd);
1532         return 0;
1533 }
1534
1535 static int
1536 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1537 {
1538         struct ixgbe_hw *hw =
1539                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1540         struct ixgbe_vfta * shadow_vfta =
1541                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1542         uint32_t vfta;
1543         uint32_t vid_idx;
1544         uint32_t vid_bit;
1545
1546         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1547         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1548         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1549         if (on)
1550                 vfta |= vid_bit;
1551         else
1552                 vfta &= ~vid_bit;
1553         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1554
1555         /* update local VFTA copy */
1556         shadow_vfta->vfta[vid_idx] = vfta;
1557
1558         return 0;
1559 }
1560
1561 static void
1562 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1563 {
1564         if (on)
1565                 ixgbe_vlan_hw_strip_enable(dev, queue);
1566         else
1567                 ixgbe_vlan_hw_strip_disable(dev, queue);
1568 }
1569
1570 static int
1571 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1572                     enum rte_vlan_type vlan_type,
1573                     uint16_t tpid)
1574 {
1575         struct ixgbe_hw *hw =
1576                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577         int ret = 0;
1578
1579         switch (vlan_type) {
1580         case ETH_VLAN_TYPE_INNER:
1581                 /* Only the high 16-bits is valid */
1582                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1583                 break;
1584         default:
1585                 ret = -EINVAL;
1586                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1587                 break;
1588         }
1589
1590         return ret;
1591 }
1592
1593 void
1594 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1595 {
1596         struct ixgbe_hw *hw =
1597                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598         uint32_t vlnctrl;
1599
1600         PMD_INIT_FUNC_TRACE();
1601
1602         /* Filter Table Disable */
1603         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1604         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1605
1606         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1607 }
1608
1609 void
1610 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1611 {
1612         struct ixgbe_hw *hw =
1613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614         struct ixgbe_vfta * shadow_vfta =
1615                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1616         uint32_t vlnctrl;
1617         uint16_t i;
1618
1619         PMD_INIT_FUNC_TRACE();
1620
1621         /* Filter Table Enable */
1622         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1623         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1624         vlnctrl |= IXGBE_VLNCTRL_VFE;
1625
1626         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1627
1628         /* write whatever is in local vfta copy */
1629         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1630                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1631 }
1632
1633 static void
1634 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1635 {
1636         struct ixgbe_hwstrip *hwstrip =
1637                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1638
1639         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1640                 return;
1641
1642         if (on)
1643                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1644         else
1645                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1646 }
1647
1648 static void
1649 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1650 {
1651         struct ixgbe_hw *hw =
1652                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653         uint32_t ctrl;
1654
1655         PMD_INIT_FUNC_TRACE();
1656
1657         if (hw->mac.type == ixgbe_mac_82598EB) {
1658                 /* No queue level support */
1659                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1660                 return;
1661         }
1662         else {
1663                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1664                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1665                 ctrl &= ~IXGBE_RXDCTL_VME;
1666                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1667         }
1668         /* record those setting for HW strip per queue */
1669         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1670 }
1671
1672 static void
1673 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1674 {
1675         struct ixgbe_hw *hw =
1676                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677         uint32_t ctrl;
1678
1679         PMD_INIT_FUNC_TRACE();
1680
1681         if (hw->mac.type == ixgbe_mac_82598EB) {
1682                 /* No queue level supported */
1683                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1684                 return;
1685         }
1686         else {
1687                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1688                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1689                 ctrl |= IXGBE_RXDCTL_VME;
1690                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1691         }
1692         /* record those setting for HW strip per queue */
1693         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1694 }
1695
1696 void
1697 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1698 {
1699         struct ixgbe_hw *hw =
1700                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701         uint32_t ctrl;
1702         uint16_t i;
1703
1704         PMD_INIT_FUNC_TRACE();
1705
1706         if (hw->mac.type == ixgbe_mac_82598EB) {
1707                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1708                 ctrl &= ~IXGBE_VLNCTRL_VME;
1709                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1710         }
1711         else {
1712                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1713                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1714                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1715                         ctrl &= ~IXGBE_RXDCTL_VME;
1716                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1717
1718                         /* record those setting for HW strip per queue */
1719                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1720                 }
1721         }
1722 }
1723
1724 void
1725 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1726 {
1727         struct ixgbe_hw *hw =
1728                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729         uint32_t ctrl;
1730         uint16_t i;
1731
1732         PMD_INIT_FUNC_TRACE();
1733
1734         if (hw->mac.type == ixgbe_mac_82598EB) {
1735                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1736                 ctrl |= IXGBE_VLNCTRL_VME;
1737                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1738         }
1739         else {
1740                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1741                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1742                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1743                         ctrl |= IXGBE_RXDCTL_VME;
1744                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1745
1746                         /* record those setting for HW strip per queue */
1747                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1748                 }
1749         }
1750 }
1751
1752 static void
1753 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1754 {
1755         struct ixgbe_hw *hw =
1756                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757         uint32_t ctrl;
1758
1759         PMD_INIT_FUNC_TRACE();
1760
1761         /* DMATXCTRL: Geric Double VLAN Disable */
1762         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1763         ctrl &= ~IXGBE_DMATXCTL_GDV;
1764         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1765
1766         /* CTRL_EXT: Global Double VLAN Disable */
1767         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1768         ctrl &= ~IXGBE_EXTENDED_VLAN;
1769         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1770
1771 }
1772
1773 static void
1774 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1775 {
1776         struct ixgbe_hw *hw =
1777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1778         uint32_t ctrl;
1779
1780         PMD_INIT_FUNC_TRACE();
1781
1782         /* DMATXCTRL: Geric Double VLAN Enable */
1783         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1784         ctrl |= IXGBE_DMATXCTL_GDV;
1785         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1786
1787         /* CTRL_EXT: Global Double VLAN Enable */
1788         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1789         ctrl |= IXGBE_EXTENDED_VLAN;
1790         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1791
1792         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1793         if (hw->mac.type == ixgbe_mac_X550 ||
1794             hw->mac.type == ixgbe_mac_X550EM_x) {
1795                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1796                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1797                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1798         }
1799
1800         /*
1801          * VET EXT field in the EXVET register = 0x8100 by default
1802          * So no need to change. Same to VT field of DMATXCTL register
1803          */
1804 }
1805
1806 static void
1807 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1808 {
1809         if (mask & ETH_VLAN_STRIP_MASK) {
1810                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1811                         ixgbe_vlan_hw_strip_enable_all(dev);
1812                 else
1813                         ixgbe_vlan_hw_strip_disable_all(dev);
1814         }
1815
1816         if (mask & ETH_VLAN_FILTER_MASK) {
1817                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1818                         ixgbe_vlan_hw_filter_enable(dev);
1819                 else
1820                         ixgbe_vlan_hw_filter_disable(dev);
1821         }
1822
1823         if (mask & ETH_VLAN_EXTEND_MASK) {
1824                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1825                         ixgbe_vlan_hw_extend_enable(dev);
1826                 else
1827                         ixgbe_vlan_hw_extend_disable(dev);
1828         }
1829 }
1830
1831 static void
1832 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1833 {
1834         struct ixgbe_hw *hw =
1835                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1837         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1838         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1839         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1840 }
1841
1842 static int
1843 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1844 {
1845         switch (nb_rx_q) {
1846         case 1:
1847         case 2:
1848                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1849                 break;
1850         case 4:
1851                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1852                 break;
1853         default:
1854                 return -EINVAL;
1855         }
1856
1857         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1858         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1859
1860         return 0;
1861 }
1862
1863 static int
1864 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1865 {
1866         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1867         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1868         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1869         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1870
1871         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1872                 /* check multi-queue mode */
1873                 switch (dev_conf->rxmode.mq_mode) {
1874                 case ETH_MQ_RX_VMDQ_DCB:
1875                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1876                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1877                         PMD_INIT_LOG(ERR, "SRIOV active,"
1878                                         " unsupported mq_mode rx %d.",
1879                                         dev_conf->rxmode.mq_mode);
1880                         return -EINVAL;
1881                 case ETH_MQ_RX_RSS:
1882                 case ETH_MQ_RX_VMDQ_RSS:
1883                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1884                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1885                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1886                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1887                                                 " invalid queue number"
1888                                                 " for VMDQ RSS, allowed"
1889                                                 " value are 1, 2 or 4.");
1890                                         return -EINVAL;
1891                                 }
1892                         break;
1893                 case ETH_MQ_RX_VMDQ_ONLY:
1894                 case ETH_MQ_RX_NONE:
1895                         /* if nothing mq mode configure, use default scheme */
1896                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1897                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1898                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1899                         break;
1900                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1901                         /* SRIOV only works in VMDq enable mode */
1902                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1903                                         " wrong mq_mode rx %d.",
1904                                         dev_conf->rxmode.mq_mode);
1905                         return -EINVAL;
1906                 }
1907
1908                 switch (dev_conf->txmode.mq_mode) {
1909                 case ETH_MQ_TX_VMDQ_DCB:
1910                         /* DCB VMDQ in SRIOV mode, not implement yet */
1911                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1912                                         " unsupported VMDQ mq_mode tx %d.",
1913                                         dev_conf->txmode.mq_mode);
1914                         return -EINVAL;
1915                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1916                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1917                         break;
1918                 }
1919
1920                 /* check valid queue number */
1921                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1922                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1923                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1924                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1925                                         " must be less than or equal to %d.",
1926                                         nb_rx_q, nb_tx_q,
1927                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1928                         return -EINVAL;
1929                 }
1930         } else {
1931                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1932                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1933                                           " not supported.");
1934                         return -EINVAL;
1935                 }
1936                 /* check configuration for vmdb+dcb mode */
1937                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1938                         const struct rte_eth_vmdq_dcb_conf *conf;
1939
1940                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1941                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1942                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1943                                 return -EINVAL;
1944                         }
1945                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1946                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1947                                conf->nb_queue_pools == ETH_32_POOLS)) {
1948                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1949                                                 " nb_queue_pools must be %d or %d.",
1950                                                 ETH_16_POOLS, ETH_32_POOLS);
1951                                 return -EINVAL;
1952                         }
1953                 }
1954                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1955                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1956
1957                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1958                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1959                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1960                                 return -EINVAL;
1961                         }
1962                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1963                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1964                                conf->nb_queue_pools == ETH_32_POOLS)) {
1965                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1966                                                 " nb_queue_pools != %d and"
1967                                                 " nb_queue_pools != %d.",
1968                                                 ETH_16_POOLS, ETH_32_POOLS);
1969                                 return -EINVAL;
1970                         }
1971                 }
1972
1973                 /* For DCB mode check our configuration before we go further */
1974                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1975                         const struct rte_eth_dcb_rx_conf *conf;
1976
1977                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1978                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1979                                                  IXGBE_DCB_NB_QUEUES);
1980                                 return -EINVAL;
1981                         }
1982                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1983                         if (!(conf->nb_tcs == ETH_4_TCS ||
1984                                conf->nb_tcs == ETH_8_TCS)) {
1985                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1986                                                 " and nb_tcs != %d.",
1987                                                 ETH_4_TCS, ETH_8_TCS);
1988                                 return -EINVAL;
1989                         }
1990                 }
1991
1992                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1993                         const struct rte_eth_dcb_tx_conf *conf;
1994
1995                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1996                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1997                                                  IXGBE_DCB_NB_QUEUES);
1998                                 return -EINVAL;
1999                         }
2000                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2001                         if (!(conf->nb_tcs == ETH_4_TCS ||
2002                                conf->nb_tcs == ETH_8_TCS)) {
2003                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2004                                                 " and nb_tcs != %d.",
2005                                                 ETH_4_TCS, ETH_8_TCS);
2006                                 return -EINVAL;
2007                         }
2008                 }
2009
2010                 /*
2011                  * When DCB/VT is off, maximum number of queues changes,
2012                  * except for 82598EB, which remains constant.
2013                  */
2014                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2015                                 hw->mac.type != ixgbe_mac_82598EB) {
2016                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2017                                 PMD_INIT_LOG(ERR,
2018                                              "Neither VT nor DCB are enabled, "
2019                                              "nb_tx_q > %d.",
2020                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2021                                 return -EINVAL;
2022                         }
2023                 }
2024         }
2025         return 0;
2026 }
2027
2028 static int
2029 ixgbe_dev_configure(struct rte_eth_dev *dev)
2030 {
2031         struct ixgbe_interrupt *intr =
2032                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2033         struct ixgbe_adapter *adapter =
2034                 (struct ixgbe_adapter *)dev->data->dev_private;
2035         int ret;
2036
2037         PMD_INIT_FUNC_TRACE();
2038         /* multipe queue mode checking */
2039         ret  = ixgbe_check_mq_mode(dev);
2040         if (ret != 0) {
2041                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2042                             ret);
2043                 return ret;
2044         }
2045
2046         /* set flag to update link status after init */
2047         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2048
2049         /*
2050          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2051          * allocation or vector Rx preconditions we will reset it.
2052          */
2053         adapter->rx_bulk_alloc_allowed = true;
2054         adapter->rx_vec_allowed = true;
2055
2056         return 0;
2057 }
2058
2059 static void
2060 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2061 {
2062         struct ixgbe_hw *hw =
2063                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2064         struct ixgbe_interrupt *intr =
2065                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2066         uint32_t gpie;
2067
2068         /* only set up it on X550EM_X */
2069         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2070                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2071                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2072                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2073                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2074                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2075         }
2076 }
2077
2078 /*
2079  * Configure device link speed and setup link.
2080  * It returns 0 on success.
2081  */
2082 static int
2083 ixgbe_dev_start(struct rte_eth_dev *dev)
2084 {
2085         struct ixgbe_hw *hw =
2086                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087         struct ixgbe_vf_info *vfinfo =
2088                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2089         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2090         uint32_t intr_vector = 0;
2091         int err, link_up = 0, negotiate = 0;
2092         uint32_t speed = 0;
2093         int mask = 0;
2094         int status;
2095         uint16_t vf, idx;
2096
2097         PMD_INIT_FUNC_TRACE();
2098
2099         /* IXGBE devices don't support half duplex */
2100         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2101                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2102                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2103                              dev->data->dev_conf.link_duplex,
2104                              dev->data->port_id);
2105                 return -EINVAL;
2106         }
2107
2108         /* disable uio/vfio intr/eventfd mapping */
2109         rte_intr_disable(intr_handle);
2110
2111         /* stop adapter */
2112         hw->adapter_stopped = 0;
2113         ixgbe_stop_adapter(hw);
2114
2115         /* reinitialize adapter
2116          * this calls reset and start */
2117         status = ixgbe_pf_reset_hw(hw);
2118         if (status != 0)
2119                 return -1;
2120         hw->mac.ops.start_hw(hw);
2121         hw->mac.get_link_status = true;
2122
2123         /* configure PF module if SRIOV enabled */
2124         ixgbe_pf_host_configure(dev);
2125
2126         ixgbe_dev_phy_intr_setup(dev);
2127
2128         /* check and configure queue intr-vector mapping */
2129         if ((rte_intr_cap_multiple(intr_handle) ||
2130              !RTE_ETH_DEV_SRIOV(dev).active) &&
2131             dev->data->dev_conf.intr_conf.rxq != 0) {
2132                 intr_vector = dev->data->nb_rx_queues;
2133                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2134                         return -1;
2135         }
2136
2137         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2138                 intr_handle->intr_vec =
2139                         rte_zmalloc("intr_vec",
2140                                     dev->data->nb_rx_queues * sizeof(int), 0);
2141                 if (intr_handle->intr_vec == NULL) {
2142                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2143                                      " intr_vec\n", dev->data->nb_rx_queues);
2144                         return -ENOMEM;
2145                 }
2146         }
2147
2148         /* confiugre msix for sleep until rx interrupt */
2149         ixgbe_configure_msix(dev);
2150
2151         /* initialize transmission unit */
2152         ixgbe_dev_tx_init(dev);
2153
2154         /* This can fail when allocating mbufs for descriptor rings */
2155         err = ixgbe_dev_rx_init(dev);
2156         if (err) {
2157                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2158                 goto error;
2159         }
2160
2161         err = ixgbe_dev_rxtx_start(dev);
2162         if (err < 0) {
2163                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2164                 goto error;
2165         }
2166
2167         /* Skip link setup if loopback mode is enabled for 82599. */
2168         if (hw->mac.type == ixgbe_mac_82599EB &&
2169                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2170                 goto skip_link_setup;
2171
2172         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2173                 err = hw->mac.ops.setup_sfp(hw);
2174                 if (err)
2175                         goto error;
2176         }
2177
2178         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2179                 /* Turn on the copper */
2180                 ixgbe_set_phy_power(hw, true);
2181         } else {
2182                 /* Turn on the laser */
2183                 ixgbe_enable_tx_laser(hw);
2184         }
2185
2186         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2187         if (err)
2188                 goto error;
2189         dev->data->dev_link.link_status = link_up;
2190
2191         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2192         if (err)
2193                 goto error;
2194
2195         switch(dev->data->dev_conf.link_speed) {
2196         case ETH_LINK_SPEED_AUTONEG:
2197                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2198                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2199                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2200                 break;
2201         case ETH_LINK_SPEED_100:
2202                 /*
2203                  * Invalid for 82598 but error will be detected by
2204                  * ixgbe_setup_link()
2205                  */
2206                 speed = IXGBE_LINK_SPEED_100_FULL;
2207                 break;
2208         case ETH_LINK_SPEED_1000:
2209                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2210                 break;
2211         case ETH_LINK_SPEED_10000:
2212                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2213                 break;
2214         default:
2215                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2216                              dev->data->dev_conf.link_speed,
2217                              dev->data->port_id);
2218                 goto error;
2219         }
2220
2221         err = ixgbe_setup_link(hw, speed, link_up);
2222         if (err)
2223                 goto error;
2224
2225 skip_link_setup:
2226
2227         if (rte_intr_allow_others(intr_handle)) {
2228                 /* check if lsc interrupt is enabled */
2229                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2230                         ixgbe_dev_lsc_interrupt_setup(dev);
2231         } else {
2232                 rte_intr_callback_unregister(intr_handle,
2233                                              ixgbe_dev_interrupt_handler,
2234                                              (void *)dev);
2235                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2236                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2237                                      " no intr multiplex\n");
2238         }
2239
2240         /* check if rxq interrupt is enabled */
2241         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2242             rte_intr_dp_is_en(intr_handle))
2243                 ixgbe_dev_rxq_interrupt_setup(dev);
2244
2245         /* enable uio/vfio intr/eventfd mapping */
2246         rte_intr_enable(intr_handle);
2247
2248         /* resume enabled intr since hw reset */
2249         ixgbe_enable_intr(dev);
2250
2251         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2252                 ETH_VLAN_EXTEND_MASK;
2253         ixgbe_vlan_offload_set(dev, mask);
2254
2255         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2256                 /* Enable vlan filtering for VMDq */
2257                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2258         }
2259
2260         /* Configure DCB hw */
2261         ixgbe_configure_dcb(dev);
2262
2263         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2264                 err = ixgbe_fdir_configure(dev);
2265                 if (err)
2266                         goto error;
2267         }
2268
2269         /* Restore vf rate limit */
2270         if (vfinfo != NULL) {
2271                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2272                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2273                                 if (vfinfo[vf].tx_rate[idx] != 0)
2274                                         ixgbe_set_vf_rate_limit(dev, vf,
2275                                                 vfinfo[vf].tx_rate[idx],
2276                                                 1 << idx);
2277         }
2278
2279         ixgbe_restore_statistics_mapping(dev);
2280
2281         return 0;
2282
2283 error:
2284         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2285         ixgbe_dev_clear_queues(dev);
2286         return -EIO;
2287 }
2288
2289 /*
2290  * Stop device: disable rx and tx functions to allow for reconfiguring.
2291  */
2292 static void
2293 ixgbe_dev_stop(struct rte_eth_dev *dev)
2294 {
2295         struct rte_eth_link link;
2296         struct ixgbe_hw *hw =
2297                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2298         struct ixgbe_vf_info *vfinfo =
2299                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2300         struct ixgbe_filter_info *filter_info =
2301                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2302         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2303         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2304         int vf;
2305
2306         PMD_INIT_FUNC_TRACE();
2307
2308         /* disable interrupts */
2309         ixgbe_disable_intr(hw);
2310
2311         /* reset the NIC */
2312         ixgbe_pf_reset_hw(hw);
2313         hw->adapter_stopped = 0;
2314
2315         /* stop adapter */
2316         ixgbe_stop_adapter(hw);
2317
2318         for (vf = 0; vfinfo != NULL &&
2319                      vf < dev->pci_dev->max_vfs; vf++)
2320                 vfinfo[vf].clear_to_send = false;
2321
2322         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2323                 /* Turn off the copper */
2324                 ixgbe_set_phy_power(hw, false);
2325         } else {
2326                 /* Turn off the laser */
2327                 ixgbe_disable_tx_laser(hw);
2328         }
2329
2330         ixgbe_dev_clear_queues(dev);
2331
2332         /* Clear stored conf */
2333         dev->data->scattered_rx = 0;
2334         dev->data->lro = 0;
2335
2336         /* Clear recorded link status */
2337         memset(&link, 0, sizeof(link));
2338         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2339
2340         /* Remove all ntuple filters of the device */
2341         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2342              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2343                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2344                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2345                              p_5tuple, entries);
2346                 rte_free(p_5tuple);
2347         }
2348         memset(filter_info->fivetuple_mask, 0,
2349                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2350
2351         if (!rte_intr_allow_others(intr_handle))
2352                 /* resume to the default handler */
2353                 rte_intr_callback_register(intr_handle,
2354                                            ixgbe_dev_interrupt_handler,
2355                                            (void *)dev);
2356
2357         /* Clean datapath event and queue/vec mapping */
2358         rte_intr_efd_disable(intr_handle);
2359         if (intr_handle->intr_vec != NULL) {
2360                 rte_free(intr_handle->intr_vec);
2361                 intr_handle->intr_vec = NULL;
2362         }
2363 }
2364
2365 /*
2366  * Set device link up: enable tx.
2367  */
2368 static int
2369 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2370 {
2371         struct ixgbe_hw *hw =
2372                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2373         if (hw->mac.type == ixgbe_mac_82599EB) {
2374 #ifdef RTE_NIC_BYPASS
2375                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2376                         /* Not suported in bypass mode */
2377                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2378                                      "by device id 0x%x", hw->device_id);
2379                         return -ENOTSUP;
2380                 }
2381 #endif
2382         }
2383
2384         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2385                 /* Turn on the copper */
2386                 ixgbe_set_phy_power(hw, true);
2387         } else {
2388                 /* Turn on the laser */
2389                 ixgbe_enable_tx_laser(hw);
2390         }
2391
2392         return 0;
2393 }
2394
2395 /*
2396  * Set device link down: disable tx.
2397  */
2398 static int
2399 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2400 {
2401         struct ixgbe_hw *hw =
2402                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2403         if (hw->mac.type == ixgbe_mac_82599EB) {
2404 #ifdef RTE_NIC_BYPASS
2405                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2406                         /* Not suported in bypass mode */
2407                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2408                                      "by device id 0x%x", hw->device_id);
2409                         return -ENOTSUP;
2410                 }
2411 #endif
2412         }
2413
2414         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2415                 /* Turn off the copper */
2416                 ixgbe_set_phy_power(hw, false);
2417         } else {
2418                 /* Turn off the laser */
2419                 ixgbe_disable_tx_laser(hw);
2420         }
2421
2422         return 0;
2423 }
2424
2425 /*
2426  * Reest and stop device.
2427  */
2428 static void
2429 ixgbe_dev_close(struct rte_eth_dev *dev)
2430 {
2431         struct ixgbe_hw *hw =
2432                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2433
2434         PMD_INIT_FUNC_TRACE();
2435
2436         ixgbe_pf_reset_hw(hw);
2437
2438         ixgbe_dev_stop(dev);
2439         hw->adapter_stopped = 1;
2440
2441         ixgbe_dev_free_queues(dev);
2442
2443         ixgbe_disable_pcie_master(hw);
2444
2445         /* reprogram the RAR[0] in case user changed it. */
2446         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2447 }
2448
2449 static void
2450 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2451                            struct ixgbe_hw_stats *hw_stats,
2452                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2453                            uint64_t *total_qprc, uint64_t *total_qprdc)
2454 {
2455         uint32_t bprc, lxon, lxoff, total;
2456         uint32_t delta_gprc = 0;
2457         unsigned i;
2458         /* Workaround for RX byte count not including CRC bytes when CRC
2459 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2460          * is disabled.
2461 +        */
2462         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2463                         IXGBE_HLREG0_RXCRCSTRP);
2464
2465         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2466         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2467         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2468         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2469
2470         for (i = 0; i < 8; i++) {
2471                 uint32_t mp;
2472                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2473                 /* global total per queue */
2474                 hw_stats->mpc[i] += mp;
2475                 /* Running comprehensive total for stats display */
2476                 *total_missed_rx += hw_stats->mpc[i];
2477                 if (hw->mac.type == ixgbe_mac_82598EB) {
2478                         hw_stats->rnbc[i] +=
2479                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2480                         hw_stats->pxonrxc[i] +=
2481                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2482                         hw_stats->pxoffrxc[i] +=
2483                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2484                 } else {
2485                         hw_stats->pxonrxc[i] +=
2486                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2487                         hw_stats->pxoffrxc[i] +=
2488                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2489                         hw_stats->pxon2offc[i] +=
2490                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2491                 }
2492                 hw_stats->pxontxc[i] +=
2493                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2494                 hw_stats->pxofftxc[i] +=
2495                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2496         }
2497         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2498                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2499                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2500                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2501
2502                 delta_gprc += delta_qprc;
2503
2504                 hw_stats->qprc[i] += delta_qprc;
2505                 hw_stats->qptc[i] += delta_qptc;
2506
2507                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2508                 hw_stats->qbrc[i] +=
2509                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2510                 if (crc_strip == 0)
2511                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2512
2513                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2514                 hw_stats->qbtc[i] +=
2515                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2516
2517                 hw_stats->qprdc[i] += delta_qprdc;
2518                 *total_qprdc += hw_stats->qprdc[i];
2519
2520                 *total_qprc += hw_stats->qprc[i];
2521                 *total_qbrc += hw_stats->qbrc[i];
2522         }
2523         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2524         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2525         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2526
2527         /*
2528          * An errata states that gprc actually counts good + missed packets:
2529          * Workaround to set gprc to summated queue packet receives
2530          */
2531         hw_stats->gprc = *total_qprc;
2532
2533         if (hw->mac.type != ixgbe_mac_82598EB) {
2534                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2535                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2536                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2537                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2538                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2539                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2540                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2541                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2542         } else {
2543                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2544                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2545                 /* 82598 only has a counter in the high register */
2546                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2547                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2548                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2549         }
2550         uint64_t old_tpr = hw_stats->tpr;
2551
2552         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2553         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2554
2555         if (crc_strip == 0)
2556                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2557
2558         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2559         hw_stats->gptc += delta_gptc;
2560         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2561         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2562
2563         /*
2564          * Workaround: mprc hardware is incorrectly counting
2565          * broadcasts, so for now we subtract those.
2566          */
2567         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2568         hw_stats->bprc += bprc;
2569         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2570         if (hw->mac.type == ixgbe_mac_82598EB)
2571                 hw_stats->mprc -= bprc;
2572
2573         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2574         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2575         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2576         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2577         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2578         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2579
2580         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2581         hw_stats->lxontxc += lxon;
2582         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2583         hw_stats->lxofftxc += lxoff;
2584         total = lxon + lxoff;
2585
2586         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2587         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2588         hw_stats->gptc -= total;
2589         hw_stats->mptc -= total;
2590         hw_stats->ptc64 -= total;
2591         hw_stats->gotc -= total * ETHER_MIN_LEN;
2592
2593         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2594         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2595         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2596         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2597         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2598         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2599         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2600         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2601         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2602         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2603         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2604         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2605         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2606         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2607         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2608         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2609         /* Only read FCOE on 82599 */
2610         if (hw->mac.type != ixgbe_mac_82598EB) {
2611                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2612                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2613                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2614                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2615                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2616         }
2617
2618         /* Flow Director Stats registers */
2619         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2620         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2621 }
2622
2623 /*
2624  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2625  */
2626 static void
2627 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2628 {
2629         struct ixgbe_hw *hw =
2630                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2631         struct ixgbe_hw_stats *hw_stats =
2632                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2633         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2634         unsigned i;
2635
2636         total_missed_rx = 0;
2637         total_qbrc = 0;
2638         total_qprc = 0;
2639         total_qprdc = 0;
2640
2641         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2642                         &total_qprc, &total_qprdc);
2643
2644         if (stats == NULL)
2645                 return;
2646
2647         /* Fill out the rte_eth_stats statistics structure */
2648         stats->ipackets = total_qprc;
2649         stats->ibytes = total_qbrc;
2650         stats->opackets = hw_stats->gptc;
2651         stats->obytes = hw_stats->gotc;
2652
2653         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2654                 stats->q_ipackets[i] = hw_stats->qprc[i];
2655                 stats->q_opackets[i] = hw_stats->qptc[i];
2656                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2657                 stats->q_obytes[i] = hw_stats->qbtc[i];
2658                 stats->q_errors[i] = hw_stats->qprdc[i];
2659         }
2660
2661         /* Rx Errors */
2662         stats->imissed  = total_missed_rx;
2663         stats->ierrors  = hw_stats->crcerrs +
2664                           hw_stats->mspdc +
2665                           hw_stats->rlec +
2666                           hw_stats->ruc +
2667                           hw_stats->roc +
2668                           hw_stats->illerrc +
2669                           hw_stats->errbc +
2670                           hw_stats->rfc +
2671                           hw_stats->fccrc +
2672                           hw_stats->fclast;
2673
2674         /* Tx Errors */
2675         stats->oerrors  = 0;
2676 }
2677
2678 static void
2679 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2680 {
2681         struct ixgbe_hw_stats *stats =
2682                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2683
2684         /* HW registers are cleared on read */
2685         ixgbe_dev_stats_get(dev, NULL);
2686
2687         /* Reset software totals */
2688         memset(stats, 0, sizeof(*stats));
2689 }
2690
2691 /* This function calculates the number of xstats based on the current config */
2692 static unsigned
2693 ixgbe_xstats_calc_num(void) {
2694         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2695                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2696 }
2697
2698 static int
2699 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2700                                          unsigned n)
2701 {
2702         struct ixgbe_hw *hw =
2703                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704         struct ixgbe_hw_stats *hw_stats =
2705                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2706         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2707         unsigned i, stat, count = 0;
2708
2709         count = ixgbe_xstats_calc_num();
2710
2711         if (n < count)
2712                 return count;
2713
2714         total_missed_rx = 0;
2715         total_qbrc = 0;
2716         total_qprc = 0;
2717         total_qprdc = 0;
2718
2719         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2720                                    &total_qprc, &total_qprdc);
2721
2722         /* If this is a reset xstats is NULL, and we have cleared the
2723          * registers by reading them.
2724          */
2725         if (!xstats)
2726                 return 0;
2727
2728         /* Extended stats from ixgbe_hw_stats */
2729         count = 0;
2730         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2731                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2732                          rte_ixgbe_stats_strings[i].name);
2733                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2734                                 rte_ixgbe_stats_strings[i].offset);
2735                 count++;
2736         }
2737
2738         /* RX Priority Stats */
2739         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2740                 for (i = 0; i < 8; i++) {
2741                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2742                                  "rx_priority%u_%s", i,
2743                                  rte_ixgbe_rxq_strings[stat].name);
2744                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2745                                         rte_ixgbe_rxq_strings[stat].offset +
2746                                         (sizeof(uint64_t) * i));
2747                         count++;
2748                 }
2749         }
2750
2751         /* TX Priority Stats */
2752         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2753                 for (i = 0; i < 8; i++) {
2754                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2755                                  "tx_priority%u_%s", i,
2756                                  rte_ixgbe_txq_strings[stat].name);
2757                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2758                                         rte_ixgbe_txq_strings[stat].offset +
2759                                         (sizeof(uint64_t) * i));
2760                         count++;
2761                 }
2762         }
2763
2764         return count;
2765 }
2766
2767 static void
2768 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2769 {
2770         struct ixgbe_hw_stats *stats =
2771                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2772
2773         unsigned count = ixgbe_xstats_calc_num();
2774
2775         /* HW registers are cleared on read */
2776         ixgbe_dev_xstats_get(dev, NULL, count);
2777
2778         /* Reset software totals */
2779         memset(stats, 0, sizeof(*stats));
2780 }
2781
2782 static void
2783 ixgbevf_update_stats(struct rte_eth_dev *dev)
2784 {
2785         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2786         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2787                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2788
2789         /* Good Rx packet, include VF loopback */
2790         UPDATE_VF_STAT(IXGBE_VFGPRC,
2791             hw_stats->last_vfgprc, hw_stats->vfgprc);
2792
2793         /* Good Rx octets, include VF loopback */
2794         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2795             hw_stats->last_vfgorc, hw_stats->vfgorc);
2796
2797         /* Good Tx packet, include VF loopback */
2798         UPDATE_VF_STAT(IXGBE_VFGPTC,
2799             hw_stats->last_vfgptc, hw_stats->vfgptc);
2800
2801         /* Good Tx octets, include VF loopback */
2802         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2803             hw_stats->last_vfgotc, hw_stats->vfgotc);
2804
2805         /* Rx Multicst Packet */
2806         UPDATE_VF_STAT(IXGBE_VFMPRC,
2807             hw_stats->last_vfmprc, hw_stats->vfmprc);
2808 }
2809
2810 static int
2811 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2812                        unsigned n)
2813 {
2814         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2815                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2816         unsigned i;
2817
2818         if (n < IXGBEVF_NB_XSTATS)
2819                 return IXGBEVF_NB_XSTATS;
2820
2821         ixgbevf_update_stats(dev);
2822
2823         if (!xstats)
2824                 return 0;
2825
2826         /* Extended stats */
2827         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2828                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2829                          "%s", rte_ixgbevf_stats_strings[i].name);
2830                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2831                         rte_ixgbevf_stats_strings[i].offset);
2832         }
2833
2834         return IXGBEVF_NB_XSTATS;
2835 }
2836
2837 static void
2838 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2839 {
2840         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2841                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2842
2843         ixgbevf_update_stats(dev);
2844
2845         if (stats == NULL)
2846                 return;
2847
2848         stats->ipackets = hw_stats->vfgprc;
2849         stats->ibytes = hw_stats->vfgorc;
2850         stats->opackets = hw_stats->vfgptc;
2851         stats->obytes = hw_stats->vfgotc;
2852         stats->imcasts = hw_stats->vfmprc;
2853         /* stats->imcasts should be removed as imcasts is deprecated */
2854 }
2855
2856 static void
2857 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2858 {
2859         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2860                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2861
2862         /* Sync HW register to the last stats */
2863         ixgbevf_dev_stats_get(dev, NULL);
2864
2865         /* reset HW current stats*/
2866         hw_stats->vfgprc = 0;
2867         hw_stats->vfgorc = 0;
2868         hw_stats->vfgptc = 0;
2869         hw_stats->vfgotc = 0;
2870         hw_stats->vfmprc = 0;
2871
2872 }
2873
2874 static void
2875 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2876 {
2877         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2878         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2879
2880         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2881         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2882         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
2883                 /*
2884                  * When DCB/VT is off, maximum number of queues changes,
2885                  * except for 82598EB, which remains constant.
2886                  */
2887                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2888                                 hw->mac.type != ixgbe_mac_82598EB)
2889                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
2890         }
2891         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2892         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2893         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2894         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2895         dev_info->max_vfs = dev->pci_dev->max_vfs;
2896         if (hw->mac.type == ixgbe_mac_82598EB)
2897                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2898         else
2899                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2900         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2901         dev_info->rx_offload_capa =
2902                 DEV_RX_OFFLOAD_VLAN_STRIP |
2903                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2904                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2905                 DEV_RX_OFFLOAD_TCP_CKSUM;
2906
2907         /*
2908          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2909          * mode.
2910          */
2911         if ((hw->mac.type == ixgbe_mac_82599EB ||
2912              hw->mac.type == ixgbe_mac_X540) &&
2913             !RTE_ETH_DEV_SRIOV(dev).active)
2914                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2915
2916         if (hw->mac.type == ixgbe_mac_X550 ||
2917             hw->mac.type == ixgbe_mac_X550EM_x)
2918                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2919
2920         dev_info->tx_offload_capa =
2921                 DEV_TX_OFFLOAD_VLAN_INSERT |
2922                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2923                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2924                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2925                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2926                 DEV_TX_OFFLOAD_TCP_TSO;
2927
2928         if (hw->mac.type == ixgbe_mac_X550 ||
2929             hw->mac.type == ixgbe_mac_X550EM_x)
2930                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2931
2932         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2933                 .rx_thresh = {
2934                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2935                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2936                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2937                 },
2938                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2939                 .rx_drop_en = 0,
2940         };
2941
2942         dev_info->default_txconf = (struct rte_eth_txconf) {
2943                 .tx_thresh = {
2944                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2945                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2946                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2947                 },
2948                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2949                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2950                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2951                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2952         };
2953
2954         dev_info->rx_desc_lim = rx_desc_lim;
2955         dev_info->tx_desc_lim = tx_desc_lim;
2956
2957         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2958         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2959         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2960 }
2961
2962 static const uint32_t *
2963 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2964 {
2965         static const uint32_t ptypes[] = {
2966                 /* For non-vec functions,
2967                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
2968                  * for vec functions,
2969                  * refers to _recv_raw_pkts_vec().
2970                  */
2971                 RTE_PTYPE_L2_ETHER,
2972                 RTE_PTYPE_L3_IPV4,
2973                 RTE_PTYPE_L3_IPV4_EXT,
2974                 RTE_PTYPE_L3_IPV6,
2975                 RTE_PTYPE_L3_IPV6_EXT,
2976                 RTE_PTYPE_L4_SCTP,
2977                 RTE_PTYPE_L4_TCP,
2978                 RTE_PTYPE_L4_UDP,
2979                 RTE_PTYPE_TUNNEL_IP,
2980                 RTE_PTYPE_INNER_L3_IPV6,
2981                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2982                 RTE_PTYPE_INNER_L4_TCP,
2983                 RTE_PTYPE_INNER_L4_UDP,
2984                 RTE_PTYPE_UNKNOWN
2985         };
2986
2987         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
2988             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
2989             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
2990             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
2991                 return ptypes;
2992         return NULL;
2993 }
2994
2995 static void
2996 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2997                      struct rte_eth_dev_info *dev_info)
2998 {
2999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3000
3001         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3002         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3003         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3004         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3005         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3006         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3007         dev_info->max_vfs = dev->pci_dev->max_vfs;
3008         if (hw->mac.type == ixgbe_mac_82598EB)
3009                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3010         else
3011                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3012         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3013                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3014                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3015                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3016         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3017                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3018                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3019                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3020                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3021                                 DEV_TX_OFFLOAD_TCP_TSO;
3022
3023         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3024                 .rx_thresh = {
3025                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3026                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3027                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3028                 },
3029                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3030                 .rx_drop_en = 0,
3031         };
3032
3033         dev_info->default_txconf = (struct rte_eth_txconf) {
3034                 .tx_thresh = {
3035                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3036                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3037                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3038                 },
3039                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3040                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3041                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3042                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3043         };
3044
3045         dev_info->rx_desc_lim = rx_desc_lim;
3046         dev_info->tx_desc_lim = tx_desc_lim;
3047 }
3048
3049 /* return 0 means link status changed, -1 means not changed */
3050 static int
3051 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3052 {
3053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3054         struct rte_eth_link link, old;
3055         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3056         int link_up;
3057         int diag;
3058
3059         link.link_status = 0;
3060         link.link_speed = 0;
3061         link.link_duplex = 0;
3062         memset(&old, 0, sizeof(old));
3063         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3064
3065         hw->mac.get_link_status = true;
3066
3067         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3068         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3069                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3070         else
3071                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3072
3073         if (diag != 0) {
3074                 link.link_speed = ETH_LINK_SPEED_100;
3075                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3076                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3077                 if (link.link_status == old.link_status)
3078                         return -1;
3079                 return 0;
3080         }
3081
3082         if (link_up == 0) {
3083                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3084                 if (link.link_status == old.link_status)
3085                         return -1;
3086                 return 0;
3087         }
3088         link.link_status = 1;
3089         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3090
3091         switch (link_speed) {
3092         default:
3093         case IXGBE_LINK_SPEED_UNKNOWN:
3094                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3095                 link.link_speed = ETH_LINK_SPEED_100;
3096                 break;
3097
3098         case IXGBE_LINK_SPEED_100_FULL:
3099                 link.link_speed = ETH_LINK_SPEED_100;
3100                 break;
3101
3102         case IXGBE_LINK_SPEED_1GB_FULL:
3103                 link.link_speed = ETH_LINK_SPEED_1000;
3104                 break;
3105
3106         case IXGBE_LINK_SPEED_10GB_FULL:
3107                 link.link_speed = ETH_LINK_SPEED_10000;
3108                 break;
3109         }
3110         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3111
3112         if (link.link_status == old.link_status)
3113                 return -1;
3114
3115         return 0;
3116 }
3117
3118 static void
3119 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3120 {
3121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3122         uint32_t fctrl;
3123
3124         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3125         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3126         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3127 }
3128
3129 static void
3130 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3131 {
3132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3133         uint32_t fctrl;
3134
3135         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3136         fctrl &= (~IXGBE_FCTRL_UPE);
3137         if (dev->data->all_multicast == 1)
3138                 fctrl |= IXGBE_FCTRL_MPE;
3139         else
3140                 fctrl &= (~IXGBE_FCTRL_MPE);
3141         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3142 }
3143
3144 static void
3145 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3146 {
3147         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3148         uint32_t fctrl;
3149
3150         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3151         fctrl |= IXGBE_FCTRL_MPE;
3152         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3153 }
3154
3155 static void
3156 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3157 {
3158         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3159         uint32_t fctrl;
3160
3161         if (dev->data->promiscuous == 1)
3162                 return; /* must remain in all_multicast mode */
3163
3164         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3165         fctrl &= (~IXGBE_FCTRL_MPE);
3166         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3167 }
3168
3169 /**
3170  * It clears the interrupt causes and enables the interrupt.
3171  * It will be called once only during nic initialized.
3172  *
3173  * @param dev
3174  *  Pointer to struct rte_eth_dev.
3175  *
3176  * @return
3177  *  - On success, zero.
3178  *  - On failure, a negative value.
3179  */
3180 static int
3181 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3182 {
3183         struct ixgbe_interrupt *intr =
3184                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3185
3186         ixgbe_dev_link_status_print(dev);
3187         intr->mask |= IXGBE_EICR_LSC;
3188
3189         return 0;
3190 }
3191
3192 /**
3193  * It clears the interrupt causes and enables the interrupt.
3194  * It will be called once only during nic initialized.
3195  *
3196  * @param dev
3197  *  Pointer to struct rte_eth_dev.
3198  *
3199  * @return
3200  *  - On success, zero.
3201  *  - On failure, a negative value.
3202  */
3203 static int
3204 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3205 {
3206         struct ixgbe_interrupt *intr =
3207                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3208
3209         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3210
3211         return 0;
3212 }
3213
3214 /*
3215  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3216  *
3217  * @param dev
3218  *  Pointer to struct rte_eth_dev.
3219  *
3220  * @return
3221  *  - On success, zero.
3222  *  - On failure, a negative value.
3223  */
3224 static int
3225 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3226 {
3227         uint32_t eicr;
3228         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3229         struct ixgbe_interrupt *intr =
3230                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3231
3232         /* clear all cause mask */
3233         ixgbe_disable_intr(hw);
3234
3235         /* read-on-clear nic registers here */
3236         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3237         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3238
3239         intr->flags = 0;
3240
3241         /* set flag for async link update */
3242         if (eicr & IXGBE_EICR_LSC)
3243                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3244
3245         if (eicr & IXGBE_EICR_MAILBOX)
3246                 intr->flags |= IXGBE_FLAG_MAILBOX;
3247
3248         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3249             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3250             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3251                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3252
3253         return 0;
3254 }
3255
3256 /**
3257  * It gets and then prints the link status.
3258  *
3259  * @param dev
3260  *  Pointer to struct rte_eth_dev.
3261  *
3262  * @return
3263  *  - On success, zero.
3264  *  - On failure, a negative value.
3265  */
3266 static void
3267 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3268 {
3269         struct rte_eth_link link;
3270
3271         memset(&link, 0, sizeof(link));
3272         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3273         if (link.link_status) {
3274                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3275                                         (int)(dev->data->port_id),
3276                                         (unsigned)link.link_speed,
3277                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3278                                         "full-duplex" : "half-duplex");
3279         } else {
3280                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3281                                 (int)(dev->data->port_id));
3282         }
3283         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3284                                 dev->pci_dev->addr.domain,
3285                                 dev->pci_dev->addr.bus,
3286                                 dev->pci_dev->addr.devid,
3287                                 dev->pci_dev->addr.function);
3288 }
3289
3290 /*
3291  * It executes link_update after knowing an interrupt occurred.
3292  *
3293  * @param dev
3294  *  Pointer to struct rte_eth_dev.
3295  *
3296  * @return
3297  *  - On success, zero.
3298  *  - On failure, a negative value.
3299  */
3300 static int
3301 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3302 {
3303         struct ixgbe_interrupt *intr =
3304                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3305         int64_t timeout;
3306         struct rte_eth_link link;
3307         int intr_enable_delay = false;
3308         struct ixgbe_hw *hw =
3309                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3310
3311         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3312
3313         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3314                 ixgbe_pf_mbx_process(dev);
3315                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3316         }
3317
3318         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3319                 ixgbe_handle_lasi(hw);
3320                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3321         }
3322
3323         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3324                 /* get the link status before link update, for predicting later */
3325                 memset(&link, 0, sizeof(link));
3326                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3327
3328                 ixgbe_dev_link_update(dev, 0);
3329
3330                 /* likely to up */
3331                 if (!link.link_status)
3332                         /* handle it 1 sec later, wait it being stable */
3333                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3334                 /* likely to down */
3335                 else
3336                         /* handle it 4 sec later, wait it being stable */
3337                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3338
3339                 ixgbe_dev_link_status_print(dev);
3340
3341                 intr_enable_delay = true;
3342         }
3343
3344         if (intr_enable_delay) {
3345                 if (rte_eal_alarm_set(timeout * 1000,
3346                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3347                         PMD_DRV_LOG(ERR, "Error setting alarm");
3348         } else {
3349                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3350                 ixgbe_enable_intr(dev);
3351                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3352         }
3353
3354
3355         return 0;
3356 }
3357
3358 /**
3359  * Interrupt handler which shall be registered for alarm callback for delayed
3360  * handling specific interrupt to wait for the stable nic state. As the
3361  * NIC interrupt state is not stable for ixgbe after link is just down,
3362  * it needs to wait 4 seconds to get the stable status.
3363  *
3364  * @param handle
3365  *  Pointer to interrupt handle.
3366  * @param param
3367  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3368  *
3369  * @return
3370  *  void
3371  */
3372 static void
3373 ixgbe_dev_interrupt_delayed_handler(void *param)
3374 {
3375         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3376         struct ixgbe_interrupt *intr =
3377                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3378         struct ixgbe_hw *hw =
3379                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3380         uint32_t eicr;
3381
3382         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3383         if (eicr & IXGBE_EICR_MAILBOX)
3384                 ixgbe_pf_mbx_process(dev);
3385
3386         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3387                 ixgbe_handle_lasi(hw);
3388                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3389         }
3390
3391         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3392                 ixgbe_dev_link_update(dev, 0);
3393                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3394                 ixgbe_dev_link_status_print(dev);
3395                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3396         }
3397
3398         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3399         ixgbe_enable_intr(dev);
3400         rte_intr_enable(&(dev->pci_dev->intr_handle));
3401 }
3402
3403 /**
3404  * Interrupt handler triggered by NIC  for handling
3405  * specific interrupt.
3406  *
3407  * @param handle
3408  *  Pointer to interrupt handle.
3409  * @param param
3410  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3411  *
3412  * @return
3413  *  void
3414  */
3415 static void
3416 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3417                             void *param)
3418 {
3419         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3420
3421         ixgbe_dev_interrupt_get_status(dev);
3422         ixgbe_dev_interrupt_action(dev);
3423 }
3424
3425 static int
3426 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3427 {
3428         struct ixgbe_hw *hw;
3429
3430         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3431         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3432 }
3433
3434 static int
3435 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3436 {
3437         struct ixgbe_hw *hw;
3438
3439         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3440         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3441 }
3442
3443 static int
3444 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3445 {
3446         struct ixgbe_hw *hw;
3447         uint32_t mflcn_reg;
3448         uint32_t fccfg_reg;
3449         int rx_pause;
3450         int tx_pause;
3451
3452         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3453
3454         fc_conf->pause_time = hw->fc.pause_time;
3455         fc_conf->high_water = hw->fc.high_water[0];
3456         fc_conf->low_water = hw->fc.low_water[0];
3457         fc_conf->send_xon = hw->fc.send_xon;
3458         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3459
3460         /*
3461          * Return rx_pause status according to actual setting of
3462          * MFLCN register.
3463          */
3464         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3465         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3466                 rx_pause = 1;
3467         else
3468                 rx_pause = 0;
3469
3470         /*
3471          * Return tx_pause status according to actual setting of
3472          * FCCFG register.
3473          */
3474         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3475         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3476                 tx_pause = 1;
3477         else
3478                 tx_pause = 0;
3479
3480         if (rx_pause && tx_pause)
3481                 fc_conf->mode = RTE_FC_FULL;
3482         else if (rx_pause)
3483                 fc_conf->mode = RTE_FC_RX_PAUSE;
3484         else if (tx_pause)
3485                 fc_conf->mode = RTE_FC_TX_PAUSE;
3486         else
3487                 fc_conf->mode = RTE_FC_NONE;
3488
3489         return 0;
3490 }
3491
3492 static int
3493 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3494 {
3495         struct ixgbe_hw *hw;
3496         int err;
3497         uint32_t rx_buf_size;
3498         uint32_t max_high_water;
3499         uint32_t mflcn;
3500         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3501                 ixgbe_fc_none,
3502                 ixgbe_fc_rx_pause,
3503                 ixgbe_fc_tx_pause,
3504                 ixgbe_fc_full
3505         };
3506
3507         PMD_INIT_FUNC_TRACE();
3508
3509         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3511         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3512
3513         /*
3514          * At least reserve one Ethernet frame for watermark
3515          * high_water/low_water in kilo bytes for ixgbe
3516          */
3517         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3518         if ((fc_conf->high_water > max_high_water) ||
3519                 (fc_conf->high_water < fc_conf->low_water)) {
3520                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3521                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3522                 return -EINVAL;
3523         }
3524
3525         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3526         hw->fc.pause_time     = fc_conf->pause_time;
3527         hw->fc.high_water[0]  = fc_conf->high_water;
3528         hw->fc.low_water[0]   = fc_conf->low_water;
3529         hw->fc.send_xon       = fc_conf->send_xon;
3530         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3531
3532         err = ixgbe_fc_enable(hw);
3533
3534         /* Not negotiated is not an error case */
3535         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3536
3537                 /* check if we want to forward MAC frames - driver doesn't have native
3538                  * capability to do that, so we'll write the registers ourselves */
3539
3540                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3541
3542                 /* set or clear MFLCN.PMCF bit depending on configuration */
3543                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3544                         mflcn |= IXGBE_MFLCN_PMCF;
3545                 else
3546                         mflcn &= ~IXGBE_MFLCN_PMCF;
3547
3548                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3549                 IXGBE_WRITE_FLUSH(hw);
3550
3551                 return 0;
3552         }
3553
3554         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3555         return -EIO;
3556 }
3557
3558 /**
3559  *  ixgbe_pfc_enable_generic - Enable flow control
3560  *  @hw: pointer to hardware structure
3561  *  @tc_num: traffic class number
3562  *  Enable flow control according to the current settings.
3563  */
3564 static int
3565 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3566 {
3567         int ret_val = 0;
3568         uint32_t mflcn_reg, fccfg_reg;
3569         uint32_t reg;
3570         uint32_t fcrtl, fcrth;
3571         uint8_t i;
3572         uint8_t nb_rx_en;
3573
3574         /* Validate the water mark configuration */
3575         if (!hw->fc.pause_time) {
3576                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3577                 goto out;
3578         }
3579
3580         /* Low water mark of zero causes XOFF floods */
3581         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3582                  /* High/Low water can not be 0 */
3583                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3584                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3585                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3586                         goto out;
3587                 }
3588
3589                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3590                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3591                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3592                         goto out;
3593                 }
3594         }
3595         /* Negotiate the fc mode to use */
3596         ixgbe_fc_autoneg(hw);
3597
3598         /* Disable any previous flow control settings */
3599         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3600         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3601
3602         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3603         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3604
3605         switch (hw->fc.current_mode) {
3606         case ixgbe_fc_none:
3607                 /*
3608                  * If the count of enabled RX Priority Flow control >1,
3609                  * and the TX pause can not be disabled
3610                  */
3611                 nb_rx_en = 0;
3612                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3613                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3614                         if (reg & IXGBE_FCRTH_FCEN)
3615                                 nb_rx_en++;
3616                 }
3617                 if (nb_rx_en > 1)
3618                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3619                 break;
3620         case ixgbe_fc_rx_pause:
3621                 /*
3622                  * Rx Flow control is enabled and Tx Flow control is
3623                  * disabled by software override. Since there really
3624                  * isn't a way to advertise that we are capable of RX
3625                  * Pause ONLY, we will advertise that we support both
3626                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3627                  * disable the adapter's ability to send PAUSE frames.
3628                  */
3629                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3630                 /*
3631                  * If the count of enabled RX Priority Flow control >1,
3632                  * and the TX pause can not be disabled
3633                  */
3634                 nb_rx_en = 0;
3635                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3636                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3637                         if (reg & IXGBE_FCRTH_FCEN)
3638                                 nb_rx_en++;
3639                 }
3640                 if (nb_rx_en > 1)
3641                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3642                 break;
3643         case ixgbe_fc_tx_pause:
3644                 /*
3645                  * Tx Flow control is enabled, and Rx Flow control is
3646                  * disabled by software override.
3647                  */
3648                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3649                 break;
3650         case ixgbe_fc_full:
3651                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3652                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3653                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3654                 break;
3655         default:
3656                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3657                 ret_val = IXGBE_ERR_CONFIG;
3658                 goto out;
3659                 break;
3660         }
3661
3662         /* Set 802.3x based flow control settings. */
3663         mflcn_reg |= IXGBE_MFLCN_DPF;
3664         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3665         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3666
3667         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3668         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3669                 hw->fc.high_water[tc_num]) {
3670                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3671                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3672                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3673         } else {
3674                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3675                 /*
3676                  * In order to prevent Tx hangs when the internal Tx
3677                  * switch is enabled we must set the high water mark
3678                  * to the maximum FCRTH value.  This allows the Tx
3679                  * switch to function even under heavy Rx workloads.
3680                  */
3681                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3682         }
3683         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3684
3685         /* Configure pause time (2 TCs per register) */
3686         reg = hw->fc.pause_time * 0x00010001;
3687         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3688                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3689
3690         /* Configure flow control refresh threshold value */
3691         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3692
3693 out:
3694         return ret_val;
3695 }
3696
3697 static int
3698 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3699 {
3700         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3701         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3702
3703         if (hw->mac.type != ixgbe_mac_82598EB) {
3704                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3705         }
3706         return ret_val;
3707 }
3708
3709 static int
3710 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3711 {
3712         int err;
3713         uint32_t rx_buf_size;
3714         uint32_t max_high_water;
3715         uint8_t tc_num;
3716         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3717         struct ixgbe_hw *hw =
3718                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3719         struct ixgbe_dcb_config *dcb_config =
3720                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3721
3722         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3723                 ixgbe_fc_none,
3724                 ixgbe_fc_rx_pause,
3725                 ixgbe_fc_tx_pause,
3726                 ixgbe_fc_full
3727         };
3728
3729         PMD_INIT_FUNC_TRACE();
3730
3731         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3732         tc_num = map[pfc_conf->priority];
3733         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3734         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3735         /*
3736          * At least reserve one Ethernet frame for watermark
3737          * high_water/low_water in kilo bytes for ixgbe
3738          */
3739         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3740         if ((pfc_conf->fc.high_water > max_high_water) ||
3741             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3742                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3743                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3744                 return -EINVAL;
3745         }
3746
3747         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3748         hw->fc.pause_time = pfc_conf->fc.pause_time;
3749         hw->fc.send_xon = pfc_conf->fc.send_xon;
3750         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3751         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3752
3753         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3754
3755         /* Not negotiated is not an error case */
3756         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3757                 return 0;
3758
3759         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3760         return -EIO;
3761 }
3762
3763 static int
3764 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3765                           struct rte_eth_rss_reta_entry64 *reta_conf,
3766                           uint16_t reta_size)
3767 {
3768         uint16_t i, sp_reta_size;
3769         uint8_t j, mask;
3770         uint32_t reta, r;
3771         uint16_t idx, shift;
3772         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3773         uint32_t reta_reg;
3774
3775         PMD_INIT_FUNC_TRACE();
3776
3777         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3778                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3779                         "NIC.");
3780                 return -ENOTSUP;
3781         }
3782
3783         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3784         if (reta_size != sp_reta_size) {
3785                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3786                         "(%d) doesn't match the number hardware can supported "
3787                         "(%d)\n", reta_size, sp_reta_size);
3788                 return -EINVAL;
3789         }
3790
3791         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3792                 idx = i / RTE_RETA_GROUP_SIZE;
3793                 shift = i % RTE_RETA_GROUP_SIZE;
3794                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3795                                                 IXGBE_4_BIT_MASK);
3796                 if (!mask)
3797                         continue;
3798                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3799                 if (mask == IXGBE_4_BIT_MASK)
3800                         r = 0;
3801                 else
3802                         r = IXGBE_READ_REG(hw, reta_reg);
3803                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3804                         if (mask & (0x1 << j))
3805                                 reta |= reta_conf[idx].reta[shift + j] <<
3806                                                         (CHAR_BIT * j);
3807                         else
3808                                 reta |= r & (IXGBE_8_BIT_MASK <<
3809                                                 (CHAR_BIT * j));
3810                 }
3811                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3812         }
3813
3814         return 0;
3815 }
3816
3817 static int
3818 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3819                          struct rte_eth_rss_reta_entry64 *reta_conf,
3820                          uint16_t reta_size)
3821 {
3822         uint16_t i, sp_reta_size;
3823         uint8_t j, mask;
3824         uint32_t reta;
3825         uint16_t idx, shift;
3826         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3827         uint32_t reta_reg;
3828
3829         PMD_INIT_FUNC_TRACE();
3830         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3831         if (reta_size != sp_reta_size) {
3832                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3833                         "(%d) doesn't match the number hardware can supported "
3834                         "(%d)\n", reta_size, sp_reta_size);
3835                 return -EINVAL;
3836         }
3837
3838         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3839                 idx = i / RTE_RETA_GROUP_SIZE;
3840                 shift = i % RTE_RETA_GROUP_SIZE;
3841                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3842                                                 IXGBE_4_BIT_MASK);
3843                 if (!mask)
3844                         continue;
3845
3846                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3847                 reta = IXGBE_READ_REG(hw, reta_reg);
3848                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3849                         if (mask & (0x1 << j))
3850                                 reta_conf[idx].reta[shift + j] =
3851                                         ((reta >> (CHAR_BIT * j)) &
3852                                                 IXGBE_8_BIT_MASK);
3853                 }
3854         }
3855
3856         return 0;
3857 }
3858
3859 static void
3860 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3861                                 uint32_t index, uint32_t pool)
3862 {
3863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3864         uint32_t enable_addr = 1;
3865
3866         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3867 }
3868
3869 static void
3870 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3871 {
3872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3873
3874         ixgbe_clear_rar(hw, index);
3875 }
3876
3877 static void
3878 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3879 {
3880         ixgbe_remove_rar(dev, 0);
3881
3882         ixgbe_add_rar(dev, addr, 0, 0);
3883 }
3884
3885 static int
3886 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3887 {
3888         uint32_t hlreg0;
3889         uint32_t maxfrs;
3890         struct ixgbe_hw *hw;
3891         struct rte_eth_dev_info dev_info;
3892         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3893
3894         ixgbe_dev_info_get(dev, &dev_info);
3895
3896         /* check that mtu is within the allowed range */
3897         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3898                 return -EINVAL;
3899
3900         /* refuse mtu that requires the support of scattered packets when this
3901          * feature has not been enabled before. */
3902         if (!dev->data->scattered_rx &&
3903             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3904              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3905                 return -EINVAL;
3906
3907         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3908         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3909
3910         /* switch to jumbo mode if needed */
3911         if (frame_size > ETHER_MAX_LEN) {
3912                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3913                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3914         } else {
3915                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3916                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3917         }
3918         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3919
3920         /* update max frame size */
3921         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3922
3923         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3924         maxfrs &= 0x0000FFFF;
3925         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3926         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3927
3928         return 0;
3929 }
3930
3931 /*
3932  * Virtual Function operations
3933  */
3934 static void
3935 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3936 {
3937         PMD_INIT_FUNC_TRACE();
3938
3939         /* Clear interrupt mask to stop from interrupts being generated */
3940         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3941
3942         IXGBE_WRITE_FLUSH(hw);
3943 }
3944
3945 static void
3946 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3947 {
3948         PMD_INIT_FUNC_TRACE();
3949
3950         /* VF enable interrupt autoclean */
3951         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3952         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3953         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3954
3955         IXGBE_WRITE_FLUSH(hw);
3956 }
3957
3958 static int
3959 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3960 {
3961         struct rte_eth_conf* conf = &dev->data->dev_conf;
3962         struct ixgbe_adapter *adapter =
3963                         (struct ixgbe_adapter *)dev->data->dev_private;
3964
3965         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3966                      dev->data->port_id);
3967
3968         /*
3969          * VF has no ability to enable/disable HW CRC
3970          * Keep the persistent behavior the same as Host PF
3971          */
3972 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3973         if (!conf->rxmode.hw_strip_crc) {
3974                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3975                 conf->rxmode.hw_strip_crc = 1;
3976         }
3977 #else
3978         if (conf->rxmode.hw_strip_crc) {
3979                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3980                 conf->rxmode.hw_strip_crc = 0;
3981         }
3982 #endif
3983
3984         /*
3985          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3986          * allocation or vector Rx preconditions we will reset it.
3987          */
3988         adapter->rx_bulk_alloc_allowed = true;
3989         adapter->rx_vec_allowed = true;
3990
3991         return 0;
3992 }
3993
3994 static int
3995 ixgbevf_dev_start(struct rte_eth_dev *dev)
3996 {
3997         struct ixgbe_hw *hw =
3998                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3999         uint32_t intr_vector = 0;
4000         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4001
4002         int err, mask = 0;
4003
4004         PMD_INIT_FUNC_TRACE();
4005
4006         hw->mac.ops.reset_hw(hw);
4007         hw->mac.get_link_status = true;
4008
4009         /* negotiate mailbox API version to use with the PF. */
4010         ixgbevf_negotiate_api(hw);
4011
4012         ixgbevf_dev_tx_init(dev);
4013
4014         /* This can fail when allocating mbufs for descriptor rings */
4015         err = ixgbevf_dev_rx_init(dev);
4016         if (err) {
4017                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4018                 ixgbe_dev_clear_queues(dev);
4019                 return err;
4020         }
4021
4022         /* Set vfta */
4023         ixgbevf_set_vfta_all(dev,1);
4024
4025         /* Set HW strip */
4026         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
4027                 ETH_VLAN_EXTEND_MASK;
4028         ixgbevf_vlan_offload_set(dev, mask);
4029
4030         ixgbevf_dev_rxtx_start(dev);
4031
4032         /* check and configure queue intr-vector mapping */
4033         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4034                 intr_vector = dev->data->nb_rx_queues;
4035                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4036                         return -1;
4037         }
4038
4039         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4040                 intr_handle->intr_vec =
4041                         rte_zmalloc("intr_vec",
4042                                     dev->data->nb_rx_queues * sizeof(int), 0);
4043                 if (intr_handle->intr_vec == NULL) {
4044                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4045                                      " intr_vec\n", dev->data->nb_rx_queues);
4046                         return -ENOMEM;
4047                 }
4048         }
4049         ixgbevf_configure_msix(dev);
4050
4051         rte_intr_enable(intr_handle);
4052
4053         /* Re-enable interrupt for VF */
4054         ixgbevf_intr_enable(hw);
4055
4056         return 0;
4057 }
4058
4059 static void
4060 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4061 {
4062         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4063         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4064
4065         PMD_INIT_FUNC_TRACE();
4066
4067         hw->adapter_stopped = 1;
4068         ixgbe_stop_adapter(hw);
4069
4070         /*
4071           * Clear what we set, but we still keep shadow_vfta to
4072           * restore after device starts
4073           */
4074         ixgbevf_set_vfta_all(dev,0);
4075
4076         /* Clear stored conf */
4077         dev->data->scattered_rx = 0;
4078
4079         ixgbe_dev_clear_queues(dev);
4080
4081         /* Clean datapath event and queue/vec mapping */
4082         rte_intr_efd_disable(intr_handle);
4083         if (intr_handle->intr_vec != NULL) {
4084                 rte_free(intr_handle->intr_vec);
4085                 intr_handle->intr_vec = NULL;
4086         }
4087 }
4088
4089 static void
4090 ixgbevf_dev_close(struct rte_eth_dev *dev)
4091 {
4092         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4093
4094         PMD_INIT_FUNC_TRACE();
4095
4096         ixgbe_reset_hw(hw);
4097
4098         ixgbevf_dev_stop(dev);
4099
4100         ixgbe_dev_free_queues(dev);
4101
4102         /**
4103          * Remove the VF MAC address ro ensure
4104          * that the VF traffic goes to the PF
4105          * after stop, close and detach of the VF
4106          **/
4107         ixgbevf_remove_mac_addr(dev, 0);
4108 }
4109
4110 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4111 {
4112         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4113         struct ixgbe_vfta * shadow_vfta =
4114                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4115         int i = 0, j = 0, vfta = 0, mask = 1;
4116
4117         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4118                 vfta = shadow_vfta->vfta[i];
4119                 if (vfta) {
4120                         mask = 1;
4121                         for (j = 0; j < 32; j++){
4122                                 if (vfta & mask)
4123                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4124                                 mask<<=1;
4125                         }
4126                 }
4127         }
4128
4129 }
4130
4131 static int
4132 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4133 {
4134         struct ixgbe_hw *hw =
4135                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4136         struct ixgbe_vfta * shadow_vfta =
4137                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4138         uint32_t vid_idx = 0;
4139         uint32_t vid_bit = 0;
4140         int ret = 0;
4141
4142         PMD_INIT_FUNC_TRACE();
4143
4144         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4145         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4146         if (ret) {
4147                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4148                 return ret;
4149         }
4150         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4151         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4152
4153         /* Save what we set and retore it after device reset */
4154         if (on)
4155                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4156         else
4157                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4158
4159         return 0;
4160 }
4161
4162 static void
4163 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4164 {
4165         struct ixgbe_hw *hw =
4166                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4167         uint32_t ctrl;
4168
4169         PMD_INIT_FUNC_TRACE();
4170
4171         if (queue >= hw->mac.max_rx_queues)
4172                 return;
4173
4174         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4175         if (on)
4176                 ctrl |= IXGBE_RXDCTL_VME;
4177         else
4178                 ctrl &= ~IXGBE_RXDCTL_VME;
4179         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4180
4181         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4182 }
4183
4184 static void
4185 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4186 {
4187         struct ixgbe_hw *hw =
4188                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4189         uint16_t i;
4190         int on = 0;
4191
4192         /* VF function only support hw strip feature, others are not support */
4193         if (mask & ETH_VLAN_STRIP_MASK) {
4194                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4195
4196                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4197                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4198         }
4199 }
4200
4201 static int
4202 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4203 {
4204         uint32_t reg_val;
4205
4206         /* we only need to do this if VMDq is enabled */
4207         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4208         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4209                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4210                 return -1;
4211         }
4212
4213         return 0;
4214 }
4215
4216 static uint32_t
4217 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4218 {
4219         uint32_t vector = 0;
4220         switch (hw->mac.mc_filter_type) {
4221         case 0:   /* use bits [47:36] of the address */
4222                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4223                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4224                 break;
4225         case 1:   /* use bits [46:35] of the address */
4226                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4227                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4228                 break;
4229         case 2:   /* use bits [45:34] of the address */
4230                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4231                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4232                 break;
4233         case 3:   /* use bits [43:32] of the address */
4234                 vector = ((uc_addr->addr_bytes[4]) |
4235                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4236                 break;
4237         default:  /* Invalid mc_filter_type */
4238                 break;
4239         }
4240
4241         /* vector can only be 12-bits or boundary will be exceeded */
4242         vector &= 0xFFF;
4243         return vector;
4244 }
4245
4246 static int
4247 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4248                                uint8_t on)
4249 {
4250         uint32_t vector;
4251         uint32_t uta_idx;
4252         uint32_t reg_val;
4253         uint32_t uta_shift;
4254         uint32_t rc;
4255         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4256         const uint32_t ixgbe_uta_bit_shift = 5;
4257         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4258         const uint32_t bit1 = 0x1;
4259
4260         struct ixgbe_hw *hw =
4261                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4262         struct ixgbe_uta_info *uta_info =
4263                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4264
4265         /* The UTA table only exists on 82599 hardware and newer */
4266         if (hw->mac.type < ixgbe_mac_82599EB)
4267                 return -ENOTSUP;
4268
4269         vector = ixgbe_uta_vector(hw,mac_addr);
4270         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4271         uta_shift = vector & ixgbe_uta_bit_mask;
4272
4273         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4274         if (rc == on)
4275                 return 0;
4276
4277         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4278         if (on) {
4279                 uta_info->uta_in_use++;
4280                 reg_val |= (bit1 << uta_shift);
4281                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4282         } else {
4283                 uta_info->uta_in_use--;
4284                 reg_val &= ~(bit1 << uta_shift);
4285                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4286         }
4287
4288         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4289
4290         if (uta_info->uta_in_use > 0)
4291                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4292                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4293         else
4294                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4295
4296         return 0;
4297 }
4298
4299 static int
4300 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4301 {
4302         int i;
4303         struct ixgbe_hw *hw =
4304                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4305         struct ixgbe_uta_info *uta_info =
4306                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4307
4308         /* The UTA table only exists on 82599 hardware and newer */
4309         if (hw->mac.type < ixgbe_mac_82599EB)
4310                 return -ENOTSUP;
4311
4312         if (on) {
4313                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4314                         uta_info->uta_shadow[i] = ~0;
4315                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4316                 }
4317         } else {
4318                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4319                         uta_info->uta_shadow[i] = 0;
4320                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4321                 }
4322         }
4323         return 0;
4324
4325 }
4326
4327 uint32_t
4328 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4329 {
4330         uint32_t new_val = orig_val;
4331
4332         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4333                 new_val |= IXGBE_VMOLR_AUPE;
4334         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4335                 new_val |= IXGBE_VMOLR_ROMPE;
4336         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4337                 new_val |= IXGBE_VMOLR_ROPE;
4338         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4339                 new_val |= IXGBE_VMOLR_BAM;
4340         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4341                 new_val |= IXGBE_VMOLR_MPE;
4342
4343         return new_val;
4344 }
4345
4346 static int
4347 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4348                                uint16_t rx_mask, uint8_t on)
4349 {
4350         int val = 0;
4351
4352         struct ixgbe_hw *hw =
4353                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4354         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4355
4356         if (hw->mac.type == ixgbe_mac_82598EB) {
4357                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4358                              " on 82599 hardware and newer");
4359                 return -ENOTSUP;
4360         }
4361         if (ixgbe_vmdq_mode_check(hw) < 0)
4362                 return -ENOTSUP;
4363
4364         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4365
4366         if (on)
4367                 vmolr |= val;
4368         else
4369                 vmolr &= ~val;
4370
4371         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4372
4373         return 0;
4374 }
4375
4376 static int
4377 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4378 {
4379         uint32_t reg,addr;
4380         uint32_t val;
4381         const uint8_t bit1 = 0x1;
4382
4383         struct ixgbe_hw *hw =
4384                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4385
4386         if (ixgbe_vmdq_mode_check(hw) < 0)
4387                 return -ENOTSUP;
4388
4389         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4390         reg = IXGBE_READ_REG(hw, addr);
4391         val = bit1 << pool;
4392
4393         if (on)
4394                 reg |= val;
4395         else
4396                 reg &= ~val;
4397
4398         IXGBE_WRITE_REG(hw, addr,reg);
4399
4400         return 0;
4401 }
4402
4403 static int
4404 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4405 {
4406         uint32_t reg,addr;
4407         uint32_t val;
4408         const uint8_t bit1 = 0x1;
4409
4410         struct ixgbe_hw *hw =
4411                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4412
4413         if (ixgbe_vmdq_mode_check(hw) < 0)
4414                 return -ENOTSUP;
4415
4416         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4417         reg = IXGBE_READ_REG(hw, addr);
4418         val = bit1 << pool;
4419
4420         if (on)
4421                 reg |= val;
4422         else
4423                 reg &= ~val;
4424
4425         IXGBE_WRITE_REG(hw, addr,reg);
4426
4427         return 0;
4428 }
4429
4430 static int
4431 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4432                         uint64_t pool_mask, uint8_t vlan_on)
4433 {
4434         int ret = 0;
4435         uint16_t pool_idx;
4436         struct ixgbe_hw *hw =
4437                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4438
4439         if (ixgbe_vmdq_mode_check(hw) < 0)
4440                 return -ENOTSUP;
4441         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4442                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4443                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4444                         if (ret < 0)
4445                                 return ret;
4446         }
4447
4448         return ret;
4449 }
4450
4451 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4452 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4453 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4454 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4455 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4456         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4457         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4458
4459 static int
4460 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4461                         struct rte_eth_mirror_conf *mirror_conf,
4462                         uint8_t rule_id, uint8_t on)
4463 {
4464         uint32_t mr_ctl,vlvf;
4465         uint32_t mp_lsb = 0;
4466         uint32_t mv_msb = 0;
4467         uint32_t mv_lsb = 0;
4468         uint32_t mp_msb = 0;
4469         uint8_t i = 0;
4470         int reg_index = 0;
4471         uint64_t vlan_mask = 0;
4472
4473         const uint8_t pool_mask_offset = 32;
4474         const uint8_t vlan_mask_offset = 32;
4475         const uint8_t dst_pool_offset = 8;
4476         const uint8_t rule_mr_offset  = 4;
4477         const uint8_t mirror_rule_mask= 0x0F;
4478
4479         struct ixgbe_mirror_info *mr_info =
4480                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4481         struct ixgbe_hw *hw =
4482                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4483         uint8_t mirror_type = 0;
4484
4485         if (ixgbe_vmdq_mode_check(hw) < 0)
4486                 return -ENOTSUP;
4487
4488         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4489                 return -EINVAL;
4490
4491         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4492                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4493                         mirror_conf->rule_type);
4494                 return -EINVAL;
4495         }
4496
4497         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4498                 mirror_type |= IXGBE_MRCTL_VLME;
4499                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4500                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4501                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4502                                 /* search vlan id related pool vlan filter index */
4503                                 reg_index = ixgbe_find_vlvf_slot(hw,
4504                                                 mirror_conf->vlan.vlan_id[i]);
4505                                 if (reg_index < 0)
4506                                         return -EINVAL;
4507                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4508                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4509                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4510                                       mirror_conf->vlan.vlan_id[i]))
4511                                         vlan_mask |= (1ULL << reg_index);
4512                                 else
4513                                         return -EINVAL;
4514                         }
4515                 }
4516
4517                 if (on) {
4518                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4519                         mv_msb = vlan_mask >> vlan_mask_offset;
4520
4521                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4522                                                 mirror_conf->vlan.vlan_mask;
4523                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4524                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4525                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4526                                                 mirror_conf->vlan.vlan_id[i];
4527                         }
4528                 } else {
4529                         mv_lsb = 0;
4530                         mv_msb = 0;
4531                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4532                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4533                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4534                 }
4535         }
4536
4537         /*
4538          * if enable pool mirror, write related pool mask register,if disable
4539          * pool mirror, clear PFMRVM register
4540          */
4541         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4542                 mirror_type |= IXGBE_MRCTL_VPME;
4543                 if (on) {
4544                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4545                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4546                         mr_info->mr_conf[rule_id].pool_mask =
4547                                         mirror_conf->pool_mask;
4548
4549                 } else {
4550                         mp_lsb = 0;
4551                         mp_msb = 0;
4552                         mr_info->mr_conf[rule_id].pool_mask = 0;
4553                 }
4554         }
4555         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4556                 mirror_type |= IXGBE_MRCTL_UPME;
4557         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4558                 mirror_type |= IXGBE_MRCTL_DPME;
4559
4560         /* read  mirror control register and recalculate it */
4561         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4562
4563         if (on) {
4564                 mr_ctl |= mirror_type;
4565                 mr_ctl &= mirror_rule_mask;
4566                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4567         } else
4568                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4569
4570         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4571         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4572
4573         /* write mirrror control  register */
4574         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4575
4576         /* write pool mirrror control  register */
4577         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4578                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4579                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4580                                 mp_msb);
4581         }
4582         /* write VLAN mirrror control  register */
4583         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4584                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4585                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4586                                 mv_msb);
4587         }
4588
4589         return 0;
4590 }
4591
4592 static int
4593 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4594 {
4595         int mr_ctl = 0;
4596         uint32_t lsb_val = 0;
4597         uint32_t msb_val = 0;
4598         const uint8_t rule_mr_offset = 4;
4599
4600         struct ixgbe_hw *hw =
4601                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4602         struct ixgbe_mirror_info *mr_info =
4603                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4604
4605         if (ixgbe_vmdq_mode_check(hw) < 0)
4606                 return -ENOTSUP;
4607
4608         memset(&mr_info->mr_conf[rule_id], 0,
4609                 sizeof(struct rte_eth_mirror_conf));
4610
4611         /* clear PFVMCTL register */
4612         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4613
4614         /* clear pool mask register */
4615         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4616         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4617
4618         /* clear vlan mask register */
4619         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4620         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4621
4622         return 0;
4623 }
4624
4625 static int
4626 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4627 {
4628         uint32_t mask;
4629         struct ixgbe_hw *hw =
4630                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4631
4632         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4633         mask |= (1 << IXGBE_MISC_VEC_ID);
4634         RTE_SET_USED(queue_id);
4635         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4636
4637         rte_intr_enable(&dev->pci_dev->intr_handle);
4638
4639         return 0;
4640 }
4641
4642 static int
4643 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4644 {
4645         uint32_t mask;
4646         struct ixgbe_hw *hw =
4647                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4648
4649         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4650         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4651         RTE_SET_USED(queue_id);
4652         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4653
4654         return 0;
4655 }
4656
4657 static int
4658 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4659 {
4660         uint32_t mask;
4661         struct ixgbe_hw *hw =
4662                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4663         struct ixgbe_interrupt *intr =
4664                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4665
4666         if (queue_id < 16) {
4667                 ixgbe_disable_intr(hw);
4668                 intr->mask |= (1 << queue_id);
4669                 ixgbe_enable_intr(dev);
4670         } else if (queue_id < 32) {
4671                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4672                 mask &= (1 << queue_id);
4673                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4674         } else if (queue_id < 64) {
4675                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4676                 mask &= (1 << (queue_id - 32));
4677                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4678         }
4679         rte_intr_enable(&dev->pci_dev->intr_handle);
4680
4681         return 0;
4682 }
4683
4684 static int
4685 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4686 {
4687         uint32_t mask;
4688         struct ixgbe_hw *hw =
4689                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4690         struct ixgbe_interrupt *intr =
4691                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4692
4693         if (queue_id < 16) {
4694                 ixgbe_disable_intr(hw);
4695                 intr->mask &= ~(1 << queue_id);
4696                 ixgbe_enable_intr(dev);
4697         } else if (queue_id < 32) {
4698                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4699                 mask &= ~(1 << queue_id);
4700                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4701         } else if (queue_id < 64) {
4702                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4703                 mask &= ~(1 << (queue_id - 32));
4704                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4705         }
4706
4707         return 0;
4708 }
4709
4710 static void
4711 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4712                      uint8_t queue, uint8_t msix_vector)
4713 {
4714         uint32_t tmp, idx;
4715
4716         if (direction == -1) {
4717                 /* other causes */
4718                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4719                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4720                 tmp &= ~0xFF;
4721                 tmp |= msix_vector;
4722                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4723         } else {
4724                 /* rx or tx cause */
4725                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4726                 idx = ((16 * (queue & 1)) + (8 * direction));
4727                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4728                 tmp &= ~(0xFF << idx);
4729                 tmp |= (msix_vector << idx);
4730                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4731         }
4732 }
4733
4734 /**
4735  * set the IVAR registers, mapping interrupt causes to vectors
4736  * @param hw
4737  *  pointer to ixgbe_hw struct
4738  * @direction
4739  *  0 for Rx, 1 for Tx, -1 for other causes
4740  * @queue
4741  *  queue to map the corresponding interrupt to
4742  * @msix_vector
4743  *  the vector to map to the corresponding queue
4744  */
4745 static void
4746 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4747                    uint8_t queue, uint8_t msix_vector)
4748 {
4749         uint32_t tmp, idx;
4750
4751         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4752         if (hw->mac.type == ixgbe_mac_82598EB) {
4753                 if (direction == -1)
4754                         direction = 0;
4755                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4756                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4757                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4758                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4759                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4760         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4761                         (hw->mac.type == ixgbe_mac_X540)) {
4762                 if (direction == -1) {
4763                         /* other causes */
4764                         idx = ((queue & 1) * 8);
4765                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4766                         tmp &= ~(0xFF << idx);
4767                         tmp |= (msix_vector << idx);
4768                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4769                 } else {
4770                         /* rx or tx causes */
4771                         idx = ((16 * (queue & 1)) + (8 * direction));
4772                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4773                         tmp &= ~(0xFF << idx);
4774                         tmp |= (msix_vector << idx);
4775                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4776                 }
4777         }
4778 }
4779
4780 static void
4781 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4782 {
4783         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4784         struct ixgbe_hw *hw =
4785                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4786         uint32_t q_idx;
4787         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4788
4789         /* won't configure msix register if no mapping is done
4790          * between intr vector and event fd.
4791          */
4792         if (!rte_intr_dp_is_en(intr_handle))
4793                 return;
4794
4795         /* Configure all RX queues of VF */
4796         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4797                 /* Force all queue use vector 0,
4798                  * as IXGBE_VF_MAXMSIVECOTR = 1
4799                  */
4800                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4801                 intr_handle->intr_vec[q_idx] = vector_idx;
4802         }
4803
4804         /* Configure VF other cause ivar */
4805         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4806 }
4807
4808 /**
4809  * Sets up the hardware to properly generate MSI-X interrupts
4810  * @hw
4811  *  board private structure
4812  */
4813 static void
4814 ixgbe_configure_msix(struct rte_eth_dev *dev)
4815 {
4816         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4817         struct ixgbe_hw *hw =
4818                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4819         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4820         uint32_t vec = IXGBE_MISC_VEC_ID;
4821         uint32_t mask;
4822         uint32_t gpie;
4823
4824         /* won't configure msix register if no mapping is done
4825          * between intr vector and event fd
4826          */
4827         if (!rte_intr_dp_is_en(intr_handle))
4828                 return;
4829
4830         if (rte_intr_allow_others(intr_handle))
4831                 vec = base = IXGBE_RX_VEC_START;
4832
4833         /* setup GPIE for MSI-x mode */
4834         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4835         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4836                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4837         /* auto clearing and auto setting corresponding bits in EIMS
4838          * when MSI-X interrupt is triggered
4839          */
4840         if (hw->mac.type == ixgbe_mac_82598EB) {
4841                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4842         } else {
4843                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4844                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4845         }
4846         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4847
4848         /* Populate the IVAR table and set the ITR values to the
4849          * corresponding register.
4850          */
4851         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4852              queue_id++) {
4853                 /* by default, 1:1 mapping */
4854                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4855                 intr_handle->intr_vec[queue_id] = vec;
4856                 if (vec < base + intr_handle->nb_efd - 1)
4857                         vec++;
4858         }
4859
4860         switch (hw->mac.type) {
4861         case ixgbe_mac_82598EB:
4862                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4863                                    IXGBE_MISC_VEC_ID);
4864                 break;
4865         case ixgbe_mac_82599EB:
4866         case ixgbe_mac_X540:
4867                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4868                 break;
4869         default:
4870                 break;
4871         }
4872         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4873                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4874
4875         /* set up to autoclear timer, and the vectors */
4876         mask = IXGBE_EIMS_ENABLE_MASK;
4877         mask &= ~(IXGBE_EIMS_OTHER |
4878                   IXGBE_EIMS_MAILBOX |
4879                   IXGBE_EIMS_LSC);
4880
4881         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4882 }
4883
4884 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4885         uint16_t queue_idx, uint16_t tx_rate)
4886 {
4887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4888         uint32_t rf_dec, rf_int;
4889         uint32_t bcnrc_val;
4890         uint16_t link_speed = dev->data->dev_link.link_speed;
4891
4892         if (queue_idx >= hw->mac.max_tx_queues)
4893                 return -EINVAL;
4894
4895         if (tx_rate != 0) {
4896                 /* Calculate the rate factor values to set */
4897                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4898                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4899                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4900
4901                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4902                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4903                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4904                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4905         } else {
4906                 bcnrc_val = 0;
4907         }
4908
4909         /*
4910          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4911          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4912          * set as 0x4.
4913          */
4914         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4915                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4916                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4917                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4918                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4919         else
4920                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4921                         IXGBE_MMW_SIZE_DEFAULT);
4922
4923         /* Set RTTBCNRC of queue X */
4924         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4925         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4926         IXGBE_WRITE_FLUSH(hw);
4927
4928         return 0;
4929 }
4930
4931 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4932         uint16_t tx_rate, uint64_t q_msk)
4933 {
4934         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4935         struct ixgbe_vf_info *vfinfo =
4936                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4937         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4938         uint32_t queue_stride =
4939                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4940         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4941         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4942         uint16_t total_rate = 0;
4943
4944         if (queue_end >= hw->mac.max_tx_queues)
4945                 return -EINVAL;
4946
4947         if (vfinfo != NULL) {
4948                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4949                         if (vf_idx == vf)
4950                                 continue;
4951                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4952                                 idx++)
4953                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4954                 }
4955         } else
4956                 return -EINVAL;
4957
4958         /* Store tx_rate for this vf. */
4959         for (idx = 0; idx < nb_q_per_pool; idx++) {
4960                 if (((uint64_t)0x1 << idx) & q_msk) {
4961                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4962                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4963                         total_rate += tx_rate;
4964                 }
4965         }
4966
4967         if (total_rate > dev->data->dev_link.link_speed) {
4968                 /*
4969                  * Reset stored TX rate of the VF if it causes exceed
4970                  * link speed.
4971                  */
4972                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4973                 return -EINVAL;
4974         }
4975
4976         /* Set RTTBCNRC of each queue/pool for vf X  */
4977         for (; queue_idx <= queue_end; queue_idx++) {
4978                 if (0x1 & q_msk)
4979                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4980                 q_msk = q_msk >> 1;
4981         }
4982
4983         return 0;
4984 }
4985
4986 static void
4987 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4988                      __attribute__((unused)) uint32_t index,
4989                      __attribute__((unused)) uint32_t pool)
4990 {
4991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4992         int diag;
4993
4994         /*
4995          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4996          * operation. Trap this case to avoid exhausting the [very limited]
4997          * set of PF resources used to store VF MAC addresses.
4998          */
4999         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5000                 return;
5001         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5002         if (diag == 0)
5003                 return;
5004         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5005 }
5006
5007 static void
5008 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5009 {
5010         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5011         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5012         struct ether_addr *mac_addr;
5013         uint32_t i;
5014         int diag;
5015
5016         /*
5017          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5018          * not support the deletion of a given MAC address.
5019          * Instead, it imposes to delete all MAC addresses, then to add again
5020          * all MAC addresses with the exception of the one to be deleted.
5021          */
5022         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5023
5024         /*
5025          * Add again all MAC addresses, with the exception of the deleted one
5026          * and of the permanent MAC address.
5027          */
5028         for (i = 0, mac_addr = dev->data->mac_addrs;
5029              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5030                 /* Skip the deleted MAC address */
5031                 if (i == index)
5032                         continue;
5033                 /* Skip NULL MAC addresses */
5034                 if (is_zero_ether_addr(mac_addr))
5035                         continue;
5036                 /* Skip the permanent MAC address */
5037                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5038                         continue;
5039                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5040                 if (diag != 0)
5041                         PMD_DRV_LOG(ERR,
5042                                     "Adding again MAC address "
5043                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5044                                     "diag=%d",
5045                                     mac_addr->addr_bytes[0],
5046                                     mac_addr->addr_bytes[1],
5047                                     mac_addr->addr_bytes[2],
5048                                     mac_addr->addr_bytes[3],
5049                                     mac_addr->addr_bytes[4],
5050                                     mac_addr->addr_bytes[5],
5051                                     diag);
5052         }
5053 }
5054
5055 static void
5056 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5057 {
5058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5059
5060         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5061 }
5062
5063 #define MAC_TYPE_FILTER_SUP(type)    do {\
5064         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5065                 (type) != ixgbe_mac_X550)\
5066                 return -ENOTSUP;\
5067 } while (0)
5068
5069 static int
5070 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5071                         struct rte_eth_syn_filter *filter,
5072                         bool add)
5073 {
5074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5075         uint32_t synqf;
5076
5077         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5078                 return -EINVAL;
5079
5080         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5081
5082         if (add) {
5083                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5084                         return -EINVAL;
5085                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5086                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5087
5088                 if (filter->hig_pri)
5089                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5090                 else
5091                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5092         } else {
5093                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5094                         return -ENOENT;
5095                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5096         }
5097         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5098         IXGBE_WRITE_FLUSH(hw);
5099         return 0;
5100 }
5101
5102 static int
5103 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5104                         struct rte_eth_syn_filter *filter)
5105 {
5106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5107         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5108
5109         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5110                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5111                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5112                 return 0;
5113         }
5114         return -ENOENT;
5115 }
5116
5117 static int
5118 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5119                         enum rte_filter_op filter_op,
5120                         void *arg)
5121 {
5122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5123         int ret;
5124
5125         MAC_TYPE_FILTER_SUP(hw->mac.type);
5126
5127         if (filter_op == RTE_ETH_FILTER_NOP)
5128                 return 0;
5129
5130         if (arg == NULL) {
5131                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5132                             filter_op);
5133                 return -EINVAL;
5134         }
5135
5136         switch (filter_op) {
5137         case RTE_ETH_FILTER_ADD:
5138                 ret = ixgbe_syn_filter_set(dev,
5139                                 (struct rte_eth_syn_filter *)arg,
5140                                 TRUE);
5141                 break;
5142         case RTE_ETH_FILTER_DELETE:
5143                 ret = ixgbe_syn_filter_set(dev,
5144                                 (struct rte_eth_syn_filter *)arg,
5145                                 FALSE);
5146                 break;
5147         case RTE_ETH_FILTER_GET:
5148                 ret = ixgbe_syn_filter_get(dev,
5149                                 (struct rte_eth_syn_filter *)arg);
5150                 break;
5151         default:
5152                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5153                 ret = -EINVAL;
5154                 break;
5155         }
5156
5157         return ret;
5158 }
5159
5160
5161 static inline enum ixgbe_5tuple_protocol
5162 convert_protocol_type(uint8_t protocol_value)
5163 {
5164         if (protocol_value == IPPROTO_TCP)
5165                 return IXGBE_FILTER_PROTOCOL_TCP;
5166         else if (protocol_value == IPPROTO_UDP)
5167                 return IXGBE_FILTER_PROTOCOL_UDP;
5168         else if (protocol_value == IPPROTO_SCTP)
5169                 return IXGBE_FILTER_PROTOCOL_SCTP;
5170         else
5171                 return IXGBE_FILTER_PROTOCOL_NONE;
5172 }
5173
5174 /*
5175  * add a 5tuple filter
5176  *
5177  * @param
5178  * dev: Pointer to struct rte_eth_dev.
5179  * index: the index the filter allocates.
5180  * filter: ponter to the filter that will be added.
5181  * rx_queue: the queue id the filter assigned to.
5182  *
5183  * @return
5184  *    - On success, zero.
5185  *    - On failure, a negative value.
5186  */
5187 static int
5188 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5189                         struct ixgbe_5tuple_filter *filter)
5190 {
5191         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5192         struct ixgbe_filter_info *filter_info =
5193                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5194         int i, idx, shift;
5195         uint32_t ftqf, sdpqf;
5196         uint32_t l34timir = 0;
5197         uint8_t mask = 0xff;
5198
5199         /*
5200          * look for an unused 5tuple filter index,
5201          * and insert the filter to list.
5202          */
5203         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5204                 idx = i / (sizeof(uint32_t) * NBBY);
5205                 shift = i % (sizeof(uint32_t) * NBBY);
5206                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5207                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5208                         filter->index = i;
5209                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5210                                           filter,
5211                                           entries);
5212                         break;
5213                 }
5214         }
5215         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5216                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5217                 return -ENOSYS;
5218         }
5219
5220         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5221                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5222         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5223
5224         ftqf = (uint32_t)(filter->filter_info.proto &
5225                 IXGBE_FTQF_PROTOCOL_MASK);
5226         ftqf |= (uint32_t)((filter->filter_info.priority &
5227                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5228         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5229                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5230         if (filter->filter_info.dst_ip_mask == 0)
5231                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5232         if (filter->filter_info.src_port_mask == 0)
5233                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5234         if (filter->filter_info.dst_port_mask == 0)
5235                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5236         if (filter->filter_info.proto_mask == 0)
5237                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5238         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5239         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5240         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5241
5242         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5243         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5244         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5245         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5246
5247         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5248         l34timir |= (uint32_t)(filter->queue <<
5249                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5250         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5251         return 0;
5252 }
5253
5254 /*
5255  * remove a 5tuple filter
5256  *
5257  * @param
5258  * dev: Pointer to struct rte_eth_dev.
5259  * filter: the pointer of the filter will be removed.
5260  */
5261 static void
5262 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5263                         struct ixgbe_5tuple_filter *filter)
5264 {
5265         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5266         struct ixgbe_filter_info *filter_info =
5267                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5268         uint16_t index = filter->index;
5269
5270         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5271                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5272         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5273         rte_free(filter);
5274
5275         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5276         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5277         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5278         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5279         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5280 }
5281
5282 static int
5283 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5284 {
5285         struct ixgbe_hw *hw;
5286         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5287
5288         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5289
5290         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5291                 return -EINVAL;
5292
5293         /* refuse mtu that requires the support of scattered packets when this
5294          * feature has not been enabled before. */
5295         if (!dev->data->scattered_rx &&
5296             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5297              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5298                 return -EINVAL;
5299
5300         /*
5301          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5302          * request of the version 2.0 of the mailbox API.
5303          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5304          * of the mailbox API.
5305          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5306          * prior to 3.11.33 which contains the following change:
5307          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5308          */
5309         ixgbevf_rlpml_set_vf(hw, max_frame);
5310
5311         /* update max frame size */
5312         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5313         return 0;
5314 }
5315
5316 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5317         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5318                 return -ENOTSUP;\
5319 } while (0)
5320
5321 static inline struct ixgbe_5tuple_filter *
5322 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5323                         struct ixgbe_5tuple_filter_info *key)
5324 {
5325         struct ixgbe_5tuple_filter *it;
5326
5327         TAILQ_FOREACH(it, filter_list, entries) {
5328                 if (memcmp(key, &it->filter_info,
5329                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5330                         return it;
5331                 }
5332         }
5333         return NULL;
5334 }
5335
5336 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5337 static inline int
5338 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5339                         struct ixgbe_5tuple_filter_info *filter_info)
5340 {
5341         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5342                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5343                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5344                 return -EINVAL;
5345
5346         switch (filter->dst_ip_mask) {
5347         case UINT32_MAX:
5348                 filter_info->dst_ip_mask = 0;
5349                 filter_info->dst_ip = filter->dst_ip;
5350                 break;
5351         case 0:
5352                 filter_info->dst_ip_mask = 1;
5353                 break;
5354         default:
5355                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5356                 return -EINVAL;
5357         }
5358
5359         switch (filter->src_ip_mask) {
5360         case UINT32_MAX:
5361                 filter_info->src_ip_mask = 0;
5362                 filter_info->src_ip = filter->src_ip;
5363                 break;
5364         case 0:
5365                 filter_info->src_ip_mask = 1;
5366                 break;
5367         default:
5368                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5369                 return -EINVAL;
5370         }
5371
5372         switch (filter->dst_port_mask) {
5373         case UINT16_MAX:
5374                 filter_info->dst_port_mask = 0;
5375                 filter_info->dst_port = filter->dst_port;
5376                 break;
5377         case 0:
5378                 filter_info->dst_port_mask = 1;
5379                 break;
5380         default:
5381                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5382                 return -EINVAL;
5383         }
5384
5385         switch (filter->src_port_mask) {
5386         case UINT16_MAX:
5387                 filter_info->src_port_mask = 0;
5388                 filter_info->src_port = filter->src_port;
5389                 break;
5390         case 0:
5391                 filter_info->src_port_mask = 1;
5392                 break;
5393         default:
5394                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5395                 return -EINVAL;
5396         }
5397
5398         switch (filter->proto_mask) {
5399         case UINT8_MAX:
5400                 filter_info->proto_mask = 0;
5401                 filter_info->proto =
5402                         convert_protocol_type(filter->proto);
5403                 break;
5404         case 0:
5405                 filter_info->proto_mask = 1;
5406                 break;
5407         default:
5408                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5409                 return -EINVAL;
5410         }
5411
5412         filter_info->priority = (uint8_t)filter->priority;
5413         return 0;
5414 }
5415
5416 /*
5417  * add or delete a ntuple filter
5418  *
5419  * @param
5420  * dev: Pointer to struct rte_eth_dev.
5421  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5422  * add: if true, add filter, if false, remove filter
5423  *
5424  * @return
5425  *    - On success, zero.
5426  *    - On failure, a negative value.
5427  */
5428 static int
5429 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5430                         struct rte_eth_ntuple_filter *ntuple_filter,
5431                         bool add)
5432 {
5433         struct ixgbe_filter_info *filter_info =
5434                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5435         struct ixgbe_5tuple_filter_info filter_5tuple;
5436         struct ixgbe_5tuple_filter *filter;
5437         int ret;
5438
5439         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5440                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5441                 return -EINVAL;
5442         }
5443
5444         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5445         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5446         if (ret < 0)
5447                 return ret;
5448
5449         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5450                                          &filter_5tuple);
5451         if (filter != NULL && add) {
5452                 PMD_DRV_LOG(ERR, "filter exists.");
5453                 return -EEXIST;
5454         }
5455         if (filter == NULL && !add) {
5456                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5457                 return -ENOENT;
5458         }
5459
5460         if (add) {
5461                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5462                                 sizeof(struct ixgbe_5tuple_filter), 0);
5463                 if (filter == NULL)
5464                         return -ENOMEM;
5465                 (void)rte_memcpy(&filter->filter_info,
5466                                  &filter_5tuple,
5467                                  sizeof(struct ixgbe_5tuple_filter_info));
5468                 filter->queue = ntuple_filter->queue;
5469                 ret = ixgbe_add_5tuple_filter(dev, filter);
5470                 if (ret < 0) {
5471                         rte_free(filter);
5472                         return ret;
5473                 }
5474         } else
5475                 ixgbe_remove_5tuple_filter(dev, filter);
5476
5477         return 0;
5478 }
5479
5480 /*
5481  * get a ntuple filter
5482  *
5483  * @param
5484  * dev: Pointer to struct rte_eth_dev.
5485  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5486  *
5487  * @return
5488  *    - On success, zero.
5489  *    - On failure, a negative value.
5490  */
5491 static int
5492 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5493                         struct rte_eth_ntuple_filter *ntuple_filter)
5494 {
5495         struct ixgbe_filter_info *filter_info =
5496                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5497         struct ixgbe_5tuple_filter_info filter_5tuple;
5498         struct ixgbe_5tuple_filter *filter;
5499         int ret;
5500
5501         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5502                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5503                 return -EINVAL;
5504         }
5505
5506         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5507         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5508         if (ret < 0)
5509                 return ret;
5510
5511         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5512                                          &filter_5tuple);
5513         if (filter == NULL) {
5514                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5515                 return -ENOENT;
5516         }
5517         ntuple_filter->queue = filter->queue;
5518         return 0;
5519 }
5520
5521 /*
5522  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5523  * @dev: pointer to rte_eth_dev structure
5524  * @filter_op:operation will be taken.
5525  * @arg: a pointer to specific structure corresponding to the filter_op
5526  *
5527  * @return
5528  *    - On success, zero.
5529  *    - On failure, a negative value.
5530  */
5531 static int
5532 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5533                                 enum rte_filter_op filter_op,
5534                                 void *arg)
5535 {
5536         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5537         int ret;
5538
5539         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5540
5541         if (filter_op == RTE_ETH_FILTER_NOP)
5542                 return 0;
5543
5544         if (arg == NULL) {
5545                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5546                             filter_op);
5547                 return -EINVAL;
5548         }
5549
5550         switch (filter_op) {
5551         case RTE_ETH_FILTER_ADD:
5552                 ret = ixgbe_add_del_ntuple_filter(dev,
5553                         (struct rte_eth_ntuple_filter *)arg,
5554                         TRUE);
5555                 break;
5556         case RTE_ETH_FILTER_DELETE:
5557                 ret = ixgbe_add_del_ntuple_filter(dev,
5558                         (struct rte_eth_ntuple_filter *)arg,
5559                         FALSE);
5560                 break;
5561         case RTE_ETH_FILTER_GET:
5562                 ret = ixgbe_get_ntuple_filter(dev,
5563                         (struct rte_eth_ntuple_filter *)arg);
5564                 break;
5565         default:
5566                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5567                 ret = -EINVAL;
5568                 break;
5569         }
5570         return ret;
5571 }
5572
5573 static inline int
5574 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5575                         uint16_t ethertype)
5576 {
5577         int i;
5578
5579         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5580                 if (filter_info->ethertype_filters[i] == ethertype &&
5581                     (filter_info->ethertype_mask & (1 << i)))
5582                         return i;
5583         }
5584         return -1;
5585 }
5586
5587 static inline int
5588 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5589                         uint16_t ethertype)
5590 {
5591         int i;
5592
5593         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5594                 if (!(filter_info->ethertype_mask & (1 << i))) {
5595                         filter_info->ethertype_mask |= 1 << i;
5596                         filter_info->ethertype_filters[i] = ethertype;
5597                         return i;
5598                 }
5599         }
5600         return -1;
5601 }
5602
5603 static inline int
5604 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5605                         uint8_t idx)
5606 {
5607         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5608                 return -1;
5609         filter_info->ethertype_mask &= ~(1 << idx);
5610         filter_info->ethertype_filters[idx] = 0;
5611         return idx;
5612 }
5613
5614 static int
5615 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5616                         struct rte_eth_ethertype_filter *filter,
5617                         bool add)
5618 {
5619         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5620         struct ixgbe_filter_info *filter_info =
5621                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5622         uint32_t etqf = 0;
5623         uint32_t etqs = 0;
5624         int ret;
5625
5626         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5627                 return -EINVAL;
5628
5629         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5630                 filter->ether_type == ETHER_TYPE_IPv6) {
5631                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5632                         " ethertype filter.", filter->ether_type);
5633                 return -EINVAL;
5634         }
5635
5636         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5637                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5638                 return -EINVAL;
5639         }
5640         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5641                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5642                 return -EINVAL;
5643         }
5644
5645         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5646         if (ret >= 0 && add) {
5647                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5648                             filter->ether_type);
5649                 return -EEXIST;
5650         }
5651         if (ret < 0 && !add) {
5652                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5653                             filter->ether_type);
5654                 return -ENOENT;
5655         }
5656
5657         if (add) {
5658                 ret = ixgbe_ethertype_filter_insert(filter_info,
5659                         filter->ether_type);
5660                 if (ret < 0) {
5661                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5662                         return -ENOSYS;
5663                 }
5664                 etqf = IXGBE_ETQF_FILTER_EN;
5665                 etqf |= (uint32_t)filter->ether_type;
5666                 etqs |= (uint32_t)((filter->queue <<
5667                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5668                                     IXGBE_ETQS_RX_QUEUE);
5669                 etqs |= IXGBE_ETQS_QUEUE_EN;
5670         } else {
5671                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5672                 if (ret < 0)
5673                         return -ENOSYS;
5674         }
5675         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5676         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5677         IXGBE_WRITE_FLUSH(hw);
5678
5679         return 0;
5680 }
5681
5682 static int
5683 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5684                         struct rte_eth_ethertype_filter *filter)
5685 {
5686         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5687         struct ixgbe_filter_info *filter_info =
5688                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5689         uint32_t etqf, etqs;
5690         int ret;
5691
5692         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5693         if (ret < 0) {
5694                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5695                             filter->ether_type);
5696                 return -ENOENT;
5697         }
5698
5699         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5700         if (etqf & IXGBE_ETQF_FILTER_EN) {
5701                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5702                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5703                 filter->flags = 0;
5704                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5705                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5706                 return 0;
5707         }
5708         return -ENOENT;
5709 }
5710
5711 /*
5712  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5713  * @dev: pointer to rte_eth_dev structure
5714  * @filter_op:operation will be taken.
5715  * @arg: a pointer to specific structure corresponding to the filter_op
5716  */
5717 static int
5718 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5719                                 enum rte_filter_op filter_op,
5720                                 void *arg)
5721 {
5722         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5723         int ret;
5724
5725         MAC_TYPE_FILTER_SUP(hw->mac.type);
5726
5727         if (filter_op == RTE_ETH_FILTER_NOP)
5728                 return 0;
5729
5730         if (arg == NULL) {
5731                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5732                             filter_op);
5733                 return -EINVAL;
5734         }
5735
5736         switch (filter_op) {
5737         case RTE_ETH_FILTER_ADD:
5738                 ret = ixgbe_add_del_ethertype_filter(dev,
5739                         (struct rte_eth_ethertype_filter *)arg,
5740                         TRUE);
5741                 break;
5742         case RTE_ETH_FILTER_DELETE:
5743                 ret = ixgbe_add_del_ethertype_filter(dev,
5744                         (struct rte_eth_ethertype_filter *)arg,
5745                         FALSE);
5746                 break;
5747         case RTE_ETH_FILTER_GET:
5748                 ret = ixgbe_get_ethertype_filter(dev,
5749                         (struct rte_eth_ethertype_filter *)arg);
5750                 break;
5751         default:
5752                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5753                 ret = -EINVAL;
5754                 break;
5755         }
5756         return ret;
5757 }
5758
5759 static int
5760 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5761                      enum rte_filter_type filter_type,
5762                      enum rte_filter_op filter_op,
5763                      void *arg)
5764 {
5765         int ret = -EINVAL;
5766
5767         switch (filter_type) {
5768         case RTE_ETH_FILTER_NTUPLE:
5769                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5770                 break;
5771         case RTE_ETH_FILTER_ETHERTYPE:
5772                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5773                 break;
5774         case RTE_ETH_FILTER_SYN:
5775                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5776                 break;
5777         case RTE_ETH_FILTER_FDIR:
5778                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5779                 break;
5780         case RTE_ETH_FILTER_L2_TUNNEL:
5781                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5782                 break;
5783         default:
5784                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5785                                                         filter_type);
5786                 break;
5787         }
5788
5789         return ret;
5790 }
5791
5792 static u8 *
5793 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5794                         u8 **mc_addr_ptr, u32 *vmdq)
5795 {
5796         u8 *mc_addr;
5797
5798         *vmdq = 0;
5799         mc_addr = *mc_addr_ptr;
5800         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5801         return mc_addr;
5802 }
5803
5804 static int
5805 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5806                           struct ether_addr *mc_addr_set,
5807                           uint32_t nb_mc_addr)
5808 {
5809         struct ixgbe_hw *hw;
5810         u8 *mc_addr_list;
5811
5812         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5813         mc_addr_list = (u8 *)mc_addr_set;
5814         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5815                                          ixgbe_dev_addr_list_itr, TRUE);
5816 }
5817
5818 static uint64_t
5819 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5820 {
5821         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5822         uint64_t systime_cycles;
5823
5824         switch (hw->mac.type) {
5825         case ixgbe_mac_X550:
5826                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5827                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5828                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5829                                 * NSEC_PER_SEC;
5830                 break;
5831         default:
5832                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5833                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5834                                 << 32;
5835         }
5836
5837         return systime_cycles;
5838 }
5839
5840 static uint64_t
5841 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5842 {
5843         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5844         uint64_t rx_tstamp_cycles;
5845
5846         switch (hw->mac.type) {
5847         case ixgbe_mac_X550:
5848                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5849                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5850                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5851                                 * NSEC_PER_SEC;
5852                 break;
5853         default:
5854                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5855                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5856                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5857                                 << 32;
5858         }
5859
5860         return rx_tstamp_cycles;
5861 }
5862
5863 static uint64_t
5864 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5865 {
5866         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5867         uint64_t tx_tstamp_cycles;
5868
5869         switch (hw->mac.type) {
5870         case ixgbe_mac_X550:
5871                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5872                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5873                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5874                                 * NSEC_PER_SEC;
5875                 break;
5876         default:
5877                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5878                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5879                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5880                                 << 32;
5881         }
5882
5883         return tx_tstamp_cycles;
5884 }
5885
5886 static void
5887 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5888 {
5889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5890         struct ixgbe_adapter *adapter =
5891                 (struct ixgbe_adapter *)dev->data->dev_private;
5892         struct rte_eth_link link;
5893         uint32_t incval = 0;
5894         uint32_t shift = 0;
5895
5896         /* Get current link speed. */
5897         memset(&link, 0, sizeof(link));
5898         ixgbe_dev_link_update(dev, 1);
5899         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5900
5901         switch (link.link_speed) {
5902         case ETH_LINK_SPEED_100:
5903                 incval = IXGBE_INCVAL_100;
5904                 shift = IXGBE_INCVAL_SHIFT_100;
5905                 break;
5906         case ETH_LINK_SPEED_1000:
5907                 incval = IXGBE_INCVAL_1GB;
5908                 shift = IXGBE_INCVAL_SHIFT_1GB;
5909                 break;
5910         case ETH_LINK_SPEED_10000:
5911         default:
5912                 incval = IXGBE_INCVAL_10GB;
5913                 shift = IXGBE_INCVAL_SHIFT_10GB;
5914                 break;
5915         }
5916
5917         switch (hw->mac.type) {
5918         case ixgbe_mac_X550:
5919                 /* Independent of link speed. */
5920                 incval = 1;
5921                 /* Cycles read will be interpreted as ns. */
5922                 shift = 0;
5923                 /* Fall-through */
5924         case ixgbe_mac_X540:
5925                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5926                 break;
5927         case ixgbe_mac_82599EB:
5928                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5929                 shift -= IXGBE_INCVAL_SHIFT_82599;
5930                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5931                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5932                 break;
5933         default:
5934                 /* Not supported. */
5935                 return;
5936         }
5937
5938         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5939         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5940         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5941
5942         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5943         adapter->systime_tc.cc_shift = shift;
5944         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5945
5946         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5947         adapter->rx_tstamp_tc.cc_shift = shift;
5948         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5949
5950         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5951         adapter->tx_tstamp_tc.cc_shift = shift;
5952         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5953 }
5954
5955 static int
5956 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5957 {
5958         struct ixgbe_adapter *adapter =
5959                         (struct ixgbe_adapter *)dev->data->dev_private;
5960
5961         adapter->systime_tc.nsec += delta;
5962         adapter->rx_tstamp_tc.nsec += delta;
5963         adapter->tx_tstamp_tc.nsec += delta;
5964
5965         return 0;
5966 }
5967
5968 static int
5969 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5970 {
5971         uint64_t ns;
5972         struct ixgbe_adapter *adapter =
5973                         (struct ixgbe_adapter *)dev->data->dev_private;
5974
5975         ns = rte_timespec_to_ns(ts);
5976         /* Set the timecounters to a new value. */
5977         adapter->systime_tc.nsec = ns;
5978         adapter->rx_tstamp_tc.nsec = ns;
5979         adapter->tx_tstamp_tc.nsec = ns;
5980
5981         return 0;
5982 }
5983
5984 static int
5985 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5986 {
5987         uint64_t ns, systime_cycles;
5988         struct ixgbe_adapter *adapter =
5989                         (struct ixgbe_adapter *)dev->data->dev_private;
5990
5991         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5992         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5993         *ts = rte_ns_to_timespec(ns);
5994
5995         return 0;
5996 }
5997
5998 static int
5999 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6000 {
6001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6002         uint32_t tsync_ctl;
6003         uint32_t tsauxc;
6004
6005         /* Stop the timesync system time. */
6006         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6007         /* Reset the timesync system time value. */
6008         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6009         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6010
6011         /* Enable system time for platforms where it isn't on by default. */
6012         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6013         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6014         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6015
6016         ixgbe_start_timecounters(dev);
6017
6018         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6019         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6020                         (ETHER_TYPE_1588 |
6021                          IXGBE_ETQF_FILTER_EN |
6022                          IXGBE_ETQF_1588));
6023
6024         /* Enable timestamping of received PTP packets. */
6025         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6026         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6027         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6028
6029         /* Enable timestamping of transmitted PTP packets. */
6030         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6031         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6032         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6033
6034         IXGBE_WRITE_FLUSH(hw);
6035
6036         return 0;
6037 }
6038
6039 static int
6040 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6041 {
6042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6043         uint32_t tsync_ctl;
6044
6045         /* Disable timestamping of transmitted PTP packets. */
6046         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6047         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6048         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6049
6050         /* Disable timestamping of received PTP packets. */
6051         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6052         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6053         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6054
6055         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6056         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6057
6058         /* Stop incrementating the System Time registers. */
6059         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6060
6061         return 0;
6062 }
6063
6064 static int
6065 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6066                                  struct timespec *timestamp,
6067                                  uint32_t flags __rte_unused)
6068 {
6069         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6070         struct ixgbe_adapter *adapter =
6071                 (struct ixgbe_adapter *)dev->data->dev_private;
6072         uint32_t tsync_rxctl;
6073         uint64_t rx_tstamp_cycles;
6074         uint64_t ns;
6075
6076         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6077         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6078                 return -EINVAL;
6079
6080         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6081         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6082         *timestamp = rte_ns_to_timespec(ns);
6083
6084         return  0;
6085 }
6086
6087 static int
6088 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6089                                  struct timespec *timestamp)
6090 {
6091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6092         struct ixgbe_adapter *adapter =
6093                 (struct ixgbe_adapter *)dev->data->dev_private;
6094         uint32_t tsync_txctl;
6095         uint64_t tx_tstamp_cycles;
6096         uint64_t ns;
6097
6098         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6099         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6100                 return -EINVAL;
6101
6102         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6103         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6104         *timestamp = rte_ns_to_timespec(ns);
6105
6106         return 0;
6107 }
6108
6109 static int
6110 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6111 {
6112         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6113         int count = 0;
6114         int g_ind = 0;
6115         const struct reg_info *reg_group;
6116         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6117                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6118
6119         while ((reg_group = reg_set[g_ind++]))
6120                 count += ixgbe_regs_group_count(reg_group);
6121
6122         return count;
6123 }
6124
6125 static int
6126 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6127 {
6128         int count = 0;
6129         int g_ind = 0;
6130         const struct reg_info *reg_group;
6131
6132         while ((reg_group = ixgbevf_regs[g_ind++]))
6133                 count += ixgbe_regs_group_count(reg_group);
6134
6135         return count;
6136 }
6137
6138 static int
6139 ixgbe_get_regs(struct rte_eth_dev *dev,
6140               struct rte_dev_reg_info *regs)
6141 {
6142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6143         uint32_t *data = regs->data;
6144         int g_ind = 0;
6145         int count = 0;
6146         const struct reg_info *reg_group;
6147         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6148                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6149
6150         /* Support only full register dump */
6151         if ((regs->length == 0) ||
6152             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6153                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6154                         hw->device_id;
6155                 while ((reg_group = reg_set[g_ind++]))
6156                         count += ixgbe_read_regs_group(dev, &data[count],
6157                                 reg_group);
6158                 return 0;
6159         }
6160
6161         return -ENOTSUP;
6162 }
6163
6164 static int
6165 ixgbevf_get_regs(struct rte_eth_dev *dev,
6166                 struct rte_dev_reg_info *regs)
6167 {
6168         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6169         uint32_t *data = regs->data;
6170         int g_ind = 0;
6171         int count = 0;
6172         const struct reg_info *reg_group;
6173
6174         /* Support only full register dump */
6175         if ((regs->length == 0) ||
6176             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6177                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6178                         hw->device_id;
6179                 while ((reg_group = ixgbevf_regs[g_ind++]))
6180                         count += ixgbe_read_regs_group(dev, &data[count],
6181                                                       reg_group);
6182                 return 0;
6183         }
6184
6185         return -ENOTSUP;
6186 }
6187
6188 static int
6189 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6190 {
6191         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6192
6193         /* Return unit is byte count */
6194         return hw->eeprom.word_size * 2;
6195 }
6196
6197 static int
6198 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6199                 struct rte_dev_eeprom_info *in_eeprom)
6200 {
6201         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6202         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6203         uint16_t *data = in_eeprom->data;
6204         int first, length;
6205
6206         first = in_eeprom->offset >> 1;
6207         length = in_eeprom->length >> 1;
6208         if ((first > hw->eeprom.word_size) ||
6209             ((first + length) > hw->eeprom.word_size))
6210                 return -EINVAL;
6211
6212         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6213
6214         return eeprom->ops.read_buffer(hw, first, length, data);
6215 }
6216
6217 static int
6218 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6219                 struct rte_dev_eeprom_info *in_eeprom)
6220 {
6221         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6222         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6223         uint16_t *data = in_eeprom->data;
6224         int first, length;
6225
6226         first = in_eeprom->offset >> 1;
6227         length = in_eeprom->length >> 1;
6228         if ((first > hw->eeprom.word_size) ||
6229             ((first + length) > hw->eeprom.word_size))
6230                 return -EINVAL;
6231
6232         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6233
6234         return eeprom->ops.write_buffer(hw,  first, length, data);
6235 }
6236
6237 uint16_t
6238 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6239         switch (mac_type) {
6240         case ixgbe_mac_X550:
6241         case ixgbe_mac_X550EM_x:
6242         case ixgbe_mac_X550EM_a:
6243                 return ETH_RSS_RETA_SIZE_512;
6244         case ixgbe_mac_X550_vf:
6245         case ixgbe_mac_X550EM_x_vf:
6246         case ixgbe_mac_X550EM_a_vf:
6247                 return ETH_RSS_RETA_SIZE_64;
6248         default:
6249                 return ETH_RSS_RETA_SIZE_128;
6250         }
6251 }
6252
6253 uint32_t
6254 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6255         switch (mac_type) {
6256         case ixgbe_mac_X550:
6257         case ixgbe_mac_X550EM_x:
6258         case ixgbe_mac_X550EM_a:
6259                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6260                         return IXGBE_RETA(reta_idx >> 2);
6261                 else
6262                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6263         case ixgbe_mac_X550_vf:
6264         case ixgbe_mac_X550EM_x_vf:
6265         case ixgbe_mac_X550EM_a_vf:
6266                 return IXGBE_VFRETA(reta_idx >> 2);
6267         default:
6268                 return IXGBE_RETA(reta_idx >> 2);
6269         }
6270 }
6271
6272 uint32_t
6273 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6274         switch (mac_type) {
6275         case ixgbe_mac_X550_vf:
6276         case ixgbe_mac_X550EM_x_vf:
6277         case ixgbe_mac_X550EM_a_vf:
6278                 return IXGBE_VFMRQC;
6279         default:
6280                 return IXGBE_MRQC;
6281         }
6282 }
6283
6284 uint32_t
6285 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6286         switch (mac_type) {
6287         case ixgbe_mac_X550_vf:
6288         case ixgbe_mac_X550EM_x_vf:
6289         case ixgbe_mac_X550EM_a_vf:
6290                 return IXGBE_VFRSSRK(i);
6291         default:
6292                 return IXGBE_RSSRK(i);
6293         }
6294 }
6295
6296 bool
6297 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6298         switch (mac_type) {
6299         case ixgbe_mac_82599_vf:
6300         case ixgbe_mac_X540_vf:
6301                 return 0;
6302         default:
6303                 return 1;
6304         }
6305 }
6306
6307 static int
6308 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6309                         struct rte_eth_dcb_info *dcb_info)
6310 {
6311         struct ixgbe_dcb_config *dcb_config =
6312                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6313         struct ixgbe_dcb_tc_config *tc;
6314         uint8_t i, j;
6315
6316         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6317                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6318         else
6319                 dcb_info->nb_tcs = 1;
6320
6321         if (dcb_config->vt_mode) { /* vt is enabled*/
6322                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6323                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6324                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6325                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6326                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6327                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6328                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6329                                                 i * dcb_info->nb_tcs + j;
6330                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6331                                 dcb_info->tc_queue.tc_txq[i][j].base =
6332                                                 i * dcb_info->nb_tcs + j;
6333                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6334                         }
6335                 }
6336         } else { /* vt is disabled*/
6337                 struct rte_eth_dcb_rx_conf *rx_conf =
6338                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6339                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6340                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6341                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6342                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6343                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6344                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6345                         }
6346                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6347                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6348                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6349                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6350                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6351                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6352                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6353                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6354                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6355                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6356                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6357                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6358                         }
6359                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6360                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6361                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6362                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6363                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6364                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6365                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6366                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6367                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6368                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6369                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6370                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6371                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6372                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6373                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6374                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6375                 }
6376         }
6377         for (i = 0; i < dcb_info->nb_tcs; i++) {
6378                 tc = &dcb_config->tc_config[i];
6379                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6380         }
6381         return 0;
6382 }
6383
6384 /* Update e-tag ether type */
6385 static int
6386 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6387                             uint16_t ether_type)
6388 {
6389         uint32_t etag_etype;
6390
6391         if (hw->mac.type != ixgbe_mac_X550 &&
6392             hw->mac.type != ixgbe_mac_X550EM_x) {
6393                 return -ENOTSUP;
6394         }
6395
6396         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6397         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6398         etag_etype |= ether_type;
6399         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6400         IXGBE_WRITE_FLUSH(hw);
6401
6402         return 0;
6403 }
6404
6405 /* Config l2 tunnel ether type */
6406 static int
6407 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6408                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6409 {
6410         int ret = 0;
6411         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6412
6413         if (l2_tunnel == NULL)
6414                 return -EINVAL;
6415
6416         switch (l2_tunnel->l2_tunnel_type) {
6417         case RTE_L2_TUNNEL_TYPE_E_TAG:
6418                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6419                 break;
6420         default:
6421                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6422                 ret = -EINVAL;
6423                 break;
6424         }
6425
6426         return ret;
6427 }
6428
6429 /* Enable e-tag tunnel */
6430 static int
6431 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6432 {
6433         uint32_t etag_etype;
6434
6435         if (hw->mac.type != ixgbe_mac_X550 &&
6436             hw->mac.type != ixgbe_mac_X550EM_x) {
6437                 return -ENOTSUP;
6438         }
6439
6440         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6441         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6442         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6443         IXGBE_WRITE_FLUSH(hw);
6444
6445         return 0;
6446 }
6447
6448 /* Enable l2 tunnel */
6449 static int
6450 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6451                            enum rte_eth_tunnel_type l2_tunnel_type)
6452 {
6453         int ret = 0;
6454         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6455
6456         switch (l2_tunnel_type) {
6457         case RTE_L2_TUNNEL_TYPE_E_TAG:
6458                 ret = ixgbe_e_tag_enable(hw);
6459                 break;
6460         default:
6461                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6462                 ret = -EINVAL;
6463                 break;
6464         }
6465
6466         return ret;
6467 }
6468
6469 /* Disable e-tag tunnel */
6470 static int
6471 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6472 {
6473         uint32_t etag_etype;
6474
6475         if (hw->mac.type != ixgbe_mac_X550 &&
6476             hw->mac.type != ixgbe_mac_X550EM_x) {
6477                 return -ENOTSUP;
6478         }
6479
6480         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6481         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6482         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6483         IXGBE_WRITE_FLUSH(hw);
6484
6485         return 0;
6486 }
6487
6488 /* Disable l2 tunnel */
6489 static int
6490 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6491                             enum rte_eth_tunnel_type l2_tunnel_type)
6492 {
6493         int ret = 0;
6494         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6495
6496         switch (l2_tunnel_type) {
6497         case RTE_L2_TUNNEL_TYPE_E_TAG:
6498                 ret = ixgbe_e_tag_disable(hw);
6499                 break;
6500         default:
6501                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6502                 ret = -EINVAL;
6503                 break;
6504         }
6505
6506         return ret;
6507 }
6508
6509 static int
6510 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6511                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6512 {
6513         int ret = 0;
6514         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6515         uint32_t i, rar_entries;
6516         uint32_t rar_low, rar_high;
6517
6518         if (hw->mac.type != ixgbe_mac_X550 &&
6519             hw->mac.type != ixgbe_mac_X550EM_x) {
6520                 return -ENOTSUP;
6521         }
6522
6523         rar_entries = ixgbe_get_num_rx_addrs(hw);
6524
6525         for (i = 1; i < rar_entries; i++) {
6526                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6527                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6528                 if ((rar_high & IXGBE_RAH_AV) &&
6529                     (rar_high & IXGBE_RAH_ADTYPE) &&
6530                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6531                      l2_tunnel->tunnel_id)) {
6532                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6533                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6534
6535                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6536
6537                         return ret;
6538                 }
6539         }
6540
6541         return ret;
6542 }
6543
6544 static int
6545 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6546                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6547 {
6548         int ret = 0;
6549         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6550         uint32_t i, rar_entries;
6551         uint32_t rar_low, rar_high;
6552
6553         if (hw->mac.type != ixgbe_mac_X550 &&
6554             hw->mac.type != ixgbe_mac_X550EM_x) {
6555                 return -ENOTSUP;
6556         }
6557
6558         /* One entry for one tunnel. Try to remove potential existing entry. */
6559         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6560
6561         rar_entries = ixgbe_get_num_rx_addrs(hw);
6562
6563         for (i = 1; i < rar_entries; i++) {
6564                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6565                 if (rar_high & IXGBE_RAH_AV) {
6566                         continue;
6567                 } else {
6568                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6569                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6570                         rar_low = l2_tunnel->tunnel_id;
6571
6572                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6573                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6574
6575                         return ret;
6576                 }
6577         }
6578
6579         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6580                      " Please remove a rule before adding a new one.");
6581         return -EINVAL;
6582 }
6583
6584 /* Add l2 tunnel filter */
6585 static int
6586 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6587                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6588 {
6589         int ret = 0;
6590
6591         switch (l2_tunnel->l2_tunnel_type) {
6592         case RTE_L2_TUNNEL_TYPE_E_TAG:
6593                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6594                 break;
6595         default:
6596                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6597                 ret = -EINVAL;
6598                 break;
6599         }
6600
6601         return ret;
6602 }
6603
6604 /* Delete l2 tunnel filter */
6605 static int
6606 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6607                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6608 {
6609         int ret = 0;
6610
6611         switch (l2_tunnel->l2_tunnel_type) {
6612         case RTE_L2_TUNNEL_TYPE_E_TAG:
6613                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6614                 break;
6615         default:
6616                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6617                 ret = -EINVAL;
6618                 break;
6619         }
6620
6621         return ret;
6622 }
6623
6624 /**
6625  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6626  * @dev: pointer to rte_eth_dev structure
6627  * @filter_op:operation will be taken.
6628  * @arg: a pointer to specific structure corresponding to the filter_op
6629  */
6630 static int
6631 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6632                                   enum rte_filter_op filter_op,
6633                                   void *arg)
6634 {
6635         int ret = 0;
6636
6637         if (filter_op == RTE_ETH_FILTER_NOP)
6638                 return 0;
6639
6640         if (arg == NULL) {
6641                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6642                             filter_op);
6643                 return -EINVAL;
6644         }
6645
6646         switch (filter_op) {
6647         case RTE_ETH_FILTER_ADD:
6648                 ret = ixgbe_dev_l2_tunnel_filter_add
6649                         (dev,
6650                          (struct rte_eth_l2_tunnel_conf *)arg);
6651                 break;
6652         case RTE_ETH_FILTER_DELETE:
6653                 ret = ixgbe_dev_l2_tunnel_filter_del
6654                         (dev,
6655                          (struct rte_eth_l2_tunnel_conf *)arg);
6656                 break;
6657         default:
6658                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6659                 ret = -EINVAL;
6660                 break;
6661         }
6662         return ret;
6663 }
6664
6665 static int
6666 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6667 {
6668         int ret = 0;
6669         uint32_t ctrl;
6670         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6671
6672         if (hw->mac.type != ixgbe_mac_X550 &&
6673             hw->mac.type != ixgbe_mac_X550EM_x) {
6674                 return -ENOTSUP;
6675         }
6676
6677         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6678         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6679         if (en)
6680                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6681         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6682
6683         return ret;
6684 }
6685
6686 /* Enable l2 tunnel forwarding */
6687 static int
6688 ixgbe_dev_l2_tunnel_forwarding_enable
6689         (struct rte_eth_dev *dev,
6690          enum rte_eth_tunnel_type l2_tunnel_type)
6691 {
6692         int ret = 0;
6693
6694         switch (l2_tunnel_type) {
6695         case RTE_L2_TUNNEL_TYPE_E_TAG:
6696                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6697                 break;
6698         default:
6699                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6700                 ret = -EINVAL;
6701                 break;
6702         }
6703
6704         return ret;
6705 }
6706
6707 /* Disable l2 tunnel forwarding */
6708 static int
6709 ixgbe_dev_l2_tunnel_forwarding_disable
6710         (struct rte_eth_dev *dev,
6711          enum rte_eth_tunnel_type l2_tunnel_type)
6712 {
6713         int ret = 0;
6714
6715         switch (l2_tunnel_type) {
6716         case RTE_L2_TUNNEL_TYPE_E_TAG:
6717                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6718                 break;
6719         default:
6720                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6721                 ret = -EINVAL;
6722                 break;
6723         }
6724
6725         return ret;
6726 }
6727
6728 static int
6729 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6730                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6731                              bool en)
6732 {
6733         int ret = 0;
6734         uint32_t vmtir, vmvir;
6735         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6736
6737         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6738                 PMD_DRV_LOG(ERR,
6739                             "VF id %u should be less than %u",
6740                             l2_tunnel->vf_id,
6741                             dev->pci_dev->max_vfs);
6742                 return -EINVAL;
6743         }
6744
6745         if (hw->mac.type != ixgbe_mac_X550 &&
6746             hw->mac.type != ixgbe_mac_X550EM_x) {
6747                 return -ENOTSUP;
6748         }
6749
6750         if (en)
6751                 vmtir = l2_tunnel->tunnel_id;
6752         else
6753                 vmtir = 0;
6754
6755         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6756
6757         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6758         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6759         if (en)
6760                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6761         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6762
6763         return ret;
6764 }
6765
6766 /* Enable l2 tunnel tag insertion */
6767 static int
6768 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6769                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6770 {
6771         int ret = 0;
6772
6773         switch (l2_tunnel->l2_tunnel_type) {
6774         case RTE_L2_TUNNEL_TYPE_E_TAG:
6775                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6776                 break;
6777         default:
6778                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6779                 ret = -EINVAL;
6780                 break;
6781         }
6782
6783         return ret;
6784 }
6785
6786 /* Disable l2 tunnel tag insertion */
6787 static int
6788 ixgbe_dev_l2_tunnel_insertion_disable
6789         (struct rte_eth_dev *dev,
6790          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6791 {
6792         int ret = 0;
6793
6794         switch (l2_tunnel->l2_tunnel_type) {
6795         case RTE_L2_TUNNEL_TYPE_E_TAG:
6796                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6797                 break;
6798         default:
6799                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6800                 ret = -EINVAL;
6801                 break;
6802         }
6803
6804         return ret;
6805 }
6806
6807 static int
6808 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6809                              bool en)
6810 {
6811         int ret = 0;
6812         uint32_t qde;
6813         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6814
6815         if (hw->mac.type != ixgbe_mac_X550 &&
6816             hw->mac.type != ixgbe_mac_X550EM_x) {
6817                 return -ENOTSUP;
6818         }
6819
6820         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6821         if (en)
6822                 qde |= IXGBE_QDE_STRIP_TAG;
6823         else
6824                 qde &= ~IXGBE_QDE_STRIP_TAG;
6825         qde &= ~IXGBE_QDE_READ;
6826         qde |= IXGBE_QDE_WRITE;
6827         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6828
6829         return ret;
6830 }
6831
6832 /* Enable l2 tunnel tag stripping */
6833 static int
6834 ixgbe_dev_l2_tunnel_stripping_enable
6835         (struct rte_eth_dev *dev,
6836          enum rte_eth_tunnel_type l2_tunnel_type)
6837 {
6838         int ret = 0;
6839
6840         switch (l2_tunnel_type) {
6841         case RTE_L2_TUNNEL_TYPE_E_TAG:
6842                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6843                 break;
6844         default:
6845                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6846                 ret = -EINVAL;
6847                 break;
6848         }
6849
6850         return ret;
6851 }
6852
6853 /* Disable l2 tunnel tag stripping */
6854 static int
6855 ixgbe_dev_l2_tunnel_stripping_disable
6856         (struct rte_eth_dev *dev,
6857          enum rte_eth_tunnel_type l2_tunnel_type)
6858 {
6859         int ret = 0;
6860
6861         switch (l2_tunnel_type) {
6862         case RTE_L2_TUNNEL_TYPE_E_TAG:
6863                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6864                 break;
6865         default:
6866                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6867                 ret = -EINVAL;
6868                 break;
6869         }
6870
6871         return ret;
6872 }
6873
6874 /* Enable/disable l2 tunnel offload functions */
6875 static int
6876 ixgbe_dev_l2_tunnel_offload_set
6877         (struct rte_eth_dev *dev,
6878          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6879          uint32_t mask,
6880          uint8_t en)
6881 {
6882         int ret = 0;
6883
6884         if (l2_tunnel == NULL)
6885                 return -EINVAL;
6886
6887         ret = -EINVAL;
6888         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6889                 if (en)
6890                         ret = ixgbe_dev_l2_tunnel_enable(
6891                                 dev,
6892                                 l2_tunnel->l2_tunnel_type);
6893                 else
6894                         ret = ixgbe_dev_l2_tunnel_disable(
6895                                 dev,
6896                                 l2_tunnel->l2_tunnel_type);
6897         }
6898
6899         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6900                 if (en)
6901                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6902                                 dev,
6903                                 l2_tunnel);
6904                 else
6905                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6906                                 dev,
6907                                 l2_tunnel);
6908         }
6909
6910         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6911                 if (en)
6912                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6913                                 dev,
6914                                 l2_tunnel->l2_tunnel_type);
6915                 else
6916                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6917                                 dev,
6918                                 l2_tunnel->l2_tunnel_type);
6919         }
6920
6921         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6922                 if (en)
6923                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6924                                 dev,
6925                                 l2_tunnel->l2_tunnel_type);
6926                 else
6927                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6928                                 dev,
6929                                 l2_tunnel->l2_tunnel_type);
6930         }
6931
6932         return ret;
6933 }
6934
6935 static int
6936 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6937                         uint16_t port)
6938 {
6939         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6940         IXGBE_WRITE_FLUSH(hw);
6941
6942         return 0;
6943 }
6944
6945 /* There's only one register for VxLAN UDP port.
6946  * So, we cannot add several ports. Will update it.
6947  */
6948 static int
6949 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6950                      uint16_t port)
6951 {
6952         if (port == 0) {
6953                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6954                 return -EINVAL;
6955         }
6956
6957         return ixgbe_update_vxlan_port(hw, port);
6958 }
6959
6960 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6961  * UDP port, it must have a value.
6962  * So, will reset it to the original value 0.
6963  */
6964 static int
6965 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6966                      uint16_t port)
6967 {
6968         uint16_t cur_port;
6969
6970         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6971
6972         if (cur_port != port) {
6973                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6974                 return -EINVAL;
6975         }
6976
6977         return ixgbe_update_vxlan_port(hw, 0);
6978 }
6979
6980 /* Add UDP tunneling port */
6981 static int
6982 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6983                               struct rte_eth_udp_tunnel *udp_tunnel)
6984 {
6985         int ret = 0;
6986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6987
6988         if (hw->mac.type != ixgbe_mac_X550 &&
6989             hw->mac.type != ixgbe_mac_X550EM_x) {
6990                 return -ENOTSUP;
6991         }
6992
6993         if (udp_tunnel == NULL)
6994                 return -EINVAL;
6995
6996         switch (udp_tunnel->prot_type) {
6997         case RTE_TUNNEL_TYPE_VXLAN:
6998                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6999                 break;
7000
7001         case RTE_TUNNEL_TYPE_GENEVE:
7002         case RTE_TUNNEL_TYPE_TEREDO:
7003                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7004                 ret = -EINVAL;
7005                 break;
7006
7007         default:
7008                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7009                 ret = -EINVAL;
7010                 break;
7011         }
7012
7013         return ret;
7014 }
7015
7016 /* Remove UDP tunneling port */
7017 static int
7018 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7019                               struct rte_eth_udp_tunnel *udp_tunnel)
7020 {
7021         int ret = 0;
7022         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7023
7024         if (hw->mac.type != ixgbe_mac_X550 &&
7025             hw->mac.type != ixgbe_mac_X550EM_x) {
7026                 return -ENOTSUP;
7027         }
7028
7029         if (udp_tunnel == NULL)
7030                 return -EINVAL;
7031
7032         switch (udp_tunnel->prot_type) {
7033         case RTE_TUNNEL_TYPE_VXLAN:
7034                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7035                 break;
7036         case RTE_TUNNEL_TYPE_GENEVE:
7037         case RTE_TUNNEL_TYPE_TEREDO:
7038                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7039                 ret = -EINVAL;
7040                 break;
7041         default:
7042                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7043                 ret = -EINVAL;
7044                 break;
7045         }
7046
7047         return ret;
7048 }
7049
7050 /* ixgbevf_update_xcast_mode - Update Multicast mode
7051  * @hw: pointer to the HW structure
7052  * @netdev: pointer to net device structure
7053  * @xcast_mode: new multicast mode
7054  *
7055  * Updates the Multicast Mode of VF.
7056  */
7057 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7058                                      int xcast_mode)
7059 {
7060         struct ixgbe_mbx_info *mbx = &hw->mbx;
7061         u32 msgbuf[2];
7062         s32 err;
7063
7064         switch (hw->api_version) {
7065         case ixgbe_mbox_api_12:
7066                 break;
7067         default:
7068                 return -EOPNOTSUPP;
7069         }
7070
7071         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7072         msgbuf[1] = xcast_mode;
7073
7074         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7075         if (err)
7076                 return err;
7077
7078         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7079         if (err)
7080                 return err;
7081
7082         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7083         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7084                 return -EPERM;
7085
7086         return 0;
7087 }
7088
7089 static void
7090 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7091 {
7092         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7093
7094         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7095 }
7096
7097 static void
7098 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7099 {
7100         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7101
7102         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7103 }
7104
7105 static struct rte_driver rte_ixgbe_driver = {
7106         .type = PMD_PDEV,
7107         .init = rte_ixgbe_pmd_init,
7108 };
7109
7110 static struct rte_driver rte_ixgbevf_driver = {
7111         .type = PMD_PDEV,
7112         .init = rte_ixgbevf_pmd_init,
7113 };
7114
7115 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7116 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);