drivers/net/ixgbe/ixgbe_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   Copyright 2014 6WIND S.A.
   6  *   All rights reserved.
   7  *
   8  *   Redistribution and use in source and binary forms, with or without
   9  *   modification, are permitted provided that the following conditions
  10  *   are met:
  11  *
  12  *     * Redistributions of source code must retain the above copyright
  13  *       notice, this list of conditions and the following disclaimer.
  14  *     * Redistributions in binary form must reproduce the above copyright
  15  *       notice, this list of conditions and the following disclaimer in
  16  *       the documentation and/or other materials provided with the
  17  *       distribution.
  18  *     * Neither the name of Intel Corporation nor the names of its
  19  *       contributors may be used to endorse or promote products derived
  20  *       from this software without specific prior written permission.
  21  *
  22  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  25  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  26  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  27  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  28  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  32  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <sys/queue.h>
  36
  37 #include <stdio.h>
  38 #include <stdlib.h>
  39 #include <string.h>
  40 #include <errno.h>
  41 #include <stdint.h>
  42 #include <stdarg.h>
  43 #include <unistd.h>
  44 #include <inttypes.h>
  45
  46 #include <rte_byteorder.h>
  47 #include <rte_common.h>
  48 #include <rte_cycles.h>
  49 #include <rte_log.h>
  50 #include <rte_debug.h>
  51 #include <rte_interrupts.h>
  52 #include <rte_pci.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_launch.h>
  56 #include <rte_eal.h>
  57 #include <rte_per_lcore.h>
  58 #include <rte_lcore.h>
  59 #include <rte_atomic.h>
  60 #include <rte_branch_prediction.h>
  61 #include <rte_ring.h>
  62 #include <rte_mempool.h>
  63 #include <rte_malloc.h>
  64 #include <rte_mbuf.h>
  65 #include <rte_ether.h>
  66 #include <rte_ethdev.h>
  67 #include <rte_prefetch.h>
  68 #include <rte_udp.h>
  69 #include <rte_tcp.h>
  70 #include <rte_sctp.h>
  71 #include <rte_string_fns.h>
  72 #include <rte_errno.h>
  73 #include <rte_ip.h>
  74
  75 #include "ixgbe_logs.h"
  76 #include "base/ixgbe_api.h"
  77 #include "base/ixgbe_vf.h"
  78 #include "ixgbe_ethdev.h"
  79 #include "base/ixgbe_dcb.h"
  80 #include "base/ixgbe_common.h"
  81 #include "ixgbe_rxtx.h"
  82
  83 /* Bit Mask to indicate what bits required for building TX context */
  84 #define IXGBE_TX_OFFLOAD_MASK (                  \
  85                 PKT_TX_VLAN_PKT |                \
  86                 PKT_TX_IP_CKSUM |                \
  87                 PKT_TX_L4_MASK |                 \
  88                 PKT_TX_TCP_SEG |                 \
  89                 PKT_TX_OUTER_IP_CKSUM)
  90
  91 static inline struct rte_mbuf *
  92 rte_rxmbuf_alloc(struct rte_mempool *mp)
  93 {
  94         struct rte_mbuf *m;
  95
  96         m = __rte_mbuf_raw_alloc(mp);
  97         __rte_mbuf_sanity_check_raw(m, 0);
  98         return m;
  99 }
 100
 101
 102 #if 1
 103 #define RTE_PMD_USE_PREFETCH
 104 #endif
 105
 106 #ifdef RTE_PMD_USE_PREFETCH
 107 /*
 108  * Prefetch a cache line into all cache levels.
 109  */
 110 #define rte_ixgbe_prefetch(p)   rte_prefetch0(p)
 111 #else
 112 #define rte_ixgbe_prefetch(p)   do {} while (0)
 113 #endif
 114
 115 /*********************************************************************
 116  *
 117  *  TX functions
 118  *
 119  **********************************************************************/
 120
 121 /*
 122  * Check for descriptors with their DD bit set and free mbufs.
 123  * Return the total number of buffers freed.
 124  */
 125 static inline int __attribute__((always_inline))
 126 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
 127 {
 128         struct ixgbe_tx_entry *txep;
 129         uint32_t status;
 130         int i, nb_free = 0;
 131         struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
 132
 133         /* check DD bit on threshold descriptor */
 134         status = txq->tx_ring[txq->tx_next_dd].wb.status;
 135         if (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))
 136                 return 0;
 137
 138         /*
 139          * first buffer to free from S/W ring is at index
 140          * tx_next_dd - (tx_rs_thresh-1)
 141          */
 142         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
 143
 144         for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
 145                 /* free buffers one at a time */
 146                 m = __rte_pktmbuf_prefree_seg(txep->mbuf);
 147                 txep->mbuf = NULL;
 148
 149                 if (unlikely(m == NULL))
 150                         continue;
 151
 152                 if (nb_free >= RTE_IXGBE_TX_MAX_FREE_BUF_SZ ||
 153                     (nb_free > 0 && m->pool != free[0]->pool)) {
 154                         rte_mempool_put_bulk(free[0]->pool,
 155                                              (void **)free, nb_free);
 156                         nb_free = 0;
 157                 }
 158
 159                 free[nb_free++] = m;
 160         }
 161
 162         if (nb_free > 0)
 163                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
 164
 165         /* buffers were freed, update counters */
 166         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
 167         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
 168         if (txq->tx_next_dd >= txq->nb_tx_desc)
 169                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 170
 171         return txq->tx_rs_thresh;
 172 }
 173
 174 /* Populate 4 descriptors with data from 4 mbufs */
 175 static inline void
 176 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
 177 {
 178         uint64_t buf_dma_addr;
 179         uint32_t pkt_len;
 180         int i;
 181
 182         for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
 183                 buf_dma_addr = rte_mbuf_data_dma_addr(*pkts);
 184                 pkt_len = (*pkts)->data_len;
 185
 186                 /* write data to descriptor */
 187                 txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
 188
 189                 txdp->read.cmd_type_len =
 190                         rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
 191
 192                 txdp->read.olinfo_status =
 193                         rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 194
 195                 rte_prefetch0(&(*pkts)->pool);
 196         }
 197 }
 198
 199 /* Populate 1 descriptor with data from 1 mbuf */
 200 static inline void
 201 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
 202 {
 203         uint64_t buf_dma_addr;
 204         uint32_t pkt_len;
 205
 206         buf_dma_addr = rte_mbuf_data_dma_addr(*pkts);
 207         pkt_len = (*pkts)->data_len;
 208
 209         /* write data to descriptor */
 210         txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
 211         txdp->read.cmd_type_len =
 212                         rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
 213         txdp->read.olinfo_status =
 214                         rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 215         rte_prefetch0(&(*pkts)->pool);
 216 }
 217
 218 /*
 219  * Fill H/W descriptor ring with mbuf data.
 220  * Copy mbuf pointers to the S/W ring.
 221  */
 222 static inline void
 223 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
 224                       uint16_t nb_pkts)
 225 {
 226         volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
 227         struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
 228         const int N_PER_LOOP = 4;
 229         const int N_PER_LOOP_MASK = N_PER_LOOP-1;
 230         int mainpart, leftover;
 231         int i, j;
 232
 233         /*
 234          * Process most of the packets in chunks of N pkts.  Any
 235          * leftover packets will get processed one at a time.
 236          */
 237         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
 238         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
 239         for (i = 0; i < mainpart; i += N_PER_LOOP) {
 240                 /* Copy N mbuf pointers to the S/W ring */
 241                 for (j = 0; j < N_PER_LOOP; ++j) {
 242                         (txep + i + j)->mbuf = *(pkts + i + j);
 243                 }
 244                 tx4(txdp + i, pkts + i);
 245         }
 246
 247         if (unlikely(leftover > 0)) {
 248                 for (i = 0; i < leftover; ++i) {
 249                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
 250                         tx1(txdp + mainpart + i, pkts + mainpart + i);
 251                 }
 252         }
 253 }
 254
 255 static inline uint16_t
 256 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 257              uint16_t nb_pkts)
 258 {
 259         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 260         volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
 261         uint16_t n = 0;
 262
 263         /*
 264          * Begin scanning the H/W ring for done descriptors when the
 265          * number of available descriptors drops below tx_free_thresh.  For
 266          * each done descriptor, free the associated buffer.
 267          */
 268         if (txq->nb_tx_free < txq->tx_free_thresh)
 269                 ixgbe_tx_free_bufs(txq);
 270
 271         /* Only use descriptors that are available */
 272         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 273         if (unlikely(nb_pkts == 0))
 274                 return 0;
 275
 276         /* Use exactly nb_pkts descriptors */
 277         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 278
 279         /*
 280          * At this point, we know there are enough descriptors in the
 281          * ring to transmit all the packets.  This assumes that each
 282          * mbuf contains a single segment, and that no new offloads
 283          * are expected, which would require a new context descriptor.
 284          */
 285
 286         /*
 287          * See if we're going to wrap-around. If so, handle the top
 288          * of the descriptor ring first, then do the bottom.  If not,
 289          * the processing looks just like the "bottom" part anyway...
 290          */
 291         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
 292                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
 293                 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
 294
 295                 /*
 296                  * We know that the last descriptor in the ring will need to
 297                  * have its RS bit set because tx_rs_thresh has to be
 298                  * a divisor of the ring size
 299                  */
 300                 tx_r[txq->tx_next_rs].read.cmd_type_len |=
 301                         rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
 302                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 303
 304                 txq->tx_tail = 0;
 305         }
 306
 307         /* Fill H/W descriptor ring with mbuf data */
 308         ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
 309         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
 310
 311         /*
 312          * Determine if RS bit should be set
 313          * This is what we actually want:
 314          *   if ((txq->tx_tail - 1) >= txq->tx_next_rs)
 315          * but instead of subtracting 1 and doing >=, we can just do
 316          * greater than without subtracting.
 317          */
 318         if (txq->tx_tail > txq->tx_next_rs) {
 319                 tx_r[txq->tx_next_rs].read.cmd_type_len |=
 320                         rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
 321                 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
 322                                                 txq->tx_rs_thresh);
 323                 if (txq->tx_next_rs >= txq->nb_tx_desc)
 324                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 325         }
 326
 327         /*
 328          * Check for wrap-around. This would only happen if we used
 329          * up to the last descriptor in the ring, no more, no less.
 330          */
 331         if (txq->tx_tail >= txq->nb_tx_desc)
 332                 txq->tx_tail = 0;
 333
 334         /* update tail pointer */
 335         rte_wmb();
 336         IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
 337
 338         return nb_pkts;
 339 }
 340
 341 uint16_t
 342 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
 343                        uint16_t nb_pkts)
 344 {
 345         uint16_t nb_tx;
 346
 347         /* Try to transmit at least chunks of TX_MAX_BURST pkts */
 348         if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
 349                 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
 350
 351         /* transmit more than the max burst, in chunks of TX_MAX_BURST */
 352         nb_tx = 0;
 353         while (nb_pkts) {
 354                 uint16_t ret, n;
 355
 356                 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
 357                 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
 358                 nb_tx = (uint16_t)(nb_tx + ret);
 359                 nb_pkts = (uint16_t)(nb_pkts - ret);
 360                 if (ret < n)
 361                         break;
 362         }
 363
 364         return nb_tx;
 365 }
 366
 367 static inline void
 368 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
 369                 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
 370                 uint64_t ol_flags, union ixgbe_tx_offload tx_offload)
 371 {
 372         uint32_t type_tucmd_mlhl;
 373         uint32_t mss_l4len_idx = 0;
 374         uint32_t ctx_idx;
 375         uint32_t vlan_macip_lens;
 376         union ixgbe_tx_offload tx_offload_mask;
 377         uint32_t seqnum_seed = 0;
 378
 379         ctx_idx = txq->ctx_curr;
 380         tx_offload_mask.data[0] = 0;
 381         tx_offload_mask.data[1] = 0;
 382         type_tucmd_mlhl = 0;
 383
 384         /* Specify which HW CTX to upload. */
 385         mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
 386
 387         if (ol_flags & PKT_TX_VLAN_PKT) {
 388                 tx_offload_mask.vlan_tci |= ~0;
 389         }
 390
 391         /* check if TCP segmentation required for this packet */
 392         if (ol_flags & PKT_TX_TCP_SEG) {
 393                 /* implies IP cksum in IPv4 */
 394                 if (ol_flags & PKT_TX_IP_CKSUM)
 395                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
 396                                 IXGBE_ADVTXD_TUCMD_L4T_TCP |
 397                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 398                 else
 399                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
 400                                 IXGBE_ADVTXD_TUCMD_L4T_TCP |
 401                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 402
 403                 tx_offload_mask.l2_len |= ~0;
 404                 tx_offload_mask.l3_len |= ~0;
 405                 tx_offload_mask.l4_len |= ~0;
 406                 tx_offload_mask.tso_segsz |= ~0;
 407                 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
 408                 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
 409         } else { /* no TSO, check if hardware checksum is needed */
 410                 if (ol_flags & PKT_TX_IP_CKSUM) {
 411                         type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
 412                         tx_offload_mask.l2_len |= ~0;
 413                         tx_offload_mask.l3_len |= ~0;
 414                 }
 415
 416                 switch (ol_flags & PKT_TX_L4_MASK) {
 417                 case PKT_TX_UDP_CKSUM:
 418                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
 419                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 420                         mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 421                         tx_offload_mask.l2_len |= ~0;
 422                         tx_offload_mask.l3_len |= ~0;
 423                         break;
 424                 case PKT_TX_TCP_CKSUM:
 425                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
 426                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 427                         mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 428                         tx_offload_mask.l2_len |= ~0;
 429                         tx_offload_mask.l3_len |= ~0;
 430                         break;
 431                 case PKT_TX_SCTP_CKSUM:
 432                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
 433                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 434                         mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
 435                         tx_offload_mask.l2_len |= ~0;
 436                         tx_offload_mask.l3_len |= ~0;
 437                         break;
 438                 default:
 439                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
 440                                 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
 441                         break;
 442                 }
 443         }
 444
 445         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 446                 tx_offload_mask.outer_l2_len |= ~0;
 447                 tx_offload_mask.outer_l3_len |= ~0;
 448                 tx_offload_mask.l2_len |= ~0;
 449                 seqnum_seed |= tx_offload.outer_l3_len
 450                                << IXGBE_ADVTXD_OUTER_IPLEN;
 451                 seqnum_seed |= tx_offload.l2_len
 452                                << IXGBE_ADVTXD_TUNNEL_LEN;
 453         }
 454
 455         txq->ctx_cache[ctx_idx].flags = ol_flags;
 456         txq->ctx_cache[ctx_idx].tx_offload.data[0]  =
 457                 tx_offload_mask.data[0] & tx_offload.data[0];
 458         txq->ctx_cache[ctx_idx].tx_offload.data[1]  =
 459                 tx_offload_mask.data[1] & tx_offload.data[1];
 460         txq->ctx_cache[ctx_idx].tx_offload_mask    = tx_offload_mask;
 461
 462         ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
 463         vlan_macip_lens = tx_offload.l3_len;
 464         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 465                 vlan_macip_lens |= (tx_offload.outer_l2_len <<
 466                                     IXGBE_ADVTXD_MACLEN_SHIFT);
 467         else
 468                 vlan_macip_lens |= (tx_offload.l2_len <<
 469                                     IXGBE_ADVTXD_MACLEN_SHIFT);
 470         vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
 471         ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
 472         ctx_txd->mss_l4len_idx   = rte_cpu_to_le_32(mss_l4len_idx);
 473         ctx_txd->seqnum_seed     = seqnum_seed;
 474 }
 475
 476 /*
 477  * Check which hardware context can be used. Use the existing match
 478  * or create a new context descriptor.
 479  */
 480 static inline uint32_t
 481 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
 482                    union ixgbe_tx_offload tx_offload)
 483 {
 484         /* If match with the current used context */
 485         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 486                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
 487                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
 488                      & tx_offload.data[0])) &&
 489                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
 490                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
 491                      & tx_offload.data[1]))))
 492                 return txq->ctx_curr;
 493
 494         /* What if match with the next context  */
 495         txq->ctx_curr ^= 1;
 496         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 497                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] ==
 498                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0]
 499                      & tx_offload.data[0])) &&
 500                    (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] ==
 501                     (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1]
 502                      & tx_offload.data[1]))))
 503                 return txq->ctx_curr;
 504
 505         /* Mismatch, use the previous context */
 506         return IXGBE_CTX_NUM;
 507 }
 508
 509 static inline uint32_t
 510 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
 511 {
 512         uint32_t tmp = 0;
 513
 514         if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
 515                 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
 516         if (ol_flags & PKT_TX_IP_CKSUM)
 517                 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
 518         if (ol_flags & PKT_TX_TCP_SEG)
 519                 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
 520         return tmp;
 521 }
 522
 523 static inline uint32_t
 524 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
 525 {
 526         uint32_t cmdtype = 0;
 527
 528         if (ol_flags & PKT_TX_VLAN_PKT)
 529                 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
 530         if (ol_flags & PKT_TX_TCP_SEG)
 531                 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
 532         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 533                 cmdtype |= (1 << IXGBE_ADVTXD_OUTERIPCS_SHIFT);
 534         return cmdtype;
 535 }
 536
 537 /* Default RS bit threshold values */
 538 #ifndef DEFAULT_TX_RS_THRESH
 539 #define DEFAULT_TX_RS_THRESH   32
 540 #endif
 541 #ifndef DEFAULT_TX_FREE_THRESH
 542 #define DEFAULT_TX_FREE_THRESH 32
 543 #endif
 544
 545 /* Reset transmit descriptors after they have been used */
 546 static inline int
 547 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
 548 {
 549         struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
 550         volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
 551         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 552         uint16_t nb_tx_desc = txq->nb_tx_desc;
 553         uint16_t desc_to_clean_to;
 554         uint16_t nb_tx_to_clean;
 555         uint32_t status;
 556
 557         /* Determine the last descriptor needing to be cleaned */
 558         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 559         if (desc_to_clean_to >= nb_tx_desc)
 560                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 561
 562         /* Check to make sure the last descriptor to clean is done */
 563         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 564         status = txr[desc_to_clean_to].wb.status;
 565         if (!(status & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD))) {
 566                 PMD_TX_FREE_LOG(DEBUG,
 567                                 "TX descriptor %4u is not done"
 568                                 "(port=%d queue=%d)",
 569                                 desc_to_clean_to,
 570                                 txq->port_id, txq->queue_id);
 571                 /* Failed to clean any descriptors, better luck next time */
 572                 return -(1);
 573         }
 574
 575         /* Figure out how many descriptors will be cleaned */
 576         if (last_desc_cleaned > desc_to_clean_to)
 577                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 578                                                         desc_to_clean_to);
 579         else
 580                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 581                                                 last_desc_cleaned);
 582
 583         PMD_TX_FREE_LOG(DEBUG,
 584                         "Cleaning %4u TX descriptors: %4u to %4u "
 585                         "(port=%d queue=%d)",
 586                         nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
 587                         txq->port_id, txq->queue_id);
 588
 589         /*
 590          * The last descriptor to clean is done, so that means all the
 591          * descriptors from the last descriptor that was cleaned
 592          * up to the last descriptor with the RS bit set
 593          * are done. Only reset the threshold descriptor.
 594          */
 595         txr[desc_to_clean_to].wb.status = 0;
 596
 597         /* Update the txq to reflect the last descriptor that was cleaned */
 598         txq->last_desc_cleaned = desc_to_clean_to;
 599         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 600
 601         /* No Error */
 602         return 0;
 603 }
 604
 605 uint16_t
 606 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 607                 uint16_t nb_pkts)
 608 {
 609         struct ixgbe_tx_queue *txq;
 610         struct ixgbe_tx_entry *sw_ring;
 611         struct ixgbe_tx_entry *txe, *txn;
 612         volatile union ixgbe_adv_tx_desc *txr;
 613         volatile union ixgbe_adv_tx_desc *txd, *txp;
 614         struct rte_mbuf     *tx_pkt;
 615         struct rte_mbuf     *m_seg;
 616         uint64_t buf_dma_addr;
 617         uint32_t olinfo_status;
 618         uint32_t cmd_type_len;
 619         uint32_t pkt_len;
 620         uint16_t slen;
 621         uint64_t ol_flags;
 622         uint16_t tx_id;
 623         uint16_t tx_last;
 624         uint16_t nb_tx;
 625         uint16_t nb_used;
 626         uint64_t tx_ol_req;
 627         uint32_t ctx = 0;
 628         uint32_t new_ctx;
 629         union ixgbe_tx_offload tx_offload;
 630
 631         tx_offload.data[0] = 0;
 632         tx_offload.data[1] = 0;
 633         txq = tx_queue;
 634         sw_ring = txq->sw_ring;
 635         txr     = txq->tx_ring;
 636         tx_id   = txq->tx_tail;
 637         txe = &sw_ring[tx_id];
 638         txp = NULL;
 639
 640         /* Determine if the descriptor ring needs to be cleaned. */
 641         if (txq->nb_tx_free < txq->tx_free_thresh)
 642                 ixgbe_xmit_cleanup(txq);
 643
 644         rte_prefetch0(&txe->mbuf->pool);
 645
 646         /* TX loop */
 647         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
 648                 new_ctx = 0;
 649                 tx_pkt = *tx_pkts++;
 650                 pkt_len = tx_pkt->pkt_len;
 651
 652                 /*
 653                  * Determine how many (if any) context descriptors
 654                  * are needed for offload functionality.
 655                  */
 656                 ol_flags = tx_pkt->ol_flags;
 657
 658                 /* If hardware offload required */
 659                 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
 660                 if (tx_ol_req) {
 661                         tx_offload.l2_len = tx_pkt->l2_len;
 662                         tx_offload.l3_len = tx_pkt->l3_len;
 663                         tx_offload.l4_len = tx_pkt->l4_len;
 664                         tx_offload.vlan_tci = tx_pkt->vlan_tci;
 665                         tx_offload.tso_segsz = tx_pkt->tso_segsz;
 666                         tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
 667                         tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
 668
 669                         /* If new context need be built or reuse the exist ctx. */
 670                         ctx = what_advctx_update(txq, tx_ol_req,
 671                                 tx_offload);
 672                         /* Only allocate context descriptor if required*/
 673                         new_ctx = (ctx == IXGBE_CTX_NUM);
 674                         ctx = txq->ctx_curr;
 675                 }
 676
 677                 /*
 678                  * Keep track of how many descriptors are used this loop
 679                  * This will always be the number of segments + the number of
 680                  * Context descriptors required to transmit the packet
 681                  */
 682                 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
 683
 684                 if (txp != NULL &&
 685                                 nb_used + txq->nb_tx_used >= txq->tx_rs_thresh)
 686                         /* set RS on the previous packet in the burst */
 687                         txp->read.cmd_type_len |=
 688                                 rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
 689
 690                 /*
 691                  * The number of descriptors that must be allocated for a
 692                  * packet is the number of segments of that packet, plus 1
 693                  * Context Descriptor for the hardware offload, if any.
 694                  * Determine the last TX descriptor to allocate in the TX ring
 695                  * for the packet, starting from the current position (tx_id)
 696                  * in the ring.
 697                  */
 698                 tx_last = (uint16_t) (tx_id + nb_used - 1);
 699
 700                 /* Circular ring */
 701                 if (tx_last >= txq->nb_tx_desc)
 702                         tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
 703
 704                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
 705                            " tx_first=%u tx_last=%u",
 706                            (unsigned) txq->port_id,
 707                            (unsigned) txq->queue_id,
 708                            (unsigned) pkt_len,
 709                            (unsigned) tx_id,
 710                            (unsigned) tx_last);
 711
 712                 /*
 713                  * Make sure there are enough TX descriptors available to
 714                  * transmit the entire packet.
 715                  * nb_used better be less than or equal to txq->tx_rs_thresh
 716                  */
 717                 if (nb_used > txq->nb_tx_free) {
 718                         PMD_TX_FREE_LOG(DEBUG,
 719                                         "Not enough free TX descriptors "
 720                                         "nb_used=%4u nb_free=%4u "
 721                                         "(port=%d queue=%d)",
 722                                         nb_used, txq->nb_tx_free,
 723                                         txq->port_id, txq->queue_id);
 724
 725                         if (ixgbe_xmit_cleanup(txq) != 0) {
 726                                 /* Could not clean any descriptors */
 727                                 if (nb_tx == 0)
 728                                         return 0;
 729                                 goto end_of_tx;
 730                         }
 731
 732                         /* nb_used better be <= txq->tx_rs_thresh */
 733                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
 734                                 PMD_TX_FREE_LOG(DEBUG,
 735                                         "The number of descriptors needed to "
 736                                         "transmit the packet exceeds the "
 737                                         "RS bit threshold. This will impact "
 738                                         "performance."
 739                                         "nb_used=%4u nb_free=%4u "
 740                                         "tx_rs_thresh=%4u. "
 741                                         "(port=%d queue=%d)",
 742                                         nb_used, txq->nb_tx_free,
 743                                         txq->tx_rs_thresh,
 744                                         txq->port_id, txq->queue_id);
 745                                 /*
 746                                  * Loop here until there are enough TX
 747                                  * descriptors or until the ring cannot be
 748                                  * cleaned.
 749                                  */
 750                                 while (nb_used > txq->nb_tx_free) {
 751                                         if (ixgbe_xmit_cleanup(txq) != 0) {
 752                                                 /*
 753                                                  * Could not clean any
 754                                                  * descriptors
 755                                                  */
 756                                                 if (nb_tx == 0)
 757                                                         return 0;
 758                                                 goto end_of_tx;
 759                                         }
 760                                 }
 761                         }
 762                 }
 763
 764                 /*
 765                  * By now there are enough free TX descriptors to transmit
 766                  * the packet.
 767                  */
 768
 769                 /*
 770                  * Set common flags of all TX Data Descriptors.
 771                  *
 772                  * The following bits must be set in all Data Descriptors:
 773                  *   - IXGBE_ADVTXD_DTYP_DATA
 774                  *   - IXGBE_ADVTXD_DCMD_DEXT
 775                  *
 776                  * The following bits must be set in the first Data Descriptor
 777                  * and are ignored in the other ones:
 778                  *   - IXGBE_ADVTXD_DCMD_IFCS
 779                  *   - IXGBE_ADVTXD_MAC_1588
 780                  *   - IXGBE_ADVTXD_DCMD_VLE
 781                  *
 782                  * The following bits must only be set in the last Data
 783                  * Descriptor:
 784                  *   - IXGBE_TXD_CMD_EOP
 785                  *
 786                  * The following bits can be set in any Data Descriptor, but
 787                  * are only set in the last Data Descriptor:
 788                  *   - IXGBE_TXD_CMD_RS
 789                  */
 790                 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
 791                         IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
 792
 793 #ifdef RTE_LIBRTE_IEEE1588
 794                 if (ol_flags & PKT_TX_IEEE1588_TMST)
 795                         cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
 796 #endif
 797
 798                 olinfo_status = 0;
 799                 if (tx_ol_req) {
 800
 801                         if (ol_flags & PKT_TX_TCP_SEG) {
 802                                 /* when TSO is on, paylen in descriptor is the
 803                                  * not the packet len but the tcp payload len */
 804                                 pkt_len -= (tx_offload.l2_len +
 805                                         tx_offload.l3_len + tx_offload.l4_len);
 806                         }
 807
 808                         /*
 809                          * Setup the TX Advanced Context Descriptor if required
 810                          */
 811                         if (new_ctx) {
 812                                 volatile struct ixgbe_adv_tx_context_desc *
 813                                     ctx_txd;
 814
 815                                 ctx_txd = (volatile struct
 816                                     ixgbe_adv_tx_context_desc *)
 817                                     &txr[tx_id];
 818
 819                                 txn = &sw_ring[txe->next_id];
 820                                 rte_prefetch0(&txn->mbuf->pool);
 821
 822                                 if (txe->mbuf != NULL) {
 823                                         rte_pktmbuf_free_seg(txe->mbuf);
 824                                         txe->mbuf = NULL;
 825                                 }
 826
 827                                 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
 828                                         tx_offload);
 829
 830                                 txe->last_id = tx_last;
 831                                 tx_id = txe->next_id;
 832                                 txe = txn;
 833                         }
 834
 835                         /*
 836                          * Setup the TX Advanced Data Descriptor,
 837                          * This path will go through
 838                          * whatever new/reuse the context descriptor
 839                          */
 840                         cmd_type_len  |= tx_desc_ol_flags_to_cmdtype(ol_flags);
 841                         olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
 842                         olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
 843                 }
 844
 845                 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
 846
 847                 m_seg = tx_pkt;
 848                 do {
 849                         txd = &txr[tx_id];
 850                         txn = &sw_ring[txe->next_id];
 851                         rte_prefetch0(&txn->mbuf->pool);
 852
 853                         if (txe->mbuf != NULL)
 854                                 rte_pktmbuf_free_seg(txe->mbuf);
 855                         txe->mbuf = m_seg;
 856
 857                         /*
 858                          * Set up Transmit Data Descriptor.
 859                          */
 860                         slen = m_seg->data_len;
 861                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
 862                         txd->read.buffer_addr =
 863                                 rte_cpu_to_le_64(buf_dma_addr);
 864                         txd->read.cmd_type_len =
 865                                 rte_cpu_to_le_32(cmd_type_len | slen);
 866                         txd->read.olinfo_status =
 867                                 rte_cpu_to_le_32(olinfo_status);
 868                         txe->last_id = tx_last;
 869                         tx_id = txe->next_id;
 870                         txe = txn;
 871                         m_seg = m_seg->next;
 872                 } while (m_seg != NULL);
 873
 874                 /*
 875                  * The last packet data descriptor needs End Of Packet (EOP)
 876                  */
 877                 cmd_type_len |= IXGBE_TXD_CMD_EOP;
 878                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
 879                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
 880
 881                 /* Set RS bit only on threshold packets' last descriptor */
 882                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
 883                         PMD_TX_FREE_LOG(DEBUG,
 884                                         "Setting RS bit on TXD id="
 885                                         "%4u (port=%d queue=%d)",
 886                                         tx_last, txq->port_id, txq->queue_id);
 887
 888                         cmd_type_len |= IXGBE_TXD_CMD_RS;
 889
 890                         /* Update txq RS bit counters */
 891                         txq->nb_tx_used = 0;
 892                         txp = NULL;
 893                 } else
 894                         txp = txd;
 895
 896                 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
 897         }
 898
 899 end_of_tx:
 900         /* set RS on last packet in the burst */
 901         if (txp != NULL)
 902                 txp->read.cmd_type_len |= rte_cpu_to_le_32(IXGBE_TXD_CMD_RS);
 903
 904         rte_wmb();
 905
 906         /*
 907          * Set the Transmit Descriptor Tail (TDT)
 908          */
 909         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
 910                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
 911                    (unsigned) tx_id, (unsigned) nb_tx);
 912         IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
 913         txq->tx_tail = tx_id;
 914
 915         return nb_tx;
 916 }
 917
 918 /*********************************************************************
 919  *
 920  *  RX functions
 921  *
 922  **********************************************************************/
 923 #define IXGBE_PACKET_TYPE_IPV4              0X01
 924 #define IXGBE_PACKET_TYPE_IPV4_TCP          0X11
 925 #define IXGBE_PACKET_TYPE_IPV4_UDP          0X21
 926 #define IXGBE_PACKET_TYPE_IPV4_SCTP         0X41
 927 #define IXGBE_PACKET_TYPE_IPV4_EXT          0X03
 928 #define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP     0X43
 929 #define IXGBE_PACKET_TYPE_IPV6              0X04
 930 #define IXGBE_PACKET_TYPE_IPV6_TCP          0X14
 931 #define IXGBE_PACKET_TYPE_IPV6_UDP          0X24
 932 #define IXGBE_PACKET_TYPE_IPV6_EXT          0X0C
 933 #define IXGBE_PACKET_TYPE_IPV6_EXT_TCP      0X1C
 934 #define IXGBE_PACKET_TYPE_IPV6_EXT_UDP      0X2C
 935 #define IXGBE_PACKET_TYPE_IPV4_IPV6         0X05
 936 #define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP     0X15
 937 #define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP     0X25
 938 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT     0X0D
 939 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D
 940 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D
 941
 942 #define IXGBE_PACKET_TYPE_NVGRE                   0X00
 943 #define IXGBE_PACKET_TYPE_NVGRE_IPV4              0X01
 944 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP          0X11
 945 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP          0X21
 946 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP         0X41
 947 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT          0X03
 948 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP     0X43
 949 #define IXGBE_PACKET_TYPE_NVGRE_IPV6              0X04
 950 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP          0X14
 951 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP          0X24
 952 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT          0X0C
 953 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP      0X1C
 954 #define IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP      0X2C
 955 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6         0X05
 956 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP     0X15
 957 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP     0X25
 958 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT     0X0D
 959 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP 0X1D
 960 #define IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP 0X2D
 961
 962 #define IXGBE_PACKET_TYPE_VXLAN                   0X80
 963 #define IXGBE_PACKET_TYPE_VXLAN_IPV4              0X81
 964 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP          0x91
 965 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP          0xA1
 966 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP         0xC1
 967 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT          0x83
 968 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP     0XC3
 969 #define IXGBE_PACKET_TYPE_VXLAN_IPV6              0X84
 970 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP          0X94
 971 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP          0XA4
 972 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT          0X8C
 973 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP      0X9C
 974 #define IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP      0XAC
 975 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6         0X85
 976 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP     0X95
 977 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP     0XA5
 978 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT     0X8D
 979 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP 0X9D
 980 #define IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP 0XAD
 981
 982 #define IXGBE_PACKET_TYPE_MAX               0X80
 983 #define IXGBE_PACKET_TYPE_TN_MAX            0X100
 984 #define IXGBE_PACKET_TYPE_SHIFT             0X04
 985
 986 /* @note: fix ixgbe_dev_supported_ptypes_get() if any change here. */
 987 static inline uint32_t
 988 ixgbe_rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint16_t ptype_mask)
 989 {
 990         /**
 991          * Use 2 different table for normal packet and tunnel packet
 992          * to save the space.
 993          */
 994         static const uint32_t
 995                 ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
 996                 [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
 997                         RTE_PTYPE_L3_IPV4,
 998                 [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
 999                         RTE_PTYPE_L3_IPV4_EXT,
1000                 [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
1001                         RTE_PTYPE_L3_IPV6,
1002                 [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1003                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1004                         RTE_PTYPE_INNER_L3_IPV6,
1005                 [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1006                         RTE_PTYPE_L3_IPV6_EXT,
1007                 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1008                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1009                         RTE_PTYPE_INNER_L3_IPV6_EXT,
1010                 [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1011                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
1012                 [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1013                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
1014                 [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1015                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1016                         RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1017                 [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1018                         RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
1019                 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1020                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1021                         RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1022                 [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1023                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
1024                 [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1025                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
1026                 [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1027                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1028                         RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1029                 [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1030                         RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
1031                 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1032                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
1033                         RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1034                 [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1035                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
1036                 [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1037                         RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
1038         };
1039
1040         static const uint32_t
1041                 ptype_table_tn[IXGBE_PACKET_TYPE_TN_MAX] __rte_cache_aligned = {
1042                 [IXGBE_PACKET_TYPE_NVGRE] = RTE_PTYPE_L2_ETHER |
1043                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1044                         RTE_PTYPE_INNER_L2_ETHER,
1045                 [IXGBE_PACKET_TYPE_NVGRE_IPV4] = RTE_PTYPE_L2_ETHER |
1046                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1047                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1048                 [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1049                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1050                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT,
1051                 [IXGBE_PACKET_TYPE_NVGRE_IPV6] = RTE_PTYPE_L2_ETHER |
1052                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1053                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6,
1054                 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1055                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1056                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1057                 [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1058                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1059                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT,
1060                 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1061                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1062                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1063                 [IXGBE_PACKET_TYPE_NVGRE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1064                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1065                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1066                         RTE_PTYPE_INNER_L4_TCP,
1067                 [IXGBE_PACKET_TYPE_NVGRE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1068                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1069                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1070                         RTE_PTYPE_INNER_L4_TCP,
1071                 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1072                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1073                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1074                 [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1075                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1076                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1077                         RTE_PTYPE_INNER_L4_TCP,
1078                 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_TCP] =
1079                         RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1080                         RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1081                         RTE_PTYPE_INNER_L3_IPV4,
1082                 [IXGBE_PACKET_TYPE_NVGRE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1083                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1084                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1085                         RTE_PTYPE_INNER_L4_UDP,
1086                 [IXGBE_PACKET_TYPE_NVGRE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1087                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1088                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6 |
1089                         RTE_PTYPE_INNER_L4_UDP,
1090                 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1091                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1092                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1093                 [IXGBE_PACKET_TYPE_NVGRE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1094                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1095                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV6_EXT |
1096                         RTE_PTYPE_INNER_L4_UDP,
1097                 [IXGBE_PACKET_TYPE_NVGRE_IPV4_IPV6_EXT_UDP] =
1098                         RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1099                         RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_INNER_L2_ETHER |
1100                         RTE_PTYPE_INNER_L3_IPV4,
1101                 [IXGBE_PACKET_TYPE_NVGRE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1102                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1103                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4 |
1104                         RTE_PTYPE_INNER_L4_SCTP,
1105                 [IXGBE_PACKET_TYPE_NVGRE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1106                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_TUNNEL_GRE |
1107                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4_EXT |
1108                         RTE_PTYPE_INNER_L4_SCTP,
1109
1110                 [IXGBE_PACKET_TYPE_VXLAN] = RTE_PTYPE_L2_ETHER |
1111                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1112                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER,
1113                 [IXGBE_PACKET_TYPE_VXLAN_IPV4] = RTE_PTYPE_L2_ETHER |
1114                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1115                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1116                         RTE_PTYPE_INNER_L3_IPV4,
1117                 [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
1118                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1119                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1120                         RTE_PTYPE_INNER_L3_IPV4_EXT,
1121                 [IXGBE_PACKET_TYPE_VXLAN_IPV6] = RTE_PTYPE_L2_ETHER |
1122                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1123                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1124                         RTE_PTYPE_INNER_L3_IPV6,
1125                 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
1126                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1127                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1128                         RTE_PTYPE_INNER_L3_IPV4,
1129                 [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1130                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1131                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1132                         RTE_PTYPE_INNER_L3_IPV6_EXT,
1133                 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
1134                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1135                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1136                         RTE_PTYPE_INNER_L3_IPV4,
1137                 [IXGBE_PACKET_TYPE_VXLAN_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
1138                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1139                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1140                         RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_TCP,
1141                 [IXGBE_PACKET_TYPE_VXLAN_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1142                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1143                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1144                         RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
1145                 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
1146                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1147                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1148                         RTE_PTYPE_INNER_L3_IPV4,
1149                 [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
1150                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1151                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1152                         RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
1153                 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_TCP] =
1154                         RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1155                         RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1156                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1157                 [IXGBE_PACKET_TYPE_VXLAN_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
1158                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1159                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1160                         RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_UDP,
1161                 [IXGBE_PACKET_TYPE_VXLAN_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1162                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1163                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1164                         RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
1165                 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
1166                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1167                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1168                         RTE_PTYPE_INNER_L3_IPV4,
1169                 [IXGBE_PACKET_TYPE_VXLAN_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
1170                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1171                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1172                         RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
1173                 [IXGBE_PACKET_TYPE_VXLAN_IPV4_IPV6_EXT_UDP] =
1174                         RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1175                         RTE_PTYPE_L4_UDP | RTE_PTYPE_TUNNEL_VXLAN |
1176                         RTE_PTYPE_INNER_L2_ETHER | RTE_PTYPE_INNER_L3_IPV4,
1177                 [IXGBE_PACKET_TYPE_VXLAN_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
1178                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1179                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1180                         RTE_PTYPE_INNER_L3_IPV4 | RTE_PTYPE_INNER_L4_SCTP,
1181                 [IXGBE_PACKET_TYPE_VXLAN_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
1182                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP |
1183                         RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_INNER_L2_ETHER |
1184                         RTE_PTYPE_INNER_L3_IPV4_EXT | RTE_PTYPE_INNER_L4_SCTP,
1185         };
1186
1187         if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1188                 return RTE_PTYPE_UNKNOWN;
1189
1190         pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) & ptype_mask;
1191
1192         /* For tunnel packet */
1193         if (pkt_info & IXGBE_PACKET_TYPE_TUNNEL_BIT) {
1194                 /* Remove the tunnel bit to save the space. */
1195                 pkt_info &= IXGBE_PACKET_TYPE_MASK_TUNNEL;
1196                 return ptype_table_tn[pkt_info];
1197         }
1198
1199         /**
1200          * For x550, if it's not tunnel,
1201          * tunnel type bit should be set to 0.
1202          * Reuse 82599's mask.
1203          */
1204         pkt_info &= IXGBE_PACKET_TYPE_MASK_82599;
1205
1206         return ptype_table[pkt_info];
1207 }
1208
1209 static inline uint64_t
1210 ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
1211 {
1212         static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
1213                 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
1214                 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
1215                 PKT_RX_RSS_HASH, 0, 0, 0,
1216                 0, 0, 0,  PKT_RX_FDIR,
1217         };
1218 #ifdef RTE_LIBRTE_IEEE1588
1219         static uint64_t ip_pkt_etqf_map[8] = {
1220                 0, 0, 0, PKT_RX_IEEE1588_PTP,
1221                 0, 0, 0, 0,
1222         };
1223
1224         if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
1225                 return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
1226                                 ip_rss_types_map[pkt_info & 0XF];
1227         else
1228                 return ip_rss_types_map[pkt_info & 0XF];
1229 #else
1230         return ip_rss_types_map[pkt_info & 0XF];
1231 #endif
1232 }
1233
1234 static inline uint64_t
1235 rx_desc_status_to_pkt_flags(uint32_t rx_status)
1236 {
1237         uint64_t pkt_flags;
1238
1239         /*
1240          * Check if VLAN present only.
1241          * Do not check whether L3/L4 rx checksum done by NIC or not,
1242          * That can be found from rte_eth_rxmode.hw_ip_checksum flag
1243          */
1244         pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ?  PKT_RX_VLAN_PKT : 0;
1245
1246 #ifdef RTE_LIBRTE_IEEE1588
1247         if (rx_status & IXGBE_RXD_STAT_TMST)
1248                 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
1249 #endif
1250         return pkt_flags;
1251 }
1252
1253 static inline uint64_t
1254 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1255 {
1256         uint64_t pkt_flags;
1257
1258         /*
1259          * Bit 31: IPE, IPv4 checksum error
1260          * Bit 30: L4I, L4I integrity error
1261          */
1262         static uint64_t error_to_pkt_flags_map[4] = {
1263                 0,  PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
1264                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1265         };
1266         pkt_flags = error_to_pkt_flags_map[(rx_status >>
1267                 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1268
1269         if ((rx_status & IXGBE_RXD_STAT_OUTERIPCS) &&
1270             (rx_status & IXGBE_RXDADV_ERR_OUTERIPER)) {
1271                 pkt_flags |= PKT_RX_EIP_CKSUM_BAD;
1272         }
1273
1274         return pkt_flags;
1275 }
1276
1277 /*
1278  * LOOK_AHEAD defines how many desc statuses to check beyond the
1279  * current descriptor.
1280  * It must be a pound define for optimal performance.
1281  * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1282  * function only works with LOOK_AHEAD=8.
1283  */
1284 #define LOOK_AHEAD 8
1285 #if (LOOK_AHEAD != 8)
1286 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1287 #endif
1288 static inline int
1289 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
1290 {
1291         volatile union ixgbe_adv_rx_desc *rxdp;
1292         struct ixgbe_rx_entry *rxep;
1293         struct rte_mbuf *mb;
1294         uint16_t pkt_len;
1295         uint64_t pkt_flags;
1296         int nb_dd;
1297         uint32_t s[LOOK_AHEAD];
1298         uint32_t pkt_info[LOOK_AHEAD];
1299         int i, j, nb_rx = 0;
1300         uint32_t status;
1301
1302         /* get references to current descriptor and S/W ring entry */
1303         rxdp = &rxq->rx_ring[rxq->rx_tail];
1304         rxep = &rxq->sw_ring[rxq->rx_tail];
1305
1306         status = rxdp->wb.upper.status_error;
1307         /* check to make sure there is at least 1 packet to receive */
1308         if (!(status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1309                 return 0;
1310
1311         /*
1312          * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1313          * reference packets that are ready to be received.
1314          */
1315         for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1316              i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD) {
1317                 /* Read desc statuses backwards to avoid race condition */
1318                 for (j = LOOK_AHEAD-1; j >= 0; --j)
1319                         s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);
1320
1321                 for (j = LOOK_AHEAD - 1; j >= 0; --j)
1322                         pkt_info[j] = rte_le_to_cpu_32(rxdp[j].wb.lower.
1323                                                        lo_dword.data);
1324
1325                 /* Compute how many status bits were set */
1326                 nb_dd = 0;
1327                 for (j = 0; j < LOOK_AHEAD; ++j)
1328                         nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
1329
1330                 nb_rx += nb_dd;
1331
1332                 /* Translate descriptor info to mbuf format */
1333                 for (j = 0; j < nb_dd; ++j) {
1334                         mb = rxep[j].mbuf;
1335                         pkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -
1336                                   rxq->crc_len;
1337                         mb->data_len = pkt_len;
1338                         mb->pkt_len = pkt_len;
1339                         mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
1340
1341                         /* convert descriptor fields to rte mbuf flags */
1342                         pkt_flags = rx_desc_status_to_pkt_flags(s[j]);
1343                         pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1344                         pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags
1345                                         ((uint16_t)pkt_info[j]);
1346                         mb->ol_flags = pkt_flags;
1347                         mb->packet_type =
1348                                 ixgbe_rxd_pkt_info_to_pkt_type
1349                                         (pkt_info[j], rxq->pkt_type_mask);
1350
1351                         if (likely(pkt_flags & PKT_RX_RSS_HASH))
1352                                 mb->hash.rss = rte_le_to_cpu_32(
1353                                     rxdp[j].wb.lower.hi_dword.rss);
1354                         else if (pkt_flags & PKT_RX_FDIR) {
1355                                 mb->hash.fdir.hash = rte_le_to_cpu_16(
1356                                     rxdp[j].wb.lower.hi_dword.csum_ip.csum) &
1357                                     IXGBE_ATR_HASH_MASK;
1358                                 mb->hash.fdir.id = rte_le_to_cpu_16(
1359                                     rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);
1360                         }
1361                 }
1362
1363                 /* Move mbuf pointers from the S/W ring to the stage */
1364                 for (j = 0; j < LOOK_AHEAD; ++j) {
1365                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1366                 }
1367
1368                 /* stop if all requested packets could not be received */
1369                 if (nb_dd != LOOK_AHEAD)
1370                         break;
1371         }
1372
1373         /* clear software ring entries so we can cleanup correctly */
1374         for (i = 0; i < nb_rx; ++i) {
1375                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1376         }
1377
1378
1379         return nb_rx;
1380 }
1381
1382 static inline int
1383 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1384 {
1385         volatile union ixgbe_adv_rx_desc *rxdp;
1386         struct ixgbe_rx_entry *rxep;
1387         struct rte_mbuf *mb;
1388         uint16_t alloc_idx;
1389         __le64 dma_addr;
1390         int diag, i;
1391
1392         /* allocate buffers in bulk directly into the S/W ring */
1393         alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1394         rxep = &rxq->sw_ring[alloc_idx];
1395         diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1396                                     rxq->rx_free_thresh);
1397         if (unlikely(diag != 0))
1398                 return -ENOMEM;
1399
1400         rxdp = &rxq->rx_ring[alloc_idx];
1401         for (i = 0; i < rxq->rx_free_thresh; ++i) {
1402                 /* populate the static rte mbuf fields */
1403                 mb = rxep[i].mbuf;
1404                 if (reset_mbuf) {
1405                         mb->next = NULL;
1406                         mb->nb_segs = 1;
1407                         mb->port = rxq->port_id;
1408                 }
1409
1410                 rte_mbuf_refcnt_set(mb, 1);
1411                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1412
1413                 /* populate the descriptors */
1414                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mb));
1415                 rxdp[i].read.hdr_addr = 0;
1416                 rxdp[i].read.pkt_addr = dma_addr;
1417         }
1418
1419         /* update state of internal queue structure */
1420         rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1421         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1422                 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1423
1424         /* no errors */
1425         return 0;
1426 }
1427
1428 static inline uint16_t
1429 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1430                          uint16_t nb_pkts)
1431 {
1432         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1433         int i;
1434
1435         /* how many packets are ready to return? */
1436         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1437
1438         /* copy mbuf pointers to the application's packet list */
1439         for (i = 0; i < nb_pkts; ++i)
1440                 rx_pkts[i] = stage[i];
1441
1442         /* update internal queue state */
1443         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1444         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1445
1446         return nb_pkts;
1447 }
1448
1449 static inline uint16_t
1450 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1451              uint16_t nb_pkts)
1452 {
1453         struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1454         uint16_t nb_rx = 0;
1455
1456         /* Any previously recv'd pkts will be returned from the Rx stage */
1457         if (rxq->rx_nb_avail)
1458                 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1459
1460         /* Scan the H/W ring for packets to receive */
1461         nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1462
1463         /* update internal queue state */
1464         rxq->rx_next_avail = 0;
1465         rxq->rx_nb_avail = nb_rx;
1466         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1467
1468         /* if required, allocate new buffers to replenish descriptors */
1469         if (rxq->rx_tail > rxq->rx_free_trigger) {
1470                 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1471
1472                 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1473                         int i, j;
1474
1475                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1476                                    "queue_id=%u", (unsigned) rxq->port_id,
1477                                    (unsigned) rxq->queue_id);
1478
1479                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1480                                 rxq->rx_free_thresh;
1481
1482                         /*
1483                          * Need to rewind any previous receives if we cannot
1484                          * allocate new buffers to replenish the old ones.
1485                          */
1486                         rxq->rx_nb_avail = 0;
1487                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1488                         for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1489                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1490
1491                         return 0;
1492                 }
1493
1494                 /* update tail pointer */
1495                 rte_wmb();
1496                 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, cur_free_trigger);
1497         }
1498
1499         if (rxq->rx_tail >= rxq->nb_rx_desc)
1500                 rxq->rx_tail = 0;
1501
1502         /* received any packets this loop? */
1503         if (rxq->rx_nb_avail)
1504                 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1505
1506         return 0;
1507 }
1508
1509 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1510 uint16_t
1511 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1512                            uint16_t nb_pkts)
1513 {
1514         uint16_t nb_rx;
1515
1516         if (unlikely(nb_pkts == 0))
1517                 return 0;
1518
1519         if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1520                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1521
1522         /* request is relatively large, chunk it up */
1523         nb_rx = 0;
1524         while (nb_pkts) {
1525                 uint16_t ret, n;
1526
1527                 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1528                 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1529                 nb_rx = (uint16_t)(nb_rx + ret);
1530                 nb_pkts = (uint16_t)(nb_pkts - ret);
1531                 if (ret < n)
1532                         break;
1533         }
1534
1535         return nb_rx;
1536 }
1537
1538 uint16_t
1539 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1540                 uint16_t nb_pkts)
1541 {
1542         struct ixgbe_rx_queue *rxq;
1543         volatile union ixgbe_adv_rx_desc *rx_ring;
1544         volatile union ixgbe_adv_rx_desc *rxdp;
1545         struct ixgbe_rx_entry *sw_ring;
1546         struct ixgbe_rx_entry *rxe;
1547         struct rte_mbuf *rxm;
1548         struct rte_mbuf *nmb;
1549         union ixgbe_adv_rx_desc rxd;
1550         uint64_t dma_addr;
1551         uint32_t staterr;
1552         uint32_t pkt_info;
1553         uint16_t pkt_len;
1554         uint16_t rx_id;
1555         uint16_t nb_rx;
1556         uint16_t nb_hold;
1557         uint64_t pkt_flags;
1558
1559         nb_rx = 0;
1560         nb_hold = 0;
1561         rxq = rx_queue;
1562         rx_id = rxq->rx_tail;
1563         rx_ring = rxq->rx_ring;
1564         sw_ring = rxq->sw_ring;
1565         while (nb_rx < nb_pkts) {
1566                 /*
1567                  * The order of operations here is important as the DD status
1568                  * bit must not be read after any other descriptor fields.
1569                  * rx_ring and rxdp are pointing to volatile data so the order
1570                  * of accesses cannot be reordered by the compiler. If they were
1571                  * not volatile, they could be reordered which could lead to
1572                  * using invalid descriptor fields when read from rxd.
1573                  */
1574                 rxdp = &rx_ring[rx_id];
1575                 staterr = rxdp->wb.upper.status_error;
1576                 if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1577                         break;
1578                 rxd = *rxdp;
1579
1580                 /*
1581                  * End of packet.
1582                  *
1583                  * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1584                  * is likely to be invalid and to be dropped by the various
1585                  * validation checks performed by the network stack.
1586                  *
1587                  * Allocate a new mbuf to replenish the RX ring descriptor.
1588                  * If the allocation fails:
1589                  *    - arrange for that RX descriptor to be the first one
1590                  *      being parsed the next time the receive function is
1591                  *      invoked [on the same queue].
1592                  *
1593                  *    - Stop parsing the RX ring and return immediately.
1594                  *
1595                  * This policy do not drop the packet received in the RX
1596                  * descriptor for which the allocation of a new mbuf failed.
1597                  * Thus, it allows that packet to be later retrieved if
1598                  * mbuf have been freed in the mean time.
1599                  * As a side effect, holding RX descriptors instead of
1600                  * systematically giving them back to the NIC may lead to
1601                  * RX ring exhaustion situations.
1602                  * However, the NIC can gracefully prevent such situations
1603                  * to happen by sending specific "back-pressure" flow control
1604                  * frames to its peer(s).
1605                  */
1606                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1607                            "ext_err_stat=0x%08x pkt_len=%u",
1608                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1609                            (unsigned) rx_id, (unsigned) staterr,
1610                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1611
1612                 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1613                 if (nmb == NULL) {
1614                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1615                                    "queue_id=%u", (unsigned) rxq->port_id,
1616                                    (unsigned) rxq->queue_id);
1617                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1618                         break;
1619                 }
1620
1621                 nb_hold++;
1622                 rxe = &sw_ring[rx_id];
1623                 rx_id++;
1624                 if (rx_id == rxq->nb_rx_desc)
1625                         rx_id = 0;
1626
1627                 /* Prefetch next mbuf while processing current one. */
1628                 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1629
1630                 /*
1631                  * When next RX descriptor is on a cache-line boundary,
1632                  * prefetch the next 4 RX descriptors and the next 8 pointers
1633                  * to mbufs.
1634                  */
1635                 if ((rx_id & 0x3) == 0) {
1636                         rte_ixgbe_prefetch(&rx_ring[rx_id]);
1637                         rte_ixgbe_prefetch(&sw_ring[rx_id]);
1638                 }
1639
1640                 rxm = rxe->mbuf;
1641                 rxe->mbuf = nmb;
1642                 dma_addr =
1643                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1644                 rxdp->read.hdr_addr = 0;
1645                 rxdp->read.pkt_addr = dma_addr;
1646
1647                 /*
1648                  * Initialize the returned mbuf.
1649                  * 1) setup generic mbuf fields:
1650                  *    - number of segments,
1651                  *    - next segment,
1652                  *    - packet length,
1653                  *    - RX port identifier.
1654                  * 2) integrate hardware offload data, if any:
1655                  *    - RSS flag & hash,
1656                  *    - IP checksum flag,
1657                  *    - VLAN TCI, if any,
1658                  *    - error flags.
1659                  */
1660                 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1661                                       rxq->crc_len);
1662                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1663                 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1664                 rxm->nb_segs = 1;
1665                 rxm->next = NULL;
1666                 rxm->pkt_len = pkt_len;
1667                 rxm->data_len = pkt_len;
1668                 rxm->port = rxq->port_id;
1669
1670                 pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1671                 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1672                 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1673
1674                 pkt_flags = rx_desc_status_to_pkt_flags(staterr);
1675                 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1676                 pkt_flags = pkt_flags |
1677                         ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1678                 rxm->ol_flags = pkt_flags;
1679                 rxm->packet_type =
1680                         ixgbe_rxd_pkt_info_to_pkt_type(pkt_info,
1681                                                        rxq->pkt_type_mask);
1682
1683                 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1684                         rxm->hash.rss = rte_le_to_cpu_32(
1685                                                 rxd.wb.lower.hi_dword.rss);
1686                 else if (pkt_flags & PKT_RX_FDIR) {
1687                         rxm->hash.fdir.hash = rte_le_to_cpu_16(
1688                                         rxd.wb.lower.hi_dword.csum_ip.csum) &
1689                                         IXGBE_ATR_HASH_MASK;
1690                         rxm->hash.fdir.id = rte_le_to_cpu_16(
1691                                         rxd.wb.lower.hi_dword.csum_ip.ip_id);
1692                 }
1693                 /*
1694                  * Store the mbuf address into the next entry of the array
1695                  * of returned packets.
1696                  */
1697                 rx_pkts[nb_rx++] = rxm;
1698         }
1699         rxq->rx_tail = rx_id;
1700
1701         /*
1702          * If the number of free RX descriptors is greater than the RX free
1703          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1704          * register.
1705          * Update the RDT with the value of the last processed RX descriptor
1706          * minus 1, to guarantee that the RDT register is never equal to the
1707          * RDH register, which creates a "full" ring situtation from the
1708          * hardware point of view...
1709          */
1710         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1711         if (nb_hold > rxq->rx_free_thresh) {
1712                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1713                            "nb_hold=%u nb_rx=%u",
1714                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1715                            (unsigned) rx_id, (unsigned) nb_hold,
1716                            (unsigned) nb_rx);
1717                 rx_id = (uint16_t) ((rx_id == 0) ?
1718                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
1719                 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1720                 nb_hold = 0;
1721         }
1722         rxq->nb_rx_hold = nb_hold;
1723         return nb_rx;
1724 }
1725
1726 /**
1727  * Detect an RSC descriptor.
1728  */
1729 static inline uint32_t
1730 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1731 {
1732         return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1733                 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1734 }
1735
1736 /**
1737  * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1738  *
1739  * Fill the following info in the HEAD buffer of the Rx cluster:
1740  *    - RX port identifier
1741  *    - hardware offload data, if any:
1742  *      - RSS flag & hash
1743  *      - IP checksum flag
1744  *      - VLAN TCI, if any
1745  *      - error flags
1746  * @head HEAD of the packet cluster
1747  * @desc HW descriptor to get data from
1748  * @rxq Pointer to the Rx queue
1749  */
1750 static inline void
1751 ixgbe_fill_cluster_head_buf(
1752         struct rte_mbuf *head,
1753         union ixgbe_adv_rx_desc *desc,
1754         struct ixgbe_rx_queue *rxq,
1755         uint32_t staterr)
1756 {
1757         uint32_t pkt_info;
1758         uint64_t pkt_flags;
1759
1760         head->port = rxq->port_id;
1761
1762         /* The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1763          * set in the pkt_flags field.
1764          */
1765         head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1766         pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1767         pkt_flags = rx_desc_status_to_pkt_flags(staterr);
1768         pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1769         pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags((uint16_t)pkt_info);
1770         head->ol_flags = pkt_flags;
1771         head->packet_type =
1772                 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info, rxq->pkt_type_mask);
1773
1774         if (likely(pkt_flags & PKT_RX_RSS_HASH))
1775                 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1776         else if (pkt_flags & PKT_RX_FDIR) {
1777                 head->hash.fdir.hash =
1778                         rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1779                                                           & IXGBE_ATR_HASH_MASK;
1780                 head->hash.fdir.id =
1781                         rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1782         }
1783 }
1784
1785 /**
1786  * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1787  *
1788  * @rx_queue Rx queue handle
1789  * @rx_pkts table of received packets
1790  * @nb_pkts size of rx_pkts table
1791  * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1792  *
1793  * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1794  * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1795  *
1796  * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1797  * 1) When non-EOP RSC completion arrives:
1798  *    a) Update the HEAD of the current RSC aggregation cluster with the new
1799  *       segment's data length.
1800  *    b) Set the "next" pointer of the current segment to point to the segment
1801  *       at the NEXTP index.
1802  *    c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
1803  *       in the sw_rsc_ring.
1804  * 2) When EOP arrives we just update the cluster's total length and offload
1805  *    flags and deliver the cluster up to the upper layers. In our case - put it
1806  *    in the rx_pkts table.
1807  *
1808  * Returns the number of received packets/clusters (according to the "bulk
1809  * receive" interface).
1810  */
1811 static inline uint16_t
1812 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
1813                     bool bulk_alloc)
1814 {
1815         struct ixgbe_rx_queue *rxq = rx_queue;
1816         volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
1817         struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
1818         struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
1819         uint16_t rx_id = rxq->rx_tail;
1820         uint16_t nb_rx = 0;
1821         uint16_t nb_hold = rxq->nb_rx_hold;
1822         uint16_t prev_id = rxq->rx_tail;
1823
1824         while (nb_rx < nb_pkts) {
1825                 bool eop;
1826                 struct ixgbe_rx_entry *rxe;
1827                 struct ixgbe_scattered_rx_entry *sc_entry;
1828                 struct ixgbe_scattered_rx_entry *next_sc_entry;
1829                 struct ixgbe_rx_entry *next_rxe = NULL;
1830                 struct rte_mbuf *first_seg;
1831                 struct rte_mbuf *rxm;
1832                 struct rte_mbuf *nmb;
1833                 union ixgbe_adv_rx_desc rxd;
1834                 uint16_t data_len;
1835                 uint16_t next_id;
1836                 volatile union ixgbe_adv_rx_desc *rxdp;
1837                 uint32_t staterr;
1838
1839 next_desc:
1840                 /*
1841                  * The code in this whole file uses the volatile pointer to
1842                  * ensure the read ordering of the status and the rest of the
1843                  * descriptor fields (on the compiler level only!!!). This is so
1844                  * UGLY - why not to just use the compiler barrier instead? DPDK
1845                  * even has the rte_compiler_barrier() for that.
1846                  *
1847                  * But most importantly this is just wrong because this doesn't
1848                  * ensure memory ordering in a general case at all. For
1849                  * instance, DPDK is supposed to work on Power CPUs where
1850                  * compiler barrier may just not be enough!
1851                  *
1852                  * I tried to write only this function properly to have a
1853                  * starting point (as a part of an LRO/RSC series) but the
1854                  * compiler cursed at me when I tried to cast away the
1855                  * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
1856                  * keeping it the way it is for now.
1857                  *
1858                  * The code in this file is broken in so many other places and
1859                  * will just not work on a big endian CPU anyway therefore the
1860                  * lines below will have to be revisited together with the rest
1861                  * of the ixgbe PMD.
1862                  *
1863                  * TODO:
1864                  *    - Get rid of "volatile" crap and let the compiler do its
1865                  *      job.
1866                  *    - Use the proper memory barrier (rte_rmb()) to ensure the
1867                  *      memory ordering below.
1868                  */
1869                 rxdp = &rx_ring[rx_id];
1870                 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
1871
1872                 if (!(staterr & IXGBE_RXDADV_STAT_DD))
1873                         break;
1874
1875                 rxd = *rxdp;
1876
1877                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1878                                   "staterr=0x%x data_len=%u",
1879                            rxq->port_id, rxq->queue_id, rx_id, staterr,
1880                            rte_le_to_cpu_16(rxd.wb.upper.length));
1881
1882                 if (!bulk_alloc) {
1883                         nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1884                         if (nmb == NULL) {
1885                                 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
1886                                                   "port_id=%u queue_id=%u",
1887                                            rxq->port_id, rxq->queue_id);
1888
1889                                 rte_eth_devices[rxq->port_id].data->
1890                                                         rx_mbuf_alloc_failed++;
1891                                 break;
1892                         }
1893                 } else if (nb_hold > rxq->rx_free_thresh) {
1894                         uint16_t next_rdt = rxq->rx_free_trigger;
1895
1896                         if (!ixgbe_rx_alloc_bufs(rxq, false)) {
1897                                 rte_wmb();
1898                                 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr,
1899                                                     next_rdt);
1900                                 nb_hold -= rxq->rx_free_thresh;
1901                         } else {
1902                                 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
1903                                                   "port_id=%u queue_id=%u",
1904                                            rxq->port_id, rxq->queue_id);
1905
1906                                 rte_eth_devices[rxq->port_id].data->
1907                                                         rx_mbuf_alloc_failed++;
1908                                 break;
1909                         }
1910                 }
1911
1912                 nb_hold++;
1913                 rxe = &sw_ring[rx_id];
1914                 eop = staterr & IXGBE_RXDADV_STAT_EOP;
1915
1916                 next_id = rx_id + 1;
1917                 if (next_id == rxq->nb_rx_desc)
1918                         next_id = 0;
1919
1920                 /* Prefetch next mbuf while processing current one. */
1921                 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
1922
1923                 /*
1924                  * When next RX descriptor is on a cache-line boundary,
1925                  * prefetch the next 4 RX descriptors and the next 4 pointers
1926                  * to mbufs.
1927                  */
1928                 if ((next_id & 0x3) == 0) {
1929                         rte_ixgbe_prefetch(&rx_ring[next_id]);
1930                         rte_ixgbe_prefetch(&sw_ring[next_id]);
1931                 }
1932
1933                 rxm = rxe->mbuf;
1934
1935                 if (!bulk_alloc) {
1936                         __le64 dma =
1937                           rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1938                         /*
1939                          * Update RX descriptor with the physical address of the
1940                          * new data buffer of the new allocated mbuf.
1941                          */
1942                         rxe->mbuf = nmb;
1943
1944                         rxm->data_off = RTE_PKTMBUF_HEADROOM;
1945                         rxdp->read.hdr_addr = 0;
1946                         rxdp->read.pkt_addr = dma;
1947                 } else
1948                         rxe->mbuf = NULL;
1949
1950                 /*
1951                  * Set data length & data buffer address of mbuf.
1952                  */
1953                 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1954                 rxm->data_len = data_len;
1955
1956                 if (!eop) {
1957                         uint16_t nextp_id;
1958                         /*
1959                          * Get next descriptor index:
1960                          *  - For RSC it's in the NEXTP field.
1961                          *  - For a scattered packet - it's just a following
1962                          *    descriptor.
1963                          */
1964                         if (ixgbe_rsc_count(&rxd))
1965                                 nextp_id =
1966                                         (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1967                                                        IXGBE_RXDADV_NEXTP_SHIFT;
1968                         else
1969                                 nextp_id = next_id;
1970
1971                         next_sc_entry = &sw_sc_ring[nextp_id];
1972                         next_rxe = &sw_ring[nextp_id];
1973                         rte_ixgbe_prefetch(next_rxe);
1974                 }
1975
1976                 sc_entry = &sw_sc_ring[rx_id];
1977                 first_seg = sc_entry->fbuf;
1978                 sc_entry->fbuf = NULL;
1979
1980                 /*
1981                  * If this is the first buffer of the received packet,
1982                  * set the pointer to the first mbuf of the packet and
1983                  * initialize its context.
1984                  * Otherwise, update the total length and the number of segments
1985                  * of the current scattered packet, and update the pointer to
1986                  * the last mbuf of the current packet.
1987                  */
1988                 if (first_seg == NULL) {
1989                         first_seg = rxm;
1990                         first_seg->pkt_len = data_len;
1991                         first_seg->nb_segs = 1;
1992                 } else {
1993                         first_seg->pkt_len += data_len;
1994                         first_seg->nb_segs++;
1995                 }
1996
1997                 prev_id = rx_id;
1998                 rx_id = next_id;
1999
2000                 /*
2001                  * If this is not the last buffer of the received packet, update
2002                  * the pointer to the first mbuf at the NEXTP entry in the
2003                  * sw_sc_ring and continue to parse the RX ring.
2004                  */
2005                 if (!eop && next_rxe) {
2006                         rxm->next = next_rxe->mbuf;
2007                         next_sc_entry->fbuf = first_seg;
2008                         goto next_desc;
2009                 }
2010
2011                 /*
2012                  * This is the last buffer of the received packet - return
2013                  * the current cluster to the user.
2014                  */
2015                 rxm->next = NULL;
2016
2017                 /* Initialize the first mbuf of the returned packet */
2018                 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq, staterr);
2019
2020                 /*
2021                  * Deal with the case, when HW CRC srip is disabled.
2022                  * That can't happen when LRO is enabled, but still could
2023                  * happen for scattered RX mode.
2024                  */
2025                 first_seg->pkt_len -= rxq->crc_len;
2026                 if (unlikely(rxm->data_len <= rxq->crc_len)) {
2027                         struct rte_mbuf *lp;
2028
2029                         for (lp = first_seg; lp->next != rxm; lp = lp->next)
2030                                 ;
2031
2032                         first_seg->nb_segs--;
2033                         lp->data_len -= rxq->crc_len - rxm->data_len;
2034                         lp->next = NULL;
2035                         rte_pktmbuf_free_seg(rxm);
2036                 } else
2037                         rxm->data_len -= rxq->crc_len;
2038
2039                 /* Prefetch data of first segment, if configured to do so. */
2040                 rte_packet_prefetch((char *)first_seg->buf_addr +
2041                         first_seg->data_off);
2042
2043                 /*
2044                  * Store the mbuf address into the next entry of the array
2045                  * of returned packets.
2046                  */
2047                 rx_pkts[nb_rx++] = first_seg;
2048         }
2049
2050         /*
2051          * Record index of the next RX descriptor to probe.
2052          */
2053         rxq->rx_tail = rx_id;
2054
2055         /*
2056          * If the number of free RX descriptors is greater than the RX free
2057          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
2058          * register.
2059          * Update the RDT with the value of the last processed RX descriptor
2060          * minus 1, to guarantee that the RDT register is never equal to the
2061          * RDH register, which creates a "full" ring situtation from the
2062          * hardware point of view...
2063          */
2064         if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
2065                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
2066                            "nb_hold=%u nb_rx=%u",
2067                            rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
2068
2069                 rte_wmb();
2070                 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, prev_id);
2071                 nb_hold = 0;
2072         }
2073
2074         rxq->nb_rx_hold = nb_hold;
2075         return nb_rx;
2076 }
2077
2078 uint16_t
2079 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2080                                  uint16_t nb_pkts)
2081 {
2082         return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
2083 }
2084
2085 uint16_t
2086 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
2087                                uint16_t nb_pkts)
2088 {
2089         return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
2090 }
2091
2092 /*********************************************************************
2093  *
2094  *  Queue management functions
2095  *
2096  **********************************************************************/
2097
2098 static void __attribute__((cold))
2099 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
2100 {
2101         unsigned i;
2102
2103         if (txq->sw_ring != NULL) {
2104                 for (i = 0; i < txq->nb_tx_desc; i++) {
2105                         if (txq->sw_ring[i].mbuf != NULL) {
2106                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2107                                 txq->sw_ring[i].mbuf = NULL;
2108                         }
2109                 }
2110         }
2111 }
2112
2113 static void __attribute__((cold))
2114 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
2115 {
2116         if (txq != NULL &&
2117             txq->sw_ring != NULL)
2118                 rte_free(txq->sw_ring);
2119 }
2120
2121 static void __attribute__((cold))
2122 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
2123 {
2124         if (txq != NULL && txq->ops != NULL) {
2125                 txq->ops->release_mbufs(txq);
2126                 txq->ops->free_swring(txq);
2127                 rte_free(txq);
2128         }
2129 }
2130
2131 void __attribute__((cold))
2132 ixgbe_dev_tx_queue_release(void *txq)
2133 {
2134         ixgbe_tx_queue_release(txq);
2135 }
2136
2137 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
2138 static void __attribute__((cold))
2139 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
2140 {
2141         static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
2142         struct ixgbe_tx_entry *txe = txq->sw_ring;
2143         uint16_t prev, i;
2144
2145         /* Zero out HW ring memory */
2146         for (i = 0; i < txq->nb_tx_desc; i++) {
2147                 txq->tx_ring[i] = zeroed_desc;
2148         }
2149
2150         /* Initialize SW ring entries */
2151         prev = (uint16_t) (txq->nb_tx_desc - 1);
2152         for (i = 0; i < txq->nb_tx_desc; i++) {
2153                 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
2154
2155                 txd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);
2156                 txe[i].mbuf = NULL;
2157                 txe[i].last_id = i;
2158                 txe[prev].next_id = i;
2159                 prev = i;
2160         }
2161
2162         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2163         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2164
2165         txq->tx_tail = 0;
2166         txq->nb_tx_used = 0;
2167         /*
2168          * Always allow 1 descriptor to be un-allocated to avoid
2169          * a H/W race condition
2170          */
2171         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2172         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2173         txq->ctx_curr = 0;
2174         memset((void *)&txq->ctx_cache, 0,
2175                 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
2176 }
2177
2178 static const struct ixgbe_txq_ops def_txq_ops = {
2179         .release_mbufs = ixgbe_tx_queue_release_mbufs,
2180         .free_swring = ixgbe_tx_free_swring,
2181         .reset = ixgbe_reset_tx_queue,
2182 };
2183
2184 /* Takes an ethdev and a queue and sets up the tx function to be used based on
2185  * the queue parameters. Used in tx_queue_setup by primary process and then
2186  * in dev_init by secondary process when attaching to an existing ethdev.
2187  */
2188 void __attribute__((cold))
2189 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
2190 {
2191         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2192         if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)
2193                         && (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2194                 PMD_INIT_LOG(DEBUG, "Using simple tx code path");
2195 #ifdef RTE_IXGBE_INC_VECTOR
2196                 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2197                                 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2198                                         ixgbe_txq_vec_setup(txq) == 0)) {
2199                         PMD_INIT_LOG(DEBUG, "Vector tx enabled.");
2200                         dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
2201                 } else
2202 #endif
2203                 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2204         } else {
2205                 PMD_INIT_LOG(DEBUG, "Using full-featured tx code path");
2206                 PMD_INIT_LOG(DEBUG,
2207                                 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
2208                                 (unsigned long)txq->txq_flags,
2209                                 (unsigned long)IXGBE_SIMPLE_FLAGS);
2210                 PMD_INIT_LOG(DEBUG,
2211                                 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
2212                                 (unsigned long)txq->tx_rs_thresh,
2213                                 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
2214                 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2215         }
2216 }
2217
2218 int __attribute__((cold))
2219 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
2220                          uint16_t queue_idx,
2221                          uint16_t nb_desc,
2222                          unsigned int socket_id,
2223                          const struct rte_eth_txconf *tx_conf)
2224 {
2225         const struct rte_memzone *tz;
2226         struct ixgbe_tx_queue *txq;
2227         struct ixgbe_hw     *hw;
2228         uint16_t tx_rs_thresh, tx_free_thresh;
2229
2230         PMD_INIT_FUNC_TRACE();
2231         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2232
2233         /*
2234          * Validate number of transmit descriptors.
2235          * It must not exceed hardware maximum, and must be multiple
2236          * of IXGBE_ALIGN.
2237          */
2238         if (nb_desc % IXGBE_TXD_ALIGN != 0 ||
2239                         (nb_desc > IXGBE_MAX_RING_DESC) ||
2240                         (nb_desc < IXGBE_MIN_RING_DESC)) {
2241                 return -EINVAL;
2242         }
2243
2244         /*
2245          * The following two parameters control the setting of the RS bit on
2246          * transmit descriptors.
2247          * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2248          * descriptors have been used.
2249          * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2250          * descriptors are used or if the number of descriptors required
2251          * to transmit a packet is greater than the number of free TX
2252          * descriptors.
2253          * The following constraints must be satisfied:
2254          *  tx_rs_thresh must be greater than 0.
2255          *  tx_rs_thresh must be less than the size of the ring minus 2.
2256          *  tx_rs_thresh must be less than or equal to tx_free_thresh.
2257          *  tx_rs_thresh must be a divisor of the ring size.
2258          *  tx_free_thresh must be greater than 0.
2259          *  tx_free_thresh must be less than the size of the ring minus 3.
2260          * One descriptor in the TX ring is used as a sentinel to avoid a
2261          * H/W race condition, hence the maximum threshold constraints.
2262          * When set to zero use default values.
2263          */
2264         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2265                         tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2266         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2267                         tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2268         if (tx_rs_thresh >= (nb_desc - 2)) {
2269                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2270                         "of TX descriptors minus 2. (tx_rs_thresh=%u "
2271                         "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2272                         (int)dev->data->port_id, (int)queue_idx);
2273                 return -(EINVAL);
2274         }
2275         if (tx_rs_thresh > DEFAULT_TX_RS_THRESH) {
2276                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less or equal than %u. "
2277                         "(tx_rs_thresh=%u port=%d queue=%d)",
2278                         DEFAULT_TX_RS_THRESH, (unsigned int)tx_rs_thresh,
2279                         (int)dev->data->port_id, (int)queue_idx);
2280                 return -(EINVAL);
2281         }
2282         if (tx_free_thresh >= (nb_desc - 3)) {
2283                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2284                              "tx_free_thresh must be less than the number of "
2285                              "TX descriptors minus 3. (tx_free_thresh=%u "
2286                              "port=%d queue=%d)",
2287                              (unsigned int)tx_free_thresh,
2288                              (int)dev->data->port_id, (int)queue_idx);
2289                 return -(EINVAL);
2290         }
2291         if (tx_rs_thresh > tx_free_thresh) {
2292                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2293                              "tx_free_thresh. (tx_free_thresh=%u "
2294                              "tx_rs_thresh=%u port=%d queue=%d)",
2295                              (unsigned int)tx_free_thresh,
2296                              (unsigned int)tx_rs_thresh,
2297                              (int)dev->data->port_id,
2298                              (int)queue_idx);
2299                 return -(EINVAL);
2300         }
2301         if ((nb_desc % tx_rs_thresh) != 0) {
2302                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2303                              "number of TX descriptors. (tx_rs_thresh=%u "
2304                              "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2305                              (int)dev->data->port_id, (int)queue_idx);
2306                 return -(EINVAL);
2307         }
2308
2309         /*
2310          * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2311          * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2312          * by the NIC and all descriptors are written back after the NIC
2313          * accumulates WTHRESH descriptors.
2314          */
2315         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2316                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2317                              "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2318                              "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2319                              (int)dev->data->port_id, (int)queue_idx);
2320                 return -(EINVAL);
2321         }
2322
2323         /* Free memory prior to re-allocation if needed... */
2324         if (dev->data->tx_queues[queue_idx] != NULL) {
2325                 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2326                 dev->data->tx_queues[queue_idx] = NULL;
2327         }
2328
2329         /* First allocate the tx queue data structure */
2330         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2331                                  RTE_CACHE_LINE_SIZE, socket_id);
2332         if (txq == NULL)
2333                 return -ENOMEM;
2334
2335         /*
2336          * Allocate TX ring hardware descriptors. A memzone large enough to
2337          * handle the maximum ring size is allocated in order to allow for
2338          * resizing in later calls to the queue setup function.
2339          */
2340         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2341                         sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2342                         IXGBE_ALIGN, socket_id);
2343         if (tz == NULL) {
2344                 ixgbe_tx_queue_release(txq);
2345                 return -ENOMEM;
2346         }
2347
2348         txq->nb_tx_desc = nb_desc;
2349         txq->tx_rs_thresh = tx_rs_thresh;
2350         txq->tx_free_thresh = tx_free_thresh;
2351         txq->pthresh = tx_conf->tx_thresh.pthresh;
2352         txq->hthresh = tx_conf->tx_thresh.hthresh;
2353         txq->wthresh = tx_conf->tx_thresh.wthresh;
2354         txq->queue_id = queue_idx;
2355         txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2356                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2357         txq->port_id = dev->data->port_id;
2358         txq->txq_flags = tx_conf->txq_flags;
2359         txq->ops = &def_txq_ops;
2360         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2361
2362         /*
2363          * Modification to set VFTDT for virtual function if vf is detected
2364          */
2365         if (hw->mac.type == ixgbe_mac_82599_vf ||
2366             hw->mac.type == ixgbe_mac_X540_vf ||
2367             hw->mac.type == ixgbe_mac_X550_vf ||
2368             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2369             hw->mac.type == ixgbe_mac_X550EM_a_vf)
2370                 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2371         else
2372                 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2373
2374         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2375         txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2376
2377         /* Allocate software ring */
2378         txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2379                                 sizeof(struct ixgbe_tx_entry) * nb_desc,
2380                                 RTE_CACHE_LINE_SIZE, socket_id);
2381         if (txq->sw_ring == NULL) {
2382                 ixgbe_tx_queue_release(txq);
2383                 return -ENOMEM;
2384         }
2385         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2386                      txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2387
2388         /* set up vector or scalar TX function as appropriate */
2389         ixgbe_set_tx_function(dev, txq);
2390
2391         txq->ops->reset(txq);
2392
2393         dev->data->tx_queues[queue_idx] = txq;
2394
2395
2396         return 0;
2397 }
2398
2399 /**
2400  * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2401  *
2402  * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2403  * in the sw_rsc_ring is not set to NULL but rather points to the next
2404  * mbuf of this RSC aggregation (that has not been completed yet and still
2405  * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2406  * will just free first "nb_segs" segments of the cluster explicitly by calling
2407  * an rte_pktmbuf_free_seg().
2408  *
2409  * @m scattered cluster head
2410  */
2411 static void __attribute__((cold))
2412 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2413 {
2414         uint8_t i, nb_segs = m->nb_segs;
2415         struct rte_mbuf *next_seg;
2416
2417         for (i = 0; i < nb_segs; i++) {
2418                 next_seg = m->next;
2419                 rte_pktmbuf_free_seg(m);
2420                 m = next_seg;
2421         }
2422 }
2423
2424 static void __attribute__((cold))
2425 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2426 {
2427         unsigned i;
2428
2429 #ifdef RTE_IXGBE_INC_VECTOR
2430         /* SSE Vector driver has a different way of releasing mbufs. */
2431         if (rxq->rx_using_sse) {
2432                 ixgbe_rx_queue_release_mbufs_vec(rxq);
2433                 return;
2434         }
2435 #endif
2436
2437         if (rxq->sw_ring != NULL) {
2438                 for (i = 0; i < rxq->nb_rx_desc; i++) {
2439                         if (rxq->sw_ring[i].mbuf != NULL) {
2440                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2441                                 rxq->sw_ring[i].mbuf = NULL;
2442                         }
2443                 }
2444                 if (rxq->rx_nb_avail) {
2445                         for (i = 0; i < rxq->rx_nb_avail; ++i) {
2446                                 struct rte_mbuf *mb;
2447
2448                                 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2449                                 rte_pktmbuf_free_seg(mb);
2450                         }
2451                         rxq->rx_nb_avail = 0;
2452                 }
2453         }
2454
2455         if (rxq->sw_sc_ring)
2456                 for (i = 0; i < rxq->nb_rx_desc; i++)
2457                         if (rxq->sw_sc_ring[i].fbuf) {
2458                                 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2459                                 rxq->sw_sc_ring[i].fbuf = NULL;
2460                         }
2461 }
2462
2463 static void __attribute__((cold))
2464 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2465 {
2466         if (rxq != NULL) {
2467                 ixgbe_rx_queue_release_mbufs(rxq);
2468                 rte_free(rxq->sw_ring);
2469                 rte_free(rxq->sw_sc_ring);
2470                 rte_free(rxq);
2471         }
2472 }
2473
2474 void __attribute__((cold))
2475 ixgbe_dev_rx_queue_release(void *rxq)
2476 {
2477         ixgbe_rx_queue_release(rxq);
2478 }
2479
2480 /*
2481  * Check if Rx Burst Bulk Alloc function can be used.
2482  * Return
2483  *        0: the preconditions are satisfied and the bulk allocation function
2484  *           can be used.
2485  *  -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2486  *           function must be used.
2487  */
2488 static inline int __attribute__((cold))
2489 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2490 {
2491         int ret = 0;
2492
2493         /*
2494          * Make sure the following pre-conditions are satisfied:
2495          *   rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2496          *   rxq->rx_free_thresh < rxq->nb_rx_desc
2497          *   (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2498          *   rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2499          * Scattered packets are not supported.  This should be checked
2500          * outside of this function.
2501          */
2502         if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2503                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2504                              "rxq->rx_free_thresh=%d, "
2505                              "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2506                              rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2507                 ret = -EINVAL;
2508         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2509                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2510                              "rxq->rx_free_thresh=%d, "
2511                              "rxq->nb_rx_desc=%d",
2512                              rxq->rx_free_thresh, rxq->nb_rx_desc);
2513                 ret = -EINVAL;
2514         } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2515                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2516                              "rxq->nb_rx_desc=%d, "
2517                              "rxq->rx_free_thresh=%d",
2518                              rxq->nb_rx_desc, rxq->rx_free_thresh);
2519                 ret = -EINVAL;
2520         } else if (!(rxq->nb_rx_desc <
2521                (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2522                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2523                              "rxq->nb_rx_desc=%d, "
2524                              "IXGBE_MAX_RING_DESC=%d, "
2525                              "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2526                              rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2527                              RTE_PMD_IXGBE_RX_MAX_BURST);
2528                 ret = -EINVAL;
2529         }
2530
2531         return ret;
2532 }
2533
2534 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2535 static void __attribute__((cold))
2536 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2537 {
2538         static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2539         unsigned i;
2540         uint16_t len = rxq->nb_rx_desc;
2541
2542         /*
2543          * By default, the Rx queue setup function allocates enough memory for
2544          * IXGBE_MAX_RING_DESC.  The Rx Burst bulk allocation function requires
2545          * extra memory at the end of the descriptor ring to be zero'd out. A
2546          * pre-condition for using the Rx burst bulk alloc function is that the
2547          * number of descriptors is less than or equal to
2548          * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2549          * constraints here to see if we need to zero out memory after the end
2550          * of the H/W descriptor ring.
2551          */
2552         if (adapter->rx_bulk_alloc_allowed)
2553                 /* zero out extra memory */
2554                 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2555
2556         /*
2557          * Zero out HW ring memory. Zero out extra memory at the end of
2558          * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2559          * reads extra memory as zeros.
2560          */
2561         for (i = 0; i < len; i++) {
2562                 rxq->rx_ring[i] = zeroed_desc;
2563         }
2564
2565         /*
2566          * initialize extra software ring entries. Space for these extra
2567          * entries is always allocated
2568          */
2569         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2570         for (i = rxq->nb_rx_desc; i < len; ++i) {
2571                 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2572         }
2573
2574         rxq->rx_nb_avail = 0;
2575         rxq->rx_next_avail = 0;
2576         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2577         rxq->rx_tail = 0;
2578         rxq->nb_rx_hold = 0;
2579         rxq->pkt_first_seg = NULL;
2580         rxq->pkt_last_seg = NULL;
2581
2582 #ifdef RTE_IXGBE_INC_VECTOR
2583         rxq->rxrearm_start = 0;
2584         rxq->rxrearm_nb = 0;
2585 #endif
2586 }
2587
2588 int __attribute__((cold))
2589 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2590                          uint16_t queue_idx,
2591                          uint16_t nb_desc,
2592                          unsigned int socket_id,
2593                          const struct rte_eth_rxconf *rx_conf,
2594                          struct rte_mempool *mp)
2595 {
2596         const struct rte_memzone *rz;
2597         struct ixgbe_rx_queue *rxq;
2598         struct ixgbe_hw     *hw;
2599         uint16_t len;
2600         struct ixgbe_adapter *adapter =
2601                 (struct ixgbe_adapter *)dev->data->dev_private;
2602
2603         PMD_INIT_FUNC_TRACE();
2604         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2605
2606         /*
2607          * Validate number of receive descriptors.
2608          * It must not exceed hardware maximum, and must be multiple
2609          * of IXGBE_ALIGN.
2610          */
2611         if (nb_desc % IXGBE_RXD_ALIGN != 0 ||
2612                         (nb_desc > IXGBE_MAX_RING_DESC) ||
2613                         (nb_desc < IXGBE_MIN_RING_DESC)) {
2614                 return -EINVAL;
2615         }
2616
2617         /* Free memory prior to re-allocation if needed... */
2618         if (dev->data->rx_queues[queue_idx] != NULL) {
2619                 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2620                 dev->data->rx_queues[queue_idx] = NULL;
2621         }
2622
2623         /* First allocate the rx queue data structure */
2624         rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2625                                  RTE_CACHE_LINE_SIZE, socket_id);
2626         if (rxq == NULL)
2627                 return -ENOMEM;
2628         rxq->mb_pool = mp;
2629         rxq->nb_rx_desc = nb_desc;
2630         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2631         rxq->queue_id = queue_idx;
2632         rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2633                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2634         rxq->port_id = dev->data->port_id;
2635         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2636                                                         0 : ETHER_CRC_LEN);
2637         rxq->drop_en = rx_conf->rx_drop_en;
2638         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2639
2640         /*
2641          * The packet type in RX descriptor is different for different NICs.
2642          * Some bits are used for x550 but reserved for other NICS.
2643          * So set different masks for different NICs.
2644          */
2645         if (hw->mac.type == ixgbe_mac_X550 ||
2646             hw->mac.type == ixgbe_mac_X550EM_x ||
2647             hw->mac.type == ixgbe_mac_X550EM_a ||
2648             hw->mac.type == ixgbe_mac_X550_vf ||
2649             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2650             hw->mac.type == ixgbe_mac_X550EM_a_vf)
2651                 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_X550;
2652         else
2653                 rxq->pkt_type_mask = IXGBE_PACKET_TYPE_MASK_82599;
2654
2655         /*
2656          * Allocate RX ring hardware descriptors. A memzone large enough to
2657          * handle the maximum ring size is allocated in order to allow for
2658          * resizing in later calls to the queue setup function.
2659          */
2660         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2661                                       RX_RING_SZ, IXGBE_ALIGN, socket_id);
2662         if (rz == NULL) {
2663                 ixgbe_rx_queue_release(rxq);
2664                 return -ENOMEM;
2665         }
2666
2667         /*
2668          * Zero init all the descriptors in the ring.
2669          */
2670         memset(rz->addr, 0, RX_RING_SZ);
2671
2672         /*
2673          * Modified to setup VFRDT for Virtual Function
2674          */
2675         if (hw->mac.type == ixgbe_mac_82599_vf ||
2676             hw->mac.type == ixgbe_mac_X540_vf ||
2677             hw->mac.type == ixgbe_mac_X550_vf ||
2678             hw->mac.type == ixgbe_mac_X550EM_x_vf ||
2679             hw->mac.type == ixgbe_mac_X550EM_a_vf) {
2680                 rxq->rdt_reg_addr =
2681                         IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2682                 rxq->rdh_reg_addr =
2683                         IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2684         } else {
2685                 rxq->rdt_reg_addr =
2686                         IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2687                 rxq->rdh_reg_addr =
2688                         IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2689         }
2690
2691         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2692         rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2693
2694         /*
2695          * Certain constraints must be met in order to use the bulk buffer
2696          * allocation Rx burst function. If any of Rx queues doesn't meet them
2697          * the feature should be disabled for the whole port.
2698          */
2699         if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2700                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
2701                                     "preconditions - canceling the feature for "
2702                                     "the whole port[%d]",
2703                              rxq->queue_id, rxq->port_id);
2704                 adapter->rx_bulk_alloc_allowed = false;
2705         }
2706
2707         /*
2708          * Allocate software ring. Allow for space at the end of the
2709          * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2710          * function does not access an invalid memory region.
2711          */
2712         len = nb_desc;
2713         if (adapter->rx_bulk_alloc_allowed)
2714                 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2715
2716         rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2717                                           sizeof(struct ixgbe_rx_entry) * len,
2718                                           RTE_CACHE_LINE_SIZE, socket_id);
2719         if (!rxq->sw_ring) {
2720                 ixgbe_rx_queue_release(rxq);
2721                 return -ENOMEM;
2722         }
2723
2724         /*
2725          * Always allocate even if it's not going to be needed in order to
2726          * simplify the code.
2727          *
2728          * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
2729          * be requested in ixgbe_dev_rx_init(), which is called later from
2730          * dev_start() flow.
2731          */
2732         rxq->sw_sc_ring =
2733                 rte_zmalloc_socket("rxq->sw_sc_ring",
2734                                    sizeof(struct ixgbe_scattered_rx_entry) * len,
2735                                    RTE_CACHE_LINE_SIZE, socket_id);
2736         if (!rxq->sw_sc_ring) {
2737                 ixgbe_rx_queue_release(rxq);
2738                 return -ENOMEM;
2739         }
2740
2741         PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
2742                             "dma_addr=0x%"PRIx64,
2743                      rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
2744                      rxq->rx_ring_phys_addr);
2745
2746         if (!rte_is_power_of_2(nb_desc)) {
2747                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
2748                                     "preconditions - canceling the feature for "
2749                                     "the whole port[%d]",
2750                              rxq->queue_id, rxq->port_id);
2751                 adapter->rx_vec_allowed = false;
2752         } else
2753                 ixgbe_rxq_vec_setup(rxq);
2754
2755         dev->data->rx_queues[queue_idx] = rxq;
2756
2757         ixgbe_reset_rx_queue(adapter, rxq);
2758
2759         return 0;
2760 }
2761
2762 uint32_t
2763 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2764 {
2765 #define IXGBE_RXQ_SCAN_INTERVAL 4
2766         volatile union ixgbe_adv_rx_desc *rxdp;
2767         struct ixgbe_rx_queue *rxq;
2768         uint32_t desc = 0;
2769
2770         if (rx_queue_id >= dev->data->nb_rx_queues) {
2771                 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2772                 return 0;
2773         }
2774
2775         rxq = dev->data->rx_queues[rx_queue_id];
2776         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2777
2778         while ((desc < rxq->nb_rx_desc) &&
2779                 (rxdp->wb.upper.status_error &
2780                         rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) {
2781                 desc += IXGBE_RXQ_SCAN_INTERVAL;
2782                 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2783                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2784                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2785                                 desc - rxq->nb_rx_desc]);
2786         }
2787
2788         return desc;
2789 }
2790
2791 int
2792 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2793 {
2794         volatile union ixgbe_adv_rx_desc *rxdp;
2795         struct ixgbe_rx_queue *rxq = rx_queue;
2796         uint32_t desc;
2797
2798         if (unlikely(offset >= rxq->nb_rx_desc))
2799                 return 0;
2800         desc = rxq->rx_tail + offset;
2801         if (desc >= rxq->nb_rx_desc)
2802                 desc -= rxq->nb_rx_desc;
2803
2804         rxdp = &rxq->rx_ring[desc];
2805         return !!(rxdp->wb.upper.status_error &
2806                         rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD));
2807 }
2808
2809 void __attribute__((cold))
2810 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2811 {
2812         unsigned i;
2813         struct ixgbe_adapter *adapter =
2814                 (struct ixgbe_adapter *)dev->data->dev_private;
2815
2816         PMD_INIT_FUNC_TRACE();
2817
2818         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2819                 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
2820
2821                 if (txq != NULL) {
2822                         txq->ops->release_mbufs(txq);
2823                         txq->ops->reset(txq);
2824                 }
2825         }
2826
2827         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2828                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
2829
2830                 if (rxq != NULL) {
2831                         ixgbe_rx_queue_release_mbufs(rxq);
2832                         ixgbe_reset_rx_queue(adapter, rxq);
2833                 }
2834         }
2835 }
2836
2837 void
2838 ixgbe_dev_free_queues(struct rte_eth_dev *dev)
2839 {
2840         unsigned i;
2841
2842         PMD_INIT_FUNC_TRACE();
2843
2844         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2845                 ixgbe_dev_rx_queue_release(dev->data->rx_queues[i]);
2846                 dev->data->rx_queues[i] = NULL;
2847         }
2848         dev->data->nb_rx_queues = 0;
2849
2850         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2851                 ixgbe_dev_tx_queue_release(dev->data->tx_queues[i]);
2852                 dev->data->tx_queues[i] = NULL;
2853         }
2854         dev->data->nb_tx_queues = 0;
2855 }
2856
2857 /*********************************************************************
2858  *
2859  *  Device RX/TX init functions
2860  *
2861  **********************************************************************/
2862
2863 /**
2864  * Receive Side Scaling (RSS)
2865  * See section 7.1.2.8 in the following document:
2866  *     "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2867  *
2868  * Principles:
2869  * The source and destination IP addresses of the IP header and the source
2870  * and destination ports of TCP/UDP headers, if any, of received packets are
2871  * hashed against a configurable random key to compute a 32-bit RSS hash result.
2872  * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2873  * 128-entry redirection table (RETA).  Each entry of the RETA provides a 3-bit
2874  * RSS output index which is used as the RX queue index where to store the
2875  * received packets.
2876  * The following output is supplied in the RX write-back descriptor:
2877  *     - 32-bit result of the Microsoft RSS hash function,
2878  *     - 4-bit RSS type field.
2879  */
2880
2881 /*
2882  * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2883  * Used as the default key.
2884  */
2885 static uint8_t rss_intel_key[40] = {
2886         0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2887         0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2888         0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2889         0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2890         0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2891 };
2892
2893 static void
2894 ixgbe_rss_disable(struct rte_eth_dev *dev)
2895 {
2896         struct ixgbe_hw *hw;
2897         uint32_t mrqc;
2898         uint32_t mrqc_reg;
2899
2900         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2901         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
2902         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
2903         mrqc &= ~IXGBE_MRQC_RSSEN;
2904         IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
2905 }
2906
2907 static void
2908 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2909 {
2910         uint8_t  *hash_key;
2911         uint32_t mrqc;
2912         uint32_t rss_key;
2913         uint64_t rss_hf;
2914         uint16_t i;
2915         uint32_t mrqc_reg;
2916         uint32_t rssrk_reg;
2917
2918         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
2919         rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
2920
2921         hash_key = rss_conf->rss_key;
2922         if (hash_key != NULL) {
2923                 /* Fill in RSS hash key */
2924                 for (i = 0; i < 10; i++) {
2925                         rss_key  = hash_key[(i * 4)];
2926                         rss_key |= hash_key[(i * 4) + 1] << 8;
2927                         rss_key |= hash_key[(i * 4) + 2] << 16;
2928                         rss_key |= hash_key[(i * 4) + 3] << 24;
2929                         IXGBE_WRITE_REG_ARRAY(hw, rssrk_reg, i, rss_key);
2930                 }
2931         }
2932
2933         /* Set configured hashing protocols in MRQC register */
2934         rss_hf = rss_conf->rss_hf;
2935         mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2936         if (rss_hf & ETH_RSS_IPV4)
2937                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2938         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2939                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2940         if (rss_hf & ETH_RSS_IPV6)
2941                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2942         if (rss_hf & ETH_RSS_IPV6_EX)
2943                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2944         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2945                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2946         if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2947                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2948         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2949                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2950         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2951                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2952         if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2953                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2954         IXGBE_WRITE_REG(hw, mrqc_reg, mrqc);
2955 }
2956
2957 int
2958 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2959                           struct rte_eth_rss_conf *rss_conf)
2960 {
2961         struct ixgbe_hw *hw;
2962         uint32_t mrqc;
2963         uint64_t rss_hf;
2964         uint32_t mrqc_reg;
2965
2966         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967
2968         if (!ixgbe_rss_update_sp(hw->mac.type)) {
2969                 PMD_DRV_LOG(ERR, "RSS hash update is not supported on this "
2970                         "NIC.");
2971                 return -ENOTSUP;
2972         }
2973         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
2974
2975         /*
2976          * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2977          *     "RSS enabling cannot be done dynamically while it must be
2978          *      preceded by a software reset"
2979          * Before changing anything, first check that the update RSS operation
2980          * does not attempt to disable RSS, if RSS was enabled at
2981          * initialization time, or does not attempt to enable RSS, if RSS was
2982          * disabled at initialization time.
2983          */
2984         rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2985         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
2986         if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2987                 if (rss_hf != 0) /* Enable RSS */
2988                         return -(EINVAL);
2989                 return 0; /* Nothing to do */
2990         }
2991         /* RSS enabled */
2992         if (rss_hf == 0) /* Disable RSS */
2993                 return -(EINVAL);
2994         ixgbe_hw_rss_hash_set(hw, rss_conf);
2995         return 0;
2996 }
2997
2998 int
2999 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
3000                             struct rte_eth_rss_conf *rss_conf)
3001 {
3002         struct ixgbe_hw *hw;
3003         uint8_t *hash_key;
3004         uint32_t mrqc;
3005         uint32_t rss_key;
3006         uint64_t rss_hf;
3007         uint16_t i;
3008         uint32_t mrqc_reg;
3009         uint32_t rssrk_reg;
3010
3011         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3012         mrqc_reg = ixgbe_mrqc_reg_get(hw->mac.type);
3013         rssrk_reg = ixgbe_rssrk_reg_get(hw->mac.type, 0);
3014         hash_key = rss_conf->rss_key;
3015         if (hash_key != NULL) {
3016                 /* Return RSS hash key */
3017                 for (i = 0; i < 10; i++) {
3018                         rss_key = IXGBE_READ_REG_ARRAY(hw, rssrk_reg, i);
3019                         hash_key[(i * 4)] = rss_key & 0x000000FF;
3020                         hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
3021                         hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
3022                         hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
3023                 }
3024         }
3025
3026         /* Get RSS functions configured in MRQC register */
3027         mrqc = IXGBE_READ_REG(hw, mrqc_reg);
3028         if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
3029                 rss_conf->rss_hf = 0;
3030                 return 0;
3031         }
3032         rss_hf = 0;
3033         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
3034                 rss_hf |= ETH_RSS_IPV4;
3035         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
3036                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
3037         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
3038                 rss_hf |= ETH_RSS_IPV6;
3039         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
3040                 rss_hf |= ETH_RSS_IPV6_EX;
3041         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
3042                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
3043         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
3044                 rss_hf |= ETH_RSS_IPV6_TCP_EX;
3045         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
3046                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
3047         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
3048                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
3049         if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
3050                 rss_hf |= ETH_RSS_IPV6_UDP_EX;
3051         rss_conf->rss_hf = rss_hf;
3052         return 0;
3053 }
3054
3055 static void
3056 ixgbe_rss_configure(struct rte_eth_dev *dev)
3057 {
3058         struct rte_eth_rss_conf rss_conf;
3059         struct ixgbe_hw *hw;
3060         uint32_t reta;
3061         uint16_t i;
3062         uint16_t j;
3063         uint16_t sp_reta_size;
3064         uint32_t reta_reg;
3065
3066         PMD_INIT_FUNC_TRACE();
3067         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068
3069         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3070
3071         /*
3072          * Fill in redirection table
3073          * The byte-swap is needed because NIC registers are in
3074          * little-endian order.
3075          */
3076         reta = 0;
3077         for (i = 0, j = 0; i < sp_reta_size; i++, j++) {
3078                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3079
3080                 if (j == dev->data->nb_rx_queues)
3081                         j = 0;
3082                 reta = (reta << 8) | j;
3083                 if ((i & 3) == 3)
3084                         IXGBE_WRITE_REG(hw, reta_reg,
3085                                         rte_bswap32(reta));
3086         }
3087
3088         /*
3089          * Configure the RSS key and the RSS protocols used to compute
3090          * the RSS hash of input packets.
3091          */
3092         rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
3093         if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
3094                 ixgbe_rss_disable(dev);
3095                 return;
3096         }
3097         if (rss_conf.rss_key == NULL)
3098                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
3099         ixgbe_hw_rss_hash_set(hw, &rss_conf);
3100 }
3101
3102 #define NUM_VFTA_REGISTERS 128
3103 #define NIC_RX_BUFFER_SIZE 0x200
3104 #define X550_RX_BUFFER_SIZE 0x180
3105
3106 static void
3107 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
3108 {
3109         struct rte_eth_vmdq_dcb_conf *cfg;
3110         struct ixgbe_hw *hw;
3111         enum rte_eth_nb_pools num_pools;
3112         uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
3113         uint16_t pbsize;
3114         uint8_t nb_tcs; /* number of traffic classes */
3115         int i;
3116
3117         PMD_INIT_FUNC_TRACE();
3118         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3119         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3120         num_pools = cfg->nb_queue_pools;
3121         /* Check we have a valid number of pools */
3122         if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
3123                 ixgbe_rss_disable(dev);
3124                 return;
3125         }
3126         /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
3127         nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
3128
3129         /*
3130          * RXPBSIZE
3131          * split rx buffer up into sections, each for 1 traffic class
3132          */
3133         switch (hw->mac.type) {
3134         case ixgbe_mac_X550:
3135         case ixgbe_mac_X550EM_x:
3136         case ixgbe_mac_X550EM_a:
3137                 pbsize = (uint16_t)(X550_RX_BUFFER_SIZE / nb_tcs);
3138                 break;
3139         default:
3140                 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3141                 break;
3142         }
3143         for (i = 0; i < nb_tcs; i++) {
3144                 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3145
3146                 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3147                 /* clear 10 bits. */
3148                 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
3149                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3150         }
3151         /* zero alloc all unused TCs */
3152         for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3153                 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
3154
3155                 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
3156                 /* clear 10 bits. */
3157                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3158         }
3159
3160         /* MRQC: enable vmdq and dcb */
3161         mrqc = (num_pools == ETH_16_POOLS) ?
3162                 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN;
3163         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3164
3165         /* PFVTCTL: turn on virtualisation and set the default pool */
3166         vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3167         if (cfg->enable_default_pool) {
3168                 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3169         } else {
3170                 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3171         }
3172
3173         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3174
3175         /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
3176         queue_mapping = 0;
3177         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
3178                 /*
3179                  * mapping is done with 3 bits per priority,
3180                  * so shift by i*3 each time
3181                  */
3182                 queue_mapping |= ((cfg->dcb_tc[i] & 0x07) << (i * 3));
3183
3184         IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
3185
3186         /* RTRPCS: DCB related */
3187         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
3188
3189         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3190         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3191         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3192         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3193
3194         /* VFTA - enable all vlan filters */
3195         for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3196                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3197         }
3198
3199         /* VFRE: pool enabling for receive - 16 or 32 */
3200         IXGBE_WRITE_REG(hw, IXGBE_VFRE(0),
3201                         num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3202
3203         /*
3204          * MPSAR - allow pools to read specific mac addresses
3205          * In this case, all pools should be able to read from mac addr 0
3206          */
3207         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
3208         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
3209
3210         /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3211         for (i = 0; i < cfg->nb_pool_maps; i++) {
3212                 /* set vlan id in VF register and set the valid bit */
3213                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
3214                                 (cfg->pool_map[i].vlan_id & 0xFFF)));
3215                 /*
3216                  * Put the allowed pools in VFB reg. As we only have 16 or 32
3217                  * pools, we only need to use the first half of the register
3218                  * i.e. bits 0-31
3219                  */
3220                 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
3221         }
3222 }
3223
3224 /**
3225  * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
3226  * @hw: pointer to hardware structure
3227  * @dcb_config: pointer to ixgbe_dcb_config structure
3228  */
3229 static void
3230 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
3231                        struct ixgbe_dcb_config *dcb_config)
3232 {
3233         uint32_t reg;
3234         uint32_t q;
3235
3236         PMD_INIT_FUNC_TRACE();
3237         if (hw->mac.type != ixgbe_mac_82598EB) {
3238                 /* Disable the Tx desc arbiter so that MTQC can be changed */
3239                 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3240                 reg |= IXGBE_RTTDCS_ARBDIS;
3241                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3242
3243                 /* Enable DCB for Tx with 8 TCs */
3244                 if (dcb_config->num_tcs.pg_tcs == 8) {
3245                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3246                 } else {
3247                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3248                 }
3249                 if (dcb_config->vt_mode)
3250                         reg |= IXGBE_MTQC_VT_ENA;
3251                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3252
3253                 /* Disable drop for all queues */
3254                 for (q = 0; q < 128; q++)
3255                         IXGBE_WRITE_REG(hw, IXGBE_QDE,
3256                                 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3257
3258                 /* Enable the Tx desc arbiter */
3259                 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3260                 reg &= ~IXGBE_RTTDCS_ARBDIS;
3261                 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3262
3263                 /* Enable Security TX Buffer IFG for DCB */
3264                 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3265                 reg |= IXGBE_SECTX_DCB;
3266                 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
3267         }
3268 }
3269
3270 /**
3271  * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
3272  * @dev: pointer to rte_eth_dev structure
3273  * @dcb_config: pointer to ixgbe_dcb_config structure
3274  */
3275 static void
3276 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
3277                         struct ixgbe_dcb_config *dcb_config)
3278 {
3279         struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3280                         &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3281         struct ixgbe_hw *hw =
3282                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3283
3284         PMD_INIT_FUNC_TRACE();
3285         if (hw->mac.type != ixgbe_mac_82598EB)
3286                 /*PF VF Transmit Enable*/
3287                 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3288                         vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3289
3290         /*Configure general DCB TX parameters*/
3291         ixgbe_dcb_tx_hw_config(hw, dcb_config);
3292 }
3293
3294 static void
3295 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3296                         struct ixgbe_dcb_config *dcb_config)
3297 {
3298         struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3299                         &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3300         struct ixgbe_dcb_tc_config *tc;
3301         uint8_t i, j;
3302
3303         /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3304         if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS) {
3305                 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3306                 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3307         } else {
3308                 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3309                 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3310         }
3311         /* User Priority to Traffic Class mapping */
3312         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3313                 j = vmdq_rx_conf->dcb_tc[i];
3314                 tc = &dcb_config->tc_config[j];
3315                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3316                                                 (uint8_t)(1 << j);
3317         }
3318 }
3319
3320 static void
3321 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3322                         struct ixgbe_dcb_config *dcb_config)
3323 {
3324         struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3325                         &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3326         struct ixgbe_dcb_tc_config *tc;
3327         uint8_t i, j;
3328
3329         /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3330         if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS) {
3331                 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3332                 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3333         } else {
3334                 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3335                 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3336         }
3337
3338         /* User Priority to Traffic Class mapping */
3339         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3340                 j = vmdq_tx_conf->dcb_tc[i];
3341                 tc = &dcb_config->tc_config[j];
3342                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3343                                                 (uint8_t)(1 << j);
3344         }
3345 }
3346
3347 static void
3348 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3349                 struct ixgbe_dcb_config *dcb_config)
3350 {
3351         struct rte_eth_dcb_rx_conf *rx_conf =
3352                         &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3353         struct ixgbe_dcb_tc_config *tc;
3354         uint8_t i, j;
3355
3356         dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3357         dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3358
3359         /* User Priority to Traffic Class mapping */
3360         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3361                 j = rx_conf->dcb_tc[i];
3362                 tc = &dcb_config->tc_config[j];
3363                 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3364                                                 (uint8_t)(1 << j);
3365         }
3366 }
3367
3368 static void
3369 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3370                 struct ixgbe_dcb_config *dcb_config)
3371 {
3372         struct rte_eth_dcb_tx_conf *tx_conf =
3373                         &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3374         struct ixgbe_dcb_tc_config *tc;
3375         uint8_t i, j;
3376
3377         dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3378         dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3379
3380         /* User Priority to Traffic Class mapping */
3381         for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3382                 j = tx_conf->dcb_tc[i];
3383                 tc = &dcb_config->tc_config[j];
3384                 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3385                                                 (uint8_t)(1 << j);
3386         }
3387 }
3388
3389 /**
3390  * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3391  * @hw: pointer to hardware structure
3392  * @dcb_config: pointer to ixgbe_dcb_config structure
3393  */
3394 static void
3395 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
3396                struct ixgbe_dcb_config *dcb_config)
3397 {
3398         uint32_t reg;
3399         uint32_t vlanctrl;
3400         uint8_t i;
3401
3402         PMD_INIT_FUNC_TRACE();
3403         /*
3404          * Disable the arbiter before changing parameters
3405          * (always enable recycle mode; WSP)
3406          */
3407         reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3408         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3409
3410         if (hw->mac.type != ixgbe_mac_82598EB) {
3411                 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3412                 if (dcb_config->num_tcs.pg_tcs == 4) {
3413                         if (dcb_config->vt_mode)
3414                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3415                                         IXGBE_MRQC_VMDQRT4TCEN;
3416                         else {
3417                                 /* no matter the mode is DCB or DCB_RSS, just
3418                                  * set the MRQE to RSSXTCEN. RSS is controlled
3419                                  * by RSS_FIELD
3420                                  */
3421                                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3422                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3423                                         IXGBE_MRQC_RTRSS4TCEN;
3424                         }
3425                 }
3426                 if (dcb_config->num_tcs.pg_tcs == 8) {
3427                         if (dcb_config->vt_mode)
3428                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3429                                         IXGBE_MRQC_VMDQRT8TCEN;
3430                         else {
3431                                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3432                                 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3433                                         IXGBE_MRQC_RTRSS8TCEN;
3434                         }
3435                 }
3436
3437                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3438         }
3439
3440         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3441         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3442         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3443         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3444
3445         /* VFTA - enable all vlan filters */
3446         for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3447                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3448         }
3449
3450         /*
3451          * Configure Rx packet plane (recycle mode; WSP) and
3452          * enable arbiter
3453          */
3454         reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3455         IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3456 }
3457
3458 static void
3459 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3460                         uint16_t *max, uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3461 {
3462         switch (hw->mac.type) {
3463         case ixgbe_mac_82598EB:
3464                 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3465                 break;
3466         case ixgbe_mac_82599EB:
3467         case ixgbe_mac_X540:
3468         case ixgbe_mac_X550:
3469         case ixgbe_mac_X550EM_x:
3470         case ixgbe_mac_X550EM_a:
3471                 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3472                                                   tsa, map);
3473                 break;
3474         default:
3475                 break;
3476         }
3477 }
3478
3479 static void
3480 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3481                             uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3482 {
3483         switch (hw->mac.type) {
3484         case ixgbe_mac_82598EB:
3485                 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, tsa);
3486                 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, tsa);
3487                 break;
3488         case ixgbe_mac_82599EB:
3489         case ixgbe_mac_X540:
3490         case ixgbe_mac_X550:
3491         case ixgbe_mac_X550EM_x:
3492         case ixgbe_mac_X550EM_a:
3493                 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, tsa);
3494                 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, tsa, map);
3495                 break;
3496         default:
3497                 break;
3498         }
3499 }
3500
3501 #define DCB_RX_CONFIG  1
3502 #define DCB_TX_CONFIG  1
3503 #define DCB_TX_PB      1024
3504 /**
3505  * ixgbe_dcb_hw_configure - Enable DCB and configure
3506  * general DCB in VT mode and non-VT mode parameters
3507  * @dev: pointer to rte_eth_dev structure
3508  * @dcb_config: pointer to ixgbe_dcb_config structure
3509  */
3510 static int
3511 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3512                         struct ixgbe_dcb_config *dcb_config)
3513 {
3514         int     ret = 0;
3515         uint8_t i, pfc_en, nb_tcs;
3516         uint16_t pbsize, rx_buffer_size;
3517         uint8_t config_dcb_rx = 0;
3518         uint8_t config_dcb_tx = 0;
3519         uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3520         uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3521         uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3522         uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3523         uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3524         struct ixgbe_dcb_tc_config *tc;
3525         uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3526         struct ixgbe_hw *hw =
3527                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3528
3529         switch (dev->data->dev_conf.rxmode.mq_mode) {
3530         case ETH_MQ_RX_VMDQ_DCB:
3531                 dcb_config->vt_mode = true;
3532                 if (hw->mac.type != ixgbe_mac_82598EB) {
3533                         config_dcb_rx = DCB_RX_CONFIG;
3534                         /*
3535                          *get dcb and VT rx configuration parameters
3536                          *from rte_eth_conf
3537                          */
3538                         ixgbe_vmdq_dcb_rx_config(dev, dcb_config);
3539                         /*Configure general VMDQ and DCB RX parameters*/
3540                         ixgbe_vmdq_dcb_configure(dev);
3541                 }
3542                 break;
3543         case ETH_MQ_RX_DCB:
3544         case ETH_MQ_RX_DCB_RSS:
3545                 dcb_config->vt_mode = false;
3546                 config_dcb_rx = DCB_RX_CONFIG;
3547                 /* Get dcb TX configuration parameters from rte_eth_conf */
3548                 ixgbe_dcb_rx_config(dev, dcb_config);
3549                 /*Configure general DCB RX parameters*/
3550                 ixgbe_dcb_rx_hw_config(hw, dcb_config);
3551                 break;
3552         default:
3553                 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3554                 break;
3555         }
3556         switch (dev->data->dev_conf.txmode.mq_mode) {
3557         case ETH_MQ_TX_VMDQ_DCB:
3558                 dcb_config->vt_mode = true;
3559                 config_dcb_tx = DCB_TX_CONFIG;
3560                 /* get DCB and VT TX configuration parameters
3561                  * from rte_eth_conf
3562                  */
3563                 ixgbe_dcb_vt_tx_config(dev, dcb_config);
3564                 /*Configure general VMDQ and DCB TX parameters*/
3565                 ixgbe_vmdq_dcb_hw_tx_config(dev, dcb_config);
3566                 break;
3567
3568         case ETH_MQ_TX_DCB:
3569                 dcb_config->vt_mode = false;
3570                 config_dcb_tx = DCB_TX_CONFIG;
3571                 /*get DCB TX configuration parameters from rte_eth_conf*/
3572                 ixgbe_dcb_tx_config(dev, dcb_config);
3573                 /*Configure general DCB TX parameters*/
3574                 ixgbe_dcb_tx_hw_config(hw, dcb_config);
3575                 break;
3576         default:
3577                 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3578                 break;
3579         }
3580
3581         nb_tcs = dcb_config->num_tcs.pfc_tcs;
3582         /* Unpack map */
3583         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3584         if (nb_tcs == ETH_4_TCS) {
3585                 /* Avoid un-configured priority mapping to TC0 */
3586                 uint8_t j = 4;
3587                 uint8_t mask = 0xFF;
3588
3589                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3590                         mask = (uint8_t)(mask & (~(1 << map[i])));
3591                 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3592                         if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3593                                 map[j++] = i;
3594                         mask >>= 1;
3595                 }
3596                 /* Re-configure 4 TCs BW */
3597                 for (i = 0; i < nb_tcs; i++) {
3598                         tc = &dcb_config->tc_config[i];
3599                         tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3600                                                 (uint8_t)(100 / nb_tcs);
3601                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3602                                                 (uint8_t)(100 / nb_tcs);
3603                 }
3604                 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3605                         tc = &dcb_config->tc_config[i];
3606                         tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3607                         tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3608                 }
3609         }
3610
3611         switch (hw->mac.type) {
3612         case ixgbe_mac_X550:
3613         case ixgbe_mac_X550EM_x:
3614         case ixgbe_mac_X550EM_a:
3615                 rx_buffer_size = X550_RX_BUFFER_SIZE;
3616                 break;
3617         default:
3618                 rx_buffer_size = NIC_RX_BUFFER_SIZE;
3619                 break;
3620         }
3621
3622         if (config_dcb_rx) {
3623                 /* Set RX buffer size */
3624                 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
3625                 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3626
3627                 for (i = 0; i < nb_tcs; i++) {
3628                         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3629                 }
3630                 /* zero alloc all unused TCs */
3631                 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3632                         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3633                 }
3634         }
3635         if (config_dcb_tx) {
3636                 /* Only support an equally distributed
3637                  *  Tx packet buffer strategy.
3638                  */
3639                 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3640                 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3641
3642                 for (i = 0; i < nb_tcs; i++) {
3643                         IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3644                         IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3645                 }
3646                 /* Clear unused TCs, if any, to zero buffer size*/
3647                 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3648                         IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3649                         IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3650                 }
3651         }
3652
3653         /*Calculates traffic class credits*/
3654         ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
3655                                 IXGBE_DCB_TX_CONFIG);
3656         ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config, max_frame,
3657                                 IXGBE_DCB_RX_CONFIG);
3658
3659         if (config_dcb_rx) {
3660                 /* Unpack CEE standard containers */
3661                 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3662                 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3663                 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3664                 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3665                 /* Configure PG(ETS) RX */
3666                 ixgbe_dcb_hw_arbite_rx_config(hw, refill, max, bwgid, tsa, map);
3667         }
3668
3669         if (config_dcb_tx) {
3670                 /* Unpack CEE standard containers */
3671                 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3672                 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3673                 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3674                 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3675                 /* Configure PG(ETS) TX */
3676                 ixgbe_dcb_hw_arbite_tx_config(hw, refill, max, bwgid, tsa, map);
3677         }
3678
3679         /*Configure queue statistics registers*/
3680         ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3681
3682         /* Check if the PFC is supported */
3683         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3684                 pbsize = (uint16_t)(rx_buffer_size / nb_tcs);
3685                 for (i = 0; i < nb_tcs; i++) {
3686                         /*
3687                         * If the TC count is 8,and the default high_water is 48,
3688                         * the low_water is 16 as default.
3689                         */
3690                         hw->fc.high_water[i] = (pbsize * 3) / 4;
3691                         hw->fc.low_water[i] = pbsize / 4;
3692                         /* Enable pfc for this TC */
3693                         tc = &dcb_config->tc_config[i];
3694                         tc->pfc = ixgbe_dcb_pfc_enabled;
3695                 }
3696                 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3697                 if (dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3698                         pfc_en &= 0x0F;
3699                 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3700         }
3701
3702         return ret;
3703 }
3704
3705 /**
3706  * ixgbe_configure_dcb - Configure DCB  Hardware
3707  * @dev: pointer to rte_eth_dev
3708  */
3709 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3710 {
3711         struct ixgbe_dcb_config *dcb_cfg =
3712                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3713         struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3714
3715         PMD_INIT_FUNC_TRACE();
3716
3717         /* check support mq_mode for DCB */
3718         if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3719             (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB) &&
3720             (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB_RSS))
3721                 return;
3722
3723         if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3724                 return;
3725
3726         /** Configure DCB hardware **/
3727         ixgbe_dcb_hw_configure(dev, dcb_cfg);
3728 }
3729
3730 /*
3731  * VMDq only support for 10 GbE NIC.
3732  */
3733 static void
3734 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3735 {
3736         struct rte_eth_vmdq_rx_conf *cfg;
3737         struct ixgbe_hw *hw;
3738         enum rte_eth_nb_pools num_pools;
3739         uint32_t mrqc, vt_ctl, vlanctrl;
3740         uint32_t vmolr = 0;
3741         int i;
3742
3743         PMD_INIT_FUNC_TRACE();
3744         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3745         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3746         num_pools = cfg->nb_queue_pools;
3747
3748         ixgbe_rss_disable(dev);
3749
3750         /* MRQC: enable vmdq */
3751         mrqc = IXGBE_MRQC_VMDQEN;
3752         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3753
3754         /* PFVTCTL: turn on virtualisation and set the default pool */
3755         vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3756         if (cfg->enable_default_pool)
3757                 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3758         else
3759                 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3760
3761         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3762
3763         for (i = 0; i < (int)num_pools; i++) {
3764                 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3765                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3766         }
3767
3768         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3769         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3770         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
3771         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3772
3773         /* VFTA - enable all vlan filters */
3774         for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3775                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3776
3777         /* VFRE: pool enabling for receive - 64 */
3778         IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3779         if (num_pools == ETH_64_POOLS)
3780                 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3781
3782         /*
3783          * MPSAR - allow pools to read specific mac addresses
3784          * In this case, all pools should be able to read from mac addr 0
3785          */
3786         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3787         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3788
3789         /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3790         for (i = 0; i < cfg->nb_pool_maps; i++) {
3791                 /* set vlan id in VF register and set the valid bit */
3792                 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN |
3793                                 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3794                 /*
3795                  * Put the allowed pools in VFB reg. As we only have 16 or 64
3796                  * pools, we only need to use the first half of the register
3797                  * i.e. bits 0-31
3798                  */
3799                 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3800                         IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i * 2),
3801                                         (cfg->pool_map[i].pools & UINT32_MAX));
3802                 else
3803                         IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i * 2 + 1)),
3804                                         ((cfg->pool_map[i].pools >> 32) & UINT32_MAX));
3805
3806         }
3807
3808         /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3809         if (cfg->enable_loop_back) {
3810                 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3811                 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3812                         IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3813         }
3814
3815         IXGBE_WRITE_FLUSH(hw);
3816 }
3817
3818 /*
3819  * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3820  * @hw: pointer to hardware structure
3821  */
3822 static void
3823 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3824 {
3825         uint32_t reg;
3826         uint32_t q;
3827
3828         PMD_INIT_FUNC_TRACE();
3829         /*PF VF Transmit Enable*/
3830         IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3831         IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3832
3833         /* Disable the Tx desc arbiter so that MTQC can be changed */
3834         reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3835         reg |= IXGBE_RTTDCS_ARBDIS;
3836         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3837
3838         reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3839         IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3840
3841         /* Disable drop for all queues */
3842         for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3843                 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3844                   (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3845
3846         /* Enable the Tx desc arbiter */
3847         reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3848         reg &= ~IXGBE_RTTDCS_ARBDIS;
3849         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3850
3851         IXGBE_WRITE_FLUSH(hw);
3852 }
3853
3854 static int __attribute__((cold))
3855 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
3856 {
3857         struct ixgbe_rx_entry *rxe = rxq->sw_ring;
3858         uint64_t dma_addr;
3859         unsigned int i;
3860
3861         /* Initialize software ring entries */
3862         for (i = 0; i < rxq->nb_rx_desc; i++) {
3863                 volatile union ixgbe_adv_rx_desc *rxd;
3864                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3865
3866                 if (mbuf == NULL) {
3867                         PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3868                                      (unsigned) rxq->queue_id);
3869                         return -ENOMEM;
3870                 }
3871
3872                 rte_mbuf_refcnt_set(mbuf, 1);
3873                 mbuf->next = NULL;
3874                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3875                 mbuf->nb_segs = 1;
3876                 mbuf->port = rxq->port_id;
3877
3878                 dma_addr =
3879                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
3880                 rxd = &rxq->rx_ring[i];
3881                 rxd->read.hdr_addr = 0;
3882                 rxd->read.pkt_addr = dma_addr;
3883                 rxe[i].mbuf = mbuf;
3884         }
3885
3886         return 0;
3887 }
3888
3889 static int
3890 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
3891 {
3892         struct ixgbe_hw *hw;
3893         uint32_t mrqc;
3894
3895         ixgbe_rss_configure(dev);
3896
3897         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3898
3899         /* MRQC: enable VF RSS */
3900         mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3901         mrqc &= ~IXGBE_MRQC_MRQE_MASK;
3902         switch (RTE_ETH_DEV_SRIOV(dev).active) {
3903         case ETH_64_POOLS:
3904                 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
3905                 break;
3906
3907         case ETH_32_POOLS:
3908                 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
3909                 break;
3910
3911         default:
3912                 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
3913                 return -EINVAL;
3914         }
3915
3916         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3917
3918         return 0;
3919 }
3920
3921 static int
3922 ixgbe_config_vf_default(struct rte_eth_dev *dev)
3923 {
3924         struct ixgbe_hw *hw =
3925                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3926
3927         switch (RTE_ETH_DEV_SRIOV(dev).active) {
3928         case ETH_64_POOLS:
3929                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3930                         IXGBE_MRQC_VMDQEN);
3931                 break;
3932
3933         case ETH_32_POOLS:
3934                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3935                         IXGBE_MRQC_VMDQRT4TCEN);
3936                 break;
3937
3938         case ETH_16_POOLS:
3939                 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3940                         IXGBE_MRQC_VMDQRT8TCEN);
3941                 break;
3942         default:
3943                 PMD_INIT_LOG(ERR,
3944                         "invalid pool number in IOV mode");
3945                 break;
3946         }
3947         return 0;
3948 }
3949
3950 static int
3951 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3952 {
3953         struct ixgbe_hw *hw =
3954                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3955
3956         if (hw->mac.type == ixgbe_mac_82598EB)
3957                 return 0;
3958
3959         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3960                 /*
3961                  * SRIOV inactive scheme
3962                  * any DCB/RSS w/o VMDq multi-queue setting
3963                  */
3964                 switch (dev->data->dev_conf.rxmode.mq_mode) {
3965                 case ETH_MQ_RX_RSS:
3966                 case ETH_MQ_RX_DCB_RSS:
3967                 case ETH_MQ_RX_VMDQ_RSS:
3968                         ixgbe_rss_configure(dev);
3969                         break;
3970
3971                 case ETH_MQ_RX_VMDQ_DCB:
3972                         ixgbe_vmdq_dcb_configure(dev);
3973                         break;
3974
3975                 case ETH_MQ_RX_VMDQ_ONLY:
3976                         ixgbe_vmdq_rx_hw_configure(dev);
3977                         break;
3978
3979                 case ETH_MQ_RX_NONE:
3980                 default:
3981                         /* if mq_mode is none, disable rss mode.*/
3982                         ixgbe_rss_disable(dev);
3983                         break;
3984                 }
3985         } else {
3986                 /*
3987                  * SRIOV active scheme
3988                  * Support RSS together with VMDq & SRIOV
3989                  */
3990                 switch (dev->data->dev_conf.rxmode.mq_mode) {
3991                 case ETH_MQ_RX_RSS:
3992                 case ETH_MQ_RX_VMDQ_RSS:
3993                         ixgbe_config_vf_rss(dev);
3994                         break;
3995
3996                 /* FIXME if support DCB/RSS together with VMDq & SRIOV */
3997                 case ETH_MQ_RX_VMDQ_DCB:
3998                 case ETH_MQ_RX_VMDQ_DCB_RSS:
3999                         PMD_INIT_LOG(ERR,
4000                                 "Could not support DCB with VMDq & SRIOV");
4001                         return -1;
4002                 default:
4003                         ixgbe_config_vf_default(dev);
4004                         break;
4005                 }
4006         }
4007
4008         return 0;
4009 }
4010
4011 static int
4012 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
4013 {
4014         struct ixgbe_hw *hw =
4015                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4016         uint32_t mtqc;
4017         uint32_t rttdcs;
4018
4019         if (hw->mac.type == ixgbe_mac_82598EB)
4020                 return 0;
4021
4022         /* disable arbiter before setting MTQC */
4023         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
4024         rttdcs |= IXGBE_RTTDCS_ARBDIS;
4025         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4026
4027         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
4028                 /*
4029                  * SRIOV inactive scheme
4030                  * any DCB w/o VMDq multi-queue setting
4031                  */
4032                 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
4033                         ixgbe_vmdq_tx_hw_configure(hw);
4034                 else {
4035                         mtqc = IXGBE_MTQC_64Q_1PB;
4036                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4037                 }
4038         } else {
4039                 switch (RTE_ETH_DEV_SRIOV(dev).active) {
4040
4041                 /*
4042                  * SRIOV active scheme
4043                  * FIXME if support DCB together with VMDq & SRIOV
4044                  */
4045                 case ETH_64_POOLS:
4046                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
4047                         break;
4048                 case ETH_32_POOLS:
4049                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
4050                         break;
4051                 case ETH_16_POOLS:
4052                         mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
4053                                 IXGBE_MTQC_8TC_8TQ;
4054                         break;
4055                 default:
4056                         mtqc = IXGBE_MTQC_64Q_1PB;
4057                         PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
4058                 }
4059                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
4060         }
4061
4062         /* re-enable arbiter */
4063         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
4064         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
4065
4066         return 0;
4067 }
4068
4069 /**
4070  * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
4071  *
4072  * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
4073  * spec rev. 3.0 chapter 8.2.3.8.13.
4074  *
4075  * @pool Memory pool of the Rx queue
4076  */
4077 static inline uint32_t
4078 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
4079 {
4080         struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
4081
4082         /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
4083         uint16_t maxdesc =
4084                 IPV4_MAX_PKT_LEN /
4085                         (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
4086
4087         if (maxdesc >= 16)
4088                 return IXGBE_RSCCTL_MAXDESC_16;
4089         else if (maxdesc >= 8)
4090                 return IXGBE_RSCCTL_MAXDESC_8;
4091         else if (maxdesc >= 4)
4092                 return IXGBE_RSCCTL_MAXDESC_4;
4093         else
4094                 return IXGBE_RSCCTL_MAXDESC_1;
4095 }
4096
4097 /**
4098  * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
4099  * interrupt
4100  *
4101  * (Taken from FreeBSD tree)
4102  * (yes this is all very magic and confusing :)
4103  *
4104  * @dev port handle
4105  * @entry the register array entry
4106  * @vector the MSIX vector for this queue
4107  * @type RX/TX/MISC
4108  */
4109 static void
4110 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
4111 {
4112         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4113         u32 ivar, index;
4114
4115         vector |= IXGBE_IVAR_ALLOC_VAL;
4116
4117         switch (hw->mac.type) {
4118
4119         case ixgbe_mac_82598EB:
4120                 if (type == -1)
4121                         entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
4122                 else
4123                         entry += (type * 64);
4124                 index = (entry >> 2) & 0x1F;
4125                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
4126                 ivar &= ~(0xFF << (8 * (entry & 0x3)));
4127                 ivar |= (vector << (8 * (entry & 0x3)));
4128                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
4129                 break;
4130
4131         case ixgbe_mac_82599EB:
4132         case ixgbe_mac_X540:
4133                 if (type == -1) { /* MISC IVAR */
4134                         index = (entry & 1) * 8;
4135                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4136                         ivar &= ~(0xFF << index);
4137                         ivar |= (vector << index);
4138                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
4139                 } else {        /* RX/TX IVARS */
4140                         index = (16 * (entry & 1)) + (8 * type);
4141                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
4142                         ivar &= ~(0xFF << index);
4143                         ivar |= (vector << index);
4144                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
4145                 }
4146
4147                 break;
4148
4149         default:
4150                 break;
4151         }
4152 }
4153
4154 void __attribute__((cold))
4155 ixgbe_set_rx_function(struct rte_eth_dev *dev)
4156 {
4157         uint16_t i, rx_using_sse;
4158         struct ixgbe_adapter *adapter =
4159                 (struct ixgbe_adapter *)dev->data->dev_private;
4160
4161         /*
4162          * In order to allow Vector Rx there are a few configuration
4163          * conditions to be met and Rx Bulk Allocation should be allowed.
4164          */
4165         if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
4166             !adapter->rx_bulk_alloc_allowed) {
4167                 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
4168                                     "preconditions or RTE_IXGBE_INC_VECTOR is "
4169                                     "not enabled",
4170                              dev->data->port_id);
4171
4172                 adapter->rx_vec_allowed = false;
4173         }
4174
4175         /*
4176          * Initialize the appropriate LRO callback.
4177          *
4178          * If all queues satisfy the bulk allocation preconditions
4179          * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
4180          * Otherwise use a single allocation version.
4181          */
4182         if (dev->data->lro) {
4183                 if (adapter->rx_bulk_alloc_allowed) {
4184                         PMD_INIT_LOG(DEBUG, "LRO is requested. Using a bulk "
4185                                            "allocation version");
4186                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4187                 } else {
4188                         PMD_INIT_LOG(DEBUG, "LRO is requested. Using a single "
4189                                            "allocation version");
4190                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4191                 }
4192         } else if (dev->data->scattered_rx) {
4193                 /*
4194                  * Set the non-LRO scattered callback: there are Vector and
4195                  * single allocation versions.
4196                  */
4197                 if (adapter->rx_vec_allowed) {
4198                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
4199                                             "callback (port=%d).",
4200                                      dev->data->port_id);
4201
4202                         dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4203                 } else if (adapter->rx_bulk_alloc_allowed) {
4204                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
4205                                            "allocation callback (port=%d).",
4206                                      dev->data->port_id);
4207                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
4208                 } else {
4209                         PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
4210                                             "single allocation) "
4211                                             "Scattered Rx callback "
4212                                             "(port=%d).",
4213                                      dev->data->port_id);
4214
4215                         dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
4216                 }
4217         /*
4218          * Below we set "simple" callbacks according to port/queues parameters.
4219          * If parameters allow we are going to choose between the following
4220          * callbacks:
4221          *    - Vector
4222          *    - Bulk Allocation
4223          *    - Single buffer allocation (the simplest one)
4224          */
4225         } else if (adapter->rx_vec_allowed) {
4226                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
4227                                     "burst size no less than %d (port=%d).",
4228                              RTE_IXGBE_DESCS_PER_LOOP,
4229                              dev->data->port_id);
4230
4231                 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
4232         } else if (adapter->rx_bulk_alloc_allowed) {
4233                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
4234                                     "satisfied. Rx Burst Bulk Alloc function "
4235                                     "will be used on port=%d.",
4236                              dev->data->port_id);
4237
4238                 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
4239         } else {
4240                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
4241                                     "satisfied, or Scattered Rx is requested "
4242                                     "(port=%d).",
4243                              dev->data->port_id);
4244
4245                 dev->rx_pkt_burst = ixgbe_recv_pkts;
4246         }
4247
4248         /* Propagate information about RX function choice through all queues. */
4249
4250         rx_using_sse =
4251                 (dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec ||
4252                 dev->rx_pkt_burst == ixgbe_recv_pkts_vec);
4253
4254         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4255                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4256
4257                 rxq->rx_using_sse = rx_using_sse;
4258         }
4259 }
4260
4261 /**
4262  * ixgbe_set_rsc - configure RSC related port HW registers
4263  *
4264  * Configures the port's RSC related registers according to the 4.6.7.2 chapter
4265  * of 82599 Spec (x540 configuration is virtually the same).
4266  *
4267  * @dev port handle
4268  *
4269  * Returns 0 in case of success or a non-zero error code
4270  */
4271 static int
4272 ixgbe_set_rsc(struct rte_eth_dev *dev)
4273 {
4274         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4275         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4276         struct rte_eth_dev_info dev_info = { 0 };
4277         bool rsc_capable = false;
4278         uint16_t i;
4279         uint32_t rdrxctl;
4280
4281         /* Sanity check */
4282         dev->dev_ops->dev_infos_get(dev, &dev_info);
4283         if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
4284                 rsc_capable = true;
4285
4286         if (!rsc_capable && rx_conf->enable_lro) {
4287                 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
4288                                    "support it");
4289                 return -EINVAL;
4290         }
4291
4292         /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
4293
4294         if (!rx_conf->hw_strip_crc && rx_conf->enable_lro) {
4295                 /*
4296                  * According to chapter of 4.6.7.2.1 of the Spec Rev.
4297                  * 3.0 RSC configuration requires HW CRC stripping being
4298                  * enabled. If user requested both HW CRC stripping off
4299                  * and RSC on - return an error.
4300                  */
4301                 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4302                                     "is disabled");
4303                 return -EINVAL;
4304         }
4305
4306         /* RFCTL configuration  */
4307         if (rsc_capable) {
4308                 uint32_t rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4309
4310                 if (rx_conf->enable_lro)
4311                         /*
4312                          * Since NFS packets coalescing is not supported - clear
4313                          * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
4314                          * enabled.
4315                          */
4316                         rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
4317                                    IXGBE_RFCTL_NFSR_DIS);
4318                 else
4319                         rfctl |= IXGBE_RFCTL_RSC_DIS;
4320
4321                 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4322         }
4323
4324         /* If LRO hasn't been requested - we are done here. */
4325         if (!rx_conf->enable_lro)
4326                 return 0;
4327
4328         /* Set RDRXCTL.RSCACKC bit */
4329         rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4330         rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4331         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4332
4333         /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4334         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4335                 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4336                 uint32_t srrctl =
4337                         IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4338                 uint32_t rscctl =
4339                         IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4340                 uint32_t psrtype =
4341                         IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4342                 uint32_t eitr =
4343                         IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4344
4345                 /*
4346                  * ixgbe PMD doesn't support header-split at the moment.
4347                  *
4348                  * Following the 4.6.7.2.1 chapter of the 82599/x540
4349                  * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4350                  * should be configured even if header split is not
4351                  * enabled. We will configure it 128 bytes following the
4352                  * recommendation in the spec.
4353                  */
4354                 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4355                 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4356                                             IXGBE_SRRCTL_BSIZEHDR_MASK;
4357
4358                 /*
4359                  * TODO: Consider setting the Receive Descriptor Minimum
4360                  * Threshold Size for an RSC case. This is not an obviously
4361                  * beneficiary option but the one worth considering...
4362                  */
4363
4364                 rscctl |= IXGBE_RSCCTL_RSCEN;
4365                 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4366                 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4367
4368                 /*
4369                  * RSC: Set ITR interval corresponding to 2K ints/s.
4370                  *
4371                  * Full-sized RSC aggregations for a 10Gb/s link will
4372                  * arrive at about 20K aggregation/s rate.
4373                  *
4374                  * 2K inst/s rate will make only 10% of the
4375                  * aggregations to be closed due to the interrupt timer
4376                  * expiration for a streaming at wire-speed case.
4377                  *
4378                  * For a sparse streaming case this setting will yield
4379                  * at most 500us latency for a single RSC aggregation.
4380                  */
4381                 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
4382                 eitr |= IXGBE_EITR_INTERVAL_US(500) | IXGBE_EITR_CNT_WDIS;
4383
4384                 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4385                 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
4386                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4387                 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
4388
4389                 /*
4390                  * RSC requires the mapping of the queue to the
4391                  * interrupt vector.
4392                  */
4393                 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
4394         }
4395
4396         dev->data->lro = 1;
4397
4398         PMD_INIT_LOG(DEBUG, "enabling LRO mode");
4399
4400         return 0;
4401 }
4402
4403 /*
4404  * Initializes Receive Unit.
4405  */
4406 int __attribute__((cold))
4407 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
4408 {
4409         struct ixgbe_hw     *hw;
4410         struct ixgbe_rx_queue *rxq;
4411         uint64_t bus_addr;
4412         uint32_t rxctrl;
4413         uint32_t fctrl;
4414         uint32_t hlreg0;
4415         uint32_t maxfrs;
4416         uint32_t srrctl;
4417         uint32_t rdrxctl;
4418         uint32_t rxcsum;
4419         uint16_t buf_size;
4420         uint16_t i;
4421         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4422         int rc;
4423
4424         PMD_INIT_FUNC_TRACE();
4425         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4426
4427         /*
4428          * Make sure receives are disabled while setting
4429          * up the RX context (registers, descriptor rings, etc.).
4430          */
4431         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4432         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4433
4434         /* Enable receipt of broadcasted frames */
4435         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4436         fctrl |= IXGBE_FCTRL_BAM;
4437         fctrl |= IXGBE_FCTRL_DPF;
4438         fctrl |= IXGBE_FCTRL_PMCF;
4439         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4440
4441         /*
4442          * Configure CRC stripping, if any.
4443          */
4444         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4445         if (rx_conf->hw_strip_crc)
4446                 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4447         else
4448                 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4449
4450         /*
4451          * Configure jumbo frame support, if any.
4452          */
4453         if (rx_conf->jumbo_frame == 1) {
4454                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4455                 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4456                 maxfrs &= 0x0000FFFF;
4457                 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4458                 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4459         } else
4460                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4461
4462         /*
4463          * If loopback mode is configured for 82599, set LPBK bit.
4464          */
4465         if (hw->mac.type == ixgbe_mac_82599EB &&
4466                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4467                 hlreg0 |= IXGBE_HLREG0_LPBK;
4468         else
4469                 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4470
4471         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4472
4473         /* Setup RX queues */
4474         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4475                 rxq = dev->data->rx_queues[i];
4476
4477                 /*
4478                  * Reset crc_len in case it was changed after queue setup by a
4479                  * call to configure.
4480                  */
4481                 rxq->crc_len = rx_conf->hw_strip_crc ? 0 : ETHER_CRC_LEN;
4482
4483                 /* Setup the Base and Length of the Rx Descriptor Rings */
4484                 bus_addr = rxq->rx_ring_phys_addr;
4485                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4486                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4487                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4488                                 (uint32_t)(bus_addr >> 32));
4489                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4490                                 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4491                 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4492                 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4493
4494                 /* Configure the SRRCTL register */
4495 #ifdef RTE_HEADER_SPLIT_ENABLE
4496                 /*
4497                  * Configure Header Split
4498                  */
4499                 if (rx_conf->header_split) {
4500                         if (hw->mac.type == ixgbe_mac_82599EB) {
4501                                 /* Must setup the PSRTYPE register */
4502                                 uint32_t psrtype;
4503
4504                                 psrtype = IXGBE_PSRTYPE_TCPHDR |
4505                                         IXGBE_PSRTYPE_UDPHDR   |
4506                                         IXGBE_PSRTYPE_IPV4HDR  |
4507                                         IXGBE_PSRTYPE_IPV6HDR;
4508                                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4509                         }
4510                         srrctl = ((rx_conf->split_hdr_size <<
4511                                 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4512                                 IXGBE_SRRCTL_BSIZEHDR_MASK);
4513                         srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4514                 } else
4515 #endif
4516                         srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4517
4518                 /* Set if packets are dropped when no descriptors available */
4519                 if (rxq->drop_en)
4520                         srrctl |= IXGBE_SRRCTL_DROP_EN;
4521
4522                 /*
4523                  * Configure the RX buffer size in the BSIZEPACKET field of
4524                  * the SRRCTL register of the queue.
4525                  * The value is in 1 KB resolution. Valid values can be from
4526                  * 1 KB to 16 KB.
4527                  */
4528                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4529                         RTE_PKTMBUF_HEADROOM);
4530                 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4531                            IXGBE_SRRCTL_BSIZEPKT_MASK);
4532
4533                 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4534
4535                 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4536                                        IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4537
4538                 /* It adds dual VLAN length for supporting dual VLAN */
4539                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4540                                             2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4541                         dev->data->scattered_rx = 1;
4542         }
4543
4544         if (rx_conf->enable_scatter)
4545                 dev->data->scattered_rx = 1;
4546
4547         /*
4548          * Device configured with multiple RX queues.
4549          */
4550         ixgbe_dev_mq_rx_configure(dev);
4551
4552         /*
4553          * Setup the Checksum Register.
4554          * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4555          * Enable IP/L4 checkum computation by hardware if requested to do so.
4556          */
4557         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4558         rxcsum |= IXGBE_RXCSUM_PCSD;
4559         if (rx_conf->hw_ip_checksum)
4560                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4561         else
4562                 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4563
4564         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4565
4566         if (hw->mac.type == ixgbe_mac_82599EB ||
4567             hw->mac.type == ixgbe_mac_X540) {
4568                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4569                 if (rx_conf->hw_strip_crc)
4570                         rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4571                 else
4572                         rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4573                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4574                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4575         }
4576
4577         rc = ixgbe_set_rsc(dev);
4578         if (rc)
4579                 return rc;
4580
4581         ixgbe_set_rx_function(dev);
4582
4583         return 0;
4584 }
4585
4586 /*
4587  * Initializes Transmit Unit.
4588  */
4589 void __attribute__((cold))
4590 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
4591 {
4592         struct ixgbe_hw     *hw;
4593         struct ixgbe_tx_queue *txq;
4594         uint64_t bus_addr;
4595         uint32_t hlreg0;
4596         uint32_t txctrl;
4597         uint16_t i;
4598
4599         PMD_INIT_FUNC_TRACE();
4600         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4601
4602         /* Enable TX CRC (checksum offload requirement) and hw padding
4603          * (TSO requirement)
4604          */
4605         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4606         hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
4607         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4608
4609         /* Setup the Base and Length of the Tx Descriptor Rings */
4610         for (i = 0; i < dev->data->nb_tx_queues; i++) {
4611                 txq = dev->data->tx_queues[i];
4612
4613                 bus_addr = txq->tx_ring_phys_addr;
4614                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
4615                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4616                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
4617                                 (uint32_t)(bus_addr >> 32));
4618                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
4619                                 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4620                 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4621                 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4622                 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4623
4624                 /*
4625                  * Disable Tx Head Writeback RO bit, since this hoses
4626                  * bookkeeping if things aren't delivered in order.
4627                  */
4628                 switch (hw->mac.type) {
4629                 case ixgbe_mac_82598EB:
4630                         txctrl = IXGBE_READ_REG(hw,
4631                                                 IXGBE_DCA_TXCTRL(txq->reg_idx));
4632                         txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4633                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
4634                                         txctrl);
4635                         break;
4636
4637                 case ixgbe_mac_82599EB:
4638                 case ixgbe_mac_X540:
4639                 case ixgbe_mac_X550:
4640                 case ixgbe_mac_X550EM_x:
4641                 case ixgbe_mac_X550EM_a:
4642                 default:
4643                         txctrl = IXGBE_READ_REG(hw,
4644                                                 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
4645                         txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4646                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
4647                                         txctrl);
4648                         break;
4649                 }
4650         }
4651
4652         /* Device configured with multiple TX queues. */
4653         ixgbe_dev_mq_tx_configure(dev);
4654 }
4655
4656 /*
4657  * Set up link for 82599 loopback mode Tx->Rx.
4658  */
4659 static inline void __attribute__((cold))
4660 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
4661 {
4662         PMD_INIT_FUNC_TRACE();
4663
4664         if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
4665                 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
4666                                 IXGBE_SUCCESS) {
4667                         PMD_INIT_LOG(ERR, "Could not enable loopback mode");
4668                         /* ignore error */
4669                         return;
4670                 }
4671         }
4672
4673         /* Restart link */
4674         IXGBE_WRITE_REG(hw,
4675                         IXGBE_AUTOC,
4676                         IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
4677         ixgbe_reset_pipeline_82599(hw);
4678
4679         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
4680         msec_delay(50);
4681 }
4682
4683
4684 /*
4685  * Start Transmit and Receive Units.
4686  */
4687 int __attribute__((cold))
4688 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
4689 {
4690         struct ixgbe_hw     *hw;
4691         struct ixgbe_tx_queue *txq;
4692         struct ixgbe_rx_queue *rxq;
4693         uint32_t txdctl;
4694         uint32_t dmatxctl;
4695         uint32_t rxctrl;
4696         uint16_t i;
4697         int ret = 0;
4698
4699         PMD_INIT_FUNC_TRACE();
4700         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4701
4702         for (i = 0; i < dev->data->nb_tx_queues; i++) {
4703                 txq = dev->data->tx_queues[i];
4704                 /* Setup Transmit Threshold Registers */
4705                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4706                 txdctl |= txq->pthresh & 0x7F;
4707                 txdctl |= ((txq->hthresh & 0x7F) << 8);
4708                 txdctl |= ((txq->wthresh & 0x7F) << 16);
4709                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4710         }
4711
4712         if (hw->mac.type != ixgbe_mac_82598EB) {
4713                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
4714                 dmatxctl |= IXGBE_DMATXCTL_TE;
4715                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
4716         }
4717
4718         for (i = 0; i < dev->data->nb_tx_queues; i++) {
4719                 txq = dev->data->tx_queues[i];
4720                 if (!txq->tx_deferred_start) {
4721                         ret = ixgbe_dev_tx_queue_start(dev, i);
4722                         if (ret < 0)
4723                                 return ret;
4724                 }
4725         }
4726
4727         for (i = 0; i < dev->data->nb_rx_queues; i++) {
4728                 rxq = dev->data->rx_queues[i];
4729                 if (!rxq->rx_deferred_start) {
4730                         ret = ixgbe_dev_rx_queue_start(dev, i);
4731                         if (ret < 0)
4732                                 return ret;
4733                 }
4734         }
4735
4736         /* Enable Receive engine */
4737         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4738         if (hw->mac.type == ixgbe_mac_82598EB)
4739                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4740         rxctrl |= IXGBE_RXCTRL_RXEN;
4741         hw->mac.ops.enable_rx_dma(hw, rxctrl);
4742
4743         /* If loopback mode is enabled for 82599, set up the link accordingly */
4744         if (hw->mac.type == ixgbe_mac_82599EB &&
4745                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4746                 ixgbe_setup_loopback_link_82599(hw);
4747
4748         return 0;
4749 }
4750
4751 /*
4752  * Start Receive Units for specified queue.
4753  */
4754 int __attribute__((cold))
4755 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4756 {
4757         struct ixgbe_hw     *hw;
4758         struct ixgbe_rx_queue *rxq;
4759         uint32_t rxdctl;
4760         int poll_ms;
4761
4762         PMD_INIT_FUNC_TRACE();
4763         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4764
4765         if (rx_queue_id < dev->data->nb_rx_queues) {
4766                 rxq = dev->data->rx_queues[rx_queue_id];
4767
4768                 /* Allocate buffers for descriptor rings */
4769                 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
4770                         PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
4771                                      rx_queue_id);
4772                         return -1;
4773                 }
4774                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4775                 rxdctl |= IXGBE_RXDCTL_ENABLE;
4776                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4777
4778                 /* Wait until RX Enable ready */
4779                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4780                 do {
4781                         rte_delay_ms(1);
4782                         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4783                 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4784                 if (!poll_ms)
4785                         PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
4786                                      rx_queue_id);
4787                 rte_wmb();
4788                 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4789                 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
4790                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
4791         } else
4792                 return -1;
4793
4794         return 0;
4795 }
4796
4797 /*
4798  * Stop Receive Units for specified queue.
4799  */
4800 int __attribute__((cold))
4801 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4802 {
4803         struct ixgbe_hw     *hw;
4804         struct ixgbe_adapter *adapter =
4805                 (struct ixgbe_adapter *)dev->data->dev_private;
4806         struct ixgbe_rx_queue *rxq;
4807         uint32_t rxdctl;
4808         int poll_ms;
4809
4810         PMD_INIT_FUNC_TRACE();
4811         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4812
4813         if (rx_queue_id < dev->data->nb_rx_queues) {
4814                 rxq = dev->data->rx_queues[rx_queue_id];
4815
4816                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4817                 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4818                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4819
4820                 /* Wait until RX Enable bit clear */
4821                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4822                 do {
4823                         rte_delay_ms(1);
4824                         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4825                 } while (--poll_ms && (rxdctl & IXGBE_RXDCTL_ENABLE));
4826                 if (!poll_ms)
4827                         PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
4828                                      rx_queue_id);
4829
4830                 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4831
4832                 ixgbe_rx_queue_release_mbufs(rxq);
4833                 ixgbe_reset_rx_queue(adapter, rxq);
4834                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
4835         } else
4836                 return -1;
4837
4838         return 0;
4839 }
4840
4841
4842 /*
4843  * Start Transmit Units for specified queue.
4844  */
4845 int __attribute__((cold))
4846 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4847 {
4848         struct ixgbe_hw     *hw;
4849         struct ixgbe_tx_queue *txq;
4850         uint32_t txdctl;
4851         int poll_ms;
4852
4853         PMD_INIT_FUNC_TRACE();
4854         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4855
4856         if (tx_queue_id < dev->data->nb_tx_queues) {
4857                 txq = dev->data->tx_queues[tx_queue_id];
4858                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4859                 txdctl |= IXGBE_TXDCTL_ENABLE;
4860                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4861
4862                 /* Wait until TX Enable ready */
4863                 if (hw->mac.type == ixgbe_mac_82599EB) {
4864                         poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4865                         do {
4866                                 rte_delay_ms(1);
4867                                 txdctl = IXGBE_READ_REG(hw,
4868                                         IXGBE_TXDCTL(txq->reg_idx));
4869                         } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4870                         if (!poll_ms)
4871                                 PMD_INIT_LOG(ERR, "Could not enable "
4872                                              "Tx Queue %d", tx_queue_id);
4873                 }
4874                 rte_wmb();
4875                 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4876                 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4877                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
4878         } else
4879                 return -1;
4880
4881         return 0;
4882 }
4883
4884 /*
4885  * Stop Transmit Units for specified queue.
4886  */
4887 int __attribute__((cold))
4888 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4889 {
4890         struct ixgbe_hw     *hw;
4891         struct ixgbe_tx_queue *txq;
4892         uint32_t txdctl;
4893         uint32_t txtdh, txtdt;
4894         int poll_ms;
4895
4896         PMD_INIT_FUNC_TRACE();
4897         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4898
4899         if (tx_queue_id >= dev->data->nb_tx_queues)
4900                 return -1;
4901
4902         txq = dev->data->tx_queues[tx_queue_id];
4903
4904         /* Wait until TX queue is empty */
4905         if (hw->mac.type == ixgbe_mac_82599EB) {
4906                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4907                 do {
4908                         rte_delay_us(RTE_IXGBE_WAIT_100_US);
4909                         txtdh = IXGBE_READ_REG(hw,
4910                                                IXGBE_TDH(txq->reg_idx));
4911                         txtdt = IXGBE_READ_REG(hw,
4912                                                IXGBE_TDT(txq->reg_idx));
4913                 } while (--poll_ms && (txtdh != txtdt));
4914                 if (!poll_ms)
4915                         PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
4916                                      "when stopping.", tx_queue_id);
4917         }
4918
4919         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4920         txdctl &= ~IXGBE_TXDCTL_ENABLE;
4921         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4922
4923         /* Wait until TX Enable bit clear */
4924         if (hw->mac.type == ixgbe_mac_82599EB) {
4925                 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4926                 do {
4927                         rte_delay_ms(1);
4928                         txdctl = IXGBE_READ_REG(hw,
4929                                                 IXGBE_TXDCTL(txq->reg_idx));
4930                 } while (--poll_ms && (txdctl & IXGBE_TXDCTL_ENABLE));
4931                 if (!poll_ms)
4932                         PMD_INIT_LOG(ERR, "Could not disable "
4933                                      "Tx Queue %d", tx_queue_id);
4934         }
4935
4936         if (txq->ops != NULL) {
4937                 txq->ops->release_mbufs(txq);
4938                 txq->ops->reset(txq);
4939         }
4940         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
4941
4942         return 0;
4943 }
4944
4945 void
4946 ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
4947         struct rte_eth_rxq_info *qinfo)
4948 {
4949         struct ixgbe_rx_queue *rxq;
4950
4951         rxq = dev->data->rx_queues[queue_id];
4952
4953         qinfo->mp = rxq->mb_pool;
4954         qinfo->scattered_rx = dev->data->scattered_rx;
4955         qinfo->nb_desc = rxq->nb_rx_desc;
4956
4957         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
4958         qinfo->conf.rx_drop_en = rxq->drop_en;
4959         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
4960 }
4961
4962 void
4963 ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
4964         struct rte_eth_txq_info *qinfo)
4965 {
4966         struct ixgbe_tx_queue *txq;
4967
4968         txq = dev->data->tx_queues[queue_id];
4969
4970         qinfo->nb_desc = txq->nb_tx_desc;
4971
4972         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
4973         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
4974         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
4975
4976         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
4977         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
4978         qinfo->conf.txq_flags = txq->txq_flags;
4979         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
4980 }
4981
4982 /*
4983  * [VF] Initializes Receive Unit.
4984  */
4985 int __attribute__((cold))
4986 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
4987 {
4988         struct ixgbe_hw     *hw;
4989         struct ixgbe_rx_queue *rxq;
4990         uint64_t bus_addr;
4991         uint32_t srrctl, psrtype = 0;
4992         uint16_t buf_size;
4993         uint16_t i;
4994         int ret;
4995
4996         PMD_INIT_FUNC_TRACE();
4997         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4998
4999         if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
5000                 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5001                         "it should be power of 2");
5002                 return -1;
5003         }
5004
5005         if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
5006                 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
5007                         "it should be equal to or less than %d",
5008                         hw->mac.max_rx_queues);
5009                 return -1;
5010         }
5011
5012         /*
5013          * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
5014          * disables the VF receipt of packets if the PF MTU is > 1500.
5015          * This is done to deal with 82599 limitations that imposes
5016          * the PF and all VFs to share the same MTU.
5017          * Then, the PF driver enables again the VF receipt of packet when
5018          * the VF driver issues a IXGBE_VF_SET_LPE request.
5019          * In the meantime, the VF device cannot be used, even if the VF driver
5020          * and the Guest VM network stack are ready to accept packets with a
5021          * size up to the PF MTU.
5022          * As a work-around to this PF behaviour, force the call to
5023          * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
5024          * VF packets received can work in all cases.
5025          */
5026         ixgbevf_rlpml_set_vf(hw,
5027                 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
5028
5029         /* Setup RX queues */
5030         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5031                 rxq = dev->data->rx_queues[i];
5032
5033                 /* Allocate buffers for descriptor rings */
5034                 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
5035                 if (ret)
5036                         return ret;
5037
5038                 /* Setup the Base and Length of the Rx Descriptor Rings */
5039                 bus_addr = rxq->rx_ring_phys_addr;
5040
5041                 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
5042                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5043                 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
5044                                 (uint32_t)(bus_addr >> 32));
5045                 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
5046                                 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
5047                 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
5048                 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
5049
5050
5051                 /* Configure the SRRCTL register */
5052 #ifdef RTE_HEADER_SPLIT_ENABLE
5053                 /*
5054                  * Configure Header Split
5055                  */
5056                 if (dev->data->dev_conf.rxmode.header_split) {
5057                         srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
5058                                 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
5059                                 IXGBE_SRRCTL_BSIZEHDR_MASK);
5060                         srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
5061                 } else
5062 #endif
5063                         srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
5064
5065                 /* Set if packets are dropped when no descriptors available */
5066                 if (rxq->drop_en)
5067                         srrctl |= IXGBE_SRRCTL_DROP_EN;
5068
5069                 /*
5070                  * Configure the RX buffer size in the BSIZEPACKET field of
5071                  * the SRRCTL register of the queue.
5072                  * The value is in 1 KB resolution. Valid values can be from
5073                  * 1 KB to 16 KB.
5074                  */
5075                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
5076                         RTE_PKTMBUF_HEADROOM);
5077                 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
5078                            IXGBE_SRRCTL_BSIZEPKT_MASK);
5079
5080                 /*
5081                  * VF modification to write virtual function SRRCTL register
5082                  */
5083                 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
5084
5085                 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
5086                                        IXGBE_SRRCTL_BSIZEPKT_SHIFT);
5087
5088                 if (dev->data->dev_conf.rxmode.enable_scatter ||
5089                     /* It adds dual VLAN length for supporting dual VLAN */
5090                     (dev->data->dev_conf.rxmode.max_rx_pkt_len +
5091                                 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
5092                         if (!dev->data->scattered_rx)
5093                                 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
5094                         dev->data->scattered_rx = 1;
5095                 }
5096         }
5097
5098 #ifdef RTE_HEADER_SPLIT_ENABLE
5099         if (dev->data->dev_conf.rxmode.header_split)
5100                 /* Must setup the PSRTYPE register */
5101                 psrtype = IXGBE_PSRTYPE_TCPHDR |
5102                         IXGBE_PSRTYPE_UDPHDR   |
5103                         IXGBE_PSRTYPE_IPV4HDR  |
5104                         IXGBE_PSRTYPE_IPV6HDR;
5105 #endif
5106
5107         /* Set RQPL for VF RSS according to max Rx queue */
5108         psrtype |= (dev->data->nb_rx_queues >> 1) <<
5109                 IXGBE_PSRTYPE_RQPL_SHIFT;
5110         IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
5111
5112         ixgbe_set_rx_function(dev);
5113
5114         return 0;
5115 }
5116
5117 /*
5118  * [VF] Initializes Transmit Unit.
5119  */
5120 void __attribute__((cold))
5121 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
5122 {
5123         struct ixgbe_hw     *hw;
5124         struct ixgbe_tx_queue *txq;
5125         uint64_t bus_addr;
5126         uint32_t txctrl;
5127         uint16_t i;
5128
5129         PMD_INIT_FUNC_TRACE();
5130         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131
5132         /* Setup the Base and Length of the Tx Descriptor Rings */
5133         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5134                 txq = dev->data->tx_queues[i];
5135                 bus_addr = txq->tx_ring_phys_addr;
5136                 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
5137                                 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
5138                 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
5139                                 (uint32_t)(bus_addr >> 32));
5140                 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
5141                                 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
5142                 /* Setup the HW Tx Head and TX Tail descriptor pointers */
5143                 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
5144                 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
5145
5146                 /*
5147                  * Disable Tx Head Writeback RO bit, since this hoses
5148                  * bookkeeping if things aren't delivered in order.
5149                  */
5150                 txctrl = IXGBE_READ_REG(hw,
5151                                 IXGBE_VFDCA_TXCTRL(i));
5152                 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
5153                 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
5154                                 txctrl);
5155         }
5156 }
5157
5158 /*
5159  * [VF] Start Transmit and Receive Units.
5160  */
5161 void __attribute__((cold))
5162 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
5163 {
5164         struct ixgbe_hw     *hw;
5165         struct ixgbe_tx_queue *txq;
5166         struct ixgbe_rx_queue *rxq;
5167         uint32_t txdctl;
5168         uint32_t rxdctl;
5169         uint16_t i;
5170         int poll_ms;
5171
5172         PMD_INIT_FUNC_TRACE();
5173         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5174
5175         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5176                 txq = dev->data->tx_queues[i];
5177                 /* Setup Transmit Threshold Registers */
5178                 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5179                 txdctl |= txq->pthresh & 0x7F;
5180                 txdctl |= ((txq->hthresh & 0x7F) << 8);
5181                 txdctl |= ((txq->wthresh & 0x7F) << 16);
5182                 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5183         }
5184
5185         for (i = 0; i < dev->data->nb_tx_queues; i++) {
5186
5187                 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5188                 txdctl |= IXGBE_TXDCTL_ENABLE;
5189                 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
5190
5191                 poll_ms = 10;
5192                 /* Wait until TX Enable ready */
5193                 do {
5194                         rte_delay_ms(1);
5195                         txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
5196                 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
5197                 if (!poll_ms)
5198                         PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
5199         }
5200         for (i = 0; i < dev->data->nb_rx_queues; i++) {
5201
5202                 rxq = dev->data->rx_queues[i];
5203
5204                 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5205                 rxdctl |= IXGBE_RXDCTL_ENABLE;
5206                 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
5207
5208                 /* Wait until RX Enable ready */
5209                 poll_ms = 10;
5210                 do {
5211                         rte_delay_ms(1);
5212                         rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
5213                 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
5214                 if (!poll_ms)
5215                         PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
5216                 rte_wmb();
5217                 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
5218
5219         }
5220 }
5221
5222 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
5223 int __attribute__((weak))
5224 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
5225 {
5226         return -1;
5227 }
5228
5229 uint16_t __attribute__((weak))
5230 ixgbe_recv_pkts_vec(
5231         void __rte_unused *rx_queue,
5232         struct rte_mbuf __rte_unused **rx_pkts,
5233         uint16_t __rte_unused nb_pkts)
5234 {
5235         return 0;
5236 }
5237
5238 uint16_t __attribute__((weak))
5239 ixgbe_recv_scattered_pkts_vec(
5240         void __rte_unused *rx_queue,
5241         struct rte_mbuf __rte_unused **rx_pkts,
5242         uint16_t __rte_unused nb_pkts)
5243 {
5244         return 0;
5245 }
5246
5247 int __attribute__((weak))
5248 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)
5249 {
5250         return -1;
5251 }