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35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "ixgbe_ethdev.h"
39 #include "ixgbe_rxtx.h"
41 #include <tmmintrin.h>
43 #ifndef __INTEL_COMPILER
44 #pragma GCC diagnostic ignored "-Wcast-qual"
48 ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
52 volatile union ixgbe_adv_rx_desc *rxdp;
53 struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
54 struct rte_mbuf *mb0, *mb1;
55 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
56 RTE_PKTMBUF_HEADROOM);
57 __m128i dma_addr0, dma_addr1;
59 const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);
61 rxdp = rxq->rx_ring + rxq->rxrearm_start;
63 /* Pull 'n' more MBUFs into the software ring */
64 if (rte_mempool_get_bulk(rxq->mb_pool,
66 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
67 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
69 dma_addr0 = _mm_setzero_si128();
70 for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
71 rxep[i].mbuf = &rxq->fake_mbuf;
72 _mm_store_si128((__m128i *)&rxdp[i].read,
76 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
77 RTE_IXGBE_RXQ_REARM_THRESH;
81 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
82 for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
83 __m128i vaddr0, vaddr1;
90 * Flush mbuf with pkt template.
91 * Data to be rearmed is 6 bytes long.
92 * Though, RX will overwrite ol_flags that are coming next
93 * anyway. So overwrite whole 8 bytes with one load:
94 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
96 p0 = (uintptr_t)&mb0->rearm_data;
97 *(uint64_t *)p0 = rxq->mbuf_initializer;
98 p1 = (uintptr_t)&mb1->rearm_data;
99 *(uint64_t *)p1 = rxq->mbuf_initializer;
101 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
102 vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
103 vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
105 /* convert pa to dma_addr hdr/data */
106 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
107 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
109 /* add headroom to pa values */
110 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
111 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
113 /* set Header Buffer Address to zero */
114 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
115 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
117 /* flush desc with pa dma_addr */
118 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
119 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
122 rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
123 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
124 rxq->rxrearm_start = 0;
126 rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
128 rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
129 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
131 /* Update the tail pointer on the NIC */
132 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
135 /* Handling the offload flags (olflags) field takes computation
136 * time when receiving packets. Therefore we provide a flag to disable
137 * the processing of the olflags field when they are not needed. This
138 * gives improved performance, at the cost of losing the offload info
139 * in the received packet
141 #ifdef RTE_IXGBE_RX_OLFLAGS_ENABLE
143 #define VTAG_SHIFT (3)
146 desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
148 __m128i ptype0, ptype1, vtag0, vtag1;
154 /* pkt type + vlan olflags mask */
155 const __m128i pkttype_msk = _mm_set_epi16(
156 0x0000, 0x0000, 0x0000, 0x0000,
157 PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT);
159 /* mask everything except rss type */
160 const __m128i rsstype_msk = _mm_set_epi16(
161 0x0000, 0x0000, 0x0000, 0x0000,
162 0x000F, 0x000F, 0x000F, 0x000F);
164 /* map rss type to rss hash flag */
165 const __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,
166 0, 0, 0, PKT_RX_RSS_HASH,
167 PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
168 PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
170 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
171 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
172 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
173 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
175 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
176 ptype0 = _mm_and_si128(ptype0, rsstype_msk);
177 ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
179 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
180 vtag1 = _mm_srli_epi16(vtag1, VTAG_SHIFT);
181 vtag1 = _mm_and_si128(vtag1, pkttype_msk);
183 vtag1 = _mm_or_si128(ptype0, vtag1);
184 vol.dword = _mm_cvtsi128_si64(vtag1);
186 rx_pkts[0]->ol_flags = vol.e[0];
187 rx_pkts[1]->ol_flags = vol.e[1];
188 rx_pkts[2]->ol_flags = vol.e[2];
189 rx_pkts[3]->ol_flags = vol.e[3];
192 #define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
196 * vPMD receive routine, now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
200 * - nb_pkts < RTE_IXGBE_VPMD_RX_BURST, just return no packet
201 * - nb_pkts > RTE_IXGBE_VPMD_RX_BURST, only scan RTE_IXGBE_VPMD_RX_BURST
203 * - don't support ol_flags for rss and csum err
205 static inline uint16_t
206 _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
207 uint16_t nb_pkts, uint8_t *split_packet)
209 volatile union ixgbe_adv_rx_desc *rxdp;
210 struct ixgbe_rx_entry *sw_ring;
211 uint16_t nb_pkts_recd;
215 __m128i crc_adjust = _mm_set_epi16(
216 0, 0, 0, /* ignore non-length fields */
217 -rxq->crc_len, /* sub crc on data_len */
218 0, /* ignore high-16bits of pkt_len */
219 -rxq->crc_len, /* sub crc on pkt_len */
220 0, 0 /* ignore pkt_type field */
222 __m128i dd_check, eop_check;
223 __m128i desc_mask = _mm_set_epi32(0xFFFFFFFF, 0xFFFFFFFF,
224 0xFFFFFFFF, 0xFFFF07F0);
226 if (unlikely(nb_pkts < RTE_IXGBE_VPMD_RX_BURST))
229 /* Just the act of getting into the function from the application is
230 * going to cost about 7 cycles */
231 rxdp = rxq->rx_ring + rxq->rx_tail;
233 _mm_prefetch((const void *)rxdp, _MM_HINT_T0);
235 /* See if we need to rearm the RX queue - gives the prefetch a bit
237 if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
238 ixgbe_rxq_rearm(rxq);
240 /* Before we start moving massive data around, check to see if
241 * there is actually a packet available */
242 if (!(rxdp->wb.upper.status_error &
243 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
246 /* 4 packets DD mask */
247 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
249 /* 4 packets EOP mask */
250 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
252 /* mask to shuffle from desc. to mbuf */
253 shuf_msk = _mm_set_epi8(
254 7, 6, 5, 4, /* octet 4~7, 32bits rss */
255 15, 14, /* octet 14~15, low 16 bits vlan_macip */
256 13, 12, /* octet 12~13, 16 bits data_len */
257 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
258 13, 12, /* octet 12~13, low 16 bits pkt_len */
259 0xFF, 0xFF, /* skip high 16 bits pkt_type */
260 1, /* octet 1, 8 bits pkt_type field */
261 0 /* octet 0, 4 bits offset 4 pkt_type field */
264 /* Cache is empty -> need to scan the buffer rings, but first move
265 * the next 'n' mbufs into the cache */
266 sw_ring = &rxq->sw_ring[rxq->rx_tail];
268 /* A. load 4 packet in one loop
269 * [A*. mask out 4 unused dirty field in desc]
270 * B. copy 4 mbuf point from swring to rx_pkts
271 * C. calc the number of DD bits among the 4 packets
272 * [C*. extract the end-of-packet bit, if requested]
273 * D. fill info. from desc to mbuf
275 for (pos = 0, nb_pkts_recd = 0; pos < RTE_IXGBE_VPMD_RX_BURST;
276 pos += RTE_IXGBE_DESCS_PER_LOOP,
277 rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
278 __m128i descs0[RTE_IXGBE_DESCS_PER_LOOP];
279 __m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
280 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
281 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
282 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
285 rte_prefetch0(&rx_pkts[pos]->cacheline1);
286 rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
287 rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
288 rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
291 /* B.1 load 1 mbuf point */
292 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
294 /* Read desc statuses backwards to avoid race condition */
295 /* A.1 load 4 pkts desc */
296 descs0[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
298 /* B.2 copy 2 mbuf point into rx_pkts */
299 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
301 /* B.1 load 1 mbuf point */
302 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
304 descs0[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
305 /* B.1 load 2 mbuf point */
306 descs0[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
307 descs0[0] = _mm_loadu_si128((__m128i *)(rxdp));
309 /* B.2 copy 2 mbuf point into rx_pkts */
310 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
312 /* A* mask out 0~3 bits RSS type */
313 descs[3] = _mm_and_si128(descs0[3], desc_mask);
314 descs[2] = _mm_and_si128(descs0[2], desc_mask);
316 /* A* mask out 0~3 bits RSS type */
317 descs[1] = _mm_and_si128(descs0[1], desc_mask);
318 descs[0] = _mm_and_si128(descs0[0], desc_mask);
320 /* avoid compiler reorder optimization */
321 rte_compiler_barrier();
323 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
324 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
325 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
327 /* C.1 4=>2 filter staterr info only */
328 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
329 /* C.1 4=>2 filter staterr info only */
330 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
332 /* set ol_flags with vlan packet type */
333 desc_to_olflags_v(descs0, &rx_pkts[pos]);
335 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
336 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
337 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
339 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
340 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
341 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
343 /* C.2 get 4 pkts staterr value */
344 zero = _mm_xor_si128(dd_check, dd_check);
345 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
347 /* D.3 copy final 3,4 data to rx_pkts */
348 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
350 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
353 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
354 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
355 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
357 /* C* extract and record EOP bit */
359 __m128i eop_shuf_mask = _mm_set_epi8(
360 0xFF, 0xFF, 0xFF, 0xFF,
361 0xFF, 0xFF, 0xFF, 0xFF,
362 0xFF, 0xFF, 0xFF, 0xFF,
363 0x04, 0x0C, 0x00, 0x08
366 /* and with mask to extract bits, flipping 1-0 */
367 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
368 /* the staterr values are not in order, as the count
369 * count of dd bits doesn't care. However, for end of
370 * packet tracking, we do care, so shuffle. This also
371 * compresses the 32-bit values to 8-bit */
372 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
373 /* store the resulting 32-bit value */
374 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
375 split_packet += RTE_IXGBE_DESCS_PER_LOOP;
377 /* zero-out next pointers */
378 rx_pkts[pos]->next = NULL;
379 rx_pkts[pos + 1]->next = NULL;
380 rx_pkts[pos + 2]->next = NULL;
381 rx_pkts[pos + 3]->next = NULL;
384 /* C.3 calc available number of desc */
385 staterr = _mm_and_si128(staterr, dd_check);
386 staterr = _mm_packs_epi32(staterr, zero);
388 /* D.3 copy final 1,2 data to rx_pkts */
389 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
391 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
394 /* C.4 calc avaialbe number of desc */
395 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
397 if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
401 /* Update our internal tail pointer */
402 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
403 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
404 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
410 * vPMD receive routine, now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
414 * - nb_pkts < RTE_IXGBE_VPMD_RX_BURST, just return no packet
415 * - nb_pkts > RTE_IXGBE_VPMD_RX_BURST, only scan RTE_IXGBE_VPMD_RX_BURST
417 * - don't support ol_flags for rss and csum err
420 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
423 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
426 static inline uint16_t
427 reassemble_packets(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_bufs,
428 uint16_t nb_bufs, uint8_t *split_flags)
430 struct rte_mbuf *pkts[RTE_IXGBE_VPMD_RX_BURST]; /*finished pkts*/
431 struct rte_mbuf *start = rxq->pkt_first_seg;
432 struct rte_mbuf *end = rxq->pkt_last_seg;
433 unsigned pkt_idx, buf_idx;
436 for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
438 /* processing a split packet */
439 end->next = rx_bufs[buf_idx];
440 rx_bufs[buf_idx]->data_len += rxq->crc_len;
443 start->pkt_len += rx_bufs[buf_idx]->data_len;
446 if (!split_flags[buf_idx]) {
447 /* it's the last packet of the set */
448 start->hash = end->hash;
449 start->ol_flags = end->ol_flags;
450 /* we need to strip crc for the whole packet */
451 start->pkt_len -= rxq->crc_len;
452 if (end->data_len > rxq->crc_len)
453 end->data_len -= rxq->crc_len;
455 /* free up last mbuf */
456 struct rte_mbuf *secondlast = start;
459 while (secondlast->next != end)
460 secondlast = secondlast->next;
461 secondlast->data_len -= (rxq->crc_len -
463 secondlast->next = NULL;
464 rte_pktmbuf_free_seg(end);
467 pkts[pkt_idx++] = start;
471 /* not processing a split packet */
472 if (!split_flags[buf_idx]) {
473 /* not a split packet, save and skip */
474 pkts[pkt_idx++] = rx_bufs[buf_idx];
477 end = start = rx_bufs[buf_idx];
478 rx_bufs[buf_idx]->data_len += rxq->crc_len;
479 rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
483 /* save the partial packet for next time */
484 rxq->pkt_first_seg = start;
485 rxq->pkt_last_seg = end;
486 memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
491 * vPMD receive routine that reassembles scattered packets
494 * - don't support ol_flags for rss and csum err
495 * - now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
498 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
501 struct ixgbe_rx_queue *rxq = rx_queue;
502 uint8_t split_flags[RTE_IXGBE_VPMD_RX_BURST] = {0};
504 /* get some new buffers */
505 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
510 /* happy day case, full burst + no packets to be joined */
511 const uint64_t *split_fl64 = (uint64_t *)split_flags;
512 if (rxq->pkt_first_seg == NULL &&
513 split_fl64[0] == 0 && split_fl64[1] == 0 &&
514 split_fl64[2] == 0 && split_fl64[3] == 0)
517 /* reassemble any packets that need reassembly*/
519 if (rxq->pkt_first_seg == NULL) {
520 /* find the first split flag, and only reassemble then*/
521 while (i < nb_bufs && !split_flags[i])
526 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
531 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
532 struct rte_mbuf *pkt, uint64_t flags)
534 __m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
535 flags | pkt->data_len,
536 pkt->buf_physaddr + pkt->data_off);
537 _mm_store_si128((__m128i *)&txdp->read, descriptor);
541 vtx(volatile union ixgbe_adv_tx_desc *txdp,
542 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
545 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
546 vtx1(txdp, *pkt, flags);
549 static inline int __attribute__((always_inline))
550 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
552 struct ixgbe_tx_entry_v *txep;
557 struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
559 /* check DD bit on threshold descriptor */
560 status = txq->tx_ring[txq->tx_next_dd].wb.status;
561 if (!(status & IXGBE_ADVTXD_STAT_DD))
564 n = txq->tx_rs_thresh;
567 * first buffer to free from S/W ring is at index
568 * tx_next_dd - (tx_rs_thresh-1)
570 txep = &txq->sw_ring_v[txq->tx_next_dd - (n - 1)];
571 m = __rte_pktmbuf_prefree_seg(txep[0].mbuf);
572 if (likely(m != NULL)) {
575 for (i = 1; i < n; i++) {
576 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
577 if (likely(m != NULL)) {
578 if (likely(m->pool == free[0]->pool))
581 rte_mempool_put_bulk(free[0]->pool,
582 (void *)free, nb_free);
588 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
590 for (i = 1; i < n; i++) {
591 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
593 rte_mempool_put(m->pool, m);
597 /* buffers were freed, update counters */
598 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
599 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
600 if (txq->tx_next_dd >= txq->nb_tx_desc)
601 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
603 return txq->tx_rs_thresh;
606 static inline void __attribute__((always_inline))
607 tx_backlog_entry(struct ixgbe_tx_entry_v *txep,
608 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
611 for (i = 0; i < (int)nb_pkts; ++i)
612 txep[i].mbuf = tx_pkts[i];
616 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
619 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
620 volatile union ixgbe_adv_tx_desc *txdp;
621 struct ixgbe_tx_entry_v *txep;
622 uint16_t n, nb_commit, tx_id;
623 uint64_t flags = DCMD_DTYP_FLAGS;
624 uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
627 if (unlikely(nb_pkts > RTE_IXGBE_VPMD_TX_BURST))
628 nb_pkts = RTE_IXGBE_VPMD_TX_BURST;
630 if (txq->nb_tx_free < txq->tx_free_thresh)
631 ixgbe_tx_free_bufs(txq);
633 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
634 if (unlikely(nb_pkts == 0))
637 tx_id = txq->tx_tail;
638 txdp = &txq->tx_ring[tx_id];
639 txep = &txq->sw_ring_v[tx_id];
641 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
643 n = (uint16_t)(txq->nb_tx_desc - tx_id);
644 if (nb_commit >= n) {
646 tx_backlog_entry(txep, tx_pkts, n);
648 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
649 vtx1(txdp, *tx_pkts, flags);
651 vtx1(txdp, *tx_pkts++, rs);
653 nb_commit = (uint16_t)(nb_commit - n);
656 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
658 /* avoid reach the end of ring */
659 txdp = &(txq->tx_ring[tx_id]);
660 txep = &txq->sw_ring_v[tx_id];
663 tx_backlog_entry(txep, tx_pkts, nb_commit);
665 vtx(txdp, tx_pkts, nb_commit, flags);
667 tx_id = (uint16_t)(tx_id + nb_commit);
668 if (tx_id > txq->tx_next_rs) {
669 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
670 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
671 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
675 txq->tx_tail = tx_id;
677 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
682 static void __attribute__((cold))
683 ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
686 struct ixgbe_tx_entry_v *txe;
687 const uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);
689 if (txq->sw_ring == NULL || txq->nb_tx_free == max_desc)
692 /* release the used mbufs in sw_ring */
693 for (i = txq->tx_next_dd - (txq->tx_rs_thresh - 1);
695 i = (i + 1) & max_desc) {
696 txe = &txq->sw_ring_v[i];
697 rte_pktmbuf_free_seg(txe->mbuf);
699 txq->nb_tx_free = max_desc;
702 for (i = 0; i < txq->nb_tx_desc; i++) {
703 txe = &txq->sw_ring_v[i];
708 void __attribute__((cold))
709 ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
711 const unsigned mask = rxq->nb_rx_desc - 1;
714 if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_rx_desc)
717 /* free all mbufs that are valid in the ring */
718 for (i = rxq->rx_tail; i != rxq->rxrearm_start; i = (i + 1) & mask)
719 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
720 rxq->rxrearm_nb = rxq->nb_rx_desc;
722 /* set all entries to NULL */
723 memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);
726 static void __attribute__((cold))
727 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
732 if (txq->sw_ring != NULL) {
733 rte_free(txq->sw_ring_v - 1);
734 txq->sw_ring_v = NULL;
738 static void __attribute__((cold))
739 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
741 static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
742 struct ixgbe_tx_entry_v *txe = txq->sw_ring_v;
745 /* Zero out HW ring memory */
746 for (i = 0; i < txq->nb_tx_desc; i++)
747 txq->tx_ring[i] = zeroed_desc;
749 /* Initialize SW ring entries */
750 for (i = 0; i < txq->nb_tx_desc; i++) {
751 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
752 txd->wb.status = IXGBE_TXD_STAT_DD;
756 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
757 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
762 * Always allow 1 descriptor to be un-allocated to avoid
763 * a H/W race condition
765 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
766 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
768 memset((void *)&txq->ctx_cache, 0,
769 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
772 static const struct ixgbe_txq_ops vec_txq_ops = {
773 .release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
774 .free_swring = ixgbe_tx_free_swring,
775 .reset = ixgbe_reset_tx_queue,
778 int __attribute__((cold))
779 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
782 struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
785 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
786 mb_def.port = rxq->port_id;
787 rte_mbuf_refcnt_set(&mb_def, 1);
789 /* prevent compiler reordering: rearm_data covers previous fields */
790 rte_compiler_barrier();
791 p = (uintptr_t)&mb_def.rearm_data;
792 rxq->mbuf_initializer = *(uint64_t *)p;
796 int __attribute__((cold))
797 ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
799 if (txq->sw_ring_v == NULL)
802 /* leave the first one for overflow */
803 txq->sw_ring_v = txq->sw_ring_v + 1;
804 txq->ops = &vec_txq_ops;
809 int __attribute__((cold))
810 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
812 #ifndef RTE_LIBRTE_IEEE1588
813 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
814 struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
816 #ifndef RTE_IXGBE_RX_OLFLAGS_ENABLE
817 /* whithout rx ol_flags, no VP flag report */
818 if (rxmode->hw_vlan_strip != 0 ||
819 rxmode->hw_vlan_extend != 0)
823 /* no fdir support */
824 if (fconf->mode != RTE_FDIR_MODE_NONE)
828 * - no csum error report support
829 * - no header split support
831 if (rxmode->hw_ip_checksum == 1 ||
832 rxmode->header_split == 1)