4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "ixgbe_ethdev.h"
39 #include "ixgbe_rxtx.h"
41 #include <tmmintrin.h>
43 #ifndef __INTEL_COMPILER
44 #pragma GCC diagnostic ignored "-Wcast-qual"
48 ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
52 volatile union ixgbe_adv_rx_desc *rxdp;
53 struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
54 struct rte_mbuf *mb0, *mb1;
55 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
56 RTE_PKTMBUF_HEADROOM);
57 __m128i dma_addr0, dma_addr1;
59 const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);
61 rxdp = rxq->rx_ring + rxq->rxrearm_start;
63 /* Pull 'n' more MBUFs into the software ring */
64 if (rte_mempool_get_bulk(rxq->mb_pool,
66 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
67 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
69 dma_addr0 = _mm_setzero_si128();
70 for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
71 rxep[i].mbuf = &rxq->fake_mbuf;
72 _mm_store_si128((__m128i *)&rxdp[i].read,
76 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
77 RTE_IXGBE_RXQ_REARM_THRESH;
81 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
82 for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
83 __m128i vaddr0, vaddr1;
90 * Flush mbuf with pkt template.
91 * Data to be rearmed is 6 bytes long.
92 * Though, RX will overwrite ol_flags that are coming next
93 * anyway. So overwrite whole 8 bytes with one load:
94 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
96 p0 = (uintptr_t)&mb0->rearm_data;
97 *(uint64_t *)p0 = rxq->mbuf_initializer;
98 p1 = (uintptr_t)&mb1->rearm_data;
99 *(uint64_t *)p1 = rxq->mbuf_initializer;
101 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
102 vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
103 vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
105 /* convert pa to dma_addr hdr/data */
106 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
107 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
109 /* add headroom to pa values */
110 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
111 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
113 /* set Header Buffer Address to zero */
114 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
115 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
117 /* flush desc with pa dma_addr */
118 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
119 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
122 rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
123 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
124 rxq->rxrearm_start = 0;
126 rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
128 rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
129 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
131 /* Update the tail pointer on the NIC */
132 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
135 /* Handling the offload flags (olflags) field takes computation
136 * time when receiving packets. Therefore we provide a flag to disable
137 * the processing of the olflags field when they are not needed. This
138 * gives improved performance, at the cost of losing the offload info
139 * in the received packet
141 #ifdef RTE_IXGBE_RX_OLFLAGS_ENABLE
143 #define VTAG_SHIFT (3)
146 desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
148 __m128i ptype0, ptype1, vtag0, vtag1;
154 /* pkt type + vlan olflags mask */
155 const __m128i pkttype_msk = _mm_set_epi16(
156 0x0000, 0x0000, 0x0000, 0x0000,
157 PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT,
158 PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT);
160 /* mask everything except rss type */
161 const __m128i rsstype_msk = _mm_set_epi16(
162 0x0000, 0x0000, 0x0000, 0x0000,
163 0x000F, 0x000F, 0x000F, 0x000F);
165 /* map rss type to rss hash flag */
166 const __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,
167 0, 0, 0, PKT_RX_RSS_HASH,
168 PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
169 PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
171 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
172 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
173 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
174 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
176 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
177 ptype0 = _mm_and_si128(ptype0, rsstype_msk);
178 ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
180 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
181 vtag1 = _mm_srli_epi16(vtag1, VTAG_SHIFT);
182 vtag1 = _mm_and_si128(vtag1, pkttype_msk);
184 vtag1 = _mm_or_si128(ptype0, vtag1);
185 vol.dword = _mm_cvtsi128_si64(vtag1);
187 rx_pkts[0]->ol_flags = vol.e[0];
188 rx_pkts[1]->ol_flags = vol.e[1];
189 rx_pkts[2]->ol_flags = vol.e[2];
190 rx_pkts[3]->ol_flags = vol.e[3];
193 #define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
197 * vPMD raw receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
200 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
201 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
203 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
204 * - don't support ol_flags for rss and csum err
206 static inline uint16_t
207 _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
208 uint16_t nb_pkts, uint8_t *split_packet)
210 volatile union ixgbe_adv_rx_desc *rxdp;
211 struct ixgbe_rx_entry *sw_ring;
212 uint16_t nb_pkts_recd;
216 __m128i crc_adjust = _mm_set_epi16(
217 0, 0, 0, /* ignore non-length fields */
218 -rxq->crc_len, /* sub crc on data_len */
219 0, /* ignore high-16bits of pkt_len */
220 -rxq->crc_len, /* sub crc on pkt_len */
221 0, 0 /* ignore pkt_type field */
223 __m128i dd_check, eop_check;
225 /* nb_pkts shall be less equal than RTE_IXGBE_MAX_RX_BURST */
226 nb_pkts = RTE_MIN(nb_pkts, RTE_IXGBE_MAX_RX_BURST);
228 /* nb_pkts has to be floor-aligned to RTE_IXGBE_DESCS_PER_LOOP */
229 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_IXGBE_DESCS_PER_LOOP);
231 /* Just the act of getting into the function from the application is
232 * going to cost about 7 cycles
234 rxdp = rxq->rx_ring + rxq->rx_tail;
236 _mm_prefetch((const void *)rxdp, _MM_HINT_T0);
238 /* See if we need to rearm the RX queue - gives the prefetch a bit
241 if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
242 ixgbe_rxq_rearm(rxq);
244 /* Before we start moving massive data around, check to see if
245 * there is actually a packet available
247 if (!(rxdp->wb.upper.status_error &
248 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
251 /* 4 packets DD mask */
252 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
254 /* 4 packets EOP mask */
255 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
257 /* mask to shuffle from desc. to mbuf */
258 shuf_msk = _mm_set_epi8(
259 7, 6, 5, 4, /* octet 4~7, 32bits rss */
260 15, 14, /* octet 14~15, low 16 bits vlan_macip */
261 13, 12, /* octet 12~13, 16 bits data_len */
262 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
263 13, 12, /* octet 12~13, low 16 bits pkt_len */
264 0xFF, 0xFF, /* skip 32 bit pkt_type */
268 /* Cache is empty -> need to scan the buffer rings, but first move
269 * the next 'n' mbufs into the cache
271 sw_ring = &rxq->sw_ring[rxq->rx_tail];
273 /* A. load 4 packet in one loop
274 * [A*. mask out 4 unused dirty field in desc]
275 * B. copy 4 mbuf point from swring to rx_pkts
276 * C. calc the number of DD bits among the 4 packets
277 * [C*. extract the end-of-packet bit, if requested]
278 * D. fill info. from desc to mbuf
280 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
281 pos += RTE_IXGBE_DESCS_PER_LOOP,
282 rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
283 __m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
284 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
285 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
286 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
288 /* B.1 load 1 mbuf point */
289 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
291 /* Read desc statuses backwards to avoid race condition */
292 /* A.1 load 4 pkts desc */
293 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
295 /* B.2 copy 2 mbuf point into rx_pkts */
296 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
298 /* B.1 load 1 mbuf point */
299 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
301 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
302 /* B.1 load 2 mbuf point */
303 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
304 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
306 /* B.2 copy 2 mbuf point into rx_pkts */
307 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
310 rte_prefetch0(&rx_pkts[pos]->cacheline1);
311 rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
312 rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
313 rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
316 /* avoid compiler reorder optimization */
317 rte_compiler_barrier();
319 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
320 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
321 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
323 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
324 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
325 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
327 /* C.1 4=>2 filter staterr info only */
328 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
329 /* C.1 4=>2 filter staterr info only */
330 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
332 /* set ol_flags with vlan packet type */
333 desc_to_olflags_v(descs, &rx_pkts[pos]);
335 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
336 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
337 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
339 /* C.2 get 4 pkts staterr value */
340 zero = _mm_xor_si128(dd_check, dd_check);
341 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
343 /* D.3 copy final 3,4 data to rx_pkts */
344 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
346 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
349 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
350 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
351 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
353 /* C* extract and record EOP bit */
355 __m128i eop_shuf_mask = _mm_set_epi8(
356 0xFF, 0xFF, 0xFF, 0xFF,
357 0xFF, 0xFF, 0xFF, 0xFF,
358 0xFF, 0xFF, 0xFF, 0xFF,
359 0x04, 0x0C, 0x00, 0x08
362 /* and with mask to extract bits, flipping 1-0 */
363 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
364 /* the staterr values are not in order, as the count
365 * count of dd bits doesn't care. However, for end of
366 * packet tracking, we do care, so shuffle. This also
367 * compresses the 32-bit values to 8-bit
369 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
370 /* store the resulting 32-bit value */
371 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
372 split_packet += RTE_IXGBE_DESCS_PER_LOOP;
374 /* zero-out next pointers */
375 rx_pkts[pos]->next = NULL;
376 rx_pkts[pos + 1]->next = NULL;
377 rx_pkts[pos + 2]->next = NULL;
378 rx_pkts[pos + 3]->next = NULL;
381 /* C.3 calc available number of desc */
382 staterr = _mm_and_si128(staterr, dd_check);
383 staterr = _mm_packs_epi32(staterr, zero);
385 /* D.3 copy final 1,2 data to rx_pkts */
386 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
388 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
391 /* C.4 calc avaialbe number of desc */
392 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
394 if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
398 /* Update our internal tail pointer */
399 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
400 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
401 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
407 * vPMD receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
410 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
411 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
413 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
414 * - don't support ol_flags for rss and csum err
417 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
420 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
423 static inline uint16_t
424 reassemble_packets(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_bufs,
425 uint16_t nb_bufs, uint8_t *split_flags)
427 struct rte_mbuf *pkts[nb_bufs]; /*finished pkts*/
428 struct rte_mbuf *start = rxq->pkt_first_seg;
429 struct rte_mbuf *end = rxq->pkt_last_seg;
430 unsigned int pkt_idx, buf_idx;
432 for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
434 /* processing a split packet */
435 end->next = rx_bufs[buf_idx];
436 rx_bufs[buf_idx]->data_len += rxq->crc_len;
439 start->pkt_len += rx_bufs[buf_idx]->data_len;
442 if (!split_flags[buf_idx]) {
443 /* it's the last packet of the set */
444 start->hash = end->hash;
445 start->ol_flags = end->ol_flags;
446 /* we need to strip crc for the whole packet */
447 start->pkt_len -= rxq->crc_len;
448 if (end->data_len > rxq->crc_len)
449 end->data_len -= rxq->crc_len;
451 /* free up last mbuf */
452 struct rte_mbuf *secondlast = start;
455 while (secondlast->next != end)
456 secondlast = secondlast->next;
457 secondlast->data_len -= (rxq->crc_len -
459 secondlast->next = NULL;
460 rte_pktmbuf_free_seg(end);
463 pkts[pkt_idx++] = start;
467 /* not processing a split packet */
468 if (!split_flags[buf_idx]) {
469 /* not a split packet, save and skip */
470 pkts[pkt_idx++] = rx_bufs[buf_idx];
473 end = start = rx_bufs[buf_idx];
474 rx_bufs[buf_idx]->data_len += rxq->crc_len;
475 rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
479 /* save the partial packet for next time */
480 rxq->pkt_first_seg = start;
481 rxq->pkt_last_seg = end;
482 memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
487 * vPMD receive routine that reassembles scattered packets
490 * - don't support ol_flags for rss and csum err
491 * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
492 * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
494 * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
497 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
500 struct ixgbe_rx_queue *rxq = rx_queue;
501 uint8_t split_flags[RTE_IXGBE_MAX_RX_BURST] = {0};
503 /* get some new buffers */
504 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
509 /* happy day case, full burst + no packets to be joined */
510 const uint64_t *split_fl64 = (uint64_t *)split_flags;
511 if (rxq->pkt_first_seg == NULL &&
512 split_fl64[0] == 0 && split_fl64[1] == 0 &&
513 split_fl64[2] == 0 && split_fl64[3] == 0)
516 /* reassemble any packets that need reassembly*/
518 if (rxq->pkt_first_seg == NULL) {
519 /* find the first split flag, and only reassemble then*/
520 while (i < nb_bufs && !split_flags[i])
525 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
530 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
531 struct rte_mbuf *pkt, uint64_t flags)
533 __m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
534 flags | pkt->data_len,
535 pkt->buf_physaddr + pkt->data_off);
536 _mm_store_si128((__m128i *)&txdp->read, descriptor);
540 vtx(volatile union ixgbe_adv_tx_desc *txdp,
541 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
545 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
546 vtx1(txdp, *pkt, flags);
549 static inline int __attribute__((always_inline))
550 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
552 struct ixgbe_tx_entry_v *txep;
557 struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
559 /* check DD bit on threshold descriptor */
560 status = txq->tx_ring[txq->tx_next_dd].wb.status;
561 if (!(status & IXGBE_ADVTXD_STAT_DD))
564 n = txq->tx_rs_thresh;
567 * first buffer to free from S/W ring is at index
568 * tx_next_dd - (tx_rs_thresh-1)
570 txep = &txq->sw_ring_v[txq->tx_next_dd - (n - 1)];
571 m = __rte_pktmbuf_prefree_seg(txep[0].mbuf);
572 if (likely(m != NULL)) {
575 for (i = 1; i < n; i++) {
576 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
577 if (likely(m != NULL)) {
578 if (likely(m->pool == free[0]->pool))
581 rte_mempool_put_bulk(free[0]->pool,
582 (void *)free, nb_free);
588 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
590 for (i = 1; i < n; i++) {
591 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
593 rte_mempool_put(m->pool, m);
597 /* buffers were freed, update counters */
598 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
599 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
600 if (txq->tx_next_dd >= txq->nb_tx_desc)
601 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
603 return txq->tx_rs_thresh;
606 static inline void __attribute__((always_inline))
607 tx_backlog_entry(struct ixgbe_tx_entry_v *txep,
608 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
612 for (i = 0; i < (int)nb_pkts; ++i)
613 txep[i].mbuf = tx_pkts[i];
617 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
620 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
621 volatile union ixgbe_adv_tx_desc *txdp;
622 struct ixgbe_tx_entry_v *txep;
623 uint16_t n, nb_commit, tx_id;
624 uint64_t flags = DCMD_DTYP_FLAGS;
625 uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
628 /* cross rx_thresh boundary is not allowed */
629 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
631 if (txq->nb_tx_free < txq->tx_free_thresh)
632 ixgbe_tx_free_bufs(txq);
634 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
635 if (unlikely(nb_pkts == 0))
638 tx_id = txq->tx_tail;
639 txdp = &txq->tx_ring[tx_id];
640 txep = &txq->sw_ring_v[tx_id];
642 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
644 n = (uint16_t)(txq->nb_tx_desc - tx_id);
645 if (nb_commit >= n) {
647 tx_backlog_entry(txep, tx_pkts, n);
649 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
650 vtx1(txdp, *tx_pkts, flags);
652 vtx1(txdp, *tx_pkts++, rs);
654 nb_commit = (uint16_t)(nb_commit - n);
657 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
659 /* avoid reach the end of ring */
660 txdp = &(txq->tx_ring[tx_id]);
661 txep = &txq->sw_ring_v[tx_id];
664 tx_backlog_entry(txep, tx_pkts, nb_commit);
666 vtx(txdp, tx_pkts, nb_commit, flags);
668 tx_id = (uint16_t)(tx_id + nb_commit);
669 if (tx_id > txq->tx_next_rs) {
670 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
671 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
672 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
676 txq->tx_tail = tx_id;
678 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
683 static void __attribute__((cold))
684 ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
687 struct ixgbe_tx_entry_v *txe;
688 const uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);
690 if (txq->sw_ring == NULL || txq->nb_tx_free == max_desc)
693 /* release the used mbufs in sw_ring */
694 for (i = txq->tx_next_dd - (txq->tx_rs_thresh - 1);
696 i = (i + 1) & max_desc) {
697 txe = &txq->sw_ring_v[i];
698 rte_pktmbuf_free_seg(txe->mbuf);
700 txq->nb_tx_free = max_desc;
703 for (i = 0; i < txq->nb_tx_desc; i++) {
704 txe = &txq->sw_ring_v[i];
709 void __attribute__((cold))
710 ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
712 const unsigned int mask = rxq->nb_rx_desc - 1;
715 if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_rx_desc)
718 /* free all mbufs that are valid in the ring */
719 for (i = rxq->rx_tail; i != rxq->rxrearm_start; i = (i + 1) & mask)
720 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
721 rxq->rxrearm_nb = rxq->nb_rx_desc;
723 /* set all entries to NULL */
724 memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);
727 static void __attribute__((cold))
728 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
733 if (txq->sw_ring != NULL) {
734 rte_free(txq->sw_ring_v - 1);
735 txq->sw_ring_v = NULL;
739 static void __attribute__((cold))
740 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
742 static const union ixgbe_adv_tx_desc zeroed_desc = { { 0 } };
743 struct ixgbe_tx_entry_v *txe = txq->sw_ring_v;
746 /* Zero out HW ring memory */
747 for (i = 0; i < txq->nb_tx_desc; i++)
748 txq->tx_ring[i] = zeroed_desc;
750 /* Initialize SW ring entries */
751 for (i = 0; i < txq->nb_tx_desc; i++) {
752 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
754 txd->wb.status = IXGBE_TXD_STAT_DD;
758 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
759 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
764 * Always allow 1 descriptor to be un-allocated to avoid
765 * a H/W race condition
767 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
768 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
770 memset((void *)&txq->ctx_cache, 0,
771 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
774 static const struct ixgbe_txq_ops vec_txq_ops = {
775 .release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
776 .free_swring = ixgbe_tx_free_swring,
777 .reset = ixgbe_reset_tx_queue,
780 int __attribute__((cold))
781 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
784 struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
787 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
788 mb_def.port = rxq->port_id;
789 rte_mbuf_refcnt_set(&mb_def, 1);
791 /* prevent compiler reordering: rearm_data covers previous fields */
792 rte_compiler_barrier();
793 p = (uintptr_t)&mb_def.rearm_data;
794 rxq->mbuf_initializer = *(uint64_t *)p;
798 int __attribute__((cold))
799 ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
801 if (txq->sw_ring_v == NULL)
804 /* leave the first one for overflow */
805 txq->sw_ring_v = txq->sw_ring_v + 1;
806 txq->ops = &vec_txq_ops;
811 int __attribute__((cold))
812 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
814 #ifndef RTE_LIBRTE_IEEE1588
815 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
816 struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
818 #ifndef RTE_IXGBE_RX_OLFLAGS_ENABLE
819 /* whithout rx ol_flags, no VP flag report */
820 if (rxmode->hw_vlan_strip != 0 ||
821 rxmode->hw_vlan_extend != 0)
825 /* no fdir support */
826 if (fconf->mode != RTE_FDIR_MODE_NONE)
830 * - no csum error report support
831 * - no header split support
833 if (rxmode->hw_ip_checksum == 1 ||
834 rxmode->header_split == 1)