drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdint.h>
  35 #include <rte_ethdev.h>
  36 #include <rte_malloc.h>
  37
  38 #include "ixgbe_ethdev.h"
  39 #include "ixgbe_rxtx.h"
  40 #include "ixgbe_rxtx_vec_common.h"
  41
  42 #include <tmmintrin.h>
  43
  44 #ifndef __INTEL_COMPILER
  45 #pragma GCC diagnostic ignored "-Wcast-qual"
  46 #endif
  47
  48 static inline void
  49 ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
  50 {
  51         int i;
  52         uint16_t rx_id;
  53         volatile union ixgbe_adv_rx_desc *rxdp;
  54         struct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
  55         struct rte_mbuf *mb0, *mb1;
  56         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  57                         RTE_PKTMBUF_HEADROOM);
  58         __m128i dma_addr0, dma_addr1;
  59
  60         const __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);
  61
  62         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  63
  64         /* Pull 'n' more MBUFs into the software ring */
  65         if (rte_mempool_get_bulk(rxq->mb_pool,
  66                                  (void *)rxep,
  67                                  RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
  68                 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
  69                     rxq->nb_rx_desc) {
  70                         dma_addr0 = _mm_setzero_si128();
  71                         for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
  72                                 rxep[i].mbuf = &rxq->fake_mbuf;
  73                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  74                                                 dma_addr0);
  75                         }
  76                 }
  77                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  78                         RTE_IXGBE_RXQ_REARM_THRESH;
  79                 return;
  80         }
  81
  82         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  83         for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
  84                 __m128i vaddr0, vaddr1;
  85
  86                 mb0 = rxep[0].mbuf;
  87                 mb1 = rxep[1].mbuf;
  88
  89                 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
  90                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_physaddr) !=
  91                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  92                 vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
  93                 vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
  94
  95                 /* convert pa to dma_addr hdr/data */
  96                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
  97                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
  98
  99                 /* add headroom to pa values */
 100                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
 101                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
 102
 103                 /* set Header Buffer Address to zero */
 104                 dma_addr0 =  _mm_and_si128(dma_addr0, hba_msk);
 105                 dma_addr1 =  _mm_and_si128(dma_addr1, hba_msk);
 106
 107                 /* flush desc with pa dma_addr */
 108                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
 109                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
 110         }
 111
 112         rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
 113         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 114                 rxq->rxrearm_start = 0;
 115
 116         rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
 117
 118         rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
 119                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 120
 121         /* Update the tail pointer on the NIC */
 122         IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
 123 }
 124
 125 #ifdef RTE_LIBRTE_SECURITY
 126 static inline void
 127 desc_to_olflags_v_ipsec(__m128i descs[4], struct rte_mbuf **rx_pkts)
 128 {
 129         __m128i sterr0, sterr1, sterr2, sterr3;
 130         __m128i tmp1, tmp2, tmp3, tmp4;
 131         __m128i rearm0, rearm1, rearm2, rearm3;
 132
 133         const __m128i ipsec_sterr_msk = _mm_set_epi32(
 134                 0, IXGBE_RXDADV_IPSEC_STATUS_SECP |
 135                         IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED,
 136                 0, 0);
 137         const __m128i ipsec_proc_msk  = _mm_set_epi32(
 138                 0, IXGBE_RXDADV_IPSEC_STATUS_SECP, 0, 0);
 139         const __m128i ipsec_err_flag  = _mm_set_epi32(
 140                 0, PKT_RX_SEC_OFFLOAD_FAILED | PKT_RX_SEC_OFFLOAD,
 141                 0, 0);
 142         const __m128i ipsec_proc_flag = _mm_set_epi32(
 143                 0, PKT_RX_SEC_OFFLOAD, 0, 0);
 144
 145         rearm0 = _mm_load_si128((__m128i *)&rx_pkts[0]->rearm_data);
 146         rearm1 = _mm_load_si128((__m128i *)&rx_pkts[1]->rearm_data);
 147         rearm2 = _mm_load_si128((__m128i *)&rx_pkts[2]->rearm_data);
 148         rearm3 = _mm_load_si128((__m128i *)&rx_pkts[3]->rearm_data);
 149         sterr0 = _mm_and_si128(descs[0], ipsec_sterr_msk);
 150         sterr1 = _mm_and_si128(descs[1], ipsec_sterr_msk);
 151         sterr2 = _mm_and_si128(descs[2], ipsec_sterr_msk);
 152         sterr3 = _mm_and_si128(descs[3], ipsec_sterr_msk);
 153         tmp1 = _mm_cmpeq_epi32(sterr0, ipsec_sterr_msk);
 154         tmp2 = _mm_cmpeq_epi32(sterr0, ipsec_proc_msk);
 155         tmp3 = _mm_cmpeq_epi32(sterr1, ipsec_sterr_msk);
 156         tmp4 = _mm_cmpeq_epi32(sterr1, ipsec_proc_msk);
 157         sterr0 = _mm_or_si128(_mm_and_si128(tmp1, ipsec_err_flag),
 158                                 _mm_and_si128(tmp2, ipsec_proc_flag));
 159         sterr1 = _mm_or_si128(_mm_and_si128(tmp3, ipsec_err_flag),
 160                                 _mm_and_si128(tmp4, ipsec_proc_flag));
 161         tmp1 = _mm_cmpeq_epi32(sterr2, ipsec_sterr_msk);
 162         tmp2 = _mm_cmpeq_epi32(sterr2, ipsec_proc_msk);
 163         tmp3 = _mm_cmpeq_epi32(sterr3, ipsec_sterr_msk);
 164         tmp4 = _mm_cmpeq_epi32(sterr3, ipsec_proc_msk);
 165         sterr2 = _mm_or_si128(_mm_and_si128(tmp1, ipsec_err_flag),
 166                                 _mm_and_si128(tmp2, ipsec_proc_flag));
 167         sterr3 = _mm_or_si128(_mm_and_si128(tmp3, ipsec_err_flag),
 168                                 _mm_and_si128(tmp4, ipsec_proc_flag));
 169         rearm0 = _mm_or_si128(rearm0, sterr0);
 170         rearm1 = _mm_or_si128(rearm1, sterr1);
 171         rearm2 = _mm_or_si128(rearm2, sterr2);
 172         rearm3 = _mm_or_si128(rearm3, sterr3);
 173         _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
 174         _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
 175         _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
 176         _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
 177 }
 178 #endif
 179
 180 static inline void
 181 desc_to_olflags_v(__m128i descs[4], __m128i mbuf_init, uint8_t vlan_flags,
 182         struct rte_mbuf **rx_pkts)
 183 {
 184         __m128i ptype0, ptype1, vtag0, vtag1, csum;
 185         __m128i rearm0, rearm1, rearm2, rearm3;
 186
 187         /* mask everything except rss type */
 188         const __m128i rsstype_msk = _mm_set_epi16(
 189                         0x0000, 0x0000, 0x0000, 0x0000,
 190                         0x000F, 0x000F, 0x000F, 0x000F);
 191
 192         /* mask the lower byte of ol_flags */
 193         const __m128i ol_flags_msk = _mm_set_epi16(
 194                         0x0000, 0x0000, 0x0000, 0x0000,
 195                         0x00FF, 0x00FF, 0x00FF, 0x00FF);
 196
 197         /* map rss type to rss hash flag */
 198         const __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,
 199                         0, 0, 0, PKT_RX_RSS_HASH,
 200                         PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
 201                         PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
 202
 203         /* mask everything except vlan present and l4/ip csum error */
 204         const __m128i vlan_csum_msk = _mm_set_epi16(
 205                 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
 206                 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
 207                 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
 208                 (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE) >> 16,
 209                 IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP,
 210                 IXGBE_RXD_STAT_VP, IXGBE_RXD_STAT_VP);
 211         /* map vlan present (0x8), IPE (0x2), L4E (0x1) to ol_flags */
 212         const __m128i vlan_csum_map_lo = _mm_set_epi8(
 213                 0, 0, 0, 0,
 214                 vlan_flags | PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
 215                 vlan_flags | PKT_RX_IP_CKSUM_BAD,
 216                 vlan_flags | PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
 217                 vlan_flags | PKT_RX_IP_CKSUM_GOOD,
 218                 0, 0, 0, 0,
 219                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
 220                 PKT_RX_IP_CKSUM_BAD,
 221                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
 222                 PKT_RX_IP_CKSUM_GOOD);
 223
 224         const __m128i vlan_csum_map_hi = _mm_set_epi8(
 225                 0, 0, 0, 0,
 226                 0, PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0,
 227                 PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t),
 228                 0, 0, 0, 0,
 229                 0, PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t), 0,
 230                 PKT_RX_L4_CKSUM_GOOD >> sizeof(uint8_t));
 231
 232         ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
 233         ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
 234         vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
 235         vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
 236
 237         ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
 238         ptype0 = _mm_and_si128(ptype0, rsstype_msk);
 239         ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
 240
 241         vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
 242         vtag1 = _mm_and_si128(vtag1, vlan_csum_msk);
 243
 244         /* csum bits are in the most significant, to use shuffle we need to
 245          * shift them. Change mask to 0xc000 to 0x0003.
 246          */
 247         csum = _mm_srli_epi16(vtag1, 14);
 248
 249         /* now or the most significant 64 bits containing the checksum
 250          * flags with the vlan present flags.
 251          */
 252         csum = _mm_srli_si128(csum, 8);
 253         vtag1 = _mm_or_si128(csum, vtag1);
 254
 255         /* convert VP, IPE, L4E to ol_flags */
 256         vtag0 = _mm_shuffle_epi8(vlan_csum_map_hi, vtag1);
 257         vtag0 = _mm_slli_epi16(vtag0, sizeof(uint8_t));
 258
 259         vtag1 = _mm_shuffle_epi8(vlan_csum_map_lo, vtag1);
 260         vtag1 = _mm_and_si128(vtag1, ol_flags_msk);
 261         vtag1 = _mm_or_si128(vtag0, vtag1);
 262
 263         vtag1 = _mm_or_si128(ptype0, vtag1);
 264
 265         /*
 266          * At this point, we have the 4 sets of flags in the low 64-bits
 267          * of vtag1 (4x16).
 268          * We want to extract these, and merge them with the mbuf init data
 269          * so we can do a single 16-byte write to the mbuf to set the flags
 270          * and all the other initialization fields. Extracting the
 271          * appropriate flags means that we have to do a shift and blend for
 272          * each mbuf before we do the write.
 273          */
 274         rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 8), 0x10);
 275         rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 6), 0x10);
 276         rearm2 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 4), 0x10);
 277         rearm3 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vtag1, 2), 0x10);
 278
 279         /* write the rearm data and the olflags in one write */
 280         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 281                         offsetof(struct rte_mbuf, rearm_data) + 8);
 282         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 283                         RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
 284         _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
 285         _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
 286         _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
 287         _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
 288 }
 289
 290 static inline uint32_t get_packet_type(int index,
 291                                        uint32_t pkt_info,
 292                                        uint32_t etqf_check,
 293                                        uint32_t tunnel_check)
 294 {
 295         if (etqf_check & (0x02 << (index * RTE_IXGBE_DESCS_PER_LOOP)))
 296                 return RTE_PTYPE_UNKNOWN;
 297
 298         if (tunnel_check & (0x02 << (index * RTE_IXGBE_DESCS_PER_LOOP))) {
 299                 pkt_info &= IXGBE_PACKET_TYPE_MASK_TUNNEL;
 300                 return ptype_table_tn[pkt_info];
 301         }
 302
 303         pkt_info &= IXGBE_PACKET_TYPE_MASK_82599;
 304         return ptype_table[pkt_info];
 305 }
 306
 307 static inline void
 308 desc_to_ptype_v(__m128i descs[4], uint16_t pkt_type_mask,
 309                 struct rte_mbuf **rx_pkts)
 310 {
 311         __m128i etqf_mask = _mm_set_epi64x(0x800000008000LL, 0x800000008000LL);
 312         __m128i ptype_mask = _mm_set_epi32(
 313                 pkt_type_mask, pkt_type_mask, pkt_type_mask, pkt_type_mask);
 314         __m128i tunnel_mask =
 315                 _mm_set_epi64x(0x100000001000LL, 0x100000001000LL);
 316
 317         uint32_t etqf_check, tunnel_check, pkt_info;
 318
 319         __m128i ptype0 = _mm_unpacklo_epi32(descs[0], descs[2]);
 320         __m128i ptype1 = _mm_unpacklo_epi32(descs[1], descs[3]);
 321
 322         /* interleave low 32 bits,
 323          * now we have 4 ptypes in a XMM register
 324          */
 325         ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
 326
 327         /* create a etqf bitmask based on the etqf bit. */
 328         etqf_check = _mm_movemask_epi8(_mm_and_si128(ptype0, etqf_mask));
 329
 330         /* shift left by IXGBE_PACKET_TYPE_SHIFT, and apply ptype mask */
 331         ptype0 = _mm_and_si128(_mm_srli_epi32(ptype0, IXGBE_PACKET_TYPE_SHIFT),
 332                                ptype_mask);
 333
 334         /* create a tunnel bitmask based on the tunnel bit */
 335         tunnel_check = _mm_movemask_epi8(
 336                 _mm_slli_epi32(_mm_and_si128(ptype0, tunnel_mask), 0x3));
 337
 338         pkt_info = _mm_extract_epi32(ptype0, 0);
 339         rx_pkts[0]->packet_type =
 340                 get_packet_type(0, pkt_info, etqf_check, tunnel_check);
 341         pkt_info = _mm_extract_epi32(ptype0, 1);
 342         rx_pkts[1]->packet_type =
 343                 get_packet_type(1, pkt_info, etqf_check, tunnel_check);
 344         pkt_info = _mm_extract_epi32(ptype0, 2);
 345         rx_pkts[2]->packet_type =
 346                 get_packet_type(2, pkt_info, etqf_check, tunnel_check);
 347         pkt_info = _mm_extract_epi32(ptype0, 3);
 348         rx_pkts[3]->packet_type =
 349                 get_packet_type(3, pkt_info, etqf_check, tunnel_check);
 350 }
 351
 352 /*
 353  * vPMD raw receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
 354  *
 355  * Notice:
 356  * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
 357  * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
 358  *   numbers of DD bit
 359  * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
 360  */
 361 static inline uint16_t
 362 _recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 363                 uint16_t nb_pkts, uint8_t *split_packet)
 364 {
 365         volatile union ixgbe_adv_rx_desc *rxdp;
 366         struct ixgbe_rx_entry *sw_ring;
 367         uint16_t nb_pkts_recd;
 368 #ifdef RTE_LIBRTE_SECURITY
 369         uint8_t use_ipsec = rxq->using_ipsec;
 370 #endif
 371         int pos;
 372         uint64_t var;
 373         __m128i shuf_msk;
 374         __m128i crc_adjust = _mm_set_epi16(
 375                                 0, 0, 0,    /* ignore non-length fields */
 376                                 -rxq->crc_len, /* sub crc on data_len */
 377                                 0,          /* ignore high-16bits of pkt_len */
 378                                 -rxq->crc_len, /* sub crc on pkt_len */
 379                                 0, 0            /* ignore pkt_type field */
 380                         );
 381         /*
 382          * compile-time check the above crc_adjust layout is correct.
 383          * NOTE: the first field (lowest address) is given last in set_epi16
 384          * call above.
 385          */
 386         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 387                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 388         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 389                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 390         __m128i dd_check, eop_check;
 391         __m128i mbuf_init;
 392         uint8_t vlan_flags;
 393
 394         /* nb_pkts shall be less equal than RTE_IXGBE_MAX_RX_BURST */
 395         nb_pkts = RTE_MIN(nb_pkts, RTE_IXGBE_MAX_RX_BURST);
 396
 397         /* nb_pkts has to be floor-aligned to RTE_IXGBE_DESCS_PER_LOOP */
 398         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_IXGBE_DESCS_PER_LOOP);
 399
 400         /* Just the act of getting into the function from the application is
 401          * going to cost about 7 cycles
 402          */
 403         rxdp = rxq->rx_ring + rxq->rx_tail;
 404
 405         rte_prefetch0(rxdp);
 406
 407         /* See if we need to rearm the RX queue - gives the prefetch a bit
 408          * of time to act
 409          */
 410         if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
 411                 ixgbe_rxq_rearm(rxq);
 412
 413         /* Before we start moving massive data around, check to see if
 414          * there is actually a packet available
 415          */
 416         if (!(rxdp->wb.upper.status_error &
 417                                 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
 418                 return 0;
 419
 420         /* 4 packets DD mask */
 421         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
 422
 423         /* 4 packets EOP mask */
 424         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
 425
 426         /* mask to shuffle from desc. to mbuf */
 427         shuf_msk = _mm_set_epi8(
 428                 7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 429                 15, 14,      /* octet 14~15, low 16 bits vlan_macip */
 430                 13, 12,      /* octet 12~13, 16 bits data_len */
 431                 0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 432                 13, 12,      /* octet 12~13, low 16 bits pkt_len */
 433                 0xFF, 0xFF,  /* skip 32 bit pkt_type */
 434                 0xFF, 0xFF
 435                 );
 436         /*
 437          * Compile-time verify the shuffle mask
 438          * NOTE: some field positions already verified above, but duplicated
 439          * here for completeness in case of future modifications.
 440          */
 441         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 442                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 443         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 444                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 445         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 446                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 447         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 448                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 449
 450         mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
 451
 452         /* Cache is empty -> need to scan the buffer rings, but first move
 453          * the next 'n' mbufs into the cache
 454          */
 455         sw_ring = &rxq->sw_ring[rxq->rx_tail];
 456
 457         /* ensure these 2 flags are in the lower 8 bits */
 458         RTE_BUILD_BUG_ON((PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED) > UINT8_MAX);
 459         vlan_flags = rxq->vlan_flags & UINT8_MAX;
 460
 461         /* A. load 4 packet in one loop
 462          * [A*. mask out 4 unused dirty field in desc]
 463          * B. copy 4 mbuf point from swring to rx_pkts
 464          * C. calc the number of DD bits among the 4 packets
 465          * [C*. extract the end-of-packet bit, if requested]
 466          * D. fill info. from desc to mbuf
 467          */
 468         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
 469                         pos += RTE_IXGBE_DESCS_PER_LOOP,
 470                         rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
 471                 __m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
 472                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
 473                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
 474                 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
 475                 __m128i mbp1;
 476 #if defined(RTE_ARCH_X86_64)
 477                 __m128i mbp2;
 478 #endif
 479
 480                 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
 481                 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
 482
 483                 /* Read desc statuses backwards to avoid race condition */
 484                 /* A.1 load 4 pkts desc */
 485                 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
 486                 rte_compiler_barrier();
 487
 488                 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
 489                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
 490
 491 #if defined(RTE_ARCH_X86_64)
 492                 /* B.1 load 2 64 bit mbuf points */
 493                 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
 494 #endif
 495
 496                 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
 497                 rte_compiler_barrier();
 498                 /* B.1 load 2 mbuf point */
 499                 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
 500                 rte_compiler_barrier();
 501                 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
 502
 503 #if defined(RTE_ARCH_X86_64)
 504                 /* B.2 copy 2 mbuf point into rx_pkts  */
 505                 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
 506 #endif
 507
 508                 if (split_packet) {
 509                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
 510                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
 511                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
 512                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
 513                 }
 514
 515                 /* avoid compiler reorder optimization */
 516                 rte_compiler_barrier();
 517
 518                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
 519                 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
 520                 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
 521
 522                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
 523                 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
 524                 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
 525
 526                 /* C.1 4=>2 filter staterr info only */
 527                 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
 528                 /* C.1 4=>2 filter staterr info only */
 529                 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
 530
 531                 /* set ol_flags with vlan packet type */
 532                 desc_to_olflags_v(descs, mbuf_init, vlan_flags, &rx_pkts[pos]);
 533
 534 #ifdef RTE_LIBRTE_SECURITY
 535                 if (unlikely(use_ipsec))
 536                         desc_to_olflags_v_ipsec(descs, rx_pkts);
 537 #endif
 538
 539                 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
 540                 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
 541                 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
 542
 543                 /* C.2 get 4 pkts staterr value  */
 544                 zero = _mm_xor_si128(dd_check, dd_check);
 545                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
 546
 547                 /* D.3 copy final 3,4 data to rx_pkts */
 548                 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
 549                                 pkt_mb4);
 550                 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
 551                                 pkt_mb3);
 552
 553                 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
 554                 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
 555                 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
 556
 557                 /* C* extract and record EOP bit */
 558                 if (split_packet) {
 559                         __m128i eop_shuf_mask = _mm_set_epi8(
 560                                         0xFF, 0xFF, 0xFF, 0xFF,
 561                                         0xFF, 0xFF, 0xFF, 0xFF,
 562                                         0xFF, 0xFF, 0xFF, 0xFF,
 563                                         0x04, 0x0C, 0x00, 0x08
 564                                         );
 565
 566                         /* and with mask to extract bits, flipping 1-0 */
 567                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
 568                         /* the staterr values are not in order, as the count
 569                          * count of dd bits doesn't care. However, for end of
 570                          * packet tracking, we do care, so shuffle. This also
 571                          * compresses the 32-bit values to 8-bit
 572                          */
 573                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
 574                         /* store the resulting 32-bit value */
 575                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
 576                         split_packet += RTE_IXGBE_DESCS_PER_LOOP;
 577                 }
 578
 579                 /* C.3 calc available number of desc */
 580                 staterr = _mm_and_si128(staterr, dd_check);
 581                 staterr = _mm_packs_epi32(staterr, zero);
 582
 583                 /* D.3 copy final 1,2 data to rx_pkts */
 584                 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
 585                                 pkt_mb2);
 586                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 587                                 pkt_mb1);
 588
 589                 desc_to_ptype_v(descs, rxq->pkt_type_mask, &rx_pkts[pos]);
 590
 591                 /* C.4 calc avaialbe number of desc */
 592                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
 593                 nb_pkts_recd += var;
 594                 if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
 595                         break;
 596         }
 597
 598         /* Update our internal tail pointer */
 599         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
 600         rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
 601         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
 602
 603         return nb_pkts_recd;
 604 }
 605
 606 /*
 607  * vPMD receive routine, only accept(nb_pkts >= RTE_IXGBE_DESCS_PER_LOOP)
 608  *
 609  * Notice:
 610  * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
 611  * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
 612  *   numbers of DD bit
 613  * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
 614  */
 615 uint16_t
 616 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 617                 uint16_t nb_pkts)
 618 {
 619         return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
 620 }
 621
 622 /*
 623  * vPMD receive routine that reassembles scattered packets
 624  *
 625  * Notice:
 626  * - nb_pkts < RTE_IXGBE_DESCS_PER_LOOP, just return no packet
 627  * - nb_pkts > RTE_IXGBE_MAX_RX_BURST, only scan RTE_IXGBE_MAX_RX_BURST
 628  *   numbers of DD bit
 629  * - floor align nb_pkts to a RTE_IXGBE_DESC_PER_LOOP power-of-two
 630  */
 631 uint16_t
 632 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 633                 uint16_t nb_pkts)
 634 {
 635         struct ixgbe_rx_queue *rxq = rx_queue;
 636         uint8_t split_flags[RTE_IXGBE_MAX_RX_BURST] = {0};
 637
 638         /* get some new buffers */
 639         uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
 640                         split_flags);
 641         if (nb_bufs == 0)
 642                 return 0;
 643
 644         /* happy day case, full burst + no packets to be joined */
 645         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 646         if (rxq->pkt_first_seg == NULL &&
 647                         split_fl64[0] == 0 && split_fl64[1] == 0 &&
 648                         split_fl64[2] == 0 && split_fl64[3] == 0)
 649                 return nb_bufs;
 650
 651         /* reassemble any packets that need reassembly*/
 652         unsigned i = 0;
 653         if (rxq->pkt_first_seg == NULL) {
 654                 /* find the first split flag, and only reassemble then*/
 655                 while (i < nb_bufs && !split_flags[i])
 656                         i++;
 657                 if (i == nb_bufs)
 658                         return nb_bufs;
 659         }
 660         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 661                 &split_flags[i]);
 662 }
 663
 664 static inline void
 665 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
 666                 struct rte_mbuf *pkt, uint64_t flags)
 667 {
 668         __m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
 669                         flags | pkt->data_len,
 670                         pkt->buf_physaddr + pkt->data_off);
 671         _mm_store_si128((__m128i *)&txdp->read, descriptor);
 672 }
 673
 674 static inline void
 675 vtx(volatile union ixgbe_adv_tx_desc *txdp,
 676                 struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 677 {
 678         int i;
 679
 680         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
 681                 vtx1(txdp, *pkt, flags);
 682 }
 683
 684 uint16_t
 685 ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 686                            uint16_t nb_pkts)
 687 {
 688         struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
 689         volatile union ixgbe_adv_tx_desc *txdp;
 690         struct ixgbe_tx_entry_v *txep;
 691         uint16_t n, nb_commit, tx_id;
 692         uint64_t flags = DCMD_DTYP_FLAGS;
 693         uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
 694         int i;
 695
 696         /* cross rx_thresh boundary is not allowed */
 697         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 698
 699         if (txq->nb_tx_free < txq->tx_free_thresh)
 700                 ixgbe_tx_free_bufs(txq);
 701
 702         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 703         if (unlikely(nb_pkts == 0))
 704                 return 0;
 705
 706         tx_id = txq->tx_tail;
 707         txdp = &txq->tx_ring[tx_id];
 708         txep = &txq->sw_ring_v[tx_id];
 709
 710         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 711
 712         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 713         if (nb_commit >= n) {
 714
 715                 tx_backlog_entry(txep, tx_pkts, n);
 716
 717                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
 718                         vtx1(txdp, *tx_pkts, flags);
 719
 720                 vtx1(txdp, *tx_pkts++, rs);
 721
 722                 nb_commit = (uint16_t)(nb_commit - n);
 723
 724                 tx_id = 0;
 725                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 726
 727                 /* avoid reach the end of ring */
 728                 txdp = &(txq->tx_ring[tx_id]);
 729                 txep = &txq->sw_ring_v[tx_id];
 730         }
 731
 732         tx_backlog_entry(txep, tx_pkts, nb_commit);
 733
 734         vtx(txdp, tx_pkts, nb_commit, flags);
 735
 736         tx_id = (uint16_t)(tx_id + nb_commit);
 737         if (tx_id > txq->tx_next_rs) {
 738                 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
 739                         rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
 740                 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
 741                         txq->tx_rs_thresh);
 742         }
 743
 744         txq->tx_tail = tx_id;
 745
 746         IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
 747
 748         return nb_pkts;
 749 }
 750
 751 static void __attribute__((cold))
 752 ixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)
 753 {
 754         _ixgbe_tx_queue_release_mbufs_vec(txq);
 755 }
 756
 757 void __attribute__((cold))
 758 ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)
 759 {
 760         _ixgbe_rx_queue_release_mbufs_vec(rxq);
 761 }
 762
 763 static void __attribute__((cold))
 764 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
 765 {
 766         _ixgbe_tx_free_swring_vec(txq);
 767 }
 768
 769 static void __attribute__((cold))
 770 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
 771 {
 772         _ixgbe_reset_tx_queue_vec(txq);
 773 }
 774
 775 static const struct ixgbe_txq_ops vec_txq_ops = {
 776         .release_mbufs = ixgbe_tx_queue_release_mbufs_vec,
 777         .free_swring = ixgbe_tx_free_swring,
 778         .reset = ixgbe_reset_tx_queue,
 779 };
 780
 781 int __attribute__((cold))
 782 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)
 783 {
 784         return ixgbe_rxq_vec_setup_default(rxq);
 785 }
 786
 787 int __attribute__((cold))
 788 ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)
 789 {
 790         return ixgbe_txq_vec_setup_default(txq, &vec_txq_ops);
 791 }
 792
 793 int __attribute__((cold))
 794 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
 795 {
 796         return ixgbe_rx_vec_dev_conf_condition_check_default(dev);
 797 }