4 * Copyright 2017 6WIND S.A.
5 * Copyright 2017 Mellanox.
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38 #include <smmintrin.h>
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
46 #include <infiniband/mlx5_hw.h>
47 #include <infiniband/arch.h>
49 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_mempool.h>
54 #include <rte_prefetch.h>
57 #include "mlx5_utils.h"
58 #include "mlx5_rxtx.h"
59 #include "mlx5_autoconf.h"
60 #include "mlx5_defs.h"
63 #ifndef __INTEL_COMPILER
64 #pragma GCC diagnostic ignored "-Wcast-qual"
68 * Fill in buffer descriptors in a multi-packet send descriptor.
71 * Pointer to TX queue structure.
73 * Pointer to buffer descriptor to be writen.
75 * Pointer to array of packets to be sent.
77 * Number of packets to be filled.
80 txq_wr_dseg_v(struct txq *txq, __m128i *dseg,
81 struct rte_mbuf **pkts, unsigned int n)
85 const __m128i shuf_mask_dseg =
86 _mm_set_epi8(8, 9, 10, 11, /* addr, bswap64 */
88 7, 6, 5, 4, /* lkey */
89 0, 1, 2, 3 /* length, bswap32 */);
90 #ifdef MLX5_PMD_SOFT_COUNTERS
94 for (pos = 0; pos < n; ++pos, ++dseg) {
96 struct rte_mbuf *pkt = pkts[pos];
98 addr = rte_pktmbuf_mtod(pkt, uintptr_t);
99 desc = _mm_set_epi32(addr >> 32,
101 mlx5_tx_mb2mr(txq, pkt),
103 desc = _mm_shuffle_epi8(desc, shuf_mask_dseg);
104 _mm_store_si128(dseg, desc);
105 #ifdef MLX5_PMD_SOFT_COUNTERS
106 tx_byte += DATA_LEN(pkt);
109 #ifdef MLX5_PMD_SOFT_COUNTERS
110 txq->stats.obytes += tx_byte;
115 * Count the number of continuous single segment packets.
118 * Pointer to array of packets.
123 * Number of continuous single segment packets.
125 static inline unsigned int
126 txq_check_multiseg(struct rte_mbuf **pkts, uint16_t pkts_n)
132 /* Count the number of continuous single segment packets. */
133 for (pos = 0; pos < pkts_n; ++pos)
134 if (NB_SEGS(pkts[pos]) > 1)
140 * Count the number of packets having same ol_flags and calculate cs_flags.
143 * Pointer to TX queue structure.
145 * Pointer to array of packets.
149 * Pointer of flags to be returned.
152 * Number of packets having same ol_flags.
154 static inline unsigned int
155 txq_calc_offload(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
159 const uint64_t ol_mask =
160 PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM |
161 PKT_TX_UDP_CKSUM | PKT_TX_TUNNEL_GRE |
162 PKT_TX_TUNNEL_VXLAN | PKT_TX_OUTER_IP_CKSUM;
166 /* Count the number of packets having same ol_flags. */
167 for (pos = 1; pos < pkts_n; ++pos)
168 if ((pkts[pos]->ol_flags ^ pkts[0]->ol_flags) & ol_mask)
170 /* Should open another MPW session for the rest. */
171 if (pkts[0]->ol_flags &
172 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
173 const uint64_t is_tunneled =
176 PKT_TX_TUNNEL_VXLAN);
178 if (is_tunneled && txq->tunnel_en) {
179 *cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
180 MLX5_ETH_WQE_L4_INNER_CSUM;
181 if (pkts[0]->ol_flags & PKT_TX_OUTER_IP_CKSUM)
182 *cs_flags |= MLX5_ETH_WQE_L3_CSUM;
184 *cs_flags = MLX5_ETH_WQE_L3_CSUM |
185 MLX5_ETH_WQE_L4_CSUM;
192 * Send multi-segmented packets until it encounters a single segment packet in
196 * Pointer to TX queue structure.
198 * Pointer to array of packets to be sent.
200 * Number of packets to be sent.
203 * Number of packets successfully transmitted (<= pkts_n).
206 txq_scatter_v(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n)
208 uint16_t elts_head = txq->elts_head;
209 const uint16_t elts_n = 1 << txq->elts_n;
210 const uint16_t elts_m = elts_n - 1;
211 const uint16_t wq_n = 1 << txq->wqe_n;
212 const uint16_t wq_mask = wq_n - 1;
213 const unsigned int nb_dword_per_wqebb =
214 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
215 const unsigned int nb_dword_in_hdr =
216 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
218 volatile struct mlx5_wqe *wqe = NULL;
220 assert(elts_n > pkts_n);
221 mlx5_tx_complete(txq);
222 if (unlikely(!pkts_n))
224 for (n = 0; n < pkts_n; ++n) {
225 struct rte_mbuf *buf = pkts[n];
226 unsigned int segs_n = buf->nb_segs;
227 unsigned int ds = nb_dword_in_hdr;
228 unsigned int len = PKT_LEN(buf);
229 uint16_t wqe_ci = txq->wqe_ci;
230 const __m128i shuf_mask_ctrl =
231 _mm_set_epi8(15, 14, 13, 12,
232 8, 9, 10, 11, /* bswap32 */
233 4, 5, 6, 7, /* bswap32 */
234 0, 1, 2, 3 /* bswap32 */);
235 uint8_t cs_flags = 0;
238 __m128i *t_wqe, *dseg;
242 max_elts = elts_n - (elts_head - txq->elts_tail);
243 max_wqe = wq_n - (txq->wqe_ci - txq->wqe_pi);
245 * A MPW session consumes 2 WQEs at most to
246 * include MLX5_MPW_DSEG_MAX pointers.
249 max_elts < segs_n || max_wqe < 2)
251 wqe = &((volatile struct mlx5_wqe64 *)
252 txq->wqes)[wqe_ci & wq_mask].hdr;
254 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
255 const uint64_t is_tunneled = buf->ol_flags &
257 PKT_TX_TUNNEL_VXLAN);
259 if (is_tunneled && txq->tunnel_en) {
260 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
261 MLX5_ETH_WQE_L4_INNER_CSUM;
262 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
263 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
265 cs_flags = MLX5_ETH_WQE_L3_CSUM |
266 MLX5_ETH_WQE_L4_CSUM;
269 /* Title WQEBB pointer. */
270 t_wqe = (__m128i *)wqe;
271 dseg = (__m128i *)(wqe + 1);
273 if (!(ds++ % nb_dword_per_wqebb)) {
275 &((volatile struct mlx5_wqe64 *)
276 txq->wqes)[++wqe_ci & wq_mask];
278 txq_wr_dseg_v(txq, dseg++, &buf, 1);
279 (*txq->elts)[elts_head++ & elts_m] = buf;
283 /* Fill CTRL in the header. */
284 ctrl = _mm_set_epi32(0, 0, txq->qp_num_8s | ds,
285 MLX5_OPC_MOD_MPW << 24 |
286 txq->wqe_ci << 8 | MLX5_OPCODE_TSO);
287 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
288 _mm_store_si128(t_wqe, ctrl);
289 /* Fill ESEG in the header. */
290 _mm_store_si128(t_wqe + 1,
291 _mm_set_epi16(0, 0, 0, 0,
292 htons(len), cs_flags,
294 txq->wqe_ci = wqe_ci;
298 txq->elts_comp += (uint16_t)(elts_head - txq->elts_head);
299 txq->elts_head = elts_head;
300 if (txq->elts_comp >= MLX5_TX_COMP_THRESH) {
301 wqe->ctrl[2] = htonl(8);
302 wqe->ctrl[3] = txq->elts_head;
306 #ifdef MLX5_PMD_SOFT_COUNTERS
307 txq->stats.opackets += n;
309 mlx5_tx_dbrec(txq, wqe);
314 * Send burst of packets with Enhanced MPW. If it encounters a multi-seg packet,
315 * it returns to make it processed by txq_scatter_v(). All the packets in
316 * the pkts list should be single segment packets having same offload flags.
317 * This must be checked by txq_check_multiseg() and txq_calc_offload().
320 * Pointer to TX queue structure.
322 * Pointer to array of packets to be sent.
324 * Number of packets to be sent (<= MLX5_VPMD_TX_MAX_BURST).
326 * Checksum offload flags to be written in the descriptor.
329 * Number of packets successfully transmitted (<= pkts_n).
331 static inline uint16_t
332 txq_burst_v(struct txq *txq, struct rte_mbuf **pkts, uint16_t pkts_n,
335 struct rte_mbuf **elts;
336 uint16_t elts_head = txq->elts_head;
337 const uint16_t elts_n = 1 << txq->elts_n;
338 const uint16_t elts_m = elts_n - 1;
339 const unsigned int nb_dword_per_wqebb =
340 MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE;
341 const unsigned int nb_dword_in_hdr =
342 sizeof(struct mlx5_wqe) / MLX5_WQE_DWORD_SIZE;
347 uint32_t comp_req = 0;
348 const uint16_t wq_n = 1 << txq->wqe_n;
349 const uint16_t wq_mask = wq_n - 1;
350 uint16_t wq_idx = txq->wqe_ci & wq_mask;
351 volatile struct mlx5_wqe64 *wq =
352 &((volatile struct mlx5_wqe64 *)txq->wqes)[wq_idx];
353 volatile struct mlx5_wqe *wqe = (volatile struct mlx5_wqe *)wq;
354 const __m128i shuf_mask_ctrl =
355 _mm_set_epi8(15, 14, 13, 12,
356 8, 9, 10, 11, /* bswap32 */
357 4, 5, 6, 7, /* bswap32 */
358 0, 1, 2, 3 /* bswap32 */);
359 __m128i *t_wqe, *dseg;
362 /* Make sure all packets can fit into a single WQE. */
363 assert(elts_n > pkts_n);
364 mlx5_tx_complete(txq);
365 max_elts = (elts_n - (elts_head - txq->elts_tail));
366 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
367 pkts_n = RTE_MIN((unsigned int)RTE_MIN(pkts_n, max_wqe), max_elts);
368 if (unlikely(!pkts_n))
370 elts = &(*txq->elts)[elts_head & elts_m];
371 /* Loop for available tailroom first. */
372 n = RTE_MIN(elts_n - (elts_head & elts_m), pkts_n);
373 for (pos = 0; pos < (n & -2); pos += 2)
374 _mm_storeu_si128((__m128i *)&elts[pos],
375 _mm_loadu_si128((__m128i *)&pkts[pos]));
377 elts[pos] = pkts[pos];
378 /* Check if it crosses the end of the queue. */
379 if (unlikely(n < pkts_n)) {
380 elts = &(*txq->elts)[0];
381 for (pos = 0; pos < pkts_n - n; ++pos)
382 elts[pos] = pkts[n + pos];
384 txq->elts_head += pkts_n;
385 /* Save title WQEBB pointer. */
386 t_wqe = (__m128i *)wqe;
387 dseg = (__m128i *)(wqe + 1);
388 /* Calculate the number of entries to the end. */
390 (wq_n - wq_idx) * nb_dword_per_wqebb - nb_dword_in_hdr,
393 txq_wr_dseg_v(txq, dseg, pkts, n);
394 /* Check if it crosses the end of the queue. */
396 dseg = (__m128i *)txq->wqes;
397 txq_wr_dseg_v(txq, dseg, &pkts[n], pkts_n - n);
399 if (txq->elts_comp + pkts_n < MLX5_TX_COMP_THRESH) {
400 txq->elts_comp += pkts_n;
402 /* Request a completion. */
407 /* Fill CTRL in the header. */
408 ctrl = _mm_set_epi32(txq->elts_head, comp_req,
409 txq->qp_num_8s | (pkts_n + 2),
410 MLX5_OPC_MOD_ENHANCED_MPSW << 24 |
411 txq->wqe_ci << 8 | MLX5_OPCODE_ENHANCED_MPSW);
412 ctrl = _mm_shuffle_epi8(ctrl, shuf_mask_ctrl);
413 _mm_store_si128(t_wqe, ctrl);
414 /* Fill ESEG in the header. */
415 _mm_store_si128(t_wqe + 1,
416 _mm_set_epi8(0, 0, 0, 0,
420 #ifdef MLX5_PMD_SOFT_COUNTERS
421 txq->stats.opackets += pkts_n;
423 txq->wqe_ci += (nb_dword_in_hdr + pkts_n + (nb_dword_per_wqebb - 1)) /
425 /* Ring QP doorbell. */
426 mlx5_tx_dbrec(txq, wqe);
431 * DPDK callback for vectorized TX.
434 * Generic pointer to TX queue structure.
436 * Packets to transmit.
438 * Number of packets in array.
441 * Number of packets successfully transmitted (<= pkts_n).
444 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
447 struct txq *txq = (struct txq *)dpdk_txq;
450 while (pkts_n > nb_tx) {
454 n = RTE_MIN((uint16_t)(pkts_n - nb_tx), MLX5_VPMD_TX_MAX_BURST);
455 ret = txq_burst_v(txq, &pkts[nb_tx], n, 0);
464 * DPDK callback for vectorized TX with multi-seg packets and offload.
467 * Generic pointer to TX queue structure.
469 * Packets to transmit.
471 * Number of packets in array.
474 * Number of packets successfully transmitted (<= pkts_n).
477 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
479 struct txq *txq = (struct txq *)dpdk_txq;
482 while (pkts_n > nb_tx) {
483 uint8_t cs_flags = 0;
487 /* Transmit multi-seg packets in the head of pkts list. */
488 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS) &&
489 NB_SEGS(pkts[nb_tx]) > 1)
490 nb_tx += txq_scatter_v(txq,
493 n = RTE_MIN((uint16_t)(pkts_n - nb_tx), MLX5_VPMD_TX_MAX_BURST);
494 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS))
495 n = txq_check_multiseg(&pkts[nb_tx], n);
496 if (!(txq->flags & ETH_TXQ_FLAGS_NOOFFLOADS))
497 n = txq_calc_offload(txq, &pkts[nb_tx], n, &cs_flags);
498 ret = txq_burst_v(txq, &pkts[nb_tx], n, cs_flags);
507 * Store free buffers to RX SW ring.
510 * Pointer to RX queue structure.
512 * Pointer to array of packets to be stored.
514 * Number of packets to be stored.
517 rxq_copy_mbuf_v(struct rxq *rxq, struct rte_mbuf **pkts, uint16_t n)
519 const uint16_t q_mask = (1 << rxq->elts_n) - 1;
520 struct rte_mbuf **elts = &(*rxq->elts)[rxq->rq_pi & q_mask];
524 for (pos = 0; pos < p; pos += 2) {
527 mbp = _mm_loadu_si128((__m128i *)&elts[pos]);
528 _mm_storeu_si128((__m128i *)&pkts[pos], mbp);
531 pkts[pos] = elts[pos];
535 * Replenish buffers for RX in bulk.
538 * Pointer to RX queue structure.
540 * Number of buffers to be replenished.
543 rxq_replenish_bulk_mbuf(struct rxq *rxq, uint16_t n)
545 const uint16_t q_n = 1 << rxq->elts_n;
546 const uint16_t q_mask = q_n - 1;
547 const uint16_t elts_idx = rxq->rq_ci & q_mask;
548 struct rte_mbuf **elts = &(*rxq->elts)[elts_idx];
549 volatile struct mlx5_wqe_data_seg *wq = &(*rxq->wqes)[elts_idx];
552 assert(n >= MLX5_VPMD_RXQ_RPLNSH_THRESH);
553 assert(n <= (uint16_t)(q_n - (rxq->rq_ci - rxq->rq_pi)));
554 assert(MLX5_VPMD_RXQ_RPLNSH_THRESH > MLX5_VPMD_DESCS_PER_LOOP);
555 /* Not to cross queue end. */
556 n = RTE_MIN(n - MLX5_VPMD_DESCS_PER_LOOP, q_n - elts_idx);
557 if (rte_mempool_get_bulk(rxq->mp, (void *)elts, n) < 0) {
558 rxq->stats.rx_nombuf += n;
561 for (i = 0; i < n; ++i)
562 wq[i].addr = htonll((uintptr_t)elts[i]->buf_addr +
563 RTE_PKTMBUF_HEADROOM);
566 *rxq->rq_db = htonl(rxq->rq_ci);
570 * Decompress a compressed completion and fill in mbufs in RX SW ring with data
571 * extracted from the title completion descriptor.
574 * Pointer to RX queue structure.
576 * Pointer to completion array having a compressed completion at first.
578 * Pointer to SW ring to be filled. The first mbuf has to be pre-built from
579 * the title completion descriptor to be copied to the rest of mbufs.
582 rxq_cq_decompress_v(struct rxq *rxq,
583 volatile struct mlx5_cqe *cq,
584 struct rte_mbuf **elts)
586 volatile struct mlx5_mini_cqe8 *mcq = (void *)(cq + 1);
587 struct rte_mbuf *t_pkt = elts[0]; /* Title packet is pre-built. */
590 unsigned int inv = 0;
591 /* Mask to shuffle from extracted mini CQE to mbuf. */
592 const __m128i shuf_mask1 =
593 _mm_set_epi8(0, 1, 2, 3, /* rss, bswap32 */
594 -1, -1, /* skip vlan_tci */
595 6, 7, /* data_len, bswap16 */
596 -1, -1, 6, 7, /* pkt_len, bswap16 */
597 -1, -1, -1, -1 /* skip packet_type */);
598 const __m128i shuf_mask2 =
599 _mm_set_epi8(8, 9, 10, 11, /* rss, bswap32 */
600 -1, -1, /* skip vlan_tci */
601 14, 15, /* data_len, bswap16 */
602 -1, -1, 14, 15, /* pkt_len, bswap16 */
603 -1, -1, -1, -1 /* skip packet_type */);
604 /* Restore the compressed count. Must be 16 bits. */
605 const uint16_t mcqe_n = t_pkt->data_len +
606 (rxq->crc_present * ETHER_CRC_LEN);
607 const __m128i rearm =
608 _mm_loadu_si128((__m128i *)&t_pkt->rearm_data);
610 _mm_loadu_si128((__m128i *)&t_pkt->rx_descriptor_fields1);
611 const __m128i crc_adj =
612 _mm_set_epi16(0, 0, 0,
613 rxq->crc_present * ETHER_CRC_LEN,
615 rxq->crc_present * ETHER_CRC_LEN,
617 const uint32_t flow_tag = t_pkt->hash.fdir.hi;
618 #ifdef MLX5_PMD_SOFT_COUNTERS
619 const __m128i zero = _mm_setzero_si128();
620 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
621 uint32_t rcvd_byte = 0;
622 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
623 const __m128i len_shuf_mask =
624 _mm_set_epi8(-1, -1, -1, -1,
630 /* Compile time sanity check for this function. */
631 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
632 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
633 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
634 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
635 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
636 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
638 * A. load mCQEs into a 128bit register.
639 * B. store rearm data to mbuf.
640 * C. combine data from mCQEs with rx_descriptor_fields1.
641 * D. store rx_descriptor_fields1.
642 * E. store flow tag (rte_flow mark).
644 for (pos = 0; pos < mcqe_n; ) {
645 __m128i mcqe1, mcqe2;
646 __m128i rxdf1, rxdf2;
647 #ifdef MLX5_PMD_SOFT_COUNTERS
648 __m128i byte_cnt, invalid_mask;
651 if (!(pos & 0x7) && pos + 8 < mcqe_n)
652 rte_prefetch0((void *)(cq + pos + 8));
653 /* A.1 load mCQEs into a 128bit register. */
654 mcqe1 = _mm_loadu_si128((__m128i *)&mcq[pos % 8]);
655 mcqe2 = _mm_loadu_si128((__m128i *)&mcq[pos % 8 + 2]);
656 /* B.1 store rearm data to mbuf. */
657 _mm_storeu_si128((__m128i *)&elts[pos]->rearm_data, rearm);
658 _mm_storeu_si128((__m128i *)&elts[pos + 1]->rearm_data, rearm);
659 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
660 rxdf1 = _mm_shuffle_epi8(mcqe1, shuf_mask1);
661 rxdf2 = _mm_shuffle_epi8(mcqe1, shuf_mask2);
662 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
663 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
664 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
665 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
666 /* D.1 store rx_descriptor_fields1. */
667 _mm_storeu_si128((__m128i *)
668 &elts[pos]->rx_descriptor_fields1,
670 _mm_storeu_si128((__m128i *)
671 &elts[pos + 1]->rx_descriptor_fields1,
673 /* B.1 store rearm data to mbuf. */
674 _mm_storeu_si128((__m128i *)&elts[pos + 2]->rearm_data, rearm);
675 _mm_storeu_si128((__m128i *)&elts[pos + 3]->rearm_data, rearm);
676 /* C.1 combine data from mCQEs with rx_descriptor_fields1. */
677 rxdf1 = _mm_shuffle_epi8(mcqe2, shuf_mask1);
678 rxdf2 = _mm_shuffle_epi8(mcqe2, shuf_mask2);
679 rxdf1 = _mm_sub_epi16(rxdf1, crc_adj);
680 rxdf2 = _mm_sub_epi16(rxdf2, crc_adj);
681 rxdf1 = _mm_blend_epi16(rxdf1, rxdf, 0x23);
682 rxdf2 = _mm_blend_epi16(rxdf2, rxdf, 0x23);
683 /* D.1 store rx_descriptor_fields1. */
684 _mm_storeu_si128((__m128i *)
685 &elts[pos + 2]->rx_descriptor_fields1,
687 _mm_storeu_si128((__m128i *)
688 &elts[pos + 3]->rx_descriptor_fields1,
690 #ifdef MLX5_PMD_SOFT_COUNTERS
691 invalid_mask = _mm_set_epi64x(0,
693 sizeof(uint16_t) * 8);
694 invalid_mask = _mm_sll_epi64(ones, invalid_mask);
695 mcqe1 = _mm_srli_si128(mcqe1, 4);
696 byte_cnt = _mm_blend_epi16(mcqe1, mcqe2, 0xcc);
697 byte_cnt = _mm_shuffle_epi8(byte_cnt, len_shuf_mask);
698 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
699 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
700 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
703 /* E.1 store flow tag (rte_flow mark). */
704 elts[pos]->hash.fdir.hi = flow_tag;
705 elts[pos + 1]->hash.fdir.hi = flow_tag;
706 elts[pos + 2]->hash.fdir.hi = flow_tag;
707 elts[pos + 3]->hash.fdir.hi = flow_tag;
709 pos += MLX5_VPMD_DESCS_PER_LOOP;
710 /* Move to next CQE and invalidate consumed CQEs. */
711 if (!(pos & 0x7) && pos < mcqe_n) {
712 mcq = (void *)(cq + pos);
713 for (i = 0; i < 8; ++i)
714 cq[inv++].op_own = MLX5_CQE_INVALIDATE;
717 /* Invalidate the rest of CQEs. */
718 for (; inv < mcqe_n; ++inv)
719 cq[inv].op_own = MLX5_CQE_INVALIDATE;
720 #ifdef MLX5_PMD_SOFT_COUNTERS
721 rxq->stats.ipackets += mcqe_n;
722 rxq->stats.ibytes += rcvd_byte;
724 rxq->cq_ci += mcqe_n;
728 * Calculate packet type and offload flag for mbuf and store it.
731 * Pointer to RX queue structure.
733 * Array of four 16bytes completions extracted from the original completion
736 * Opcode vector having responder error status. Each field is 4B.
738 * Pointer to array of packets to be filled.
741 rxq_cq_to_ptype_oflags_v(struct rxq *rxq, __m128i cqes[4], __m128i op_err,
742 struct rte_mbuf **pkts)
744 __m128i pinfo0, pinfo1;
745 __m128i pinfo, ptype;
746 __m128i ol_flags = _mm_set1_epi32(rxq->rss_hash * PKT_RX_RSS_HASH);
748 const __m128i zero = _mm_setzero_si128();
749 const __m128i ptype_mask =
750 _mm_set_epi32(0xfd06, 0xfd06, 0xfd06, 0xfd06);
751 const __m128i ptype_ol_mask =
752 _mm_set_epi32(0x106, 0x106, 0x106, 0x106);
753 const __m128i pinfo_mask =
754 _mm_set_epi32(0x3, 0x3, 0x3, 0x3);
755 const __m128i cv_flag_sel =
756 _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
757 (uint8_t)((PKT_RX_IP_CKSUM_GOOD |
758 PKT_RX_L4_CKSUM_GOOD) >> 1),
760 (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
762 (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
763 (uint8_t)(PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED),
765 const __m128i cv_mask =
766 _mm_set_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
767 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
768 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
769 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
770 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
771 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED,
772 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
773 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED);
774 const __m128i mbuf_init =
775 _mm_loadl_epi64((__m128i *)&rxq->mbuf_initializer);
776 __m128i rearm0, rearm1, rearm2, rearm3;
778 /* Extract pkt_info field. */
779 pinfo0 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
780 pinfo1 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
781 pinfo = _mm_unpacklo_epi64(pinfo0, pinfo1);
782 /* Extract hdr_type_etc field. */
783 pinfo0 = _mm_unpackhi_epi32(cqes[0], cqes[1]);
784 pinfo1 = _mm_unpackhi_epi32(cqes[2], cqes[3]);
785 ptype = _mm_unpacklo_epi64(pinfo0, pinfo1);
787 const __m128i pinfo_ft_mask =
788 _mm_set_epi32(0xffffff00, 0xffffff00,
789 0xffffff00, 0xffffff00);
790 const __m128i fdir_flags = _mm_set1_epi32(PKT_RX_FDIR);
791 const __m128i fdir_id_flags = _mm_set1_epi32(PKT_RX_FDIR_ID);
792 __m128i flow_tag, invalid_mask;
794 flow_tag = _mm_and_si128(pinfo, pinfo_ft_mask);
795 /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
796 invalid_mask = _mm_cmpeq_epi32(flow_tag, zero);
797 ol_flags = _mm_or_si128(ol_flags,
798 _mm_andnot_si128(invalid_mask,
800 /* Mask out invalid entries. */
801 flow_tag = _mm_andnot_si128(invalid_mask, flow_tag);
802 /* Check if flow tag MLX5_FLOW_MARK_DEFAULT. */
803 ol_flags = _mm_or_si128(ol_flags,
805 _mm_cmpeq_epi32(flow_tag,
810 * Merge the two fields to generate the following:
814 * bit[11:10] = l3_hdr_type
815 * bit[14:12] = l4_hdr_type
818 * bit[17] = outer_l3_type
820 ptype = _mm_and_si128(ptype, ptype_mask);
821 pinfo = _mm_and_si128(pinfo, pinfo_mask);
822 pinfo = _mm_slli_epi32(pinfo, 16);
823 /* Make pinfo has merged fields for ol_flags calculation. */
824 pinfo = _mm_or_si128(ptype, pinfo);
825 ptype = _mm_srli_epi32(pinfo, 10);
826 ptype = _mm_packs_epi32(ptype, zero);
827 /* Errored packets will have RTE_PTYPE_ALL_MASK. */
828 op_err = _mm_srli_epi16(op_err, 8);
829 ptype = _mm_or_si128(ptype, op_err);
830 pkts[0]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 0)];
831 pkts[1]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 2)];
832 pkts[2]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 4)];
833 pkts[3]->packet_type = mlx5_ptype_table[_mm_extract_epi8(ptype, 6)];
834 /* Fill flags for checksum and VLAN. */
835 pinfo = _mm_and_si128(pinfo, ptype_ol_mask);
836 pinfo = _mm_shuffle_epi8(cv_flag_sel, pinfo);
837 /* Locate checksum flags at byte[2:1] and merge with VLAN flags. */
838 cv_flags = _mm_slli_epi32(pinfo, 9);
839 cv_flags = _mm_or_si128(pinfo, cv_flags);
840 /* Move back flags to start from byte[0]. */
841 cv_flags = _mm_srli_epi32(cv_flags, 8);
842 /* Mask out garbage bits. */
843 cv_flags = _mm_and_si128(cv_flags, cv_mask);
844 /* Merge to ol_flags. */
845 ol_flags = _mm_or_si128(ol_flags, cv_flags);
846 /* Merge mbuf_init and ol_flags. */
847 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
848 offsetof(struct rte_mbuf, rearm_data) + 8);
849 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 8), 0x30);
850 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(ol_flags, 4), 0x30);
851 rearm2 = _mm_blend_epi16(mbuf_init, ol_flags, 0x30);
852 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(ol_flags, 4), 0x30);
853 /* Write 8B rearm_data and 8B ol_flags. */
854 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
855 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
856 _mm_store_si128((__m128i *)&pkts[0]->rearm_data, rearm0);
857 _mm_store_si128((__m128i *)&pkts[1]->rearm_data, rearm1);
858 _mm_store_si128((__m128i *)&pkts[2]->rearm_data, rearm2);
859 _mm_store_si128((__m128i *)&pkts[3]->rearm_data, rearm3);
863 * Skip error packets.
866 * Pointer to RX queue structure.
868 * Array to store received packets.
870 * Maximum number of packets in array.
873 * Number of packets successfully received (<= pkts_n).
876 rxq_handle_pending_error(struct rxq *rxq, struct rte_mbuf **pkts,
881 #ifdef MLX5_PMD_SOFT_COUNTERS
882 uint32_t err_bytes = 0;
885 for (i = 0; i < pkts_n; ++i) {
886 struct rte_mbuf *pkt = pkts[i];
888 if (pkt->packet_type == RTE_PTYPE_ALL_MASK) {
889 #ifdef MLX5_PMD_SOFT_COUNTERS
890 err_bytes += PKT_LEN(pkt);
892 rte_pktmbuf_free_seg(pkt);
897 rxq->stats.idropped += (pkts_n - n);
898 #ifdef MLX5_PMD_SOFT_COUNTERS
899 /* Correct counters of errored completions. */
900 rxq->stats.ipackets -= (pkts_n - n);
901 rxq->stats.ibytes -= err_bytes;
903 rxq->pending_err = 0;
908 * Receive burst of packets. An errored completion also consumes a mbuf, but the
909 * packet_type is set to be RTE_PTYPE_ALL_MASK. Marked mbufs should be freed
910 * before returning to application.
913 * Pointer to RX queue structure.
915 * Array to store received packets.
917 * Maximum number of packets in array.
920 * Number of packets received including errors (<= pkts_n).
922 static inline uint16_t
923 rxq_burst_v(struct rxq *rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
925 const uint16_t q_n = 1 << rxq->cqe_n;
926 const uint16_t q_mask = q_n - 1;
927 volatile struct mlx5_cqe *cq;
928 struct rte_mbuf **elts;
932 uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
933 uint16_t nocmp_n = 0;
934 uint16_t rcvd_pkt = 0;
935 unsigned int cq_idx = rxq->cq_ci & q_mask;
936 unsigned int elts_idx;
937 unsigned int ownership = !!(rxq->cq_ci & (q_mask + 1));
938 const __m128i owner_check =
939 _mm_set_epi64x(0x0100000001000000LL, 0x0100000001000000LL);
940 const __m128i opcode_check =
941 _mm_set_epi64x(0xf0000000f0000000LL, 0xf0000000f0000000LL);
942 const __m128i format_check =
943 _mm_set_epi64x(0x0c0000000c000000LL, 0x0c0000000c000000LL);
944 const __m128i resp_err_check =
945 _mm_set_epi64x(0xe0000000e0000000LL, 0xe0000000e0000000LL);
946 #ifdef MLX5_PMD_SOFT_COUNTERS
947 uint32_t rcvd_byte = 0;
948 /* Mask to shuffle byte_cnt to add up stats. Do bswap16 for all. */
949 const __m128i len_shuf_mask =
950 _mm_set_epi8(-1, -1, -1, -1,
955 /* Mask to shuffle from extracted CQE to mbuf. */
956 const __m128i shuf_mask =
957 _mm_set_epi8(-1, 3, 2, 1, /* fdir.hi */
958 12, 13, 14, 15, /* rss, bswap32 */
959 10, 11, /* vlan_tci, bswap16 */
960 4, 5, /* data_len, bswap16 */
961 -1, -1, /* zero out 2nd half of pkt_len */
962 4, 5 /* pkt_len, bswap16 */);
963 /* Mask to blend from the last Qword to the first DQword. */
964 const __m128i blend_mask =
965 _mm_set_epi8(-1, -1, -1, -1,
969 const __m128i zero = _mm_setzero_si128();
970 const __m128i ones = _mm_cmpeq_epi32(zero, zero);
971 const __m128i crc_adj =
972 _mm_set_epi16(0, 0, 0, 0, 0,
973 rxq->crc_present * ETHER_CRC_LEN,
975 rxq->crc_present * ETHER_CRC_LEN);
976 const __m128i flow_mark_adj = _mm_set_epi32(rxq->mark * (-1), 0, 0, 0);
978 /* Compile time sanity check for this function. */
979 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
980 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
981 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
982 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
983 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, pkt_info) != 0);
984 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rx_hash_res) !=
985 offsetof(struct mlx5_cqe, pkt_info) + 12);
986 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rsvd1) +
987 sizeof(((struct mlx5_cqe *)0)->rsvd1) !=
988 offsetof(struct mlx5_cqe, hdr_type_etc));
989 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, vlan_info) !=
990 offsetof(struct mlx5_cqe, hdr_type_etc) + 2);
991 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, rsvd2) +
992 sizeof(((struct mlx5_cqe *)0)->rsvd2) !=
993 offsetof(struct mlx5_cqe, byte_cnt));
994 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, sop_drop_qpn) !=
995 RTE_ALIGN(offsetof(struct mlx5_cqe, sop_drop_qpn), 8));
996 RTE_BUILD_BUG_ON(offsetof(struct mlx5_cqe, op_own) !=
997 offsetof(struct mlx5_cqe, sop_drop_qpn) + 7);
998 assert(rxq->sges_n == 0);
999 assert(rxq->cqe_n == rxq->elts_n);
1000 cq = &(*rxq->cqes)[cq_idx];
1002 rte_prefetch0(cq + 1);
1003 rte_prefetch0(cq + 2);
1004 rte_prefetch0(cq + 3);
1005 pkts_n = RTE_MIN(pkts_n, MLX5_VPMD_RX_MAX_BURST);
1008 * rq_ci >= cq_ci >= rq_pi
1009 * Definition of indexes:
1010 * rq_ci - cq_ci := # of buffers owned by HW (posted).
1011 * cq_ci - rq_pi := # of buffers not returned to app (decompressed).
1012 * N - (rq_ci - rq_pi) := # of buffers consumed (to be replenished).
1014 repl_n = q_n - (rxq->rq_ci - rxq->rq_pi);
1015 if (repl_n >= MLX5_VPMD_RXQ_RPLNSH_THRESH)
1016 rxq_replenish_bulk_mbuf(rxq, repl_n);
1017 /* See if there're unreturned mbufs from compressed CQE. */
1018 rcvd_pkt = rxq->cq_ci - rxq->rq_pi;
1020 rcvd_pkt = RTE_MIN(rcvd_pkt, pkts_n);
1021 rxq_copy_mbuf_v(rxq, pkts, rcvd_pkt);
1022 rxq->rq_pi += rcvd_pkt;
1025 elts_idx = rxq->rq_pi & q_mask;
1026 elts = &(*rxq->elts)[elts_idx];
1027 /* Not to overflow pkts array. */
1028 pkts_n = RTE_ALIGN_FLOOR(pkts_n - rcvd_pkt, MLX5_VPMD_DESCS_PER_LOOP);
1029 /* Not to cross queue end. */
1030 pkts_n = RTE_MIN(pkts_n, q_n - elts_idx);
1033 /* At this point, there shouldn't be any remained packets. */
1034 assert(rxq->rq_pi == rxq->cq_ci);
1036 * A. load first Qword (8bytes) in one loop.
1037 * B. copy 4 mbuf pointers from elts ring to returing pkts.
1038 * C. load remained CQE data and extract necessary fields.
1039 * Final 16bytes cqes[] extracted from original 64bytes CQE has the
1040 * following structure:
1043 * uint8_t flow_tag[3];
1044 * uint16_t byte_cnt;
1047 * uint16_t hdr_type_etc;
1048 * uint16_t vlan_info;
1049 * uint32_t rx_has_res;
1052 * E. get valid CQEs.
1053 * F. find compressed CQE.
1057 pos += MLX5_VPMD_DESCS_PER_LOOP) {
1058 __m128i cqes[MLX5_VPMD_DESCS_PER_LOOP];
1059 __m128i cqe_tmp1, cqe_tmp2;
1060 __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;
1061 __m128i op_own, op_own_tmp1, op_own_tmp2;
1062 __m128i opcode, owner_mask, invalid_mask;
1065 #ifdef MLX5_PMD_SOFT_COUNTERS
1069 __m128i p = _mm_set_epi16(0, 0, 0, 0, 3, 2, 1, 0);
1070 unsigned int p1, p2, p3;
1072 /* Prefetch next 4 CQEs. */
1073 if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
1074 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP]);
1075 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 1]);
1076 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 2]);
1077 rte_prefetch0(&cq[pos + MLX5_VPMD_DESCS_PER_LOOP + 3]);
1079 /* A.0 do not cross the end of CQ. */
1080 mask = _mm_set_epi64x(0, (pkts_n - pos) * sizeof(uint16_t) * 8);
1081 mask = _mm_sll_epi64(ones, mask);
1082 p = _mm_andnot_si128(mask, p);
1083 /* A.1 load cqes. */
1084 p3 = _mm_extract_epi16(p, 3);
1085 cqes[3] = _mm_loadl_epi64((__m128i *)
1086 &cq[pos + p3].sop_drop_qpn);
1087 rte_compiler_barrier();
1088 p2 = _mm_extract_epi16(p, 2);
1089 cqes[2] = _mm_loadl_epi64((__m128i *)
1090 &cq[pos + p2].sop_drop_qpn);
1091 rte_compiler_barrier();
1092 /* B.1 load mbuf pointers. */
1093 mbp1 = _mm_loadu_si128((__m128i *)&elts[pos]);
1094 mbp2 = _mm_loadu_si128((__m128i *)&elts[pos + 2]);
1095 /* A.1 load a block having op_own. */
1096 p1 = _mm_extract_epi16(p, 1);
1097 cqes[1] = _mm_loadl_epi64((__m128i *)
1098 &cq[pos + p1].sop_drop_qpn);
1099 rte_compiler_barrier();
1100 cqes[0] = _mm_loadl_epi64((__m128i *)
1101 &cq[pos].sop_drop_qpn);
1102 /* B.2 copy mbuf pointers. */
1103 _mm_storeu_si128((__m128i *)&pkts[pos], mbp1);
1104 _mm_storeu_si128((__m128i *)&pkts[pos + 2], mbp2);
1105 rte_compiler_barrier();
1106 /* C.1 load remained CQE data and extract necessary fields. */
1107 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p3]);
1108 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos + p2]);
1109 cqes[3] = _mm_blendv_epi8(cqes[3], cqe_tmp2, blend_mask);
1110 cqes[2] = _mm_blendv_epi8(cqes[2], cqe_tmp1, blend_mask);
1111 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p3].rsvd1[3]);
1112 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos + p2].rsvd1[3]);
1113 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x30);
1114 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x30);
1115 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p3].rsvd2[10]);
1116 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos + p2].rsvd2[10]);
1117 cqes[3] = _mm_blend_epi16(cqes[3], cqe_tmp2, 0x04);
1118 cqes[2] = _mm_blend_epi16(cqes[2], cqe_tmp1, 0x04);
1119 /* C.2 generate final structure for mbuf with swapping bytes. */
1120 pkt_mb3 = _mm_shuffle_epi8(cqes[3], shuf_mask);
1121 pkt_mb2 = _mm_shuffle_epi8(cqes[2], shuf_mask);
1122 /* C.3 adjust CRC length. */
1123 pkt_mb3 = _mm_sub_epi16(pkt_mb3, crc_adj);
1124 pkt_mb2 = _mm_sub_epi16(pkt_mb2, crc_adj);
1125 /* C.4 adjust flow mark. */
1126 pkt_mb3 = _mm_add_epi32(pkt_mb3, flow_mark_adj);
1127 pkt_mb2 = _mm_add_epi32(pkt_mb2, flow_mark_adj);
1128 /* D.1 fill in mbuf - rx_descriptor_fields1. */
1129 _mm_storeu_si128((void *)&pkts[pos + 3]->pkt_len, pkt_mb3);
1130 _mm_storeu_si128((void *)&pkts[pos + 2]->pkt_len, pkt_mb2);
1131 /* E.1 extract op_own field. */
1132 op_own_tmp2 = _mm_unpacklo_epi32(cqes[2], cqes[3]);
1133 /* C.1 load remained CQE data and extract necessary fields. */
1134 cqe_tmp2 = _mm_load_si128((__m128i *)&cq[pos + p1]);
1135 cqe_tmp1 = _mm_load_si128((__m128i *)&cq[pos]);
1136 cqes[1] = _mm_blendv_epi8(cqes[1], cqe_tmp2, blend_mask);
1137 cqes[0] = _mm_blendv_epi8(cqes[0], cqe_tmp1, blend_mask);
1138 cqe_tmp2 = _mm_loadu_si128((__m128i *)&cq[pos + p1].rsvd1[3]);
1139 cqe_tmp1 = _mm_loadu_si128((__m128i *)&cq[pos].rsvd1[3]);
1140 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x30);
1141 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x30);
1142 cqe_tmp2 = _mm_loadl_epi64((__m128i *)&cq[pos + p1].rsvd2[10]);
1143 cqe_tmp1 = _mm_loadl_epi64((__m128i *)&cq[pos].rsvd2[10]);
1144 cqes[1] = _mm_blend_epi16(cqes[1], cqe_tmp2, 0x04);
1145 cqes[0] = _mm_blend_epi16(cqes[0], cqe_tmp1, 0x04);
1146 /* C.2 generate final structure for mbuf with swapping bytes. */
1147 pkt_mb1 = _mm_shuffle_epi8(cqes[1], shuf_mask);
1148 pkt_mb0 = _mm_shuffle_epi8(cqes[0], shuf_mask);
1149 /* C.3 adjust CRC length. */
1150 pkt_mb1 = _mm_sub_epi16(pkt_mb1, crc_adj);
1151 pkt_mb0 = _mm_sub_epi16(pkt_mb0, crc_adj);
1152 /* C.4 adjust flow mark. */
1153 pkt_mb1 = _mm_add_epi32(pkt_mb1, flow_mark_adj);
1154 pkt_mb0 = _mm_add_epi32(pkt_mb0, flow_mark_adj);
1155 /* E.1 extract op_own byte. */
1156 op_own_tmp1 = _mm_unpacklo_epi32(cqes[0], cqes[1]);
1157 op_own = _mm_unpackhi_epi64(op_own_tmp1, op_own_tmp2);
1158 /* D.1 fill in mbuf - rx_descriptor_fields1. */
1159 _mm_storeu_si128((void *)&pkts[pos + 1]->pkt_len, pkt_mb1);
1160 _mm_storeu_si128((void *)&pkts[pos]->pkt_len, pkt_mb0);
1161 /* E.2 flip owner bit to mark CQEs from last round. */
1162 owner_mask = _mm_and_si128(op_own, owner_check);
1164 owner_mask = _mm_xor_si128(owner_mask, owner_check);
1165 owner_mask = _mm_cmpeq_epi32(owner_mask, owner_check);
1166 owner_mask = _mm_packs_epi32(owner_mask, zero);
1167 /* E.3 get mask for invalidated CQEs. */
1168 opcode = _mm_and_si128(op_own, opcode_check);
1169 invalid_mask = _mm_cmpeq_epi32(opcode_check, opcode);
1170 invalid_mask = _mm_packs_epi32(invalid_mask, zero);
1171 /* E.4 mask out beyond boundary. */
1172 invalid_mask = _mm_or_si128(invalid_mask, mask);
1173 /* E.5 merge invalid_mask with invalid owner. */
1174 invalid_mask = _mm_or_si128(invalid_mask, owner_mask);
1175 /* F.1 find compressed CQE format. */
1176 comp_mask = _mm_and_si128(op_own, format_check);
1177 comp_mask = _mm_cmpeq_epi32(comp_mask, format_check);
1178 comp_mask = _mm_packs_epi32(comp_mask, zero);
1179 /* F.2 mask out invalid entries. */
1180 comp_mask = _mm_andnot_si128(invalid_mask, comp_mask);
1181 comp_idx = _mm_cvtsi128_si64(comp_mask);
1182 /* F.3 get the first compressed CQE. */
1183 comp_idx = comp_idx ?
1184 __builtin_ctzll(comp_idx) /
1185 (sizeof(uint16_t) * 8) :
1186 MLX5_VPMD_DESCS_PER_LOOP;
1187 /* E.6 mask out entries after the compressed CQE. */
1188 mask = _mm_set_epi64x(0, comp_idx * sizeof(uint16_t) * 8);
1189 mask = _mm_sll_epi64(ones, mask);
1190 invalid_mask = _mm_or_si128(invalid_mask, mask);
1191 /* E.7 count non-compressed valid CQEs. */
1192 n = _mm_cvtsi128_si64(invalid_mask);
1193 n = n ? __builtin_ctzll(n) / (sizeof(uint16_t) * 8) :
1194 MLX5_VPMD_DESCS_PER_LOOP;
1196 /* D.2 get the final invalid mask. */
1197 mask = _mm_set_epi64x(0, n * sizeof(uint16_t) * 8);
1198 mask = _mm_sll_epi64(ones, mask);
1199 invalid_mask = _mm_or_si128(invalid_mask, mask);
1200 /* D.3 check error in opcode. */
1201 opcode = _mm_cmpeq_epi32(resp_err_check, opcode);
1202 opcode = _mm_packs_epi32(opcode, zero);
1203 opcode = _mm_andnot_si128(invalid_mask, opcode);
1204 /* D.4 mark if any error is set */
1205 rxq->pending_err |= !!_mm_cvtsi128_si64(opcode);
1206 /* D.5 fill in mbuf - rearm_data and packet_type. */
1207 rxq_cq_to_ptype_oflags_v(rxq, cqes, opcode, &pkts[pos]);
1208 #ifdef MLX5_PMD_SOFT_COUNTERS
1209 /* Add up received bytes count. */
1210 byte_cnt = _mm_shuffle_epi8(op_own, len_shuf_mask);
1211 byte_cnt = _mm_andnot_si128(invalid_mask, byte_cnt);
1212 byte_cnt = _mm_hadd_epi16(byte_cnt, zero);
1213 rcvd_byte += _mm_cvtsi128_si64(_mm_hadd_epi16(byte_cnt, zero));
1216 * Break the loop unless more valid CQE is expected, or if
1217 * there's a compressed CQE.
1219 if (n != MLX5_VPMD_DESCS_PER_LOOP)
1222 /* If no new CQE seen, return without updating cq_db. */
1223 if (unlikely(!nocmp_n && comp_idx == MLX5_VPMD_DESCS_PER_LOOP))
1225 /* Update the consumer indexes for non-compressed CQEs. */
1226 assert(nocmp_n <= pkts_n);
1227 rxq->cq_ci += nocmp_n;
1228 rxq->rq_pi += nocmp_n;
1229 rcvd_pkt += nocmp_n;
1230 #ifdef MLX5_PMD_SOFT_COUNTERS
1231 rxq->stats.ipackets += nocmp_n;
1232 rxq->stats.ibytes += rcvd_byte;
1234 /* Decompress the last CQE if compressed. */
1235 if (comp_idx < MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n) {
1236 assert(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));
1237 rxq_cq_decompress_v(rxq, &cq[nocmp_n], &elts[nocmp_n]);
1238 /* Return more packets if needed. */
1239 if (nocmp_n < pkts_n) {
1240 uint16_t n = rxq->cq_ci - rxq->rq_pi;
1242 n = RTE_MIN(n, pkts_n - nocmp_n);
1243 rxq_copy_mbuf_v(rxq, &pkts[nocmp_n], n);
1249 *rxq->cq_db = htonl(rxq->cq_ci);
1254 * DPDK callback for vectorized RX.
1257 * Generic pointer to RX queue structure.
1259 * Array to store received packets.
1261 * Maximum number of packets in array.
1264 * Number of packets successfully received (<= pkts_n).
1267 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1269 struct rxq *rxq = dpdk_rxq;
1272 nb_rx = rxq_burst_v(rxq, pkts, pkts_n);
1273 if (unlikely(rxq->pending_err))
1274 nb_rx = rxq_handle_pending_error(rxq, pkts, nb_rx);
1279 * Check Tx queue flags are set for raw vectorized Tx.
1282 * Pointer to private structure.
1285 * 1 if supported, negative errno value if not.
1287 int __attribute__((cold))
1288 priv_check_raw_vec_tx_support(struct priv *priv)
1292 /* All the configured queues should support. */
1293 for (i = 0; i < priv->txqs_n; ++i) {
1294 struct txq *txq = (*priv->txqs)[i];
1296 if (!(txq->flags & ETH_TXQ_FLAGS_NOMULTSEGS) ||
1297 !(txq->flags & ETH_TXQ_FLAGS_NOOFFLOADS))
1300 if (i != priv->txqs_n)
1306 * Check a device can support vectorized TX.
1309 * Pointer to private structure.
1312 * 1 if supported, negative errno value if not.
1314 int __attribute__((cold))
1315 priv_check_vec_tx_support(struct priv *priv)
1317 if (!priv->tx_vec_en ||
1318 priv->txqs_n > MLX5_VPMD_MIN_TXQS ||
1319 priv->mps != MLX5_MPW_ENHANCED ||
1326 * Check a RX queue can support vectorized RX.
1329 * Pointer to RX queue.
1332 * 1 if supported, negative errno value if not.
1334 int __attribute__((cold))
1335 rxq_check_vec_support(struct rxq *rxq)
1337 struct rxq_ctrl *ctrl = container_of(rxq, struct rxq_ctrl, rxq);
1339 if (!ctrl->priv->rx_vec_en || rxq->sges_n != 0)
1345 * Check a device can support vectorized RX.
1348 * Pointer to private structure.
1351 * 1 if supported, negative errno value if not.
1353 int __attribute__((cold))
1354 priv_check_vec_rx_support(struct priv *priv)
1358 if (!priv->rx_vec_en)
1360 /* All the configured queues should support. */
1361 for (i = 0; i < priv->rxqs_n; ++i) {
1362 struct rxq *rxq = (*priv->rxqs)[i];
1364 if (rxq_check_vec_support(rxq) < 0)
1367 if (i != priv->rxqs_n)