2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
47 #include <rte_debug.h>
48 #include <rte_ethdev.h>
50 #include <rte_ether.h>
51 #include <rte_malloc.h>
52 #include <rte_memzone.h>
53 #include <rte_mempool.h>
54 #include <rte_version.h>
55 #include <rte_string_fns.h>
56 #include <rte_alarm.h>
57 #include <rte_spinlock.h>
59 #include "nfp_net_pmd.h"
60 #include "nfp_net_logs.h"
61 #include "nfp_net_ctrl.h"
64 static void nfp_net_close(struct rte_eth_dev *dev);
65 static int nfp_net_configure(struct rte_eth_dev *dev);
66 static void nfp_net_dev_interrupt_handler(void *param);
67 static void nfp_net_dev_interrupt_delayed_handler(void *param);
68 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
69 static void nfp_net_infos_get(struct rte_eth_dev *dev,
70 struct rte_eth_dev_info *dev_info);
71 static int nfp_net_init(struct rte_eth_dev *eth_dev);
72 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
73 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
74 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
75 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
76 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
78 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
80 static void nfp_net_rx_queue_release(void *rxq);
81 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
82 uint16_t nb_desc, unsigned int socket_id,
83 const struct rte_eth_rxconf *rx_conf,
84 struct rte_mempool *mp);
85 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
86 static void nfp_net_tx_queue_release(void *txq);
87 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
88 uint16_t nb_desc, unsigned int socket_id,
89 const struct rte_eth_txconf *tx_conf);
90 static int nfp_net_start(struct rte_eth_dev *dev);
91 static void nfp_net_stats_get(struct rte_eth_dev *dev,
92 struct rte_eth_stats *stats);
93 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
94 static void nfp_net_stop(struct rte_eth_dev *dev);
95 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
99 * The offset of the queue controller queues in the PCIe Target. These
100 * happen to be at the same offset on the NFP6000 and the NFP3200 so
101 * we use a single macro here.
103 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
105 /* Maximum value which can be added to a queue with one transaction */
106 #define NFP_QCP_MAX_ADD 0x7f
108 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
109 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
111 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
113 NFP_QCP_READ_PTR = 0,
118 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
119 * @q: Base address for queue structure
120 * @ptr: Add to the Read or Write pointer
121 * @val: Value to add to the queue pointer
123 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
126 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
130 if (ptr == NFP_QCP_READ_PTR)
131 off = NFP_QCP_QUEUE_ADD_RPTR;
133 off = NFP_QCP_QUEUE_ADD_WPTR;
135 while (val > NFP_QCP_MAX_ADD) {
136 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
137 val -= NFP_QCP_MAX_ADD;
140 nn_writel(rte_cpu_to_le_32(val), q + off);
144 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
145 * @q: Base address for queue structure
146 * @ptr: Read or Write pointer
148 static inline uint32_t
149 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
154 if (ptr == NFP_QCP_READ_PTR)
155 off = NFP_QCP_QUEUE_STS_LO;
157 off = NFP_QCP_QUEUE_STS_HI;
159 val = rte_cpu_to_le_32(nn_readl(q + off));
161 if (ptr == NFP_QCP_READ_PTR)
162 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
164 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
168 * Functions to read/write from/to Config BAR
169 * Performs any endian conversion necessary.
171 static inline uint8_t
172 nn_cfg_readb(struct nfp_net_hw *hw, int off)
174 return nn_readb(hw->ctrl_bar + off);
178 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
180 nn_writeb(val, hw->ctrl_bar + off);
183 static inline uint32_t
184 nn_cfg_readl(struct nfp_net_hw *hw, int off)
186 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
190 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
192 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
195 static inline uint64_t
196 nn_cfg_readq(struct nfp_net_hw *hw, int off)
198 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
202 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
204 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
207 /* Creating memzone for hardware rings. */
208 static const struct rte_memzone *
209 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
210 uint16_t queue_id, uint32_t ring_size, int socket_id)
212 char z_name[RTE_MEMZONE_NAMESIZE];
213 const struct rte_memzone *mz;
215 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
216 dev->driver->pci_drv.driver.name,
217 ring_name, dev->data->port_id, queue_id);
219 mz = rte_memzone_lookup(z_name);
223 return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,
228 * Atomically reads link status information from global structure rte_eth_dev.
231 * - Pointer to the structure rte_eth_dev to read from.
232 * - Pointer to the buffer to be saved with the link status.
235 * - On success, zero.
236 * - On failure, negative value.
239 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
240 struct rte_eth_link *link)
242 struct rte_eth_link *dst = link;
243 struct rte_eth_link *src = &dev->data->dev_link;
245 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
246 *(uint64_t *)src) == 0)
253 * Atomically writes the link status information into global
254 * structure rte_eth_dev.
257 * - Pointer to the structure rte_eth_dev to read from.
258 * - Pointer to the buffer to be saved with the link status.
261 * - On success, zero.
262 * - On failure, negative value.
265 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
266 struct rte_eth_link *link)
268 struct rte_eth_link *dst = &dev->data->dev_link;
269 struct rte_eth_link *src = link;
271 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
272 *(uint64_t *)src) == 0)
279 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
283 if (rxq->rxbufs == NULL)
286 for (i = 0; i < rxq->rx_count; i++) {
287 if (rxq->rxbufs[i].mbuf) {
288 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
289 rxq->rxbufs[i].mbuf = NULL;
295 nfp_net_rx_queue_release(void *rx_queue)
297 struct nfp_net_rxq *rxq = rx_queue;
300 nfp_net_rx_queue_release_mbufs(rxq);
301 rte_free(rxq->rxbufs);
307 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
309 nfp_net_rx_queue_release_mbufs(rxq);
315 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
319 if (txq->txbufs == NULL)
322 for (i = 0; i < txq->tx_count; i++) {
323 if (txq->txbufs[i].mbuf) {
324 rte_pktmbuf_free(txq->txbufs[i].mbuf);
325 txq->txbufs[i].mbuf = NULL;
331 nfp_net_tx_queue_release(void *tx_queue)
333 struct nfp_net_txq *txq = tx_queue;
336 nfp_net_tx_queue_release_mbufs(txq);
337 rte_free(txq->txbufs);
343 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
345 nfp_net_tx_queue_release_mbufs(txq);
351 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
355 struct timespec wait;
357 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
360 if (hw->qcp_cfg == NULL)
361 rte_panic("Bad configuration queue pointer\n");
363 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
366 wait.tv_nsec = 1000000;
368 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
370 /* Poll update field, waiting for NFP to ack the config */
371 for (cnt = 0; ; cnt++) {
372 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
375 if (new & NFP_NET_CFG_UPDATE_ERR) {
376 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x", new);
379 if (cnt >= NFP_NET_POLL_TIMEOUT) {
380 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
381 " %dms", update, cnt);
382 rte_panic("Exiting\n");
384 nanosleep(&wait, 0); /* waiting for a 1ms */
386 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
391 * Reconfigure the NIC
392 * @nn: device to reconfigure
393 * @ctrl: The value for the ctrl field in the BAR config
394 * @update: The value for the update field in the BAR config
396 * Write the update word to the BAR and ping the reconfig queue. Then poll
397 * until the firmware has acknowledged the update by zeroing the update word.
400 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
404 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
407 rte_spinlock_lock(&hw->reconfig_lock);
409 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
410 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
414 err = __nfp_net_reconfig(hw, update);
416 rte_spinlock_unlock(&hw->reconfig_lock);
422 * Reconfig errors imply situations where they can be handled.
423 * Otherwise, rte_panic is called inside __nfp_net_reconfig
425 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x",
431 * Configure an Ethernet device. This function must be invoked first
432 * before any other function in the Ethernet API. This function can
433 * also be re-invoked when a device is in the stopped state.
436 nfp_net_configure(struct rte_eth_dev *dev)
438 struct rte_eth_conf *dev_conf;
439 struct rte_eth_rxmode *rxmode;
440 struct rte_eth_txmode *txmode;
441 uint32_t new_ctrl = 0;
443 struct nfp_net_hw *hw;
445 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
448 * A DPDK app sends info about how many queues to use and how
449 * those queues need to be configured. This is used by the
450 * DPDK core and it makes sure no more queues than those
451 * advertised by the driver are requested. This function is
452 * called after that internal process
455 PMD_INIT_LOG(DEBUG, "Configure");
457 dev_conf = &dev->data->dev_conf;
458 rxmode = &dev_conf->rxmode;
459 txmode = &dev_conf->txmode;
461 /* Checking TX mode */
462 if (txmode->mq_mode) {
463 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported");
467 /* Checking RX mode */
468 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
469 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
470 update = NFP_NET_CFG_UPDATE_RSS;
471 new_ctrl = NFP_NET_CFG_CTRL_RSS;
473 PMD_INIT_LOG(INFO, "RSS not supported");
478 if (rxmode->split_hdr_size) {
479 PMD_INIT_LOG(INFO, "rxmode does not support split header");
483 if (rxmode->hw_ip_checksum) {
484 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
485 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
487 PMD_INIT_LOG(INFO, "RXCSUM not supported");
492 if (rxmode->hw_vlan_filter) {
493 PMD_INIT_LOG(INFO, "VLAN filter not supported");
497 if (rxmode->hw_vlan_strip) {
498 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
499 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
501 PMD_INIT_LOG(INFO, "hw vlan strip not supported");
506 if (rxmode->hw_vlan_extend) {
507 PMD_INIT_LOG(INFO, "VLAN extended not supported");
511 /* Supporting VLAN insertion by default */
512 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
513 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
515 if (rxmode->jumbo_frame)
516 /* this is handled in rte_eth_dev_configure */
518 if (rxmode->hw_strip_crc) {
519 PMD_INIT_LOG(INFO, "strip CRC not supported");
523 if (rxmode->enable_scatter) {
524 PMD_INIT_LOG(INFO, "Scatter not supported");
531 update |= NFP_NET_CFG_UPDATE_GEN;
533 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
534 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
543 nfp_net_enable_queues(struct rte_eth_dev *dev)
545 struct nfp_net_hw *hw;
546 uint64_t enabled_queues = 0;
549 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
551 /* Enabling the required TX queues in the device */
552 for (i = 0; i < dev->data->nb_tx_queues; i++)
553 enabled_queues |= (1 << i);
555 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
559 /* Enabling the required RX queues in the device */
560 for (i = 0; i < dev->data->nb_rx_queues; i++)
561 enabled_queues |= (1 << i);
563 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
567 nfp_net_disable_queues(struct rte_eth_dev *dev)
569 struct nfp_net_hw *hw;
570 uint32_t new_ctrl, update = 0;
572 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
574 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
575 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
577 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
578 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
579 NFP_NET_CFG_UPDATE_MSIX;
581 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
582 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
584 /* If an error when reconfig we avoid to change hw state */
585 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
592 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
596 for (i = 0; i < dev->data->nb_rx_queues; i++) {
597 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
604 nfp_net_params_setup(struct nfp_net_hw *hw)
606 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
607 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
611 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
613 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
616 static void nfp_net_read_mac(struct nfp_net_hw *hw)
620 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR));
621 memcpy(&hw->mac_addr[0], &tmp, sizeof(struct ether_addr));
623 tmp = rte_be_to_cpu_32(nn_cfg_readl(hw, NFP_NET_CFG_MACADDR + 4));
624 memcpy(&hw->mac_addr[4], &tmp, 2);
628 nfp_configure_rx_interrupt(struct rte_eth_dev *dev,
629 struct rte_intr_handle *intr_handle)
631 struct nfp_net_hw *hw;
634 if (!intr_handle->intr_vec) {
635 intr_handle->intr_vec =
636 rte_zmalloc("intr_vec",
637 dev->data->nb_rx_queues * sizeof(int), 0);
638 if (!intr_handle->intr_vec) {
639 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
640 " intr_vec", dev->data->nb_rx_queues);
645 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
647 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
648 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with UIO");
649 /* UIO just supports one queue and no LSC*/
650 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(0), 0);
652 PMD_INIT_LOG(INFO, "VF: enabling RX interrupt with VFIO");
653 for (i = 0; i < dev->data->nb_rx_queues; i++)
655 * The first msix vector is reserved for non
658 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_VEC(i), i + 1);
661 /* Avoiding TX interrupts */
662 hw->ctrl |= NFP_NET_CFG_CTRL_MSIX_TX_OFF;
667 nfp_net_start(struct rte_eth_dev *dev)
669 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
670 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
671 uint32_t new_ctrl, update = 0;
672 struct nfp_net_hw *hw;
673 uint32_t intr_vector;
676 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
678 PMD_INIT_LOG(DEBUG, "Start");
680 /* Disabling queues just in case... */
681 nfp_net_disable_queues(dev);
683 /* Writing configuration parameters in the device */
684 nfp_net_params_setup(hw);
686 /* Enabling the required queues in the device */
687 nfp_net_enable_queues(dev);
689 /* check and configure queue intr-vector mapping */
690 if (dev->data->dev_conf.intr_conf.rxq != 0) {
691 if (intr_handle->type == RTE_INTR_HANDLE_UIO) {
693 * Better not to share LSC with RX interrupts.
694 * Unregistering LSC interrupt handler
696 rte_intr_callback_unregister(&pci_dev->intr_handle,
697 nfp_net_dev_interrupt_handler, (void *)dev);
699 if (dev->data->nb_rx_queues > 1) {
700 PMD_INIT_LOG(ERR, "PMD rx interrupt only "
701 "supports 1 queue with UIO");
705 intr_vector = dev->data->nb_rx_queues;
706 if (rte_intr_efd_enable(intr_handle, intr_vector))
710 if (rte_intr_dp_is_en(intr_handle))
711 nfp_configure_rx_interrupt(dev, intr_handle);
713 rte_intr_enable(intr_handle);
716 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE;
717 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
719 /* Just configuring queues interrupts when necessary */
720 if (rte_intr_dp_is_en(intr_handle))
721 update |= NFP_NET_CFG_UPDATE_MSIX;
723 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
724 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
726 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
727 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
731 * Allocating rte mbuffs for configured rx queues.
732 * This requires queues being enabled before
734 if (nfp_net_rx_freelist_setup(dev) < 0) {
745 * An error returned by this function should mean the app
746 * exiting and then the system releasing all the memory
747 * allocated even memory coming from hugepages.
749 * The device could be enabled at this point with some queues
750 * ready for getting packets. This is true if the call to
751 * nfp_net_rx_freelist_setup() succeeds for some queues but
752 * fails for subsequent queues.
754 * This should make the app exiting but better if we tell the
757 nfp_net_disable_queues(dev);
762 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
764 nfp_net_stop(struct rte_eth_dev *dev)
768 PMD_INIT_LOG(DEBUG, "Stop");
770 nfp_net_disable_queues(dev);
773 for (i = 0; i < dev->data->nb_tx_queues; i++) {
774 nfp_net_reset_tx_queue(
775 (struct nfp_net_txq *)dev->data->tx_queues[i]);
778 for (i = 0; i < dev->data->nb_rx_queues; i++) {
779 nfp_net_reset_rx_queue(
780 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
784 /* Reset and stop device. The device can not be restarted. */
786 nfp_net_close(struct rte_eth_dev *dev)
788 struct nfp_net_hw *hw;
789 struct rte_pci_device *pci_dev;
791 PMD_INIT_LOG(DEBUG, "Close");
793 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
794 pci_dev = RTE_DEV_TO_PCI(dev->device);
797 * We assume that the DPDK application is stopping all the
798 * threads/queues before calling the device close function.
803 rte_intr_disable(&pci_dev->intr_handle);
804 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
806 /* unregister callback func from eal lib */
807 rte_intr_callback_unregister(&pci_dev->intr_handle,
808 nfp_net_dev_interrupt_handler,
812 * The ixgbe PMD driver disables the pcie master on the
813 * device. The i40e does not...
818 nfp_net_promisc_enable(struct rte_eth_dev *dev)
820 uint32_t new_ctrl, update = 0;
821 struct nfp_net_hw *hw;
823 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
825 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
827 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
828 PMD_INIT_LOG(INFO, "Promiscuous mode not supported");
832 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
833 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
837 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
838 update = NFP_NET_CFG_UPDATE_GEN;
841 * DPDK sets promiscuous mode on just after this call assuming
842 * it can not fail ...
844 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
851 nfp_net_promisc_disable(struct rte_eth_dev *dev)
853 uint32_t new_ctrl, update = 0;
854 struct nfp_net_hw *hw;
856 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
858 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
859 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
863 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
864 update = NFP_NET_CFG_UPDATE_GEN;
867 * DPDK sets promiscuous mode off just before this call
868 * assuming it can not fail ...
870 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
877 * return 0 means link status changed, -1 means not changed
879 * Wait to complete is needed as it can take up to 9 seconds to get the Link
883 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
885 struct nfp_net_hw *hw;
886 struct rte_eth_link link, old;
887 uint32_t nn_link_status;
889 static const uint32_t ls_to_ethtool[] = {
890 [NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED] = ETH_SPEED_NUM_NONE,
891 [NFP_NET_CFG_STS_LINK_RATE_UNKNOWN] = ETH_SPEED_NUM_NONE,
892 [NFP_NET_CFG_STS_LINK_RATE_1G] = ETH_SPEED_NUM_1G,
893 [NFP_NET_CFG_STS_LINK_RATE_10G] = ETH_SPEED_NUM_10G,
894 [NFP_NET_CFG_STS_LINK_RATE_25G] = ETH_SPEED_NUM_25G,
895 [NFP_NET_CFG_STS_LINK_RATE_40G] = ETH_SPEED_NUM_40G,
896 [NFP_NET_CFG_STS_LINK_RATE_50G] = ETH_SPEED_NUM_50G,
897 [NFP_NET_CFG_STS_LINK_RATE_100G] = ETH_SPEED_NUM_100G,
900 PMD_DRV_LOG(DEBUG, "Link update\n");
902 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
904 memset(&old, 0, sizeof(old));
905 nfp_net_dev_atomic_read_link_status(dev, &old);
907 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
909 memset(&link, 0, sizeof(struct rte_eth_link));
911 if (nn_link_status & NFP_NET_CFG_STS_LINK)
912 link.link_status = ETH_LINK_UP;
914 link.link_duplex = ETH_LINK_FULL_DUPLEX;
916 nn_link_status = (nn_link_status >> NFP_NET_CFG_STS_LINK_RATE_SHIFT) &
917 NFP_NET_CFG_STS_LINK_RATE_MASK;
919 if ((NFD_CFG_MAJOR_VERSION_of(hw->ver) < 4) ||
920 ((NFD_CFG_MINOR_VERSION_of(hw->ver) == 4) &&
921 (NFD_CFG_MINOR_VERSION_of(hw->ver) == 0)))
922 /* We really do not know the speed wil old firmware */
923 link.link_speed = ETH_SPEED_NUM_NONE;
925 if (nn_link_status >= RTE_DIM(ls_to_ethtool))
926 link.link_speed = ETH_SPEED_NUM_NONE;
928 link.link_speed = ls_to_ethtool[nn_link_status];
931 if (old.link_status != link.link_status) {
932 nfp_net_dev_atomic_write_link_status(dev, &link);
933 if (link.link_status)
934 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
936 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
944 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
947 struct nfp_net_hw *hw;
948 struct rte_eth_stats nfp_dev_stats;
950 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
952 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
954 /* reading per RX ring stats */
955 for (i = 0; i < dev->data->nb_rx_queues; i++) {
956 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
959 nfp_dev_stats.q_ipackets[i] =
960 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
962 nfp_dev_stats.q_ipackets[i] -=
963 hw->eth_stats_base.q_ipackets[i];
965 nfp_dev_stats.q_ibytes[i] =
966 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
968 nfp_dev_stats.q_ibytes[i] -=
969 hw->eth_stats_base.q_ibytes[i];
972 /* reading per TX ring stats */
973 for (i = 0; i < dev->data->nb_tx_queues; i++) {
974 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
977 nfp_dev_stats.q_opackets[i] =
978 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
980 nfp_dev_stats.q_opackets[i] -=
981 hw->eth_stats_base.q_opackets[i];
983 nfp_dev_stats.q_obytes[i] =
984 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
986 nfp_dev_stats.q_obytes[i] -=
987 hw->eth_stats_base.q_obytes[i];
990 nfp_dev_stats.ipackets =
991 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
993 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
995 nfp_dev_stats.ibytes =
996 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
998 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
1000 nfp_dev_stats.opackets =
1001 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1003 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
1005 nfp_dev_stats.obytes =
1006 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1008 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
1010 /* reading general device stats */
1011 nfp_dev_stats.ierrors =
1012 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1014 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
1016 nfp_dev_stats.oerrors =
1017 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1019 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
1021 /* RX ring mbuf allocation failures */
1022 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1024 nfp_dev_stats.imissed =
1025 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1027 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
1030 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
1034 nfp_net_stats_reset(struct rte_eth_dev *dev)
1037 struct nfp_net_hw *hw;
1039 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1042 * hw->eth_stats_base records the per counter starting point.
1043 * Lets update it now
1046 /* reading per RX ring stats */
1047 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1048 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1051 hw->eth_stats_base.q_ipackets[i] =
1052 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
1054 hw->eth_stats_base.q_ibytes[i] =
1055 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
1058 /* reading per TX ring stats */
1059 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1060 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
1063 hw->eth_stats_base.q_opackets[i] =
1064 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
1066 hw->eth_stats_base.q_obytes[i] =
1067 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
1070 hw->eth_stats_base.ipackets =
1071 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
1073 hw->eth_stats_base.ibytes =
1074 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
1076 hw->eth_stats_base.opackets =
1077 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
1079 hw->eth_stats_base.obytes =
1080 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
1082 /* reading general device stats */
1083 hw->eth_stats_base.ierrors =
1084 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1086 hw->eth_stats_base.oerrors =
1087 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1089 /* RX ring mbuf allocation failures */
1090 dev->data->rx_mbuf_alloc_failed = 0;
1092 hw->eth_stats_base.imissed =
1093 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1097 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1099 struct nfp_net_hw *hw;
1101 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1103 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1104 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1105 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1106 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1107 dev_info->max_rx_pktlen = hw->mtu;
1108 /* Next should change when PF support is implemented */
1109 dev_info->max_mac_addrs = 1;
1111 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1112 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1114 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1115 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1116 DEV_RX_OFFLOAD_UDP_CKSUM |
1117 DEV_RX_OFFLOAD_TCP_CKSUM;
1119 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1120 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1122 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1123 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1124 DEV_TX_OFFLOAD_UDP_CKSUM |
1125 DEV_TX_OFFLOAD_TCP_CKSUM;
1127 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1129 .pthresh = DEFAULT_RX_PTHRESH,
1130 .hthresh = DEFAULT_RX_HTHRESH,
1131 .wthresh = DEFAULT_RX_WTHRESH,
1133 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1137 dev_info->default_txconf = (struct rte_eth_txconf) {
1139 .pthresh = DEFAULT_TX_PTHRESH,
1140 .hthresh = DEFAULT_TX_HTHRESH,
1141 .wthresh = DEFAULT_TX_WTHRESH,
1143 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1144 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1145 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1146 ETH_TXQ_FLAGS_NOOFFLOADS,
1149 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1150 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1152 dev_info->speed_capa = ETH_SPEED_NUM_1G | ETH_LINK_SPEED_10G |
1153 ETH_SPEED_NUM_25G | ETH_SPEED_NUM_40G |
1154 ETH_SPEED_NUM_50G | ETH_LINK_SPEED_100G;
1156 if (hw->cap & NFP_NET_CFG_CTRL_LSO)
1157 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO;
1160 static const uint32_t *
1161 nfp_net_supported_ptypes_get(struct rte_eth_dev *dev)
1163 static const uint32_t ptypes[] = {
1164 /* refers to nfp_net_set_hash() */
1165 RTE_PTYPE_INNER_L3_IPV4,
1166 RTE_PTYPE_INNER_L3_IPV6,
1167 RTE_PTYPE_INNER_L3_IPV6_EXT,
1168 RTE_PTYPE_INNER_L4_MASK,
1172 if (dev->rx_pkt_burst == nfp_net_recv_pkts)
1178 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1180 struct nfp_net_rxq *rxq;
1181 struct nfp_net_rx_desc *rxds;
1185 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1192 * Other PMDs are just checking the DD bit in intervals of 4
1193 * descriptors and counting all four if the first has the DD
1194 * bit on. Of course, this is not accurate but can be good for
1195 * perfomance. But ideally that should be done in descriptors
1196 * chunks belonging to the same cache line
1199 while (count < rxq->rx_count) {
1200 rxds = &rxq->rxds[idx];
1201 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1208 if ((idx) == rxq->rx_count)
1216 nfp_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1218 struct rte_pci_device *pci_dev;
1219 struct nfp_net_hw *hw;
1222 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1223 pci_dev = RTE_DEV_TO_PCI(dev->device);
1225 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1228 /* Make sure all updates are written before un-masking */
1230 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id),
1231 NFP_NET_CFG_ICR_UNMASKED);
1236 nfp_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1238 struct rte_pci_device *pci_dev;
1239 struct nfp_net_hw *hw;
1242 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1243 pci_dev = RTE_DEV_TO_PCI(dev->device);
1245 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UIO)
1248 /* Make sure all updates are written before un-masking */
1250 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(base + queue_id), 0x1);
1255 nfp_net_dev_link_status_print(struct rte_eth_dev *dev)
1257 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1258 struct rte_eth_link link;
1260 memset(&link, 0, sizeof(link));
1261 nfp_net_dev_atomic_read_link_status(dev, &link);
1262 if (link.link_status)
1263 RTE_LOG(INFO, PMD, "Port %d: Link Up - speed %u Mbps - %s\n",
1264 (int)(dev->data->port_id), (unsigned)link.link_speed,
1265 link.link_duplex == ETH_LINK_FULL_DUPLEX
1266 ? "full-duplex" : "half-duplex");
1268 RTE_LOG(INFO, PMD, " Port %d: Link Down\n",
1269 (int)(dev->data->port_id));
1271 RTE_LOG(INFO, PMD, "PCI Address: %04d:%02d:%02d:%d\n",
1272 pci_dev->addr.domain, pci_dev->addr.bus,
1273 pci_dev->addr.devid, pci_dev->addr.function);
1276 /* Interrupt configuration and handling */
1279 * nfp_net_irq_unmask - Unmask an interrupt
1281 * If MSI-X auto-masking is enabled clear the mask bit, otherwise
1282 * clear the ICR for the entry.
1285 nfp_net_irq_unmask(struct rte_eth_dev *dev)
1287 struct nfp_net_hw *hw;
1288 struct rte_pci_device *pci_dev;
1290 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1291 pci_dev = RTE_DEV_TO_PCI(dev->device);
1293 if (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {
1294 /* If MSI-X auto-masking is used, clear the entry */
1296 rte_intr_enable(&pci_dev->intr_handle);
1298 /* Make sure all updates are written before un-masking */
1300 nn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),
1301 NFP_NET_CFG_ICR_UNMASKED);
1306 nfp_net_dev_interrupt_handler(void *param)
1309 struct rte_eth_link link;
1310 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1312 PMD_DRV_LOG(DEBUG, "We got a LSC interrupt!!!\n");
1314 /* get the link status */
1315 memset(&link, 0, sizeof(link));
1316 nfp_net_dev_atomic_read_link_status(dev, &link);
1318 nfp_net_link_update(dev, 0);
1321 if (!link.link_status) {
1322 /* handle it 1 sec later, wait it being stable */
1323 timeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;
1324 /* likely to down */
1326 /* handle it 4 sec later, wait it being stable */
1327 timeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;
1330 if (rte_eal_alarm_set(timeout * 1000,
1331 nfp_net_dev_interrupt_delayed_handler,
1333 RTE_LOG(ERR, PMD, "Error setting alarm");
1335 nfp_net_irq_unmask(dev);
1340 * Interrupt handler which shall be registered for alarm callback for delayed
1341 * handling specific interrupt to wait for the stable nic state. As the NIC
1342 * interrupt state is not stable for nfp after link is just down, it needs
1343 * to wait 4 seconds to get the stable status.
1345 * @param handle Pointer to interrupt handle.
1346 * @param param The address of parameter (struct rte_eth_dev *)
1351 nfp_net_dev_interrupt_delayed_handler(void *param)
1353 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1355 nfp_net_link_update(dev, 0);
1356 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1358 nfp_net_dev_link_status_print(dev);
1361 nfp_net_irq_unmask(dev);
1365 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1367 struct nfp_net_hw *hw;
1369 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1371 /* check that mtu is within the allowed range */
1372 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1375 /* switch to jumbo mode if needed */
1376 if ((uint32_t)mtu > ETHER_MAX_LEN)
1377 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1379 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1381 /* update max frame size */
1382 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1384 /* writing to configuration space */
1385 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1393 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1394 uint16_t queue_idx, uint16_t nb_desc,
1395 unsigned int socket_id,
1396 const struct rte_eth_rxconf *rx_conf,
1397 struct rte_mempool *mp)
1399 const struct rte_memzone *tz;
1400 struct nfp_net_rxq *rxq;
1401 struct nfp_net_hw *hw;
1403 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1405 PMD_INIT_FUNC_TRACE();
1407 /* Validating number of descriptors */
1408 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1409 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1410 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1411 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1416 * Free memory prior to re-allocation if needed. This is the case after
1417 * calling nfp_net_stop
1419 if (dev->data->rx_queues[queue_idx]) {
1420 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1421 dev->data->rx_queues[queue_idx] = NULL;
1424 /* Allocating rx queue data structure */
1425 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1426 RTE_CACHE_LINE_SIZE, socket_id);
1430 /* Hw queues mapping based on firmware confifguration */
1431 rxq->qidx = queue_idx;
1432 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1433 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1434 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1435 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1438 * Tracking mbuf size for detecting a potential mbuf overflow due to
1442 rxq->mbuf_size = rxq->mem_pool->elt_size;
1443 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1444 hw->flbufsz = rxq->mbuf_size;
1446 rxq->rx_count = nb_desc;
1447 rxq->port_id = dev->data->port_id;
1448 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1449 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1451 rxq->drop_en = rx_conf->rx_drop_en;
1454 * Allocate RX ring hardware descriptors. A memzone large enough to
1455 * handle the maximum ring size is allocated in order to allow for
1456 * resizing in later calls to the queue setup function.
1458 tz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1459 sizeof(struct nfp_net_rx_desc) *
1460 NFP_NET_MAX_RX_DESC, socket_id);
1463 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1464 nfp_net_rx_queue_release(rxq);
1468 /* Saving physical and virtual addresses for the RX ring */
1469 rxq->dma = (uint64_t)tz->phys_addr;
1470 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1472 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1473 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1474 sizeof(*rxq->rxbufs) * nb_desc,
1475 RTE_CACHE_LINE_SIZE, socket_id);
1476 if (rxq->rxbufs == NULL) {
1477 nfp_net_rx_queue_release(rxq);
1481 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1482 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1484 nfp_net_reset_rx_queue(rxq);
1486 dev->data->rx_queues[queue_idx] = rxq;
1490 * Telling the HW about the physical address of the RX ring and number
1491 * of descriptors in log2 format
1493 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1494 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1500 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1502 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1506 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1509 for (i = 0; i < rxq->rx_count; i++) {
1510 struct nfp_net_rx_desc *rxd;
1511 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1514 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1515 (unsigned)rxq->qidx);
1519 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1521 rxd = &rxq->rxds[i];
1523 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1524 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1526 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1529 /* Make sure all writes are flushed before telling the hardware */
1532 /* Not advertising the whole ring as the firmware gets confused if so */
1533 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1536 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1542 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1543 uint16_t nb_desc, unsigned int socket_id,
1544 const struct rte_eth_txconf *tx_conf)
1546 const struct rte_memzone *tz;
1547 struct nfp_net_txq *txq;
1548 uint16_t tx_free_thresh;
1549 struct nfp_net_hw *hw;
1551 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1553 PMD_INIT_FUNC_TRACE();
1555 /* Validating number of descriptors */
1556 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1557 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1558 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1559 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1563 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1564 tx_conf->tx_free_thresh :
1565 DEFAULT_TX_FREE_THRESH);
1567 if (tx_free_thresh > (nb_desc)) {
1569 "tx_free_thresh must be less than the number of TX "
1570 "descriptors. (tx_free_thresh=%u port=%d "
1571 "queue=%d)\n", (unsigned int)tx_free_thresh,
1572 (int)dev->data->port_id, (int)queue_idx);
1577 * Free memory prior to re-allocation if needed. This is the case after
1578 * calling nfp_net_stop
1580 if (dev->data->tx_queues[queue_idx]) {
1581 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1583 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1584 dev->data->tx_queues[queue_idx] = NULL;
1587 /* Allocating tx queue data structure */
1588 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1589 RTE_CACHE_LINE_SIZE, socket_id);
1591 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1596 * Allocate TX ring hardware descriptors. A memzone large enough to
1597 * handle the maximum ring size is allocated in order to allow for
1598 * resizing in later calls to the queue setup function.
1600 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1601 sizeof(struct nfp_net_tx_desc) *
1602 NFP_NET_MAX_TX_DESC, socket_id);
1604 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1605 nfp_net_tx_queue_release(txq);
1609 txq->tx_count = nb_desc;
1610 txq->tx_free_thresh = tx_free_thresh;
1611 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1612 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1613 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1615 /* queue mapping based on firmware configuration */
1616 txq->qidx = queue_idx;
1617 txq->tx_qcidx = queue_idx * hw->stride_tx;
1618 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1620 txq->port_id = dev->data->port_id;
1621 txq->txq_flags = tx_conf->txq_flags;
1623 /* Saving physical and virtual addresses for the TX ring */
1624 txq->dma = (uint64_t)tz->phys_addr;
1625 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1627 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1628 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1629 sizeof(*txq->txbufs) * nb_desc,
1630 RTE_CACHE_LINE_SIZE, socket_id);
1631 if (txq->txbufs == NULL) {
1632 nfp_net_tx_queue_release(txq);
1635 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1636 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1638 nfp_net_reset_tx_queue(txq);
1640 dev->data->tx_queues[queue_idx] = txq;
1644 * Telling the HW about the physical address of the TX ring and number
1645 * of descriptors in log2 format
1647 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1648 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1653 /* nfp_net_tx_tso - Set TX descriptor for TSO */
1655 nfp_net_tx_tso(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1656 struct rte_mbuf *mb)
1659 struct nfp_net_hw *hw = txq->hw;
1661 if (!(hw->cap & NFP_NET_CFG_CTRL_LSO))
1664 ol_flags = mb->ol_flags;
1666 if (!(ol_flags & PKT_TX_TCP_SEG))
1669 txd->l4_offset = mb->l2_len + mb->l3_len + mb->l4_len;
1670 txd->lso = rte_cpu_to_le_16(mb->tso_segsz);
1671 txd->flags = PCIE_DESC_TX_LSO;
1680 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1682 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1683 struct rte_mbuf *mb)
1686 struct nfp_net_hw *hw = txq->hw;
1688 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1691 ol_flags = mb->ol_flags;
1693 /* IPv6 does not need checksum */
1694 if (ol_flags & PKT_TX_IP_CKSUM)
1695 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1697 switch (ol_flags & PKT_TX_L4_MASK) {
1698 case PKT_TX_UDP_CKSUM:
1699 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1701 case PKT_TX_TCP_CKSUM:
1702 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1706 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
1707 txd->flags |= PCIE_DESC_TX_CSUM;
1710 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1712 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1713 struct rte_mbuf *mb)
1715 struct nfp_net_hw *hw = rxq->hw;
1717 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1720 /* If IPv4 and IP checksum error, fail */
1721 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1722 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1723 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1725 /* If neither UDP nor TCP return */
1726 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1727 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1730 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1731 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1732 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1734 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1735 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1736 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1739 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1740 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1743 * nfp_net_set_hash - Set mbuf hash data
1745 * The RSS hash and hash-type are pre-pended to the packet data.
1746 * Extract and decode it and set the mbuf fields.
1749 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1750 struct rte_mbuf *mbuf)
1754 struct nfp_net_hw *hw = rxq->hw;
1756 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1759 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1762 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1763 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1765 mbuf->hash.rss = hash;
1766 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1768 switch (hash_type) {
1769 case NFP_NET_RSS_IPV4:
1770 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1772 case NFP_NET_RSS_IPV6:
1773 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1775 case NFP_NET_RSS_IPV6_EX:
1776 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1779 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1784 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1786 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1789 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1794 * There are some decissions to take:
1795 * 1) How to check DD RX descriptors bit
1796 * 2) How and when to allocate new mbufs
1798 * Current implementation checks just one single DD bit each loop. As each
1799 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1800 * a single cache line instead. Tests with this change have not shown any
1801 * performance improvement but it requires further investigation. For example,
1802 * depending on which descriptor is next, the number of descriptors could be
1803 * less than 8 for just checking those in the same cache line. This implies
1804 * extra work which could be counterproductive by itself. Indeed, last firmware
1805 * changes are just doing this: writing several descriptors with the DD bit
1806 * for saving PCIe bandwidth and DMA operations from the NFP.
1808 * Mbuf allocation is done when a new packet is received. Then the descriptor
1809 * is automatically linked with the new mbuf and the old one is given to the
1810 * user. The main drawback with this design is mbuf allocation is heavier than
1811 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1812 * cache point of view it does not seem allocating the mbuf early on as we are
1813 * doing now have any benefit at all. Again, tests with this change have not
1814 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1815 * so looking at the implications of this type of allocation should be studied
1820 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1822 struct nfp_net_rxq *rxq;
1823 struct nfp_net_rx_desc *rxds;
1824 struct nfp_net_rx_buff *rxb;
1825 struct nfp_net_hw *hw;
1826 struct rte_mbuf *mb;
1827 struct rte_mbuf *new_mb;
1833 if (unlikely(rxq == NULL)) {
1835 * DPDK just checks the queue is lower than max queues
1836 * enabled. But the queue needs to be configured
1838 RTE_LOG_DP(ERR, PMD, "RX Bad queue\n");
1846 while (avail < nb_pkts) {
1847 rxb = &rxq->rxbufs[rxq->rd_p];
1848 if (unlikely(rxb == NULL)) {
1849 RTE_LOG_DP(ERR, PMD, "rxb does not exist!\n");
1854 * Memory barrier to ensure that we won't do other
1855 * reads before the DD bit.
1859 rxds = &rxq->rxds[rxq->rd_p];
1860 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1864 * We got a packet. Let's alloc a new mbuff for refilling the
1865 * free descriptor ring as soon as possible
1867 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1868 if (unlikely(new_mb == NULL)) {
1869 RTE_LOG_DP(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1870 "queue_id=%u\n", (unsigned)rxq->port_id,
1871 (unsigned)rxq->qidx);
1872 nfp_net_mbuf_alloc_failed(rxq);
1879 * Grab the mbuff and refill the descriptor with the
1880 * previously allocated mbuff
1885 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1886 rxds->rxd.data_len, rxq->mbuf_size);
1888 /* Size of this segment */
1889 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1890 /* Size of the whole packet. We just support 1 segment */
1891 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1893 if (unlikely((mb->data_len + hw->rx_offset) >
1896 * This should not happen and the user has the
1897 * responsibility of avoiding it. But we have
1898 * to give some info about the error
1900 RTE_LOG_DP(ERR, PMD,
1901 "mbuf overflow likely due to the RX offset.\n"
1902 "\t\tYour mbuf size should have extra space for"
1903 " RX offset=%u bytes.\n"
1904 "\t\tCurrently you just have %u bytes available"
1905 " but the received packet is %u bytes long",
1907 rxq->mbuf_size - hw->rx_offset,
1912 /* Filling the received mbuff with packet info */
1914 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1916 mb->data_off = RTE_PKTMBUF_HEADROOM +
1917 NFP_DESC_META_LEN(rxds);
1919 /* No scatter mode supported */
1923 /* Checking the RSS flag */
1924 nfp_net_set_hash(rxq, rxds, mb);
1926 /* Checking the checksum flag */
1927 nfp_net_rx_cksum(rxq, rxds, mb);
1929 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1930 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1931 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1932 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1935 /* Adding the mbuff to the mbuff array passed by the app */
1936 rx_pkts[avail++] = mb;
1938 /* Now resetting and updating the descriptor */
1941 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1943 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1944 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1947 if (unlikely(rxq->rd_p == rxq->rx_count)) /* wrapping?*/
1954 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1955 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1957 nb_hold += rxq->nb_rx_hold;
1960 * FL descriptors needs to be written before incrementing the
1961 * FL queue WR pointer
1964 if (nb_hold > rxq->rx_free_thresh) {
1965 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1966 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1967 (unsigned)nb_hold, (unsigned)avail);
1968 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1971 rxq->nb_rx_hold = nb_hold;
1977 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1979 * @txq: TX queue to work with
1980 * Returns number of descriptors freed
1983 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1988 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1989 " status\n", txq->qidx);
1991 /* Work out how many packets have been sent */
1992 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1994 if (qcp_rd_p == txq->rd_p) {
1995 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1996 "packets (%u, %u)\n", txq->qidx,
1997 qcp_rd_p, txq->rd_p);
2001 if (qcp_rd_p > txq->rd_p)
2002 todo = qcp_rd_p - txq->rd_p;
2004 todo = qcp_rd_p + txq->tx_count - txq->rd_p;
2006 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->rd_p: %u, qcp->rd_p: %u\n",
2007 qcp_rd_p, txq->rd_p, txq->rd_p);
2013 if (unlikely(txq->rd_p >= txq->tx_count))
2014 txq->rd_p -= txq->tx_count;
2019 /* Leaving always free descriptors for avoiding wrapping confusion */
2021 uint32_t nfp_free_tx_desc(struct nfp_net_txq *txq)
2023 if (txq->wr_p >= txq->rd_p)
2024 return txq->tx_count - (txq->wr_p - txq->rd_p) - 8;
2026 return txq->rd_p - txq->wr_p - 8;
2030 * nfp_net_txq_full - Check if the TX queue free descriptors
2031 * is below tx_free_threshold
2033 * @txq: TX queue to check
2035 * This function uses the host copy* of read/write pointers
2038 uint32_t nfp_net_txq_full(struct nfp_net_txq *txq)
2040 return (nfp_free_tx_desc(txq) < txq->tx_free_thresh);
2044 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2046 struct nfp_net_txq *txq;
2047 struct nfp_net_hw *hw;
2048 struct nfp_net_tx_desc *txds, txd;
2049 struct rte_mbuf *pkt;
2051 int pkt_size, dma_size;
2052 uint16_t free_descs, issued_descs;
2053 struct rte_mbuf **lmbuf;
2058 txds = &txq->txds[txq->wr_p];
2060 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
2061 txq->qidx, txq->wr_p, nb_pkts);
2063 if ((nfp_free_tx_desc(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
2064 nfp_net_tx_free_bufs(txq);
2066 free_descs = (uint16_t)nfp_free_tx_desc(txq);
2067 if (unlikely(free_descs == 0))
2074 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
2075 txq->qidx, nb_pkts);
2076 /* Sending packets */
2077 while ((i < nb_pkts) && free_descs) {
2078 /* Grabbing the mbuf linked to the current descriptor */
2079 lmbuf = &txq->txbufs[txq->wr_p].mbuf;
2080 /* Warming the cache for releasing the mbuf later on */
2081 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
2083 pkt = *(tx_pkts + i);
2085 if (unlikely((pkt->nb_segs > 1) &&
2086 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
2087 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set");
2088 rte_panic("Multisegment packet unsupported\n");
2091 /* Checking if we have enough descriptors */
2092 if (unlikely(pkt->nb_segs > free_descs))
2096 * Checksum and VLAN flags just in the first descriptor for a
2097 * multisegment packet, but TSO info needs to be in all of them.
2099 txd.data_len = pkt->pkt_len;
2100 nfp_net_tx_tso(txq, &txd, pkt);
2101 nfp_net_tx_cksum(txq, &txd, pkt);
2103 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
2104 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
2105 txd.flags |= PCIE_DESC_TX_VLAN;
2106 txd.vlan = pkt->vlan_tci;
2110 * mbuf data_len is the data in one segment and pkt_len data
2111 * in the whole packet. When the packet is just one segment,
2112 * then data_len = pkt_len
2114 pkt_size = pkt->pkt_len;
2116 /* Releasing mbuf which was prefetched above */
2118 rte_pktmbuf_free(*lmbuf);
2120 * Linking mbuf with descriptor for being released
2121 * next time descriptor is used
2126 /* Copying TSO, VLAN and cksum info */
2128 dma_size = pkt->data_len;
2129 dma_addr = rte_mbuf_data_dma_addr(pkt);
2130 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
2131 "%" PRIx64 "\n", dma_addr);
2133 /* Filling descriptors fields */
2134 txds->dma_len = dma_size;
2135 txds->data_len = txd.data_len;
2136 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
2137 txds->dma_addr_lo = (dma_addr & 0xffffffff);
2138 ASSERT(free_descs > 0);
2142 if (unlikely(txq->wr_p == txq->tx_count)) /* wrapping?*/
2145 pkt_size -= dma_size;
2148 txds->offset_eop |= PCIE_DESC_TX_EOP;
2150 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
2153 /* Referencing next free TX descriptor */
2154 txds = &txq->txds[txq->wr_p];
2161 /* Increment write pointers. Force memory write before we let HW know */
2163 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
2169 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2171 uint32_t new_ctrl, update;
2172 struct nfp_net_hw *hw;
2174 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
2178 (mask & ETH_VLAN_EXTEND_OFFLOAD))
2179 RTE_LOG(INFO, PMD, "No support for ETH_VLAN_FILTER_OFFLOAD or"
2180 " ETH_VLAN_EXTEND_OFFLOAD");
2182 /* Enable vlan strip if it is not configured yet */
2183 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
2184 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2185 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
2187 /* Disable vlan strip just if it is configured */
2188 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
2189 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
2190 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
2195 update = NFP_NET_CFG_UPDATE_GEN;
2197 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
2200 hw->ctrl = new_ctrl;
2203 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
2205 nfp_net_reta_update(struct rte_eth_dev *dev,
2206 struct rte_eth_rss_reta_entry64 *reta_conf,
2209 uint32_t reta, mask;
2213 struct nfp_net_hw *hw =
2214 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2219 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2220 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2221 "(%d) doesn't match the number hardware can supported "
2222 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2227 * Update Redirection Table. There are 128 8bit-entries which can be
2228 * manage as 32 32bit-entries
2230 for (i = 0; i < reta_size; i += 4) {
2231 /* Handling 4 RSS entries per loop */
2232 idx = i / RTE_RETA_GROUP_SIZE;
2233 shift = i % RTE_RETA_GROUP_SIZE;
2234 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2240 /* If all 4 entries were set, don't need read RETA register */
2242 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2244 for (j = 0; j < 4; j++) {
2245 if (!(mask & (0x1 << j)))
2248 /* Clearing the entry bits */
2249 reta &= ~(0xFF << (8 * j));
2250 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2252 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
2255 update = NFP_NET_CFG_UPDATE_RSS;
2257 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2263 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2265 nfp_net_reta_query(struct rte_eth_dev *dev,
2266 struct rte_eth_rss_reta_entry64 *reta_conf,
2272 struct nfp_net_hw *hw;
2274 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2276 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2279 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2280 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2281 "(%d) doesn't match the number hardware can supported "
2282 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2287 * Reading Redirection Table. There are 128 8bit-entries which can be
2288 * manage as 32 32bit-entries
2290 for (i = 0; i < reta_size; i += 4) {
2291 /* Handling 4 RSS entries per loop */
2292 idx = i / RTE_RETA_GROUP_SIZE;
2293 shift = i % RTE_RETA_GROUP_SIZE;
2294 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2299 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
2300 for (j = 0; j < 4; j++) {
2301 if (!(mask & (0x1 << j)))
2303 reta_conf->reta[shift + j] =
2304 (uint8_t)((reta >> (8 * j)) & 0xF);
2311 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2312 struct rte_eth_rss_conf *rss_conf)
2315 uint32_t cfg_rss_ctrl = 0;
2319 struct nfp_net_hw *hw;
2321 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2323 rss_hf = rss_conf->rss_hf;
2325 /* Checking if RSS is enabled */
2326 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2327 if (rss_hf != 0) { /* Enable RSS? */
2328 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2331 return 0; /* Nothing to do */
2334 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2335 RTE_LOG(ERR, PMD, "hash key too long\n");
2339 if (rss_hf & ETH_RSS_IPV4)
2340 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2341 NFP_NET_CFG_RSS_IPV4_TCP |
2342 NFP_NET_CFG_RSS_IPV4_UDP;
2344 if (rss_hf & ETH_RSS_IPV6)
2345 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2346 NFP_NET_CFG_RSS_IPV6_TCP |
2347 NFP_NET_CFG_RSS_IPV6_UDP;
2349 /* configuring where to apply the RSS hash */
2350 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2352 /* Writing the key byte a byte */
2353 for (i = 0; i < rss_conf->rss_key_len; i++) {
2354 memcpy(&key, &rss_conf->rss_key[i], 1);
2355 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2358 /* Writing the key size */
2359 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2361 update = NFP_NET_CFG_UPDATE_RSS;
2363 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2370 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2371 struct rte_eth_rss_conf *rss_conf)
2374 uint32_t cfg_rss_ctrl;
2377 struct nfp_net_hw *hw;
2379 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2381 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2384 rss_hf = rss_conf->rss_hf;
2385 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2387 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2388 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2390 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2391 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2393 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2394 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2396 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2397 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2399 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2400 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2402 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2403 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2405 /* Reading the key size */
2406 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2408 /* Reading the key byte a byte */
2409 for (i = 0; i < rss_conf->rss_key_len; i++) {
2410 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2411 memcpy(&rss_conf->rss_key[i], &key, 1);
2417 /* Initialise and register driver with DPDK Application */
2418 static const struct eth_dev_ops nfp_net_eth_dev_ops = {
2419 .dev_configure = nfp_net_configure,
2420 .dev_start = nfp_net_start,
2421 .dev_stop = nfp_net_stop,
2422 .dev_close = nfp_net_close,
2423 .promiscuous_enable = nfp_net_promisc_enable,
2424 .promiscuous_disable = nfp_net_promisc_disable,
2425 .link_update = nfp_net_link_update,
2426 .stats_get = nfp_net_stats_get,
2427 .stats_reset = nfp_net_stats_reset,
2428 .dev_infos_get = nfp_net_infos_get,
2429 .dev_supported_ptypes_get = nfp_net_supported_ptypes_get,
2430 .mtu_set = nfp_net_dev_mtu_set,
2431 .vlan_offload_set = nfp_net_vlan_offload_set,
2432 .reta_update = nfp_net_reta_update,
2433 .reta_query = nfp_net_reta_query,
2434 .rss_hash_update = nfp_net_rss_hash_update,
2435 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2436 .rx_queue_setup = nfp_net_rx_queue_setup,
2437 .rx_queue_release = nfp_net_rx_queue_release,
2438 .rx_queue_count = nfp_net_rx_queue_count,
2439 .tx_queue_setup = nfp_net_tx_queue_setup,
2440 .tx_queue_release = nfp_net_tx_queue_release,
2441 .rx_queue_intr_enable = nfp_rx_queue_intr_enable,
2442 .rx_queue_intr_disable = nfp_rx_queue_intr_disable,
2446 nfp_net_init(struct rte_eth_dev *eth_dev)
2448 struct rte_pci_device *pci_dev;
2449 struct nfp_net_hw *hw;
2451 uint32_t tx_bar_off, rx_bar_off;
2455 PMD_INIT_FUNC_TRACE();
2457 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2459 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2460 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2461 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2463 /* For secondary processes, the primary has done all the work */
2464 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2467 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2468 rte_eth_copy_pci_info(eth_dev, pci_dev);
2469 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2471 hw->device_id = pci_dev->id.device_id;
2472 hw->vendor_id = pci_dev->id.vendor_id;
2473 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2474 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2476 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u",
2477 pci_dev->id.vendor_id, pci_dev->id.device_id,
2478 pci_dev->addr.domain, pci_dev->addr.bus,
2479 pci_dev->addr.devid, pci_dev->addr.function);
2481 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2482 if (hw->ctrl_bar == NULL) {
2484 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2487 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2488 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2490 /* Work out where in the BAR the queues start. */
2491 switch (pci_dev->id.device_id) {
2492 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2493 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2494 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2495 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2496 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2499 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2503 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x", tx_bar_off);
2504 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x", rx_bar_off);
2506 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2507 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2509 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p",
2510 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2512 nfp_net_cfg_queue_setup(hw);
2514 /* Get some of the read-only fields from the config BAR */
2515 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2516 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2517 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2518 hw->mtu = hw->max_mtu;
2520 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2521 hw->rx_offset = NFP_NET_RX_OFFSET;
2523 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2525 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d",
2526 hw->ver, hw->max_mtu);
2527 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s", hw->cap,
2528 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2529 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2530 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2531 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2532 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2533 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2534 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2535 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2536 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2540 hw->stride_rx = stride;
2541 hw->stride_tx = stride;
2543 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u",
2544 hw->max_rx_queues, hw->max_tx_queues);
2546 /* Initializing spinlock for reconfigs */
2547 rte_spinlock_init(&hw->reconfig_lock);
2549 /* Allocating memory for mac addr */
2550 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2551 if (eth_dev->data->mac_addrs == NULL) {
2552 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2556 nfp_net_read_mac(hw);
2558 if (!is_valid_assigned_ether_addr((struct ether_addr *)&hw->mac_addr))
2559 /* Using random mac addresses for VFs */
2560 eth_random_addr(&hw->mac_addr[0]);
2562 /* Copying mac address to DPDK eth_dev struct */
2563 ether_addr_copy((struct ether_addr *)hw->mac_addr,
2564 ð_dev->data->mac_addrs[0]);
2566 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2567 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2568 eth_dev->data->port_id, pci_dev->id.vendor_id,
2569 pci_dev->id.device_id,
2570 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2571 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2573 /* Registering LSC interrupt handler */
2574 rte_intr_callback_register(&pci_dev->intr_handle,
2575 nfp_net_dev_interrupt_handler,
2578 /* Telling the firmware about the LSC interrupt entry */
2579 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);
2581 /* Recording current stats counters values */
2582 nfp_net_stats_reset(eth_dev);
2587 static const struct rte_pci_id pci_id_nfp_net_map[] = {
2589 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2590 PCI_DEVICE_ID_NFP6000_PF_NIC)
2593 RTE_PCI_DEVICE(PCI_VENDOR_ID_NETRONOME,
2594 PCI_DEVICE_ID_NFP6000_VF_NIC)
2601 static struct eth_driver rte_nfp_net_pmd = {
2603 .id_table = pci_id_nfp_net_map,
2604 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2605 .probe = rte_eth_dev_pci_probe,
2606 .remove = rte_eth_dev_pci_remove,
2608 .eth_dev_init = nfp_net_init,
2609 .dev_private_size = sizeof(struct nfp_net_adapter),
2612 RTE_PMD_REGISTER_PCI(net_nfp, rte_nfp_net_pmd.pci_drv);
2613 RTE_PMD_REGISTER_PCI_TABLE(net_nfp, pci_id_nfp_net_map);
2614 RTE_PMD_REGISTER_KMOD_DEP(net_nfp, "* igb_uio | uio_pci_generic | vfio");
2618 * c-file-style: "Linux"
2619 * indent-tabs-mode: t