2 * Copyright (c) 2014, 2015 Netronome Systems, Inc.
5 * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
35 * vim:shiftwidth=8:noexpandtab
37 * @file dpdk/pmd/nfp_net.c
39 * Netronome vNIC DPDK Poll-Mode Driver: Main entry point
48 #include <sys/socket.h>
55 #include <rte_byteorder.h>
56 #include <rte_common.h>
58 #include <rte_debug.h>
59 #include <rte_ethdev.h>
61 #include <rte_ether.h>
62 #include <rte_malloc.h>
63 #include <rte_memzone.h>
64 #include <rte_mempool.h>
65 #include <rte_version.h>
66 #include <rte_string_fns.h>
67 #include <rte_alarm.h>
69 #include "nfp_net_pmd.h"
70 #include "nfp_net_logs.h"
71 #include "nfp_net_ctrl.h"
74 static void nfp_net_close(struct rte_eth_dev *dev);
75 static int nfp_net_configure(struct rte_eth_dev *dev);
76 static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
77 static void nfp_net_infos_get(struct rte_eth_dev *dev,
78 struct rte_eth_dev_info *dev_info);
79 static int nfp_net_init(struct rte_eth_dev *eth_dev);
80 static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);
81 static void nfp_net_promisc_enable(struct rte_eth_dev *dev);
82 static void nfp_net_promisc_disable(struct rte_eth_dev *dev);
83 static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);
84 static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,
86 static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
88 static void nfp_net_rx_queue_release(void *rxq);
89 static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
90 uint16_t nb_desc, unsigned int socket_id,
91 const struct rte_eth_rxconf *rx_conf,
92 struct rte_mempool *mp);
93 static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);
94 static void nfp_net_tx_queue_release(void *txq);
95 static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
96 uint16_t nb_desc, unsigned int socket_id,
97 const struct rte_eth_txconf *tx_conf);
98 static int nfp_net_start(struct rte_eth_dev *dev);
99 static void nfp_net_stats_get(struct rte_eth_dev *dev,
100 struct rte_eth_stats *stats);
101 static void nfp_net_stats_reset(struct rte_eth_dev *dev);
102 static void nfp_net_stop(struct rte_eth_dev *dev);
103 static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
107 * The offset of the queue controller queues in the PCIe Target. These
108 * happen to be at the same offset on the NFP6000 and the NFP3200 so
109 * we use a single macro here.
111 #define NFP_PCIE_QUEUE(_q) (0x80000 + (0x800 * ((_q) & 0xff)))
113 /* Maximum value which can be added to a queue with one transaction */
114 #define NFP_QCP_MAX_ADD 0x7f
116 #define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \
117 (uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
119 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
121 NFP_QCP_READ_PTR = 0,
126 * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue
127 * @q: Base address for queue structure
128 * @ptr: Add to the Read or Write pointer
129 * @val: Value to add to the queue pointer
131 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
134 nfp_qcp_ptr_add(uint8_t *q, enum nfp_qcp_ptr ptr, uint32_t val)
138 if (ptr == NFP_QCP_READ_PTR)
139 off = NFP_QCP_QUEUE_ADD_RPTR;
141 off = NFP_QCP_QUEUE_ADD_WPTR;
143 while (val > NFP_QCP_MAX_ADD) {
144 nn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);
145 val -= NFP_QCP_MAX_ADD;
148 nn_writel(rte_cpu_to_le_32(val), q + off);
152 * nfp_qcp_read - Read the current Read/Write pointer value for a queue
153 * @q: Base address for queue structure
154 * @ptr: Read or Write pointer
156 static inline uint32_t
157 nfp_qcp_read(uint8_t *q, enum nfp_qcp_ptr ptr)
162 if (ptr == NFP_QCP_READ_PTR)
163 off = NFP_QCP_QUEUE_STS_LO;
165 off = NFP_QCP_QUEUE_STS_HI;
167 val = rte_cpu_to_le_32(nn_readl(q + off));
169 if (ptr == NFP_QCP_READ_PTR)
170 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
172 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
176 * Functions to read/write from/to Config BAR
177 * Performs any endian conversion necessary.
179 static inline uint8_t
180 nn_cfg_readb(struct nfp_net_hw *hw, int off)
182 return nn_readb(hw->ctrl_bar + off);
186 nn_cfg_writeb(struct nfp_net_hw *hw, int off, uint8_t val)
188 nn_writeb(val, hw->ctrl_bar + off);
191 static inline uint32_t
192 nn_cfg_readl(struct nfp_net_hw *hw, int off)
194 return rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));
198 nn_cfg_writel(struct nfp_net_hw *hw, int off, uint32_t val)
200 nn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);
203 static inline uint64_t
204 nn_cfg_readq(struct nfp_net_hw *hw, int off)
206 return rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));
210 nn_cfg_writeq(struct nfp_net_hw *hw, int off, uint64_t val)
212 nn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);
215 /* Creating memzone for hardware rings. */
216 static const struct rte_memzone *
217 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
218 uint16_t queue_id, uint32_t ring_size, int socket_id)
220 char z_name[RTE_MEMZONE_NAMESIZE];
221 const struct rte_memzone *mz;
223 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
224 dev->driver->pci_drv.name,
225 ring_name, dev->data->port_id, queue_id);
227 mz = rte_memzone_lookup(z_name);
231 return rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,
236 * Atomically reads link status information from global structure rte_eth_dev.
239 * - Pointer to the structure rte_eth_dev to read from.
240 * - Pointer to the buffer to be saved with the link status.
243 * - On success, zero.
244 * - On failure, negative value.
247 nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,
248 struct rte_eth_link *link)
250 struct rte_eth_link *dst = link;
251 struct rte_eth_link *src = &dev->data->dev_link;
253 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
254 *(uint64_t *)src) == 0)
261 * Atomically writes the link status information into global
262 * structure rte_eth_dev.
265 * - Pointer to the structure rte_eth_dev to read from.
266 * - Pointer to the buffer to be saved with the link status.
269 * - On success, zero.
270 * - On failure, negative value.
273 nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,
274 struct rte_eth_link *link)
276 struct rte_eth_link *dst = &dev->data->dev_link;
277 struct rte_eth_link *src = link;
279 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
280 *(uint64_t *)src) == 0)
287 nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)
291 if (rxq->rxbufs == NULL)
294 for (i = 0; i < rxq->rx_count; i++) {
295 if (rxq->rxbufs[i].mbuf) {
296 rte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);
297 rxq->rxbufs[i].mbuf = NULL;
303 nfp_net_rx_queue_release(void *rx_queue)
305 struct nfp_net_rxq *rxq = rx_queue;
308 nfp_net_rx_queue_release_mbufs(rxq);
309 rte_free(rxq->rxbufs);
315 nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)
317 nfp_net_rx_queue_release_mbufs(rxq);
324 nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)
328 if (txq->txbufs == NULL)
331 for (i = 0; i < txq->tx_count; i++) {
332 if (txq->txbufs[i].mbuf) {
333 rte_pktmbuf_free_seg(txq->txbufs[i].mbuf);
334 txq->txbufs[i].mbuf = NULL;
340 nfp_net_tx_queue_release(void *tx_queue)
342 struct nfp_net_txq *txq = tx_queue;
345 nfp_net_tx_queue_release_mbufs(txq);
346 rte_free(txq->txbufs);
352 nfp_net_reset_tx_queue(struct nfp_net_txq *txq)
354 nfp_net_tx_queue_release_mbufs(txq);
361 __nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t update)
365 struct timespec wait;
367 PMD_DRV_LOG(DEBUG, "Writing to the configuration queue (%p)...\n",
370 if (hw->qcp_cfg == NULL)
371 rte_panic("Bad configuration queue pointer\n");
373 nfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);
376 wait.tv_nsec = 1000000;
378 PMD_DRV_LOG(DEBUG, "Polling for update ack...\n");
380 /* Poll update field, waiting for NFP to ack the config */
381 for (cnt = 0; ; cnt++) {
382 new = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);
385 if (new & NFP_NET_CFG_UPDATE_ERR) {
386 PMD_INIT_LOG(ERR, "Reconfig error: 0x%08x\n", new);
389 if (cnt >= NFP_NET_POLL_TIMEOUT) {
390 PMD_INIT_LOG(ERR, "Reconfig timeout for 0x%08x after"
391 " %dms\n", update, cnt);
392 rte_panic("Exiting\n");
394 nanosleep(&wait, 0); /* waiting for a 1ms */
396 PMD_DRV_LOG(DEBUG, "Ack DONE\n");
401 * Reconfigure the NIC
402 * @nn: device to reconfigure
403 * @ctrl: The value for the ctrl field in the BAR config
404 * @update: The value for the update field in the BAR config
406 * Write the update word to the BAR and ping the reconfig queue. Then poll
407 * until the firmware has acknowledged the update by zeroing the update word.
410 nfp_net_reconfig(struct nfp_net_hw *hw, uint32_t ctrl, uint32_t update)
414 PMD_DRV_LOG(DEBUG, "nfp_net_reconfig: ctrl=%08x update=%08x\n",
417 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);
418 nn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);
422 err = __nfp_net_reconfig(hw, update);
428 * Reconfig errors imply situations where they can be handled.
429 * Otherwise, rte_panic is called inside __nfp_net_reconfig
431 PMD_INIT_LOG(ERR, "Error nfp_net reconfig for ctrl: %x update: %x\n",
437 * Configure an Ethernet device. This function must be invoked first
438 * before any other function in the Ethernet API. This function can
439 * also be re-invoked when a device is in the stopped state.
442 nfp_net_configure(struct rte_eth_dev *dev)
444 struct rte_eth_conf *dev_conf;
445 struct rte_eth_rxmode *rxmode;
446 struct rte_eth_txmode *txmode;
447 uint32_t new_ctrl = 0;
449 struct nfp_net_hw *hw;
451 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
454 * A DPDK app sends info about how many queues to use and how
455 * those queues need to be configured. This is used by the
456 * DPDK core and it makes sure no more queues than those
457 * advertised by the driver are requested. This function is
458 * called after that internal process
461 PMD_INIT_LOG(DEBUG, "Configure\n");
463 dev_conf = &dev->data->dev_conf;
464 rxmode = &dev_conf->rxmode;
465 txmode = &dev_conf->txmode;
467 /* Checking TX mode */
468 if (txmode->mq_mode) {
469 PMD_INIT_LOG(INFO, "TX mq_mode DCB and VMDq not supported\n");
473 /* Checking RX mode */
474 if (rxmode->mq_mode & ETH_MQ_RX_RSS) {
475 if (hw->cap & NFP_NET_CFG_CTRL_RSS) {
476 update = NFP_NET_CFG_UPDATE_RSS;
477 new_ctrl = NFP_NET_CFG_CTRL_RSS;
479 PMD_INIT_LOG(INFO, "RSS not supported\n");
484 if (rxmode->split_hdr_size) {
485 PMD_INIT_LOG(INFO, "rxmode does not support split header\n");
489 if (rxmode->hw_ip_checksum) {
490 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {
491 new_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;
493 PMD_INIT_LOG(INFO, "RXCSUM not supported\n");
498 if (rxmode->hw_vlan_filter) {
499 PMD_INIT_LOG(INFO, "VLAN filter not supported\n");
503 if (rxmode->hw_vlan_strip) {
504 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {
505 new_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;
507 PMD_INIT_LOG(INFO, "hw vlan strip not supported\n");
512 if (rxmode->hw_vlan_extend) {
513 PMD_INIT_LOG(INFO, "VLAN extended not supported\n");
517 /* Supporting VLAN insertion by default */
518 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
519 new_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;
521 if (rxmode->jumbo_frame)
522 /* this is handled in rte_eth_dev_configure */
524 if (rxmode->hw_strip_crc) {
525 PMD_INIT_LOG(INFO, "strip CRC not supported\n");
529 if (rxmode->enable_scatter) {
530 PMD_INIT_LOG(INFO, "Scatter not supported\n");
537 update |= NFP_NET_CFG_UPDATE_GEN;
539 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
540 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
549 nfp_net_enable_queues(struct rte_eth_dev *dev)
551 struct nfp_net_hw *hw;
552 uint64_t enabled_queues = 0;
555 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
557 /* Enabling the required TX queues in the device */
558 for (i = 0; i < dev->data->nb_tx_queues; i++)
559 enabled_queues |= (1 << i);
561 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);
565 /* Enabling the required RX queues in the device */
566 for (i = 0; i < dev->data->nb_rx_queues; i++)
567 enabled_queues |= (1 << i);
569 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);
573 nfp_net_disable_queues(struct rte_eth_dev *dev)
575 struct nfp_net_hw *hw;
576 uint32_t new_ctrl, update = 0;
578 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
580 nn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);
581 nn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);
583 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;
584 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |
585 NFP_NET_CFG_UPDATE_MSIX;
587 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
588 new_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;
590 /* If an error when reconfig we avoid to change hw state */
591 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
598 nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)
602 for (i = 0; i < dev->data->nb_rx_queues; i++) {
603 if (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)
610 nfp_net_params_setup(struct nfp_net_hw *hw)
612 uint32_t *mac_address;
614 nn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);
615 nn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);
617 /* A MAC address is 8 bytes long */
618 mac_address = (uint32_t *)(hw->mac_addr);
620 nn_cfg_writel(hw, NFP_NET_CFG_MACADDR,
621 rte_cpu_to_be_32(*mac_address));
622 nn_cfg_writel(hw, NFP_NET_CFG_MACADDR + 4,
623 rte_cpu_to_be_32(*(mac_address + 4)));
627 nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)
629 hw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;
633 nfp_net_start(struct rte_eth_dev *dev)
635 uint32_t new_ctrl, update = 0;
636 struct nfp_net_hw *hw;
639 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
641 PMD_INIT_LOG(DEBUG, "Start\n");
643 /* Disabling queues just in case... */
644 nfp_net_disable_queues(dev);
646 /* Writing configuration parameters in the device */
647 nfp_net_params_setup(hw);
649 /* Enabling the required queues in the device */
650 nfp_net_enable_queues(dev);
653 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE | NFP_NET_CFG_UPDATE_MSIX;
654 update = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;
656 if (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)
657 new_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;
659 nn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);
660 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
664 * Allocating rte mbuffs for configured rx queues.
665 * This requires queues being enabled before
667 if (nfp_net_rx_freelist_setup(dev) < 0) {
678 * An error returned by this function should mean the app
679 * exiting and then the system releasing all the memory
680 * allocated even memory coming from hugepages.
682 * The device could be enabled at this point with some queues
683 * ready for getting packets. This is true if the call to
684 * nfp_net_rx_freelist_setup() succeeds for some queues but
685 * fails for subsequent queues.
687 * This should make the app exiting but better if we tell the
690 nfp_net_disable_queues(dev);
695 /* Stop device: disable rx and tx functions to allow for reconfiguring. */
697 nfp_net_stop(struct rte_eth_dev *dev)
701 PMD_INIT_LOG(DEBUG, "Stop\n");
703 nfp_net_disable_queues(dev);
706 for (i = 0; i < dev->data->nb_tx_queues; i++) {
707 nfp_net_reset_tx_queue(
708 (struct nfp_net_txq *)dev->data->tx_queues[i]);
711 for (i = 0; i < dev->data->nb_rx_queues; i++) {
712 nfp_net_reset_rx_queue(
713 (struct nfp_net_rxq *)dev->data->rx_queues[i]);
717 /* Reset and stop device. The device can not be restarted. */
719 nfp_net_close(struct rte_eth_dev *dev)
721 struct nfp_net_hw *hw;
723 PMD_INIT_LOG(DEBUG, "Close\n");
725 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
728 * We assume that the DPDK application is stopping all the
729 * threads/queues before calling the device close function.
734 nn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);
737 * The ixgbe PMD driver disables the pcie master on the
738 * device. The i40e does not...
743 nfp_net_promisc_enable(struct rte_eth_dev *dev)
745 uint32_t new_ctrl, update = 0;
746 struct nfp_net_hw *hw;
748 PMD_DRV_LOG(DEBUG, "Promiscuous mode enable\n");
750 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
752 if (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {
753 PMD_INIT_LOG(INFO, "Promiscuous mode not supported\n");
757 if (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {
758 PMD_DRV_LOG(INFO, "Promiscuous mode already enabled\n");
762 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;
763 update = NFP_NET_CFG_UPDATE_GEN;
766 * DPDK sets promiscuous mode on just after this call assuming
767 * it can not fail ...
769 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
776 nfp_net_promisc_disable(struct rte_eth_dev *dev)
778 uint32_t new_ctrl, update = 0;
779 struct nfp_net_hw *hw;
781 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
783 if ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {
784 PMD_DRV_LOG(INFO, "Promiscuous mode already disabled\n");
788 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;
789 update = NFP_NET_CFG_UPDATE_GEN;
792 * DPDK sets promiscuous mode off just before this call
793 * assuming it can not fail ...
795 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
802 * return 0 means link status changed, -1 means not changed
804 * Wait to complete is needed as it can take up to 9 seconds to get the Link
808 nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)
810 struct nfp_net_hw *hw;
811 struct rte_eth_link link, old;
812 uint32_t nn_link_status;
814 PMD_DRV_LOG(DEBUG, "Link update\n");
816 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
818 memset(&old, 0, sizeof(old));
819 nfp_net_dev_atomic_read_link_status(dev, &old);
821 nn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);
823 memset(&link, 0, sizeof(struct rte_eth_link));
825 if (nn_link_status & NFP_NET_CFG_STS_LINK)
826 link.link_status = 1;
828 link.link_duplex = ETH_LINK_FULL_DUPLEX;
829 /* Other cards can limit the tx and rx rate per VF */
830 link.link_speed = ETH_LINK_SPEED_40G;
832 if (old.link_status != link.link_status) {
833 nfp_net_dev_atomic_write_link_status(dev, &link);
834 if (link.link_status)
835 PMD_DRV_LOG(INFO, "NIC Link is Up\n");
837 PMD_DRV_LOG(INFO, "NIC Link is Down\n");
845 nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
848 struct nfp_net_hw *hw;
849 struct rte_eth_stats nfp_dev_stats;
851 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
853 /* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */
855 /* reading per RX ring stats */
856 for (i = 0; i < dev->data->nb_rx_queues; i++) {
857 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
860 nfp_dev_stats.q_ipackets[i] =
861 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
863 nfp_dev_stats.q_ipackets[i] -=
864 hw->eth_stats_base.q_ipackets[i];
866 nfp_dev_stats.q_ibytes[i] =
867 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
869 nfp_dev_stats.q_ibytes[i] -=
870 hw->eth_stats_base.q_ibytes[i];
873 /* reading per TX ring stats */
874 for (i = 0; i < dev->data->nb_tx_queues; i++) {
875 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
878 nfp_dev_stats.q_opackets[i] =
879 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
881 nfp_dev_stats.q_opackets[i] -=
882 hw->eth_stats_base.q_opackets[i];
884 nfp_dev_stats.q_obytes[i] =
885 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
887 nfp_dev_stats.q_obytes[i] -=
888 hw->eth_stats_base.q_obytes[i];
891 nfp_dev_stats.ipackets =
892 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
894 nfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;
896 nfp_dev_stats.ibytes =
897 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
899 nfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;
901 nfp_dev_stats.opackets =
902 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
904 nfp_dev_stats.opackets -= hw->eth_stats_base.opackets;
906 nfp_dev_stats.obytes =
907 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
909 nfp_dev_stats.obytes -= hw->eth_stats_base.obytes;
911 nfp_dev_stats.imcasts =
912 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
914 nfp_dev_stats.imcasts -= hw->eth_stats_base.imcasts;
916 /* reading general device stats */
917 nfp_dev_stats.ierrors =
918 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
920 nfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;
922 nfp_dev_stats.oerrors =
923 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
925 nfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;
927 /* Multicast frames received */
928 nfp_dev_stats.imcasts =
929 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
931 nfp_dev_stats.imcasts -= hw->eth_stats_base.imcasts;
933 /* RX ring mbuf allocation failures */
934 nfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;
936 nfp_dev_stats.imissed =
937 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
939 nfp_dev_stats.imissed -= hw->eth_stats_base.imissed;
942 memcpy(stats, &nfp_dev_stats, sizeof(*stats));
946 nfp_net_stats_reset(struct rte_eth_dev *dev)
949 struct nfp_net_hw *hw;
951 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
954 * hw->eth_stats_base records the per counter starting point.
958 /* reading per RX ring stats */
959 for (i = 0; i < dev->data->nb_rx_queues; i++) {
960 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
963 hw->eth_stats_base.q_ipackets[i] =
964 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));
966 hw->eth_stats_base.q_ibytes[i] =
967 nn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);
970 /* reading per TX ring stats */
971 for (i = 0; i < dev->data->nb_tx_queues; i++) {
972 if (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)
975 hw->eth_stats_base.q_opackets[i] =
976 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));
978 hw->eth_stats_base.q_obytes[i] =
979 nn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);
982 hw->eth_stats_base.ipackets =
983 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);
985 hw->eth_stats_base.ibytes =
986 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);
988 hw->eth_stats_base.opackets =
989 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);
991 hw->eth_stats_base.obytes =
992 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);
994 hw->eth_stats_base.imcasts =
995 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
997 /* reading general device stats */
998 hw->eth_stats_base.ierrors =
999 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);
1001 hw->eth_stats_base.oerrors =
1002 nn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);
1004 /* Multicast frames received */
1005 hw->eth_stats_base.imcasts =
1006 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);
1008 /* RX ring mbuf allocation failures */
1009 dev->data->rx_mbuf_alloc_failed = 0;
1011 hw->eth_stats_base.imissed =
1012 nn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);
1016 nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1018 struct nfp_net_hw *hw;
1020 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022 dev_info->driver_name = dev->driver->pci_drv.name;
1023 dev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;
1024 dev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;
1025 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1026 dev_info->max_rx_pktlen = hw->mtu;
1027 /* Next should change when PF support is implemented */
1028 dev_info->max_mac_addrs = 1;
1030 if (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)
1031 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1033 if (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)
1034 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1035 DEV_RX_OFFLOAD_UDP_CKSUM |
1036 DEV_RX_OFFLOAD_TCP_CKSUM;
1038 if (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)
1039 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;
1041 if (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)
1042 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1043 DEV_RX_OFFLOAD_UDP_CKSUM |
1044 DEV_RX_OFFLOAD_TCP_CKSUM;
1046 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1048 .pthresh = DEFAULT_RX_PTHRESH,
1049 .hthresh = DEFAULT_RX_HTHRESH,
1050 .wthresh = DEFAULT_RX_WTHRESH,
1052 .rx_free_thresh = DEFAULT_RX_FREE_THRESH,
1056 dev_info->default_txconf = (struct rte_eth_txconf) {
1058 .pthresh = DEFAULT_TX_PTHRESH,
1059 .hthresh = DEFAULT_TX_HTHRESH,
1060 .wthresh = DEFAULT_TX_WTHRESH,
1062 .tx_free_thresh = DEFAULT_TX_FREE_THRESH,
1063 .tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,
1064 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1065 ETH_TXQ_FLAGS_NOOFFLOADS,
1068 dev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;
1069 #if RTE_VER_MAJOR == 2 && RTE_VER_MINOR >= 1
1070 dev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;
1075 nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
1077 struct nfp_net_rxq *rxq;
1078 struct nfp_net_rx_desc *rxds;
1082 rxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];
1085 PMD_INIT_LOG(ERR, "Bad queue: %u\n", queue_idx);
1089 idx = rxq->rd_p % rxq->rx_count;
1090 rxds = &rxq->rxds[idx];
1095 * Other PMDs are just checking the DD bit in intervals of 4
1096 * descriptors and counting all four if the first has the DD
1097 * bit on. Of course, this is not accurate but can be good for
1098 * perfomance. But ideally that should be done in descriptors
1099 * chunks belonging to the same cache line
1102 while (count < rxq->rx_count) {
1103 rxds = &rxq->rxds[idx];
1104 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1111 if ((idx) == rxq->rx_count)
1119 nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1121 struct nfp_net_hw *hw;
1123 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1125 /* check that mtu is within the allowed range */
1126 if ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))
1129 /* switch to jumbo mode if needed */
1130 if ((uint32_t)mtu > ETHER_MAX_LEN)
1131 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1133 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1135 /* update max frame size */
1136 dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;
1138 /* writing to configuration space */
1139 nn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);
1147 nfp_net_rx_queue_setup(struct rte_eth_dev *dev,
1148 uint16_t queue_idx, uint16_t nb_desc,
1149 unsigned int socket_id,
1150 const struct rte_eth_rxconf *rx_conf,
1151 struct rte_mempool *mp)
1153 const struct rte_memzone *tz;
1154 struct nfp_net_rxq *rxq;
1155 struct nfp_net_hw *hw;
1157 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1159 PMD_INIT_FUNC_TRACE();
1161 /* Validating number of descriptors */
1162 if (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||
1163 (nb_desc > NFP_NET_MAX_RX_DESC) ||
1164 (nb_desc < NFP_NET_MIN_RX_DESC)) {
1165 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1170 * Free memory prior to re-allocation if needed. This is the case after
1171 * calling nfp_net_stop
1173 if (dev->data->rx_queues[queue_idx]) {
1174 nfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);
1175 dev->data->rx_queues[queue_idx] = NULL;
1178 /* Allocating rx queue data structure */
1179 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct nfp_net_rxq),
1180 RTE_CACHE_LINE_SIZE, socket_id);
1184 /* Hw queues mapping based on firmware confifguration */
1185 rxq->qidx = queue_idx;
1186 rxq->fl_qcidx = queue_idx * hw->stride_rx;
1187 rxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);
1188 rxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);
1189 rxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);
1192 * Tracking mbuf size for detecting a potential mbuf overflow due to
1196 rxq->mbuf_size = rxq->mem_pool->elt_size;
1197 rxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);
1198 hw->flbufsz = rxq->mbuf_size;
1200 rxq->rx_count = nb_desc;
1201 rxq->port_id = dev->data->port_id;
1202 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1203 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0
1205 rxq->drop_en = rx_conf->rx_drop_en;
1208 * Allocate RX ring hardware descriptors. A memzone large enough to
1209 * handle the maximum ring size is allocated in order to allow for
1210 * resizing in later calls to the queue setup function.
1212 tz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1213 sizeof(struct nfp_net_rx_desc) *
1214 NFP_NET_MAX_RX_DESC, socket_id);
1217 RTE_LOG(ERR, PMD, "Error allocatig rx dma\n");
1218 nfp_net_rx_queue_release(rxq);
1222 /* Saving physical and virtual addresses for the RX ring */
1223 rxq->dma = (uint64_t)tz->phys_addr;
1224 rxq->rxds = (struct nfp_net_rx_desc *)tz->addr;
1226 /* mbuf pointers array for referencing mbufs linked to RX descriptors */
1227 rxq->rxbufs = rte_zmalloc_socket("rxq->rxbufs",
1228 sizeof(*rxq->rxbufs) * nb_desc,
1229 RTE_CACHE_LINE_SIZE, socket_id);
1230 if (rxq->rxbufs == NULL) {
1231 nfp_net_rx_queue_release(rxq);
1235 PMD_RX_LOG(DEBUG, "rxbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1236 rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);
1238 nfp_net_reset_rx_queue(rxq);
1240 dev->data->rx_queues[queue_idx] = rxq;
1244 * Telling the HW about the physical address of the RX ring and number
1245 * of descriptors in log2 format
1247 nn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);
1248 nn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));
1254 nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)
1256 struct nfp_net_rx_buff *rxe = rxq->rxbufs;
1260 PMD_RX_LOG(DEBUG, "nfp_net_rx_fill_freelist for %u descriptors\n",
1263 for (i = 0; i < rxq->rx_count; i++) {
1264 struct nfp_net_rx_desc *rxd;
1265 struct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);
1268 RTE_LOG(ERR, PMD, "RX mbuf alloc failed queue_id=%u\n",
1269 (unsigned)rxq->qidx);
1273 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));
1275 rxd = &rxq->rxds[i];
1277 rxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1278 rxd->fld.dma_addr_lo = dma_addr & 0xffffffff;
1280 PMD_RX_LOG(DEBUG, "[%d]: %" PRIx64 "\n", i, dma_addr);
1285 /* Make sure all writes are flushed before telling the hardware */
1288 /* Not advertising the whole ring as the firmware gets confused if so */
1289 PMD_RX_LOG(DEBUG, "Increment FL write pointer in %u\n",
1292 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);
1298 nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1299 uint16_t nb_desc, unsigned int socket_id,
1300 const struct rte_eth_txconf *tx_conf)
1302 const struct rte_memzone *tz;
1303 struct nfp_net_txq *txq;
1304 uint16_t tx_free_thresh;
1305 struct nfp_net_hw *hw;
1307 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1309 PMD_INIT_FUNC_TRACE();
1311 /* Validating number of descriptors */
1312 if (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||
1313 (nb_desc > NFP_NET_MAX_TX_DESC) ||
1314 (nb_desc < NFP_NET_MIN_TX_DESC)) {
1315 RTE_LOG(ERR, PMD, "Wrong nb_desc value\n");
1319 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1320 tx_conf->tx_free_thresh :
1321 DEFAULT_TX_FREE_THRESH);
1323 if (tx_free_thresh > (nb_desc)) {
1325 "tx_free_thresh must be less than the number of TX "
1326 "descriptors. (tx_free_thresh=%u port=%d "
1327 "queue=%d)\n", (unsigned int)tx_free_thresh,
1328 (int)dev->data->port_id, (int)queue_idx);
1333 * Free memory prior to re-allocation if needed. This is the case after
1334 * calling nfp_net_stop
1336 if (dev->data->tx_queues[queue_idx]) {
1337 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d\n",
1339 nfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);
1340 dev->data->tx_queues[queue_idx] = NULL;
1343 /* Allocating tx queue data structure */
1344 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nfp_net_txq),
1345 RTE_CACHE_LINE_SIZE, socket_id);
1347 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1352 * Allocate TX ring hardware descriptors. A memzone large enough to
1353 * handle the maximum ring size is allocated in order to allow for
1354 * resizing in later calls to the queue setup function.
1356 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1357 sizeof(struct nfp_net_tx_desc) *
1358 NFP_NET_MAX_TX_DESC, socket_id);
1360 RTE_LOG(ERR, PMD, "Error allocating tx dma\n");
1361 nfp_net_tx_queue_release(txq);
1365 txq->tx_count = nb_desc;
1367 txq->tx_free_thresh = tx_free_thresh;
1368 txq->tx_pthresh = tx_conf->tx_thresh.pthresh;
1369 txq->tx_hthresh = tx_conf->tx_thresh.hthresh;
1370 txq->tx_wthresh = tx_conf->tx_thresh.wthresh;
1372 /* queue mapping based on firmware configuration */
1373 txq->qidx = queue_idx;
1374 txq->tx_qcidx = queue_idx * hw->stride_tx;
1375 txq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);
1377 txq->port_id = dev->data->port_id;
1378 txq->txq_flags = tx_conf->txq_flags;
1380 /* Saving physical and virtual addresses for the TX ring */
1381 txq->dma = (uint64_t)tz->phys_addr;
1382 txq->txds = (struct nfp_net_tx_desc *)tz->addr;
1384 /* mbuf pointers array for referencing mbufs linked to TX descriptors */
1385 txq->txbufs = rte_zmalloc_socket("txq->txbufs",
1386 sizeof(*txq->txbufs) * nb_desc,
1387 RTE_CACHE_LINE_SIZE, socket_id);
1388 if (txq->txbufs == NULL) {
1389 nfp_net_tx_queue_release(txq);
1392 PMD_TX_LOG(DEBUG, "txbufs=%p hw_ring=%p dma_addr=0x%" PRIx64 "\n",
1393 txq->txbufs, txq->txds, (unsigned long int)txq->dma);
1395 nfp_net_reset_tx_queue(txq);
1397 dev->data->tx_queues[queue_idx] = txq;
1401 * Telling the HW about the physical address of the TX ring and number
1402 * of descriptors in log2 format
1404 nn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);
1405 nn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));
1410 /* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */
1412 nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,
1413 struct rte_mbuf *mb)
1416 struct nfp_net_hw *hw = txq->hw;
1418 if (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))
1421 ol_flags = mb->ol_flags;
1423 /* IPv6 does not need checksum */
1424 if (ol_flags & PKT_TX_IP_CKSUM)
1425 txd->flags |= PCIE_DESC_TX_IP4_CSUM;
1427 switch (ol_flags & PKT_TX_L4_MASK) {
1428 case PKT_TX_UDP_CKSUM:
1429 txd->flags |= PCIE_DESC_TX_UDP_CSUM;
1431 case PKT_TX_TCP_CKSUM:
1432 txd->flags |= PCIE_DESC_TX_TCP_CSUM;
1436 txd->flags |= PCIE_DESC_TX_CSUM;
1439 /* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */
1441 nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1442 struct rte_mbuf *mb)
1444 struct nfp_net_hw *hw = rxq->hw;
1446 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))
1449 /* If IPv4 and IP checksum error, fail */
1450 if ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&
1451 !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))
1452 mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1454 /* If neither UDP nor TCP return */
1455 if (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1456 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))
1459 if ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&
1460 !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))
1461 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1463 if ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&
1464 !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))
1465 mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1468 #define NFP_HASH_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)
1469 #define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)
1472 * nfp_net_set_hash - Set mbuf hash data
1474 * The RSS hash and hash-type are pre-pended to the packet data.
1475 * Extract and decode it and set the mbuf fields.
1478 nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,
1479 struct rte_mbuf *mbuf)
1483 struct nfp_net_hw *hw = rxq->hw;
1485 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1488 if (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))
1491 hash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);
1492 hash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);
1495 * hash type is sharing the same word with input port info
1500 mbuf->hash.rss = hash;
1501 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1503 switch (hash_type) {
1504 case NFP_NET_RSS_IPV4:
1505 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;
1507 case NFP_NET_RSS_IPV6:
1508 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;
1510 case NFP_NET_RSS_IPV6_EX:
1511 mbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;
1514 mbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;
1518 /* nfp_net_check_port - Set mbuf in_port field */
1520 nfp_net_check_port(struct nfp_net_rx_desc *rxd, struct rte_mbuf *mbuf)
1524 if (!(rxd->rxd.flags & PCIE_DESC_RX_INGRESS_PORT)) {
1529 port = rte_be_to_cpu_32(*(uint32_t *)((uint8_t *)mbuf->buf_addr +
1530 mbuf->data_off - 8));
1533 * hash type is sharing the same word with input port info
1537 port = (uint8_t)(port >> 8);
1542 nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)
1544 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1547 #define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)
1552 * There are some decissions to take:
1553 * 1) How to check DD RX descriptors bit
1554 * 2) How and when to allocate new mbufs
1556 * Current implementation checks just one single DD bit each loop. As each
1557 * descriptor is 8 bytes, it is likely a good idea to check descriptors in
1558 * a single cache line instead. Tests with this change have not shown any
1559 * performance improvement but it requires further investigation. For example,
1560 * depending on which descriptor is next, the number of descriptors could be
1561 * less than 8 for just checking those in the same cache line. This implies
1562 * extra work which could be counterproductive by itself. Indeed, last firmware
1563 * changes are just doing this: writing several descriptors with the DD bit
1564 * for saving PCIe bandwidth and DMA operations from the NFP.
1566 * Mbuf allocation is done when a new packet is received. Then the descriptor
1567 * is automatically linked with the new mbuf and the old one is given to the
1568 * user. The main drawback with this design is mbuf allocation is heavier than
1569 * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the
1570 * cache point of view it does not seem allocating the mbuf early on as we are
1571 * doing now have any benefit at all. Again, tests with this change have not
1572 * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing
1573 * so looking at the implications of this type of allocation should be studied
1578 nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1580 struct nfp_net_rxq *rxq;
1581 struct nfp_net_rx_desc *rxds;
1582 struct nfp_net_rx_buff *rxb;
1583 struct nfp_net_hw *hw;
1584 struct rte_mbuf *mb;
1585 struct rte_mbuf *new_mb;
1592 if (unlikely(rxq == NULL)) {
1594 * DPDK just checks the queue is lower than max queues
1595 * enabled. But the queue needs to be configured
1597 RTE_LOG(ERR, PMD, "RX Bad queue\n");
1605 while (avail < nb_pkts) {
1606 idx = rxq->rd_p % rxq->rx_count;
1608 rxb = &rxq->rxbufs[idx];
1609 if (unlikely(rxb == NULL)) {
1610 RTE_LOG(ERR, PMD, "rxb does not exist!\n");
1615 * Memory barrier to ensure that we won't do other
1616 * reads before the DD bit.
1620 rxds = &rxq->rxds[idx];
1621 if ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)
1625 * We got a packet. Let's alloc a new mbuff for refilling the
1626 * free descriptor ring as soon as possible
1628 new_mb = rte_pktmbuf_alloc(rxq->mem_pool);
1629 if (unlikely(new_mb == NULL)) {
1630 RTE_LOG(DEBUG, PMD, "RX mbuf alloc failed port_id=%u "
1631 "queue_id=%u\n", (unsigned)rxq->port_id,
1632 (unsigned)rxq->qidx);
1633 nfp_net_mbuf_alloc_failed(rxq);
1640 * Grab the mbuff and refill the descriptor with the
1641 * previously allocated mbuff
1646 PMD_RX_LOG(DEBUG, "Packet len: %u, mbuf_size: %u\n",
1647 rxds->rxd.data_len, rxq->mbuf_size);
1649 /* Size of this segment */
1650 mb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1651 /* Size of the whole packet. We just support 1 segment */
1652 mb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);
1654 if (unlikely((mb->data_len + hw->rx_offset) >
1657 * This should not happen and the user has the
1658 * responsibility of avoiding it. But we have
1659 * to give some info about the error
1662 "mbuf overflow likely due to the RX offset.\n"
1663 "\t\tYour mbuf size should have extra space for"
1664 " RX offset=%u bytes.\n"
1665 "\t\tCurrently you just have %u bytes available"
1666 " but the received packet is %u bytes long",
1668 rxq->mbuf_size - hw->rx_offset,
1673 /* Filling the received mbuff with packet info */
1675 mb->data_off = RTE_PKTMBUF_HEADROOM + hw->rx_offset;
1677 mb->data_off = RTE_PKTMBUF_HEADROOM +
1678 NFP_DESC_META_LEN(rxds);
1680 /* No scatter mode supported */
1684 /* Checking the RSS flag */
1685 nfp_net_set_hash(rxq, rxds, mb);
1687 /* Checking the checksum flag */
1688 nfp_net_rx_cksum(rxq, rxds, mb);
1690 /* Checking the port flag */
1691 nfp_net_check_port(rxds, mb);
1693 if ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&
1694 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {
1695 mb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);
1696 mb->ol_flags |= PKT_RX_VLAN_PKT;
1699 /* Adding the mbuff to the mbuff array passed by the app */
1700 rx_pkts[avail++] = mb;
1702 /* Now resetting and updating the descriptor */
1705 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));
1707 rxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;
1708 rxds->fld.dma_addr_lo = dma_addr & 0xffffffff;
1716 PMD_RX_LOG(DEBUG, "RX port_id=%u queue_id=%u, %d packets received\n",
1717 (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);
1719 nb_hold += rxq->nb_rx_hold;
1722 * FL descriptors needs to be written before incrementing the
1723 * FL queue WR pointer
1726 if (nb_hold > rxq->rx_free_thresh) {
1727 PMD_RX_LOG(DEBUG, "port=%u queue=%u nb_hold=%u avail=%u\n",
1728 (unsigned)rxq->port_id, (unsigned)rxq->qidx,
1729 (unsigned)nb_hold, (unsigned)avail);
1730 nfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);
1733 rxq->nb_rx_hold = nb_hold;
1739 * nfp_net_tx_free_bufs - Check for descriptors with a complete
1741 * @txq: TX queue to work with
1742 * Returns number of descriptors freed
1745 nfp_net_tx_free_bufs(struct nfp_net_txq *txq)
1750 PMD_TX_LOG(DEBUG, "queue %u. Check for descriptor with a complete"
1751 " status\n", txq->qidx);
1753 /* Work out how many packets have been sent */
1754 qcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);
1756 if (qcp_rd_p == txq->qcp_rd_p) {
1757 PMD_TX_LOG(DEBUG, "queue %u: It seems harrier is not sending "
1758 "packets (%u, %u)\n", txq->qidx,
1759 qcp_rd_p, txq->qcp_rd_p);
1763 if (qcp_rd_p > txq->qcp_rd_p)
1764 todo = qcp_rd_p - txq->qcp_rd_p;
1766 todo = qcp_rd_p + txq->tx_count - txq->qcp_rd_p;
1768 PMD_TX_LOG(DEBUG, "qcp_rd_p %u, txq->qcp_rd_p: %u, qcp->rd_p: %u\n",
1769 qcp_rd_p, txq->qcp_rd_p, txq->rd_p);
1774 txq->qcp_rd_p += todo;
1775 txq->qcp_rd_p %= txq->tx_count;
1781 /* Leaving always free descriptors for avoiding wrapping confusion */
1782 #define NFP_FREE_TX_DESC(t) (t->tx_count - (t->wr_p - t->rd_p) - 8)
1785 * nfp_net_txq_full - Check if the TX queue free descriptors
1786 * is below tx_free_threshold
1788 * @txq: TX queue to check
1790 * This function uses the host copy* of read/write pointers
1793 int nfp_net_txq_full(struct nfp_net_txq *txq)
1795 return NFP_FREE_TX_DESC(txq) < txq->tx_free_thresh;
1799 nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1801 struct nfp_net_txq *txq;
1802 struct nfp_net_hw *hw;
1803 struct nfp_net_tx_desc *txds;
1804 struct rte_mbuf *pkt;
1806 int pkt_size, dma_size;
1807 uint16_t free_descs, issued_descs;
1808 struct rte_mbuf **lmbuf;
1813 txds = &txq->txds[txq->tail];
1815 PMD_TX_LOG(DEBUG, "working for queue %u at pos %d and %u packets\n",
1816 txq->qidx, txq->tail, nb_pkts);
1818 if ((NFP_FREE_TX_DESC(txq) < nb_pkts) || (nfp_net_txq_full(txq)))
1819 nfp_net_tx_free_bufs(txq);
1821 free_descs = (uint16_t)NFP_FREE_TX_DESC(txq);
1822 if (unlikely(free_descs == 0))
1829 PMD_TX_LOG(DEBUG, "queue: %u. Sending %u packets\n",
1830 txq->qidx, nb_pkts);
1831 /* Sending packets */
1832 while ((i < nb_pkts) && free_descs) {
1833 /* Grabbing the mbuf linked to the current descriptor */
1834 lmbuf = &txq->txbufs[txq->tail].mbuf;
1835 /* Warming the cache for releasing the mbuf later on */
1836 RTE_MBUF_PREFETCH_TO_FREE(*lmbuf);
1838 pkt = *(tx_pkts + i);
1840 if (unlikely((pkt->nb_segs > 1) &&
1841 !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {
1842 PMD_INIT_LOG(INFO, "NFP_NET_CFG_CTRL_GATHER not set\n");
1843 rte_panic("Multisegment packet unsupported\n");
1846 /* Checking if we have enough descriptors */
1847 if (unlikely(pkt->nb_segs > free_descs))
1851 * Checksum and VLAN flags just in the first descriptor for a
1852 * multisegment packet
1854 nfp_net_tx_cksum(txq, txds, pkt);
1856 if ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&
1857 (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {
1858 txds->flags |= PCIE_DESC_TX_VLAN;
1859 txds->vlan = pkt->vlan_tci;
1862 if (pkt->ol_flags & PKT_TX_TCP_SEG)
1863 rte_panic("TSO is not supported\n");
1866 * mbuf data_len is the data in one segment and pkt_len data
1867 * in the whole packet. When the packet is just one segment,
1868 * then data_len = pkt_len
1870 pkt_size = pkt->pkt_len;
1873 /* Releasing mbuf which was prefetched above */
1875 rte_pktmbuf_free_seg(*lmbuf);
1877 dma_size = pkt->data_len;
1878 dma_addr = RTE_MBUF_DATA_DMA_ADDR(pkt);
1879 PMD_TX_LOG(DEBUG, "Working with mbuf at dma address:"
1880 "%" PRIx64 "\n", dma_addr);
1882 /* Filling descriptors fields */
1883 txds->dma_len = dma_size;
1884 txds->data_len = pkt->pkt_len;
1885 txds->dma_addr_hi = (dma_addr >> 32) & 0xff;
1886 txds->dma_addr_lo = (dma_addr & 0xffffffff);
1887 ASSERT(free_descs > 0);
1891 * Linking mbuf with descriptor for being released
1892 * next time descriptor is used
1898 if (unlikely(txq->tail == txq->tx_count)) /* wrapping?*/
1901 pkt_size -= dma_size;
1904 txds->offset_eop |= PCIE_DESC_TX_EOP;
1906 txds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;
1909 /* Referencing next free TX descriptor */
1910 txds = &txq->txds[txq->tail];
1917 /* Increment write pointers. Force memory write before we let HW know */
1919 nfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);
1925 nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1927 uint32_t new_ctrl, update;
1928 struct nfp_net_hw *hw;
1930 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933 if ((mask & ETH_VLAN_FILTER_OFFLOAD) ||
1934 (mask & ETH_VLAN_FILTER_OFFLOAD))
1935 RTE_LOG(INFO, PMD, "Not support for ETH_VLAN_FILTER_OFFLOAD or"
1936 " ETH_VLAN_FILTER_EXTEND");
1938 /* Enable vlan strip if it is not configured yet */
1939 if ((mask & ETH_VLAN_STRIP_OFFLOAD) &&
1940 !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
1941 new_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;
1943 /* Disable vlan strip just if it is configured */
1944 if (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&
1945 (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))
1946 new_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;
1951 update = NFP_NET_CFG_UPDATE_GEN;
1953 if (nfp_net_reconfig(hw, new_ctrl, update) < 0)
1956 hw->ctrl = new_ctrl;
1959 /* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */
1961 nfp_net_reta_update(struct rte_eth_dev *dev,
1962 struct rte_eth_rss_reta_entry64 *reta_conf,
1965 uint32_t reta, mask;
1969 struct nfp_net_hw *hw =
1970 NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
1975 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
1976 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
1977 "(%d) doesn't match the number hardware can supported "
1978 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
1983 * Update Redirection Table. There are 128 8bit-entries which can be
1984 * manage as 32 32bit-entries
1986 for (i = 0; i < reta_size; i += 4) {
1987 /* Handling 4 RSS entries per loop */
1988 idx = i / RTE_RETA_GROUP_SIZE;
1989 shift = i % RTE_RETA_GROUP_SIZE;
1990 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
1996 /* If all 4 entries were set, don't need read RETA register */
1998 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);
2000 for (j = 0; j < 4; j++) {
2001 if (!(mask & (0x1 << j)))
2004 /* Clearing the entry bits */
2005 reta &= ~(0xFF << (8 * j));
2006 reta |= reta_conf[idx].reta[shift + j] << (8 * j);
2008 nn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);
2011 update = NFP_NET_CFG_UPDATE_RSS;
2013 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2019 /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */
2021 nfp_net_reta_query(struct rte_eth_dev *dev,
2022 struct rte_eth_rss_reta_entry64 *reta_conf,
2028 struct nfp_net_hw *hw;
2030 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2032 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2035 if (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {
2036 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
2037 "(%d) doesn't match the number hardware can supported "
2038 "(%d)\n", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);
2043 * Reading Redirection Table. There are 128 8bit-entries which can be
2044 * manage as 32 32bit-entries
2046 for (i = 0; i < reta_size; i += 4) {
2047 /* Handling 4 RSS entries per loop */
2048 idx = i / RTE_RETA_GROUP_SIZE;
2049 shift = i % RTE_RETA_GROUP_SIZE;
2050 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);
2055 reta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);
2056 for (j = 0; j < 4; j++) {
2057 if (!(mask & (0x1 << j)))
2059 reta_conf->reta[shift + j] =
2060 (uint8_t)((reta >> (8 * j)) & 0xF);
2067 nfp_net_rss_hash_update(struct rte_eth_dev *dev,
2068 struct rte_eth_rss_conf *rss_conf)
2071 uint32_t cfg_rss_ctrl = 0;
2075 struct nfp_net_hw *hw;
2077 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079 rss_hf = rss_conf->rss_hf;
2081 /* Checking if RSS is enabled */
2082 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {
2083 if (rss_hf != 0) { /* Enable RSS? */
2084 RTE_LOG(ERR, PMD, "RSS unsupported\n");
2087 return 0; /* Nothing to do */
2090 if (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {
2091 RTE_LOG(ERR, PMD, "hash key too long\n");
2095 if (rss_hf & ETH_RSS_IPV4)
2096 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |
2097 NFP_NET_CFG_RSS_IPV4_TCP |
2098 NFP_NET_CFG_RSS_IPV4_UDP;
2100 if (rss_hf & ETH_RSS_IPV6)
2101 cfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |
2102 NFP_NET_CFG_RSS_IPV6_TCP |
2103 NFP_NET_CFG_RSS_IPV6_UDP;
2105 /* configuring where to apply the RSS hash */
2106 nn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);
2108 /* Writing the key byte a byte */
2109 for (i = 0; i < rss_conf->rss_key_len; i++) {
2110 memcpy(&key, &rss_conf->rss_key[i], 1);
2111 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);
2114 /* Writing the key size */
2115 nn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);
2117 update = NFP_NET_CFG_UPDATE_RSS;
2119 if (nfp_net_reconfig(hw, hw->ctrl, update) < 0)
2126 nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,
2127 struct rte_eth_rss_conf *rss_conf)
2130 uint32_t cfg_rss_ctrl;
2133 struct nfp_net_hw *hw;
2135 hw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2137 if (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))
2140 rss_hf = rss_conf->rss_hf;
2141 cfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);
2143 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)
2144 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;
2146 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)
2147 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2149 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)
2150 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2152 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)
2153 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2155 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)
2156 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2158 if (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)
2159 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;
2161 /* Reading the key size */
2162 rss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);
2164 /* Reading the key byte a byte */
2165 for (i = 0; i < rss_conf->rss_key_len; i++) {
2166 key = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);
2167 memcpy(&rss_conf->rss_key[i], &key, 1);
2173 /* Initialise and register driver with DPDK Application */
2174 static struct eth_dev_ops nfp_net_eth_dev_ops = {
2175 .dev_configure = nfp_net_configure,
2176 .dev_start = nfp_net_start,
2177 .dev_stop = nfp_net_stop,
2178 .dev_close = nfp_net_close,
2179 .promiscuous_enable = nfp_net_promisc_enable,
2180 .promiscuous_disable = nfp_net_promisc_disable,
2181 .link_update = nfp_net_link_update,
2182 .stats_get = nfp_net_stats_get,
2183 .stats_reset = nfp_net_stats_reset,
2184 .dev_infos_get = nfp_net_infos_get,
2185 .mtu_set = nfp_net_dev_mtu_set,
2186 .vlan_offload_set = nfp_net_vlan_offload_set,
2187 .reta_update = nfp_net_reta_update,
2188 .reta_query = nfp_net_reta_query,
2189 .rss_hash_update = nfp_net_rss_hash_update,
2190 .rss_hash_conf_get = nfp_net_rss_hash_conf_get,
2191 .rx_queue_setup = nfp_net_rx_queue_setup,
2192 .rx_queue_release = nfp_net_rx_queue_release,
2193 .rx_queue_count = nfp_net_rx_queue_count,
2194 .tx_queue_setup = nfp_net_tx_queue_setup,
2195 .tx_queue_release = nfp_net_tx_queue_release,
2199 nfp_net_init(struct rte_eth_dev *eth_dev)
2201 struct rte_pci_device *pci_dev;
2202 struct nfp_net_hw *hw;
2204 uint32_t tx_bar_off, rx_bar_off;
2208 PMD_INIT_FUNC_TRACE();
2210 hw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2212 eth_dev->dev_ops = &nfp_net_eth_dev_ops;
2213 eth_dev->rx_pkt_burst = &nfp_net_recv_pkts;
2214 eth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;
2216 /* For secondary processes, the primary has done all the work */
2217 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2220 pci_dev = eth_dev->pci_dev;
2221 hw->device_id = pci_dev->id.device_id;
2222 hw->vendor_id = pci_dev->id.vendor_id;
2223 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2224 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2226 PMD_INIT_LOG(DEBUG, "nfp_net: device (%u:%u) %u:%u:%u:%u\n",
2227 pci_dev->id.vendor_id, pci_dev->id.device_id,
2228 pci_dev->addr.domain, pci_dev->addr.bus,
2229 pci_dev->addr.devid, pci_dev->addr.function);
2231 hw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;
2232 if (hw->ctrl_bar == NULL) {
2234 "hw->ctrl_bar is NULL. BAR0 not configured\n");
2237 hw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);
2238 hw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);
2240 /* Work out where in the BAR the queues start. */
2241 switch (pci_dev->id.device_id) {
2242 case PCI_DEVICE_ID_NFP6000_VF_NIC:
2243 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);
2244 tx_bar_off = NFP_PCIE_QUEUE(start_q);
2245 start_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);
2246 rx_bar_off = NFP_PCIE_QUEUE(start_q);
2249 RTE_LOG(ERR, PMD, "nfp_net: no device ID matching\n");
2253 PMD_INIT_LOG(DEBUG, "tx_bar_off: 0x%08x\n", tx_bar_off);
2254 PMD_INIT_LOG(DEBUG, "rx_bar_off: 0x%08x\n", rx_bar_off);
2256 hw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;
2257 hw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;
2259 PMD_INIT_LOG(DEBUG, "ctrl_bar: %p, tx_bar: %p, rx_bar: %p\n",
2260 hw->ctrl_bar, hw->tx_bar, hw->rx_bar);
2262 nfp_net_cfg_queue_setup(hw);
2264 /* Get some of the read-only fields from the config BAR */
2265 hw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);
2266 hw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);
2267 hw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);
2268 hw->mtu = hw->max_mtu;
2270 if (NFD_CFG_MAJOR_VERSION_of(hw->ver) < 2)
2271 hw->rx_offset = NFP_NET_RX_OFFSET;
2273 hw->rx_offset = nn_cfg_readl(hw, NFP_NET_CFG_RX_OFFSET_ADDR);
2275 PMD_INIT_LOG(INFO, "VER: %#x, Maximum supported MTU: %d\n",
2276 hw->ver, hw->max_mtu);
2277 PMD_INIT_LOG(INFO, "CAP: %#x, %s%s%s%s%s%s%s%s%s\n", hw->cap,
2278 hw->cap & NFP_NET_CFG_CTRL_PROMISC ? "PROMISC " : "",
2279 hw->cap & NFP_NET_CFG_CTRL_RXCSUM ? "RXCSUM " : "",
2280 hw->cap & NFP_NET_CFG_CTRL_TXCSUM ? "TXCSUM " : "",
2281 hw->cap & NFP_NET_CFG_CTRL_RXVLAN ? "RXVLAN " : "",
2282 hw->cap & NFP_NET_CFG_CTRL_TXVLAN ? "TXVLAN " : "",
2283 hw->cap & NFP_NET_CFG_CTRL_SCATTER ? "SCATTER " : "",
2284 hw->cap & NFP_NET_CFG_CTRL_GATHER ? "GATHER " : "",
2285 hw->cap & NFP_NET_CFG_CTRL_LSO ? "TSO " : "",
2286 hw->cap & NFP_NET_CFG_CTRL_RSS ? "RSS " : "");
2288 pci_dev = eth_dev->pci_dev;
2291 hw->stride_rx = stride;
2292 hw->stride_tx = stride;
2294 PMD_INIT_LOG(INFO, "max_rx_queues: %u, max_tx_queues: %u\n",
2295 hw->max_rx_queues, hw->max_tx_queues);
2297 /* Allocating memory for mac addr */
2298 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2299 if (eth_dev->data->mac_addrs == NULL) {
2300 PMD_INIT_LOG(ERR, "Failed to space for MAC address");
2304 /* Using random mac addresses for VFs */
2305 eth_random_addr(&hw->mac_addr[0]);
2307 /* Copying mac address to DPDK eth_dev struct */
2308 ether_addr_copy(ð_dev->data->mac_addrs[0],
2309 (struct ether_addr *)hw->mac_addr);
2311 PMD_INIT_LOG(INFO, "port %d VendorID=0x%x DeviceID=0x%x "
2312 "mac=%02x:%02x:%02x:%02x:%02x:%02x",
2313 eth_dev->data->port_id, pci_dev->id.vendor_id,
2314 pci_dev->id.device_id,
2315 hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],
2316 hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);
2318 /* Recording current stats counters values */
2319 nfp_net_stats_reset(eth_dev);
2324 static struct rte_pci_id pci_id_nfp_net_map[] = {
2326 .vendor_id = PCI_VENDOR_ID_NETRONOME,
2327 .device_id = PCI_DEVICE_ID_NFP6000_PF_NIC,
2328 .subsystem_vendor_id = PCI_ANY_ID,
2329 .subsystem_device_id = PCI_ANY_ID,
2332 .vendor_id = PCI_VENDOR_ID_NETRONOME,
2333 .device_id = PCI_DEVICE_ID_NFP6000_VF_NIC,
2334 .subsystem_vendor_id = PCI_ANY_ID,
2335 .subsystem_device_id = PCI_ANY_ID,
2342 static struct eth_driver rte_nfp_net_pmd = {
2344 .name = "rte_nfp_net_pmd",
2345 .id_table = pci_id_nfp_net_map,
2346 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2348 .eth_dev_init = nfp_net_init,
2349 .dev_private_size = sizeof(struct nfp_net_adapter),
2353 nfp_net_pmd_init(const char *name __rte_unused,
2354 const char *params __rte_unused)
2356 PMD_INIT_FUNC_TRACE();
2357 PMD_INIT_LOG(INFO, "librte_pmd_nfp_net version %s\n",
2358 NFP_NET_PMD_VERSION);
2360 rte_eth_driver_register(&rte_nfp_net_pmd);
2364 static struct rte_driver rte_nfp_net_driver = {
2366 .init = nfp_net_pmd_init,
2369 PMD_REGISTER_DRIVER(rte_nfp_net_driver);
2373 * c-file-style: "Linux"
2374 * indent-tabs-mode: t