drivers/net/qede/qede_ethdev.h

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9
  10 #ifndef _QEDE_ETHDEV_H_
  11 #define _QEDE_ETHDEV_H_
  12
  13 #include <sys/queue.h>
  14
  15 #include <rte_ether.h>
  16 #include <rte_ethdev.h>
  17 #include <rte_dev.h>
  18 #include <rte_ip.h>
  19
  20 /* ecore includes */
  21 #include "base/bcm_osal.h"
  22 #include "base/ecore.h"
  23 #include "base/ecore_dev_api.h"
  24 #include "base/ecore_l2_api.h"
  25 #include "base/ecore_vf_api.h"
  26 #include "base/ecore_hsi_common.h"
  27 #include "base/ecore_int_api.h"
  28 #include "base/ecore_chain.h"
  29 #include "base/ecore_status.h"
  30 #include "base/ecore_hsi_eth.h"
  31 #include "base/ecore_dev_api.h"
  32 #include "base/ecore_iov_api.h"
  33 #include "base/ecore_cxt.h"
  34 #include "base/nvm_cfg.h"
  35 #include "base/ecore_iov_api.h"
  36 #include "base/ecore_sp_commands.h"
  37 #include "base/ecore_l2.h"
  38 #include "base/ecore_dev_api.h"
  39
  40 #include "qede_logs.h"
  41 #include "qede_if.h"
  42 #include "qede_eth_if.h"
  43
  44 #include "qede_rxtx.h"
  45
  46 #define qede_stringify1(x...)           #x
  47 #define qede_stringify(x...)            qede_stringify1(x)
  48
  49 /* Driver versions */
  50 #define QEDE_PMD_VER_PREFIX             "QEDE PMD"
  51 #define QEDE_PMD_VERSION_MAJOR          2
  52 #define QEDE_PMD_VERSION_MINOR          4
  53 #define QEDE_PMD_VERSION_REVISION       0
  54 #define QEDE_PMD_VERSION_PATCH          1
  55
  56 #define QEDE_PMD_VERSION qede_stringify(QEDE_PMD_VERSION_MAJOR) "."     \
  57                          qede_stringify(QEDE_PMD_VERSION_MINOR) "."     \
  58                          qede_stringify(QEDE_PMD_VERSION_REVISION) "."  \
  59                          qede_stringify(QEDE_PMD_VERSION_PATCH)
  60
  61 #define QEDE_PMD_DRV_VER_STR_SIZE NAME_SIZE
  62 #define QEDE_PMD_VER_PREFIX "QEDE PMD"
  63
  64
  65 #define QEDE_RSS_INDIR_INITED     (1 << 0)
  66 #define QEDE_RSS_KEY_INITED       (1 << 1)
  67 #define QEDE_RSS_CAPS_INITED      (1 << 2)
  68
  69 #define QEDE_MAX_RSS_CNT(edev)  ((edev)->dev_info.num_queues)
  70 #define QEDE_MAX_TSS_CNT(edev)  ((edev)->dev_info.num_queues * \
  71                                         (edev)->dev_info.num_tc)
  72
  73 #define QEDE_QUEUE_CNT(qdev) ((qdev)->num_queues)
  74 #define QEDE_RSS_COUNT(qdev) ((qdev)->num_queues - (qdev)->fp_num_tx)
  75 #define QEDE_TSS_COUNT(qdev) (((qdev)->num_queues - (qdev)->fp_num_rx) * \
  76                                         (qdev)->num_tc)
  77
  78 #define QEDE_FASTPATH_TX        (1 << 0)
  79 #define QEDE_FASTPATH_RX        (1 << 1)
  80
  81 #define QEDE_DUPLEX_FULL        1
  82 #define QEDE_DUPLEX_HALF        2
  83 #define QEDE_DUPLEX_UNKNOWN     0xff
  84
  85 #define QEDE_SUPPORTED_AUTONEG (1 << 6)
  86 #define QEDE_SUPPORTED_PAUSE   (1 << 13)
  87
  88 #define QEDE_INIT_QDEV(eth_dev) (eth_dev->data->dev_private)
  89
  90 #define QEDE_INIT_EDEV(adapter) (&((struct qede_dev *)adapter)->edev)
  91
  92 #define QEDE_INIT(eth_dev) {                                    \
  93         struct qede_dev *qdev = eth_dev->data->dev_private;     \
  94         struct ecore_dev *edev = &qdev->edev;                   \
  95 }
  96
  97 /************* QLogic 10G/25G/40G/50G/100G vendor/devices ids *************/
  98 #define PCI_VENDOR_ID_QLOGIC                   0x1077
  99
 100 #define CHIP_NUM_57980E                        0x1634
 101 #define CHIP_NUM_57980S                        0x1629
 102 #define CHIP_NUM_VF                            0x1630
 103 #define CHIP_NUM_57980S_40                     0x1634
 104 #define CHIP_NUM_57980S_25                     0x1656
 105 #define CHIP_NUM_57980S_IOV                    0x1664
 106 #define CHIP_NUM_57980S_100                    0x1644
 107 #define CHIP_NUM_57980S_50                     0x1654
 108 #define CHIP_NUM_AH_50G                        0x8070
 109 #define CHIP_NUM_AH_10G                        0x8071
 110 #define CHIP_NUM_AH_40G                        0x8072
 111 #define CHIP_NUM_AH_25G                        0x8073
 112 #define CHIP_NUM_AH_IOV                        0x8090
 113
 114 #define PCI_DEVICE_ID_QLOGIC_NX2_57980E        CHIP_NUM_57980E
 115 #define PCI_DEVICE_ID_QLOGIC_NX2_57980S        CHIP_NUM_57980S
 116 #define PCI_DEVICE_ID_QLOGIC_NX2_VF            CHIP_NUM_VF
 117 #define PCI_DEVICE_ID_QLOGIC_57980S_40         CHIP_NUM_57980S_40
 118 #define PCI_DEVICE_ID_QLOGIC_57980S_25         CHIP_NUM_57980S_25
 119 #define PCI_DEVICE_ID_QLOGIC_57980S_IOV        CHIP_NUM_57980S_IOV
 120 #define PCI_DEVICE_ID_QLOGIC_57980S_100        CHIP_NUM_57980S_100
 121 #define PCI_DEVICE_ID_QLOGIC_57980S_50         CHIP_NUM_57980S_50
 122 #define PCI_DEVICE_ID_QLOGIC_AH_50G            CHIP_NUM_AH_50G
 123 #define PCI_DEVICE_ID_QLOGIC_AH_10G            CHIP_NUM_AH_10G
 124 #define PCI_DEVICE_ID_QLOGIC_AH_40G            CHIP_NUM_AH_40G
 125 #define PCI_DEVICE_ID_QLOGIC_AH_25G            CHIP_NUM_AH_25G
 126 #define PCI_DEVICE_ID_QLOGIC_AH_IOV            CHIP_NUM_AH_IOV
 127
 128
 129 #define QEDE_VXLAN_DEF_PORT             8472
 130
 131 extern char fw_file[];
 132
 133 /* Number of PF connections - 32 RX + 32 TX */
 134 #define QEDE_PF_NUM_CONNS               (64)
 135
 136 /* Maximum number of flowdir filters */
 137 #define QEDE_RFS_MAX_FLTR               (256)
 138
 139 /* Port/function states */
 140 enum qede_dev_state {
 141         QEDE_DEV_INIT, /* Init the chip and Slowpath */
 142         QEDE_DEV_CONFIG, /* Create Vport/Fastpath resources */
 143         QEDE_DEV_START, /* Start RX/TX queues, enable traffic */
 144         QEDE_DEV_STOP, /* Deactivate vport and stop traffic */
 145 };
 146
 147 struct qede_vlan_entry {
 148         SLIST_ENTRY(qede_vlan_entry) list;
 149         uint16_t vid;
 150 };
 151
 152 struct qede_mcast_entry {
 153         struct ether_addr mac;
 154         SLIST_ENTRY(qede_mcast_entry) list;
 155 };
 156
 157 struct qede_ucast_entry {
 158         struct ether_addr mac;
 159         uint16_t vlan;
 160         uint16_t vni;
 161         SLIST_ENTRY(qede_ucast_entry) list;
 162 };
 163
 164 struct qede_fdir_entry {
 165         uint32_t soft_id; /* unused for now */
 166         uint16_t pkt_len; /* actual packet length to match */
 167         uint16_t rx_queue; /* queue to be steered to */
 168         const struct rte_memzone *mz; /* mz used to hold L2 frame */
 169         SLIST_ENTRY(qede_fdir_entry) list;
 170 };
 171
 172 struct qede_fdir_info {
 173         struct ecore_arfs_config_params arfs;
 174         uint16_t filter_count;
 175         SLIST_HEAD(fdir_list_head, qede_fdir_entry)fdir_list_head;
 176 };
 177
 178
 179 /*
 180  *  Structure to store private data for each port.
 181  */
 182 struct qede_dev {
 183         struct ecore_dev edev;
 184         uint8_t protocol;
 185         const struct qed_eth_ops *ops;
 186         struct qed_dev_eth_info dev_info;
 187         struct ecore_sb_info *sb_array;
 188         struct qede_fastpath *fp_array;
 189         uint8_t num_tc;
 190         uint16_t mtu;
 191         bool rss_enable;
 192         struct rte_eth_rss_conf rss_conf;
 193         uint16_t rss_ind_table[ECORE_RSS_IND_TABLE_SIZE];
 194         uint64_t rss_hf;
 195         uint8_t rss_key_len;
 196         bool enable_lro;
 197         uint16_t num_queues;
 198         uint8_t fp_num_tx;
 199         uint8_t fp_num_rx;
 200         enum qede_dev_state state;
 201         SLIST_HEAD(vlan_list_head, qede_vlan_entry)vlan_list_head;
 202         uint16_t configured_vlans;
 203         bool accept_any_vlan;
 204         struct ether_addr primary_mac;
 205         SLIST_HEAD(mc_list_head, qede_mcast_entry) mc_list_head;
 206         uint16_t num_mc_addr;
 207         SLIST_HEAD(uc_list_head, qede_ucast_entry) uc_list_head;
 208         uint16_t num_uc_addr;
 209         bool handle_hw_err;
 210         uint16_t num_tunn_filters;
 211         uint16_t vxlan_filter_type;
 212         struct qede_fdir_info fdir_info;
 213         char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 214 };
 215
 216 /* Static functions */
 217 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 218                                 uint16_t vlan_id, int on);
 219
 220 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
 221                                 struct rte_eth_rss_conf *rss_conf);
 222
 223 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
 224                                 struct rte_eth_rss_reta_entry64 *reta_conf,
 225                                 uint16_t reta_size);
 226
 227 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf);
 228
 229 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags);
 230
 231 static uint16_t qede_fdir_construct_pkt(struct rte_eth_dev *eth_dev,
 232                                         struct rte_eth_fdir_filter *fdir,
 233                                         void *buff,
 234                                         struct ecore_arfs_config_params *param);
 235
 236 /* Non-static functions */
 237 int qede_config_rss(struct rte_eth_dev *eth_dev);
 238
 239 int qed_fill_eth_dev_info(struct ecore_dev *edev,
 240                                  struct qed_dev_eth_info *info);
 241 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up);
 242
 243 int qede_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type type,
 244                          enum rte_filter_op op, void *arg);
 245
 246 int qede_fdir_filter_conf(struct rte_eth_dev *eth_dev,
 247                           enum rte_filter_op filter_op, void *arg);
 248
 249 int qede_ntuple_filter_conf(struct rte_eth_dev *eth_dev,
 250                             enum rte_filter_op filter_op, void *arg);
 251
 252 int qede_check_fdir_support(struct rte_eth_dev *eth_dev);
 253
 254 void qede_fdir_dealloc_resc(struct rte_eth_dev *eth_dev);
 255
 256 #endif /* _QEDE_ETHDEV_H_ */