drivers/net/thunderx/nicvf_ethdev.c

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (C) Cavium networks Ltd. 2016.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Cavium networks nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <assert.h>
  34 #include <stdio.h>
  35 #include <stdbool.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <sys/queue.h>
  44 #include <sys/timerfd.h>
  45
  46 #include <rte_alarm.h>
  47 #include <rte_atomic.h>
  48 #include <rte_branch_prediction.h>
  49 #include <rte_byteorder.h>
  50 #include <rte_common.h>
  51 #include <rte_cycles.h>
  52 #include <rte_debug.h>
  53 #include <rte_dev.h>
  54 #include <rte_eal.h>
  55 #include <rte_ether.h>
  56 #include <rte_ethdev.h>
  57 #include <rte_interrupts.h>
  58 #include <rte_log.h>
  59 #include <rte_memory.h>
  60 #include <rte_memzone.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_pci.h>
  64 #include <rte_tailq.h>
  65
  66 #include "base/nicvf_plat.h"
  67
  68 #include "nicvf_ethdev.h"
  69 #include "nicvf_rxtx.h"
  70 #include "nicvf_svf.h"
  71 #include "nicvf_logs.h"
  72
  73 static void nicvf_dev_stop(struct rte_eth_dev *dev);
  74 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
  75 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
  76                           bool cleanup);
  77
  78 static inline int
  79 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
  80                                struct rte_eth_link *link)
  81 {
  82         struct rte_eth_link *dst = &dev->data->dev_link;
  83         struct rte_eth_link *src = link;
  84
  85         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
  86                 *(uint64_t *)src) == 0)
  87                 return -1;
  88
  89         return 0;
  90 }
  91
  92 static inline void
  93 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
  94 {
  95         link->link_status = nic->link_up;
  96         link->link_duplex = ETH_LINK_AUTONEG;
  97         if (nic->duplex == NICVF_HALF_DUPLEX)
  98                 link->link_duplex = ETH_LINK_HALF_DUPLEX;
  99         else if (nic->duplex == NICVF_FULL_DUPLEX)
 100                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
 101         link->link_speed = nic->speed;
 102         link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
 103 }
 104
 105 static void
 106 nicvf_interrupt(void *arg)
 107 {
 108         struct rte_eth_dev *dev = arg;
 109         struct nicvf *nic = nicvf_pmd_priv(dev);
 110
 111         if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
 112                 if (dev->data->dev_conf.intr_conf.lsc)
 113                         nicvf_set_eth_link_status(nic, &dev->data->dev_link);
 114                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 115         }
 116
 117         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 118                                 nicvf_interrupt, dev);
 119 }
 120
 121 static void
 122 nicvf_vf_interrupt(void *arg)
 123 {
 124         struct nicvf *nic = arg;
 125
 126         nicvf_reg_poll_interrupts(nic);
 127
 128         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 129                                 nicvf_vf_interrupt, nic);
 130 }
 131
 132 static int
 133 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
 134 {
 135         return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
 136 }
 137
 138 static int
 139 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
 140 {
 141         return rte_eal_alarm_cancel(fn, arg);
 142 }
 143
 144 /*
 145  * Return 0 means link status changed, -1 means not changed
 146  */
 147 static int
 148 nicvf_dev_link_update(struct rte_eth_dev *dev,
 149                       int wait_to_complete __rte_unused)
 150 {
 151         struct rte_eth_link link;
 152         struct nicvf *nic = nicvf_pmd_priv(dev);
 153
 154         PMD_INIT_FUNC_TRACE();
 155
 156         memset(&link, 0, sizeof(link));
 157         nicvf_set_eth_link_status(nic, &link);
 158         return nicvf_atomic_write_link_status(dev, &link);
 159 }
 160
 161 static int
 162 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 163 {
 164         struct nicvf *nic = nicvf_pmd_priv(dev);
 165         uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
 166         size_t i;
 167
 168         PMD_INIT_FUNC_TRACE();
 169
 170         if (frame_size > NIC_HW_MAX_FRS)
 171                 return -EINVAL;
 172
 173         if (frame_size < NIC_HW_MIN_FRS)
 174                 return -EINVAL;
 175
 176         buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 177
 178         /*
 179          * Refuse mtu that requires the support of scattered packets
 180          * when this feature has not been enabled before.
 181          */
 182         if (!dev->data->scattered_rx &&
 183                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
 184                 return -EINVAL;
 185
 186         /* check <seg size> * <max_seg>  >= max_frame */
 187         if (dev->data->scattered_rx &&
 188                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
 189                 return -EINVAL;
 190
 191         if (frame_size > ETHER_MAX_LEN)
 192                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
 193         else
 194                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
 195
 196         if (nicvf_mbox_update_hw_max_frs(nic, frame_size))
 197                 return -EINVAL;
 198
 199         /* Update max frame size */
 200         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size;
 201         nic->mtu = mtu;
 202
 203         for (i = 0; i < nic->sqs_count; i++)
 204                 nic->snicvf[i]->mtu = mtu;
 205
 206         return 0;
 207 }
 208
 209 static int
 210 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
 211 {
 212         uint64_t *data = regs->data;
 213         struct nicvf *nic = nicvf_pmd_priv(dev);
 214
 215         if (data == NULL) {
 216                 regs->length = nicvf_reg_get_count();
 217                 regs->width = THUNDERX_REG_BYTES;
 218                 return 0;
 219         }
 220
 221         /* Support only full register dump */
 222         if ((regs->length == 0) ||
 223                 (regs->length == (uint32_t)nicvf_reg_get_count())) {
 224                 regs->version = nic->vendor_id << 16 | nic->device_id;
 225                 nicvf_reg_dump(nic, data);
 226                 return 0;
 227         }
 228         return -ENOTSUP;
 229 }
 230
 231 static void
 232 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 233 {
 234         uint16_t qidx;
 235         struct nicvf_hw_rx_qstats rx_qstats;
 236         struct nicvf_hw_tx_qstats tx_qstats;
 237         struct nicvf_hw_stats port_stats;
 238         struct nicvf *nic = nicvf_pmd_priv(dev);
 239         uint16_t rx_start, rx_end;
 240         uint16_t tx_start, tx_end;
 241         size_t i;
 242
 243         /* RX queue indices for the first VF */
 244         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 245
 246         /* Reading per RX ring stats */
 247         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 248                 if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 249                         break;
 250
 251                 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
 252                 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 253                 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 254         }
 255
 256         /* TX queue indices for the first VF */
 257         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 258
 259         /* Reading per TX ring stats */
 260         for (qidx = tx_start; qidx <= tx_end; qidx++) {
 261                 if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 262                         break;
 263
 264                 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
 265                 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 266                 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 267         }
 268
 269         for (i = 0; i < nic->sqs_count; i++) {
 270                 struct nicvf *snic = nic->snicvf[i];
 271
 272                 if (snic == NULL)
 273                         break;
 274
 275                 /* RX queue indices for a secondary VF */
 276                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 277
 278                 /* Reading per RX ring stats */
 279                 for (qidx = rx_start; qidx <= rx_end; qidx++) {
 280                         if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 281                                 break;
 282
 283                         nicvf_hw_get_rx_qstats(snic, &rx_qstats,
 284                                                qidx % MAX_RCV_QUEUES_PER_QS);
 285                         stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 286                         stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 287                 }
 288
 289                 /* TX queue indices for a secondary VF */
 290                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 291                 /* Reading per TX ring stats */
 292                 for (qidx = tx_start; qidx <= tx_end; qidx++) {
 293                         if (qidx == RTE_ETHDEV_QUEUE_STAT_CNTRS)
 294                                 break;
 295
 296                         nicvf_hw_get_tx_qstats(snic, &tx_qstats,
 297                                                qidx % MAX_SND_QUEUES_PER_QS);
 298                         stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 299                         stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 300                 }
 301         }
 302
 303         nicvf_hw_get_stats(nic, &port_stats);
 304         stats->ibytes = port_stats.rx_bytes;
 305         stats->ipackets = port_stats.rx_ucast_frames;
 306         stats->ipackets += port_stats.rx_bcast_frames;
 307         stats->ipackets += port_stats.rx_mcast_frames;
 308         stats->ierrors = port_stats.rx_l2_errors;
 309         stats->imissed = port_stats.rx_drop_red;
 310         stats->imissed += port_stats.rx_drop_overrun;
 311         stats->imissed += port_stats.rx_drop_bcast;
 312         stats->imissed += port_stats.rx_drop_mcast;
 313         stats->imissed += port_stats.rx_drop_l3_bcast;
 314         stats->imissed += port_stats.rx_drop_l3_mcast;
 315
 316         stats->obytes = port_stats.tx_bytes_ok;
 317         stats->opackets = port_stats.tx_ucast_frames_ok;
 318         stats->opackets += port_stats.tx_bcast_frames_ok;
 319         stats->opackets += port_stats.tx_mcast_frames_ok;
 320         stats->oerrors = port_stats.tx_drops;
 321 }
 322
 323 static const uint32_t *
 324 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 325 {
 326         size_t copied;
 327         static uint32_t ptypes[32];
 328         struct nicvf *nic = nicvf_pmd_priv(dev);
 329         static const uint32_t ptypes_common[] = {
 330                 RTE_PTYPE_L3_IPV4,
 331                 RTE_PTYPE_L3_IPV4_EXT,
 332                 RTE_PTYPE_L3_IPV6,
 333                 RTE_PTYPE_L3_IPV6_EXT,
 334                 RTE_PTYPE_L4_TCP,
 335                 RTE_PTYPE_L4_UDP,
 336                 RTE_PTYPE_L4_FRAG,
 337         };
 338         static const uint32_t ptypes_tunnel[] = {
 339                 RTE_PTYPE_TUNNEL_GRE,
 340                 RTE_PTYPE_TUNNEL_GENEVE,
 341                 RTE_PTYPE_TUNNEL_VXLAN,
 342                 RTE_PTYPE_TUNNEL_NVGRE,
 343         };
 344         static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
 345
 346         copied = sizeof(ptypes_common);
 347         memcpy(ptypes, ptypes_common, copied);
 348         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 349                 memcpy((char *)ptypes + copied, ptypes_tunnel,
 350                         sizeof(ptypes_tunnel));
 351                 copied += sizeof(ptypes_tunnel);
 352         }
 353
 354         memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
 355         if (dev->rx_pkt_burst == nicvf_recv_pkts ||
 356                 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg)
 357                 return ptypes;
 358
 359         return NULL;
 360 }
 361
 362 static void
 363 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
 364 {
 365         int i;
 366         uint16_t rxqs = 0, txqs = 0;
 367         struct nicvf *nic = nicvf_pmd_priv(dev);
 368         uint16_t rx_start, rx_end;
 369         uint16_t tx_start, tx_end;
 370
 371         /* Reset all primary nic counters */
 372         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 373         for (i = rx_start; i <= rx_end; i++)
 374                 rxqs |= (0x3 << (i * 2));
 375
 376         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 377         for (i = tx_start; i <= tx_end; i++)
 378                 txqs |= (0x3 << (i * 2));
 379
 380         nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
 381
 382         /* Reset secondary nic queue counters */
 383         for (i = 0; i < nic->sqs_count; i++) {
 384                 struct nicvf *snic = nic->snicvf[i];
 385                 if (snic == NULL)
 386                         break;
 387
 388                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 389                 for (i = rx_start; i <= rx_end; i++)
 390                         rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2));
 391
 392                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 393                 for (i = tx_start; i <= tx_end; i++)
 394                         txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2));
 395
 396                 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs);
 397         }
 398 }
 399
 400 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
 401 static void
 402 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
 403 {
 404 }
 405
 406 static inline uint64_t
 407 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
 408 {
 409         uint64_t nic_rss = 0;
 410
 411         if (ethdev_rss & ETH_RSS_IPV4)
 412                 nic_rss |= RSS_IP_ENA;
 413
 414         if (ethdev_rss & ETH_RSS_IPV6)
 415                 nic_rss |= RSS_IP_ENA;
 416
 417         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
 418                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 419
 420         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
 421                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 422
 423         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
 424                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 425
 426         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
 427                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 428
 429         if (ethdev_rss & ETH_RSS_PORT)
 430                 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
 431
 432         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 433                 if (ethdev_rss & ETH_RSS_VXLAN)
 434                         nic_rss |= RSS_TUN_VXLAN_ENA;
 435
 436                 if (ethdev_rss & ETH_RSS_GENEVE)
 437                         nic_rss |= RSS_TUN_GENEVE_ENA;
 438
 439                 if (ethdev_rss & ETH_RSS_NVGRE)
 440                         nic_rss |= RSS_TUN_NVGRE_ENA;
 441         }
 442
 443         return nic_rss;
 444 }
 445
 446 static inline uint64_t
 447 nicvf_rss_nic_to_ethdev(struct nicvf *nic,  uint64_t nic_rss)
 448 {
 449         uint64_t ethdev_rss = 0;
 450
 451         if (nic_rss & RSS_IP_ENA)
 452                 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
 453
 454         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
 455                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
 456                                 ETH_RSS_NONFRAG_IPV6_TCP);
 457
 458         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
 459                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
 460                                 ETH_RSS_NONFRAG_IPV6_UDP);
 461
 462         if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
 463                 ethdev_rss |= ETH_RSS_PORT;
 464
 465         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 466                 if (nic_rss & RSS_TUN_VXLAN_ENA)
 467                         ethdev_rss |= ETH_RSS_VXLAN;
 468
 469                 if (nic_rss & RSS_TUN_GENEVE_ENA)
 470                         ethdev_rss |= ETH_RSS_GENEVE;
 471
 472                 if (nic_rss & RSS_TUN_NVGRE_ENA)
 473                         ethdev_rss |= ETH_RSS_NVGRE;
 474         }
 475         return ethdev_rss;
 476 }
 477
 478 static int
 479 nicvf_dev_reta_query(struct rte_eth_dev *dev,
 480                      struct rte_eth_rss_reta_entry64 *reta_conf,
 481                      uint16_t reta_size)
 482 {
 483         struct nicvf *nic = nicvf_pmd_priv(dev);
 484         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 485         int ret, i, j;
 486
 487         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 488                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 489                         "(%d) doesn't match the number hardware can supported "
 490                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 491                 return -EINVAL;
 492         }
 493
 494         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 495         if (ret)
 496                 return ret;
 497
 498         /* Copy RETA table */
 499         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 500                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 501                         if ((reta_conf[i].mask >> j) & 0x01)
 502                                 reta_conf[i].reta[j] = tbl[j];
 503         }
 504
 505         return 0;
 506 }
 507
 508 static int
 509 nicvf_dev_reta_update(struct rte_eth_dev *dev,
 510                       struct rte_eth_rss_reta_entry64 *reta_conf,
 511                       uint16_t reta_size)
 512 {
 513         struct nicvf *nic = nicvf_pmd_priv(dev);
 514         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 515         int ret, i, j;
 516
 517         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 518                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 519                         "(%d) doesn't match the number hardware can supported "
 520                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 521                 return -EINVAL;
 522         }
 523
 524         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 525         if (ret)
 526                 return ret;
 527
 528         /* Copy RETA table */
 529         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 530                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 531                         if ((reta_conf[i].mask >> j) & 0x01)
 532                                 tbl[j] = reta_conf[i].reta[j];
 533         }
 534
 535         return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 536 }
 537
 538 static int
 539 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 540                             struct rte_eth_rss_conf *rss_conf)
 541 {
 542         struct nicvf *nic = nicvf_pmd_priv(dev);
 543
 544         if (rss_conf->rss_key)
 545                 nicvf_rss_get_key(nic, rss_conf->rss_key);
 546
 547         rss_conf->rss_key_len =  RSS_HASH_KEY_BYTE_SIZE;
 548         rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
 549         return 0;
 550 }
 551
 552 static int
 553 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
 554                           struct rte_eth_rss_conf *rss_conf)
 555 {
 556         struct nicvf *nic = nicvf_pmd_priv(dev);
 557         uint64_t nic_rss;
 558
 559         if (rss_conf->rss_key &&
 560                 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
 561                 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
 562                                 rss_conf->rss_key_len);
 563                 return -EINVAL;
 564         }
 565
 566         if (rss_conf->rss_key)
 567                 nicvf_rss_set_key(nic, rss_conf->rss_key);
 568
 569         nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
 570         nicvf_rss_set_cfg(nic, nic_rss);
 571         return 0;
 572 }
 573
 574 static int
 575 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 576                     struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
 577 {
 578         const struct rte_memzone *rz;
 579         uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
 580
 581         rz = rte_eth_dma_zone_reserve(dev, "cq_ring",
 582                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 583                                       NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
 584         if (rz == NULL) {
 585                 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
 586                 return -ENOMEM;
 587         }
 588
 589         memset(rz->addr, 0, ring_size);
 590
 591         rxq->phys = rz->phys_addr;
 592         rxq->desc = rz->addr;
 593         rxq->qlen_mask = desc_cnt - 1;
 594
 595         return 0;
 596 }
 597
 598 static int
 599 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 600                     struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
 601 {
 602         const struct rte_memzone *rz;
 603         uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
 604
 605         rz = rte_eth_dma_zone_reserve(dev, "sq",
 606                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 607                                       NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
 608         if (rz == NULL) {
 609                 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
 610                 return -ENOMEM;
 611         }
 612
 613         memset(rz->addr, 0, ring_size);
 614
 615         sq->phys = rz->phys_addr;
 616         sq->desc = rz->addr;
 617         sq->qlen_mask = desc_cnt - 1;
 618
 619         return 0;
 620 }
 621
 622 static int
 623 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 624                       uint32_t desc_cnt, uint32_t buffsz)
 625 {
 626         struct nicvf_rbdr *rbdr;
 627         const struct rte_memzone *rz;
 628         uint32_t ring_size;
 629
 630         assert(nic->rbdr == NULL);
 631         rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
 632                                   RTE_CACHE_LINE_SIZE, nic->node);
 633         if (rbdr == NULL) {
 634                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
 635                 return -ENOMEM;
 636         }
 637
 638         ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
 639         rz = rte_eth_dma_zone_reserve(dev, "rbdr",
 640                                       nicvf_netdev_qidx(nic, 0), ring_size,
 641                                       NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
 642         if (rz == NULL) {
 643                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
 644                 return -ENOMEM;
 645         }
 646
 647         memset(rz->addr, 0, ring_size);
 648
 649         rbdr->phys = rz->phys_addr;
 650         rbdr->tail = 0;
 651         rbdr->next_tail = 0;
 652         rbdr->desc = rz->addr;
 653         rbdr->buffsz = buffsz;
 654         rbdr->qlen_mask = desc_cnt - 1;
 655         rbdr->rbdr_status =
 656                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
 657         rbdr->rbdr_door =
 658                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
 659
 660         nic->rbdr = rbdr;
 661         return 0;
 662 }
 663
 664 static void
 665 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
 666                         nicvf_phys_addr_t phy)
 667 {
 668         uint16_t qidx;
 669         void *obj;
 670         struct nicvf_rxq *rxq;
 671         uint16_t rx_start, rx_end;
 672
 673         /* Get queue ranges for this VF */
 674         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 675
 676         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 677                 rxq = dev->data->rx_queues[qidx];
 678                 if (rxq->precharge_cnt) {
 679                         obj = (void *)nicvf_mbuff_phy2virt(phy,
 680                                                            rxq->mbuf_phys_off);
 681                         rte_mempool_put(rxq->pool, obj);
 682                         rxq->precharge_cnt--;
 683                         break;
 684                 }
 685         }
 686 }
 687
 688 static inline void
 689 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
 690 {
 691         uint32_t qlen_mask, head;
 692         struct rbdr_entry_t *entry;
 693         struct nicvf_rbdr *rbdr = nic->rbdr;
 694
 695         qlen_mask = rbdr->qlen_mask;
 696         head = rbdr->head;
 697         while (head != rbdr->tail) {
 698                 entry = rbdr->desc + head;
 699                 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
 700                 head++;
 701                 head = head & qlen_mask;
 702         }
 703 }
 704
 705 static inline void
 706 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
 707 {
 708         uint32_t head;
 709
 710         head = txq->head;
 711         while (head != txq->tail) {
 712                 if (txq->txbuffs[head]) {
 713                         rte_pktmbuf_free_seg(txq->txbuffs[head]);
 714                         txq->txbuffs[head] = NULL;
 715                 }
 716                 head++;
 717                 head = head & txq->qlen_mask;
 718         }
 719 }
 720
 721 static void
 722 nicvf_tx_queue_reset(struct nicvf_txq *txq)
 723 {
 724         uint32_t txq_desc_cnt = txq->qlen_mask + 1;
 725
 726         memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
 727         memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
 728         txq->tail = 0;
 729         txq->head = 0;
 730         txq->xmit_bufs = 0;
 731 }
 732
 733 static inline int
 734 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 735                         uint16_t qidx)
 736 {
 737         struct nicvf_txq *txq;
 738         int ret;
 739
 740         assert(qidx < MAX_SND_QUEUES_PER_QS);
 741
 742         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 743                 RTE_ETH_QUEUE_STATE_STARTED)
 744                 return 0;
 745
 746         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 747         txq->pool = NULL;
 748         ret = nicvf_qset_sq_config(nic, qidx, txq);
 749         if (ret) {
 750                 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d",
 751                              nic->vf_id, qidx, ret);
 752                 goto config_sq_error;
 753         }
 754
 755         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 756                 RTE_ETH_QUEUE_STATE_STARTED;
 757         return ret;
 758
 759 config_sq_error:
 760         nicvf_qset_sq_reclaim(nic, qidx);
 761         return ret;
 762 }
 763
 764 static inline int
 765 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 766                        uint16_t qidx)
 767 {
 768         struct nicvf_txq *txq;
 769         int ret;
 770
 771         assert(qidx < MAX_SND_QUEUES_PER_QS);
 772
 773         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 774                 RTE_ETH_QUEUE_STATE_STOPPED)
 775                 return 0;
 776
 777         ret = nicvf_qset_sq_reclaim(nic, qidx);
 778         if (ret)
 779                 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
 780                              nic->vf_id, qidx, ret);
 781
 782         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 783         nicvf_tx_queue_release_mbufs(txq);
 784         nicvf_tx_queue_reset(txq);
 785
 786         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 787                 RTE_ETH_QUEUE_STATE_STOPPED;
 788         return ret;
 789 }
 790
 791 static inline int
 792 nicvf_configure_cpi(struct rte_eth_dev *dev)
 793 {
 794         struct nicvf *nic = nicvf_pmd_priv(dev);
 795         uint16_t qidx, qcnt;
 796         int ret;
 797
 798         /* Count started rx queues */
 799         for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
 800                 if (dev->data->rx_queue_state[qidx] ==
 801                     RTE_ETH_QUEUE_STATE_STARTED)
 802                         qcnt++;
 803
 804         nic->cpi_alg = CPI_ALG_NONE;
 805         ret = nicvf_mbox_config_cpi(nic, qcnt);
 806         if (ret)
 807                 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
 808
 809         return ret;
 810 }
 811
 812 static inline int
 813 nicvf_configure_rss(struct rte_eth_dev *dev)
 814 {
 815         struct nicvf *nic = nicvf_pmd_priv(dev);
 816         uint64_t rsshf;
 817         int ret = -EINVAL;
 818
 819         rsshf = nicvf_rss_ethdev_to_nic(nic,
 820                         dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
 821         PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
 822                     dev->data->dev_conf.rxmode.mq_mode,
 823                     dev->data->nb_rx_queues,
 824                     dev->data->dev_conf.lpbk_mode, rsshf);
 825
 826         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
 827                 ret = nicvf_rss_term(nic);
 828         else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
 829                 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
 830         if (ret)
 831                 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
 832
 833         return ret;
 834 }
 835
 836 static int
 837 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
 838 {
 839         struct nicvf *nic = nicvf_pmd_priv(dev);
 840         unsigned int idx, qmap_size;
 841         uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
 842         uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
 843
 844         if (nic->cpi_alg != CPI_ALG_NONE)
 845                 return -EINVAL;
 846
 847         /* Prepare queue map */
 848         for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
 849                 if (dev->data->rx_queue_state[idx] ==
 850                                 RTE_ETH_QUEUE_STATE_STARTED)
 851                         qmap[qmap_size++] = idx;
 852         }
 853
 854         /* Update default RSS RETA */
 855         for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
 856                 default_reta[idx] = qmap[idx % qmap_size];
 857
 858         return nicvf_rss_reta_update(nic, default_reta,
 859                                      NIC_MAX_RSS_IDR_TBL_SIZE);
 860 }
 861
 862 static void
 863 nicvf_dev_tx_queue_release(void *sq)
 864 {
 865         struct nicvf_txq *txq;
 866
 867         PMD_INIT_FUNC_TRACE();
 868
 869         txq = (struct nicvf_txq *)sq;
 870         if (txq) {
 871                 if (txq->txbuffs != NULL) {
 872                         nicvf_tx_queue_release_mbufs(txq);
 873                         rte_free(txq->txbuffs);
 874                         txq->txbuffs = NULL;
 875                 }
 876                 rte_free(txq);
 877         }
 878 }
 879
 880 static void
 881 nicvf_set_tx_function(struct rte_eth_dev *dev)
 882 {
 883         struct nicvf_txq *txq;
 884         size_t i;
 885         bool multiseg = false;
 886
 887         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 888                 txq = dev->data->tx_queues[i];
 889                 if ((txq->txq_flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) {
 890                         multiseg = true;
 891                         break;
 892                 }
 893         }
 894
 895         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
 896         if (multiseg) {
 897                 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
 898                 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
 899         } else {
 900                 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
 901                 dev->tx_pkt_burst = nicvf_xmit_pkts;
 902         }
 903
 904         if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
 905                 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
 906         else
 907                 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
 908 }
 909
 910 static void
 911 nicvf_set_rx_function(struct rte_eth_dev *dev)
 912 {
 913         if (dev->data->scattered_rx) {
 914                 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback");
 915                 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg;
 916         } else {
 917                 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback");
 918                 dev->rx_pkt_burst = nicvf_recv_pkts;
 919         }
 920 }
 921
 922 static int
 923 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
 924                          uint16_t nb_desc, unsigned int socket_id,
 925                          const struct rte_eth_txconf *tx_conf)
 926 {
 927         uint16_t tx_free_thresh;
 928         uint8_t is_single_pool;
 929         struct nicvf_txq *txq;
 930         struct nicvf *nic = nicvf_pmd_priv(dev);
 931
 932         PMD_INIT_FUNC_TRACE();
 933
 934         if (qidx >= MAX_SND_QUEUES_PER_QS)
 935                 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1];
 936
 937         qidx = qidx % MAX_SND_QUEUES_PER_QS;
 938
 939         /* Socket id check */
 940         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
 941                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
 942                 socket_id, nic->node);
 943
 944         /* Tx deferred start is not supported */
 945         if (tx_conf->tx_deferred_start) {
 946                 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
 947                 return -EINVAL;
 948         }
 949
 950         /* Roundup nb_desc to available qsize and validate max number of desc */
 951         nb_desc = nicvf_qsize_sq_roundup(nb_desc);
 952         if (nb_desc == 0) {
 953                 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
 954                 return -EINVAL;
 955         }
 956
 957         /* Validate tx_free_thresh */
 958         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 959                                 tx_conf->tx_free_thresh :
 960                                 NICVF_DEFAULT_TX_FREE_THRESH);
 961
 962         if (tx_free_thresh > (nb_desc) ||
 963                 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
 964                 PMD_INIT_LOG(ERR,
 965                         "tx_free_thresh must be less than the number of TX "
 966                         "descriptors. (tx_free_thresh=%u port=%d "
 967                         "queue=%d)", (unsigned int)tx_free_thresh,
 968                         (int)dev->data->port_id, (int)qidx);
 969                 return -EINVAL;
 970         }
 971
 972         /* Free memory prior to re-allocation if needed. */
 973         if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
 974                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
 975                                 nicvf_netdev_qidx(nic, qidx));
 976                 nicvf_dev_tx_queue_release(
 977                         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]);
 978                 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
 979         }
 980
 981         /* Allocating tx queue data structure */
 982         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
 983                                         RTE_CACHE_LINE_SIZE, nic->node);
 984         if (txq == NULL) {
 985                 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d",
 986                              nicvf_netdev_qidx(nic, qidx));
 987                 return -ENOMEM;
 988         }
 989
 990         txq->nic = nic;
 991         txq->queue_id = qidx;
 992         txq->tx_free_thresh = tx_free_thresh;
 993         txq->txq_flags = tx_conf->txq_flags;
 994         txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
 995         txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
 996         is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
 997                                 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
 998
 999         /* Choose optimum free threshold value for multipool case */
1000         if (!is_single_pool) {
1001                 txq->tx_free_thresh = (uint16_t)
1002                 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
1003                                 NICVF_TX_FREE_MPOOL_THRESH :
1004                                 tx_conf->tx_free_thresh);
1005                 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
1006         } else {
1007                 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
1008         }
1009
1010         /* Allocate software ring */
1011         txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
1012                                 nb_desc * sizeof(struct rte_mbuf *),
1013                                 RTE_CACHE_LINE_SIZE, nic->node);
1014
1015         if (txq->txbuffs == NULL) {
1016                 nicvf_dev_tx_queue_release(txq);
1017                 return -ENOMEM;
1018         }
1019
1020         if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
1021                 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
1022                 nicvf_dev_tx_queue_release(txq);
1023                 return -ENOMEM;
1024         }
1025
1026         nicvf_tx_queue_reset(txq);
1027
1028         PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
1029                         nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc,
1030                         txq->phys);
1031
1032         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq;
1033         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1034                 RTE_ETH_QUEUE_STATE_STOPPED;
1035         return 0;
1036 }
1037
1038 static inline void
1039 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
1040 {
1041         uint32_t rxq_cnt;
1042         uint32_t nb_pkts, released_pkts = 0;
1043         uint32_t refill_cnt = 0;
1044         struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
1045
1046         if (dev->rx_pkt_burst == NULL)
1047                 return;
1048
1049         while ((rxq_cnt = nicvf_dev_rx_queue_count(dev,
1050                                 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) {
1051                 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
1052                                         NICVF_MAX_RX_FREE_THRESH);
1053                 PMD_DRV_LOG(INFO, "nb_pkts=%d  rxq_cnt=%d", nb_pkts, rxq_cnt);
1054                 while (nb_pkts) {
1055                         rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
1056                         released_pkts++;
1057                 }
1058         }
1059
1060
1061         refill_cnt += nicvf_dev_rbdr_refill(dev,
1062                         nicvf_netdev_qidx(rxq->nic, rxq->queue_id));
1063
1064         PMD_DRV_LOG(INFO, "free_cnt=%d  refill_cnt=%d",
1065                     released_pkts, refill_cnt);
1066 }
1067
1068 static void
1069 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
1070 {
1071         rxq->head = 0;
1072         rxq->available_space = 0;
1073         rxq->recv_buffers = 0;
1074 }
1075
1076 static inline int
1077 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1078                         uint16_t qidx)
1079 {
1080         struct nicvf_rxq *rxq;
1081         int ret;
1082
1083         assert(qidx < MAX_RCV_QUEUES_PER_QS);
1084
1085         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1086                 RTE_ETH_QUEUE_STATE_STARTED)
1087                 return 0;
1088
1089         /* Update rbdr pointer to all rxq */
1090         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1091         rxq->shared_rbdr = nic->rbdr;
1092
1093         ret = nicvf_qset_rq_config(nic, qidx, rxq);
1094         if (ret) {
1095                 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d",
1096                              nic->vf_id, qidx, ret);
1097                 goto config_rq_error;
1098         }
1099         ret = nicvf_qset_cq_config(nic, qidx, rxq);
1100         if (ret) {
1101                 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d",
1102                              nic->vf_id, qidx, ret);
1103                 goto config_cq_error;
1104         }
1105
1106         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1107                 RTE_ETH_QUEUE_STATE_STARTED;
1108         return 0;
1109
1110 config_cq_error:
1111         nicvf_qset_cq_reclaim(nic, qidx);
1112 config_rq_error:
1113         nicvf_qset_rq_reclaim(nic, qidx);
1114         return ret;
1115 }
1116
1117 static inline int
1118 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1119                        uint16_t qidx)
1120 {
1121         struct nicvf_rxq *rxq;
1122         int ret, other_error;
1123
1124         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1125                 RTE_ETH_QUEUE_STATE_STOPPED)
1126                 return 0;
1127
1128         ret = nicvf_qset_rq_reclaim(nic, qidx);
1129         if (ret)
1130                 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1131                              nic->vf_id, qidx, ret);
1132
1133         other_error = ret;
1134         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1135         nicvf_rx_queue_release_mbufs(dev, rxq);
1136         nicvf_rx_queue_reset(rxq);
1137
1138         ret = nicvf_qset_cq_reclaim(nic, qidx);
1139         if (ret)
1140                 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1141                              nic->vf_id, qidx, ret);
1142
1143         other_error |= ret;
1144         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1145                 RTE_ETH_QUEUE_STATE_STOPPED;
1146         return other_error;
1147 }
1148
1149 static void
1150 nicvf_dev_rx_queue_release(void *rx_queue)
1151 {
1152         PMD_INIT_FUNC_TRACE();
1153
1154         rte_free(rx_queue);
1155 }
1156
1157 static int
1158 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1159 {
1160         struct nicvf *nic = nicvf_pmd_priv(dev);
1161         int ret;
1162
1163         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1164                 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)];
1165
1166         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1167
1168         ret = nicvf_vf_start_rx_queue(dev, nic, qidx);
1169         if (ret)
1170                 return ret;
1171
1172         ret = nicvf_configure_cpi(dev);
1173         if (ret)
1174                 return ret;
1175
1176         return nicvf_configure_rss_reta(dev);
1177 }
1178
1179 static int
1180 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1181 {
1182         int ret;
1183         struct nicvf *nic = nicvf_pmd_priv(dev);
1184
1185         if (qidx >= MAX_SND_QUEUES_PER_QS)
1186                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1187
1188         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1189
1190         ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1191         ret |= nicvf_configure_cpi(dev);
1192         ret |= nicvf_configure_rss_reta(dev);
1193         return ret;
1194 }
1195
1196 static int
1197 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1198 {
1199         struct nicvf *nic = nicvf_pmd_priv(dev);
1200
1201         if (qidx >= MAX_SND_QUEUES_PER_QS)
1202                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1203
1204         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1205
1206         return nicvf_vf_start_tx_queue(dev, nic, qidx);
1207 }
1208
1209 static int
1210 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1211 {
1212         struct nicvf *nic = nicvf_pmd_priv(dev);
1213
1214         if (qidx >= MAX_SND_QUEUES_PER_QS)
1215                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1216
1217         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1218
1219         return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1220 }
1221
1222
1223 static int
1224 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1225                          uint16_t nb_desc, unsigned int socket_id,
1226                          const struct rte_eth_rxconf *rx_conf,
1227                          struct rte_mempool *mp)
1228 {
1229         uint16_t rx_free_thresh;
1230         struct nicvf_rxq *rxq;
1231         struct nicvf *nic = nicvf_pmd_priv(dev);
1232
1233         PMD_INIT_FUNC_TRACE();
1234
1235         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1236                 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1];
1237
1238         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1239
1240         /* Socket id check */
1241         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1242                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1243                 socket_id, nic->node);
1244
1245         /* Mempool memory must be contiguous, so must be one memory segment*/
1246         if (mp->nb_mem_chunks != 1) {
1247                 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1248                 return -EINVAL;
1249         }
1250
1251         /* Mempool memory must be physically contiguous */
1252         if (mp->flags & MEMPOOL_F_NO_PHYS_CONTIG) {
1253                 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1254                 return -EINVAL;
1255         }
1256
1257         /* Rx deferred start is not supported */
1258         if (rx_conf->rx_deferred_start) {
1259                 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1260                 return -EINVAL;
1261         }
1262
1263         /* Roundup nb_desc to available qsize and validate max number of desc */
1264         nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1265         if (nb_desc == 0) {
1266                 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1267                 return -EINVAL;
1268         }
1269
1270         /* Check rx_free_thresh upper bound */
1271         rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1272                                 rx_conf->rx_free_thresh :
1273                                 NICVF_DEFAULT_RX_FREE_THRESH);
1274         if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1275                 rx_free_thresh >= nb_desc * .75) {
1276                 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1277                                 rx_free_thresh);
1278                 return -EINVAL;
1279         }
1280
1281         /* Free memory prior to re-allocation if needed */
1282         if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
1283                 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1284                                 nicvf_netdev_qidx(nic, qidx));
1285                 nicvf_dev_rx_queue_release(
1286                         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]);
1287                 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1288         }
1289
1290         /* Allocate rxq memory */
1291         rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1292                                         RTE_CACHE_LINE_SIZE, nic->node);
1293         if (rxq == NULL) {
1294                 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d",
1295                              nicvf_netdev_qidx(nic, qidx));
1296                 return -ENOMEM;
1297         }
1298
1299         rxq->nic = nic;
1300         rxq->pool = mp;
1301         rxq->queue_id = qidx;
1302         rxq->port_id = dev->data->port_id;
1303         rxq->rx_free_thresh = rx_free_thresh;
1304         rxq->rx_drop_en = rx_conf->rx_drop_en;
1305         rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1306         rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1307         rxq->precharge_cnt = 0;
1308
1309         if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1310                 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1311         else
1312                 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1313
1314
1315         /* Alloc completion queue */
1316         if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1317                 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1318                 nicvf_dev_rx_queue_release(rxq);
1319                 return -ENOMEM;
1320         }
1321
1322         nicvf_rx_queue_reset(rxq);
1323
1324         PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
1325                         nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc,
1326                         rte_mempool_avail_count(mp), rxq->phys);
1327
1328         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq;
1329         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1330                 RTE_ETH_QUEUE_STATE_STOPPED;
1331         return 0;
1332 }
1333
1334 static void
1335 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1336 {
1337         struct nicvf *nic = nicvf_pmd_priv(dev);
1338         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1339
1340         PMD_INIT_FUNC_TRACE();
1341
1342         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1343
1344         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1345         dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
1346         dev_info->max_rx_queues =
1347                         (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1348         dev_info->max_tx_queues =
1349                         (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1350         dev_info->max_mac_addrs = 1;
1351         dev_info->max_vfs = pci_dev->max_vfs;
1352
1353         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1354         dev_info->tx_offload_capa =
1355                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1356                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1357                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1358                 DEV_TX_OFFLOAD_TCP_TSO     |
1359                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1360
1361         dev_info->reta_size = nic->rss_info.rss_size;
1362         dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1363         dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1364         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1365                 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1366
1367         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1368                 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1369                 .rx_drop_en = 0,
1370         };
1371
1372         dev_info->default_txconf = (struct rte_eth_txconf) {
1373                 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1374                 .txq_flags =
1375                         ETH_TXQ_FLAGS_NOMULTSEGS  |
1376                         ETH_TXQ_FLAGS_NOREFCOUNT  |
1377                         ETH_TXQ_FLAGS_NOMULTMEMP  |
1378                         ETH_TXQ_FLAGS_NOVLANOFFL  |
1379                         ETH_TXQ_FLAGS_NOXSUMSCTP,
1380         };
1381 }
1382
1383 static nicvf_phys_addr_t
1384 rbdr_rte_mempool_get(void *dev, void *opaque)
1385 {
1386         uint16_t qidx;
1387         uintptr_t mbuf;
1388         struct nicvf_rxq *rxq;
1389         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1390         struct nicvf *nic = (struct nicvf *)opaque;
1391         uint16_t rx_start, rx_end;
1392
1393         /* Get queue ranges for this VF */
1394         nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end);
1395
1396         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1397                 rxq = eth_dev->data->rx_queues[qidx];
1398                 /* Maintain equal buffer count across all pools */
1399                 if (rxq->precharge_cnt >= rxq->qlen_mask)
1400                         continue;
1401                 rxq->precharge_cnt++;
1402                 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1403                 if (mbuf)
1404                         return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1405         }
1406         return 0;
1407 }
1408
1409 static int
1410 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
1411 {
1412         int ret;
1413         uint16_t qidx;
1414         uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1415         uint64_t mbuf_phys_off = 0;
1416         struct nicvf_rxq *rxq;
1417         struct rte_mbuf *mbuf;
1418         uint16_t rx_start, rx_end;
1419         uint16_t tx_start, tx_end;
1420
1421         PMD_INIT_FUNC_TRACE();
1422
1423         /* Userspace process exited without proper shutdown in last run */
1424         if (nicvf_qset_rbdr_active(nic, 0))
1425                 nicvf_vf_stop(dev, nic, false);
1426
1427         /* Get queue ranges for this VF */
1428         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1429
1430         /*
1431          * Thunderx nicvf PMD can support more than one pool per port only when
1432          * 1) Data payload size is same across all the pools in given port
1433          * AND
1434          * 2) All mbuffs in the pools are from the same hugepage
1435          * AND
1436          * 3) Mbuff metadata size is same across all the pools in given port
1437          *
1438          * This is to support existing application that uses multiple pool/port.
1439          * But, the purpose of using multipool for QoS will not be addressed.
1440          *
1441          */
1442
1443         /* Validate mempool attributes */
1444         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1445                 rxq = dev->data->rx_queues[qidx];
1446                 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1447                 mbuf = rte_pktmbuf_alloc(rxq->pool);
1448                 if (mbuf == NULL) {
1449                         PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d "
1450                                      "pool=%s",
1451                                      nic->vf_id, qidx, rxq->pool->name);
1452                         return -ENOMEM;
1453                 }
1454                 rxq->mbuf_phys_off -= nicvf_mbuff_meta_length(mbuf);
1455                 rxq->mbuf_phys_off -= RTE_PKTMBUF_HEADROOM;
1456                 rte_pktmbuf_free(mbuf);
1457
1458                 if (mbuf_phys_off == 0)
1459                         mbuf_phys_off = rxq->mbuf_phys_off;
1460                 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1461                         PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %"
1462                                      PRIx64, rxq->pool->name, nic->vf_id,
1463                                      mbuf_phys_off);
1464                         return -EINVAL;
1465                 }
1466         }
1467
1468         /* Check the level of buffers in the pool */
1469         total_rxq_desc = 0;
1470         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1471                 rxq = dev->data->rx_queues[qidx];
1472                 /* Count total numbers of rxq descs */
1473                 total_rxq_desc += rxq->qlen_mask + 1;
1474                 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1475                 exp_buffs *= dev->data->nb_rx_queues;
1476                 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1477                         PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1478                                      rxq->pool->name,
1479                                      rte_mempool_avail_count(rxq->pool),
1480                                      exp_buffs);
1481                         return -ENOENT;
1482                 }
1483         }
1484
1485         /* Check RBDR desc overflow */
1486         ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1487         if (ret == 0) {
1488                 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc "
1489                              "VF%d", nic->vf_id);
1490                 return -ENOMEM;
1491         }
1492
1493         /* Enable qset */
1494         ret = nicvf_qset_config(nic);
1495         if (ret) {
1496                 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret,
1497                              nic->vf_id);
1498                 return ret;
1499         }
1500
1501         /* Allocate RBDR and RBDR ring desc */
1502         nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1503         ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1504         if (ret) {
1505                 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc "
1506                              "VF%d", nic->vf_id);
1507                 goto qset_reclaim;
1508         }
1509
1510         /* Enable and configure RBDR registers */
1511         ret = nicvf_qset_rbdr_config(nic, 0);
1512         if (ret) {
1513                 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret,
1514                              nic->vf_id);
1515                 goto qset_rbdr_free;
1516         }
1517
1518         /* Fill rte_mempool buffers in RBDR pool and precharge it */
1519         ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1520                                         total_rxq_desc);
1521         if (ret) {
1522                 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret,
1523                              nic->vf_id);
1524                 goto qset_rbdr_reclaim;
1525         }
1526
1527         PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d",
1528                      nic->rbdr->tail, nb_rbdr_desc, nic->vf_id);
1529
1530         /* Configure VLAN Strip */
1531         nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip);
1532
1533         /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
1534          * to the 64bit memory address.
1535          * The alignment creates a hole in mbuf(between the end of headroom and
1536          * packet data start). The new revision of the HW provides an option to
1537          * disable the L3 alignment feature and make mbuf layout looks
1538          * more like other NICs. For better application compatibility, disabling
1539          * l3 alignment feature on the hardware revisions it supports
1540          */
1541         nicvf_apad_config(nic, false);
1542
1543         /* Get queue ranges for this VF */
1544         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1545
1546         /* Configure TX queues */
1547         for (qidx = tx_start; qidx <= tx_end; qidx++) {
1548                 ret = nicvf_vf_start_tx_queue(dev, nic,
1549                         qidx % MAX_SND_QUEUES_PER_QS);
1550                 if (ret)
1551                         goto start_txq_error;
1552         }
1553
1554         /* Configure RX queues */
1555         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1556                 ret = nicvf_vf_start_rx_queue(dev, nic,
1557                         qidx % MAX_RCV_QUEUES_PER_QS);
1558                 if (ret)
1559                         goto start_rxq_error;
1560         }
1561
1562         if (!nic->sqs_mode) {
1563                 /* Configure CPI algorithm */
1564                 ret = nicvf_configure_cpi(dev);
1565                 if (ret)
1566                         goto start_txq_error;
1567
1568                 ret = nicvf_mbox_get_rss_size(nic);
1569                 if (ret) {
1570                         PMD_INIT_LOG(ERR, "Failed to get rss table size");
1571                         goto qset_rss_error;
1572                 }
1573
1574                 /* Configure RSS */
1575                 ret = nicvf_configure_rss(dev);
1576                 if (ret)
1577                         goto qset_rss_error;
1578         }
1579
1580         /* Done; Let PF make the BGX's RX and TX switches to ON position */
1581         nicvf_mbox_cfg_done(nic);
1582         return 0;
1583
1584 qset_rss_error:
1585         nicvf_rss_term(nic);
1586 start_rxq_error:
1587         for (qidx = rx_start; qidx <= rx_end; qidx++)
1588                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1589 start_txq_error:
1590         for (qidx = tx_start; qidx <= tx_end; qidx++)
1591                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1592 qset_rbdr_reclaim:
1593         nicvf_qset_rbdr_reclaim(nic, 0);
1594         nicvf_rbdr_release_mbufs(dev, nic);
1595 qset_rbdr_free:
1596         if (nic->rbdr) {
1597                 rte_free(nic->rbdr);
1598                 nic->rbdr = NULL;
1599         }
1600 qset_reclaim:
1601         nicvf_qset_reclaim(nic);
1602         return ret;
1603 }
1604
1605 static int
1606 nicvf_dev_start(struct rte_eth_dev *dev)
1607 {
1608         uint16_t qidx;
1609         int ret;
1610         size_t i;
1611         struct nicvf *nic = nicvf_pmd_priv(dev);
1612         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1613         uint16_t mtu;
1614         uint32_t buffsz = 0, rbdrsz = 0;
1615         struct rte_pktmbuf_pool_private *mbp_priv;
1616         struct nicvf_rxq *rxq;
1617
1618         PMD_INIT_FUNC_TRACE();
1619
1620         /* This function must be called for a primary device */
1621         assert_primary(nic);
1622
1623         /* Validate RBDR buff size */
1624         for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1625                 rxq = dev->data->rx_queues[qidx];
1626                 mbp_priv = rte_mempool_get_priv(rxq->pool);
1627                 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1628                 if (buffsz % 128) {
1629                         PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1630                         return -EINVAL;
1631                 }
1632                 if (rbdrsz == 0)
1633                         rbdrsz = buffsz;
1634                 if (rbdrsz != buffsz) {
1635                         PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)",
1636                                      qidx, rbdrsz, buffsz);
1637                         return -EINVAL;
1638                 }
1639         }
1640
1641         /* Configure loopback */
1642         ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1643         if (ret) {
1644                 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1645                 return ret;
1646         }
1647
1648         /* Reset all statistics counters attached to this port */
1649         ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1650         if (ret) {
1651                 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1652                 return ret;
1653         }
1654
1655         /* Setup scatter mode if needed by jumbo */
1656         if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1657                                             2 * VLAN_TAG_SIZE > buffsz)
1658                 dev->data->scattered_rx = 1;
1659         if (rx_conf->enable_scatter)
1660                 dev->data->scattered_rx = 1;
1661
1662         /* Setup MTU based on max_rx_pkt_len or default */
1663         mtu = dev->data->dev_conf.rxmode.jumbo_frame ?
1664                 dev->data->dev_conf.rxmode.max_rx_pkt_len
1665                         -  ETHER_HDR_LEN - ETHER_CRC_LEN
1666                 : ETHER_MTU;
1667
1668         if (nicvf_dev_set_mtu(dev, mtu)) {
1669                 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1670                 return -EBUSY;
1671         }
1672
1673         ret = nicvf_vf_start(dev, nic, rbdrsz);
1674         if (ret != 0)
1675                 return ret;
1676
1677         for (i = 0; i < nic->sqs_count; i++) {
1678                 assert(nic->snicvf[i]);
1679
1680                 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz);
1681                 if (ret != 0)
1682                         return ret;
1683         }
1684
1685         /* Configure callbacks based on scatter mode */
1686         nicvf_set_tx_function(dev);
1687         nicvf_set_rx_function(dev);
1688
1689         return 0;
1690 }
1691
1692 static void
1693 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1694 {
1695         size_t i;
1696         int ret;
1697         struct nicvf *nic = nicvf_pmd_priv(dev);
1698
1699         PMD_INIT_FUNC_TRACE();
1700
1701         /* Teardown secondary vf first */
1702         for (i = 0; i < nic->sqs_count; i++) {
1703                 if (!nic->snicvf[i])
1704                         continue;
1705
1706                 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1707         }
1708
1709         /* Stop the primary VF now */
1710         nicvf_vf_stop(dev, nic, cleanup);
1711
1712         /* Disable loopback */
1713         ret = nicvf_loopback_config(nic, 0);
1714         if (ret)
1715                 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1716
1717         /* Reclaim CPI configuration */
1718         ret = nicvf_mbox_config_cpi(nic, 0);
1719         if (ret)
1720                 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1721 }
1722
1723 static void
1724 nicvf_dev_stop(struct rte_eth_dev *dev)
1725 {
1726         PMD_INIT_FUNC_TRACE();
1727
1728         nicvf_dev_stop_cleanup(dev, false);
1729 }
1730
1731 static void
1732 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1733 {
1734         int ret;
1735         uint16_t qidx;
1736         uint16_t tx_start, tx_end;
1737         uint16_t rx_start, rx_end;
1738
1739         PMD_INIT_FUNC_TRACE();
1740
1741         if (cleanup) {
1742                 /* Let PF make the BGX's RX and TX switches to OFF position */
1743                 nicvf_mbox_shutdown(nic);
1744         }
1745
1746         /* Disable VLAN Strip */
1747         nicvf_vlan_hw_strip(nic, 0);
1748
1749         /* Get queue ranges for this VF */
1750         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1751
1752         for (qidx = tx_start; qidx <= tx_end; qidx++)
1753                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1754
1755         /* Get queue ranges for this VF */
1756         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1757
1758         /* Reclaim rq */
1759         for (qidx = rx_start; qidx <= rx_end; qidx++)
1760                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1761
1762         /* Reclaim RBDR */
1763         ret = nicvf_qset_rbdr_reclaim(nic, 0);
1764         if (ret)
1765                 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1766
1767         /* Move all charged buffers in RBDR back to pool */
1768         if (nic->rbdr != NULL)
1769                 nicvf_rbdr_release_mbufs(dev, nic);
1770
1771         /* Disable qset */
1772         ret = nicvf_qset_reclaim(nic);
1773         if (ret)
1774                 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1775
1776         /* Disable all interrupts */
1777         nicvf_disable_all_interrupts(nic);
1778
1779         /* Free RBDR SW structure */
1780         if (nic->rbdr) {
1781                 rte_free(nic->rbdr);
1782                 nic->rbdr = NULL;
1783         }
1784 }
1785
1786 static void
1787 nicvf_dev_close(struct rte_eth_dev *dev)
1788 {
1789         size_t i;
1790         struct nicvf *nic = nicvf_pmd_priv(dev);
1791
1792         PMD_INIT_FUNC_TRACE();
1793
1794         nicvf_dev_stop_cleanup(dev, true);
1795         nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1796
1797         for (i = 0; i < nic->sqs_count; i++) {
1798                 if (!nic->snicvf[i])
1799                         continue;
1800
1801                 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1802         }
1803 }
1804
1805 static int
1806 nicvf_request_sqs(struct nicvf *nic)
1807 {
1808         size_t i;
1809
1810         assert_primary(nic);
1811         assert(nic->sqs_count > 0);
1812         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1813
1814         /* Set no of Rx/Tx queues in each of the SQsets */
1815         for (i = 0; i < nic->sqs_count; i++) {
1816                 if (nicvf_svf_empty())
1817                         rte_panic("Cannot assign sufficient number of "
1818                                   "secondary queues to primary VF%" PRIu8 "\n",
1819                                   nic->vf_id);
1820
1821                 nic->snicvf[i] = nicvf_svf_pop();
1822                 nic->snicvf[i]->sqs_id = i;
1823         }
1824
1825         return nicvf_mbox_request_sqs(nic);
1826 }
1827
1828 static int
1829 nicvf_dev_configure(struct rte_eth_dev *dev)
1830 {
1831         struct rte_eth_dev_data *data = dev->data;
1832         struct rte_eth_conf *conf = &data->dev_conf;
1833         struct rte_eth_rxmode *rxmode = &conf->rxmode;
1834         struct rte_eth_txmode *txmode = &conf->txmode;
1835         struct nicvf *nic = nicvf_pmd_priv(dev);
1836         uint8_t cqcount;
1837
1838         PMD_INIT_FUNC_TRACE();
1839
1840         if (!rte_eal_has_hugepages()) {
1841                 PMD_INIT_LOG(INFO, "Huge page is not configured");
1842                 return -EINVAL;
1843         }
1844
1845         if (txmode->mq_mode) {
1846                 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1847                 return -EINVAL;
1848         }
1849
1850         if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1851                 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1852                 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1853                 return -EINVAL;
1854         }
1855
1856         if (!rxmode->hw_strip_crc) {
1857                 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
1858                 rxmode->hw_strip_crc = 1;
1859         }
1860
1861         if (rxmode->hw_ip_checksum) {
1862                 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
1863                 rxmode->hw_ip_checksum = 0;
1864         }
1865
1866         if (rxmode->split_hdr_size) {
1867                 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1868                 return -EINVAL;
1869         }
1870
1871         if (rxmode->hw_vlan_filter) {
1872                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
1873                 return -EINVAL;
1874         }
1875
1876         if (rxmode->hw_vlan_extend) {
1877                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
1878                 return -EINVAL;
1879         }
1880
1881         if (rxmode->enable_lro) {
1882                 PMD_INIT_LOG(INFO, "LRO not supported");
1883                 return -EINVAL;
1884         }
1885
1886         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1887                 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1888                 return -EINVAL;
1889         }
1890
1891         if (conf->dcb_capability_en) {
1892                 PMD_INIT_LOG(INFO, "DCB enable not supported");
1893                 return -EINVAL;
1894         }
1895
1896         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1897                 PMD_INIT_LOG(INFO, "Flow director not supported");
1898                 return -EINVAL;
1899         }
1900
1901         assert_primary(nic);
1902         NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS);
1903         cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues);
1904         if (cqcount > MAX_RCV_QUEUES_PER_QS) {
1905                 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS);
1906                 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1;
1907         } else {
1908                 nic->sqs_count = 0;
1909         }
1910
1911         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1912
1913         if (nic->sqs_count > 0) {
1914                 if (nicvf_request_sqs(nic)) {
1915                         rte_panic("Cannot assign sufficient number of "
1916                                   "secondary queues to PORT%d VF%" PRIu8 "\n",
1917                                   dev->data->port_id, nic->vf_id);
1918                 }
1919         }
1920
1921         PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1922                 dev->data->port_id, nicvf_hw_cap(nic));
1923
1924         return 0;
1925 }
1926
1927 /* Initialize and register driver with DPDK Application */
1928 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1929         .dev_configure            = nicvf_dev_configure,
1930         .dev_start                = nicvf_dev_start,
1931         .dev_stop                 = nicvf_dev_stop,
1932         .link_update              = nicvf_dev_link_update,
1933         .dev_close                = nicvf_dev_close,
1934         .stats_get                = nicvf_dev_stats_get,
1935         .stats_reset              = nicvf_dev_stats_reset,
1936         .promiscuous_enable       = nicvf_dev_promisc_enable,
1937         .dev_infos_get            = nicvf_dev_info_get,
1938         .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1939         .mtu_set                  = nicvf_dev_set_mtu,
1940         .reta_update              = nicvf_dev_reta_update,
1941         .reta_query               = nicvf_dev_reta_query,
1942         .rss_hash_update          = nicvf_dev_rss_hash_update,
1943         .rss_hash_conf_get        = nicvf_dev_rss_hash_conf_get,
1944         .rx_queue_start           = nicvf_dev_rx_queue_start,
1945         .rx_queue_stop            = nicvf_dev_rx_queue_stop,
1946         .tx_queue_start           = nicvf_dev_tx_queue_start,
1947         .tx_queue_stop            = nicvf_dev_tx_queue_stop,
1948         .rx_queue_setup           = nicvf_dev_rx_queue_setup,
1949         .rx_queue_release         = nicvf_dev_rx_queue_release,
1950         .rx_queue_count           = nicvf_dev_rx_queue_count,
1951         .tx_queue_setup           = nicvf_dev_tx_queue_setup,
1952         .tx_queue_release         = nicvf_dev_tx_queue_release,
1953         .get_reg                  = nicvf_dev_get_regs,
1954 };
1955
1956 static int
1957 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
1958 {
1959         int ret;
1960         struct rte_pci_device *pci_dev;
1961         struct nicvf *nic = nicvf_pmd_priv(eth_dev);
1962
1963         PMD_INIT_FUNC_TRACE();
1964
1965         eth_dev->dev_ops = &nicvf_eth_dev_ops;
1966
1967         /* For secondary processes, the primary has done all the work */
1968         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1969                 if (nic) {
1970                         /* Setup callbacks for secondary process */
1971                         nicvf_set_tx_function(eth_dev);
1972                         nicvf_set_rx_function(eth_dev);
1973                         return 0;
1974                 } else {
1975                         /* If nic == NULL than it is secondary function
1976                          * so ethdev need to be released by caller */
1977                         return ENOTSUP;
1978                 }
1979         }
1980
1981         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1982         rte_eth_copy_pci_info(eth_dev, pci_dev);
1983
1984         nic->device_id = pci_dev->id.device_id;
1985         nic->vendor_id = pci_dev->id.vendor_id;
1986         nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
1987         nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1988
1989         PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
1990                         pci_dev->id.vendor_id, pci_dev->id.device_id,
1991                         pci_dev->addr.domain, pci_dev->addr.bus,
1992                         pci_dev->addr.devid, pci_dev->addr.function);
1993
1994         nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
1995         if (!nic->reg_base) {
1996                 PMD_INIT_LOG(ERR, "Failed to map BAR0");
1997                 ret = -ENODEV;
1998                 goto fail;
1999         }
2000
2001         nicvf_disable_all_interrupts(nic);
2002
2003         ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
2004         if (ret) {
2005                 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2006                 goto fail;
2007         }
2008
2009         ret = nicvf_mbox_check_pf_ready(nic);
2010         if (ret) {
2011                 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
2012                 goto alarm_fail;
2013         } else {
2014                 PMD_INIT_LOG(INFO,
2015                         "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
2016                         nic->node, nic->vf_id,
2017                         nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
2018                         nic->sqs_mode ? "true" : "false",
2019                         nic->loopback_supported ? "true" : "false"
2020                         );
2021         }
2022
2023         ret = nicvf_base_init(nic);
2024         if (ret) {
2025                 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
2026                 goto malloc_fail;
2027         }
2028
2029         if (nic->sqs_mode) {
2030                 /* Push nic to stack of secondary vfs */
2031                 nicvf_svf_push(nic);
2032
2033                 /* Steal nic pointer from the device for further reuse */
2034                 eth_dev->data->dev_private = NULL;
2035
2036                 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2037                 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic);
2038                 if (ret) {
2039                         PMD_INIT_LOG(ERR, "Failed to start period alarm");
2040                         goto fail;
2041                 }
2042
2043                 /* Detach port by returning postive error number */
2044                 return ENOTSUP;
2045         }
2046
2047         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2048         if (eth_dev->data->mac_addrs == NULL) {
2049                 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
2050                 ret = -ENOMEM;
2051                 goto alarm_fail;
2052         }
2053         if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
2054                 eth_random_addr(&nic->mac_addr[0]);
2055
2056         ether_addr_copy((struct ether_addr *)nic->mac_addr,
2057                         &eth_dev->data->mac_addrs[0]);
2058
2059         ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
2060         if (ret) {
2061                 PMD_INIT_LOG(ERR, "Failed to set mac addr");
2062                 goto malloc_fail;
2063         }
2064
2065         PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
2066                 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
2067                 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
2068                 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
2069
2070         return 0;
2071
2072 malloc_fail:
2073         rte_free(eth_dev->data->mac_addrs);
2074 alarm_fail:
2075         nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2076 fail:
2077         return ret;
2078 }
2079
2080 static const struct rte_pci_id pci_id_nicvf_map[] = {
2081         {
2082                 .class_id = RTE_CLASS_ANY_ID,
2083                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2084                 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
2085                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2086                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
2087         },
2088         {
2089                 .class_id = RTE_CLASS_ANY_ID,
2090                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2091                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2092                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2093                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
2094         },
2095         {
2096                 .class_id = RTE_CLASS_ANY_ID,
2097                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2098                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2099                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2100                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
2101         },
2102         {
2103                 .class_id = RTE_CLASS_ANY_ID,
2104                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2105                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2106                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2107                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF,
2108         },
2109         {
2110                 .vendor_id = 0,
2111         },
2112 };
2113
2114 static struct eth_driver rte_nicvf_pmd = {
2115         .pci_drv = {
2116                 .id_table = pci_id_nicvf_map,
2117                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2118                 .probe = rte_eth_dev_pci_probe,
2119                 .remove = rte_eth_dev_pci_remove,
2120         },
2121         .eth_dev_init = nicvf_eth_dev_init,
2122         .dev_private_size = sizeof(struct nicvf),
2123 };
2124
2125 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd.pci_drv);
2126 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);
2127 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio");