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34 #include <sys/queue.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_string_fns.h>
61 #include <rte_malloc.h>
64 #include "base/vmxnet3_defs.h"
66 #include "vmxnet3_ring.h"
67 #include "vmxnet3_logs.h"
68 #include "vmxnet3_ethdev.h"
70 #define PROCESS_SYS_EVENTS 0
72 #define VMXNET3_TX_MAX_SEG UINT8_MAX
74 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
75 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev);
76 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
77 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
78 static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
79 static void vmxnet3_dev_close(struct rte_eth_dev *dev);
80 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
81 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
82 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
83 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
84 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
85 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
86 int wait_to_complete);
87 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
88 int wait_to_complete);
89 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw);
90 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
91 struct rte_eth_stats *stats);
92 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
93 struct rte_eth_xstat_name *xstats,
95 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev,
96 struct rte_eth_xstat *xstats, unsigned int n);
97 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev,
98 struct rte_eth_dev_info *dev_info);
99 static const uint32_t *
100 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
101 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
102 uint16_t vid, int on);
103 static void vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
104 static void vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
105 struct ether_addr *mac_addr);
106 static void vmxnet3_interrupt_handler(void *param);
109 * The set of PCI devices this driver supports
111 #define VMWARE_PCI_VENDOR_ID 0x15AD
112 #define VMWARE_DEV_ID_VMXNET3 0x07B0
113 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
114 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) },
115 { .vendor_id = 0, /* sentinel */ },
118 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
119 .dev_configure = vmxnet3_dev_configure,
120 .dev_start = vmxnet3_dev_start,
121 .dev_stop = vmxnet3_dev_stop,
122 .dev_close = vmxnet3_dev_close,
123 .promiscuous_enable = vmxnet3_dev_promiscuous_enable,
124 .promiscuous_disable = vmxnet3_dev_promiscuous_disable,
125 .allmulticast_enable = vmxnet3_dev_allmulticast_enable,
126 .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
127 .link_update = vmxnet3_dev_link_update,
128 .stats_get = vmxnet3_dev_stats_get,
129 .xstats_get_names = vmxnet3_dev_xstats_get_names,
130 .xstats_get = vmxnet3_dev_xstats_get,
131 .mac_addr_set = vmxnet3_mac_addr_set,
132 .dev_infos_get = vmxnet3_dev_info_get,
133 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
134 .vlan_filter_set = vmxnet3_dev_vlan_filter_set,
135 .vlan_offload_set = vmxnet3_dev_vlan_offload_set,
136 .rx_queue_setup = vmxnet3_dev_rx_queue_setup,
137 .rx_queue_release = vmxnet3_dev_rx_queue_release,
138 .tx_queue_setup = vmxnet3_dev_tx_queue_setup,
139 .tx_queue_release = vmxnet3_dev_tx_queue_release,
142 struct vmxnet3_xstats_name_off {
143 char name[RTE_ETH_XSTATS_NAME_SIZE];
147 /* tx_qX_ is prepended to the name string here */
148 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = {
149 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)},
150 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)},
151 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)},
152 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)},
155 /* rx_qX_ is prepended to the name string here */
156 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = {
157 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)},
158 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)},
159 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)},
160 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)},
163 static const struct rte_memzone *
164 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
165 const char *post_string, int socket_id,
166 uint16_t align, bool reuse)
168 char z_name[RTE_MEMZONE_NAMESIZE];
169 const struct rte_memzone *mz;
171 snprintf(z_name, sizeof(z_name), "%s_%d_%s",
172 dev->device->driver->name, dev->data->port_id, post_string);
174 mz = rte_memzone_lookup(z_name);
177 rte_memzone_free(mz);
178 return rte_memzone_reserve_aligned(z_name, size, socket_id,
185 return rte_memzone_reserve_aligned(z_name, size, socket_id, 0, align);
189 * Atomically reads the link status information from global
190 * structure rte_eth_dev.
193 * - Pointer to the structure rte_eth_dev to read from.
194 * - Pointer to the buffer to be saved with the link status.
197 * - On success, zero.
198 * - On failure, negative value.
202 vmxnet3_dev_atomic_read_link_status(struct rte_eth_dev *dev,
203 struct rte_eth_link *link)
205 struct rte_eth_link *dst = link;
206 struct rte_eth_link *src = &(dev->data->dev_link);
208 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
209 *(uint64_t *)src) == 0)
216 * Atomically writes the link status information into global
217 * structure rte_eth_dev.
220 * - Pointer to the structure rte_eth_dev to write to.
221 * - Pointer to the buffer to be saved with the link status.
224 * - On success, zero.
225 * - On failure, negative value.
228 vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev,
229 struct rte_eth_link *link)
231 struct rte_eth_link *dst = &(dev->data->dev_link);
232 struct rte_eth_link *src = link;
234 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
235 *(uint64_t *)src) == 0)
242 * This function is based on vmxnet3_disable_intr()
245 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
249 PMD_INIT_FUNC_TRACE();
251 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
252 for (i = 0; i < hw->num_intrs; i++)
253 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
257 vmxnet3_enable_intr(struct vmxnet3_hw *hw)
261 PMD_INIT_FUNC_TRACE();
263 hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL;
264 for (i = 0; i < hw->num_intrs; i++)
265 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0);
269 * Gets tx data ring descriptor size.
272 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw)
274 uint16 txdata_desc_size;
276 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
277 VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
278 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
280 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE ||
281 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE ||
282 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ?
283 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size;
287 * It returns 0 on success.
290 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
292 struct rte_pci_device *pci_dev;
293 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
294 uint32_t mac_hi, mac_lo, ver;
296 PMD_INIT_FUNC_TRACE();
298 eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
299 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
300 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
301 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
302 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
305 * for secondary processes, we don't initialize any further as primary
306 * has already done this work.
308 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
311 rte_eth_copy_pci_info(eth_dev, pci_dev);
313 /* Vendor and Device ID need to be set before init of shared code */
314 hw->device_id = pci_dev->id.device_id;
315 hw->vendor_id = pci_dev->id.vendor_id;
316 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
317 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
319 hw->num_rx_queues = 1;
320 hw->num_tx_queues = 1;
321 hw->bufs_per_pkt = 1;
323 /* Check h/w version compatibility with driver. */
324 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
325 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
327 if (ver & (1 << VMXNET3_REV_3)) {
328 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
330 hw->version = VMXNET3_REV_3 + 1;
331 } else if (ver & (1 << VMXNET3_REV_2)) {
332 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
334 hw->version = VMXNET3_REV_2 + 1;
335 } else if (ver & (1 << VMXNET3_REV_1)) {
336 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
338 hw->version = VMXNET3_REV_1 + 1;
340 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver);
344 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version);
346 /* Check UPT version compatibility with driver. */
347 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
348 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
350 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
352 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
356 /* Getting MAC Address */
357 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
358 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
359 memcpy(hw->perm_addr, &mac_lo, 4);
360 memcpy(hw->perm_addr + 4, &mac_hi, 2);
362 /* Allocate memory for storing MAC addresses */
363 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN *
364 VMXNET3_MAX_MAC_ADDRS, 0);
365 if (eth_dev->data->mac_addrs == NULL) {
367 "Failed to allocate %d bytes needed to store MAC addresses",
368 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
371 /* Copy the permanent MAC address */
372 ether_addr_copy((struct ether_addr *) hw->perm_addr,
373 ð_dev->data->mac_addrs[0]);
375 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
376 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
377 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
379 /* Put device in Quiesce Mode */
380 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
382 /* allow untagged pkts */
383 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
385 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
386 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc);
388 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
389 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
390 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) ==
391 hw->rxdata_desc_size);
393 /* clear shadow stats */
394 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats));
395 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats));
401 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev)
403 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
405 PMD_INIT_FUNC_TRACE();
407 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
410 if (hw->adapter_stopped == 0)
411 vmxnet3_dev_close(eth_dev);
413 eth_dev->dev_ops = NULL;
414 eth_dev->rx_pkt_burst = NULL;
415 eth_dev->tx_pkt_burst = NULL;
416 eth_dev->tx_pkt_prepare = NULL;
418 rte_free(eth_dev->data->mac_addrs);
419 eth_dev->data->mac_addrs = NULL;
424 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
425 struct rte_pci_device *pci_dev)
427 return rte_eth_dev_pci_generic_probe(pci_dev,
428 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init);
431 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev)
433 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit);
436 static struct rte_pci_driver rte_vmxnet3_pmd = {
437 .id_table = pci_id_vmxnet3_map,
438 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
439 .probe = eth_vmxnet3_pci_probe,
440 .remove = eth_vmxnet3_pci_remove,
444 vmxnet3_dev_configure(struct rte_eth_dev *dev)
446 const struct rte_memzone *mz;
447 struct vmxnet3_hw *hw = dev->data->dev_private;
450 PMD_INIT_FUNC_TRACE();
452 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES ||
453 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) {
454 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported");
458 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) {
459 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2");
463 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
464 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
466 if (size > UINT16_MAX)
469 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
470 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
473 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
476 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
477 "shared", rte_socket_id(), 8, 1);
480 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
483 memset(mz->addr, 0, mz->len);
485 hw->shared = mz->addr;
486 hw->sharedPA = mz->phys_addr;
489 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
492 * We cannot reuse this memzone from previous allocation as its size
493 * depends on the number of tx and rx queues, which could be different
494 * from one config to another.
496 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(),
497 VMXNET3_QUEUE_DESC_ALIGN, 0);
499 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
502 memset(mz->addr, 0, mz->len);
504 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
505 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
507 hw->queueDescPA = mz->phys_addr;
508 hw->queue_desc_len = (uint16_t)size;
510 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
511 /* Allocate memory structure for UPT1_RSSConf and configure */
512 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf),
513 "rss_conf", rte_socket_id(),
514 RTE_CACHE_LINE_SIZE, 1);
517 "ERROR: Creating rss_conf structure zone");
520 memset(mz->addr, 0, mz->len);
522 hw->rss_conf = mz->addr;
523 hw->rss_confPA = mz->phys_addr;
530 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr)
535 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
536 addr[0], addr[1], addr[2],
537 addr[3], addr[4], addr[5]);
539 memcpy(&val, addr, 4);
540 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
542 memcpy(&val, addr + 4, 2);
543 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
547 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev)
549 struct vmxnet3_hw *hw = dev->data->dev_private;
550 Vmxnet3_DriverShared *shared = hw->shared;
551 Vmxnet3_CmdInfo *cmdInfo;
552 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES];
553 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES];
554 uint32_t num, i, j, size;
556 if (hw->memRegsPA == 0) {
557 const struct rte_memzone *mz;
559 size = sizeof(Vmxnet3_MemRegs) +
560 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) *
561 sizeof(Vmxnet3_MemoryRegion);
563 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8,
566 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone");
569 memset(mz->addr, 0, mz->len);
570 hw->memRegs = mz->addr;
571 hw->memRegsPA = mz->phys_addr;
574 num = hw->num_rx_queues;
576 for (i = 0; i < num; i++) {
577 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
584 * The same mempool could be used by multiple queues. In such a case,
585 * remove duplicate mempool entries. Only one entry is kept with
586 * bitmask indicating queues that are using this mempool.
588 for (i = 1; i < num; i++) {
589 for (j = 0; j < i; j++) {
590 if (mp[i] == mp[j]) {
599 for (i = 0; i < num; i++) {
603 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j];
606 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->phys_addr;
607 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ?
608 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX;
609 mr->txQueueBits = index[i];
610 mr->rxQueueBits = index[i];
613 "index: %u startPA: %" PRIu64 " length: %u, "
615 j, mr->startPA, mr->length, mr->rxQueueBits);
618 hw->memRegs->numRegs = j;
619 PMD_INIT_LOG(INFO, "numRegs: %u", j);
621 size = sizeof(Vmxnet3_MemRegs) +
622 (j - 1) * sizeof(Vmxnet3_MemoryRegion);
624 cmdInfo = &shared->cu.cmdInfo;
625 cmdInfo->varConf.confVer = 1;
626 cmdInfo->varConf.confLen = size;
627 cmdInfo->varConf.confPA = hw->memRegsPA;
633 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
635 struct rte_eth_conf port_conf = dev->data->dev_conf;
636 struct vmxnet3_hw *hw = dev->data->dev_private;
637 uint32_t mtu = dev->data->mtu;
638 Vmxnet3_DriverShared *shared = hw->shared;
639 Vmxnet3_DSDevRead *devRead = &shared->devRead;
643 shared->magic = VMXNET3_REV1_MAGIC;
644 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
646 /* Setting up Guest OS information */
647 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ?
648 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64;
649 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
650 devRead->misc.driverInfo.vmxnet3RevSpt = 1;
651 devRead->misc.driverInfo.uptVerSpt = 1;
653 devRead->misc.mtu = rte_le_to_cpu_32(mtu);
654 devRead->misc.queueDescPA = hw->queueDescPA;
655 devRead->misc.queueDescLen = hw->queue_desc_len;
656 devRead->misc.numTxQueues = hw->num_tx_queues;
657 devRead->misc.numRxQueues = hw->num_rx_queues;
660 * Set number of interrupts to 1
661 * PMD by default disables all the interrupts but this is MUST
662 * to activate device. It needs at least one interrupt for
663 * link events to handle
665 hw->num_intrs = devRead->intrConf.numIntrs = 1;
666 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
668 for (i = 0; i < hw->num_tx_queues; i++) {
669 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
670 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i];
672 tqd->ctrl.txNumDeferred = 0;
673 tqd->ctrl.txThreshold = 1;
674 tqd->conf.txRingBasePA = txq->cmd_ring.basePA;
675 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
676 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
678 tqd->conf.txRingSize = txq->cmd_ring.size;
679 tqd->conf.compRingSize = txq->comp_ring.size;
680 tqd->conf.dataRingSize = txq->data_ring.size;
681 tqd->conf.txDataRingDescSize = txq->txdata_desc_size;
682 tqd->conf.intrIdx = txq->comp_ring.intr_idx;
683 tqd->status.stopped = TRUE;
684 tqd->status.error = 0;
685 memset(&tqd->stats, 0, sizeof(tqd->stats));
688 for (i = 0; i < hw->num_rx_queues; i++) {
689 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i];
690 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
692 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
693 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
694 rqd->conf.compRingBasePA = rxq->comp_ring.basePA;
696 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size;
697 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size;
698 rqd->conf.compRingSize = rxq->comp_ring.size;
699 rqd->conf.intrIdx = rxq->comp_ring.intr_idx;
700 if (VMXNET3_VERSION_GE_3(hw)) {
701 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA;
702 rqd->conf.rxDataRingDescSize = rxq->data_desc_size;
704 rqd->status.stopped = TRUE;
705 rqd->status.error = 0;
706 memset(&rqd->stats, 0, sizeof(rqd->stats));
709 /* RxMode set to 0 of VMXNET3_RXM_xxx */
710 devRead->rxFilterConf.rxMode = 0;
712 /* Setting up feature flags */
713 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
714 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
716 if (dev->data->dev_conf.rxmode.enable_lro) {
717 devRead->misc.uptFeatures |= VMXNET3_F_LRO;
718 devRead->misc.maxNumRxSG = 0;
721 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
722 ret = vmxnet3_rss_configure(dev);
723 if (ret != VMXNET3_SUCCESS)
726 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
727 devRead->rssConfDesc.confVer = 1;
728 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
729 devRead->rssConfDesc.confPA = hw->rss_confPA;
732 vmxnet3_dev_vlan_offload_set(dev,
733 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK);
735 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes);
737 return VMXNET3_SUCCESS;
741 * Configure device link speed and setup link.
742 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
743 * It returns 0 on success.
746 vmxnet3_dev_start(struct rte_eth_dev *dev)
749 struct vmxnet3_hw *hw = dev->data->dev_private;
751 PMD_INIT_FUNC_TRACE();
753 /* Save stats before it is reset by CMD_ACTIVATE */
754 vmxnet3_hw_stats_save(hw);
756 ret = vmxnet3_setup_driver_shared(dev);
757 if (ret != VMXNET3_SUCCESS)
760 /* check if lsc interrupt feature is enabled */
761 if (dev->data->dev_conf.intr_conf.lsc) {
762 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
764 /* Setup interrupt callback */
765 rte_intr_callback_register(&pci_dev->intr_handle,
766 vmxnet3_interrupt_handler, dev);
768 if (rte_intr_enable(&pci_dev->intr_handle) < 0) {
769 PMD_INIT_LOG(ERR, "interrupt enable failed");
774 /* Exchange shared data with device */
775 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
776 VMXNET3_GET_ADDR_LO(hw->sharedPA));
777 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
778 VMXNET3_GET_ADDR_HI(hw->sharedPA));
780 /* Activate device by register write */
781 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
782 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
785 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
789 /* Setup memory region for rx buffers */
790 ret = vmxnet3_dev_setup_memreg(dev);
792 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
793 VMXNET3_CMD_REGISTER_MEMREGS);
794 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
797 "Failed in setup memory region cmd\n");
800 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n");
803 /* Disable interrupts */
804 vmxnet3_disable_intr(hw);
807 * Load RX queues with blank mbufs and update next2fill index for device
808 * Update RxMode of the device
810 ret = vmxnet3_dev_rxtx_init(dev);
811 if (ret != VMXNET3_SUCCESS) {
812 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL");
816 hw->adapter_stopped = FALSE;
818 /* Setting proper Rx Mode and issue Rx Mode Update command */
819 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
821 if (dev->data->dev_conf.intr_conf.lsc) {
822 vmxnet3_enable_intr(hw);
825 * Update link state from device since this won't be
826 * done upon starting with lsc in use. This is done
827 * only after enabling interrupts to avoid any race
828 * where the link state could change without an
829 * interrupt being fired.
831 __vmxnet3_dev_link_update(dev, 0);
834 return VMXNET3_SUCCESS;
838 * Stop device: disable rx and tx functions to allow for reconfiguring.
841 vmxnet3_dev_stop(struct rte_eth_dev *dev)
843 struct rte_eth_link link;
844 struct vmxnet3_hw *hw = dev->data->dev_private;
846 PMD_INIT_FUNC_TRACE();
848 if (hw->adapter_stopped == 1) {
849 PMD_INIT_LOG(DEBUG, "Device already closed.");
853 /* disable interrupts */
854 vmxnet3_disable_intr(hw);
856 if (dev->data->dev_conf.intr_conf.lsc) {
857 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
859 rte_intr_disable(&pci_dev->intr_handle);
861 rte_intr_callback_unregister(&pci_dev->intr_handle,
862 vmxnet3_interrupt_handler, dev);
865 /* quiesce the device first */
866 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
867 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
868 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
870 /* reset the device */
871 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
872 PMD_INIT_LOG(DEBUG, "Device reset.");
873 hw->adapter_stopped = 0;
875 vmxnet3_dev_clear_queues(dev);
877 /* Clear recorded link status */
878 memset(&link, 0, sizeof(link));
879 vmxnet3_dev_atomic_write_link_status(dev, &link);
883 * Reset and stop device.
886 vmxnet3_dev_close(struct rte_eth_dev *dev)
888 struct vmxnet3_hw *hw = dev->data->dev_private;
890 PMD_INIT_FUNC_TRACE();
892 vmxnet3_dev_stop(dev);
893 hw->adapter_stopped = 1;
897 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
898 struct UPT1_TxStats *res)
900 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \
901 ((r)->f = (h)->tqd_start[(i)].stats.f + \
902 (h)->saved_tx_stats[(i)].f)
904 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res);
905 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res);
906 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res);
907 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res);
908 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res);
909 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res);
910 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res);
911 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res);
913 #undef VMXNET3_UPDATE_TX_STAT
917 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
918 struct UPT1_RxStats *res)
920 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \
921 ((r)->f = (h)->rqd_start[(i)].stats.f + \
922 (h)->saved_rx_stats[(i)].f)
924 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res);
925 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res);
926 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res);
927 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res);
928 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res);
929 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res);
930 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res);
931 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res);
933 #undef VMXNET3_UPDATE_RX_STATS
937 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw)
941 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
943 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
945 for (i = 0; i < hw->num_tx_queues; i++)
946 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]);
947 for (i = 0; i < hw->num_rx_queues; i++)
948 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]);
952 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
953 struct rte_eth_xstat_name *xstats_names,
956 unsigned int i, t, count = 0;
957 unsigned int nstats =
958 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
959 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
961 if (!xstats_names || n < nstats)
964 for (i = 0; i < dev->data->nb_rx_queues; i++) {
965 if (!dev->data->rx_queues[i])
968 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
969 snprintf(xstats_names[count].name,
970 sizeof(xstats_names[count].name),
972 vmxnet3_rxq_stat_strings[t].name);
977 for (i = 0; i < dev->data->nb_tx_queues; i++) {
978 if (!dev->data->tx_queues[i])
981 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
982 snprintf(xstats_names[count].name,
983 sizeof(xstats_names[count].name),
985 vmxnet3_txq_stat_strings[t].name);
994 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
997 unsigned int i, t, count = 0;
998 unsigned int nstats =
999 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
1000 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
1005 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1006 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i];
1011 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
1012 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) +
1013 vmxnet3_rxq_stat_strings[t].offset);
1014 xstats[count].id = count;
1019 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1020 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i];
1025 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1026 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) +
1027 vmxnet3_txq_stat_strings[t].offset);
1028 xstats[count].id = count;
1037 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1040 struct vmxnet3_hw *hw = dev->data->dev_private;
1041 struct UPT1_TxStats txStats;
1042 struct UPT1_RxStats rxStats;
1044 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1046 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1047 for (i = 0; i < hw->num_tx_queues; i++) {
1048 vmxnet3_hw_tx_stats_get(hw, i, &txStats);
1050 stats->q_opackets[i] = txStats.ucastPktsTxOK +
1051 txStats.mcastPktsTxOK +
1052 txStats.bcastPktsTxOK;
1054 stats->q_obytes[i] = txStats.ucastBytesTxOK +
1055 txStats.mcastBytesTxOK +
1056 txStats.bcastBytesTxOK;
1058 stats->opackets += stats->q_opackets[i];
1059 stats->obytes += stats->q_obytes[i];
1060 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard;
1063 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
1064 for (i = 0; i < hw->num_rx_queues; i++) {
1065 vmxnet3_hw_rx_stats_get(hw, i, &rxStats);
1067 stats->q_ipackets[i] = rxStats.ucastPktsRxOK +
1068 rxStats.mcastPktsRxOK +
1069 rxStats.bcastPktsRxOK;
1071 stats->q_ibytes[i] = rxStats.ucastBytesRxOK +
1072 rxStats.mcastBytesRxOK +
1073 rxStats.bcastBytesRxOK;
1075 stats->ipackets += stats->q_ipackets[i];
1076 stats->ibytes += stats->q_ibytes[i];
1078 stats->q_errors[i] = rxStats.pktsRxError;
1079 stats->ierrors += rxStats.pktsRxError;
1080 stats->rx_nombuf += rxStats.pktsRxOutOfBuf;
1087 vmxnet3_dev_info_get(struct rte_eth_dev *dev,
1088 struct rte_eth_dev_info *dev_info)
1090 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1092 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
1093 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
1094 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
1095 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
1096 dev_info->speed_capa = ETH_LINK_SPEED_10G;
1097 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
1099 dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOXSUMSCTP;
1100 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
1102 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1103 .nb_max = VMXNET3_RX_RING_MAX_SIZE,
1104 .nb_min = VMXNET3_DEF_RX_RING_SIZE,
1108 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1109 .nb_max = VMXNET3_TX_RING_MAX_SIZE,
1110 .nb_min = VMXNET3_DEF_TX_RING_SIZE,
1112 .nb_seg_max = VMXNET3_TX_MAX_SEG,
1113 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT,
1116 dev_info->rx_offload_capa =
1117 DEV_RX_OFFLOAD_VLAN_STRIP |
1118 DEV_RX_OFFLOAD_UDP_CKSUM |
1119 DEV_RX_OFFLOAD_TCP_CKSUM |
1120 DEV_RX_OFFLOAD_TCP_LRO;
1122 dev_info->tx_offload_capa =
1123 DEV_TX_OFFLOAD_VLAN_INSERT |
1124 DEV_TX_OFFLOAD_TCP_CKSUM |
1125 DEV_TX_OFFLOAD_UDP_CKSUM |
1126 DEV_TX_OFFLOAD_TCP_TSO;
1129 static const uint32_t *
1130 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1132 static const uint32_t ptypes[] = {
1133 RTE_PTYPE_L3_IPV4_EXT,
1138 if (dev->rx_pkt_burst == vmxnet3_recv_pkts)
1144 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1146 struct vmxnet3_hw *hw = dev->data->dev_private;
1148 ether_addr_copy(mac_addr, (struct ether_addr *)(hw->perm_addr));
1149 ether_addr_copy(mac_addr, &dev->data->mac_addrs[0]);
1150 vmxnet3_write_mac(hw, mac_addr->addr_bytes);
1153 /* return 0 means link status changed, -1 means not changed */
1155 __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
1156 __rte_unused int wait_to_complete)
1158 struct vmxnet3_hw *hw = dev->data->dev_private;
1159 struct rte_eth_link old = { 0 }, link;
1162 memset(&link, 0, sizeof(link));
1163 vmxnet3_dev_atomic_read_link_status(dev, &old);
1165 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
1166 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
1169 link.link_status = ETH_LINK_UP;
1170 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1171 link.link_speed = ETH_SPEED_NUM_10G;
1172 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1175 vmxnet3_dev_atomic_write_link_status(dev, &link);
1177 return (old.link_status == link.link_status) ? -1 : 0;
1181 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1183 /* Link status doesn't change for stopped dev */
1184 if (dev->data->dev_started == 0)
1187 return __vmxnet3_dev_link_update(dev, wait_to_complete);
1190 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
1192 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set)
1194 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1197 rxConf->rxMode = rxConf->rxMode | feature;
1199 rxConf->rxMode = rxConf->rxMode & (~feature);
1201 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
1204 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1206 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
1208 struct vmxnet3_hw *hw = dev->data->dev_private;
1209 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1211 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
1212 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
1214 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1215 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1218 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1220 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
1222 struct vmxnet3_hw *hw = dev->data->dev_private;
1223 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1225 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1226 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1228 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1229 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
1230 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1231 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1234 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1236 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
1238 struct vmxnet3_hw *hw = dev->data->dev_private;
1240 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
1243 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1245 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
1247 struct vmxnet3_hw *hw = dev->data->dev_private;
1249 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
1252 /* Enable/disable filter on vlan */
1254 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
1256 struct vmxnet3_hw *hw = dev->data->dev_private;
1257 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1258 uint32_t *vf_table = rxConf->vfTable;
1260 /* save state for restore */
1262 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1264 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1266 /* don't change active filter if in promiscuous mode */
1267 if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
1270 /* set in hardware */
1272 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
1274 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
1276 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1277 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1282 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1284 struct vmxnet3_hw *hw = dev->data->dev_private;
1285 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
1286 uint32_t *vf_table = devRead->rxFilterConf.vfTable;
1288 if (mask & ETH_VLAN_STRIP_MASK) {
1289 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1290 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
1292 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
1294 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1295 VMXNET3_CMD_UPDATE_FEATURE);
1298 if (mask & ETH_VLAN_FILTER_MASK) {
1299 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1300 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1302 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1304 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1305 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1310 vmxnet3_process_events(struct rte_eth_dev *dev)
1312 struct vmxnet3_hw *hw = dev->data->dev_private;
1313 uint32_t events = hw->shared->ecr;
1319 * ECR bits when written with 1b are cleared. Hence write
1320 * events back to ECR so that the bits which were set will be reset.
1322 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
1324 /* Check if link state has changed */
1325 if (events & VMXNET3_ECR_LINK) {
1326 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event");
1327 if (vmxnet3_dev_link_update(dev, 0) == 0)
1328 _rte_eth_dev_callback_process(dev,
1329 RTE_ETH_EVENT_INTR_LSC,
1333 /* Check if there is an error on xmit/recv queues */
1334 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
1335 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1336 VMXNET3_CMD_GET_QUEUE_STATUS);
1338 if (hw->tqd_start->status.stopped)
1339 PMD_DRV_LOG(ERR, "tq error 0x%x",
1340 hw->tqd_start->status.error);
1342 if (hw->rqd_start->status.stopped)
1343 PMD_DRV_LOG(ERR, "rq error 0x%x",
1344 hw->rqd_start->status.error);
1346 /* Reset the device */
1347 /* Have to reset the device */
1350 if (events & VMXNET3_ECR_DIC)
1351 PMD_DRV_LOG(DEBUG, "Device implementation change event.");
1353 if (events & VMXNET3_ECR_DEBUG)
1354 PMD_DRV_LOG(DEBUG, "Debug event generated by device.");
1358 vmxnet3_interrupt_handler(void *param)
1360 struct rte_eth_dev *dev = param;
1361 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1363 vmxnet3_process_events(dev);
1365 if (rte_intr_enable(&pci_dev->intr_handle) < 0)
1366 PMD_DRV_LOG(ERR, "interrupt enable failed");
1369 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd);
1370 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map);
1371 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci");