4 * Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #ifndef APP_MAX_SOCKETS
40 #define APP_MAX_SOCKETS 2
43 #ifndef APP_MAX_LCORES
44 #define APP_MAX_LCORES RTE_MAX_LCORE
47 #ifndef APP_MAX_NIC_PORTS
48 #define APP_MAX_NIC_PORTS RTE_MAX_ETHPORTS
51 #ifndef APP_MAX_RX_QUEUES_PER_NIC_PORT
52 #define APP_MAX_RX_QUEUES_PER_NIC_PORT 128
55 #ifndef APP_MAX_TX_QUEUES_PER_NIC_PORT
56 #define APP_MAX_TX_QUEUES_PER_NIC_PORT 128
59 #ifndef APP_MAX_IO_LCORES
60 #define APP_MAX_IO_LCORES 16
62 #if (APP_MAX_IO_LCORES > APP_MAX_LCORES)
63 #error "APP_MAX_IO_LCORES is too big"
66 #ifndef APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE
67 #define APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE 16
70 #ifndef APP_MAX_NIC_TX_PORTS_PER_IO_LCORE
71 #define APP_MAX_NIC_TX_PORTS_PER_IO_LCORE 16
73 #if (APP_MAX_NIC_TX_PORTS_PER_IO_LCORE > APP_MAX_NIC_PORTS)
74 #error "APP_MAX_NIC_TX_PORTS_PER_IO_LCORE too big"
77 #ifndef APP_MAX_WORKER_LCORES
78 #define APP_MAX_WORKER_LCORES 16
80 #if (APP_MAX_WORKER_LCORES > APP_MAX_LCORES)
81 #error "APP_MAX_WORKER_LCORES is too big"
86 #ifndef APP_DEFAULT_MBUF_SIZE
87 #define APP_DEFAULT_MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)
90 #ifndef APP_DEFAULT_MEMPOOL_BUFFERS
91 #define APP_DEFAULT_MEMPOOL_BUFFERS 8192
94 #ifndef APP_DEFAULT_MEMPOOL_CACHE_SIZE
95 #define APP_DEFAULT_MEMPOOL_CACHE_SIZE 256
99 #ifndef APP_MAX_LPM_RULES
100 #define APP_MAX_LPM_RULES 1024
104 #ifndef APP_DEFAULT_NIC_RX_RING_SIZE
105 #define APP_DEFAULT_NIC_RX_RING_SIZE 1024
109 * RX and TX Prefetch, Host, and Write-back threshold values should be
110 * carefully set for optimal performance. Consult the network
111 * controller's datasheet and supporting DPDK documentation for guidance
112 * on how these parameters should be set.
114 #ifndef APP_DEFAULT_NIC_RX_PTHRESH
115 #define APP_DEFAULT_NIC_RX_PTHRESH 8
118 #ifndef APP_DEFAULT_NIC_RX_HTHRESH
119 #define APP_DEFAULT_NIC_RX_HTHRESH 8
122 #ifndef APP_DEFAULT_NIC_RX_WTHRESH
123 #define APP_DEFAULT_NIC_RX_WTHRESH 4
126 #ifndef APP_DEFAULT_NIC_RX_FREE_THRESH
127 #define APP_DEFAULT_NIC_RX_FREE_THRESH 64
131 #ifndef APP_DEFAULT_NIC_TX_RING_SIZE
132 #define APP_DEFAULT_NIC_TX_RING_SIZE 1024
136 * These default values are optimized for use with the Intel(R) 82599 10 GbE
137 * Controller and the DPDK ixgbe PMD. Consider using other values for other
138 * network controllers and/or network drivers.
140 #ifndef APP_DEFAULT_NIC_TX_PTHRESH
141 #define APP_DEFAULT_NIC_TX_PTHRESH 36
144 #ifndef APP_DEFAULT_NIC_TX_HTHRESH
145 #define APP_DEFAULT_NIC_TX_HTHRESH 0
148 #ifndef APP_DEFAULT_NIC_TX_WTHRESH
149 #define APP_DEFAULT_NIC_TX_WTHRESH 0
152 #ifndef APP_DEFAULT_NIC_TX_FREE_THRESH
153 #define APP_DEFAULT_NIC_TX_FREE_THRESH 0
156 #ifndef APP_DEFAULT_NIC_TX_RS_THRESH
157 #define APP_DEFAULT_NIC_TX_RS_THRESH 0
161 #ifndef APP_DEFAULT_RING_RX_SIZE
162 #define APP_DEFAULT_RING_RX_SIZE 1024
165 #ifndef APP_DEFAULT_RING_TX_SIZE
166 #define APP_DEFAULT_RING_TX_SIZE 1024
170 #ifndef APP_MBUF_ARRAY_SIZE
171 #define APP_MBUF_ARRAY_SIZE 512
174 #ifndef APP_DEFAULT_BURST_SIZE_IO_RX_READ
175 #define APP_DEFAULT_BURST_SIZE_IO_RX_READ 144
177 #if (APP_DEFAULT_BURST_SIZE_IO_RX_READ > APP_MBUF_ARRAY_SIZE)
178 #error "APP_DEFAULT_BURST_SIZE_IO_RX_READ is too big"
181 #ifndef APP_DEFAULT_BURST_SIZE_IO_RX_WRITE
182 #define APP_DEFAULT_BURST_SIZE_IO_RX_WRITE 144
184 #if (APP_DEFAULT_BURST_SIZE_IO_RX_WRITE > APP_MBUF_ARRAY_SIZE)
185 #error "APP_DEFAULT_BURST_SIZE_IO_RX_WRITE is too big"
188 #ifndef APP_DEFAULT_BURST_SIZE_IO_TX_READ
189 #define APP_DEFAULT_BURST_SIZE_IO_TX_READ 144
191 #if (APP_DEFAULT_BURST_SIZE_IO_TX_READ > APP_MBUF_ARRAY_SIZE)
192 #error "APP_DEFAULT_BURST_SIZE_IO_TX_READ is too big"
195 #ifndef APP_DEFAULT_BURST_SIZE_IO_TX_WRITE
196 #define APP_DEFAULT_BURST_SIZE_IO_TX_WRITE 144
198 #if (APP_DEFAULT_BURST_SIZE_IO_TX_WRITE > APP_MBUF_ARRAY_SIZE)
199 #error "APP_DEFAULT_BURST_SIZE_IO_TX_WRITE is too big"
202 #ifndef APP_DEFAULT_BURST_SIZE_WORKER_READ
203 #define APP_DEFAULT_BURST_SIZE_WORKER_READ 144
205 #if ((2 * APP_DEFAULT_BURST_SIZE_WORKER_READ) > APP_MBUF_ARRAY_SIZE)
206 #error "APP_DEFAULT_BURST_SIZE_WORKER_READ is too big"
209 #ifndef APP_DEFAULT_BURST_SIZE_WORKER_WRITE
210 #define APP_DEFAULT_BURST_SIZE_WORKER_WRITE 144
212 #if (APP_DEFAULT_BURST_SIZE_WORKER_WRITE > APP_MBUF_ARRAY_SIZE)
213 #error "APP_DEFAULT_BURST_SIZE_WORKER_WRITE is too big"
216 /* Load balancing logic */
217 #ifndef APP_DEFAULT_IO_RX_LB_POS
218 #define APP_DEFAULT_IO_RX_LB_POS 29
220 #if (APP_DEFAULT_IO_RX_LB_POS >= 64)
221 #error "APP_DEFAULT_IO_RX_LB_POS is too big"
224 struct app_mbuf_array {
225 struct rte_mbuf *array[APP_MBUF_ARRAY_SIZE];
229 enum app_lcore_type {
230 e_APP_LCORE_DISABLED = 0,
235 struct app_lcore_params_io {
242 } nic_queues[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
243 uint32_t n_nic_queues;
246 struct rte_ring *rings[APP_MAX_WORKER_LCORES];
249 /* Internal buffers */
250 struct app_mbuf_array mbuf_in;
251 struct app_mbuf_array mbuf_out[APP_MAX_WORKER_LCORES];
252 uint8_t mbuf_out_flush[APP_MAX_WORKER_LCORES];
255 uint32_t nic_queues_count[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
256 uint32_t nic_queues_iters[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
257 uint32_t rings_count[APP_MAX_WORKER_LCORES];
258 uint32_t rings_iters[APP_MAX_WORKER_LCORES];
264 struct rte_ring *rings[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
267 uint8_t nic_ports[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
268 uint32_t n_nic_ports;
270 /* Internal buffers */
271 struct app_mbuf_array mbuf_out[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
272 uint8_t mbuf_out_flush[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
275 uint32_t rings_count[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
276 uint32_t rings_iters[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
277 uint32_t nic_ports_count[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
278 uint32_t nic_ports_iters[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
282 struct app_lcore_params_worker {
284 struct rte_ring *rings_in[APP_MAX_IO_LCORES];
286 struct rte_ring *rings_out[APP_MAX_NIC_PORTS];
289 struct rte_lpm *lpm_table;
292 /* Internal buffers */
293 struct app_mbuf_array mbuf_in;
294 struct app_mbuf_array mbuf_out[APP_MAX_NIC_PORTS];
295 uint8_t mbuf_out_flush[APP_MAX_NIC_PORTS];
298 uint32_t rings_in_count[APP_MAX_IO_LCORES];
299 uint32_t rings_in_iters[APP_MAX_IO_LCORES];
300 uint32_t rings_out_count[APP_MAX_NIC_PORTS];
301 uint32_t rings_out_iters[APP_MAX_NIC_PORTS];
304 struct app_lcore_params {
306 struct app_lcore_params_io io;
307 struct app_lcore_params_worker worker;
309 enum app_lcore_type type;
310 struct rte_mempool *pool;
311 } __rte_cache_aligned;
313 struct app_lpm_rule {
321 struct app_lcore_params lcore_params[APP_MAX_LCORES];
324 uint8_t nic_rx_queue_mask[APP_MAX_NIC_PORTS][APP_MAX_RX_QUEUES_PER_NIC_PORT];
325 uint8_t nic_tx_port_mask[APP_MAX_NIC_PORTS];
328 struct rte_mempool *pools[APP_MAX_SOCKETS];
331 struct rte_lpm *lpm_tables[APP_MAX_SOCKETS];
332 struct app_lpm_rule lpm_rules[APP_MAX_LPM_RULES];
333 uint32_t n_lpm_rules;
336 uint32_t nic_rx_ring_size;
337 uint32_t nic_tx_ring_size;
338 uint32_t ring_rx_size;
339 uint32_t ring_tx_size;
342 uint32_t burst_size_io_rx_read;
343 uint32_t burst_size_io_rx_write;
344 uint32_t burst_size_io_tx_read;
345 uint32_t burst_size_io_tx_write;
346 uint32_t burst_size_worker_read;
347 uint32_t burst_size_worker_write;
351 } __rte_cache_aligned;
353 extern struct app_params app;
355 int app_parse_args(int argc, char **argv);
356 void app_print_usage(void);
358 int app_lcore_main_loop(void *arg);
360 int app_get_nic_rx_queues_per_port(uint8_t port);
361 int app_get_lcore_for_nic_rx(uint8_t port, uint8_t queue, uint32_t *lcore_out);
362 int app_get_lcore_for_nic_tx(uint8_t port, uint32_t *lcore_out);
363 int app_is_socket_used(uint32_t socket);
364 uint32_t app_get_lcores_io_rx(void);
365 uint32_t app_get_lcores_worker(void);
366 void app_print_params(void);
368 #ifdef RTE_EXEC_ENV_BAREMETAL
374 int MAIN(int argc, char **argv);
376 #endif /* _MAIN_H_ */