lib/librte_eal/common/include/arch/x86/rte_atomic_32.h

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * Inspired from FreeBSD src/sys/i386/include/atomic.h
  36  * Copyright (c) 1998 Doug Rabson
  37  * All rights reserved.
  38  */
  39
  40 #ifndef _RTE_ATOMIC_I686_H_
  41 #define _RTE_ATOMIC_I686_H_
  42
  43 #include <rte_common.h>
  44
  45 /*------------------------- 64 bit atomic operations -------------------------*/
  46
  47 #ifndef RTE_FORCE_INTRINSICS
  48 static inline int
  49 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
  50 {
  51         uint8_t res;
  52         RTE_STD_C11
  53         union {
  54                 struct {
  55                         uint32_t l32;
  56                         uint32_t h32;
  57                 };
  58                 uint64_t u64;
  59         } _exp, _src;
  60
  61         _exp.u64 = exp;
  62         _src.u64 = src;
  63
  64 #ifndef __PIC__
  65     asm volatile (
  66             MPLOCKED
  67             "cmpxchg8b (%[dst]);"
  68             "setz %[res];"
  69             : [res] "=a" (res)      /* result in eax */
  70             : [dst] "S" (dst),      /* esi */
  71              "b" (_src.l32),       /* ebx */
  72              "c" (_src.h32),       /* ecx */
  73              "a" (_exp.l32),       /* eax */
  74              "d" (_exp.h32)        /* edx */
  75                         : "memory" );           /* no-clobber list */
  76 #else
  77         asm volatile (
  78             "mov %%ebx, %%edi\n"
  79                         MPLOCKED
  80                         "cmpxchg8b (%[dst]);"
  81                         "setz %[res];"
  82             "xchgl %%ebx, %%edi;\n"
  83                         : [res] "=a" (res)      /* result in eax */
  84                         : [dst] "S" (dst),      /* esi */
  85                           "D" (_src.l32),       /* ebx */
  86                           "c" (_src.h32),       /* ecx */
  87                           "a" (_exp.l32),       /* eax */
  88                           "d" (_exp.h32)        /* edx */
  89                         : "memory" );           /* no-clobber list */
  90 #endif
  91
  92         return res;
  93 }
  94
  95 static inline void
  96 rte_atomic64_init(rte_atomic64_t *v)
  97 {
  98         int success = 0;
  99         uint64_t tmp;
 100
 101         while (success == 0) {
 102                 tmp = v->cnt;
 103                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 104                                               tmp, 0);
 105         }
 106 }
 107
 108 static inline int64_t
 109 rte_atomic64_read(rte_atomic64_t *v)
 110 {
 111         int success = 0;
 112         uint64_t tmp;
 113
 114         while (success == 0) {
 115                 tmp = v->cnt;
 116                 /* replace the value by itself */
 117                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 118                                               tmp, tmp);
 119         }
 120         return tmp;
 121 }
 122
 123 static inline void
 124 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
 125 {
 126         int success = 0;
 127         uint64_t tmp;
 128
 129         while (success == 0) {
 130                 tmp = v->cnt;
 131                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 132                                               tmp, new_value);
 133         }
 134 }
 135
 136 static inline void
 137 rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
 138 {
 139         int success = 0;
 140         uint64_t tmp;
 141
 142         while (success == 0) {
 143                 tmp = v->cnt;
 144                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 145                                               tmp, tmp + inc);
 146         }
 147 }
 148
 149 static inline void
 150 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
 151 {
 152         int success = 0;
 153         uint64_t tmp;
 154
 155         while (success == 0) {
 156                 tmp = v->cnt;
 157                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 158                                               tmp, tmp - dec);
 159         }
 160 }
 161
 162 static inline void
 163 rte_atomic64_inc(rte_atomic64_t *v)
 164 {
 165         rte_atomic64_add(v, 1);
 166 }
 167
 168 static inline void
 169 rte_atomic64_dec(rte_atomic64_t *v)
 170 {
 171         rte_atomic64_sub(v, 1);
 172 }
 173
 174 static inline int64_t
 175 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
 176 {
 177         int success = 0;
 178         uint64_t tmp;
 179
 180         while (success == 0) {
 181                 tmp = v->cnt;
 182                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 183                                               tmp, tmp + inc);
 184         }
 185
 186         return tmp + inc;
 187 }
 188
 189 static inline int64_t
 190 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
 191 {
 192         int success = 0;
 193         uint64_t tmp;
 194
 195         while (success == 0) {
 196                 tmp = v->cnt;
 197                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 198                                               tmp, tmp - dec);
 199         }
 200
 201         return tmp - dec;
 202 }
 203
 204 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
 205 {
 206         return rte_atomic64_add_return(v, 1) == 0;
 207 }
 208
 209 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
 210 {
 211         return rte_atomic64_sub_return(v, 1) == 0;
 212 }
 213
 214 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
 215 {
 216         return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
 217 }
 218
 219 static inline void rte_atomic64_clear(rte_atomic64_t *v)
 220 {
 221         rte_atomic64_set(v, 0);
 222 }
 223 #endif
 224
 225 #endif /* _RTE_ATOMIC_I686_H_ */