lib/librte_pmd_e1000/e1000/e1000_82575.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /*
  35  * 82575EB Gigabit Network Connection
  36  * 82575EB Gigabit Backplane Connection
  37  * 82575GB Gigabit Network Connection
  38  * 82576 Gigabit Network Connection
  39  * 82576 Quad Port Gigabit Mezzanine Adapter
  40  * 82580 Gigabit Network Connection
  41  * I350 Gigabit Network Connection
  42  */
  43
  44 #include "e1000_api.h"
  45 #include "e1000_i210.h"
  46
  47 STATIC s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  48 STATIC s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  49 STATIC s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
  51 STATIC s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
  53 STATIC s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  54 STATIC s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
  55 STATIC s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  56 STATIC s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  57                                          u16 *duplex);
  58 STATIC s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  59 STATIC s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  60                                            u16 *data);
  61 STATIC s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  62 STATIC s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  63 STATIC s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  64                                      u32 offset, u16 *data);
  65 STATIC s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  66                                       u32 offset, u16 data);
  67 STATIC s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  68                                           bool active);
  69 STATIC s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  70                                           bool active);
  71 STATIC s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  72                                           bool active);
  73 STATIC s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  74 STATIC s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  75 STATIC s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  76 STATIC s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  77 STATIC s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  78 STATIC s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  79                                             u32 offset, u16 data);
  80 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  81 STATIC s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  82 STATIC s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  83                                                  u16 *speed, u16 *duplex);
  84 STATIC s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  85 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  86 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  87 STATIC s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  88 STATIC s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  89 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  90 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  91 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  92 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  93 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  94 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  95 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  96 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  97 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  98                                                  u16 offset);
  99 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
 100                                                    u16 offset);
 101 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 102 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
 103 STATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
 104 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
 105
 106 STATIC void e1000_i2c_start(struct e1000_hw *hw);
 107 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
 108 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
 109 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
 110 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
 111 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
 112 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
 113 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 114 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 115 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
 116 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
 117
 118 STATIC const u16 e1000_82580_rxpbs_table[] = {
 119         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 120 #define E1000_82580_RXPBS_TABLE_SIZE \
 121         (sizeof(e1000_82580_rxpbs_table) / \
 122          sizeof(e1000_82580_rxpbs_table[0]))
 123
 124
 125 /**
 126  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 127  *  @hw: pointer to the HW structure
 128  *
 129  *  Called to determine if the I2C pins are being used for I2C or as an
 130  *  external MDIO interface since the two options are mutually exclusive.
 131  **/
 132 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 133 {
 134         u32 reg = 0;
 135         bool ext_mdio = false;
 136
 137         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 138
 139         switch (hw->mac.type) {
 140         case e1000_82575:
 141         case e1000_82576:
 142                 reg = E1000_READ_REG(hw, E1000_MDIC);
 143                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 144                 break;
 145         case e1000_82580:
 146         case e1000_i350:
 147         case e1000_i354:
 148         case e1000_i210:
 149         case e1000_i211:
 150                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 151                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 152                 break;
 153         default:
 154                 break;
 155         }
 156         return ext_mdio;
 157 }
 158
 159 /**
 160  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 161  *  @hw: pointer to the HW structure
 162  **/
 163 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 164 {
 165         struct e1000_phy_info *phy = &hw->phy;
 166         s32 ret_val = E1000_SUCCESS;
 167         u32 ctrl_ext;
 168
 169         DEBUGFUNC("e1000_init_phy_params_82575");
 170
 171         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 172         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 173
 174         if (hw->phy.media_type != e1000_media_type_copper) {
 175                 phy->type = e1000_phy_none;
 176                 goto out;
 177         }
 178
 179         phy->ops.power_up   = e1000_power_up_phy_copper;
 180         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 181
 182         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 183         phy->reset_delay_us     = 100;
 184
 185         phy->ops.acquire        = e1000_acquire_phy_82575;
 186         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 187         phy->ops.commit         = e1000_phy_sw_reset_generic;
 188         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 189         phy->ops.release        = e1000_release_phy_82575;
 190
 191         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 192
 193         if (e1000_sgmii_active_82575(hw)) {
 194                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 195                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 196         } else {
 197                 phy->ops.reset = e1000_phy_hw_reset_generic;
 198                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 199         }
 200
 201         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 202         e1000_reset_mdicnfg_82580(hw);
 203
 204         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 205                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 206                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 207         } else {
 208                 switch (hw->mac.type) {
 209                 case e1000_82580:
 210                 case e1000_i350:
 211                 case e1000_i354:
 212                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 213                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 214                         break;
 215                 case e1000_i210:
 216                 case e1000_i211:
 217                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 218                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 219                         break;
 220                 default:
 221                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 222                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 223                 }
 224         }
 225
 226         /* Set phy->phy_addr and phy->id. */
 227         ret_val = e1000_get_phy_id_82575(hw);
 228
 229         /* Verify phy id and set remaining function pointers */
 230         switch (phy->id) {
 231         case M88E1543_E_PHY_ID:
 232         case M88E1512_E_PHY_ID:
 233         case I347AT4_E_PHY_ID:
 234         case M88E1112_E_PHY_ID:
 235         case M88E1340M_E_PHY_ID:
 236         case M88E1111_I_PHY_ID:
 237                 phy->type               = e1000_phy_m88;
 238                 phy->ops.check_polarity = e1000_check_polarity_m88;
 239                 phy->ops.get_info       = e1000_get_phy_info_m88;
 240                 if (phy->id == I347AT4_E_PHY_ID ||
 241                     phy->id == M88E1112_E_PHY_ID ||
 242                     phy->id == M88E1340M_E_PHY_ID)
 243                         phy->ops.get_cable_length =
 244                                          e1000_get_cable_length_m88_gen2;
 245                 else if (phy->id == M88E1543_E_PHY_ID ||
 246                          phy->id == M88E1512_E_PHY_ID)
 247                         phy->ops.get_cable_length =
 248                                          e1000_get_cable_length_m88_gen2;
 249                 else
 250                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 251                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 252                 /* Check if this PHY is confgured for media swap. */
 253                 if (phy->id == M88E1112_E_PHY_ID) {
 254                         u16 data;
 255
 256                         ret_val = phy->ops.write_reg(hw,
 257                                                      E1000_M88E1112_PAGE_ADDR,
 258                                                      2);
 259                         if (ret_val)
 260                                 goto out;
 261
 262                         ret_val = phy->ops.read_reg(hw,
 263                                                     E1000_M88E1112_MAC_CTRL_1,
 264                                                     &data);
 265                         if (ret_val)
 266                                 goto out;
 267
 268                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 269                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 270                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 271                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 272                                 hw->mac.ops.check_for_link =
 273                                                 e1000_check_for_link_media_swap;
 274                 }
 275                 if (phy->id == M88E1512_E_PHY_ID) {
 276                         ret_val = e1000_initialize_M88E1512_phy(hw);
 277                         if (ret_val)
 278                                 goto out;
 279                 }
 280                 break;
 281         case IGP03E1000_E_PHY_ID:
 282         case IGP04E1000_E_PHY_ID:
 283                 phy->type = e1000_phy_igp_3;
 284                 phy->ops.check_polarity = e1000_check_polarity_igp;
 285                 phy->ops.get_info = e1000_get_phy_info_igp;
 286                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 287                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 288                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 289                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 290                 break;
 291         case I82580_I_PHY_ID:
 292         case I350_I_PHY_ID:
 293                 phy->type = e1000_phy_82580;
 294                 phy->ops.check_polarity = e1000_check_polarity_82577;
 295                 phy->ops.force_speed_duplex =
 296                                          e1000_phy_force_speed_duplex_82577;
 297                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 298                 phy->ops.get_info = e1000_get_phy_info_82577;
 299                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 300                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 301                 break;
 302         case I210_I_PHY_ID:
 303                 phy->type               = e1000_phy_i210;
 304                 phy->ops.check_polarity = e1000_check_polarity_m88;
 305                 phy->ops.get_info       = e1000_get_phy_info_m88;
 306                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 307                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 308                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 309                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 310                 break;
 311         default:
 312                 ret_val = -E1000_ERR_PHY;
 313                 goto out;
 314         }
 315
 316 out:
 317         return ret_val;
 318 }
 319
 320 /**
 321  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 322  *  @hw: pointer to the HW structure
 323  **/
 324 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 325 {
 326         struct e1000_nvm_info *nvm = &hw->nvm;
 327         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 328         u16 size;
 329
 330         DEBUGFUNC("e1000_init_nvm_params_82575");
 331
 332         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 333                      E1000_EECD_SIZE_EX_SHIFT);
 334         /*
 335          * Added to a constant, "size" becomes the left-shift value
 336          * for setting word_size.
 337          */
 338         size += NVM_WORD_SIZE_BASE_SHIFT;
 339
 340         /* Just in case size is out of range, cap it to the largest
 341          * EEPROM size supported
 342          */
 343         if (size > 15)
 344                 size = 15;
 345
 346         nvm->word_size = 1 << size;
 347         if (hw->mac.type < e1000_i210) {
 348                 nvm->opcode_bits = 8;
 349                 nvm->delay_usec = 1;
 350
 351                 switch (nvm->override) {
 352                 case e1000_nvm_override_spi_large:
 353                         nvm->page_size = 32;
 354                         nvm->address_bits = 16;
 355                         break;
 356                 case e1000_nvm_override_spi_small:
 357                         nvm->page_size = 8;
 358                         nvm->address_bits = 8;
 359                         break;
 360                 default:
 361                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 362                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 363                                             16 : 8;
 364                         break;
 365                 }
 366                 if (nvm->word_size == (1 << 15))
 367                         nvm->page_size = 128;
 368
 369                 nvm->type = e1000_nvm_eeprom_spi;
 370         } else {
 371                 nvm->type = e1000_nvm_flash_hw;
 372         }
 373
 374         /* Function Pointers */
 375         nvm->ops.acquire = e1000_acquire_nvm_82575;
 376         nvm->ops.release = e1000_release_nvm_82575;
 377         if (nvm->word_size < (1 << 15))
 378                 nvm->ops.read = e1000_read_nvm_eerd;
 379         else
 380                 nvm->ops.read = e1000_read_nvm_spi;
 381
 382         nvm->ops.write = e1000_write_nvm_spi;
 383         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 384         nvm->ops.update = e1000_update_nvm_checksum_generic;
 385         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 386
 387         /* override generic family function pointers for specific descendants */
 388         switch (hw->mac.type) {
 389         case e1000_82580:
 390                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 391                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 392                 break;
 393         case e1000_i350:
 394         case e1000_i354:
 395                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 396                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 397                 break;
 398         default:
 399                 break;
 400         }
 401
 402         return E1000_SUCCESS;
 403 }
 404
 405 /**
 406  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 407  *  @hw: pointer to the HW structure
 408  **/
 409 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 410 {
 411         struct e1000_mac_info *mac = &hw->mac;
 412         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 413
 414         DEBUGFUNC("e1000_init_mac_params_82575");
 415
 416         /* Derives media type */
 417         e1000_get_media_type_82575(hw);
 418         /* Set mta register count */
 419         mac->mta_reg_count = 128;
 420         /* Set uta register count */
 421         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 422         /* Set rar entry count */
 423         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 424         if (mac->type == e1000_82576)
 425                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 426         if (mac->type == e1000_82580)
 427                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 428         if (mac->type == e1000_i350 || mac->type == e1000_i354)
 429                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 430
 431         /* Enable EEE default settings for EEE supported devices */
 432         if (mac->type >= e1000_i350)
 433                 dev_spec->eee_disable = false;
 434
 435         /* Allow a single clear of the SW semaphore on I210 and newer */
 436         if (mac->type >= e1000_i210)
 437                 dev_spec->clear_semaphore_once = true;
 438
 439         /* Set if part includes ASF firmware */
 440         mac->asf_firmware_present = true;
 441         /* FWSM register */
 442         mac->has_fwsm = true;
 443         /* ARC supported; valid only if manageability features are enabled. */
 444         mac->arc_subsystem_valid =
 445                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 446
 447         /* Function pointers */
 448
 449         /* bus type/speed/width */
 450         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 451         /* reset */
 452         if (mac->type >= e1000_82580)
 453                 mac->ops.reset_hw = e1000_reset_hw_82580;
 454         else
 455         mac->ops.reset_hw = e1000_reset_hw_82575;
 456         /* hw initialization */
 457         if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
 458                 mac->ops.init_hw = e1000_init_hw_i210;
 459         else
 460         mac->ops.init_hw = e1000_init_hw_82575;
 461         /* link setup */
 462         mac->ops.setup_link = e1000_setup_link_generic;
 463         /* physical interface link setup */
 464         mac->ops.setup_physical_interface =
 465                 (hw->phy.media_type == e1000_media_type_copper)
 466                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 467         /* physical interface shutdown */
 468         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 469         /* physical interface power up */
 470         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 471         /* check for link */
 472         mac->ops.check_for_link = e1000_check_for_link_82575;
 473         /* read mac address */
 474         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 475         /* configure collision distance */
 476         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 477         /* multicast address update */
 478         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 479         if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
 480                 /* writing VFTA */
 481                 mac->ops.write_vfta = e1000_write_vfta_i350;
 482                 /* clearing VFTA */
 483                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 484         } else {
 485                 /* writing VFTA */
 486                 mac->ops.write_vfta = e1000_write_vfta_generic;
 487                 /* clearing VFTA */
 488                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 489         }
 490         if (hw->mac.type >= e1000_82580)
 491                 mac->ops.validate_mdi_setting =
 492                                 e1000_validate_mdi_setting_crossover_generic;
 493         /* ID LED init */
 494         mac->ops.id_led_init = e1000_id_led_init_generic;
 495         /* blink LED */
 496         mac->ops.blink_led = e1000_blink_led_generic;
 497         /* setup LED */
 498         mac->ops.setup_led = e1000_setup_led_generic;
 499         /* cleanup LED */
 500         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 501         /* turn on/off LED */
 502         mac->ops.led_on = e1000_led_on_generic;
 503         mac->ops.led_off = e1000_led_off_generic;
 504         /* clear hardware counters */
 505         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 506         /* link info */
 507         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 508         /* acquire SW_FW sync */
 509         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 510         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 511         if (mac->type >= e1000_i210) {
 512                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 513                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 514         }
 515
 516         /* set lan id for port to determine which phy lock to use */
 517         hw->mac.ops.set_lan_id(hw);
 518
 519         return E1000_SUCCESS;
 520 }
 521
 522 /**
 523  *  e1000_init_function_pointers_82575 - Init func ptrs.
 524  *  @hw: pointer to the HW structure
 525  *
 526  *  Called to initialize all function pointers and parameters.
 527  **/
 528 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 529 {
 530         DEBUGFUNC("e1000_init_function_pointers_82575");
 531
 532         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 533         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 534         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 535         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 536 }
 537
 538 /**
 539  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 540  *  @hw: pointer to the HW structure
 541  *
 542  *  Acquire access rights to the correct PHY.
 543  **/
 544 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 545 {
 546         u16 mask = E1000_SWFW_PHY0_SM;
 547
 548         DEBUGFUNC("e1000_acquire_phy_82575");
 549
 550         if (hw->bus.func == E1000_FUNC_1)
 551                 mask = E1000_SWFW_PHY1_SM;
 552         else if (hw->bus.func == E1000_FUNC_2)
 553                 mask = E1000_SWFW_PHY2_SM;
 554         else if (hw->bus.func == E1000_FUNC_3)
 555                 mask = E1000_SWFW_PHY3_SM;
 556
 557         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 558 }
 559
 560 /**
 561  *  e1000_release_phy_82575 - Release rights to access PHY
 562  *  @hw: pointer to the HW structure
 563  *
 564  *  A wrapper to release access rights to the correct PHY.
 565  **/
 566 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
 567 {
 568         u16 mask = E1000_SWFW_PHY0_SM;
 569
 570         DEBUGFUNC("e1000_release_phy_82575");
 571
 572         if (hw->bus.func == E1000_FUNC_1)
 573                 mask = E1000_SWFW_PHY1_SM;
 574         else if (hw->bus.func == E1000_FUNC_2)
 575                 mask = E1000_SWFW_PHY2_SM;
 576         else if (hw->bus.func == E1000_FUNC_3)
 577                 mask = E1000_SWFW_PHY3_SM;
 578
 579         hw->mac.ops.release_swfw_sync(hw, mask);
 580 }
 581
 582 /**
 583  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 584  *  @hw: pointer to the HW structure
 585  *  @offset: register offset to be read
 586  *  @data: pointer to the read data
 587  *
 588  *  Reads the PHY register at offset using the serial gigabit media independent
 589  *  interface and stores the retrieved information in data.
 590  **/
 591 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 592                                           u16 *data)
 593 {
 594         s32 ret_val = -E1000_ERR_PARAM;
 595
 596         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 597
 598         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 599                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 600                 goto out;
 601         }
 602
 603         ret_val = hw->phy.ops.acquire(hw);
 604         if (ret_val)
 605                 goto out;
 606
 607         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 608
 609         hw->phy.ops.release(hw);
 610
 611 out:
 612         return ret_val;
 613 }
 614
 615 /**
 616  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 617  *  @hw: pointer to the HW structure
 618  *  @offset: register offset to write to
 619  *  @data: data to write at register offset
 620  *
 621  *  Writes the data to PHY register at the offset using the serial gigabit
 622  *  media independent interface.
 623  **/
 624 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 625                                            u16 data)
 626 {
 627         s32 ret_val = -E1000_ERR_PARAM;
 628
 629         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 630
 631         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 632                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 633                 goto out;
 634         }
 635
 636         ret_val = hw->phy.ops.acquire(hw);
 637         if (ret_val)
 638                 goto out;
 639
 640         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 641
 642         hw->phy.ops.release(hw);
 643
 644 out:
 645         return ret_val;
 646 }
 647
 648 /**
 649  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 650  *  @hw: pointer to the HW structure
 651  *
 652  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 653  *  sgmi interface.
 654  **/
 655 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 656 {
 657         struct e1000_phy_info *phy = &hw->phy;
 658         s32  ret_val = E1000_SUCCESS;
 659         u16 phy_id;
 660         u32 ctrl_ext;
 661         u32 mdic;
 662
 663         DEBUGFUNC("e1000_get_phy_id_82575");
 664
 665         /* some i354 devices need an extra read for phy id */
 666         if (hw->mac.type == e1000_i354)
 667                 e1000_get_phy_id(hw);
 668
 669         /*
 670          * For SGMII PHYs, we try the list of possible addresses until
 671          * we find one that works.  For non-SGMII PHYs
 672          * (e.g. integrated copper PHYs), an address of 1 should
 673          * work.  The result of this function should mean phy->phy_addr
 674          * and phy->id are set correctly.
 675          */
 676         if (!e1000_sgmii_active_82575(hw)) {
 677                 phy->addr = 1;
 678                 ret_val = e1000_get_phy_id(hw);
 679                 goto out;
 680         }
 681
 682         if (e1000_sgmii_uses_mdio_82575(hw)) {
 683                 switch (hw->mac.type) {
 684                 case e1000_82575:
 685                 case e1000_82576:
 686                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 687                         mdic &= E1000_MDIC_PHY_MASK;
 688                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 689                         break;
 690                 case e1000_82580:
 691                 case e1000_i350:
 692                 case e1000_i354:
 693                 case e1000_i210:
 694                 case e1000_i211:
 695                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 696                         mdic &= E1000_MDICNFG_PHY_MASK;
 697                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 698                         break;
 699                 default:
 700                         ret_val = -E1000_ERR_PHY;
 701                         goto out;
 702                         break;
 703                 }
 704                 ret_val = e1000_get_phy_id(hw);
 705                 goto out;
 706         }
 707
 708         /* Power on sgmii phy if it is disabled */
 709         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 710         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 711                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 712         E1000_WRITE_FLUSH(hw);
 713         msec_delay(300);
 714
 715         /*
 716          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 717          * Therefore, we need to test 1-7
 718          */
 719         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 720                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 721                 if (ret_val == E1000_SUCCESS) {
 722                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 723                                   phy_id, phy->addr);
 724                         /*
 725                          * At the time of this writing, The M88 part is
 726                          * the only supported SGMII PHY product.
 727                          */
 728                         if (phy_id == M88_VENDOR)
 729                                 break;
 730                 } else {
 731                         DEBUGOUT1("PHY address %u was unreadable\n",
 732                                   phy->addr);
 733                 }
 734         }
 735
 736         /* A valid PHY type couldn't be found. */
 737         if (phy->addr == 8) {
 738                 phy->addr = 0;
 739                 ret_val = -E1000_ERR_PHY;
 740         } else {
 741                 ret_val = e1000_get_phy_id(hw);
 742         }
 743
 744         /* restore previous sfp cage power state */
 745         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 746
 747 out:
 748         return ret_val;
 749 }
 750
 751 /**
 752  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 753  *  @hw: pointer to the HW structure
 754  *
 755  *  Resets the PHY using the serial gigabit media independent interface.
 756  **/
 757 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 758 {
 759         s32 ret_val = E1000_SUCCESS;
 760         struct e1000_phy_info *phy = &hw->phy;
 761
 762         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 763
 764         /*
 765          * This isn't a true "hard" reset, but is the only reset
 766          * available to us at this time.
 767          */
 768
 769         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 770
 771         if (!(hw->phy.ops.write_reg))
 772                 goto out;
 773
 774         /*
 775          * SFP documentation requires the following to configure the SPF module
 776          * to work on SGMII.  No further documentation is given.
 777          */
 778         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 779         if (ret_val)
 780                 goto out;
 781
 782         ret_val = hw->phy.ops.commit(hw);
 783         if (ret_val)
 784                 goto out;
 785
 786         if (phy->id == M88E1512_E_PHY_ID)
 787                 ret_val = e1000_initialize_M88E1512_phy(hw);
 788 out:
 789         return ret_val;
 790 }
 791
 792 /**
 793  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 794  *  @hw: pointer to the HW structure
 795  *  @active: true to enable LPLU, false to disable
 796  *
 797  *  Sets the LPLU D0 state according to the active flag.  When
 798  *  activating LPLU this function also disables smart speed
 799  *  and vice versa.  LPLU will not be activated unless the
 800  *  device autonegotiation advertisement meets standards of
 801  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 802  *  This is a function pointer entry point only called by
 803  *  PHY setup routines.
 804  **/
 805 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 806 {
 807         struct e1000_phy_info *phy = &hw->phy;
 808         s32 ret_val = E1000_SUCCESS;
 809         u16 data;
 810
 811         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 812
 813         if (!(hw->phy.ops.read_reg))
 814                 goto out;
 815
 816         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 817         if (ret_val)
 818                 goto out;
 819
 820         if (active) {
 821                 data |= IGP02E1000_PM_D0_LPLU;
 822                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 823                                              data);
 824                 if (ret_val)
 825                         goto out;
 826
 827                 /* When LPLU is enabled, we should disable SmartSpeed */
 828                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 829                                             &data);
 830                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 831                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 832                                              data);
 833                 if (ret_val)
 834                         goto out;
 835         } else {
 836                 data &= ~IGP02E1000_PM_D0_LPLU;
 837                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 838                                              data);
 839                 /*
 840                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 841                  * during Dx states where the power conservation is most
 842                  * important.  During driver activity we should enable
 843                  * SmartSpeed, so performance is maintained.
 844                  */
 845                 if (phy->smart_speed == e1000_smart_speed_on) {
 846                         ret_val = phy->ops.read_reg(hw,
 847                                                     IGP01E1000_PHY_PORT_CONFIG,
 848                                                     &data);
 849                         if (ret_val)
 850                                 goto out;
 851
 852                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 853                         ret_val = phy->ops.write_reg(hw,
 854                                                      IGP01E1000_PHY_PORT_CONFIG,
 855                                                      data);
 856                         if (ret_val)
 857                                 goto out;
 858                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 859                         ret_val = phy->ops.read_reg(hw,
 860                                                     IGP01E1000_PHY_PORT_CONFIG,
 861                                                     &data);
 862                         if (ret_val)
 863                                 goto out;
 864
 865                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 866                         ret_val = phy->ops.write_reg(hw,
 867                                                      IGP01E1000_PHY_PORT_CONFIG,
 868                                                      data);
 869                         if (ret_val)
 870                                 goto out;
 871                 }
 872         }
 873
 874 out:
 875         return ret_val;
 876 }
 877
 878 /**
 879  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 880  *  @hw: pointer to the HW structure
 881  *  @active: true to enable LPLU, false to disable
 882  *
 883  *  Sets the LPLU D0 state according to the active flag.  When
 884  *  activating LPLU this function also disables smart speed
 885  *  and vice versa.  LPLU will not be activated unless the
 886  *  device autonegotiation advertisement meets standards of
 887  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 888  *  This is a function pointer entry point only called by
 889  *  PHY setup routines.
 890  **/
 891 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 892 {
 893         struct e1000_phy_info *phy = &hw->phy;
 894         s32 ret_val = E1000_SUCCESS;
 895         u32 data;
 896
 897         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 898
 899         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 900
 901         if (active) {
 902                 data |= E1000_82580_PM_D0_LPLU;
 903
 904                 /* When LPLU is enabled, we should disable SmartSpeed */
 905                 data &= ~E1000_82580_PM_SPD;
 906         } else {
 907                 data &= ~E1000_82580_PM_D0_LPLU;
 908
 909                 /*
 910                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 911                  * during Dx states where the power conservation is most
 912                  * important.  During driver activity we should enable
 913                  * SmartSpeed, so performance is maintained.
 914                  */
 915                 if (phy->smart_speed == e1000_smart_speed_on)
 916                         data |= E1000_82580_PM_SPD;
 917                 else if (phy->smart_speed == e1000_smart_speed_off)
 918                         data &= ~E1000_82580_PM_SPD;
 919         }
 920
 921         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 922         return ret_val;
 923 }
 924
 925 /**
 926  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 927  *  @hw: pointer to the HW structure
 928  *  @active: boolean used to enable/disable lplu
 929  *
 930  *  Success returns 0, Failure returns 1
 931  *
 932  *  The low power link up (lplu) state is set to the power management level D3
 933  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 934  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 935  *  is used during Dx states where the power conservation is most important.
 936  *  During driver activity, SmartSpeed should be enabled so performance is
 937  *  maintained.
 938  **/
 939 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 940 {
 941         struct e1000_phy_info *phy = &hw->phy;
 942         s32 ret_val = E1000_SUCCESS;
 943         u32 data;
 944
 945         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 946
 947         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 948
 949         if (!active) {
 950                 data &= ~E1000_82580_PM_D3_LPLU;
 951                 /*
 952                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 953                  * during Dx states where the power conservation is most
 954                  * important.  During driver activity we should enable
 955                  * SmartSpeed, so performance is maintained.
 956                  */
 957                 if (phy->smart_speed == e1000_smart_speed_on)
 958                         data |= E1000_82580_PM_SPD;
 959                 else if (phy->smart_speed == e1000_smart_speed_off)
 960                         data &= ~E1000_82580_PM_SPD;
 961         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 962                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 963                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 964                 data |= E1000_82580_PM_D3_LPLU;
 965                 /* When LPLU is enabled, we should disable SmartSpeed */
 966                 data &= ~E1000_82580_PM_SPD;
 967         }
 968
 969         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 970         return ret_val;
 971 }
 972
 973 /**
 974  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 975  *  @hw: pointer to the HW structure
 976  *
 977  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 978  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 979  *  Return successful if access grant bit set, else clear the request for
 980  *  EEPROM access and return -E1000_ERR_NVM (-1).
 981  **/
 982 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 983 {
 984         s32 ret_val;
 985
 986         DEBUGFUNC("e1000_acquire_nvm_82575");
 987
 988         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 989         if (ret_val)
 990                 goto out;
 991
 992         /*
 993          * Check if there is some access
 994          * error this access may hook on
 995          */
 996         if (hw->mac.type == e1000_i350) {
 997                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 998                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 999                     E1000_EECD_TIMEOUT)) {
1000                         /* Clear all access error flags */
1001                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1002                                         E1000_EECD_ERROR_CLR);
1003                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1004                 }
1005         }
1006         if (hw->mac.type == e1000_82580) {
1007                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1008                 if (eecd & E1000_EECD_BLOCKED) {
1009                         /* Clear access error flag */
1010                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1011                                         E1000_EECD_BLOCKED);
1012                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1013                 }
1014         }
1015
1016
1017         ret_val = e1000_acquire_nvm_generic(hw);
1018         if (ret_val)
1019                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1020
1021 out:
1022         return ret_val;
1023 }
1024
1025 /**
1026  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1027  *  @hw: pointer to the HW structure
1028  *
1029  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1030  *  then release the semaphores acquired.
1031  **/
1032 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1033 {
1034         DEBUGFUNC("e1000_release_nvm_82575");
1035
1036         e1000_release_nvm_generic(hw);
1037
1038         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1039 }
1040
1041 /**
1042  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1043  *  @hw: pointer to the HW structure
1044  *  @mask: specifies which semaphore to acquire
1045  *
1046  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1047  *  will also specify which port we're acquiring the lock for.
1048  **/
1049 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1050 {
1051         u32 swfw_sync;
1052         u32 swmask = mask;
1053         u32 fwmask = mask << 16;
1054         s32 ret_val = E1000_SUCCESS;
1055         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1056
1057         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1058
1059         while (i < timeout) {
1060                 if (e1000_get_hw_semaphore_generic(hw)) {
1061                         ret_val = -E1000_ERR_SWFW_SYNC;
1062                         goto out;
1063                 }
1064
1065                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1066                 if (!(swfw_sync & (fwmask | swmask)))
1067                         break;
1068
1069                 /*
1070                  * Firmware currently using resource (fwmask)
1071                  * or other software thread using resource (swmask)
1072                  */
1073                 e1000_put_hw_semaphore_generic(hw);
1074                 msec_delay_irq(5);
1075                 i++;
1076         }
1077
1078         if (i == timeout) {
1079                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1080                 ret_val = -E1000_ERR_SWFW_SYNC;
1081                 goto out;
1082         }
1083
1084         swfw_sync |= swmask;
1085         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1086
1087         e1000_put_hw_semaphore_generic(hw);
1088
1089 out:
1090         return ret_val;
1091 }
1092
1093 /**
1094  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1095  *  @hw: pointer to the HW structure
1096  *  @mask: specifies which semaphore to acquire
1097  *
1098  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1099  *  will also specify which port we're releasing the lock for.
1100  **/
1101 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1102 {
1103         u32 swfw_sync;
1104
1105         DEBUGFUNC("e1000_release_swfw_sync_82575");
1106
1107         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1108                 ; /* Empty */
1109
1110         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1111         swfw_sync &= ~mask;
1112         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1113
1114         e1000_put_hw_semaphore_generic(hw);
1115 }
1116
1117 /**
1118  *  e1000_get_cfg_done_82575 - Read config done bit
1119  *  @hw: pointer to the HW structure
1120  *
1121  *  Read the management control register for the config done bit for
1122  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1123  *  to read the config done bit, so an error is *ONLY* logged and returns
1124  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1125  *  would not be able to be reset or change link.
1126  **/
1127 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1128 {
1129         s32 timeout = PHY_CFG_TIMEOUT;
1130         s32 ret_val = E1000_SUCCESS;
1131         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1132
1133         DEBUGFUNC("e1000_get_cfg_done_82575");
1134
1135         if (hw->bus.func == E1000_FUNC_1)
1136                 mask = E1000_NVM_CFG_DONE_PORT_1;
1137         else if (hw->bus.func == E1000_FUNC_2)
1138                 mask = E1000_NVM_CFG_DONE_PORT_2;
1139         else if (hw->bus.func == E1000_FUNC_3)
1140                 mask = E1000_NVM_CFG_DONE_PORT_3;
1141         while (timeout) {
1142                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1143                         break;
1144                 msec_delay(1);
1145                 timeout--;
1146         }
1147         if (!timeout)
1148                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1149
1150         /* If EEPROM is not marked present, init the PHY manually */
1151         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1152             (hw->phy.type == e1000_phy_igp_3))
1153                 e1000_phy_init_script_igp3(hw);
1154
1155         return ret_val;
1156 }
1157
1158 /**
1159  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1160  *  @hw: pointer to the HW structure
1161  *  @speed: stores the current speed
1162  *  @duplex: stores the current duplex
1163  *
1164  *  This is a wrapper function, if using the serial gigabit media independent
1165  *  interface, use PCS to retrieve the link speed and duplex information.
1166  *  Otherwise, use the generic function to get the link speed and duplex info.
1167  **/
1168 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1169                                         u16 *duplex)
1170 {
1171         s32 ret_val;
1172
1173         DEBUGFUNC("e1000_get_link_up_info_82575");
1174
1175         if (hw->phy.media_type != e1000_media_type_copper)
1176                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1177                                                                duplex);
1178         else
1179                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1180                                                                     duplex);
1181
1182         return ret_val;
1183 }
1184
1185 /**
1186  *  e1000_check_for_link_82575 - Check for link
1187  *  @hw: pointer to the HW structure
1188  *
1189  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1190  *  use the generic interface for determining link.
1191  **/
1192 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1193 {
1194         s32 ret_val;
1195         u16 speed, duplex;
1196
1197         DEBUGFUNC("e1000_check_for_link_82575");
1198
1199         if (hw->phy.media_type != e1000_media_type_copper) {
1200                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1201                                                                &duplex);
1202                 /*
1203                  * Use this flag to determine if link needs to be checked or
1204                  * not.  If we have link clear the flag so that we do not
1205                  * continue to check for link.
1206                  */
1207                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1208
1209                 /*
1210                  * Configure Flow Control now that Auto-Neg has completed.
1211                  * First, we need to restore the desired flow control
1212                  * settings because we may have had to re-autoneg with a
1213                  * different link partner.
1214                  */
1215                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1216                 if (ret_val)
1217                         DEBUGOUT("Error configuring flow control\n");
1218         } else {
1219                 ret_val = e1000_check_for_copper_link_generic(hw);
1220         }
1221
1222         return ret_val;
1223 }
1224
1225 /**
1226  *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1227  *  @hw: pointer to the HW structure
1228  *
1229  *  Poll the M88E1112 interfaces to see which interface achieved link.
1230  */
1231 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1232 {
1233         struct e1000_phy_info *phy = &hw->phy;
1234         s32 ret_val;
1235         u16 data;
1236         u8 port = 0;
1237
1238         DEBUGFUNC("e1000_check_for_link_media_swap");
1239
1240         /* Check the copper medium. */
1241         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1242         if (ret_val)
1243                 return ret_val;
1244
1245         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1246         if (ret_val)
1247                 return ret_val;
1248
1249         if (data & E1000_M88E1112_STATUS_LINK)
1250                 port = E1000_MEDIA_PORT_COPPER;
1251
1252         /* Check the other medium. */
1253         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1254         if (ret_val)
1255                 return ret_val;
1256
1257         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1258         if (ret_val)
1259                 return ret_val;
1260
1261         /* reset page to 0 */
1262         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1263         if (ret_val)
1264                 return ret_val;
1265
1266         if (data & E1000_M88E1112_STATUS_LINK)
1267                 port = E1000_MEDIA_PORT_OTHER;
1268
1269         /* Determine if a swap needs to happen. */
1270         if (port && (hw->dev_spec._82575.media_port != port)) {
1271                 hw->dev_spec._82575.media_port = port;
1272                 hw->dev_spec._82575.media_changed = true;
1273         } else {
1274                 ret_val = e1000_check_for_link_82575(hw);
1275         }
1276
1277         return E1000_SUCCESS;
1278 }
1279
1280 /**
1281  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1282  *  @hw: pointer to the HW structure
1283  **/
1284 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1285 {
1286         u32 reg;
1287
1288         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1289
1290         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1291             !e1000_sgmii_active_82575(hw))
1292                 return;
1293
1294         /* Enable PCS to turn on link */
1295         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1296         reg |= E1000_PCS_CFG_PCS_EN;
1297         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1298
1299         /* Power up the laser */
1300         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1301         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1302         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1303
1304         /* flush the write to verify completion */
1305         E1000_WRITE_FLUSH(hw);
1306         msec_delay(1);
1307 }
1308
1309 /**
1310  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1311  *  @hw: pointer to the HW structure
1312  *  @speed: stores the current speed
1313  *  @duplex: stores the current duplex
1314  *
1315  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1316  *  duplex, then store the values in the pointers provided.
1317  **/
1318 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1319                                                 u16 *speed, u16 *duplex)
1320 {
1321         struct e1000_mac_info *mac = &hw->mac;
1322         u32 pcs;
1323         u32 status;
1324
1325         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1326
1327         /*
1328          * Read the PCS Status register for link state. For non-copper mode,
1329          * the status register is not accurate. The PCS status register is
1330          * used instead.
1331          */
1332         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1333
1334         /*
1335          * The link up bit determines when link is up on autoneg.
1336          */
1337         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1338                 mac->serdes_has_link = true;
1339
1340                 /* Detect and store PCS speed */
1341                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1342                         *speed = SPEED_1000;
1343                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1344                         *speed = SPEED_100;
1345                 else
1346                         *speed = SPEED_10;
1347
1348                 /* Detect and store PCS duplex */
1349                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1350                         *duplex = FULL_DUPLEX;
1351                 else
1352                         *duplex = HALF_DUPLEX;
1353
1354                 /* Check if it is an I354 2.5Gb backplane connection. */
1355                 if (mac->type == e1000_i354) {
1356                         status = E1000_READ_REG(hw, E1000_STATUS);
1357                         if ((status & E1000_STATUS_2P5_SKU) &&
1358                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1359                                 *speed = SPEED_2500;
1360                                 *duplex = FULL_DUPLEX;
1361                                 DEBUGOUT("2500 Mbs, ");
1362                                 DEBUGOUT("Full Duplex\n");
1363                         }
1364                 }
1365
1366         } else {
1367                 mac->serdes_has_link = false;
1368                 *speed = 0;
1369                 *duplex = 0;
1370         }
1371
1372         return E1000_SUCCESS;
1373 }
1374
1375 /**
1376  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1377  *  @hw: pointer to the HW structure
1378  *
1379  *  In the case of serdes shut down sfp and PCS on driver unload
1380  *  when management pass thru is not enabled.
1381  **/
1382 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1383 {
1384         u32 reg;
1385
1386         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1387
1388         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1389             !e1000_sgmii_active_82575(hw))
1390                 return;
1391
1392         if (!e1000_enable_mng_pass_thru(hw)) {
1393                 /* Disable PCS to turn off link */
1394                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1395                 reg &= ~E1000_PCS_CFG_PCS_EN;
1396                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1397
1398                 /* shutdown the laser */
1399                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1400                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1401                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1402
1403                 /* flush the write to verify completion */
1404                 E1000_WRITE_FLUSH(hw);
1405                 msec_delay(1);
1406         }
1407
1408         return;
1409 }
1410
1411 /**
1412  *  e1000_reset_hw_82575 - Reset hardware
1413  *  @hw: pointer to the HW structure
1414  *
1415  *  This resets the hardware into a known state.
1416  **/
1417 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1418 {
1419         u32 ctrl;
1420         s32 ret_val;
1421
1422         DEBUGFUNC("e1000_reset_hw_82575");
1423
1424         /*
1425          * Prevent the PCI-E bus from sticking if there is no TLP connection
1426          * on the last TLP read/write transaction when MAC is reset.
1427          */
1428         ret_val = e1000_disable_pcie_master_generic(hw);
1429         if (ret_val)
1430                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1431
1432         /* set the completion timeout for interface */
1433         ret_val = e1000_set_pcie_completion_timeout(hw);
1434         if (ret_val)
1435                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1436
1437         DEBUGOUT("Masking off all interrupts\n");
1438         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1439
1440         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1441         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1442         E1000_WRITE_FLUSH(hw);
1443
1444         msec_delay(10);
1445
1446         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1447
1448         DEBUGOUT("Issuing a global reset to MAC\n");
1449         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1450
1451         ret_val = e1000_get_auto_rd_done_generic(hw);
1452         if (ret_val) {
1453                 /*
1454                  * When auto config read does not complete, do not
1455                  * return with an error. This can happen in situations
1456                  * where there is no eeprom and prevents getting link.
1457                  */
1458                 DEBUGOUT("Auto Read Done did not complete\n");
1459         }
1460
1461         /* If EEPROM is not present, run manual init scripts */
1462         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1463                 e1000_reset_init_script_82575(hw);
1464
1465         /* Clear any pending interrupt events. */
1466         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1467         E1000_READ_REG(hw, E1000_ICR);
1468
1469         /* Install any alternate MAC address into RAR0 */
1470         ret_val = e1000_check_alt_mac_addr_generic(hw);
1471
1472         return ret_val;
1473 }
1474
1475 /**
1476  *  e1000_init_hw_82575 - Initialize hardware
1477  *  @hw: pointer to the HW structure
1478  *
1479  *  This inits the hardware readying it for operation.
1480  **/
1481 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1482 {
1483         struct e1000_mac_info *mac = &hw->mac;
1484         s32 ret_val;
1485         u16 i, rar_count = mac->rar_entry_count;
1486
1487         DEBUGFUNC("e1000_init_hw_82575");
1488
1489         /* Initialize identification LED */
1490         ret_val = mac->ops.id_led_init(hw);
1491         if (ret_val) {
1492                 DEBUGOUT("Error initializing identification LED\n");
1493                 /* This is not fatal and we should not stop init due to this */
1494         }
1495
1496         /* Disabling VLAN filtering */
1497         DEBUGOUT("Initializing the IEEE VLAN\n");
1498         mac->ops.clear_vfta(hw);
1499
1500         /* Setup the receive address */
1501         e1000_init_rx_addrs_generic(hw, rar_count);
1502
1503         /* Zero out the Multicast HASH table */
1504         DEBUGOUT("Zeroing the MTA\n");
1505         for (i = 0; i < mac->mta_reg_count; i++)
1506                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1507
1508         /* Zero out the Unicast HASH table */
1509         DEBUGOUT("Zeroing the UTA\n");
1510         for (i = 0; i < mac->uta_reg_count; i++)
1511                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1512
1513         /* Setup link and flow control */
1514         ret_val = mac->ops.setup_link(hw);
1515
1516         /* Set the default MTU size */
1517         hw->dev_spec._82575.mtu = 1500;
1518
1519         /*
1520          * Clear all of the statistics registers (clear on read).  It is
1521          * important that we do this after we have tried to establish link
1522          * because the symbol error count will increment wildly if there
1523          * is no link.
1524          */
1525         e1000_clear_hw_cntrs_82575(hw);
1526
1527         return ret_val;
1528 }
1529
1530 /**
1531  *  e1000_setup_copper_link_82575 - Configure copper link settings
1532  *  @hw: pointer to the HW structure
1533  *
1534  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1535  *  for link, once link is established calls to configure collision distance
1536  *  and flow control are called.
1537  **/
1538 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1539 {
1540         u32 ctrl;
1541         s32 ret_val;
1542         u32 phpm_reg;
1543
1544         DEBUGFUNC("e1000_setup_copper_link_82575");
1545
1546         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1547         ctrl |= E1000_CTRL_SLU;
1548         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1549         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1550
1551         /* Clear Go Link Disconnect bit on supported devices */
1552         switch (hw->mac.type) {
1553         case e1000_82580:
1554         case e1000_i350:
1555         case e1000_i210:
1556         case e1000_i211:
1557                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1558                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1559                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1560                 break;
1561         default:
1562                 break;
1563         }
1564
1565         ret_val = e1000_setup_serdes_link_82575(hw);
1566         if (ret_val)
1567                 goto out;
1568
1569         if (e1000_sgmii_active_82575(hw)) {
1570                 /* allow time for SFP cage time to power up phy */
1571                 msec_delay(300);
1572
1573                 ret_val = hw->phy.ops.reset(hw);
1574                 if (ret_val) {
1575                         DEBUGOUT("Error resetting the PHY.\n");
1576                         goto out;
1577                 }
1578         }
1579         switch (hw->phy.type) {
1580         case e1000_phy_i210:
1581         case e1000_phy_m88:
1582                 switch (hw->phy.id) {
1583                 case I347AT4_E_PHY_ID:
1584                 case M88E1112_E_PHY_ID:
1585                 case M88E1340M_E_PHY_ID:
1586                 case M88E1543_E_PHY_ID:
1587                 case M88E1512_E_PHY_ID:
1588                 case I210_I_PHY_ID:
1589                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1590                         break;
1591                 default:
1592                         ret_val = e1000_copper_link_setup_m88(hw);
1593                         break;
1594                 }
1595                 break;
1596         case e1000_phy_igp_3:
1597                 ret_val = e1000_copper_link_setup_igp(hw);
1598                 break;
1599         case e1000_phy_82580:
1600                 ret_val = e1000_copper_link_setup_82577(hw);
1601                 break;
1602         default:
1603                 ret_val = -E1000_ERR_PHY;
1604                 break;
1605         }
1606
1607         if (ret_val)
1608                 goto out;
1609
1610         ret_val = e1000_setup_copper_link_generic(hw);
1611 out:
1612         return ret_val;
1613 }
1614
1615 /**
1616  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1617  *  @hw: pointer to the HW structure
1618  *
1619  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1620  *  used on copper connections where the serialized gigabit media independent
1621  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1622  *  for auto-negotiation or forces speed/duplex.
1623  **/
1624 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1625 {
1626         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1627         bool pcs_autoneg;
1628         s32 ret_val = E1000_SUCCESS;
1629         u16 data;
1630
1631         DEBUGFUNC("e1000_setup_serdes_link_82575");
1632
1633         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1634             !e1000_sgmii_active_82575(hw))
1635                 return ret_val;
1636
1637         /*
1638          * On the 82575, SerDes loopback mode persists until it is
1639          * explicitly turned off or a power cycle is performed.  A read to
1640          * the register does not indicate its status.  Therefore, we ensure
1641          * loopback mode is disabled during initialization.
1642          */
1643         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1644
1645         /* power on the sfp cage if present */
1646         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1647         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1648         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1649
1650         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1651         ctrl_reg |= E1000_CTRL_SLU;
1652
1653         /* set both sw defined pins on 82575/82576*/
1654         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1655                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1656
1657         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1658
1659         /* default pcs_autoneg to the same setting as mac autoneg */
1660         pcs_autoneg = hw->mac.autoneg;
1661
1662         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1663         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1664                 /* sgmii mode lets the phy handle forcing speed/duplex */
1665                 pcs_autoneg = true;
1666                 /* autoneg time out should be disabled for SGMII mode */
1667                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1668                 break;
1669         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1670                 /* disable PCS autoneg and support parallel detect only */
1671                 pcs_autoneg = false;
1672                 /* fall through to default case */
1673         default:
1674                 if (hw->mac.type == e1000_82575 ||
1675                     hw->mac.type == e1000_82576) {
1676                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1677                         if (ret_val) {
1678                                 DEBUGOUT("NVM Read Error\n");
1679                                 return ret_val;
1680                         }
1681
1682                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1683                                 pcs_autoneg = false;
1684                 }
1685
1686                 /*
1687                  * non-SGMII modes only supports a speed of 1000/Full for the
1688                  * link so it is best to just force the MAC and let the pcs
1689                  * link either autoneg or be forced to 1000/Full
1690                  */
1691                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1692                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1693
1694                 /* set speed of 1000/Full if speed/duplex is forced */
1695                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1696                 break;
1697         }
1698
1699         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1700
1701         /*
1702          * New SerDes mode allows for forcing speed or autonegotiating speed
1703          * at 1gb. Autoneg should be default set by most drivers. This is the
1704          * mode that will be compatible with older link partners and switches.
1705          * However, both are supported by the hardware and some drivers/tools.
1706          */
1707         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1708                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1709
1710         if (pcs_autoneg) {
1711                 /* Set PCS register for autoneg */
1712                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1713                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1714
1715                 /* Disable force flow control for autoneg */
1716                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1717
1718                 /* Configure flow control advertisement for autoneg */
1719                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1720                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1721
1722                 switch (hw->fc.requested_mode) {
1723                 case e1000_fc_full:
1724                 case e1000_fc_rx_pause:
1725                         anadv_reg |= E1000_TXCW_ASM_DIR;
1726                         anadv_reg |= E1000_TXCW_PAUSE;
1727                         break;
1728                 case e1000_fc_tx_pause:
1729                         anadv_reg |= E1000_TXCW_ASM_DIR;
1730                         break;
1731                 default:
1732                         break;
1733                 }
1734
1735                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1736
1737                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1738         } else {
1739                 /* Set PCS register for forced link */
1740                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1741
1742                 /* Force flow control for forced link */
1743                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1744
1745                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1746         }
1747
1748         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1749
1750         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1751                 e1000_force_mac_fc_generic(hw);
1752
1753         return ret_val;
1754 }
1755
1756 /**
1757  *  e1000_get_media_type_82575 - derives current media type.
1758  *  @hw: pointer to the HW structure
1759  *
1760  *  The media type is chosen reflecting few settings.
1761  *  The following are taken into account:
1762  *  - link mode set in the current port Init Control Word #3
1763  *  - current link mode settings in CSR register
1764  *  - MDIO vs. I2C PHY control interface chosen
1765  *  - SFP module media type
1766  **/
1767 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1768 {
1769         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1770         s32 ret_val = E1000_SUCCESS;
1771         u32 ctrl_ext = 0;
1772         u32 link_mode = 0;
1773
1774         /* Set internal phy as default */
1775         dev_spec->sgmii_active = false;
1776         dev_spec->module_plugged = false;
1777
1778         /* Get CSR setting */
1779         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1780
1781         /* extract link mode setting */
1782         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1783
1784         switch (link_mode) {
1785         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1786                 hw->phy.media_type = e1000_media_type_internal_serdes;
1787                 break;
1788         case E1000_CTRL_EXT_LINK_MODE_GMII:
1789                 hw->phy.media_type = e1000_media_type_copper;
1790                 break;
1791         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1792                 /* Get phy control interface type set (MDIO vs. I2C)*/
1793                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1794                         hw->phy.media_type = e1000_media_type_copper;
1795                         dev_spec->sgmii_active = true;
1796                         break;
1797                 }
1798                 /* fall through for I2C based SGMII */
1799         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1800                 /* read media type from SFP EEPROM */
1801                 ret_val = e1000_set_sfp_media_type_82575(hw);
1802                 if ((ret_val != E1000_SUCCESS) ||
1803                     (hw->phy.media_type == e1000_media_type_unknown)) {
1804                         /*
1805                          * If media type was not identified then return media
1806                          * type defined by the CTRL_EXT settings.
1807                          */
1808                         hw->phy.media_type = e1000_media_type_internal_serdes;
1809
1810                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1811                                 hw->phy.media_type = e1000_media_type_copper;
1812                                 dev_spec->sgmii_active = true;
1813                         }
1814
1815                         break;
1816                 }
1817
1818                 /* do not change link mode for 100BaseFX */
1819                 if (dev_spec->eth_flags.e100_base_fx)
1820                         break;
1821
1822                 /* change current link mode setting */
1823                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1824
1825                 if (hw->phy.media_type == e1000_media_type_copper)
1826                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1827                 else
1828                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1829
1830                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1831
1832                 break;
1833         }
1834
1835         return ret_val;
1836 }
1837
1838 /**
1839  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1840  *  @hw: pointer to the HW structure
1841  *
1842  *  The media type is chosen based on SFP module.
1843  *  compatibility flags retrieved from SFP ID EEPROM.
1844  **/
1845 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1846 {
1847         s32 ret_val = E1000_ERR_CONFIG;
1848         u32 ctrl_ext = 0;
1849         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1850         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1851         u8 tranceiver_type = 0;
1852         s32 timeout = 3;
1853
1854         /* Turn I2C interface ON and power on sfp cage */
1855         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1856         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1857         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1858
1859         E1000_WRITE_FLUSH(hw);
1860
1861         /* Read SFP module data */
1862         while (timeout) {
1863                 ret_val = e1000_read_sfp_data_byte(hw,
1864                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1865                         &tranceiver_type);
1866                 if (ret_val == E1000_SUCCESS)
1867                         break;
1868                 msec_delay(100);
1869                 timeout--;
1870         }
1871         if (ret_val != E1000_SUCCESS)
1872                 goto out;
1873
1874         ret_val = e1000_read_sfp_data_byte(hw,
1875                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1876                         (u8 *)eth_flags);
1877         if (ret_val != E1000_SUCCESS)
1878                 goto out;
1879
1880         /* Check if there is some SFP module plugged and powered */
1881         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1882             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1883                 dev_spec->module_plugged = true;
1884                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1885                         hw->phy.media_type = e1000_media_type_internal_serdes;
1886                 } else if (eth_flags->e100_base_fx) {
1887                         dev_spec->sgmii_active = true;
1888                         hw->phy.media_type = e1000_media_type_internal_serdes;
1889                 } else if (eth_flags->e1000_base_t) {
1890                         dev_spec->sgmii_active = true;
1891                         hw->phy.media_type = e1000_media_type_copper;
1892                 } else {
1893                         hw->phy.media_type = e1000_media_type_unknown;
1894                         DEBUGOUT("PHY module has not been recognized\n");
1895                         goto out;
1896                 }
1897         } else {
1898                 hw->phy.media_type = e1000_media_type_unknown;
1899         }
1900         ret_val = E1000_SUCCESS;
1901 out:
1902         /* Restore I2C interface setting */
1903         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1904         return ret_val;
1905 }
1906
1907 /**
1908  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1909  *  @hw: pointer to the HW structure
1910  *  @data: pointer to the NVM (EEPROM)
1911  *
1912  *  Read the EEPROM for the current default LED configuration.  If the
1913  *  LED configuration is not valid, set to a valid LED configuration.
1914  **/
1915 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1916 {
1917         s32 ret_val;
1918
1919         DEBUGFUNC("e1000_valid_led_default_82575");
1920
1921         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1922         if (ret_val) {
1923                 DEBUGOUT("NVM Read Error\n");
1924                 goto out;
1925         }
1926
1927         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1928                 switch (hw->phy.media_type) {
1929                 case e1000_media_type_internal_serdes:
1930                         *data = ID_LED_DEFAULT_82575_SERDES;
1931                         break;
1932                 case e1000_media_type_copper:
1933                 default:
1934                         *data = ID_LED_DEFAULT;
1935                         break;
1936                 }
1937         }
1938 out:
1939         return ret_val;
1940 }
1941
1942 /**
1943  *  e1000_sgmii_active_82575 - Return sgmii state
1944  *  @hw: pointer to the HW structure
1945  *
1946  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1947  *  which can be enabled for use in the embedded applications.  Simply
1948  *  return the current state of the sgmii interface.
1949  **/
1950 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1951 {
1952         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1953         return dev_spec->sgmii_active;
1954 }
1955
1956 /**
1957  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1958  *  @hw: pointer to the HW structure
1959  *
1960  *  Inits recommended HW defaults after a reset when there is no EEPROM
1961  *  detected. This is only for the 82575.
1962  **/
1963 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1964 {
1965         DEBUGFUNC("e1000_reset_init_script_82575");
1966
1967         if (hw->mac.type == e1000_82575) {
1968                 DEBUGOUT("Running reset init script for 82575\n");
1969                 /* SerDes configuration via SERDESCTRL */
1970                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1971                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1972                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1973                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1974
1975                 /* CCM configuration via CCMCTL register */
1976                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1977                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1978
1979                 /* PCIe lanes configuration */
1980                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1981                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1982                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1983                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1984
1985                 /* PCIe PLL Configuration */
1986                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1987                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1988                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1989         }
1990
1991         return E1000_SUCCESS;
1992 }
1993
1994 /**
1995  *  e1000_read_mac_addr_82575 - Read device MAC address
1996  *  @hw: pointer to the HW structure
1997  **/
1998 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1999 {
2000         s32 ret_val;
2001
2002         DEBUGFUNC("e1000_read_mac_addr_82575");
2003
2004         /*
2005          * If there's an alternate MAC address place it in RAR0
2006          * so that it will override the Si installed default perm
2007          * address.
2008          */
2009         ret_val = e1000_check_alt_mac_addr_generic(hw);
2010         if (ret_val)
2011                 goto out;
2012
2013         ret_val = e1000_read_mac_addr_generic(hw);
2014
2015 out:
2016         return ret_val;
2017 }
2018
2019 /**
2020  *  e1000_config_collision_dist_82575 - Configure collision distance
2021  *  @hw: pointer to the HW structure
2022  *
2023  *  Configures the collision distance to the default value and is used
2024  *  during link setup.
2025  **/
2026 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2027 {
2028         u32 tctl_ext;
2029
2030         DEBUGFUNC("e1000_config_collision_dist_82575");
2031
2032         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2033
2034         tctl_ext &= ~E1000_TCTL_EXT_COLD;
2035         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2036
2037         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2038         E1000_WRITE_FLUSH(hw);
2039 }
2040
2041 /**
2042  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2043  * @hw: pointer to the HW structure
2044  *
2045  * In the case of a PHY power down to save power, or to turn off link during a
2046  * driver unload, or wake on lan is not enabled, remove the link.
2047  **/
2048 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2049 {
2050         struct e1000_phy_info *phy = &hw->phy;
2051
2052         if (!(phy->ops.check_reset_block))
2053                 return;
2054
2055         /* If the management interface is not enabled, then power down */
2056         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2057                 e1000_power_down_phy_copper(hw);
2058
2059         return;
2060 }
2061
2062 /**
2063  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2064  *  @hw: pointer to the HW structure
2065  *
2066  *  Clears the hardware counters by reading the counter registers.
2067  **/
2068 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2069 {
2070         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2071
2072         e1000_clear_hw_cntrs_base_generic(hw);
2073
2074         E1000_READ_REG(hw, E1000_PRC64);
2075         E1000_READ_REG(hw, E1000_PRC127);
2076         E1000_READ_REG(hw, E1000_PRC255);
2077         E1000_READ_REG(hw, E1000_PRC511);
2078         E1000_READ_REG(hw, E1000_PRC1023);
2079         E1000_READ_REG(hw, E1000_PRC1522);
2080         E1000_READ_REG(hw, E1000_PTC64);
2081         E1000_READ_REG(hw, E1000_PTC127);
2082         E1000_READ_REG(hw, E1000_PTC255);
2083         E1000_READ_REG(hw, E1000_PTC511);
2084         E1000_READ_REG(hw, E1000_PTC1023);
2085         E1000_READ_REG(hw, E1000_PTC1522);
2086
2087         E1000_READ_REG(hw, E1000_ALGNERRC);
2088         E1000_READ_REG(hw, E1000_RXERRC);
2089         E1000_READ_REG(hw, E1000_TNCRS);
2090         E1000_READ_REG(hw, E1000_CEXTERR);
2091         E1000_READ_REG(hw, E1000_TSCTC);
2092         E1000_READ_REG(hw, E1000_TSCTFC);
2093
2094         E1000_READ_REG(hw, E1000_MGTPRC);
2095         E1000_READ_REG(hw, E1000_MGTPDC);
2096         E1000_READ_REG(hw, E1000_MGTPTC);
2097
2098         E1000_READ_REG(hw, E1000_IAC);
2099         E1000_READ_REG(hw, E1000_ICRXOC);
2100
2101         E1000_READ_REG(hw, E1000_ICRXPTC);
2102         E1000_READ_REG(hw, E1000_ICRXATC);
2103         E1000_READ_REG(hw, E1000_ICTXPTC);
2104         E1000_READ_REG(hw, E1000_ICTXATC);
2105         E1000_READ_REG(hw, E1000_ICTXQEC);
2106         E1000_READ_REG(hw, E1000_ICTXQMTC);
2107         E1000_READ_REG(hw, E1000_ICRXDMTC);
2108
2109         E1000_READ_REG(hw, E1000_CBTMPC);
2110         E1000_READ_REG(hw, E1000_HTDPMC);
2111         E1000_READ_REG(hw, E1000_CBRMPC);
2112         E1000_READ_REG(hw, E1000_RPTHC);
2113         E1000_READ_REG(hw, E1000_HGPTC);
2114         E1000_READ_REG(hw, E1000_HTCBDPC);
2115         E1000_READ_REG(hw, E1000_HGORCL);
2116         E1000_READ_REG(hw, E1000_HGORCH);
2117         E1000_READ_REG(hw, E1000_HGOTCL);
2118         E1000_READ_REG(hw, E1000_HGOTCH);
2119         E1000_READ_REG(hw, E1000_LENERRS);
2120
2121         /* This register should not be read in copper configurations */
2122         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2123             e1000_sgmii_active_82575(hw))
2124                 E1000_READ_REG(hw, E1000_SCVPC);
2125 }
2126
2127 /**
2128  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2129  *  @hw: pointer to the HW structure
2130  *
2131  *  After rx enable if managability is enabled then there is likely some
2132  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2133  *  function clears the fifos and flushes any packets that came in as rx was
2134  *  being enabled.
2135  **/
2136 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2137 {
2138         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2139         int i, ms_wait;
2140
2141         DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2142         if (hw->mac.type != e1000_82575 ||
2143             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2144                 return;
2145
2146         /* Disable all Rx queues */
2147         for (i = 0; i < 4; i++) {
2148                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2149                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2150                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2151         }
2152         /* Poll all queues to verify they have shut down */
2153         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2154                 msec_delay(1);
2155                 rx_enabled = 0;
2156                 for (i = 0; i < 4; i++)
2157                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2158                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2159                         break;
2160         }
2161
2162         if (ms_wait == 10)
2163                 DEBUGOUT("Queue disable timed out after 10ms\n");
2164
2165         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2166          * incoming packets are rejected.  Set enable and wait 2ms so that
2167          * any packet that was coming in as RCTL.EN was set is flushed
2168          */
2169         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2170         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2171
2172         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2173         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2174
2175         rctl = E1000_READ_REG(hw, E1000_RCTL);
2176         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2177         temp_rctl |= E1000_RCTL_LPE;
2178
2179         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2180         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2181         E1000_WRITE_FLUSH(hw);
2182         msec_delay(2);
2183
2184         /* Enable Rx queues that were previously enabled and restore our
2185          * previous state
2186          */
2187         for (i = 0; i < 4; i++)
2188                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2189         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2190         E1000_WRITE_FLUSH(hw);
2191
2192         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2193         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2194
2195         /* Flush receive errors generated by workaround */
2196         E1000_READ_REG(hw, E1000_ROC);
2197         E1000_READ_REG(hw, E1000_RNBC);
2198         E1000_READ_REG(hw, E1000_MPC);
2199 }
2200
2201 /**
2202  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2203  *  @hw: pointer to the HW structure
2204  *
2205  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2206  *  however the hardware default for these parts is 500us to 1ms which is less
2207  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2208  *  increase the value to either 10ms to 200ms for capability version 1 config,
2209  *  or 16ms to 55ms for version 2.
2210  **/
2211 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2212 {
2213         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2214         s32 ret_val = E1000_SUCCESS;
2215         u16 pcie_devctl2;
2216
2217         /* only take action if timeout value is defaulted to 0 */
2218         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2219                 goto out;
2220
2221         /*
2222          * if capababilities version is type 1 we can write the
2223          * timeout of 10ms to 200ms through the GCR register
2224          */
2225         if (!(gcr & E1000_GCR_CAP_VER2)) {
2226                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2227                 goto out;
2228         }
2229
2230         /*
2231          * for version 2 capabilities we need to write the config space
2232          * directly in order to set the completion timeout value for
2233          * 16ms to 55ms
2234          */
2235         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2236                                           &pcie_devctl2);
2237         if (ret_val)
2238                 goto out;
2239
2240         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2241
2242         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2243                                            &pcie_devctl2);
2244 out:
2245         /* disable completion timeout resend */
2246         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2247
2248         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2249         return ret_val;
2250 }
2251
2252 /**
2253  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2254  *  @hw: pointer to the hardware struct
2255  *  @enable: state to enter, either enabled or disabled
2256  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2257  *
2258  *  enables/disables L2 switch anti-spoofing functionality.
2259  **/
2260 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2261 {
2262         u32 reg_val, reg_offset;
2263
2264         switch (hw->mac.type) {
2265         case e1000_82576:
2266                 reg_offset = E1000_DTXSWC;
2267                 break;
2268         case e1000_i350:
2269         case e1000_i354:
2270                 reg_offset = E1000_TXSWC;
2271                 break;
2272         default:
2273                 return;
2274         }
2275
2276         reg_val = E1000_READ_REG(hw, reg_offset);
2277         if (enable) {
2278                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2279                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2280                 /* The PF can spoof - it has to in order to
2281                  * support emulation mode NICs
2282                  */
2283                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2284         } else {
2285                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2286                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2287         }
2288         E1000_WRITE_REG(hw, reg_offset, reg_val);
2289 }
2290
2291 /**
2292  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2293  *  @hw: pointer to the hardware struct
2294  *  @enable: state to enter, either enabled or disabled
2295  *
2296  *  enables/disables L2 switch loopback functionality.
2297  **/
2298 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2299 {
2300         u32 dtxswc;
2301
2302         switch (hw->mac.type) {
2303         case e1000_82576:
2304                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2305                 if (enable)
2306                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2307                 else
2308                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2309                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2310                 break;
2311         case e1000_i350:
2312         case e1000_i354:
2313                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2314                 if (enable)
2315                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2316                 else
2317                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2318                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2319                 break;
2320         default:
2321                 /* Currently no other hardware supports loopback */
2322                 break;
2323         }
2324
2325
2326 }
2327
2328 /**
2329  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2330  *  @hw: pointer to the hardware struct
2331  *  @enable: state to enter, either enabled or disabled
2332  *
2333  *  enables/disables replication of packets across multiple pools.
2334  **/
2335 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2336 {
2337         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2338
2339         if (enable)
2340                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2341         else
2342                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2343
2344         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2345 }
2346
2347 /**
2348  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2349  *  @hw: pointer to the HW structure
2350  *  @offset: register offset to be read
2351  *  @data: pointer to the read data
2352  *
2353  *  Reads the MDI control register in the PHY at offset and stores the
2354  *  information read to data.
2355  **/
2356 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2357 {
2358         s32 ret_val;
2359
2360         DEBUGFUNC("e1000_read_phy_reg_82580");
2361
2362         ret_val = hw->phy.ops.acquire(hw);
2363         if (ret_val)
2364                 goto out;
2365
2366         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2367
2368         hw->phy.ops.release(hw);
2369
2370 out:
2371         return ret_val;
2372 }
2373
2374 /**
2375  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2376  *  @hw: pointer to the HW structure
2377  *  @offset: register offset to write to
2378  *  @data: data to write to register at offset
2379  *
2380  *  Writes data to MDI control register in the PHY at offset.
2381  **/
2382 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2383 {
2384         s32 ret_val;
2385
2386         DEBUGFUNC("e1000_write_phy_reg_82580");
2387
2388         ret_val = hw->phy.ops.acquire(hw);
2389         if (ret_val)
2390                 goto out;
2391
2392         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2393
2394         hw->phy.ops.release(hw);
2395
2396 out:
2397         return ret_val;
2398 }
2399
2400 /**
2401  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2402  *  @hw: pointer to the HW structure
2403  *
2404  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2405  *  the values found in the EEPROM.  This addresses an issue in which these
2406  *  bits are not restored from EEPROM after reset.
2407  **/
2408 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2409 {
2410         s32 ret_val = E1000_SUCCESS;
2411         u32 mdicnfg;
2412         u16 nvm_data = 0;
2413
2414         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2415
2416         if (hw->mac.type != e1000_82580)
2417                 goto out;
2418         if (!e1000_sgmii_active_82575(hw))
2419                 goto out;
2420
2421         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2422                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2423                                    &nvm_data);
2424         if (ret_val) {
2425                 DEBUGOUT("NVM Read Error\n");
2426                 goto out;
2427         }
2428
2429         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2430         if (nvm_data & NVM_WORD24_EXT_MDIO)
2431                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2432         if (nvm_data & NVM_WORD24_COM_MDIO)
2433                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2434         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2435 out:
2436         return ret_val;
2437 }
2438
2439 /**
2440  *  e1000_reset_hw_82580 - Reset hardware
2441  *  @hw: pointer to the HW structure
2442  *
2443  *  This resets function or entire device (all ports, etc.)
2444  *  to a known state.
2445  **/
2446 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2447 {
2448         s32 ret_val = E1000_SUCCESS;
2449         /* BH SW mailbox bit in SW_FW_SYNC */
2450         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2451         u32 ctrl;
2452         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2453
2454         DEBUGFUNC("e1000_reset_hw_82580");
2455
2456         hw->dev_spec._82575.global_device_reset = false;
2457
2458         /* 82580 does not reliably do global_device_reset due to hw errata */
2459         if (hw->mac.type == e1000_82580)
2460                 global_device_reset = false;
2461
2462         /* Get current control state. */
2463         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2464
2465         /*
2466          * Prevent the PCI-E bus from sticking if there is no TLP connection
2467          * on the last TLP read/write transaction when MAC is reset.
2468          */
2469         ret_val = e1000_disable_pcie_master_generic(hw);
2470         if (ret_val)
2471                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2472
2473         DEBUGOUT("Masking off all interrupts\n");
2474         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2475         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2476         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2477         E1000_WRITE_FLUSH(hw);
2478
2479         msec_delay(10);
2480
2481         /* Determine whether or not a global dev reset is requested */
2482         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2483             swmbsw_mask))
2484                         global_device_reset = false;
2485
2486         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2487             E1000_STAT_DEV_RST_SET))
2488                 ctrl |= E1000_CTRL_DEV_RST;
2489         else
2490                 ctrl |= E1000_CTRL_RST;
2491
2492         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2493         E1000_WRITE_FLUSH(hw);
2494
2495         /* Add delay to insure DEV_RST has time to complete */
2496         if (global_device_reset)
2497                 msec_delay(5);
2498
2499         ret_val = e1000_get_auto_rd_done_generic(hw);
2500         if (ret_val) {
2501                 /*
2502                  * When auto config read does not complete, do not
2503                  * return with an error. This can happen in situations
2504                  * where there is no eeprom and prevents getting link.
2505                  */
2506                 DEBUGOUT("Auto Read Done did not complete\n");
2507         }
2508
2509         /* clear global device reset status bit */
2510         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2511
2512         /* Clear any pending interrupt events. */
2513         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2514         E1000_READ_REG(hw, E1000_ICR);
2515
2516         ret_val = e1000_reset_mdicnfg_82580(hw);
2517         if (ret_val)
2518                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2519
2520         /* Install any alternate MAC address into RAR0 */
2521         ret_val = e1000_check_alt_mac_addr_generic(hw);
2522
2523         /* Release semaphore */
2524         if (global_device_reset)
2525                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2526
2527         return ret_val;
2528 }
2529
2530 /**
2531  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2532  *  @data: data received by reading RXPBS register
2533  *
2534  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2535  *  This function converts the retrieved value into the correct table value
2536  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2537  *  0x0 36  72 144   1   2   4   8  16
2538  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2539  */
2540 u16 e1000_rxpbs_adjust_82580(u32 data)
2541 {
2542         u16 ret_val = 0;
2543
2544         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2545                 ret_val = e1000_82580_rxpbs_table[data];
2546
2547         return ret_val;
2548 }
2549
2550 /**
2551  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2552  *  checksum
2553  *  @hw: pointer to the HW structure
2554  *  @offset: offset in words of the checksum protected region
2555  *
2556  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2557  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2558  **/
2559 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2560 {
2561         s32 ret_val = E1000_SUCCESS;
2562         u16 checksum = 0;
2563         u16 i, nvm_data;
2564
2565         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2566
2567         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2568                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2569                 if (ret_val) {
2570                         DEBUGOUT("NVM Read Error\n");
2571                         goto out;
2572                 }
2573                 checksum += nvm_data;
2574         }
2575
2576         if (checksum != (u16) NVM_SUM) {
2577                 DEBUGOUT("NVM Checksum Invalid\n");
2578                 ret_val = -E1000_ERR_NVM;
2579                 goto out;
2580         }
2581
2582 out:
2583         return ret_val;
2584 }
2585
2586 /**
2587  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2588  *  checksum
2589  *  @hw: pointer to the HW structure
2590  *  @offset: offset in words of the checksum protected region
2591  *
2592  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2593  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2594  *  value to the EEPROM.
2595  **/
2596 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2597 {
2598         s32 ret_val;
2599         u16 checksum = 0;
2600         u16 i, nvm_data;
2601
2602         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2603
2604         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2605                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2606                 if (ret_val) {
2607                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2608                         goto out;
2609                 }
2610                 checksum += nvm_data;
2611         }
2612         checksum = (u16) NVM_SUM - checksum;
2613         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2614                                     &checksum);
2615         if (ret_val)
2616                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2617
2618 out:
2619         return ret_val;
2620 }
2621
2622 /**
2623  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2624  *  @hw: pointer to the HW structure
2625  *
2626  *  Calculates the EEPROM section checksum by reading/adding each word of
2627  *  the EEPROM and then verifies that the sum of the EEPROM is
2628  *  equal to 0xBABA.
2629  **/
2630 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2631 {
2632         s32 ret_val;
2633         u16 eeprom_regions_count = 1;
2634         u16 j, nvm_data;
2635         u16 nvm_offset;
2636
2637         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2638
2639         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2640         if (ret_val) {
2641                 DEBUGOUT("NVM Read Error\n");
2642                 goto out;
2643         }
2644
2645         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2646                 /* if chekcsums compatibility bit is set validate checksums
2647                  * for all 4 ports. */
2648                 eeprom_regions_count = 4;
2649         }
2650
2651         for (j = 0; j < eeprom_regions_count; j++) {
2652                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2653                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2654                                                                   nvm_offset);
2655                 if (ret_val != E1000_SUCCESS)
2656                         goto out;
2657         }
2658
2659 out:
2660         return ret_val;
2661 }
2662
2663 /**
2664  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2665  *  @hw: pointer to the HW structure
2666  *
2667  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2668  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2669  *  checksum and writes the value to the EEPROM.
2670  **/
2671 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2672 {
2673         s32 ret_val;
2674         u16 j, nvm_data;
2675         u16 nvm_offset;
2676
2677         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2678
2679         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2680         if (ret_val) {
2681                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2682                 goto out;
2683         }
2684
2685         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2686                 /* set compatibility bit to validate checksums appropriately */
2687                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2688                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2689                                             &nvm_data);
2690                 if (ret_val) {
2691                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2692                         goto out;
2693                 }
2694         }
2695
2696         for (j = 0; j < 4; j++) {
2697                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2698                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2699                 if (ret_val)
2700                         goto out;
2701         }
2702
2703 out:
2704         return ret_val;
2705 }
2706
2707 /**
2708  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2709  *  @hw: pointer to the HW structure
2710  *
2711  *  Calculates the EEPROM section checksum by reading/adding each word of
2712  *  the EEPROM and then verifies that the sum of the EEPROM is
2713  *  equal to 0xBABA.
2714  **/
2715 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2716 {
2717         s32 ret_val = E1000_SUCCESS;
2718         u16 j;
2719         u16 nvm_offset;
2720
2721         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2722
2723         for (j = 0; j < 4; j++) {
2724                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2725                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2726                                                                   nvm_offset);
2727                 if (ret_val != E1000_SUCCESS)
2728                         goto out;
2729         }
2730
2731 out:
2732         return ret_val;
2733 }
2734
2735 /**
2736  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2737  *  @hw: pointer to the HW structure
2738  *
2739  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2740  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2741  *  checksum and writes the value to the EEPROM.
2742  **/
2743 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2744 {
2745         s32 ret_val = E1000_SUCCESS;
2746         u16 j;
2747         u16 nvm_offset;
2748
2749         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2750
2751         for (j = 0; j < 4; j++) {
2752                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2753                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2754                 if (ret_val != E1000_SUCCESS)
2755                         goto out;
2756         }
2757
2758 out:
2759         return ret_val;
2760 }
2761
2762 /**
2763  *  __e1000_access_emi_reg - Read/write EMI register
2764  *  @hw: pointer to the HW structure
2765  *  @addr: EMI address to program
2766  *  @data: pointer to value to read/write from/to the EMI address
2767  *  @read: boolean flag to indicate read or write
2768  **/
2769 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2770                                   u16 *data, bool read)
2771 {
2772         s32 ret_val;
2773
2774         DEBUGFUNC("__e1000_access_emi_reg");
2775
2776         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2777         if (ret_val)
2778                 return ret_val;
2779
2780         if (read)
2781                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2782         else
2783                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2784
2785         return ret_val;
2786 }
2787
2788 /**
2789  *  e1000_read_emi_reg - Read Extended Management Interface register
2790  *  @hw: pointer to the HW structure
2791  *  @addr: EMI address to program
2792  *  @data: value to be read from the EMI address
2793  **/
2794 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2795 {
2796         DEBUGFUNC("e1000_read_emi_reg");
2797
2798         return __e1000_access_emi_reg(hw, addr, data, true);
2799 }
2800
2801 /**
2802  *  e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2803  *  @hw: pointer to the HW structure
2804  *
2805  *  Initialize Marverl 1512 to work correctly with Avoton.
2806  **/
2807 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2808 {
2809         struct e1000_phy_info *phy = &hw->phy;
2810         s32 ret_val = E1000_SUCCESS;
2811
2812         DEBUGFUNC("e1000_initialize_M88E1512_phy");
2813
2814         /* Check if this is correct PHY. */
2815         if (phy->id != M88E1512_E_PHY_ID)
2816                 goto out;
2817
2818         /* Switch to PHY page 0xFF. */
2819         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2820         if (ret_val)
2821                 goto out;
2822
2823         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2824         if (ret_val)
2825                 goto out;
2826
2827         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2828         if (ret_val)
2829                 goto out;
2830
2831         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2832         if (ret_val)
2833                 goto out;
2834
2835         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2836         if (ret_val)
2837                 goto out;
2838
2839         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2840         if (ret_val)
2841                 goto out;
2842
2843         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2844         if (ret_val)
2845                 goto out;
2846
2847         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2848         if (ret_val)
2849                 goto out;
2850
2851         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2852         if (ret_val)
2853                 goto out;
2854
2855         /* Switch to PHY page 0xFB. */
2856         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2857         if (ret_val)
2858                 goto out;
2859
2860         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2861         if (ret_val)
2862                 goto out;
2863
2864         /* Switch to PHY page 0x12. */
2865         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2866         if (ret_val)
2867                 goto out;
2868
2869         /* Change mode to SGMII-to-Copper */
2870         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2871         if (ret_val)
2872                 goto out;
2873
2874         /* Return the PHY to page 0. */
2875         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2876         if (ret_val)
2877                 goto out;
2878
2879         ret_val = phy->ops.commit(hw);
2880         if (ret_val) {
2881                 DEBUGOUT("Error committing the PHY changes\n");
2882                 return ret_val;
2883         }
2884
2885         msec_delay(1000);
2886 out:
2887         return ret_val;
2888 }
2889
2890 /**
2891  *  e1000_set_eee_i350 - Enable/disable EEE support
2892  *  @hw: pointer to the HW structure
2893  *
2894  *  Enable/disable EEE based on setting in dev_spec structure.
2895  *
2896  **/
2897 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2898 {
2899         s32 ret_val = E1000_SUCCESS;
2900         u32 ipcnfg, eeer;
2901
2902         DEBUGFUNC("e1000_set_eee_i350");
2903
2904         if ((hw->mac.type < e1000_i350) ||
2905             (hw->phy.media_type != e1000_media_type_copper))
2906                 goto out;
2907         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2908         eeer = E1000_READ_REG(hw, E1000_EEER);
2909
2910         /* enable or disable per user setting */
2911         if (!(hw->dev_spec._82575.eee_disable)) {
2912                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2913
2914                 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2915                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2916                          E1000_EEER_LPI_FC);
2917
2918                 /* This bit should not be set in normal operation. */
2919                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2920                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2921         } else {
2922                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2923                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2924                           E1000_EEER_LPI_FC);
2925         }
2926         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2927         E1000_WRITE_REG(hw, E1000_EEER, eeer);
2928         E1000_READ_REG(hw, E1000_IPCNFG);
2929         E1000_READ_REG(hw, E1000_EEER);
2930 out:
2931
2932         return ret_val;
2933 }
2934
2935 /**
2936  *  e1000_set_eee_i354 - Enable/disable EEE support
2937  *  @hw: pointer to the HW structure
2938  *
2939  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2940  *
2941  **/
2942 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2943 {
2944         struct e1000_phy_info *phy = &hw->phy;
2945         s32 ret_val = E1000_SUCCESS;
2946         u16 phy_data;
2947
2948         DEBUGFUNC("e1000_set_eee_i354");
2949
2950         if ((hw->phy.media_type != e1000_media_type_copper) ||
2951             ((phy->id != M88E1543_E_PHY_ID) &&
2952             (phy->id != M88E1512_E_PHY_ID)))
2953                 goto out;
2954
2955         if (!hw->dev_spec._82575.eee_disable) {
2956                 /* Switch to PHY page 18. */
2957                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2958                 if (ret_val)
2959                         goto out;
2960
2961                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2962                                             &phy_data);
2963                 if (ret_val)
2964                         goto out;
2965
2966                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2967                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2968                                              phy_data);
2969                 if (ret_val)
2970                         goto out;
2971
2972                 /* Return the PHY to page 0. */
2973                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2974                 if (ret_val)
2975                         goto out;
2976
2977                 /* Turn on EEE advertisement. */
2978                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2979                                                E1000_EEE_ADV_DEV_I354,
2980                                                &phy_data);
2981                 if (ret_val)
2982                         goto out;
2983
2984                 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2985                             E1000_EEE_ADV_1000_SUPPORTED;
2986                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2987                                                 E1000_EEE_ADV_DEV_I354,
2988                                                 phy_data);
2989         } else {
2990                 /* Turn off EEE advertisement. */
2991                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2992                                                E1000_EEE_ADV_DEV_I354,
2993                                                &phy_data);
2994                 if (ret_val)
2995                         goto out;
2996
2997                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2998                               E1000_EEE_ADV_1000_SUPPORTED);
2999                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3000                                                 E1000_EEE_ADV_DEV_I354,
3001                                                 phy_data);
3002         }
3003
3004 out:
3005         return ret_val;
3006 }
3007
3008 /**
3009  *  e1000_get_eee_status_i354 - Get EEE status
3010  *  @hw: pointer to the HW structure
3011  *  @status: EEE status
3012  *
3013  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
3014  *  been received.
3015  **/
3016 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3017 {
3018         struct e1000_phy_info *phy = &hw->phy;
3019         s32 ret_val = E1000_SUCCESS;
3020         u16 phy_data;
3021
3022         DEBUGFUNC("e1000_get_eee_status_i354");
3023
3024         /* Check if EEE is supported on this device. */
3025         if ((hw->phy.media_type != e1000_media_type_copper) ||
3026             ((phy->id != M88E1543_E_PHY_ID) &&
3027             (phy->id != M88E1512_E_PHY_ID)))
3028                 goto out;
3029
3030         ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3031                                        E1000_PCS_STATUS_DEV_I354,
3032                                        &phy_data);
3033         if (ret_val)
3034                 goto out;
3035
3036         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3037                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
3038
3039 out:
3040         return ret_val;
3041 }
3042
3043 /* Due to a hw errata, if the host tries to  configure the VFTA register
3044  * while performing queries from the BMC or DMA, then the VFTA in some
3045  * cases won't be written.
3046  */
3047
3048 /**
3049  *  e1000_clear_vfta_i350 - Clear VLAN filter table
3050  *  @hw: pointer to the HW structure
3051  *
3052  *  Clears the register array which contains the VLAN filter table by
3053  *  setting all the values to 0.
3054  **/
3055 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3056 {
3057         u32 offset;
3058         int i;
3059
3060         DEBUGFUNC("e1000_clear_vfta_350");
3061
3062         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3063                 for (i = 0; i < 10; i++)
3064                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3065
3066                 E1000_WRITE_FLUSH(hw);
3067         }
3068 }
3069
3070 /**
3071  *  e1000_write_vfta_i350 - Write value to VLAN filter table
3072  *  @hw: pointer to the HW structure
3073  *  @offset: register offset in VLAN filter table
3074  *  @value: register value written to VLAN filter table
3075  *
3076  *  Writes value at the given offset in the register array which stores
3077  *  the VLAN filter table.
3078  **/
3079 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3080 {
3081         int i;
3082
3083         DEBUGFUNC("e1000_write_vfta_350");
3084
3085         for (i = 0; i < 10; i++)
3086                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3087
3088         E1000_WRITE_FLUSH(hw);
3089 }
3090
3091
3092 /**
3093  *  e1000_set_i2c_bb - Enable I2C bit-bang
3094  *  @hw: pointer to the HW structure
3095  *
3096  *  Enable I2C bit-bang interface
3097  *
3098  **/
3099 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3100 {
3101         s32 ret_val = E1000_SUCCESS;
3102         u32 ctrl_ext, i2cparams;
3103
3104         DEBUGFUNC("e1000_set_i2c_bb");
3105
3106         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3107         ctrl_ext |= E1000_CTRL_I2C_ENA;
3108         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3109         E1000_WRITE_FLUSH(hw);
3110
3111         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3112         i2cparams |= E1000_I2CBB_EN;
3113         i2cparams |= E1000_I2C_DATA_OE_N;
3114         i2cparams |= E1000_I2C_CLK_OE_N;
3115         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3116         E1000_WRITE_FLUSH(hw);
3117
3118         return ret_val;
3119 }
3120
3121 /**
3122  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3123  *  @hw: pointer to hardware structure
3124  *  @byte_offset: byte offset to read
3125  *  @dev_addr: device address
3126  *  @data: value read
3127  *
3128  *  Performs byte read operation over I2C interface at
3129  *  a specified device address.
3130  **/
3131 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3132                                 u8 dev_addr, u8 *data)
3133 {
3134         s32 status = E1000_SUCCESS;
3135         u32 max_retry = 10;
3136         u32 retry = 1;
3137         u16 swfw_mask = 0;
3138
3139         bool nack = true;
3140
3141         DEBUGFUNC("e1000_read_i2c_byte_generic");
3142
3143         swfw_mask = E1000_SWFW_PHY0_SM;
3144
3145         do {
3146                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3147                     != E1000_SUCCESS) {
3148                         status = E1000_ERR_SWFW_SYNC;
3149                         goto read_byte_out;
3150                 }
3151
3152                 e1000_i2c_start(hw);
3153
3154                 /* Device Address and write indication */
3155                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3156                 if (status != E1000_SUCCESS)
3157                         goto fail;
3158
3159                 status = e1000_get_i2c_ack(hw);
3160                 if (status != E1000_SUCCESS)
3161                         goto fail;
3162
3163                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3164                 if (status != E1000_SUCCESS)
3165                         goto fail;
3166
3167                 status = e1000_get_i2c_ack(hw);
3168                 if (status != E1000_SUCCESS)
3169                         goto fail;
3170
3171                 e1000_i2c_start(hw);
3172
3173                 /* Device Address and read indication */
3174                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3175                 if (status != E1000_SUCCESS)
3176                         goto fail;
3177
3178                 status = e1000_get_i2c_ack(hw);
3179                 if (status != E1000_SUCCESS)
3180                         goto fail;
3181
3182                 status = e1000_clock_in_i2c_byte(hw, data);
3183                 if (status != E1000_SUCCESS)
3184                         goto fail;
3185
3186                 status = e1000_clock_out_i2c_bit(hw, nack);
3187                 if (status != E1000_SUCCESS)
3188                         goto fail;
3189
3190                 e1000_i2c_stop(hw);
3191                 break;
3192
3193 fail:
3194                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3195                 msec_delay(100);
3196                 e1000_i2c_bus_clear(hw);
3197                 retry++;
3198                 if (retry < max_retry)
3199                         DEBUGOUT("I2C byte read error - Retrying.\n");
3200                 else
3201                         DEBUGOUT("I2C byte read error.\n");
3202
3203         } while (retry < max_retry);
3204
3205         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3206
3207 read_byte_out:
3208
3209         return status;
3210 }
3211
3212 /**
3213  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3214  *  @hw: pointer to hardware structure
3215  *  @byte_offset: byte offset to write
3216  *  @dev_addr: device address
3217  *  @data: value to write
3218  *
3219  *  Performs byte write operation over I2C interface at
3220  *  a specified device address.
3221  **/
3222 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3223                                  u8 dev_addr, u8 data)
3224 {
3225         s32 status = E1000_SUCCESS;
3226         u32 max_retry = 1;
3227         u32 retry = 0;
3228         u16 swfw_mask = 0;
3229
3230         DEBUGFUNC("e1000_write_i2c_byte_generic");
3231
3232         swfw_mask = E1000_SWFW_PHY0_SM;
3233
3234         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3235                 status = E1000_ERR_SWFW_SYNC;
3236                 goto write_byte_out;
3237         }
3238
3239         do {
3240                 e1000_i2c_start(hw);
3241
3242                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3243                 if (status != E1000_SUCCESS)
3244                         goto fail;
3245
3246                 status = e1000_get_i2c_ack(hw);
3247                 if (status != E1000_SUCCESS)
3248                         goto fail;
3249
3250                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3251                 if (status != E1000_SUCCESS)
3252                         goto fail;
3253
3254                 status = e1000_get_i2c_ack(hw);
3255                 if (status != E1000_SUCCESS)
3256                         goto fail;
3257
3258                 status = e1000_clock_out_i2c_byte(hw, data);
3259                 if (status != E1000_SUCCESS)
3260                         goto fail;
3261
3262                 status = e1000_get_i2c_ack(hw);
3263                 if (status != E1000_SUCCESS)
3264                         goto fail;
3265
3266                 e1000_i2c_stop(hw);
3267                 break;
3268
3269 fail:
3270                 e1000_i2c_bus_clear(hw);
3271                 retry++;
3272                 if (retry < max_retry)
3273                         DEBUGOUT("I2C byte write error - Retrying.\n");
3274                 else
3275                         DEBUGOUT("I2C byte write error.\n");
3276         } while (retry < max_retry);
3277
3278         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3279
3280 write_byte_out:
3281
3282         return status;
3283 }
3284
3285 /**
3286  *  e1000_i2c_start - Sets I2C start condition
3287  *  @hw: pointer to hardware structure
3288  *
3289  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3290  **/
3291 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3292 {
3293         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3294
3295         DEBUGFUNC("e1000_i2c_start");
3296
3297         /* Start condition must begin with data and clock high */
3298         e1000_set_i2c_data(hw, &i2cctl, 1);
3299         e1000_raise_i2c_clk(hw, &i2cctl);
3300
3301         /* Setup time for start condition (4.7us) */
3302         usec_delay(E1000_I2C_T_SU_STA);
3303
3304         e1000_set_i2c_data(hw, &i2cctl, 0);
3305
3306         /* Hold time for start condition (4us) */
3307         usec_delay(E1000_I2C_T_HD_STA);
3308
3309         e1000_lower_i2c_clk(hw, &i2cctl);
3310
3311         /* Minimum low period of clock is 4.7 us */
3312         usec_delay(E1000_I2C_T_LOW);
3313
3314 }
3315
3316 /**
3317  *  e1000_i2c_stop - Sets I2C stop condition
3318  *  @hw: pointer to hardware structure
3319  *
3320  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3321  **/
3322 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3323 {
3324         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3325
3326         DEBUGFUNC("e1000_i2c_stop");
3327
3328         /* Stop condition must begin with data low and clock high */
3329         e1000_set_i2c_data(hw, &i2cctl, 0);
3330         e1000_raise_i2c_clk(hw, &i2cctl);
3331
3332         /* Setup time for stop condition (4us) */
3333         usec_delay(E1000_I2C_T_SU_STO);
3334
3335         e1000_set_i2c_data(hw, &i2cctl, 1);
3336
3337         /* bus free time between stop and start (4.7us)*/
3338         usec_delay(E1000_I2C_T_BUF);
3339 }
3340
3341 /**
3342  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3343  *  @hw: pointer to hardware structure
3344  *  @data: data byte to clock in
3345  *
3346  *  Clocks in one byte data via I2C data/clock
3347  **/
3348 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3349 {
3350         s32 i;
3351         bool bit = 0;
3352
3353         DEBUGFUNC("e1000_clock_in_i2c_byte");
3354
3355         *data = 0;
3356         for (i = 7; i >= 0; i--) {
3357                 e1000_clock_in_i2c_bit(hw, &bit);
3358                 *data |= bit << i;
3359         }
3360
3361         return E1000_SUCCESS;
3362 }
3363
3364 /**
3365  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3366  *  @hw: pointer to hardware structure
3367  *  @data: data byte clocked out
3368  *
3369  *  Clocks out one byte data via I2C data/clock
3370  **/
3371 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3372 {
3373         s32 status = E1000_SUCCESS;
3374         s32 i;
3375         u32 i2cctl;
3376         bool bit = 0;
3377
3378         DEBUGFUNC("e1000_clock_out_i2c_byte");
3379
3380         for (i = 7; i >= 0; i--) {
3381                 bit = (data >> i) & 0x1;
3382                 status = e1000_clock_out_i2c_bit(hw, bit);
3383
3384                 if (status != E1000_SUCCESS)
3385                         break;
3386         }
3387
3388         /* Release SDA line (set high) */
3389         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3390
3391         i2cctl |= E1000_I2C_DATA_OE_N;
3392         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3393         E1000_WRITE_FLUSH(hw);
3394
3395         return status;
3396 }
3397
3398 /**
3399  *  e1000_get_i2c_ack - Polls for I2C ACK
3400  *  @hw: pointer to hardware structure
3401  *
3402  *  Clocks in/out one bit via I2C data/clock
3403  **/
3404 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3405 {
3406         s32 status = E1000_SUCCESS;
3407         u32 i = 0;
3408         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3409         u32 timeout = 10;
3410         bool ack = true;
3411
3412         DEBUGFUNC("e1000_get_i2c_ack");
3413
3414         e1000_raise_i2c_clk(hw, &i2cctl);
3415
3416         /* Minimum high period of clock is 4us */
3417         usec_delay(E1000_I2C_T_HIGH);
3418
3419         /* Wait until SCL returns high */
3420         for (i = 0; i < timeout; i++) {
3421                 usec_delay(1);
3422                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3423                 if (i2cctl & E1000_I2C_CLK_IN)
3424                         break;
3425         }
3426         if (!(i2cctl & E1000_I2C_CLK_IN))
3427                 return E1000_ERR_I2C;
3428
3429         ack = e1000_get_i2c_data(&i2cctl);
3430         if (ack) {
3431                 DEBUGOUT("I2C ack was not received.\n");
3432                 status = E1000_ERR_I2C;
3433         }
3434
3435         e1000_lower_i2c_clk(hw, &i2cctl);
3436
3437         /* Minimum low period of clock is 4.7 us */
3438         usec_delay(E1000_I2C_T_LOW);
3439
3440         return status;
3441 }
3442
3443 /**
3444  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3445  *  @hw: pointer to hardware structure
3446  *  @data: read data value
3447  *
3448  *  Clocks in one bit via I2C data/clock
3449  **/
3450 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3451 {
3452         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3453
3454         DEBUGFUNC("e1000_clock_in_i2c_bit");
3455
3456         e1000_raise_i2c_clk(hw, &i2cctl);
3457
3458         /* Minimum high period of clock is 4us */
3459         usec_delay(E1000_I2C_T_HIGH);
3460
3461         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3462         *data = e1000_get_i2c_data(&i2cctl);
3463
3464         e1000_lower_i2c_clk(hw, &i2cctl);
3465
3466         /* Minimum low period of clock is 4.7 us */
3467         usec_delay(E1000_I2C_T_LOW);
3468
3469         return E1000_SUCCESS;
3470 }
3471
3472 /**
3473  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3474  *  @hw: pointer to hardware structure
3475  *  @data: data value to write
3476  *
3477  *  Clocks out one bit via I2C data/clock
3478  **/
3479 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3480 {
3481         s32 status;
3482         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3483
3484         DEBUGFUNC("e1000_clock_out_i2c_bit");
3485
3486         status = e1000_set_i2c_data(hw, &i2cctl, data);
3487         if (status == E1000_SUCCESS) {
3488                 e1000_raise_i2c_clk(hw, &i2cctl);
3489
3490                 /* Minimum high period of clock is 4us */
3491                 usec_delay(E1000_I2C_T_HIGH);
3492
3493                 e1000_lower_i2c_clk(hw, &i2cctl);
3494
3495                 /* Minimum low period of clock is 4.7 us.
3496                  * This also takes care of the data hold time.
3497                  */
3498                 usec_delay(E1000_I2C_T_LOW);
3499         } else {
3500                 status = E1000_ERR_I2C;
3501                 DEBUGOUT1("I2C data was not set to %X\n", data);
3502         }
3503
3504         return status;
3505 }
3506 /**
3507  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3508  *  @hw: pointer to hardware structure
3509  *  @i2cctl: Current value of I2CCTL register
3510  *
3511  *  Raises the I2C clock line '0'->'1'
3512  **/
3513 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3514 {
3515         DEBUGFUNC("e1000_raise_i2c_clk");
3516
3517         *i2cctl |= E1000_I2C_CLK_OUT;
3518         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3519         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3520         E1000_WRITE_FLUSH(hw);
3521
3522         /* SCL rise time (1000ns) */
3523         usec_delay(E1000_I2C_T_RISE);
3524 }
3525
3526 /**
3527  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3528  *  @hw: pointer to hardware structure
3529  *  @i2cctl: Current value of I2CCTL register
3530  *
3531  *  Lowers the I2C clock line '1'->'0'
3532  **/
3533 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3534 {
3535
3536         DEBUGFUNC("e1000_lower_i2c_clk");
3537
3538         *i2cctl &= ~E1000_I2C_CLK_OUT;
3539         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3540         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3541         E1000_WRITE_FLUSH(hw);
3542
3543         /* SCL fall time (300ns) */
3544         usec_delay(E1000_I2C_T_FALL);
3545 }
3546
3547 /**
3548  *  e1000_set_i2c_data - Sets the I2C data bit
3549  *  @hw: pointer to hardware structure
3550  *  @i2cctl: Current value of I2CCTL register
3551  *  @data: I2C data value (0 or 1) to set
3552  *
3553  *  Sets the I2C data bit
3554  **/
3555 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3556 {
3557         s32 status = E1000_SUCCESS;
3558
3559         DEBUGFUNC("e1000_set_i2c_data");
3560
3561         if (data)
3562                 *i2cctl |= E1000_I2C_DATA_OUT;
3563         else
3564                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3565
3566         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3567         *i2cctl |= E1000_I2C_CLK_OE_N;
3568         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3569         E1000_WRITE_FLUSH(hw);
3570
3571         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3572         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3573
3574         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3575         if (data != e1000_get_i2c_data(i2cctl)) {
3576                 status = E1000_ERR_I2C;
3577                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3578         }
3579
3580         return status;
3581 }
3582
3583 /**
3584  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3585  *  @hw: pointer to hardware structure
3586  *  @i2cctl: Current value of I2CCTL register
3587  *
3588  *  Returns the I2C data bit value
3589  **/
3590 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3591 {
3592         bool data;
3593
3594         DEBUGFUNC("e1000_get_i2c_data");
3595
3596         if (*i2cctl & E1000_I2C_DATA_IN)
3597                 data = 1;
3598         else
3599                 data = 0;
3600
3601         return data;
3602 }
3603
3604 /**
3605  *  e1000_i2c_bus_clear - Clears the I2C bus
3606  *  @hw: pointer to hardware structure
3607  *
3608  *  Clears the I2C bus by sending nine clock pulses.
3609  *  Used when data line is stuck low.
3610  **/
3611 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3612 {
3613         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3614         u32 i;
3615
3616         DEBUGFUNC("e1000_i2c_bus_clear");
3617
3618         e1000_i2c_start(hw);
3619
3620         e1000_set_i2c_data(hw, &i2cctl, 1);
3621
3622         for (i = 0; i < 9; i++) {
3623                 e1000_raise_i2c_clk(hw, &i2cctl);
3624
3625                 /* Min high period of clock is 4us */
3626                 usec_delay(E1000_I2C_T_HIGH);
3627
3628                 e1000_lower_i2c_clk(hw, &i2cctl);
3629
3630                 /* Min low period of clock is 4.7us*/
3631                 usec_delay(E1000_I2C_T_LOW);
3632         }
3633
3634         e1000_i2c_start(hw);
3635
3636         /* Put the i2c bus back to default state */
3637         e1000_i2c_stop(hw);
3638 }
3639