lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "e1000/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 /*
  60  * Default values for port configuration
  61  */
  62 #define IGB_DEFAULT_RX_FREE_THRESH  32
  63 #define IGB_DEFAULT_RX_PTHRESH      8
  64 #define IGB_DEFAULT_RX_HTHRESH      8
  65 #define IGB_DEFAULT_RX_WTHRESH      0
  66
  67 #define IGB_DEFAULT_TX_PTHRESH      32
  68 #define IGB_DEFAULT_TX_HTHRESH      0
  69 #define IGB_DEFAULT_TX_WTHRESH      0
  70
  71 /* Bit shift and mask */
  72 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  73 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  74 #define IGB_8_BIT_WIDTH  CHAR_BIT
  75 #define IGB_8_BIT_MASK   UINT8_MAX
  76
  77 static int  eth_igb_configure(struct rte_eth_dev *dev);
  78 static int  eth_igb_start(struct rte_eth_dev *dev);
  79 static void eth_igb_stop(struct rte_eth_dev *dev);
  80 static void eth_igb_close(struct rte_eth_dev *dev);
  81 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  82 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  83 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  84 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  85 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  86                                 int wait_to_complete);
  87 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  88                                 struct rte_eth_stats *rte_stats);
  89 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  90 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_dev_info *dev_info);
  92 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
  93                                 struct rte_eth_dev_info *dev_info);
  94 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
  95                                 struct rte_eth_fc_conf *fc_conf);
  96 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  97                                 struct rte_eth_fc_conf *fc_conf);
  98 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  99 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 100 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 101 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 102                                                         void *param);
 103 static int  igb_hardware_init(struct e1000_hw *hw);
 104 static void igb_hw_control_acquire(struct e1000_hw *hw);
 105 static void igb_hw_control_release(struct e1000_hw *hw);
 106 static void igb_init_manageability(struct e1000_hw *hw);
 107 static void igb_release_manageability(struct e1000_hw *hw);
 108
 109 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 110
 111 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 112                 uint16_t vlan_id, int on);
 113 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 114 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 115
 116 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 117 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 118 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 119 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 120 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 121 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 122
 123 static int eth_igb_led_on(struct rte_eth_dev *dev);
 124 static int eth_igb_led_off(struct rte_eth_dev *dev);
 125
 126 static void igb_intr_disable(struct e1000_hw *hw);
 127 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 128 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 129                 struct ether_addr *mac_addr,
 130                 uint32_t index, uint32_t pool);
 131 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 132
 133 static void igbvf_intr_disable(struct e1000_hw *hw);
 134 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 135 static int igbvf_dev_start(struct rte_eth_dev *dev);
 136 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 137 static void igbvf_dev_close(struct rte_eth_dev *dev);
 138 static int eth_igbvf_link_update(struct e1000_hw *hw);
 139 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 140 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 141 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 142                 uint16_t vlan_id, int on);
 143 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 144 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 145 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 146                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 147                                    uint16_t reta_size);
 148 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 149                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 150                                   uint16_t reta_size);
 151
 152 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 153                         struct rte_eth_syn_filter *filter,
 154                         bool add);
 155 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 156                         struct rte_eth_syn_filter *filter);
 157 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 158                         enum rte_filter_op filter_op,
 159                         void *arg);
 160 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 161                         struct rte_eth_ntuple_filter *ntuple_filter);
 162 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 163                         struct rte_eth_ntuple_filter *ntuple_filter);
 164 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 165                         struct rte_eth_flex_filter *filter,
 166                         bool add);
 167 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 168                         struct rte_eth_flex_filter *filter);
 169 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 170                         enum rte_filter_op filter_op,
 171                         void *arg);
 172 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 173                         struct rte_eth_ntuple_filter *ntuple_filter);
 174 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 175                         struct rte_eth_ntuple_filter *ntuple_filter);
 176 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 177                         struct rte_eth_ntuple_filter *filter,
 178                         bool add);
 179 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 180                         struct rte_eth_ntuple_filter *filter);
 181 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 182                                 enum rte_filter_op filter_op,
 183                                 void *arg);
 184 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 185                         struct rte_eth_ethertype_filter *filter,
 186                         bool add);
 187 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 188                                 enum rte_filter_op filter_op,
 189                                 void *arg);
 190 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 191                         struct rte_eth_ethertype_filter *filter);
 192 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 193                      enum rte_filter_type filter_type,
 194                      enum rte_filter_op filter_op,
 195                      void *arg);
 196
 197 /*
 198  * Define VF Stats MACRO for Non "cleared on read" register
 199  */
 200 #define UPDATE_VF_STAT(reg, last, cur)            \
 201 {                                                 \
 202         u32 latest = E1000_READ_REG(hw, reg);     \
 203         cur += latest - last;                     \
 204         last = latest;                            \
 205 }
 206
 207
 208 #define IGB_FC_PAUSE_TIME 0x0680
 209 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 210 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 211
 212 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 213
 214 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 215
 216 /*
 217  * The set of PCI devices this driver supports
 218  */
 219 static const struct rte_pci_id pci_id_igb_map[] = {
 220
 221 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 222 #include "rte_pci_dev_ids.h"
 223
 224 {0},
 225 };
 226
 227 /*
 228  * The set of PCI devices this driver supports (for 82576&I350 VF)
 229  */
 230 static const struct rte_pci_id pci_id_igbvf_map[] = {
 231
 232 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 233 #include "rte_pci_dev_ids.h"
 234
 235 {0},
 236 };
 237
 238 static const struct eth_dev_ops eth_igb_ops = {
 239         .dev_configure        = eth_igb_configure,
 240         .dev_start            = eth_igb_start,
 241         .dev_stop             = eth_igb_stop,
 242         .dev_close            = eth_igb_close,
 243         .promiscuous_enable   = eth_igb_promiscuous_enable,
 244         .promiscuous_disable  = eth_igb_promiscuous_disable,
 245         .allmulticast_enable  = eth_igb_allmulticast_enable,
 246         .allmulticast_disable = eth_igb_allmulticast_disable,
 247         .link_update          = eth_igb_link_update,
 248         .stats_get            = eth_igb_stats_get,
 249         .stats_reset          = eth_igb_stats_reset,
 250         .dev_infos_get        = eth_igb_infos_get,
 251         .mtu_set              = eth_igb_mtu_set,
 252         .vlan_filter_set      = eth_igb_vlan_filter_set,
 253         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 254         .vlan_offload_set     = eth_igb_vlan_offload_set,
 255         .rx_queue_setup       = eth_igb_rx_queue_setup,
 256         .rx_queue_release     = eth_igb_rx_queue_release,
 257         .rx_queue_count       = eth_igb_rx_queue_count,
 258         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 259         .tx_queue_setup       = eth_igb_tx_queue_setup,
 260         .tx_queue_release     = eth_igb_tx_queue_release,
 261         .dev_led_on           = eth_igb_led_on,
 262         .dev_led_off          = eth_igb_led_off,
 263         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 264         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 265         .mac_addr_add         = eth_igb_rar_set,
 266         .mac_addr_remove      = eth_igb_rar_clear,
 267         .reta_update          = eth_igb_rss_reta_update,
 268         .reta_query           = eth_igb_rss_reta_query,
 269         .rss_hash_update      = eth_igb_rss_hash_update,
 270         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 271         .filter_ctrl          = eth_igb_filter_ctrl,
 272 };
 273
 274 /*
 275  * dev_ops for virtual function, bare necessities for basic vf
 276  * operation have been implemented
 277  */
 278 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 279         .dev_configure        = igbvf_dev_configure,
 280         .dev_start            = igbvf_dev_start,
 281         .dev_stop             = igbvf_dev_stop,
 282         .dev_close            = igbvf_dev_close,
 283         .link_update          = eth_igb_link_update,
 284         .stats_get            = eth_igbvf_stats_get,
 285         .stats_reset          = eth_igbvf_stats_reset,
 286         .vlan_filter_set      = igbvf_vlan_filter_set,
 287         .dev_infos_get        = eth_igbvf_infos_get,
 288         .rx_queue_setup       = eth_igb_rx_queue_setup,
 289         .rx_queue_release     = eth_igb_rx_queue_release,
 290         .tx_queue_setup       = eth_igb_tx_queue_setup,
 291         .tx_queue_release     = eth_igb_tx_queue_release,
 292 };
 293
 294 /**
 295  * Atomically reads the link status information from global
 296  * structure rte_eth_dev.
 297  *
 298  * @param dev
 299  *   - Pointer to the structure rte_eth_dev to read from.
 300  *   - Pointer to the buffer to be saved with the link status.
 301  *
 302  * @return
 303  *   - On success, zero.
 304  *   - On failure, negative value.
 305  */
 306 static inline int
 307 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 308                                 struct rte_eth_link *link)
 309 {
 310         struct rte_eth_link *dst = link;
 311         struct rte_eth_link *src = &(dev->data->dev_link);
 312
 313         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 314                                         *(uint64_t *)src) == 0)
 315                 return -1;
 316
 317         return 0;
 318 }
 319
 320 /**
 321  * Atomically writes the link status information into global
 322  * structure rte_eth_dev.
 323  *
 324  * @param dev
 325  *   - Pointer to the structure rte_eth_dev to read from.
 326  *   - Pointer to the buffer to be saved with the link status.
 327  *
 328  * @return
 329  *   - On success, zero.
 330  *   - On failure, negative value.
 331  */
 332 static inline int
 333 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 334                                 struct rte_eth_link *link)
 335 {
 336         struct rte_eth_link *dst = &(dev->data->dev_link);
 337         struct rte_eth_link *src = link;
 338
 339         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 340                                         *(uint64_t *)src) == 0)
 341                 return -1;
 342
 343         return 0;
 344 }
 345
 346 static inline void
 347 igb_intr_enable(struct rte_eth_dev *dev)
 348 {
 349         struct e1000_interrupt *intr =
 350                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 351         struct e1000_hw *hw =
 352                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 353
 354         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 355         E1000_WRITE_FLUSH(hw);
 356 }
 357
 358 static void
 359 igb_intr_disable(struct e1000_hw *hw)
 360 {
 361         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 362         E1000_WRITE_FLUSH(hw);
 363 }
 364
 365 static inline int32_t
 366 igb_pf_reset_hw(struct e1000_hw *hw)
 367 {
 368         uint32_t ctrl_ext;
 369         int32_t status;
 370
 371         status = e1000_reset_hw(hw);
 372
 373         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 374         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 375         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 376         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 377         E1000_WRITE_FLUSH(hw);
 378
 379         return status;
 380 }
 381
 382 static void
 383 igb_identify_hardware(struct rte_eth_dev *dev)
 384 {
 385         struct e1000_hw *hw =
 386                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 387
 388         hw->vendor_id = dev->pci_dev->id.vendor_id;
 389         hw->device_id = dev->pci_dev->id.device_id;
 390         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 391         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 392
 393         e1000_set_mac_type(hw);
 394
 395         /* need to check if it is a vf device below */
 396 }
 397
 398 static int
 399 igb_reset_swfw_lock(struct e1000_hw *hw)
 400 {
 401         int ret_val;
 402
 403         /*
 404          * Do mac ops initialization manually here, since we will need
 405          * some function pointers set by this call.
 406          */
 407         ret_val = e1000_init_mac_params(hw);
 408         if (ret_val)
 409                 return ret_val;
 410
 411         /*
 412          * SMBI lock should not fail in this early stage. If this is the case,
 413          * it is due to an improper exit of the application.
 414          * So force the release of the faulty lock.
 415          */
 416         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 417                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 418         }
 419         e1000_put_hw_semaphore_generic(hw);
 420
 421         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 422                 uint16_t mask;
 423
 424                 /*
 425                  * Phy lock should not fail in this early stage. If this is the case,
 426                  * it is due to an improper exit of the application.
 427                  * So force the release of the faulty lock.
 428                  */
 429                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 430                 if (hw->bus.func > E1000_FUNC_1)
 431                         mask <<= 2;
 432                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 433                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 434                                     hw->bus.func);
 435                 }
 436                 hw->mac.ops.release_swfw_sync(hw, mask);
 437
 438                 /*
 439                  * This one is more tricky since it is common to all ports; but
 440                  * swfw_sync retries last long enough (1s) to be almost sure that if
 441                  * lock can not be taken it is due to an improper lock of the
 442                  * semaphore.
 443                  */
 444                 mask = E1000_SWFW_EEP_SM;
 445                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 446                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 447                 }
 448                 hw->mac.ops.release_swfw_sync(hw, mask);
 449         }
 450
 451         return E1000_SUCCESS;
 452 }
 453
 454 static int
 455 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 456 {
 457         int error = 0;
 458         struct rte_pci_device *pci_dev;
 459         struct e1000_hw *hw =
 460                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 461         struct e1000_vfta * shadow_vfta =
 462                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 463         struct e1000_filter_info *filter_info =
 464                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 465         uint32_t ctrl_ext;
 466
 467         pci_dev = eth_dev->pci_dev;
 468         eth_dev->dev_ops = &eth_igb_ops;
 469         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 470         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 471
 472         /* for secondary processes, we don't initialise any further as primary
 473          * has already done this work. Only check we don't need a different
 474          * RX function */
 475         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 476                 if (eth_dev->data->scattered_rx)
 477                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 478                 return 0;
 479         }
 480
 481         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 482
 483         igb_identify_hardware(eth_dev);
 484         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 485                 error = -EIO;
 486                 goto err_late;
 487         }
 488
 489         e1000_get_bus_info(hw);
 490
 491         /* Reset any pending lock */
 492         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 493                 error = -EIO;
 494                 goto err_late;
 495         }
 496
 497         /* Finish initialization */
 498         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 499                 error = -EIO;
 500                 goto err_late;
 501         }
 502
 503         hw->mac.autoneg = 1;
 504         hw->phy.autoneg_wait_to_complete = 0;
 505         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 506
 507         /* Copper options */
 508         if (hw->phy.media_type == e1000_media_type_copper) {
 509                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 510                 hw->phy.disable_polarity_correction = 0;
 511                 hw->phy.ms_type = e1000_ms_hw_default;
 512         }
 513
 514         /*
 515          * Start from a known state, this is important in reading the nvm
 516          * and mac from that.
 517          */
 518         igb_pf_reset_hw(hw);
 519
 520         /* Make sure we have a good EEPROM before we read from it */
 521         if (e1000_validate_nvm_checksum(hw) < 0) {
 522                 /*
 523                  * Some PCI-E parts fail the first check due to
 524                  * the link being in sleep state, call it again,
 525                  * if it fails a second time its a real issue.
 526                  */
 527                 if (e1000_validate_nvm_checksum(hw) < 0) {
 528                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 529                         error = -EIO;
 530                         goto err_late;
 531                 }
 532         }
 533
 534         /* Read the permanent MAC address out of the EEPROM */
 535         if (e1000_read_mac_addr(hw) != 0) {
 536                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 537                 error = -EIO;
 538                 goto err_late;
 539         }
 540
 541         /* Allocate memory for storing MAC addresses */
 542         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 543                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 544         if (eth_dev->data->mac_addrs == NULL) {
 545                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 546                                                 "store MAC addresses",
 547                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 548                 error = -ENOMEM;
 549                 goto err_late;
 550         }
 551
 552         /* Copy the permanent MAC address */
 553         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 554
 555         /* initialize the vfta */
 556         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 557
 558         /* Now initialize the hardware */
 559         if (igb_hardware_init(hw) != 0) {
 560                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 561                 rte_free(eth_dev->data->mac_addrs);
 562                 eth_dev->data->mac_addrs = NULL;
 563                 error = -ENODEV;
 564                 goto err_late;
 565         }
 566         hw->mac.get_link_status = 1;
 567
 568         /* Indicate SOL/IDER usage */
 569         if (e1000_check_reset_block(hw) < 0) {
 570                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 571                                         "SOL/IDER session");
 572         }
 573
 574         /* initialize PF if max_vfs not zero */
 575         igb_pf_host_init(eth_dev);
 576
 577         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 578         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 579         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 580         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 581         E1000_WRITE_FLUSH(hw);
 582
 583         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 584                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 585                      pci_dev->id.device_id);
 586
 587         rte_intr_callback_register(&(pci_dev->intr_handle),
 588                 eth_igb_interrupt_handler, (void *)eth_dev);
 589
 590         /* enable uio intr after callback register */
 591         rte_intr_enable(&(pci_dev->intr_handle));
 592
 593         /* enable support intr */
 594         igb_intr_enable(eth_dev);
 595
 596         TAILQ_INIT(&filter_info->flex_list);
 597         filter_info->flex_mask = 0;
 598         TAILQ_INIT(&filter_info->twotuple_list);
 599         filter_info->twotuple_mask = 0;
 600         TAILQ_INIT(&filter_info->fivetuple_list);
 601         filter_info->fivetuple_mask = 0;
 602
 603         return 0;
 604
 605 err_late:
 606         igb_hw_control_release(hw);
 607
 608         return (error);
 609 }
 610
 611 /*
 612  * Virtual Function device init
 613  */
 614 static int
 615 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 616 {
 617         struct rte_pci_device *pci_dev;
 618         struct e1000_hw *hw =
 619                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 620         int diag;
 621
 622         PMD_INIT_FUNC_TRACE();
 623
 624         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 625         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 626         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 627
 628         /* for secondary processes, we don't initialise any further as primary
 629          * has already done this work. Only check we don't need a different
 630          * RX function */
 631         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 632                 if (eth_dev->data->scattered_rx)
 633                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 634                 return 0;
 635         }
 636
 637         pci_dev = eth_dev->pci_dev;
 638
 639         hw->device_id = pci_dev->id.device_id;
 640         hw->vendor_id = pci_dev->id.vendor_id;
 641         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 642
 643         /* Initialize the shared code (base driver) */
 644         diag = e1000_setup_init_funcs(hw, TRUE);
 645         if (diag != 0) {
 646                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 647                         diag);
 648                 return -EIO;
 649         }
 650
 651         /* init_mailbox_params */
 652         hw->mbx.ops.init_params(hw);
 653
 654         /* Disable the interrupts for VF */
 655         igbvf_intr_disable(hw);
 656
 657         diag = hw->mac.ops.reset_hw(hw);
 658
 659         /* Allocate memory for storing MAC addresses */
 660         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 661                 hw->mac.rar_entry_count, 0);
 662         if (eth_dev->data->mac_addrs == NULL) {
 663                 PMD_INIT_LOG(ERR,
 664                         "Failed to allocate %d bytes needed to store MAC "
 665                         "addresses",
 666                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 667                 return -ENOMEM;
 668         }
 669
 670         /* Copy the permanent MAC address */
 671         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 672                         &eth_dev->data->mac_addrs[0]);
 673
 674         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 675                      "mac.type=%s",
 676                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 677                      pci_dev->id.device_id, "igb_mac_82576_vf");
 678
 679         return 0;
 680 }
 681
 682 static struct eth_driver rte_igb_pmd = {
 683         {
 684                 .name = "rte_igb_pmd",
 685                 .id_table = pci_id_igb_map,
 686                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 687         },
 688         .eth_dev_init = eth_igb_dev_init,
 689         .dev_private_size = sizeof(struct e1000_adapter),
 690 };
 691
 692 /*
 693  * virtual function driver struct
 694  */
 695 static struct eth_driver rte_igbvf_pmd = {
 696         {
 697                 .name = "rte_igbvf_pmd",
 698                 .id_table = pci_id_igbvf_map,
 699                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 700         },
 701         .eth_dev_init = eth_igbvf_dev_init,
 702         .dev_private_size = sizeof(struct e1000_adapter),
 703 };
 704
 705 static int
 706 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 707 {
 708         rte_eth_driver_register(&rte_igb_pmd);
 709         return 0;
 710 }
 711
 712 static void
 713 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 714 {
 715         struct e1000_hw *hw =
 716                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 717         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 718         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 719         rctl |= E1000_RCTL_VFE;
 720         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 721 }
 722
 723 /*
 724  * VF Driver initialization routine.
 725  * Invoked one at EAL init time.
 726  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 727  */
 728 static int
 729 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 730 {
 731         PMD_INIT_FUNC_TRACE();
 732
 733         rte_eth_driver_register(&rte_igbvf_pmd);
 734         return (0);
 735 }
 736
 737 static int
 738 eth_igb_configure(struct rte_eth_dev *dev)
 739 {
 740         struct e1000_interrupt *intr =
 741                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 742
 743         PMD_INIT_FUNC_TRACE();
 744         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 745         PMD_INIT_FUNC_TRACE();
 746
 747         return (0);
 748 }
 749
 750 static int
 751 eth_igb_start(struct rte_eth_dev *dev)
 752 {
 753         struct e1000_hw *hw =
 754                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 755         int ret, i, mask;
 756         uint32_t ctrl_ext;
 757
 758         PMD_INIT_FUNC_TRACE();
 759
 760         /* Power up the phy. Needed to make the link go Up */
 761         e1000_power_up_phy(hw);
 762
 763         /*
 764          * Packet Buffer Allocation (PBA)
 765          * Writing PBA sets the receive portion of the buffer
 766          * the remainder is used for the transmit buffer.
 767          */
 768         if (hw->mac.type == e1000_82575) {
 769                 uint32_t pba;
 770
 771                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 772                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 773         }
 774
 775         /* Put the address into the Receive Address Array */
 776         e1000_rar_set(hw, hw->mac.addr, 0);
 777
 778         /* Initialize the hardware */
 779         if (igb_hardware_init(hw)) {
 780                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 781                 return (-EIO);
 782         }
 783
 784         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 785
 786         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 787         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 788         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 789         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 790         E1000_WRITE_FLUSH(hw);
 791
 792         /* configure PF module if SRIOV enabled */
 793         igb_pf_host_configure(dev);
 794
 795         /* Configure for OS presence */
 796         igb_init_manageability(hw);
 797
 798         eth_igb_tx_init(dev);
 799
 800         /* This can fail when allocating mbufs for descriptor rings */
 801         ret = eth_igb_rx_init(dev);
 802         if (ret) {
 803                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 804                 igb_dev_clear_queues(dev);
 805                 return ret;
 806         }
 807
 808         e1000_clear_hw_cntrs_base_generic(hw);
 809
 810         /*
 811          * VLAN Offload Settings
 812          */
 813         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 814                         ETH_VLAN_EXTEND_MASK;
 815         eth_igb_vlan_offload_set(dev, mask);
 816
 817         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 818                 /* Enable VLAN filter since VMDq always use VLAN filter */
 819                 igb_vmdq_vlan_hw_filter_enable(dev);
 820         }
 821
 822         /*
 823          * Configure the Interrupt Moderation register (EITR) with the maximum
 824          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 825          * spurious [DMA] memory updates of RX and TX ring descriptors.
 826          *
 827          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 828          * spurious memory updates per second should be expected.
 829          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 830          *
 831          * Because interrupts are not used at all, the MSI-X is not activated
 832          * and interrupt moderation is controlled by EITR[0].
 833          *
 834          * Note that having [almost] disabled memory updates of RX and TX ring
 835          * descriptors through the Interrupt Moderation mechanism, memory
 836          * updates of ring descriptors are now moderated by the configurable
 837          * value of Write-Back Threshold registers.
 838          */
 839         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 840                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
 841                 (hw->mac.type == e1000_i211)) {
 842                 uint32_t ivar;
 843
 844                 /* Enable all RX & TX queues in the IVAR registers */
 845                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 846                 for (i = 0; i < 8; i++)
 847                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 848
 849                 /* Configure EITR with the maximum possible value (0xFFFF) */
 850                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 851         }
 852
 853         /* Setup link speed and duplex */
 854         switch (dev->data->dev_conf.link_speed) {
 855         case ETH_LINK_SPEED_AUTONEG:
 856                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 857                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 858                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 859                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 860                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 861                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 862                 else
 863                         goto error_invalid_config;
 864                 break;
 865         case ETH_LINK_SPEED_10:
 866                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 867                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 868                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 869                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 870                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 871                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 872                 else
 873                         goto error_invalid_config;
 874                 break;
 875         case ETH_LINK_SPEED_100:
 876                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 877                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 878                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 879                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 880                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 881                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 882                 else
 883                         goto error_invalid_config;
 884                 break;
 885         case ETH_LINK_SPEED_1000:
 886                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 887                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 888                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 889                 else
 890                         goto error_invalid_config;
 891                 break;
 892         case ETH_LINK_SPEED_10000:
 893         default:
 894                 goto error_invalid_config;
 895         }
 896         e1000_setup_link(hw);
 897
 898         /* check if lsc interrupt feature is enabled */
 899         if (dev->data->dev_conf.intr_conf.lsc != 0)
 900                 ret = eth_igb_lsc_interrupt_setup(dev);
 901
 902         /* resume enabled intr since hw reset */
 903         igb_intr_enable(dev);
 904
 905         PMD_INIT_LOG(DEBUG, "<<");
 906
 907         return (0);
 908
 909 error_invalid_config:
 910         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 911                      dev->data->dev_conf.link_speed,
 912                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 913         igb_dev_clear_queues(dev);
 914         return (-EINVAL);
 915 }
 916
 917 /*********************************************************************
 918  *
 919  *  This routine disables all traffic on the adapter by issuing a
 920  *  global reset on the MAC.
 921  *
 922  **********************************************************************/
 923 static void
 924 eth_igb_stop(struct rte_eth_dev *dev)
 925 {
 926         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 927         struct e1000_filter_info *filter_info =
 928                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
 929         struct rte_eth_link link;
 930         struct e1000_flex_filter *p_flex;
 931         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
 932         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
 933
 934         igb_intr_disable(hw);
 935         igb_pf_reset_hw(hw);
 936         E1000_WRITE_REG(hw, E1000_WUC, 0);
 937
 938         /* Set bit for Go Link disconnect */
 939         if (hw->mac.type >= e1000_82580) {
 940                 uint32_t phpm_reg;
 941
 942                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 943                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 944                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 945         }
 946
 947         /* Power down the phy. Needed to make the link go Down */
 948         if (hw->phy.media_type == e1000_media_type_copper)
 949                 e1000_power_down_phy(hw);
 950         else
 951                 e1000_shutdown_fiber_serdes_link(hw);
 952
 953         igb_dev_clear_queues(dev);
 954
 955         /* clear the recorded link status */
 956         memset(&link, 0, sizeof(link));
 957         rte_igb_dev_atomic_write_link_status(dev, &link);
 958
 959         /* Remove all flex filters of the device */
 960         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 961                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 962                 rte_free(p_flex);
 963         }
 964         filter_info->flex_mask = 0;
 965
 966         /* Remove all ntuple filters of the device */
 967         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
 968              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
 969                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
 970                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 971                              p_5tuple, entries);
 972                 rte_free(p_5tuple);
 973         }
 974         filter_info->fivetuple_mask = 0;
 975         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
 976              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
 977                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
 978                 TAILQ_REMOVE(&filter_info->twotuple_list,
 979                              p_2tuple, entries);
 980                 rte_free(p_2tuple);
 981         }
 982         filter_info->twotuple_mask = 0;
 983 }
 984
 985 static void
 986 eth_igb_close(struct rte_eth_dev *dev)
 987 {
 988         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 989         struct rte_eth_link link;
 990
 991         eth_igb_stop(dev);
 992         e1000_phy_hw_reset(hw);
 993         igb_release_manageability(hw);
 994         igb_hw_control_release(hw);
 995
 996         /* Clear bit for Go Link disconnect */
 997         if (hw->mac.type >= e1000_82580) {
 998                 uint32_t phpm_reg;
 999
1000                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1001                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1002                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1003         }
1004
1005         igb_dev_clear_queues(dev);
1006
1007         memset(&link, 0, sizeof(link));
1008         rte_igb_dev_atomic_write_link_status(dev, &link);
1009 }
1010
1011 static int
1012 igb_get_rx_buffer_size(struct e1000_hw *hw)
1013 {
1014         uint32_t rx_buf_size;
1015         if (hw->mac.type == e1000_82576) {
1016                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1017         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1018                 /* PBS needs to be translated according to a lookup table */
1019                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1020                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1021                 rx_buf_size = (rx_buf_size << 10);
1022         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1023                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1024         } else {
1025                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1026         }
1027
1028         return rx_buf_size;
1029 }
1030
1031 /*********************************************************************
1032  *
1033  *  Initialize the hardware
1034  *
1035  **********************************************************************/
1036 static int
1037 igb_hardware_init(struct e1000_hw *hw)
1038 {
1039         uint32_t rx_buf_size;
1040         int diag;
1041
1042         /* Let the firmware know the OS is in control */
1043         igb_hw_control_acquire(hw);
1044
1045         /*
1046          * These parameters control the automatic generation (Tx) and
1047          * response (Rx) to Ethernet PAUSE frames.
1048          * - High water mark should allow for at least two standard size (1518)
1049          *   frames to be received after sending an XOFF.
1050          * - Low water mark works best when it is very near the high water mark.
1051          *   This allows the receiver to restart by sending XON when it has
1052          *   drained a bit. Here we use an arbitrary value of 1500 which will
1053          *   restart after one full frame is pulled from the buffer. There
1054          *   could be several smaller frames in the buffer and if so they will
1055          *   not trigger the XON until their total number reduces the buffer
1056          *   by 1500.
1057          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1058          */
1059         rx_buf_size = igb_get_rx_buffer_size(hw);
1060
1061         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1062         hw->fc.low_water = hw->fc.high_water - 1500;
1063         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1064         hw->fc.send_xon = 1;
1065
1066         /* Set Flow control, use the tunable location if sane */
1067         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1068                 hw->fc.requested_mode = igb_fc_setting;
1069         else
1070                 hw->fc.requested_mode = e1000_fc_none;
1071
1072         /* Issue a global reset */
1073         igb_pf_reset_hw(hw);
1074         E1000_WRITE_REG(hw, E1000_WUC, 0);
1075
1076         diag = e1000_init_hw(hw);
1077         if (diag < 0)
1078                 return (diag);
1079
1080         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1081         e1000_get_phy_info(hw);
1082         e1000_check_for_link(hw);
1083
1084         return (0);
1085 }
1086
1087 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1088 static void
1089 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1090 {
1091         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1092         struct e1000_hw_stats *stats =
1093                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1094         int pause_frames;
1095
1096         if(hw->phy.media_type == e1000_media_type_copper ||
1097             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1098                 stats->symerrs +=
1099                     E1000_READ_REG(hw,E1000_SYMERRS);
1100                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1101         }
1102
1103         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1104         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1105         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1106         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1107
1108         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1109         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1110         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1111         stats->dc += E1000_READ_REG(hw, E1000_DC);
1112         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1113         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1114         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1115         /*
1116         ** For watchdog management we need to know if we have been
1117         ** paused during the last interval, so capture that here.
1118         */
1119         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1120         stats->xoffrxc += pause_frames;
1121         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1122         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1123         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1124         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1125         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1126         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1127         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1128         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1129         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1130         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1131         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1132         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1133
1134         /* For the 64-bit byte counters the low dword must be read first. */
1135         /* Both registers clear on the read of the high dword */
1136
1137         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1138         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1139         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1140         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1141
1142         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1143         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1144         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1145         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1146         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1147
1148         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1149         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1150
1151         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1152         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1153         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1154         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1155         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1156         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1157         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1158         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1159         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1160         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1161
1162         /* Interrupt Counts */
1163
1164         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1165         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1166         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1167         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1168         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1169         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1170         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1171         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1172         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1173
1174         /* Host to Card Statistics */
1175
1176         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1177         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1178         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1179         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1180         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1181         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1182         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1183         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1184         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1185         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1186         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1187         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1188         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1189         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1190
1191         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1192         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1193         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1194         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1195         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1196         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1197
1198         if (rte_stats == NULL)
1199                 return;
1200
1201         /* Rx Errors */
1202         rte_stats->ibadcrc = stats->crcerrs;
1203         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1204         rte_stats->imissed = stats->mpc;
1205         rte_stats->ierrors = rte_stats->ibadcrc +
1206                              rte_stats->ibadlen +
1207                              rte_stats->imissed +
1208                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1209
1210         /* Tx Errors */
1211         rte_stats->oerrors = stats->ecol + stats->latecol;
1212
1213         /* XON/XOFF pause frames */
1214         rte_stats->tx_pause_xon  = stats->xontxc;
1215         rte_stats->rx_pause_xon  = stats->xonrxc;
1216         rte_stats->tx_pause_xoff = stats->xofftxc;
1217         rte_stats->rx_pause_xoff = stats->xoffrxc;
1218
1219         rte_stats->ipackets = stats->gprc;
1220         rte_stats->opackets = stats->gptc;
1221         rte_stats->ibytes   = stats->gorc;
1222         rte_stats->obytes   = stats->gotc;
1223 }
1224
1225 static void
1226 eth_igb_stats_reset(struct rte_eth_dev *dev)
1227 {
1228         struct e1000_hw_stats *hw_stats =
1229                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1230
1231         /* HW registers are cleared on read */
1232         eth_igb_stats_get(dev, NULL);
1233
1234         /* Reset software totals */
1235         memset(hw_stats, 0, sizeof(*hw_stats));
1236 }
1237
1238 static void
1239 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1240 {
1241         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1242         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1243                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1244
1245         /* Good Rx packets, include VF loopback */
1246         UPDATE_VF_STAT(E1000_VFGPRC,
1247             hw_stats->last_gprc, hw_stats->gprc);
1248
1249         /* Good Rx octets, include VF loopback */
1250         UPDATE_VF_STAT(E1000_VFGORC,
1251             hw_stats->last_gorc, hw_stats->gorc);
1252
1253         /* Good Tx packets, include VF loopback */
1254         UPDATE_VF_STAT(E1000_VFGPTC,
1255             hw_stats->last_gptc, hw_stats->gptc);
1256
1257         /* Good Tx octets, include VF loopback */
1258         UPDATE_VF_STAT(E1000_VFGOTC,
1259             hw_stats->last_gotc, hw_stats->gotc);
1260
1261         /* Rx Multicst packets */
1262         UPDATE_VF_STAT(E1000_VFMPRC,
1263             hw_stats->last_mprc, hw_stats->mprc);
1264
1265         /* Good Rx loopback packets */
1266         UPDATE_VF_STAT(E1000_VFGPRLBC,
1267             hw_stats->last_gprlbc, hw_stats->gprlbc);
1268
1269         /* Good Rx loopback octets */
1270         UPDATE_VF_STAT(E1000_VFGORLBC,
1271             hw_stats->last_gorlbc, hw_stats->gorlbc);
1272
1273         /* Good Tx loopback packets */
1274         UPDATE_VF_STAT(E1000_VFGPTLBC,
1275             hw_stats->last_gptlbc, hw_stats->gptlbc);
1276
1277         /* Good Tx loopback octets */
1278         UPDATE_VF_STAT(E1000_VFGOTLBC,
1279             hw_stats->last_gotlbc, hw_stats->gotlbc);
1280
1281         if (rte_stats == NULL)
1282                 return;
1283
1284         rte_stats->ipackets = hw_stats->gprc;
1285         rte_stats->ibytes = hw_stats->gorc;
1286         rte_stats->opackets = hw_stats->gptc;
1287         rte_stats->obytes = hw_stats->gotc;
1288         rte_stats->imcasts = hw_stats->mprc;
1289         rte_stats->ilbpackets = hw_stats->gprlbc;
1290         rte_stats->ilbbytes = hw_stats->gorlbc;
1291         rte_stats->olbpackets = hw_stats->gptlbc;
1292         rte_stats->olbbytes = hw_stats->gotlbc;
1293
1294 }
1295
1296 static void
1297 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1298 {
1299         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1300                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1301
1302         /* Sync HW register to the last stats */
1303         eth_igbvf_stats_get(dev, NULL);
1304
1305         /* reset HW current stats*/
1306         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1307                offsetof(struct e1000_vf_stats, gprc));
1308
1309 }
1310
1311 static void
1312 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1313 {
1314         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1315
1316         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1317         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1318         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1319         dev_info->rx_offload_capa =
1320                 DEV_RX_OFFLOAD_VLAN_STRIP |
1321                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1322                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1323                 DEV_RX_OFFLOAD_TCP_CKSUM;
1324         dev_info->tx_offload_capa =
1325                 DEV_TX_OFFLOAD_VLAN_INSERT |
1326                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1327                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1328                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1329                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1330
1331         switch (hw->mac.type) {
1332         case e1000_82575:
1333                 dev_info->max_rx_queues = 4;
1334                 dev_info->max_tx_queues = 4;
1335                 dev_info->max_vmdq_pools = 0;
1336                 break;
1337
1338         case e1000_82576:
1339                 dev_info->max_rx_queues = 16;
1340                 dev_info->max_tx_queues = 16;
1341                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1342                 dev_info->vmdq_queue_num = 16;
1343                 break;
1344
1345         case e1000_82580:
1346                 dev_info->max_rx_queues = 8;
1347                 dev_info->max_tx_queues = 8;
1348                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1349                 dev_info->vmdq_queue_num = 8;
1350                 break;
1351
1352         case e1000_i350:
1353                 dev_info->max_rx_queues = 8;
1354                 dev_info->max_tx_queues = 8;
1355                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1356                 dev_info->vmdq_queue_num = 8;
1357                 break;
1358
1359         case e1000_i354:
1360                 dev_info->max_rx_queues = 8;
1361                 dev_info->max_tx_queues = 8;
1362                 break;
1363
1364         case e1000_i210:
1365                 dev_info->max_rx_queues = 4;
1366                 dev_info->max_tx_queues = 4;
1367                 dev_info->max_vmdq_pools = 0;
1368                 break;
1369
1370         case e1000_i211:
1371                 dev_info->max_rx_queues = 2;
1372                 dev_info->max_tx_queues = 2;
1373                 dev_info->max_vmdq_pools = 0;
1374                 break;
1375
1376         default:
1377                 /* Should not happen */
1378                 break;
1379         }
1380         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1381         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1382
1383         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1384                 .rx_thresh = {
1385                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1386                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1387                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1388                 },
1389                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1390                 .rx_drop_en = 0,
1391         };
1392
1393         dev_info->default_txconf = (struct rte_eth_txconf) {
1394                 .tx_thresh = {
1395                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1396                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1397                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1398                 },
1399                 .txq_flags = 0,
1400         };
1401 }
1402
1403 static void
1404 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1405 {
1406         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1407
1408         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1409         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1410         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1411         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1412                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1413                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1414                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1415         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1416                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1417                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1418                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1419                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1420         switch (hw->mac.type) {
1421         case e1000_vfadapt:
1422                 dev_info->max_rx_queues = 2;
1423                 dev_info->max_tx_queues = 2;
1424                 break;
1425         case e1000_vfadapt_i350:
1426                 dev_info->max_rx_queues = 1;
1427                 dev_info->max_tx_queues = 1;
1428                 break;
1429         default:
1430                 /* Should not happen */
1431                 break;
1432         }
1433
1434         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1435                 .rx_thresh = {
1436                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1437                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1438                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1439                 },
1440                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1441                 .rx_drop_en = 0,
1442         };
1443
1444         dev_info->default_txconf = (struct rte_eth_txconf) {
1445                 .tx_thresh = {
1446                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1447                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1448                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1449                 },
1450                 .txq_flags = 0,
1451         };
1452 }
1453
1454 /* return 0 means link status changed, -1 means not changed */
1455 static int
1456 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1457 {
1458         struct e1000_hw *hw =
1459                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1460         struct rte_eth_link link, old;
1461         int link_check, count;
1462
1463         link_check = 0;
1464         hw->mac.get_link_status = 1;
1465
1466         /* possible wait-to-complete in up to 9 seconds */
1467         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1468                 /* Read the real link status */
1469                 switch (hw->phy.media_type) {
1470                 case e1000_media_type_copper:
1471                         /* Do the work to read phy */
1472                         e1000_check_for_link(hw);
1473                         link_check = !hw->mac.get_link_status;
1474                         break;
1475
1476                 case e1000_media_type_fiber:
1477                         e1000_check_for_link(hw);
1478                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1479                                       E1000_STATUS_LU);
1480                         break;
1481
1482                 case e1000_media_type_internal_serdes:
1483                         e1000_check_for_link(hw);
1484                         link_check = hw->mac.serdes_has_link;
1485                         break;
1486
1487                 /* VF device is type_unknown */
1488                 case e1000_media_type_unknown:
1489                         eth_igbvf_link_update(hw);
1490                         link_check = !hw->mac.get_link_status;
1491                         break;
1492
1493                 default:
1494                         break;
1495                 }
1496                 if (link_check || wait_to_complete == 0)
1497                         break;
1498                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1499         }
1500         memset(&link, 0, sizeof(link));
1501         rte_igb_dev_atomic_read_link_status(dev, &link);
1502         old = link;
1503
1504         /* Now we check if a transition has happened */
1505         if (link_check) {
1506                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1507                                           &link.link_duplex);
1508                 link.link_status = 1;
1509         } else if (!link_check) {
1510                 link.link_speed = 0;
1511                 link.link_duplex = 0;
1512                 link.link_status = 0;
1513         }
1514         rte_igb_dev_atomic_write_link_status(dev, &link);
1515
1516         /* not changed */
1517         if (old.link_status == link.link_status)
1518                 return -1;
1519
1520         /* changed */
1521         return 0;
1522 }
1523
1524 /*
1525  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1526  * For ASF and Pass Through versions of f/w this means
1527  * that the driver is loaded.
1528  */
1529 static void
1530 igb_hw_control_acquire(struct e1000_hw *hw)
1531 {
1532         uint32_t ctrl_ext;
1533
1534         /* Let firmware know the driver has taken over */
1535         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1536         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1537 }
1538
1539 /*
1540  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1541  * For ASF and Pass Through versions of f/w this means that the
1542  * driver is no longer loaded.
1543  */
1544 static void
1545 igb_hw_control_release(struct e1000_hw *hw)
1546 {
1547         uint32_t ctrl_ext;
1548
1549         /* Let firmware taken over control of h/w */
1550         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1551         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1552                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1553 }
1554
1555 /*
1556  * Bit of a misnomer, what this really means is
1557  * to enable OS management of the system... aka
1558  * to disable special hardware management features.
1559  */
1560 static void
1561 igb_init_manageability(struct e1000_hw *hw)
1562 {
1563         if (e1000_enable_mng_pass_thru(hw)) {
1564                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1565                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1566
1567                 /* disable hardware interception of ARP */
1568                 manc &= ~(E1000_MANC_ARP_EN);
1569
1570                 /* enable receiving management packets to the host */
1571                 manc |= E1000_MANC_EN_MNG2HOST;
1572                 manc2h |= 1 << 5;  /* Mng Port 623 */
1573                 manc2h |= 1 << 6;  /* Mng Port 664 */
1574                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1575                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1576         }
1577 }
1578
1579 static void
1580 igb_release_manageability(struct e1000_hw *hw)
1581 {
1582         if (e1000_enable_mng_pass_thru(hw)) {
1583                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1584
1585                 manc |= E1000_MANC_ARP_EN;
1586                 manc &= ~E1000_MANC_EN_MNG2HOST;
1587
1588                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1589         }
1590 }
1591
1592 static void
1593 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1594 {
1595         struct e1000_hw *hw =
1596                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1597         uint32_t rctl;
1598
1599         rctl = E1000_READ_REG(hw, E1000_RCTL);
1600         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1601         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1602 }
1603
1604 static void
1605 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1606 {
1607         struct e1000_hw *hw =
1608                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1609         uint32_t rctl;
1610
1611         rctl = E1000_READ_REG(hw, E1000_RCTL);
1612         rctl &= (~E1000_RCTL_UPE);
1613         if (dev->data->all_multicast == 1)
1614                 rctl |= E1000_RCTL_MPE;
1615         else
1616                 rctl &= (~E1000_RCTL_MPE);
1617         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1618 }
1619
1620 static void
1621 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1622 {
1623         struct e1000_hw *hw =
1624                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1625         uint32_t rctl;
1626
1627         rctl = E1000_READ_REG(hw, E1000_RCTL);
1628         rctl |= E1000_RCTL_MPE;
1629         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1630 }
1631
1632 static void
1633 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1634 {
1635         struct e1000_hw *hw =
1636                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637         uint32_t rctl;
1638
1639         if (dev->data->promiscuous == 1)
1640                 return; /* must remain in all_multicast mode */
1641         rctl = E1000_READ_REG(hw, E1000_RCTL);
1642         rctl &= (~E1000_RCTL_MPE);
1643         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1644 }
1645
1646 static int
1647 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1648 {
1649         struct e1000_hw *hw =
1650                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1651         struct e1000_vfta * shadow_vfta =
1652                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1653         uint32_t vfta;
1654         uint32_t vid_idx;
1655         uint32_t vid_bit;
1656
1657         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1658                               E1000_VFTA_ENTRY_MASK);
1659         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1660         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1661         if (on)
1662                 vfta |= vid_bit;
1663         else
1664                 vfta &= ~vid_bit;
1665         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1666
1667         /* update local VFTA copy */
1668         shadow_vfta->vfta[vid_idx] = vfta;
1669
1670         return 0;
1671 }
1672
1673 static void
1674 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1675 {
1676         struct e1000_hw *hw =
1677                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1678         uint32_t reg = ETHER_TYPE_VLAN ;
1679
1680         reg |= (tpid << 16);
1681         E1000_WRITE_REG(hw, E1000_VET, reg);
1682 }
1683
1684 static void
1685 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1686 {
1687         struct e1000_hw *hw =
1688                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1689         uint32_t reg;
1690
1691         /* Filter Table Disable */
1692         reg = E1000_READ_REG(hw, E1000_RCTL);
1693         reg &= ~E1000_RCTL_CFIEN;
1694         reg &= ~E1000_RCTL_VFE;
1695         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1696 }
1697
1698 static void
1699 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1700 {
1701         struct e1000_hw *hw =
1702                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1703         struct e1000_vfta * shadow_vfta =
1704                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1705         uint32_t reg;
1706         int i;
1707
1708         /* Filter Table Enable, CFI not used for packet acceptance */
1709         reg = E1000_READ_REG(hw, E1000_RCTL);
1710         reg &= ~E1000_RCTL_CFIEN;
1711         reg |= E1000_RCTL_VFE;
1712         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1713
1714         /* restore VFTA table */
1715         for (i = 0; i < IGB_VFTA_SIZE; i++)
1716                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1717 }
1718
1719 static void
1720 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1721 {
1722         struct e1000_hw *hw =
1723                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1724         uint32_t reg;
1725
1726         /* VLAN Mode Disable */
1727         reg = E1000_READ_REG(hw, E1000_CTRL);
1728         reg &= ~E1000_CTRL_VME;
1729         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1730 }
1731
1732 static void
1733 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1734 {
1735         struct e1000_hw *hw =
1736                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737         uint32_t reg;
1738
1739         /* VLAN Mode Enable */
1740         reg = E1000_READ_REG(hw, E1000_CTRL);
1741         reg |= E1000_CTRL_VME;
1742         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1743 }
1744
1745 static void
1746 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1747 {
1748         struct e1000_hw *hw =
1749                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750         uint32_t reg;
1751
1752         /* CTRL_EXT: Extended VLAN */
1753         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1754         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1755         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1756
1757         /* Update maximum packet length */
1758         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1759                 E1000_WRITE_REG(hw, E1000_RLPML,
1760                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1761                                                 VLAN_TAG_SIZE);
1762 }
1763
1764 static void
1765 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1766 {
1767         struct e1000_hw *hw =
1768                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1769         uint32_t reg;
1770
1771         /* CTRL_EXT: Extended VLAN */
1772         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1773         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1774         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1775
1776         /* Update maximum packet length */
1777         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1778                 E1000_WRITE_REG(hw, E1000_RLPML,
1779                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1780                                                 2 * VLAN_TAG_SIZE);
1781 }
1782
1783 static void
1784 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1785 {
1786         if(mask & ETH_VLAN_STRIP_MASK){
1787                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1788                         igb_vlan_hw_strip_enable(dev);
1789                 else
1790                         igb_vlan_hw_strip_disable(dev);
1791         }
1792
1793         if(mask & ETH_VLAN_FILTER_MASK){
1794                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1795                         igb_vlan_hw_filter_enable(dev);
1796                 else
1797                         igb_vlan_hw_filter_disable(dev);
1798         }
1799
1800         if(mask & ETH_VLAN_EXTEND_MASK){
1801                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1802                         igb_vlan_hw_extend_enable(dev);
1803                 else
1804                         igb_vlan_hw_extend_disable(dev);
1805         }
1806 }
1807
1808
1809 /**
1810  * It enables the interrupt mask and then enable the interrupt.
1811  *
1812  * @param dev
1813  *  Pointer to struct rte_eth_dev.
1814  *
1815  * @return
1816  *  - On success, zero.
1817  *  - On failure, a negative value.
1818  */
1819 static int
1820 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1821 {
1822         struct e1000_interrupt *intr =
1823                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1824
1825         intr->mask |= E1000_ICR_LSC;
1826
1827         return 0;
1828 }
1829
1830 /*
1831  * It reads ICR and gets interrupt causes, check it and set a bit flag
1832  * to update link status.
1833  *
1834  * @param dev
1835  *  Pointer to struct rte_eth_dev.
1836  *
1837  * @return
1838  *  - On success, zero.
1839  *  - On failure, a negative value.
1840  */
1841 static int
1842 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1843 {
1844         uint32_t icr;
1845         struct e1000_hw *hw =
1846                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847         struct e1000_interrupt *intr =
1848                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1849
1850         igb_intr_disable(hw);
1851
1852         /* read-on-clear nic registers here */
1853         icr = E1000_READ_REG(hw, E1000_ICR);
1854
1855         intr->flags = 0;
1856         if (icr & E1000_ICR_LSC) {
1857                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1858         }
1859
1860         if (icr & E1000_ICR_VMMB)
1861                 intr->flags |= E1000_FLAG_MAILBOX;
1862
1863         return 0;
1864 }
1865
1866 /*
1867  * It executes link_update after knowing an interrupt is prsent.
1868  *
1869  * @param dev
1870  *  Pointer to struct rte_eth_dev.
1871  *
1872  * @return
1873  *  - On success, zero.
1874  *  - On failure, a negative value.
1875  */
1876 static int
1877 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1878 {
1879         struct e1000_hw *hw =
1880                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1881         struct e1000_interrupt *intr =
1882                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1883         uint32_t tctl, rctl;
1884         struct rte_eth_link link;
1885         int ret;
1886
1887         if (intr->flags & E1000_FLAG_MAILBOX) {
1888                 igb_pf_mbx_process(dev);
1889                 intr->flags &= ~E1000_FLAG_MAILBOX;
1890         }
1891
1892         igb_intr_enable(dev);
1893         rte_intr_enable(&(dev->pci_dev->intr_handle));
1894
1895         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1896                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1897
1898                 /* set get_link_status to check register later */
1899                 hw->mac.get_link_status = 1;
1900                 ret = eth_igb_link_update(dev, 0);
1901
1902                 /* check if link has changed */
1903                 if (ret < 0)
1904                         return 0;
1905
1906                 memset(&link, 0, sizeof(link));
1907                 rte_igb_dev_atomic_read_link_status(dev, &link);
1908                 if (link.link_status) {
1909                         PMD_INIT_LOG(INFO,
1910                                      " Port %d: Link Up - speed %u Mbps - %s",
1911                                      dev->data->port_id,
1912                                      (unsigned)link.link_speed,
1913                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1914                                      "full-duplex" : "half-duplex");
1915                 } else {
1916                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
1917                                      dev->data->port_id);
1918                 }
1919                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1920                              dev->pci_dev->addr.domain,
1921                              dev->pci_dev->addr.bus,
1922                              dev->pci_dev->addr.devid,
1923                              dev->pci_dev->addr.function);
1924                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1925                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1926                 if (link.link_status) {
1927                         /* enable Tx/Rx */
1928                         tctl |= E1000_TCTL_EN;
1929                         rctl |= E1000_RCTL_EN;
1930                 } else {
1931                         /* disable Tx/Rx */
1932                         tctl &= ~E1000_TCTL_EN;
1933                         rctl &= ~E1000_RCTL_EN;
1934                 }
1935                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1936                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1937                 E1000_WRITE_FLUSH(hw);
1938                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1939         }
1940
1941         return 0;
1942 }
1943
1944 /**
1945  * Interrupt handler which shall be registered at first.
1946  *
1947  * @param handle
1948  *  Pointer to interrupt handle.
1949  * @param param
1950  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1951  *
1952  * @return
1953  *  void
1954  */
1955 static void
1956 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1957                                                         void *param)
1958 {
1959         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1960
1961         eth_igb_interrupt_get_status(dev);
1962         eth_igb_interrupt_action(dev);
1963 }
1964
1965 static int
1966 eth_igb_led_on(struct rte_eth_dev *dev)
1967 {
1968         struct e1000_hw *hw;
1969
1970         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1971         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1972 }
1973
1974 static int
1975 eth_igb_led_off(struct rte_eth_dev *dev)
1976 {
1977         struct e1000_hw *hw;
1978
1979         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1980         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1981 }
1982
1983 static int
1984 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1985 {
1986         struct e1000_hw *hw;
1987         uint32_t ctrl;
1988         int tx_pause;
1989         int rx_pause;
1990
1991         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1992         fc_conf->pause_time = hw->fc.pause_time;
1993         fc_conf->high_water = hw->fc.high_water;
1994         fc_conf->low_water = hw->fc.low_water;
1995         fc_conf->send_xon = hw->fc.send_xon;
1996         fc_conf->autoneg = hw->mac.autoneg;
1997
1998         /*
1999          * Return rx_pause and tx_pause status according to actual setting of
2000          * the TFCE and RFCE bits in the CTRL register.
2001          */
2002         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2003         if (ctrl & E1000_CTRL_TFCE)
2004                 tx_pause = 1;
2005         else
2006                 tx_pause = 0;
2007
2008         if (ctrl & E1000_CTRL_RFCE)
2009                 rx_pause = 1;
2010         else
2011                 rx_pause = 0;
2012
2013         if (rx_pause && tx_pause)
2014                 fc_conf->mode = RTE_FC_FULL;
2015         else if (rx_pause)
2016                 fc_conf->mode = RTE_FC_RX_PAUSE;
2017         else if (tx_pause)
2018                 fc_conf->mode = RTE_FC_TX_PAUSE;
2019         else
2020                 fc_conf->mode = RTE_FC_NONE;
2021
2022         return 0;
2023 }
2024
2025 static int
2026 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2027 {
2028         struct e1000_hw *hw;
2029         int err;
2030         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2031                 e1000_fc_none,
2032                 e1000_fc_rx_pause,
2033                 e1000_fc_tx_pause,
2034                 e1000_fc_full
2035         };
2036         uint32_t rx_buf_size;
2037         uint32_t max_high_water;
2038         uint32_t rctl;
2039
2040         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2041         if (fc_conf->autoneg != hw->mac.autoneg)
2042                 return -ENOTSUP;
2043         rx_buf_size = igb_get_rx_buffer_size(hw);
2044         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2045
2046         /* At least reserve one Ethernet frame for watermark */
2047         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2048         if ((fc_conf->high_water > max_high_water) ||
2049             (fc_conf->high_water < fc_conf->low_water)) {
2050                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2051                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2052                 return (-EINVAL);
2053         }
2054
2055         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2056         hw->fc.pause_time     = fc_conf->pause_time;
2057         hw->fc.high_water     = fc_conf->high_water;
2058         hw->fc.low_water      = fc_conf->low_water;
2059         hw->fc.send_xon       = fc_conf->send_xon;
2060
2061         err = e1000_setup_link_generic(hw);
2062         if (err == E1000_SUCCESS) {
2063
2064                 /* check if we want to forward MAC frames - driver doesn't have native
2065                  * capability to do that, so we'll write the registers ourselves */
2066
2067                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2068
2069                 /* set or clear MFLCN.PMCF bit depending on configuration */
2070                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2071                         rctl |= E1000_RCTL_PMCF;
2072                 else
2073                         rctl &= ~E1000_RCTL_PMCF;
2074
2075                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2076                 E1000_WRITE_FLUSH(hw);
2077
2078                 return 0;
2079         }
2080
2081         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2082         return (-EIO);
2083 }
2084
2085 #define E1000_RAH_POOLSEL_SHIFT      (18)
2086 static void
2087 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2088                 uint32_t index, __rte_unused uint32_t pool)
2089 {
2090         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091         uint32_t rah;
2092
2093         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2094         rah = E1000_READ_REG(hw, E1000_RAH(index));
2095         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2096         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2097 }
2098
2099 static void
2100 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2101 {
2102         uint8_t addr[ETHER_ADDR_LEN];
2103         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2104
2105         memset(addr, 0, sizeof(addr));
2106
2107         e1000_rar_set(hw, addr, index);
2108 }
2109
2110 /*
2111  * Virtual Function operations
2112  */
2113 static void
2114 igbvf_intr_disable(struct e1000_hw *hw)
2115 {
2116         PMD_INIT_FUNC_TRACE();
2117
2118         /* Clear interrupt mask to stop from interrupts being generated */
2119         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2120
2121         E1000_WRITE_FLUSH(hw);
2122 }
2123
2124 static void
2125 igbvf_stop_adapter(struct rte_eth_dev *dev)
2126 {
2127         u32 reg_val;
2128         u16 i;
2129         struct rte_eth_dev_info dev_info;
2130         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2131
2132         memset(&dev_info, 0, sizeof(dev_info));
2133         eth_igbvf_infos_get(dev, &dev_info);
2134
2135         /* Clear interrupt mask to stop from interrupts being generated */
2136         igbvf_intr_disable(hw);
2137
2138         /* Clear any pending interrupts, flush previous writes */
2139         E1000_READ_REG(hw, E1000_EICR);
2140
2141         /* Disable the transmit unit.  Each queue must be disabled. */
2142         for (i = 0; i < dev_info.max_tx_queues; i++)
2143                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2144
2145         /* Disable the receive unit by stopping each queue */
2146         for (i = 0; i < dev_info.max_rx_queues; i++) {
2147                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2148                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2149                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2150                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2151                         ;
2152         }
2153
2154         /* flush all queues disables */
2155         E1000_WRITE_FLUSH(hw);
2156         msec_delay(2);
2157 }
2158
2159 static int eth_igbvf_link_update(struct e1000_hw *hw)
2160 {
2161         struct e1000_mbx_info *mbx = &hw->mbx;
2162         struct e1000_mac_info *mac = &hw->mac;
2163         int ret_val = E1000_SUCCESS;
2164
2165         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2166
2167         /*
2168          * We only want to run this if there has been a rst asserted.
2169          * in this case that could mean a link change, device reset,
2170          * or a virtual function reset
2171          */
2172
2173         /* If we were hit with a reset or timeout drop the link */
2174         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2175                 mac->get_link_status = TRUE;
2176
2177         if (!mac->get_link_status)
2178                 goto out;
2179
2180         /* if link status is down no point in checking to see if pf is up */
2181         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2182                 goto out;
2183
2184         /* if we passed all the tests above then the link is up and we no
2185          * longer need to check for link */
2186         mac->get_link_status = FALSE;
2187
2188 out:
2189         return ret_val;
2190 }
2191
2192
2193 static int
2194 igbvf_dev_configure(struct rte_eth_dev *dev)
2195 {
2196         struct rte_eth_conf* conf = &dev->data->dev_conf;
2197
2198         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2199                      dev->data->port_id);
2200
2201         /*
2202          * VF has no ability to enable/disable HW CRC
2203          * Keep the persistent behavior the same as Host PF
2204          */
2205 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2206         if (!conf->rxmode.hw_strip_crc) {
2207                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2208                 conf->rxmode.hw_strip_crc = 1;
2209         }
2210 #else
2211         if (conf->rxmode.hw_strip_crc) {
2212                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2213                 conf->rxmode.hw_strip_crc = 0;
2214         }
2215 #endif
2216
2217         return 0;
2218 }
2219
2220 static int
2221 igbvf_dev_start(struct rte_eth_dev *dev)
2222 {
2223         struct e1000_hw *hw =
2224                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2225         int ret;
2226
2227         PMD_INIT_FUNC_TRACE();
2228
2229         hw->mac.ops.reset_hw(hw);
2230
2231         /* Set all vfta */
2232         igbvf_set_vfta_all(dev,1);
2233
2234         eth_igbvf_tx_init(dev);
2235
2236         /* This can fail when allocating mbufs for descriptor rings */
2237         ret = eth_igbvf_rx_init(dev);
2238         if (ret) {
2239                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2240                 igb_dev_clear_queues(dev);
2241                 return ret;
2242         }
2243
2244         return 0;
2245 }
2246
2247 static void
2248 igbvf_dev_stop(struct rte_eth_dev *dev)
2249 {
2250         PMD_INIT_FUNC_TRACE();
2251
2252         igbvf_stop_adapter(dev);
2253
2254         /*
2255           * Clear what we set, but we still keep shadow_vfta to
2256           * restore after device starts
2257           */
2258         igbvf_set_vfta_all(dev,0);
2259
2260         igb_dev_clear_queues(dev);
2261 }
2262
2263 static void
2264 igbvf_dev_close(struct rte_eth_dev *dev)
2265 {
2266         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2267
2268         PMD_INIT_FUNC_TRACE();
2269
2270         e1000_reset_hw(hw);
2271
2272         igbvf_dev_stop(dev);
2273 }
2274
2275 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2276 {
2277         struct e1000_mbx_info *mbx = &hw->mbx;
2278         uint32_t msgbuf[2];
2279
2280         /* After set vlan, vlan strip will also be enabled in igb driver*/
2281         msgbuf[0] = E1000_VF_SET_VLAN;
2282         msgbuf[1] = vid;
2283         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2284         if (on)
2285                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2286
2287         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2288 }
2289
2290 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2291 {
2292         struct e1000_hw *hw =
2293                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2294         struct e1000_vfta * shadow_vfta =
2295                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2296         int i = 0, j = 0, vfta = 0, mask = 1;
2297
2298         for (i = 0; i < IGB_VFTA_SIZE; i++){
2299                 vfta = shadow_vfta->vfta[i];
2300                 if(vfta){
2301                         mask = 1;
2302                         for (j = 0; j < 32; j++){
2303                                 if(vfta & mask)
2304                                         igbvf_set_vfta(hw,
2305                                                 (uint16_t)((i<<5)+j), on);
2306                                 mask<<=1;
2307                         }
2308                 }
2309         }
2310
2311 }
2312
2313 static int
2314 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2315 {
2316         struct e1000_hw *hw =
2317                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2318         struct e1000_vfta * shadow_vfta =
2319                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2320         uint32_t vid_idx = 0;
2321         uint32_t vid_bit = 0;
2322         int ret = 0;
2323
2324         PMD_INIT_FUNC_TRACE();
2325
2326         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2327         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2328         if(ret){
2329                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2330                 return ret;
2331         }
2332         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2333         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2334
2335         /*Save what we set and retore it after device reset*/
2336         if (on)
2337                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2338         else
2339                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2340
2341         return 0;
2342 }
2343
2344 static int
2345 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2346                         struct rte_eth_rss_reta_entry64 *reta_conf,
2347                         uint16_t reta_size)
2348 {
2349         uint8_t i, j, mask;
2350         uint32_t reta, r;
2351         uint16_t idx, shift;
2352         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2353
2354         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2355                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2356                         "(%d) doesn't match the number hardware can supported "
2357                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2358                 return -EINVAL;
2359         }
2360
2361         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2362                 idx = i / RTE_RETA_GROUP_SIZE;
2363                 shift = i % RTE_RETA_GROUP_SIZE;
2364                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2365                                                 IGB_4_BIT_MASK);
2366                 if (!mask)
2367                         continue;
2368                 if (mask == IGB_4_BIT_MASK)
2369                         r = 0;
2370                 else
2371                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2372                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2373                         if (mask & (0x1 << j))
2374                                 reta |= reta_conf[idx].reta[shift + j] <<
2375                                                         (CHAR_BIT * j);
2376                         else
2377                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2378                 }
2379                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2380         }
2381
2382         return 0;
2383 }
2384
2385 static int
2386 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2387                        struct rte_eth_rss_reta_entry64 *reta_conf,
2388                        uint16_t reta_size)
2389 {
2390         uint8_t i, j, mask;
2391         uint32_t reta;
2392         uint16_t idx, shift;
2393         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2394
2395         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2396                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2397                         "(%d) doesn't match the number hardware can supported "
2398                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2399                 return -EINVAL;
2400         }
2401
2402         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2403                 idx = i / RTE_RETA_GROUP_SIZE;
2404                 shift = i % RTE_RETA_GROUP_SIZE;
2405                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2406                                                 IGB_4_BIT_MASK);
2407                 if (!mask)
2408                         continue;
2409                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2410                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2411                         if (mask & (0x1 << j))
2412                                 reta_conf[idx].reta[shift + j] =
2413                                         ((reta >> (CHAR_BIT * j)) &
2414                                                 IGB_8_BIT_MASK);
2415                 }
2416         }
2417
2418         return 0;
2419 }
2420
2421 #define MAC_TYPE_FILTER_SUP(type)    do {\
2422         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2423                 (type) != e1000_82576)\
2424                 return -ENOTSUP;\
2425 } while (0)
2426
2427 static int
2428 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2429                         struct rte_eth_syn_filter *filter,
2430                         bool add)
2431 {
2432         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2433         uint32_t synqf, rfctl;
2434
2435         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2436                 return -EINVAL;
2437
2438         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2439
2440         if (add) {
2441                 if (synqf & E1000_SYN_FILTER_ENABLE)
2442                         return -EINVAL;
2443
2444                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2445                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2446
2447                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2448                 if (filter->hig_pri)
2449                         rfctl |= E1000_RFCTL_SYNQFP;
2450                 else
2451                         rfctl &= ~E1000_RFCTL_SYNQFP;
2452
2453                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2454         } else {
2455                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2456                         return -ENOENT;
2457                 synqf = 0;
2458         }
2459
2460         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2461         E1000_WRITE_FLUSH(hw);
2462         return 0;
2463 }
2464
2465 static int
2466 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2467                         struct rte_eth_syn_filter *filter)
2468 {
2469         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2470         uint32_t synqf, rfctl;
2471
2472         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2473         if (synqf & E1000_SYN_FILTER_ENABLE) {
2474                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2475                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2476                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2477                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2478                 return 0;
2479         }
2480
2481         return -ENOENT;
2482 }
2483
2484 static int
2485 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2486                         enum rte_filter_op filter_op,
2487                         void *arg)
2488 {
2489         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490         int ret;
2491
2492         MAC_TYPE_FILTER_SUP(hw->mac.type);
2493
2494         if (filter_op == RTE_ETH_FILTER_NOP)
2495                 return 0;
2496
2497         if (arg == NULL) {
2498                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2499                             filter_op);
2500                 return -EINVAL;
2501         }
2502
2503         switch (filter_op) {
2504         case RTE_ETH_FILTER_ADD:
2505                 ret = eth_igb_syn_filter_set(dev,
2506                                 (struct rte_eth_syn_filter *)arg,
2507                                 TRUE);
2508                 break;
2509         case RTE_ETH_FILTER_DELETE:
2510                 ret = eth_igb_syn_filter_set(dev,
2511                                 (struct rte_eth_syn_filter *)arg,
2512                                 FALSE);
2513                 break;
2514         case RTE_ETH_FILTER_GET:
2515                 ret = eth_igb_syn_filter_get(dev,
2516                                 (struct rte_eth_syn_filter *)arg);
2517                 break;
2518         default:
2519                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
2520                 ret = -EINVAL;
2521                 break;
2522         }
2523
2524         return ret;
2525 }
2526
2527 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2528         if ((type) != e1000_82580 && (type) != e1000_i350)\
2529                 return -ENOSYS; \
2530 } while (0)
2531
2532 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
2533 static inline int
2534 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
2535                         struct e1000_2tuple_filter_info *filter_info)
2536 {
2537         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2538                 return -EINVAL;
2539         if (filter->priority > E1000_2TUPLE_MAX_PRI)
2540                 return -EINVAL;  /* filter index is out of range. */
2541         if (filter->tcp_flags > TCP_FLAG_ALL)
2542                 return -EINVAL;  /* flags is invalid. */
2543
2544         switch (filter->dst_port_mask) {
2545         case UINT16_MAX:
2546                 filter_info->dst_port_mask = 0;
2547                 filter_info->dst_port = filter->dst_port;
2548                 break;
2549         case 0:
2550                 filter_info->dst_port_mask = 1;
2551                 break;
2552         default:
2553                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2554                 return -EINVAL;
2555         }
2556
2557         switch (filter->proto_mask) {
2558         case UINT8_MAX:
2559                 filter_info->proto_mask = 0;
2560                 filter_info->proto = filter->proto;
2561                 break;
2562         case 0:
2563                 filter_info->proto_mask = 1;
2564                 break;
2565         default:
2566                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2567                 return -EINVAL;
2568         }
2569
2570         filter_info->priority = (uint8_t)filter->priority;
2571         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
2572                 filter_info->tcp_flags = filter->tcp_flags;
2573         else
2574                 filter_info->tcp_flags = 0;
2575
2576         return 0;
2577 }
2578
2579 static inline struct e1000_2tuple_filter *
2580 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
2581                         struct e1000_2tuple_filter_info *key)
2582 {
2583         struct e1000_2tuple_filter *it;
2584
2585         TAILQ_FOREACH(it, filter_list, entries) {
2586                 if (memcmp(key, &it->filter_info,
2587                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
2588                         return it;
2589                 }
2590         }
2591         return NULL;
2592 }
2593
2594 /*
2595  * igb_add_2tuple_filter - add a 2tuple filter
2596  *
2597  * @param
2598  * dev: Pointer to struct rte_eth_dev.
2599  * ntuple_filter: ponter to the filter that will be added.
2600  *
2601  * @return
2602  *    - On success, zero.
2603  *    - On failure, a negative value.
2604  */
2605 static int
2606 igb_add_2tuple_filter(struct rte_eth_dev *dev,
2607                         struct rte_eth_ntuple_filter *ntuple_filter)
2608 {
2609         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2610         struct e1000_filter_info *filter_info =
2611                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2612         struct e1000_2tuple_filter *filter;
2613         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
2614         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
2615         int i, ret;
2616
2617         filter = rte_zmalloc("e1000_2tuple_filter",
2618                         sizeof(struct e1000_2tuple_filter), 0);
2619         if (filter == NULL)
2620                 return -ENOMEM;
2621
2622         ret = ntuple_filter_to_2tuple(ntuple_filter,
2623                                       &filter->filter_info);
2624         if (ret < 0) {
2625                 rte_free(filter);
2626                 return ret;
2627         }
2628         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2629                                          &filter->filter_info) != NULL) {
2630                 PMD_DRV_LOG(ERR, "filter exists.");
2631                 rte_free(filter);
2632                 return -EEXIST;
2633         }
2634         filter->queue = ntuple_filter->queue;
2635
2636         /*
2637          * look for an unused 2tuple filter index,
2638          * and insert the filter to list.
2639          */
2640         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
2641                 if (!(filter_info->twotuple_mask & (1 << i))) {
2642                         filter_info->twotuple_mask |= 1 << i;
2643                         filter->index = i;
2644                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
2645                                           filter,
2646                                           entries);
2647                         break;
2648                 }
2649         }
2650         if (i >= E1000_MAX_TTQF_FILTERS) {
2651                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
2652                 rte_free(filter);
2653                 return -ENOSYS;
2654         }
2655
2656         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
2657         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
2658                 imir |= E1000_IMIR_PORT_BP;
2659         else
2660                 imir &= ~E1000_IMIR_PORT_BP;
2661
2662         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
2663
2664         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2665         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
2666         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
2667         if (filter->filter_info.proto_mask == 0)
2668                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2669
2670         /* tcp flags bits setting. */
2671         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
2672                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
2673                         imir_ext |= E1000_IMIREXT_CTRL_URG;
2674                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
2675                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
2676                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
2677                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
2678                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
2679                         imir_ext |= E1000_IMIREXT_CTRL_RST;
2680                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
2681                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
2682                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
2683                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
2684         } else
2685                 imir_ext |= E1000_IMIREXT_CTRL_BP;
2686         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
2687         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
2688         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
2689         return 0;
2690 }
2691
2692 /*
2693  * igb_remove_2tuple_filter - remove a 2tuple filter
2694  *
2695  * @param
2696  * dev: Pointer to struct rte_eth_dev.
2697  * ntuple_filter: ponter to the filter that will be removed.
2698  *
2699  * @return
2700  *    - On success, zero.
2701  *    - On failure, a negative value.
2702  */
2703 static int
2704 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2705                         struct rte_eth_ntuple_filter *ntuple_filter)
2706 {
2707         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2708         struct e1000_filter_info *filter_info =
2709                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2710         struct e1000_2tuple_filter_info filter_2tuple;
2711         struct e1000_2tuple_filter *filter;
2712         int ret;
2713
2714         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
2715         ret = ntuple_filter_to_2tuple(ntuple_filter,
2716                                       &filter_2tuple);
2717         if (ret < 0)
2718                 return ret;
2719
2720         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2721                                          &filter_2tuple);
2722         if (filter == NULL) {
2723                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2724                 return -ENOENT;
2725         }
2726
2727         filter_info->twotuple_mask &= ~(1 << filter->index);
2728         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
2729         rte_free(filter);
2730
2731         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
2732         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
2733         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
2734         return 0;
2735 }
2736
2737 static inline struct e1000_flex_filter *
2738 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
2739                         struct e1000_flex_filter_info *key)
2740 {
2741         struct e1000_flex_filter *it;
2742
2743         TAILQ_FOREACH(it, filter_list, entries) {
2744                 if (memcmp(key, &it->filter_info,
2745                         sizeof(struct e1000_flex_filter_info)) == 0)
2746                         return it;
2747         }
2748
2749         return NULL;
2750 }
2751
2752 static int
2753 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
2754                         struct rte_eth_flex_filter *filter,
2755                         bool add)
2756 {
2757         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2758         struct e1000_filter_info *filter_info =
2759                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2760         struct e1000_flex_filter *flex_filter, *it;
2761         uint32_t wufc, queueing, mask;
2762         uint32_t reg_off;
2763         uint8_t shift, i, j = 0;
2764
2765         flex_filter = rte_zmalloc("e1000_flex_filter",
2766                         sizeof(struct e1000_flex_filter), 0);
2767         if (flex_filter == NULL)
2768                 return -ENOMEM;
2769
2770         flex_filter->filter_info.len = filter->len;
2771         flex_filter->filter_info.priority = filter->priority;
2772         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
2773         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
2774                 mask = 0;
2775                 /* reverse bits in flex filter's mask*/
2776                 for (shift = 0; shift < CHAR_BIT; shift++) {
2777                         if (filter->mask[i] & (0x01 << shift))
2778                                 mask |= (0x80 >> shift);
2779                 }
2780                 flex_filter->filter_info.mask[i] = mask;
2781         }
2782
2783         wufc = E1000_READ_REG(hw, E1000_WUFC);
2784         if (flex_filter->index < E1000_MAX_FHFT)
2785                 reg_off = E1000_FHFT(flex_filter->index);
2786         else
2787                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
2788
2789         if (add) {
2790                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
2791                                 &flex_filter->filter_info) != NULL) {
2792                         PMD_DRV_LOG(ERR, "filter exists.");
2793                         rte_free(flex_filter);
2794                         return -EEXIST;
2795                 }
2796                 flex_filter->queue = filter->queue;
2797                 /*
2798                  * look for an unused flex filter index
2799                  * and insert the filter into the list.
2800                  */
2801                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
2802                         if (!(filter_info->flex_mask & (1 << i))) {
2803                                 filter_info->flex_mask |= 1 << i;
2804                                 flex_filter->index = i;
2805                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
2806                                         flex_filter,
2807                                         entries);
2808                                 break;
2809                         }
2810                 }
2811                 if (i >= E1000_MAX_FLEX_FILTERS) {
2812                         PMD_DRV_LOG(ERR, "flex filters are full.");
2813                         rte_free(flex_filter);
2814                         return -ENOSYS;
2815                 }
2816
2817                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
2818                                 (E1000_WUFC_FLX0 << flex_filter->index));
2819                 queueing = filter->len |
2820                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2821                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2822                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
2823                                 queueing);
2824                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
2825                         E1000_WRITE_REG(hw, reg_off,
2826                                         flex_filter->filter_info.dwords[j]);
2827                         reg_off += sizeof(uint32_t);
2828                         E1000_WRITE_REG(hw, reg_off,
2829                                         flex_filter->filter_info.dwords[++j]);
2830                         reg_off += sizeof(uint32_t);
2831                         E1000_WRITE_REG(hw, reg_off,
2832                                 (uint32_t)flex_filter->filter_info.mask[i]);
2833                         reg_off += sizeof(uint32_t) * 2;
2834                         ++j;
2835                 }
2836         } else {
2837                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2838                                 &flex_filter->filter_info);
2839                 if (it == NULL) {
2840                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
2841                         rte_free(flex_filter);
2842                         return -ENOENT;
2843                 }
2844
2845                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
2846                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
2847                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
2848                         (~(E1000_WUFC_FLX0 << it->index)));
2849
2850                 filter_info->flex_mask &= ~(1 << it->index);
2851                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
2852                 rte_free(it);
2853                 rte_free(flex_filter);
2854         }
2855
2856         return 0;
2857 }
2858
2859 static int
2860 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
2861                         struct rte_eth_flex_filter *filter)
2862 {
2863         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2864         struct e1000_filter_info *filter_info =
2865                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2866         struct e1000_flex_filter flex_filter, *it;
2867         uint32_t wufc, queueing, wufc_en = 0;
2868
2869         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
2870         flex_filter.filter_info.len = filter->len;
2871         flex_filter.filter_info.priority = filter->priority;
2872         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
2873         memcpy(flex_filter.filter_info.mask, filter->mask,
2874                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
2875
2876         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
2877                                 &flex_filter.filter_info);
2878         if (it == NULL) {
2879                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2880                 return -ENOENT;
2881         }
2882
2883         wufc = E1000_READ_REG(hw, E1000_WUFC);
2884         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
2885
2886         if ((wufc & wufc_en) == wufc_en) {
2887                 uint32_t reg_off = 0;
2888                 if (it->index < E1000_MAX_FHFT)
2889                         reg_off = E1000_FHFT(it->index);
2890                 else
2891                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
2892
2893                 queueing = E1000_READ_REG(hw,
2894                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2895                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2896                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2897                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
2898                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2899                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2900                 return 0;
2901         }
2902         return -ENOENT;
2903 }
2904
2905 static int
2906 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
2907                         enum rte_filter_op filter_op,
2908                         void *arg)
2909 {
2910         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2911         struct rte_eth_flex_filter *filter;
2912         int ret = 0;
2913
2914         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2915
2916         if (filter_op == RTE_ETH_FILTER_NOP)
2917                 return ret;
2918
2919         if (arg == NULL) {
2920                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2921                             filter_op);
2922                 return -EINVAL;
2923         }
2924
2925         filter = (struct rte_eth_flex_filter *)arg;
2926         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
2927             || filter->len % sizeof(uint64_t) != 0) {
2928                 PMD_DRV_LOG(ERR, "filter's length is out of range");
2929                 return -EINVAL;
2930         }
2931         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
2932                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
2933                 return -EINVAL;
2934         }
2935
2936         switch (filter_op) {
2937         case RTE_ETH_FILTER_ADD:
2938                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
2939                 break;
2940         case RTE_ETH_FILTER_DELETE:
2941                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
2942                 break;
2943         case RTE_ETH_FILTER_GET:
2944                 ret = eth_igb_get_flex_filter(dev, filter);
2945                 break;
2946         default:
2947                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
2948                 ret = -EINVAL;
2949                 break;
2950         }
2951
2952         return ret;
2953 }
2954
2955 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
2956 static inline int
2957 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
2958                         struct e1000_5tuple_filter_info *filter_info)
2959 {
2960         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2961                 return -EINVAL;
2962         if (filter->priority > E1000_2TUPLE_MAX_PRI)
2963                 return -EINVAL;  /* filter index is out of range. */
2964         if (filter->tcp_flags > TCP_FLAG_ALL)
2965                 return -EINVAL;  /* flags is invalid. */
2966
2967         switch (filter->dst_ip_mask) {
2968         case UINT32_MAX:
2969                 filter_info->dst_ip_mask = 0;
2970                 filter_info->dst_ip = filter->dst_ip;
2971                 break;
2972         case 0:
2973                 filter_info->dst_ip_mask = 1;
2974                 break;
2975         default:
2976                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2977                 return -EINVAL;
2978         }
2979
2980         switch (filter->src_ip_mask) {
2981         case UINT32_MAX:
2982                 filter_info->src_ip_mask = 0;
2983                 filter_info->src_ip = filter->src_ip;
2984                 break;
2985         case 0:
2986                 filter_info->src_ip_mask = 1;
2987                 break;
2988         default:
2989                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2990                 return -EINVAL;
2991         }
2992
2993         switch (filter->dst_port_mask) {
2994         case UINT16_MAX:
2995                 filter_info->dst_port_mask = 0;
2996                 filter_info->dst_port = filter->dst_port;
2997                 break;
2998         case 0:
2999                 filter_info->dst_port_mask = 1;
3000                 break;
3001         default:
3002                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3003                 return -EINVAL;
3004         }
3005
3006         switch (filter->src_port_mask) {
3007         case UINT16_MAX:
3008                 filter_info->src_port_mask = 0;
3009                 filter_info->src_port = filter->src_port;
3010                 break;
3011         case 0:
3012                 filter_info->src_port_mask = 1;
3013                 break;
3014         default:
3015                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3016                 return -EINVAL;
3017         }
3018
3019         switch (filter->proto_mask) {
3020         case UINT8_MAX:
3021                 filter_info->proto_mask = 0;
3022                 filter_info->proto = filter->proto;
3023                 break;
3024         case 0:
3025                 filter_info->proto_mask = 1;
3026                 break;
3027         default:
3028                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3029                 return -EINVAL;
3030         }
3031
3032         filter_info->priority = (uint8_t)filter->priority;
3033         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3034                 filter_info->tcp_flags = filter->tcp_flags;
3035         else
3036                 filter_info->tcp_flags = 0;
3037
3038         return 0;
3039 }
3040
3041 static inline struct e1000_5tuple_filter *
3042 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3043                         struct e1000_5tuple_filter_info *key)
3044 {
3045         struct e1000_5tuple_filter *it;
3046
3047         TAILQ_FOREACH(it, filter_list, entries) {
3048                 if (memcmp(key, &it->filter_info,
3049                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3050                         return it;
3051                 }
3052         }
3053         return NULL;
3054 }
3055
3056 /*
3057  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3058  *
3059  * @param
3060  * dev: Pointer to struct rte_eth_dev.
3061  * ntuple_filter: ponter to the filter that will be added.
3062  *
3063  * @return
3064  *    - On success, zero.
3065  *    - On failure, a negative value.
3066  */
3067 static int
3068 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3069                         struct rte_eth_ntuple_filter *ntuple_filter)
3070 {
3071         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3072         struct e1000_filter_info *filter_info =
3073                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3074         struct e1000_5tuple_filter *filter;
3075         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3076         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3077         uint8_t i;
3078         int ret;
3079
3080         filter = rte_zmalloc("e1000_5tuple_filter",
3081                         sizeof(struct e1000_5tuple_filter), 0);
3082         if (filter == NULL)
3083                 return -ENOMEM;
3084
3085         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3086                                             &filter->filter_info);
3087         if (ret < 0) {
3088                 rte_free(filter);
3089                 return ret;
3090         }
3091
3092         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3093                                          &filter->filter_info) != NULL) {
3094                 PMD_DRV_LOG(ERR, "filter exists.");
3095                 rte_free(filter);
3096                 return -EEXIST;
3097         }
3098         filter->queue = ntuple_filter->queue;
3099
3100         /*
3101          * look for an unused 5tuple filter index,
3102          * and insert the filter to list.
3103          */
3104         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3105                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3106                         filter_info->fivetuple_mask |= 1 << i;
3107                         filter->index = i;
3108                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3109                                           filter,
3110                                           entries);
3111                         break;
3112                 }
3113         }
3114         if (i >= E1000_MAX_FTQF_FILTERS) {
3115                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3116                 rte_free(filter);
3117                 return -ENOSYS;
3118         }
3119
3120         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3121         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3122                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3123         if (filter->filter_info.dst_ip_mask == 0)
3124                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3125         if (filter->filter_info.src_port_mask == 0)
3126                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3127         if (filter->filter_info.proto_mask == 0)
3128                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3129         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3130                 E1000_FTQF_QUEUE_MASK;
3131         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3132         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3133         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3134         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3135
3136         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3137         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3138
3139         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3140         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3141                 imir |= E1000_IMIR_PORT_BP;
3142         else
3143                 imir &= ~E1000_IMIR_PORT_BP;
3144         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3145
3146         /* tcp flags bits setting. */
3147         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3148                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3149                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3150                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3151                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3152                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3153                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3154                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3155                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3156                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3157                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3158                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3159                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3160         } else
3161                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3162         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3163         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3164         return 0;
3165 }
3166
3167 /*
3168  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3169  *
3170  * @param
3171  * dev: Pointer to struct rte_eth_dev.
3172  * ntuple_filter: ponter to the filter that will be removed.
3173  *
3174  * @return
3175  *    - On success, zero.
3176  *    - On failure, a negative value.
3177  */
3178 static int
3179 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3180                                 struct rte_eth_ntuple_filter *ntuple_filter)
3181 {
3182         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3183         struct e1000_filter_info *filter_info =
3184                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3185         struct e1000_5tuple_filter_info filter_5tuple;
3186         struct e1000_5tuple_filter *filter;
3187         int ret;
3188
3189         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3190         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3191                                             &filter_5tuple);
3192         if (ret < 0)
3193                 return ret;
3194
3195         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3196                                          &filter_5tuple);
3197         if (filter == NULL) {
3198                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3199                 return -ENOENT;
3200         }
3201
3202         filter_info->fivetuple_mask &= ~(1 << filter->index);
3203         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3204         rte_free(filter);
3205
3206         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3207                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3208         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3209         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3210         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3211         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3212         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3213         return 0;
3214 }
3215
3216 static int
3217 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3218 {
3219         uint32_t rctl;
3220         struct e1000_hw *hw;
3221         struct rte_eth_dev_info dev_info;
3222         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3223                                      VLAN_TAG_SIZE);
3224
3225         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3226
3227 #ifdef RTE_LIBRTE_82571_SUPPORT
3228         /* XXX: not bigger than max_rx_pktlen */
3229         if (hw->mac.type == e1000_82571)
3230                 return -ENOTSUP;
3231 #endif
3232         eth_igb_infos_get(dev, &dev_info);
3233
3234         /* check that mtu is within the allowed range */
3235         if ((mtu < ETHER_MIN_MTU) ||
3236             (frame_size > dev_info.max_rx_pktlen))
3237                 return -EINVAL;
3238
3239         /* refuse mtu that requires the support of scattered packets when this
3240          * feature has not been enabled before. */
3241         if (!dev->data->scattered_rx &&
3242             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3243                 return -EINVAL;
3244
3245         rctl = E1000_READ_REG(hw, E1000_RCTL);
3246
3247         /* switch to jumbo mode if needed */
3248         if (frame_size > ETHER_MAX_LEN) {
3249                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3250                 rctl |= E1000_RCTL_LPE;
3251         } else {
3252                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3253                 rctl &= ~E1000_RCTL_LPE;
3254         }
3255         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3256
3257         /* update max frame size */
3258         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3259
3260         E1000_WRITE_REG(hw, E1000_RLPML,
3261                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3262
3263         return 0;
3264 }
3265
3266 /*
3267  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3268  *
3269  * @param
3270  * dev: Pointer to struct rte_eth_dev.
3271  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3272  * add: if true, add filter, if false, remove filter
3273  *
3274  * @return
3275  *    - On success, zero.
3276  *    - On failure, a negative value.
3277  */
3278 static int
3279 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3280                         struct rte_eth_ntuple_filter *ntuple_filter,
3281                         bool add)
3282 {
3283         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3284         int ret;
3285
3286         switch (ntuple_filter->flags) {
3287         case RTE_5TUPLE_FLAGS:
3288         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3289                 if (hw->mac.type != e1000_82576)
3290                         return -ENOTSUP;
3291                 if (add)
3292                         ret = igb_add_5tuple_filter_82576(dev,
3293                                                           ntuple_filter);
3294                 else
3295                         ret = igb_remove_5tuple_filter_82576(dev,
3296                                                              ntuple_filter);
3297                 break;
3298         case RTE_2TUPLE_FLAGS:
3299         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3300                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3301                         return -ENOTSUP;
3302                 if (add)
3303                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3304                 else
3305                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3306                 break;
3307         default:
3308                 ret = -EINVAL;
3309                 break;
3310         }
3311
3312         return ret;
3313 }
3314
3315 /*
3316  * igb_get_ntuple_filter - get a ntuple filter
3317  *
3318  * @param
3319  * dev: Pointer to struct rte_eth_dev.
3320  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3321  *
3322  * @return
3323  *    - On success, zero.
3324  *    - On failure, a negative value.
3325  */
3326 static int
3327 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3328                         struct rte_eth_ntuple_filter *ntuple_filter)
3329 {
3330         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3331         struct e1000_filter_info *filter_info =
3332                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3333         struct e1000_5tuple_filter_info filter_5tuple;
3334         struct e1000_2tuple_filter_info filter_2tuple;
3335         struct e1000_5tuple_filter *p_5tuple_filter;
3336         struct e1000_2tuple_filter *p_2tuple_filter;
3337         int ret;
3338
3339         switch (ntuple_filter->flags) {
3340         case RTE_5TUPLE_FLAGS:
3341         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3342                 if (hw->mac.type != e1000_82576)
3343                         return -ENOTSUP;
3344                 memset(&filter_5tuple,
3345                         0,
3346                         sizeof(struct e1000_5tuple_filter_info));
3347                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3348                                                     &filter_5tuple);
3349                 if (ret < 0)
3350                         return ret;
3351                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3352                                         &filter_info->fivetuple_list,
3353                                         &filter_5tuple);
3354                 if (p_5tuple_filter == NULL) {
3355                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3356                         return -ENOENT;
3357                 }
3358                 ntuple_filter->queue = p_5tuple_filter->queue;
3359                 break;
3360         case RTE_2TUPLE_FLAGS:
3361         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3362                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3363                         return -ENOTSUP;
3364                 memset(&filter_2tuple,
3365                         0,
3366                         sizeof(struct e1000_2tuple_filter_info));
3367                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3368                 if (ret < 0)
3369                         return ret;
3370                 p_2tuple_filter = igb_2tuple_filter_lookup(
3371                                         &filter_info->twotuple_list,
3372                                         &filter_2tuple);
3373                 if (p_2tuple_filter == NULL) {
3374                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3375                         return -ENOENT;
3376                 }
3377                 ntuple_filter->queue = p_2tuple_filter->queue;
3378                 break;
3379         default:
3380                 ret = -EINVAL;
3381                 break;
3382         }
3383
3384         return 0;
3385 }
3386
3387 /*
3388  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3389  * @dev: pointer to rte_eth_dev structure
3390  * @filter_op:operation will be taken.
3391  * @arg: a pointer to specific structure corresponding to the filter_op
3392  */
3393 static int
3394 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3395                                 enum rte_filter_op filter_op,
3396                                 void *arg)
3397 {
3398         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3399         int ret;
3400
3401         MAC_TYPE_FILTER_SUP(hw->mac.type);
3402
3403         if (filter_op == RTE_ETH_FILTER_NOP)
3404                 return 0;
3405
3406         if (arg == NULL) {
3407                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3408                             filter_op);
3409                 return -EINVAL;
3410         }
3411
3412         switch (filter_op) {
3413         case RTE_ETH_FILTER_ADD:
3414                 ret = igb_add_del_ntuple_filter(dev,
3415                         (struct rte_eth_ntuple_filter *)arg,
3416                         TRUE);
3417                 break;
3418         case RTE_ETH_FILTER_DELETE:
3419                 ret = igb_add_del_ntuple_filter(dev,
3420                         (struct rte_eth_ntuple_filter *)arg,
3421                         FALSE);
3422                 break;
3423         case RTE_ETH_FILTER_GET:
3424                 ret = igb_get_ntuple_filter(dev,
3425                         (struct rte_eth_ntuple_filter *)arg);
3426                 break;
3427         default:
3428                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3429                 ret = -EINVAL;
3430                 break;
3431         }
3432         return ret;
3433 }
3434
3435 static inline int
3436 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3437                         uint16_t ethertype)
3438 {
3439         int i;
3440
3441         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3442                 if (filter_info->ethertype_filters[i] == ethertype &&
3443                     (filter_info->ethertype_mask & (1 << i)))
3444                         return i;
3445         }
3446         return -1;
3447 }
3448
3449 static inline int
3450 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3451                         uint16_t ethertype)
3452 {
3453         int i;
3454
3455         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3456                 if (!(filter_info->ethertype_mask & (1 << i))) {
3457                         filter_info->ethertype_mask |= 1 << i;
3458                         filter_info->ethertype_filters[i] = ethertype;
3459                         return i;
3460                 }
3461         }
3462         return -1;
3463 }
3464
3465 static inline int
3466 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3467                         uint8_t idx)
3468 {
3469         if (idx >= E1000_MAX_ETQF_FILTERS)
3470                 return -1;
3471         filter_info->ethertype_mask &= ~(1 << idx);
3472         filter_info->ethertype_filters[idx] = 0;
3473         return idx;
3474 }
3475
3476
3477 static int
3478 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3479                         struct rte_eth_ethertype_filter *filter,
3480                         bool add)
3481 {
3482         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3483         struct e1000_filter_info *filter_info =
3484                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3485         uint32_t etqf = 0;
3486         int ret;
3487
3488         if (filter->ether_type == ETHER_TYPE_IPv4 ||
3489                 filter->ether_type == ETHER_TYPE_IPv6) {
3490                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3491                         " ethertype filter.", filter->ether_type);
3492                 return -EINVAL;
3493         }
3494
3495         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3496                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3497                 return -EINVAL;
3498         }
3499         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3500                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3501                 return -EINVAL;
3502         }
3503
3504         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3505         if (ret >= 0 && add) {
3506                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3507                             filter->ether_type);
3508                 return -EEXIST;
3509         }
3510         if (ret < 0 && !add) {
3511                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3512                             filter->ether_type);
3513                 return -ENOENT;
3514         }
3515
3516         if (add) {
3517                 ret = igb_ethertype_filter_insert(filter_info,
3518                         filter->ether_type);
3519                 if (ret < 0) {
3520                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
3521                         return -ENOSYS;
3522                 }
3523
3524                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3525                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3526                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3527         } else {
3528                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3529                 if (ret < 0)
3530                         return -ENOSYS;
3531         }
3532         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3533         E1000_WRITE_FLUSH(hw);
3534
3535         return 0;
3536 }
3537
3538 static int
3539 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3540                         struct rte_eth_ethertype_filter *filter)
3541 {
3542         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3543         struct e1000_filter_info *filter_info =
3544                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3545         uint32_t etqf;
3546         int ret;
3547
3548         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3549         if (ret < 0) {
3550                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3551                             filter->ether_type);
3552                 return -ENOENT;
3553         }
3554
3555         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3556         if (etqf & E1000_ETQF_FILTER_ENABLE) {
3557                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3558                 filter->flags = 0;
3559                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3560                                 E1000_ETQF_QUEUE_SHIFT;
3561                 return 0;
3562         }
3563
3564         return -ENOENT;
3565 }
3566
3567 /*
3568  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3569  * @dev: pointer to rte_eth_dev structure
3570  * @filter_op:operation will be taken.
3571  * @arg: a pointer to specific structure corresponding to the filter_op
3572  */
3573 static int
3574 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3575                                 enum rte_filter_op filter_op,
3576                                 void *arg)
3577 {
3578         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3579         int ret;
3580
3581         MAC_TYPE_FILTER_SUP(hw->mac.type);
3582
3583         if (filter_op == RTE_ETH_FILTER_NOP)
3584                 return 0;
3585
3586         if (arg == NULL) {
3587                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3588                             filter_op);
3589                 return -EINVAL;
3590         }
3591
3592         switch (filter_op) {
3593         case RTE_ETH_FILTER_ADD:
3594                 ret = igb_add_del_ethertype_filter(dev,
3595                         (struct rte_eth_ethertype_filter *)arg,
3596                         TRUE);
3597                 break;
3598         case RTE_ETH_FILTER_DELETE:
3599                 ret = igb_add_del_ethertype_filter(dev,
3600                         (struct rte_eth_ethertype_filter *)arg,
3601                         FALSE);
3602                 break;
3603         case RTE_ETH_FILTER_GET:
3604                 ret = igb_get_ethertype_filter(dev,
3605                         (struct rte_eth_ethertype_filter *)arg);
3606                 break;
3607         default:
3608                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3609                 ret = -EINVAL;
3610                 break;
3611         }
3612         return ret;
3613 }
3614
3615 static int
3616 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3617                      enum rte_filter_type filter_type,
3618                      enum rte_filter_op filter_op,
3619                      void *arg)
3620 {
3621         int ret = -EINVAL;
3622
3623         switch (filter_type) {
3624         case RTE_ETH_FILTER_NTUPLE:
3625                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
3626                 break;
3627         case RTE_ETH_FILTER_ETHERTYPE:
3628                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3629                 break;
3630         case RTE_ETH_FILTER_SYN:
3631                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
3632                 break;
3633         case RTE_ETH_FILTER_FLEXIBLE:
3634                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
3635                 break;
3636         default:
3637                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3638                                                         filter_type);
3639                 break;
3640         }
3641
3642         return ret;
3643 }
3644
3645 static struct rte_driver pmd_igb_drv = {
3646         .type = PMD_PDEV,
3647         .init = rte_igb_pmd_init,
3648 };
3649
3650 static struct rte_driver pmd_igbvf_drv = {
3651         .type = PMD_PDEV,
3652         .init = rte_igbvf_pmd_init,
3653 };
3654
3655 PMD_REGISTER_DRIVER(pmd_igb_drv);
3656 PMD_REGISTER_DRIVER(pmd_igbvf_drv);