lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40
  41 #include <rte_common.h>
  42 #include <rte_interrupts.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_log.h>
  45 #include <rte_debug.h>
  46 #include <rte_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_tailq.h>
  52 #include <rte_eal.h>
  53 #include <rte_atomic.h>
  54 #include <rte_malloc.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 static int  eth_igb_configure(struct rte_eth_dev *dev);
  61 static int  eth_igb_start(struct rte_eth_dev *dev);
  62 static void eth_igb_stop(struct rte_eth_dev *dev);
  63 static void eth_igb_close(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  68 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  69                                 int wait_to_complete);
  70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  71                                 struct rte_eth_stats *rte_stats);
  72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  74                                 struct rte_eth_dev_info *dev_info);
  75 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  76                                 struct rte_eth_fc_conf *fc_conf);
  77 static int eth_igb_interrupt_setup(struct rte_eth_dev *dev);
  78 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  79 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  80 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  81                                                         void *param);
  82 static int  igb_hardware_init(struct e1000_hw *hw);
  83 static void igb_hw_control_acquire(struct e1000_hw *hw);
  84 static void igb_hw_control_release(struct e1000_hw *hw);
  85 static void igb_init_manageability(struct e1000_hw *hw);
  86 static void igb_release_manageability(struct e1000_hw *hw);
  87
  88 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  89                 uint16_t vlan_id, int on);
  90 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  91 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  92
  93 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  94 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  95 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  96 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  97 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
  98 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
  99
 100 static int eth_igb_led_on(struct rte_eth_dev *dev);
 101 static int eth_igb_led_off(struct rte_eth_dev *dev);
 102
 103 static void igb_intr_disable(struct e1000_hw *hw);
 104 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 105 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 106                 struct ether_addr *mac_addr,
 107                 uint32_t index, uint32_t pool);
 108 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 109
 110 static void igbvf_intr_disable(struct e1000_hw *hw);
 111 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 112 static int igbvf_dev_start(struct rte_eth_dev *dev);
 113 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 114 static void igbvf_dev_close(struct rte_eth_dev *dev);
 115 static int eth_igbvf_link_update(struct e1000_hw *hw);
 116 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 117 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 118 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 119                 uint16_t vlan_id, int on);
 120 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 121 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 122
 123 /*
 124  * Define VF Stats MACRO for Non "cleared on read" register
 125  */
 126 #define UPDATE_VF_STAT(reg, last, cur)            \
 127 {                                                 \
 128         u32 latest = E1000_READ_REG(hw, reg);     \
 129         cur += latest - last;                     \
 130         last = latest;                            \
 131 }
 132
 133
 134 #define IGB_FC_PAUSE_TIME 0x0680
 135 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 136 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 137
 138 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 139
 140 /*
 141  * The set of PCI devices this driver supports
 142  */
 143 static struct rte_pci_id pci_id_igb_map[] = {
 144
 145 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 146 #include "rte_pci_dev_ids.h"
 147
 148 {.device_id = 0},
 149 };
 150
 151 /*
 152  * The set of PCI devices this driver supports (for 82576&I350 VF)
 153  */
 154 static struct rte_pci_id pci_id_igbvf_map[] = {
 155
 156 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 157 #include "rte_pci_dev_ids.h"
 158
 159 {.device_id = 0},
 160 };
 161
 162 static struct eth_dev_ops eth_igb_ops = {
 163         .dev_configure        = eth_igb_configure,
 164         .dev_start            = eth_igb_start,
 165         .dev_stop             = eth_igb_stop,
 166         .dev_close            = eth_igb_close,
 167         .promiscuous_enable   = eth_igb_promiscuous_enable,
 168         .promiscuous_disable  = eth_igb_promiscuous_disable,
 169         .allmulticast_enable  = eth_igb_allmulticast_enable,
 170         .allmulticast_disable = eth_igb_allmulticast_disable,
 171         .link_update          = eth_igb_link_update,
 172         .stats_get            = eth_igb_stats_get,
 173         .stats_reset          = eth_igb_stats_reset,
 174         .dev_infos_get        = eth_igb_infos_get,
 175         .vlan_filter_set      = eth_igb_vlan_filter_set,
 176         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 177         .vlan_offload_set     = eth_igb_vlan_offload_set,
 178         .rx_queue_setup       = eth_igb_rx_queue_setup,
 179         .rx_queue_release     = eth_igb_rx_queue_release,
 180         .tx_queue_setup       = eth_igb_tx_queue_setup,
 181         .tx_queue_release     = eth_igb_tx_queue_release,
 182         .dev_led_on           = eth_igb_led_on,
 183         .dev_led_off          = eth_igb_led_off,
 184         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 185         .mac_addr_add         = eth_igb_rar_set,
 186         .mac_addr_remove      = eth_igb_rar_clear,
 187 };
 188
 189 /*
 190  * dev_ops for virtual function, bare necessities for basic vf
 191  * operation have been implemented
 192  */
 193 static struct eth_dev_ops igbvf_eth_dev_ops = {
 194         .dev_configure        = igbvf_dev_configure,
 195         .dev_start            = igbvf_dev_start,
 196         .dev_stop             = igbvf_dev_stop,
 197         .dev_close            = igbvf_dev_close,
 198         .link_update          = eth_igb_link_update,
 199         .stats_get            = eth_igbvf_stats_get,
 200         .stats_reset          = eth_igbvf_stats_reset,
 201         .vlan_filter_set      = igbvf_vlan_filter_set,
 202         .dev_infos_get        = eth_igb_infos_get,
 203         .rx_queue_setup       = eth_igb_rx_queue_setup,
 204         .rx_queue_release     = eth_igb_rx_queue_release,
 205         .tx_queue_setup       = eth_igb_tx_queue_setup,
 206         .tx_queue_release     = eth_igb_tx_queue_release,
 207 };
 208
 209 /**
 210  * Atomically reads the link status information from global
 211  * structure rte_eth_dev.
 212  *
 213  * @param dev
 214  *   - Pointer to the structure rte_eth_dev to read from.
 215  *   - Pointer to the buffer to be saved with the link status.
 216  *
 217  * @return
 218  *   - On success, zero.
 219  *   - On failure, negative value.
 220  */
 221 static inline int
 222 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 223                                 struct rte_eth_link *link)
 224 {
 225         struct rte_eth_link *dst = link;
 226         struct rte_eth_link *src = &(dev->data->dev_link);
 227
 228         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 229                                         *(uint64_t *)src) == 0)
 230                 return -1;
 231
 232         return 0;
 233 }
 234
 235 /**
 236  * Atomically writes the link status information into global
 237  * structure rte_eth_dev.
 238  *
 239  * @param dev
 240  *   - Pointer to the structure rte_eth_dev to read from.
 241  *   - Pointer to the buffer to be saved with the link status.
 242  *
 243  * @return
 244  *   - On success, zero.
 245  *   - On failure, negative value.
 246  */
 247 static inline int
 248 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 249                                 struct rte_eth_link *link)
 250 {
 251         struct rte_eth_link *dst = &(dev->data->dev_link);
 252         struct rte_eth_link *src = link;
 253
 254         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 255                                         *(uint64_t *)src) == 0)
 256                 return -1;
 257
 258         return 0;
 259 }
 260
 261 static void
 262 igb_identify_hardware(struct rte_eth_dev *dev)
 263 {
 264         struct e1000_hw *hw =
 265                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 266
 267         hw->vendor_id = dev->pci_dev->id.vendor_id;
 268         hw->device_id = dev->pci_dev->id.device_id;
 269         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 270         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 271
 272         e1000_set_mac_type(hw);
 273
 274         /* need to check if it is a vf device below */
 275 }
 276
 277 static int
 278 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 279                    struct rte_eth_dev *eth_dev)
 280 {
 281         int error = 0;
 282         struct rte_pci_device *pci_dev;
 283         struct e1000_hw *hw =
 284                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 285         struct e1000_vfta * shadow_vfta =
 286                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 287
 288         pci_dev = eth_dev->pci_dev;
 289         eth_dev->dev_ops = &eth_igb_ops;
 290         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 291         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 292
 293         /* for secondary processes, we don't initialise any further as primary
 294          * has already done this work. Only check we don't need a different
 295          * RX function */
 296         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 297                 if (eth_dev->data->scattered_rx)
 298                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 299                 return 0;
 300         }
 301
 302         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 303
 304         igb_identify_hardware(eth_dev);
 305         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 306                 error = -EIO;
 307                 goto err_late;
 308         }
 309
 310         e1000_get_bus_info(hw);
 311
 312         hw->mac.autoneg = 1;
 313         hw->phy.autoneg_wait_to_complete = 0;
 314         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 315
 316         /* Copper options */
 317         if (hw->phy.media_type == e1000_media_type_copper) {
 318                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 319                 hw->phy.disable_polarity_correction = 0;
 320                 hw->phy.ms_type = e1000_ms_hw_default;
 321         }
 322
 323         /*
 324          * Start from a known state, this is important in reading the nvm
 325          * and mac from that.
 326          */
 327         e1000_reset_hw(hw);
 328
 329         /* Make sure we have a good EEPROM before we read from it */
 330         if (e1000_validate_nvm_checksum(hw) < 0) {
 331                 /*
 332                  * Some PCI-E parts fail the first check due to
 333                  * the link being in sleep state, call it again,
 334                  * if it fails a second time its a real issue.
 335                  */
 336                 if (e1000_validate_nvm_checksum(hw) < 0) {
 337                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 338                         error = -EIO;
 339                         goto err_late;
 340                 }
 341         }
 342
 343         /* Read the permanent MAC address out of the EEPROM */
 344         if (e1000_read_mac_addr(hw) != 0) {
 345                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 346                 error = -EIO;
 347                 goto err_late;
 348         }
 349
 350         /* Allocate memory for storing MAC addresses */
 351         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 352                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 353         if (eth_dev->data->mac_addrs == NULL) {
 354                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 355                                                 "store MAC addresses",
 356                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 357                 error = -ENOMEM;
 358                 goto err_late;
 359         }
 360
 361         /* Copy the permanent MAC address */
 362         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 363
 364         /* initialize the vfta */
 365         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 366
 367         /* Now initialize the hardware */
 368         if (igb_hardware_init(hw) != 0) {
 369                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 370                 rte_free(eth_dev->data->mac_addrs);
 371                 eth_dev->data->mac_addrs = NULL;
 372                 error = -ENODEV;
 373                 goto err_late;
 374         }
 375         hw->mac.get_link_status = 1;
 376
 377         /* Indicate SOL/IDER usage */
 378         if (e1000_check_reset_block(hw) < 0) {
 379                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 380                                         "SOL/IDER session");
 381         }
 382
 383         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 384                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 385                      pci_dev->id.device_id);
 386
 387         rte_intr_callback_register(&(pci_dev->intr_handle),
 388                 eth_igb_interrupt_handler, (void *)eth_dev);
 389
 390         return 0;
 391
 392 err_late:
 393         igb_hw_control_release(hw);
 394
 395         return (error);
 396 }
 397
 398 /*
 399  * Virtual Function device init
 400  */
 401 static int
 402 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 403                 struct rte_eth_dev *eth_dev)
 404 {
 405         struct rte_pci_device *pci_dev;
 406         struct e1000_hw *hw =
 407                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 408         int diag;
 409
 410         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 411
 412         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 413         pci_dev = eth_dev->pci_dev;
 414
 415         hw->device_id = pci_dev->id.device_id;
 416         hw->vendor_id = pci_dev->id.vendor_id;
 417         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 418
 419         /* Initialize the shared code */
 420         diag = e1000_setup_init_funcs(hw, TRUE);
 421         if (diag != 0) {
 422                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 423                         diag);
 424                 return -EIO;
 425         }
 426
 427         /* init_mailbox_params */
 428         hw->mbx.ops.init_params(hw);
 429
 430         /* Disable the interrupts for VF */
 431         igbvf_intr_disable(hw);
 432
 433         diag = hw->mac.ops.reset_hw(hw);
 434
 435         /* Allocate memory for storing MAC addresses */
 436         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 437                 hw->mac.rar_entry_count, 0);
 438         if (eth_dev->data->mac_addrs == NULL) {
 439                 PMD_INIT_LOG(ERR,
 440                         "Failed to allocate %d bytes needed to store MAC "
 441                         "addresses",
 442                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 443                 return -ENOMEM;
 444         }
 445         /* Copy the permanent MAC address */
 446         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 447                         &eth_dev->data->mac_addrs[0]);
 448
 449         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 450                         "mac.type=%s\n",
 451                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 452                         pci_dev->id.device_id,
 453                         "igb_mac_82576_vf");
 454
 455         return 0;
 456 }
 457
 458 static struct eth_driver rte_igb_pmd = {
 459         {
 460                 .name = "rte_igb_pmd",
 461                 .id_table = pci_id_igb_map,
 462                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 463         },
 464         .eth_dev_init = eth_igb_dev_init,
 465         .dev_private_size = sizeof(struct e1000_adapter),
 466 };
 467
 468 /*
 469  * virtual function driver struct
 470  */
 471 static struct eth_driver rte_igbvf_pmd = {
 472         {
 473                 .name = "rte_igbvf_pmd",
 474                 .id_table = pci_id_igbvf_map,
 475                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 476         },
 477         .eth_dev_init = eth_igbvf_dev_init,
 478         .dev_private_size = sizeof(struct e1000_adapter),
 479 };
 480
 481 int
 482 rte_igb_pmd_init(void)
 483 {
 484         rte_eth_driver_register(&rte_igb_pmd);
 485         return 0;
 486 }
 487
 488 /*
 489  * VF Driver initialization routine.
 490  * Invoked one at EAL init time.
 491  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 492  */
 493 int
 494 rte_igbvf_pmd_init(void)
 495 {
 496         DEBUGFUNC("rte_igbvf_pmd_init");
 497
 498         rte_eth_driver_register(&rte_igbvf_pmd);
 499         return (0);
 500 }
 501
 502 static int
 503 eth_igb_configure(struct rte_eth_dev *dev)
 504 {
 505         struct e1000_interrupt *intr =
 506                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 507
 508         PMD_INIT_LOG(DEBUG, ">>");
 509
 510         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 511
 512         PMD_INIT_LOG(DEBUG, "<<");
 513
 514         return (0);
 515 }
 516
 517 static int
 518 eth_igb_start(struct rte_eth_dev *dev)
 519 {
 520         struct e1000_hw *hw =
 521                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 522         int ret, i, mask;
 523
 524         PMD_INIT_LOG(DEBUG, ">>");
 525
 526         igb_intr_disable(hw);
 527
 528         /* Power up the phy. Needed to make the link go Up */
 529         e1000_power_up_phy(hw);
 530
 531         /*
 532          * Packet Buffer Allocation (PBA)
 533          * Writing PBA sets the receive portion of the buffer
 534          * the remainder is used for the transmit buffer.
 535          */
 536         if (hw->mac.type == e1000_82575) {
 537                 uint32_t pba;
 538
 539                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 540                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 541         }
 542
 543         /* Put the address into the Receive Address Array */
 544         e1000_rar_set(hw, hw->mac.addr, 0);
 545
 546         /* Initialize the hardware */
 547         if (igb_hardware_init(hw)) {
 548                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 549                 return (-EIO);
 550         }
 551
 552         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 553
 554         /* Configure for OS presence */
 555         igb_init_manageability(hw);
 556
 557         eth_igb_tx_init(dev);
 558
 559         /* This can fail when allocating mbufs for descriptor rings */
 560         ret = eth_igb_rx_init(dev);
 561         if (ret) {
 562                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 563                 igb_dev_clear_queues(dev);
 564                 return ret;
 565         }
 566
 567         e1000_clear_hw_cntrs_base_generic(hw);
 568
 569         /*
 570          * VLAN Offload Settings
 571          */
 572         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 573                         ETH_VLAN_EXTEND_MASK;
 574         eth_igb_vlan_offload_set(dev, mask);
 575
 576         /*
 577          * Configure the Interrupt Moderation register (EITR) with the maximum
 578          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 579          * spurious [DMA] memory updates of RX and TX ring descriptors.
 580          *
 581          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 582          * spurious memory updates per second should be expected.
 583          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 584          *
 585          * Because interrupts are not used at all, the MSI-X is not activated
 586          * and interrupt moderation is controlled by EITR[0].
 587          *
 588          * Note that having [almost] disabled memory updates of RX and TX ring
 589          * descriptors through the Interrupt Moderation mechanism, memory
 590          * updates of ring descriptors are now moderated by the configurable
 591          * value of Write-Back Threshold registers.
 592          */
 593         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 594                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 595                 uint32_t ivar;
 596
 597                 /* Enable all RX & TX queues in the IVAR registers */
 598                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 599                 for (i = 0; i < 8; i++)
 600                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 601
 602                 /* Configure EITR with the maximum possible value (0xFFFF) */
 603                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 604         }
 605
 606         /* Setup link speed and duplex */
 607         switch (dev->data->dev_conf.link_speed) {
 608         case ETH_LINK_SPEED_AUTONEG:
 609                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 610                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 611                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 612                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 613                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 614                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 615                 else
 616                         goto error_invalid_config;
 617                 break;
 618         case ETH_LINK_SPEED_10:
 619                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 620                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 621                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 622                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 623                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 624                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 625                 else
 626                         goto error_invalid_config;
 627                 break;
 628         case ETH_LINK_SPEED_100:
 629                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 630                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 631                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 632                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 633                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 634                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 635                 else
 636                         goto error_invalid_config;
 637                 break;
 638         case ETH_LINK_SPEED_1000:
 639                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 640                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 641                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 642                 else
 643                         goto error_invalid_config;
 644                 break;
 645         case ETH_LINK_SPEED_10000:
 646         default:
 647                 goto error_invalid_config;
 648         }
 649         e1000_setup_link(hw);
 650
 651         /* check if lsc interrupt feature is enabled */
 652         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 653                 ret = eth_igb_interrupt_setup(dev);
 654                 if (ret) {
 655                         PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 656                         igb_dev_clear_queues(dev);
 657                         return ret;
 658                 }
 659         }
 660
 661         PMD_INIT_LOG(DEBUG, "<<");
 662
 663         return (0);
 664
 665 error_invalid_config:
 666         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 667                         dev->data->dev_conf.link_speed,
 668                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 669         igb_dev_clear_queues(dev);
 670         return (-EINVAL);
 671 }
 672
 673 /*********************************************************************
 674  *
 675  *  This routine disables all traffic on the adapter by issuing a
 676  *  global reset on the MAC.
 677  *
 678  **********************************************************************/
 679 static void
 680 eth_igb_stop(struct rte_eth_dev *dev)
 681 {
 682         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 683         struct rte_eth_link link;
 684
 685         igb_intr_disable(hw);
 686         e1000_reset_hw(hw);
 687         E1000_WRITE_REG(hw, E1000_WUC, 0);
 688
 689         /* Power down the phy. Needed to make the link go Down */
 690         e1000_power_down_phy(hw);
 691
 692         igb_dev_clear_queues(dev);
 693
 694         /* clear the recorded link status */
 695         memset(&link, 0, sizeof(link));
 696         rte_igb_dev_atomic_write_link_status(dev, &link);
 697 }
 698
 699 static void
 700 eth_igb_close(struct rte_eth_dev *dev)
 701 {
 702         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 703         struct rte_eth_link link;
 704
 705         eth_igb_stop(dev);
 706         e1000_phy_hw_reset(hw);
 707         igb_release_manageability(hw);
 708         igb_hw_control_release(hw);
 709
 710         igb_dev_clear_queues(dev);
 711
 712         memset(&link, 0, sizeof(link));
 713         rte_igb_dev_atomic_write_link_status(dev, &link);
 714 }
 715
 716 static int
 717 igb_get_rx_buffer_size(struct e1000_hw *hw)
 718 {
 719         uint32_t rx_buf_size;
 720         if (hw->mac.type == e1000_82576) {
 721                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 722         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 723                 /* PBS needs to be translated according to a lookup table */
 724                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 725                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 726                 rx_buf_size = (rx_buf_size << 10);
 727         } else if (hw->mac.type == e1000_i210) {
 728                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 729         } else {
 730                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 731         }
 732
 733         return rx_buf_size;
 734 }
 735
 736 /*********************************************************************
 737  *
 738  *  Initialize the hardware
 739  *
 740  **********************************************************************/
 741 static int
 742 igb_hardware_init(struct e1000_hw *hw)
 743 {
 744         uint32_t rx_buf_size;
 745         int diag;
 746
 747         /* Let the firmware know the OS is in control */
 748         igb_hw_control_acquire(hw);
 749
 750         /*
 751          * These parameters control the automatic generation (Tx) and
 752          * response (Rx) to Ethernet PAUSE frames.
 753          * - High water mark should allow for at least two standard size (1518)
 754          *   frames to be received after sending an XOFF.
 755          * - Low water mark works best when it is very near the high water mark.
 756          *   This allows the receiver to restart by sending XON when it has
 757          *   drained a bit. Here we use an arbitary value of 1500 which will
 758          *   restart after one full frame is pulled from the buffer. There
 759          *   could be several smaller frames in the buffer and if so they will
 760          *   not trigger the XON until their total number reduces the buffer
 761          *   by 1500.
 762          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 763          */
 764         rx_buf_size = igb_get_rx_buffer_size(hw);
 765
 766         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 767         hw->fc.low_water = hw->fc.high_water - 1500;
 768         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 769         hw->fc.send_xon = 1;
 770
 771         /* Set Flow control, use the tunable location if sane */
 772         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 773                 hw->fc.requested_mode = igb_fc_setting;
 774         else
 775                 hw->fc.requested_mode = e1000_fc_none;
 776
 777         /* Issue a global reset */
 778         e1000_reset_hw(hw);
 779         E1000_WRITE_REG(hw, E1000_WUC, 0);
 780
 781         diag = e1000_init_hw(hw);
 782         if (diag < 0)
 783                 return (diag);
 784
 785         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 786         e1000_get_phy_info(hw);
 787         e1000_check_for_link(hw);
 788
 789         return (0);
 790 }
 791
 792 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 793 static void
 794 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 795 {
 796         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 797         struct e1000_hw_stats *stats =
 798                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 799         int pause_frames;
 800
 801         if(hw->phy.media_type == e1000_media_type_copper ||
 802             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 803                 stats->symerrs +=
 804                     E1000_READ_REG(hw,E1000_SYMERRS);
 805                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 806         }
 807
 808         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 809         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 810         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 811         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 812
 813         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 814         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 815         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 816         stats->dc += E1000_READ_REG(hw, E1000_DC);
 817         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 818         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 819         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 820         /*
 821         ** For watchdog management we need to know if we have been
 822         ** paused during the last interval, so capture that here.
 823         */
 824         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 825         stats->xoffrxc += pause_frames;
 826         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 827         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 828         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 829         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 830         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 831         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 832         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 833         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 834         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 835         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 836         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 837         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 838
 839         /* For the 64-bit byte counters the low dword must be read first. */
 840         /* Both registers clear on the read of the high dword */
 841
 842         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 843         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 844         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 845         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 846
 847         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 848         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 849         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 850         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 851         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 852
 853         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 854         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 855
 856         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 857         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 858         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 859         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 860         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 861         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 862         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 863         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 864         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 865         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 866
 867         /* Interrupt Counts */
 868
 869         stats->iac += E1000_READ_REG(hw, E1000_IAC);
 870         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 871         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 872         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 873         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 874         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 875         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 876         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 877         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 878
 879         /* Host to Card Statistics */
 880
 881         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
 882         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
 883         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
 884         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
 885         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
 886         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
 887         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
 888         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
 889         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
 890         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
 891         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
 892         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
 893         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
 894         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
 895
 896         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 897         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 898         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 899         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 900         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 901         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 902
 903         if (rte_stats == NULL)
 904                 return;
 905
 906         /* Rx Errors */
 907         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
 908             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
 909
 910         /* Tx Errors */
 911         rte_stats->oerrors = stats->ecol + stats->latecol;
 912
 913         rte_stats->ipackets = stats->gprc;
 914         rte_stats->opackets = stats->gptc;
 915         rte_stats->ibytes   = stats->gorc;
 916         rte_stats->obytes   = stats->gotc;
 917 }
 918
 919 static void
 920 eth_igb_stats_reset(struct rte_eth_dev *dev)
 921 {
 922         struct e1000_hw_stats *hw_stats =
 923                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 924
 925         /* HW registers are cleared on read */
 926         eth_igb_stats_get(dev, NULL);
 927
 928         /* Reset software totals */
 929         memset(hw_stats, 0, sizeof(*hw_stats));
 930 }
 931
 932 static void
 933 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 934 {
 935         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 936         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
 937                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 938
 939         /* Good Rx packets, include VF loopback */
 940         UPDATE_VF_STAT(E1000_VFGPRC,
 941             hw_stats->last_gprc, hw_stats->gprc);
 942
 943         /* Good Rx octets, include VF loopback */
 944         UPDATE_VF_STAT(E1000_VFGORC,
 945             hw_stats->last_gorc, hw_stats->gorc);
 946
 947         /* Good Tx packets, include VF loopback */
 948         UPDATE_VF_STAT(E1000_VFGPTC,
 949             hw_stats->last_gptc, hw_stats->gptc);
 950
 951         /* Good Tx octets, include VF loopback */
 952         UPDATE_VF_STAT(E1000_VFGOTC,
 953             hw_stats->last_gotc, hw_stats->gotc);
 954
 955         /* Rx Multicst packets */
 956         UPDATE_VF_STAT(E1000_VFMPRC,
 957             hw_stats->last_mprc, hw_stats->mprc);
 958
 959         /* Good Rx loopback packets */
 960         UPDATE_VF_STAT(E1000_VFGPRLBC,
 961             hw_stats->last_gprlbc, hw_stats->gprlbc);
 962
 963         /* Good Rx loopback octets */
 964         UPDATE_VF_STAT(E1000_VFGORLBC,
 965             hw_stats->last_gorlbc, hw_stats->gorlbc);
 966
 967         /* Good Tx loopback packets */
 968         UPDATE_VF_STAT(E1000_VFGPTLBC,
 969             hw_stats->last_gptlbc, hw_stats->gptlbc);
 970
 971         /* Good Tx loopback octets */
 972         UPDATE_VF_STAT(E1000_VFGOTLBC,
 973             hw_stats->last_gotlbc, hw_stats->gotlbc);
 974
 975         if (rte_stats == NULL)
 976                 return;
 977
 978         memset(rte_stats, 0, sizeof(*rte_stats));
 979         rte_stats->ipackets = hw_stats->gprc;
 980         rte_stats->ibytes = hw_stats->gorc;
 981         rte_stats->opackets = hw_stats->gptc;
 982         rte_stats->obytes = hw_stats->gotc;
 983         rte_stats->imcasts = hw_stats->mprc;
 984         rte_stats->ilbpackets = hw_stats->gprlbc;
 985         rte_stats->ilbbytes = hw_stats->gorlbc;
 986         rte_stats->olbpackets = hw_stats->gptlbc;
 987         rte_stats->olbbytes = hw_stats->gotlbc;
 988
 989 }
 990
 991 static void
 992 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
 993 {
 994         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
 995                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 996
 997         /* Sync HW register to the last stats */
 998         eth_igbvf_stats_get(dev, NULL);
 999
1000         /* reset HW current stats*/
1001         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1002                offsetof(struct e1000_vf_stats, gprc));
1003
1004 }
1005
1006 static void
1007 eth_igb_infos_get(struct rte_eth_dev *dev,
1008                     struct rte_eth_dev_info *dev_info)
1009 {
1010         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1011
1012         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1013         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1014         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1015
1016         switch (hw->mac.type) {
1017         case e1000_82575:
1018                 dev_info->max_rx_queues = 4;
1019                 dev_info->max_tx_queues = 4;
1020                 break;
1021
1022         case e1000_82576:
1023                 dev_info->max_rx_queues = 16;
1024                 dev_info->max_tx_queues = 16;
1025                 break;
1026
1027         case e1000_82580:
1028                 dev_info->max_rx_queues = 8;
1029                 dev_info->max_tx_queues = 8;
1030                 break;
1031
1032         case e1000_i350:
1033                 dev_info->max_rx_queues = 8;
1034                 dev_info->max_tx_queues = 8;
1035                 break;
1036
1037         case e1000_i210:
1038                 dev_info->max_rx_queues = 4;
1039                 dev_info->max_tx_queues = 4;
1040                 break;
1041
1042         case e1000_vfadapt:
1043                 dev_info->max_rx_queues = 2;
1044                 dev_info->max_tx_queues = 2;
1045                 break;
1046
1047         case e1000_vfadapt_i350:
1048                 dev_info->max_rx_queues = 1;
1049                 dev_info->max_tx_queues = 1;
1050                 break;
1051
1052         default:
1053                 /* Should not happen */
1054                 dev_info->max_rx_queues = 0;
1055                 dev_info->max_tx_queues = 0;
1056         }
1057 }
1058
1059 /* return 0 means link status changed, -1 means not changed */
1060 static int
1061 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1062 {
1063         struct e1000_hw *hw =
1064                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1065         struct rte_eth_link link, old;
1066         int link_check, count;
1067
1068         link_check = 0;
1069         hw->mac.get_link_status = 1;
1070
1071         /* possible wait-to-complete in up to 9 seconds */
1072         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1073                 /* Read the real link status */
1074                 switch (hw->phy.media_type) {
1075                 case e1000_media_type_copper:
1076                         /* Do the work to read phy */
1077                         e1000_check_for_link(hw);
1078                         link_check = !hw->mac.get_link_status;
1079                         break;
1080
1081                 case e1000_media_type_fiber:
1082                         e1000_check_for_link(hw);
1083                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1084                                       E1000_STATUS_LU);
1085                         break;
1086
1087                 case e1000_media_type_internal_serdes:
1088                         e1000_check_for_link(hw);
1089                         link_check = hw->mac.serdes_has_link;
1090                         break;
1091
1092                 /* VF device is type_unknown */
1093                 case e1000_media_type_unknown:
1094                         eth_igbvf_link_update(hw);
1095                         link_check = !hw->mac.get_link_status;
1096                         break;
1097
1098                 default:
1099                         break;
1100                 }
1101                 if (link_check || wait_to_complete == 0)
1102                         break;
1103                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1104         }
1105         memset(&link, 0, sizeof(link));
1106         rte_igb_dev_atomic_read_link_status(dev, &link);
1107         old = link;
1108
1109         /* Now we check if a transition has happened */
1110         if (link_check) {
1111                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1112                                           &link.link_duplex);
1113                 link.link_status = 1;
1114         } else if (!link_check) {
1115                 link.link_speed = 0;
1116                 link.link_duplex = 0;
1117                 link.link_status = 0;
1118         }
1119         rte_igb_dev_atomic_write_link_status(dev, &link);
1120
1121         /* not changed */
1122         if (old.link_status == link.link_status)
1123                 return -1;
1124
1125         /* changed */
1126         return 0;
1127 }
1128
1129 /*
1130  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1131  * For ASF and Pass Through versions of f/w this means
1132  * that the driver is loaded.
1133  */
1134 static void
1135 igb_hw_control_acquire(struct e1000_hw *hw)
1136 {
1137         uint32_t ctrl_ext;
1138
1139         /* Let firmware know the driver has taken over */
1140         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1141         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1142 }
1143
1144 /*
1145  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1146  * For ASF and Pass Through versions of f/w this means that the
1147  * driver is no longer loaded.
1148  */
1149 static void
1150 igb_hw_control_release(struct e1000_hw *hw)
1151 {
1152         uint32_t ctrl_ext;
1153
1154         /* Let firmware taken over control of h/w */
1155         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1156         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1157                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1158 }
1159
1160 /*
1161  * Bit of a misnomer, what this really means is
1162  * to enable OS management of the system... aka
1163  * to disable special hardware management features.
1164  */
1165 static void
1166 igb_init_manageability(struct e1000_hw *hw)
1167 {
1168         if (e1000_enable_mng_pass_thru(hw)) {
1169                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1170                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1171
1172                 /* disable hardware interception of ARP */
1173                 manc &= ~(E1000_MANC_ARP_EN);
1174
1175                 /* enable receiving management packets to the host */
1176                 manc |= E1000_MANC_EN_MNG2HOST;
1177                 manc2h |= 1 << 5;  /* Mng Port 623 */
1178                 manc2h |= 1 << 6;  /* Mng Port 664 */
1179                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1180                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1181         }
1182 }
1183
1184 static void
1185 igb_release_manageability(struct e1000_hw *hw)
1186 {
1187         if (e1000_enable_mng_pass_thru(hw)) {
1188                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1189
1190                 manc |= E1000_MANC_ARP_EN;
1191                 manc &= ~E1000_MANC_EN_MNG2HOST;
1192
1193                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1194         }
1195 }
1196
1197 static void
1198 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1199 {
1200         struct e1000_hw *hw =
1201                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1202         uint32_t rctl;
1203
1204         rctl = E1000_READ_REG(hw, E1000_RCTL);
1205         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1206         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1207 }
1208
1209 static void
1210 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1211 {
1212         struct e1000_hw *hw =
1213                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1214         uint32_t rctl;
1215
1216         rctl = E1000_READ_REG(hw, E1000_RCTL);
1217         rctl &= (~E1000_RCTL_UPE);
1218         if (dev->data->all_multicast == 1)
1219                 rctl |= E1000_RCTL_MPE;
1220         else
1221                 rctl &= (~E1000_RCTL_MPE);
1222         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1223 }
1224
1225 static void
1226 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1227 {
1228         struct e1000_hw *hw =
1229                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1230         uint32_t rctl;
1231
1232         rctl = E1000_READ_REG(hw, E1000_RCTL);
1233         rctl |= E1000_RCTL_MPE;
1234         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1235 }
1236
1237 static void
1238 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1239 {
1240         struct e1000_hw *hw =
1241                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1242         uint32_t rctl;
1243
1244         if (dev->data->promiscuous == 1)
1245                 return; /* must remain in all_multicast mode */
1246         rctl = E1000_READ_REG(hw, E1000_RCTL);
1247         rctl &= (~E1000_RCTL_MPE);
1248         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1249 }
1250
1251 static int
1252 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1253 {
1254         struct e1000_hw *hw =
1255                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1256         struct e1000_vfta * shadow_vfta =
1257                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1258         uint32_t vfta;
1259         uint32_t vid_idx;
1260         uint32_t vid_bit;
1261
1262         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1263                               E1000_VFTA_ENTRY_MASK);
1264         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1265         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1266         if (on)
1267                 vfta |= vid_bit;
1268         else
1269                 vfta &= ~vid_bit;
1270         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1271
1272         /* update local VFTA copy */
1273         shadow_vfta->vfta[vid_idx] = vfta;
1274
1275         return 0;
1276 }
1277
1278 static void
1279 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1280 {
1281         struct e1000_hw *hw =
1282                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1283         uint32_t reg = ETHER_TYPE_VLAN ;
1284
1285         reg |= (tpid << 16);
1286         E1000_WRITE_REG(hw, E1000_VET, reg);
1287 }
1288
1289 static void
1290 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1291 {
1292         struct e1000_hw *hw =
1293                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1294         uint32_t reg;
1295
1296         /* Filter Table Disable */
1297         reg = E1000_READ_REG(hw, E1000_RCTL);
1298         reg &= ~E1000_RCTL_CFIEN;
1299         reg &= ~E1000_RCTL_VFE;
1300         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1301 }
1302
1303 static void
1304 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1305 {
1306         struct e1000_hw *hw =
1307                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1308         struct e1000_vfta * shadow_vfta =
1309                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1310         uint32_t reg;
1311         int i;
1312
1313         /* Filter Table Enable, CFI not used for packet acceptance */
1314         reg = E1000_READ_REG(hw, E1000_RCTL);
1315         reg &= ~E1000_RCTL_CFIEN;
1316         reg |= E1000_RCTL_VFE;
1317         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1318
1319         /* restore VFTA table */
1320         for (i = 0; i < IGB_VFTA_SIZE; i++)
1321                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1322 }
1323
1324 static void
1325 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1326 {
1327         struct e1000_hw *hw =
1328                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1329         uint32_t reg;
1330
1331         /* VLAN Mode Disable */
1332         reg = E1000_READ_REG(hw, E1000_CTRL);
1333         reg &= ~E1000_CTRL_VME;
1334         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1335
1336         /* Update maximum frame size */
1337         E1000_WRITE_REG(hw, E1000_RLPML,
1338                 dev->data->dev_conf.rxmode.max_rx_pkt_len + VLAN_TAG_SIZE);
1339 }
1340
1341 static void
1342 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1343 {
1344         struct e1000_hw *hw =
1345                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1346         uint32_t reg;
1347
1348         /* VLAN Mode Enable */
1349         reg = E1000_READ_REG(hw, E1000_CTRL);
1350         reg |= E1000_CTRL_VME;
1351         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1352
1353         /* Update maximum frame size */
1354         E1000_WRITE_REG(hw, E1000_RLPML,
1355                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1356
1357 }
1358
1359 static void
1360 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1361 {
1362         struct e1000_hw *hw =
1363                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1364         uint32_t reg;
1365
1366         /* CTRL_EXT: Extended VLAN */
1367         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1368         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1369         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1370
1371 }
1372
1373 static void
1374 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1375 {
1376         struct e1000_hw *hw =
1377                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378         uint32_t reg;
1379
1380         /* CTRL_EXT: Extended VLAN */
1381         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1382         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1383         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1384 }
1385
1386 static void
1387 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1388 {
1389         if(mask & ETH_VLAN_STRIP_MASK){
1390                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1391                         igb_vlan_hw_strip_enable(dev);
1392                 else
1393                         igb_vlan_hw_strip_disable(dev);
1394         }
1395
1396         if(mask & ETH_VLAN_FILTER_MASK){
1397                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1398                         igb_vlan_hw_filter_enable(dev);
1399                 else
1400                         igb_vlan_hw_filter_disable(dev);
1401         }
1402
1403         if(mask & ETH_VLAN_EXTEND_MASK){
1404                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1405                         igb_vlan_hw_extend_enable(dev);
1406                 else
1407                         igb_vlan_hw_extend_disable(dev);
1408         }
1409 }
1410
1411 static void
1412 igb_intr_disable(struct e1000_hw *hw)
1413 {
1414         E1000_WRITE_REG(hw, E1000_IMC, ~0);
1415         E1000_WRITE_FLUSH(hw);
1416 }
1417
1418 /**
1419  * It enables the interrupt mask and then enable the interrupt.
1420  *
1421  * @param dev
1422  *  Pointer to struct rte_eth_dev.
1423  *
1424  * @return
1425  *  - On success, zero.
1426  *  - On failure, a negative value.
1427  */
1428 static int
1429 eth_igb_interrupt_setup(struct rte_eth_dev *dev)
1430 {
1431         struct e1000_hw *hw =
1432                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1433
1434         E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1435         E1000_WRITE_FLUSH(hw);
1436         rte_intr_enable(&(dev->pci_dev->intr_handle));
1437
1438         return 0;
1439 }
1440
1441 /*
1442  * It reads ICR and gets interrupt causes, check it and set a bit flag
1443  * to update link status.
1444  *
1445  * @param dev
1446  *  Pointer to struct rte_eth_dev.
1447  *
1448  * @return
1449  *  - On success, zero.
1450  *  - On failure, a negative value.
1451  */
1452 static int
1453 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1454 {
1455         uint32_t icr;
1456         struct e1000_hw *hw =
1457                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1458         struct e1000_interrupt *intr =
1459                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1460
1461         /* read-on-clear nic registers here */
1462         icr = E1000_READ_REG(hw, E1000_ICR);
1463         if (icr & E1000_ICR_LSC) {
1464                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1465         }
1466
1467         return 0;
1468 }
1469
1470 /*
1471  * It executes link_update after knowing an interrupt is prsent.
1472  *
1473  * @param dev
1474  *  Pointer to struct rte_eth_dev.
1475  *
1476  * @return
1477  *  - On success, zero.
1478  *  - On failure, a negative value.
1479  */
1480 static int
1481 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1482 {
1483         struct e1000_hw *hw =
1484                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1485         struct e1000_interrupt *intr =
1486                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1487         uint32_t tctl, rctl;
1488         struct rte_eth_link link;
1489         int ret;
1490
1491         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1492                 return -1;
1493
1494         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1495         rte_intr_enable(&(dev->pci_dev->intr_handle));
1496
1497         /* set get_link_status to check register later */
1498         hw->mac.get_link_status = 1;
1499         ret = eth_igb_link_update(dev, 0);
1500
1501         /* check if link has changed */
1502         if (ret < 0)
1503                 return 0;
1504
1505         memset(&link, 0, sizeof(link));
1506         rte_igb_dev_atomic_read_link_status(dev, &link);
1507         if (link.link_status) {
1508                 PMD_INIT_LOG(INFO,
1509                         " Port %d: Link Up - speed %u Mbps - %s\n",
1510                         dev->data->port_id, (unsigned)link.link_speed,
1511                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1512                                 "full-duplex" : "half-duplex");
1513         } else {
1514                 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1515                                         dev->data->port_id);
1516         }
1517         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1518                                 dev->pci_dev->addr.domain,
1519                                 dev->pci_dev->addr.bus,
1520                                 dev->pci_dev->addr.devid,
1521                                 dev->pci_dev->addr.function);
1522         tctl = E1000_READ_REG(hw, E1000_TCTL);
1523         rctl = E1000_READ_REG(hw, E1000_RCTL);
1524         if (link.link_status) {
1525                 /* enable Tx/Rx */
1526                 tctl |= E1000_TCTL_EN;
1527                 rctl |= E1000_RCTL_EN;
1528         } else {
1529                 /* disable Tx/Rx */
1530                 tctl &= ~E1000_TCTL_EN;
1531                 rctl &= ~E1000_RCTL_EN;
1532         }
1533         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1534         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1535         E1000_WRITE_FLUSH(hw);
1536
1537         return 0;
1538 }
1539
1540 /**
1541  * Interrupt handler which shall be registered at first.
1542  *
1543  * @param handle
1544  *  Pointer to interrupt handle.
1545  * @param param
1546  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1547  *
1548  * @return
1549  *  void
1550  */
1551 static void
1552 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1553                                                         void *param)
1554 {
1555         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1556
1557         eth_igb_interrupt_get_status(dev);
1558         eth_igb_interrupt_action(dev);
1559         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1560 }
1561
1562 static int
1563 eth_igb_led_on(struct rte_eth_dev *dev)
1564 {
1565         struct e1000_hw *hw;
1566
1567         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1568         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1569 }
1570
1571 static int
1572 eth_igb_led_off(struct rte_eth_dev *dev)
1573 {
1574         struct e1000_hw *hw;
1575
1576         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1578 }
1579
1580 static int
1581 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1582 {
1583         struct e1000_hw *hw;
1584         int err;
1585         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1586                 e1000_fc_none,
1587                 e1000_fc_rx_pause,
1588                 e1000_fc_tx_pause,
1589                 e1000_fc_full
1590         };
1591         uint32_t rx_buf_size;
1592         uint32_t max_high_water;
1593
1594         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595         rx_buf_size = igb_get_rx_buffer_size(hw);
1596         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1597
1598         /* At least reserve one Ethernet frame for watermark */
1599         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1600         if ((fc_conf->high_water > max_high_water) ||
1601                 (fc_conf->high_water < fc_conf->low_water)) {
1602                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1603                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1604                 return (-EINVAL);
1605         }
1606
1607         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1608         hw->fc.pause_time     = fc_conf->pause_time;
1609         hw->fc.high_water     = fc_conf->high_water;
1610         hw->fc.low_water      = fc_conf->low_water;
1611         hw->fc.send_xon       = fc_conf->send_xon;
1612
1613         err = e1000_setup_link_generic(hw);
1614         if (err == E1000_SUCCESS) {
1615                 return 0;
1616         }
1617
1618         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1619         return (-EIO);
1620 }
1621
1622 static void
1623 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1624                 uint32_t index, __rte_unused uint32_t pool)
1625 {
1626         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1627
1628         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1629 }
1630
1631 static void
1632 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1633 {
1634         uint8_t addr[ETHER_ADDR_LEN];
1635         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1636
1637         memset(addr, 0, sizeof(addr));
1638
1639         e1000_rar_set(hw, addr, index);
1640 }
1641
1642 /*
1643  * Virtual Function operations
1644  */
1645 static void
1646 igbvf_intr_disable(struct e1000_hw *hw)
1647 {
1648         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1649
1650         /* Clear interrupt mask to stop from interrupts being generated */
1651         E1000_WRITE_REG(hw, E1000_EIMC, ~0);
1652
1653         E1000_WRITE_FLUSH(hw);
1654 }
1655
1656 static void
1657 igbvf_stop_adapter(struct rte_eth_dev *dev)
1658 {
1659         u32 reg_val;
1660         u16 i;
1661         struct rte_eth_dev_info dev_info;
1662         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663
1664         memset(&dev_info, 0, sizeof(dev_info));
1665         eth_igb_infos_get(dev, &dev_info);
1666
1667         /* Clear interrupt mask to stop from interrupts being generated */
1668         E1000_WRITE_REG(hw, E1000_EIMC, ~0);
1669
1670         /* Clear any pending interrupts, flush previous writes */
1671         E1000_READ_REG(hw, E1000_EICR);
1672
1673         /* Disable the transmit unit.  Each queue must be disabled. */
1674         for (i = 0; i < dev_info.max_tx_queues; i++)
1675                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1676
1677         /* Disable the receive unit by stopping each queue */
1678         for (i = 0; i < dev_info.max_rx_queues; i++) {
1679                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1680                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1681                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1682                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1683                         ;
1684         }
1685
1686         /* flush all queues disables */
1687         E1000_WRITE_FLUSH(hw);
1688         msec_delay(2);
1689 }
1690
1691 static int eth_igbvf_link_update(struct e1000_hw *hw)
1692 {
1693         struct e1000_mbx_info *mbx = &hw->mbx;
1694         struct e1000_mac_info *mac = &hw->mac;
1695         int ret_val = E1000_SUCCESS;
1696
1697         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1698
1699         /*
1700          * We only want to run this if there has been a rst asserted.
1701          * in this case that could mean a link change, device reset,
1702          * or a virtual function reset
1703          */
1704
1705         /* If we were hit with a reset or timeout drop the link */
1706         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1707                 mac->get_link_status = TRUE;
1708
1709         if (!mac->get_link_status)
1710                 goto out;
1711
1712         /* if link status is down no point in checking to see if pf is up */
1713         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1714                 goto out;
1715
1716         /* if we passed all the tests above then the link is up and we no
1717          * longer need to check for link */
1718         mac->get_link_status = FALSE;
1719
1720 out:
1721         return ret_val;
1722 }
1723
1724
1725 static int
1726 igbvf_dev_configure(struct rte_eth_dev *dev)
1727 {
1728         struct rte_eth_conf* conf = &dev->data->dev_conf;
1729
1730         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1731                 dev->data->port_id);
1732
1733         /*
1734          * VF has no ability to enable/disable HW CRC
1735          * Keep the persistent behavior the same as Host PF
1736          */
1737 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1738         if (!conf->rxmode.hw_strip_crc) {
1739                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1740                 conf->rxmode.hw_strip_crc = 1;
1741         }
1742 #else
1743         if (conf->rxmode.hw_strip_crc) {
1744                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1745                 conf->rxmode.hw_strip_crc = 0;
1746         }
1747 #endif
1748
1749         return 0;
1750 }
1751
1752 static int
1753 igbvf_dev_start(struct rte_eth_dev *dev)
1754 {
1755         int ret;
1756
1757         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1758
1759         /* Set all vfta */
1760         igbvf_set_vfta_all(dev,1);
1761
1762         eth_igbvf_tx_init(dev);
1763
1764         /* This can fail when allocating mbufs for descriptor rings */
1765         ret = eth_igbvf_rx_init(dev);
1766         if (ret) {
1767                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1768                 igb_dev_clear_queues(dev);
1769                 return ret;
1770         }
1771
1772         return 0;
1773 }
1774
1775 static void
1776 igbvf_dev_stop(struct rte_eth_dev *dev)
1777 {
1778         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
1779
1780         igbvf_stop_adapter(dev);
1781
1782         /*
1783           * Clear what we set, but we still keep shadow_vfta to
1784           * restore after device starts
1785           */
1786         igbvf_set_vfta_all(dev,0);
1787
1788         igb_dev_clear_queues(dev);
1789 }
1790
1791 static void
1792 igbvf_dev_close(struct rte_eth_dev *dev)
1793 {
1794         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795
1796         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
1797
1798         e1000_reset_hw(hw);
1799
1800         igbvf_dev_stop(dev);
1801 }
1802
1803 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
1804 {
1805         struct e1000_mbx_info *mbx = &hw->mbx;
1806         uint32_t msgbuf[2];
1807
1808         /* After set vlan, vlan strip will also be enabled in igb driver*/
1809         msgbuf[0] = E1000_VF_SET_VLAN;
1810         msgbuf[1] = vid;
1811         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
1812         if (on)
1813                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
1814
1815         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
1816 }
1817
1818 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
1819 {
1820         struct e1000_hw *hw =
1821                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1822         struct e1000_vfta * shadow_vfta =
1823                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1824         int i = 0, j = 0, vfta = 0, mask = 1;
1825
1826         for (i = 0; i < IGB_VFTA_SIZE; i++){
1827                 vfta = shadow_vfta->vfta[i];
1828                 if(vfta){
1829                         mask = 1;
1830                         for (j = 0; j < 32; j++){
1831                                 if(vfta & mask)
1832                                         igbvf_set_vfta(hw,
1833                                                 (uint16_t)((i<<5)+j), on);
1834                                 mask<<=1;
1835                         }
1836                 }
1837         }
1838
1839 }
1840
1841 static int
1842 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1843 {
1844         struct e1000_hw *hw =
1845                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1846         struct e1000_vfta * shadow_vfta =
1847                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1848         uint32_t vid_idx = 0;
1849         uint32_t vid_bit = 0;
1850         int ret = 0;
1851
1852         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
1853
1854         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
1855         ret = igbvf_set_vfta(hw, vlan_id, !!on);
1856         if(ret){
1857                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
1858                 return ret;
1859         }
1860         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1861         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1862
1863         /*Save what we set and retore it after device reset*/
1864         if (on)
1865                 shadow_vfta->vfta[vid_idx] |= vid_bit;
1866         else
1867                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
1868
1869         return 0;
1870 }
1871