lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54
  55 #include "e1000_logs.h"
  56 #include "e1000/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 static int  eth_igb_configure(struct rte_eth_dev *dev);
  60 static int  eth_igb_start(struct rte_eth_dev *dev);
  61 static void eth_igb_stop(struct rte_eth_dev *dev);
  62 static void eth_igb_close(struct rte_eth_dev *dev);
  63 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  65 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  67 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  68                                 int wait_to_complete);
  69 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  70                                 struct rte_eth_stats *rte_stats);
  71 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  72 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  73                                 struct rte_eth_dev_info *dev_info);
  74 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  75                                 struct rte_eth_fc_conf *fc_conf);
  76 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  77 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  78 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  79 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  80                                                         void *param);
  81 static int  igb_hardware_init(struct e1000_hw *hw);
  82 static void igb_hw_control_acquire(struct e1000_hw *hw);
  83 static void igb_hw_control_release(struct e1000_hw *hw);
  84 static void igb_init_manageability(struct e1000_hw *hw);
  85 static void igb_release_manageability(struct e1000_hw *hw);
  86
  87 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  88                 uint16_t vlan_id, int on);
  89 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  90 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  91
  92 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  93 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  94 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  95 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  96 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
  97 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
  98
  99 static int eth_igb_led_on(struct rte_eth_dev *dev);
 100 static int eth_igb_led_off(struct rte_eth_dev *dev);
 101
 102 static void igb_intr_disable(struct e1000_hw *hw);
 103 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 104 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 105                 struct ether_addr *mac_addr,
 106                 uint32_t index, uint32_t pool);
 107 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 108
 109 static void igbvf_intr_disable(struct e1000_hw *hw);
 110 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 111 static int igbvf_dev_start(struct rte_eth_dev *dev);
 112 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 113 static void igbvf_dev_close(struct rte_eth_dev *dev);
 114 static int eth_igbvf_link_update(struct e1000_hw *hw);
 115 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 116 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 117 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 118                 uint16_t vlan_id, int on);
 119 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 120 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 121 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 122                  struct rte_eth_rss_reta *reta_conf);
 123 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 124                 struct rte_eth_rss_reta *reta_conf);
 125
 126 /*
 127  * Define VF Stats MACRO for Non "cleared on read" register
 128  */
 129 #define UPDATE_VF_STAT(reg, last, cur)            \
 130 {                                                 \
 131         u32 latest = E1000_READ_REG(hw, reg);     \
 132         cur += latest - last;                     \
 133         last = latest;                            \
 134 }
 135
 136
 137 #define IGB_FC_PAUSE_TIME 0x0680
 138 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 139 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 140
 141 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 142
 143 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 144
 145 /*
 146  * The set of PCI devices this driver supports
 147  */
 148 static struct rte_pci_id pci_id_igb_map[] = {
 149
 150 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 151 #include "rte_pci_dev_ids.h"
 152
 153 {.device_id = 0},
 154 };
 155
 156 /*
 157  * The set of PCI devices this driver supports (for 82576&I350 VF)
 158  */
 159 static struct rte_pci_id pci_id_igbvf_map[] = {
 160
 161 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 162 #include "rte_pci_dev_ids.h"
 163
 164 {.device_id = 0},
 165 };
 166
 167 static struct eth_dev_ops eth_igb_ops = {
 168         .dev_configure        = eth_igb_configure,
 169         .dev_start            = eth_igb_start,
 170         .dev_stop             = eth_igb_stop,
 171         .dev_close            = eth_igb_close,
 172         .promiscuous_enable   = eth_igb_promiscuous_enable,
 173         .promiscuous_disable  = eth_igb_promiscuous_disable,
 174         .allmulticast_enable  = eth_igb_allmulticast_enable,
 175         .allmulticast_disable = eth_igb_allmulticast_disable,
 176         .link_update          = eth_igb_link_update,
 177         .stats_get            = eth_igb_stats_get,
 178         .stats_reset          = eth_igb_stats_reset,
 179         .dev_infos_get        = eth_igb_infos_get,
 180         .vlan_filter_set      = eth_igb_vlan_filter_set,
 181         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 182         .vlan_offload_set     = eth_igb_vlan_offload_set,
 183         .rx_queue_setup       = eth_igb_rx_queue_setup,
 184         .rx_queue_release     = eth_igb_rx_queue_release,
 185         .rx_queue_count       = eth_igb_rx_queue_count,
 186         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 187         .tx_queue_setup       = eth_igb_tx_queue_setup,
 188         .tx_queue_release     = eth_igb_tx_queue_release,
 189         .dev_led_on           = eth_igb_led_on,
 190         .dev_led_off          = eth_igb_led_off,
 191         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 192         .mac_addr_add         = eth_igb_rar_set,
 193         .mac_addr_remove      = eth_igb_rar_clear,
 194         .reta_update          = eth_igb_rss_reta_update,
 195         .reta_query           = eth_igb_rss_reta_query,
 196 };
 197
 198 /*
 199  * dev_ops for virtual function, bare necessities for basic vf
 200  * operation have been implemented
 201  */
 202 static struct eth_dev_ops igbvf_eth_dev_ops = {
 203         .dev_configure        = igbvf_dev_configure,
 204         .dev_start            = igbvf_dev_start,
 205         .dev_stop             = igbvf_dev_stop,
 206         .dev_close            = igbvf_dev_close,
 207         .link_update          = eth_igb_link_update,
 208         .stats_get            = eth_igbvf_stats_get,
 209         .stats_reset          = eth_igbvf_stats_reset,
 210         .vlan_filter_set      = igbvf_vlan_filter_set,
 211         .dev_infos_get        = eth_igb_infos_get,
 212         .rx_queue_setup       = eth_igb_rx_queue_setup,
 213         .rx_queue_release     = eth_igb_rx_queue_release,
 214         .tx_queue_setup       = eth_igb_tx_queue_setup,
 215         .tx_queue_release     = eth_igb_tx_queue_release,
 216 };
 217
 218 /**
 219  * Atomically reads the link status information from global
 220  * structure rte_eth_dev.
 221  *
 222  * @param dev
 223  *   - Pointer to the structure rte_eth_dev to read from.
 224  *   - Pointer to the buffer to be saved with the link status.
 225  *
 226  * @return
 227  *   - On success, zero.
 228  *   - On failure, negative value.
 229  */
 230 static inline int
 231 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 232                                 struct rte_eth_link *link)
 233 {
 234         struct rte_eth_link *dst = link;
 235         struct rte_eth_link *src = &(dev->data->dev_link);
 236
 237         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 238                                         *(uint64_t *)src) == 0)
 239                 return -1;
 240
 241         return 0;
 242 }
 243
 244 /**
 245  * Atomically writes the link status information into global
 246  * structure rte_eth_dev.
 247  *
 248  * @param dev
 249  *   - Pointer to the structure rte_eth_dev to read from.
 250  *   - Pointer to the buffer to be saved with the link status.
 251  *
 252  * @return
 253  *   - On success, zero.
 254  *   - On failure, negative value.
 255  */
 256 static inline int
 257 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 258                                 struct rte_eth_link *link)
 259 {
 260         struct rte_eth_link *dst = &(dev->data->dev_link);
 261         struct rte_eth_link *src = link;
 262
 263         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 264                                         *(uint64_t *)src) == 0)
 265                 return -1;
 266
 267         return 0;
 268 }
 269
 270 static inline void
 271 igb_intr_enable(struct rte_eth_dev *dev)
 272 {
 273         struct e1000_interrupt *intr =
 274                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 275         struct e1000_hw *hw =
 276                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 277
 278         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 279         E1000_WRITE_FLUSH(hw);
 280 }
 281
 282 static void
 283 igb_intr_disable(struct e1000_hw *hw)
 284 {
 285         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 286         E1000_WRITE_FLUSH(hw);
 287 }
 288
 289 static inline int32_t
 290 igb_pf_reset_hw(struct e1000_hw *hw)
 291 {
 292         uint32_t ctrl_ext;
 293         int32_t status;
 294
 295         status = e1000_reset_hw(hw);
 296
 297         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 298         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 299         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 300         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 301         E1000_WRITE_FLUSH(hw);
 302
 303         return status;
 304 }
 305
 306 static void
 307 igb_identify_hardware(struct rte_eth_dev *dev)
 308 {
 309         struct e1000_hw *hw =
 310                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 311
 312         hw->vendor_id = dev->pci_dev->id.vendor_id;
 313         hw->device_id = dev->pci_dev->id.device_id;
 314         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 315         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 316
 317         e1000_set_mac_type(hw);
 318
 319         /* need to check if it is a vf device below */
 320 }
 321
 322 static int
 323 igb_reset_swfw_lock(struct e1000_hw *hw)
 324 {
 325         int ret_val;
 326
 327         /*
 328          * Do mac ops initialization manually here, since we will need
 329          * some function pointers set by this call.
 330          */
 331         ret_val = e1000_init_mac_params(hw);
 332         if (ret_val)
 333                 return ret_val;
 334
 335         /*
 336          * SMBI lock should not fail in this early stage. If this is the case,
 337          * it is due to an improper exit of the application.
 338          * So force the release of the faulty lock.
 339          */
 340         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 341                 DEBUGOUT("SMBI lock released");
 342         }
 343         e1000_put_hw_semaphore_generic(hw);
 344
 345         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 346                 uint16_t mask;
 347
 348                 /*
 349                  * Phy lock should not fail in this early stage. If this is the case,
 350                  * it is due to an improper exit of the application.
 351                  * So force the release of the faulty lock.
 352                  */
 353                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 354                 if (hw->bus.func > E1000_FUNC_1)
 355                         mask <<= 2;
 356                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 357                         DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
 358                 }
 359                 hw->mac.ops.release_swfw_sync(hw, mask);
 360
 361                 /*
 362                  * This one is more tricky since it is common to all ports; but
 363                  * swfw_sync retries last long enough (1s) to be almost sure that if
 364                  * lock can not be taken it is due to an improper lock of the
 365                  * semaphore.
 366                  */
 367                 mask = E1000_SWFW_EEP_SM;
 368                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 369                         DEBUGOUT("SWFW common locks released");
 370                 }
 371                 hw->mac.ops.release_swfw_sync(hw, mask);
 372         }
 373
 374         return E1000_SUCCESS;
 375 }
 376
 377 static int
 378 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 379                    struct rte_eth_dev *eth_dev)
 380 {
 381         int error = 0;
 382         struct rte_pci_device *pci_dev;
 383         struct e1000_hw *hw =
 384                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 385         struct e1000_vfta * shadow_vfta =
 386                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 387         uint32_t ctrl_ext;
 388
 389         pci_dev = eth_dev->pci_dev;
 390         eth_dev->dev_ops = &eth_igb_ops;
 391         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 392         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 393
 394         /* for secondary processes, we don't initialise any further as primary
 395          * has already done this work. Only check we don't need a different
 396          * RX function */
 397         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 398                 if (eth_dev->data->scattered_rx)
 399                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 400                 return 0;
 401         }
 402
 403         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 404
 405         igb_identify_hardware(eth_dev);
 406         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 407                 error = -EIO;
 408                 goto err_late;
 409         }
 410
 411         e1000_get_bus_info(hw);
 412
 413         /* Reset any pending lock */
 414         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 415                 error = -EIO;
 416                 goto err_late;
 417         }
 418
 419         /* Finish initialization */
 420         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 421                 error = -EIO;
 422                 goto err_late;
 423         }
 424
 425         hw->mac.autoneg = 1;
 426         hw->phy.autoneg_wait_to_complete = 0;
 427         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 428
 429         /* Copper options */
 430         if (hw->phy.media_type == e1000_media_type_copper) {
 431                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 432                 hw->phy.disable_polarity_correction = 0;
 433                 hw->phy.ms_type = e1000_ms_hw_default;
 434         }
 435
 436         /*
 437          * Start from a known state, this is important in reading the nvm
 438          * and mac from that.
 439          */
 440         igb_pf_reset_hw(hw);
 441
 442         /* Make sure we have a good EEPROM before we read from it */
 443         if (e1000_validate_nvm_checksum(hw) < 0) {
 444                 /*
 445                  * Some PCI-E parts fail the first check due to
 446                  * the link being in sleep state, call it again,
 447                  * if it fails a second time its a real issue.
 448                  */
 449                 if (e1000_validate_nvm_checksum(hw) < 0) {
 450                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 451                         error = -EIO;
 452                         goto err_late;
 453                 }
 454         }
 455
 456         /* Read the permanent MAC address out of the EEPROM */
 457         if (e1000_read_mac_addr(hw) != 0) {
 458                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 459                 error = -EIO;
 460                 goto err_late;
 461         }
 462
 463         /* Allocate memory for storing MAC addresses */
 464         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 465                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 466         if (eth_dev->data->mac_addrs == NULL) {
 467                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 468                                                 "store MAC addresses",
 469                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 470                 error = -ENOMEM;
 471                 goto err_late;
 472         }
 473
 474         /* Copy the permanent MAC address */
 475         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 476
 477         /* initialize the vfta */
 478         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 479
 480         /* Now initialize the hardware */
 481         if (igb_hardware_init(hw) != 0) {
 482                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 483                 rte_free(eth_dev->data->mac_addrs);
 484                 eth_dev->data->mac_addrs = NULL;
 485                 error = -ENODEV;
 486                 goto err_late;
 487         }
 488         hw->mac.get_link_status = 1;
 489
 490         /* Indicate SOL/IDER usage */
 491         if (e1000_check_reset_block(hw) < 0) {
 492                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 493                                         "SOL/IDER session");
 494         }
 495
 496         /* initialize PF if max_vfs not zero */
 497         igb_pf_host_init(eth_dev);
 498
 499         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 500         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 501         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 502         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 503         E1000_WRITE_FLUSH(hw);
 504
 505         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
 506                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 507                      pci_dev->id.device_id);
 508
 509         rte_intr_callback_register(&(pci_dev->intr_handle),
 510                 eth_igb_interrupt_handler, (void *)eth_dev);
 511
 512         /* enable uio intr after callback register */
 513         rte_intr_enable(&(pci_dev->intr_handle));
 514
 515         /* enable support intr */
 516         igb_intr_enable(eth_dev);
 517
 518         return 0;
 519
 520 err_late:
 521         igb_hw_control_release(hw);
 522
 523         return (error);
 524 }
 525
 526 /*
 527  * Virtual Function device init
 528  */
 529 static int
 530 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 531                 struct rte_eth_dev *eth_dev)
 532 {
 533         struct rte_pci_device *pci_dev;
 534         struct e1000_hw *hw =
 535                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 536         int diag;
 537
 538         PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 539
 540         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 541         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 542         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 543
 544         /* for secondary processes, we don't initialise any further as primary
 545          * has already done this work. Only check we don't need a different
 546          * RX function */
 547         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 548                 if (eth_dev->data->scattered_rx)
 549                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 550                 return 0;
 551         }
 552
 553         pci_dev = eth_dev->pci_dev;
 554
 555         hw->device_id = pci_dev->id.device_id;
 556         hw->vendor_id = pci_dev->id.vendor_id;
 557         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 558
 559         /* Initialize the shared code */
 560         diag = e1000_setup_init_funcs(hw, TRUE);
 561         if (diag != 0) {
 562                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 563                         diag);
 564                 return -EIO;
 565         }
 566
 567         /* init_mailbox_params */
 568         hw->mbx.ops.init_params(hw);
 569
 570         /* Disable the interrupts for VF */
 571         igbvf_intr_disable(hw);
 572
 573         diag = hw->mac.ops.reset_hw(hw);
 574
 575         /* Allocate memory for storing MAC addresses */
 576         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 577                 hw->mac.rar_entry_count, 0);
 578         if (eth_dev->data->mac_addrs == NULL) {
 579                 PMD_INIT_LOG(ERR,
 580                         "Failed to allocate %d bytes needed to store MAC "
 581                         "addresses",
 582                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 583                 return -ENOMEM;
 584         }
 585
 586         /* Copy the permanent MAC address */
 587         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 588                         &eth_dev->data->mac_addrs[0]);
 589
 590         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x "
 591                         "mac.type=%s\n",
 592                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 593                         pci_dev->id.device_id,
 594                         "igb_mac_82576_vf");
 595
 596         return 0;
 597 }
 598
 599 static struct eth_driver rte_igb_pmd = {
 600         {
 601                 .name = "rte_igb_pmd",
 602                 .id_table = pci_id_igb_map,
 603                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 604         },
 605         .eth_dev_init = eth_igb_dev_init,
 606         .dev_private_size = sizeof(struct e1000_adapter),
 607 };
 608
 609 /*
 610  * virtual function driver struct
 611  */
 612 static struct eth_driver rte_igbvf_pmd = {
 613         {
 614                 .name = "rte_igbvf_pmd",
 615                 .id_table = pci_id_igbvf_map,
 616                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 617         },
 618         .eth_dev_init = eth_igbvf_dev_init,
 619         .dev_private_size = sizeof(struct e1000_adapter),
 620 };
 621
 622 int
 623 rte_igb_pmd_init(void)
 624 {
 625         rte_eth_driver_register(&rte_igb_pmd);
 626         return 0;
 627 }
 628
 629 static void
 630 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 631 {
 632         struct e1000_hw *hw =
 633                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 634         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 635         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 636         rctl |= E1000_RCTL_VFE;
 637         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 638 }
 639
 640 /*
 641  * VF Driver initialization routine.
 642  * Invoked one at EAL init time.
 643  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 644  */
 645 int
 646 rte_igbvf_pmd_init(void)
 647 {
 648         DEBUGFUNC("rte_igbvf_pmd_init");
 649
 650         rte_eth_driver_register(&rte_igbvf_pmd);
 651         return (0);
 652 }
 653
 654 static int
 655 eth_igb_configure(struct rte_eth_dev *dev)
 656 {
 657         struct e1000_interrupt *intr =
 658                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 659
 660         PMD_INIT_LOG(DEBUG, ">>");
 661
 662         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 663
 664         PMD_INIT_LOG(DEBUG, "<<");
 665
 666         return (0);
 667 }
 668
 669 static int
 670 eth_igb_start(struct rte_eth_dev *dev)
 671 {
 672         struct e1000_hw *hw =
 673                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 674         int ret, i, mask;
 675         uint32_t ctrl_ext;
 676
 677         PMD_INIT_LOG(DEBUG, ">>");
 678
 679         /* Power up the phy. Needed to make the link go Up */
 680         e1000_power_up_phy(hw);
 681
 682         /*
 683          * Packet Buffer Allocation (PBA)
 684          * Writing PBA sets the receive portion of the buffer
 685          * the remainder is used for the transmit buffer.
 686          */
 687         if (hw->mac.type == e1000_82575) {
 688                 uint32_t pba;
 689
 690                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 691                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 692         }
 693
 694         /* Put the address into the Receive Address Array */
 695         e1000_rar_set(hw, hw->mac.addr, 0);
 696
 697         /* Initialize the hardware */
 698         if (igb_hardware_init(hw)) {
 699                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 700                 return (-EIO);
 701         }
 702
 703         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 704
 705         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 706         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 707         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 708         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 709         E1000_WRITE_FLUSH(hw);
 710
 711         /* configure PF module if SRIOV enabled */
 712         igb_pf_host_configure(dev);
 713
 714         /* Configure for OS presence */
 715         igb_init_manageability(hw);
 716
 717         eth_igb_tx_init(dev);
 718
 719         /* This can fail when allocating mbufs for descriptor rings */
 720         ret = eth_igb_rx_init(dev);
 721         if (ret) {
 722                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 723                 igb_dev_clear_queues(dev);
 724                 return ret;
 725         }
 726
 727         e1000_clear_hw_cntrs_base_generic(hw);
 728
 729         /*
 730          * VLAN Offload Settings
 731          */
 732         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 733                         ETH_VLAN_EXTEND_MASK;
 734         eth_igb_vlan_offload_set(dev, mask);
 735
 736         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 737                 /* Enable VLAN filter since VMDq always use VLAN filter */
 738                 igb_vmdq_vlan_hw_filter_enable(dev);
 739         }
 740
 741         /*
 742          * Configure the Interrupt Moderation register (EITR) with the maximum
 743          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 744          * spurious [DMA] memory updates of RX and TX ring descriptors.
 745          *
 746          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 747          * spurious memory updates per second should be expected.
 748          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 749          *
 750          * Because interrupts are not used at all, the MSI-X is not activated
 751          * and interrupt moderation is controlled by EITR[0].
 752          *
 753          * Note that having [almost] disabled memory updates of RX and TX ring
 754          * descriptors through the Interrupt Moderation mechanism, memory
 755          * updates of ring descriptors are now moderated by the configurable
 756          * value of Write-Back Threshold registers.
 757          */
 758         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 759                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 760                 uint32_t ivar;
 761
 762                 /* Enable all RX & TX queues in the IVAR registers */
 763                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 764                 for (i = 0; i < 8; i++)
 765                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 766
 767                 /* Configure EITR with the maximum possible value (0xFFFF) */
 768                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 769         }
 770
 771         /* Setup link speed and duplex */
 772         switch (dev->data->dev_conf.link_speed) {
 773         case ETH_LINK_SPEED_AUTONEG:
 774                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 775                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 776                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 777                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 778                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 779                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 780                 else
 781                         goto error_invalid_config;
 782                 break;
 783         case ETH_LINK_SPEED_10:
 784                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 785                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 786                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 787                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 788                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 789                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 790                 else
 791                         goto error_invalid_config;
 792                 break;
 793         case ETH_LINK_SPEED_100:
 794                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 795                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 796                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 797                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 798                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 799                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 800                 else
 801                         goto error_invalid_config;
 802                 break;
 803         case ETH_LINK_SPEED_1000:
 804                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 805                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 806                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 807                 else
 808                         goto error_invalid_config;
 809                 break;
 810         case ETH_LINK_SPEED_10000:
 811         default:
 812                 goto error_invalid_config;
 813         }
 814         e1000_setup_link(hw);
 815
 816         /* check if lsc interrupt feature is enabled */
 817         if (dev->data->dev_conf.intr_conf.lsc != 0)
 818                 ret = eth_igb_lsc_interrupt_setup(dev);
 819
 820         /* resume enabled intr since hw reset */
 821         igb_intr_enable(dev);
 822
 823         PMD_INIT_LOG(DEBUG, "<<");
 824
 825         return (0);
 826
 827 error_invalid_config:
 828         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
 829                         dev->data->dev_conf.link_speed,
 830                         dev->data->dev_conf.link_duplex, dev->data->port_id);
 831         igb_dev_clear_queues(dev);
 832         return (-EINVAL);
 833 }
 834
 835 /*********************************************************************
 836  *
 837  *  This routine disables all traffic on the adapter by issuing a
 838  *  global reset on the MAC.
 839  *
 840  **********************************************************************/
 841 static void
 842 eth_igb_stop(struct rte_eth_dev *dev)
 843 {
 844         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 845         struct rte_eth_link link;
 846
 847         igb_intr_disable(hw);
 848         igb_pf_reset_hw(hw);
 849         E1000_WRITE_REG(hw, E1000_WUC, 0);
 850
 851         /* Set bit for Go Link disconnect */
 852         if (hw->mac.type >= e1000_82580) {
 853                 uint32_t phpm_reg;
 854
 855                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 856                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 857                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 858         }
 859
 860         /* Power down the phy. Needed to make the link go Down */
 861         e1000_power_down_phy(hw);
 862
 863         igb_dev_clear_queues(dev);
 864
 865         /* clear the recorded link status */
 866         memset(&link, 0, sizeof(link));
 867         rte_igb_dev_atomic_write_link_status(dev, &link);
 868 }
 869
 870 static void
 871 eth_igb_close(struct rte_eth_dev *dev)
 872 {
 873         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 874         struct rte_eth_link link;
 875
 876         eth_igb_stop(dev);
 877         e1000_phy_hw_reset(hw);
 878         igb_release_manageability(hw);
 879         igb_hw_control_release(hw);
 880
 881         /* Clear bit for Go Link disconnect */
 882         if (hw->mac.type >= e1000_82580) {
 883                 uint32_t phpm_reg;
 884
 885                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 886                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 887                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 888         }
 889
 890         igb_dev_clear_queues(dev);
 891
 892         memset(&link, 0, sizeof(link));
 893         rte_igb_dev_atomic_write_link_status(dev, &link);
 894 }
 895
 896 static int
 897 igb_get_rx_buffer_size(struct e1000_hw *hw)
 898 {
 899         uint32_t rx_buf_size;
 900         if (hw->mac.type == e1000_82576) {
 901                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 902         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 903                 /* PBS needs to be translated according to a lookup table */
 904                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 905                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 906                 rx_buf_size = (rx_buf_size << 10);
 907         } else if (hw->mac.type == e1000_i210) {
 908                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 909         } else {
 910                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 911         }
 912
 913         return rx_buf_size;
 914 }
 915
 916 /*********************************************************************
 917  *
 918  *  Initialize the hardware
 919  *
 920  **********************************************************************/
 921 static int
 922 igb_hardware_init(struct e1000_hw *hw)
 923 {
 924         uint32_t rx_buf_size;
 925         int diag;
 926
 927         /* Let the firmware know the OS is in control */
 928         igb_hw_control_acquire(hw);
 929
 930         /*
 931          * These parameters control the automatic generation (Tx) and
 932          * response (Rx) to Ethernet PAUSE frames.
 933          * - High water mark should allow for at least two standard size (1518)
 934          *   frames to be received after sending an XOFF.
 935          * - Low water mark works best when it is very near the high water mark.
 936          *   This allows the receiver to restart by sending XON when it has
 937          *   drained a bit. Here we use an arbitrary value of 1500 which will
 938          *   restart after one full frame is pulled from the buffer. There
 939          *   could be several smaller frames in the buffer and if so they will
 940          *   not trigger the XON until their total number reduces the buffer
 941          *   by 1500.
 942          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 943          */
 944         rx_buf_size = igb_get_rx_buffer_size(hw);
 945
 946         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
 947         hw->fc.low_water = hw->fc.high_water - 1500;
 948         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
 949         hw->fc.send_xon = 1;
 950
 951         /* Set Flow control, use the tunable location if sane */
 952         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
 953                 hw->fc.requested_mode = igb_fc_setting;
 954         else
 955                 hw->fc.requested_mode = e1000_fc_none;
 956
 957         /* Issue a global reset */
 958         igb_pf_reset_hw(hw);
 959         E1000_WRITE_REG(hw, E1000_WUC, 0);
 960
 961         diag = e1000_init_hw(hw);
 962         if (diag < 0)
 963                 return (diag);
 964
 965         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 966         e1000_get_phy_info(hw);
 967         e1000_check_for_link(hw);
 968
 969         return (0);
 970 }
 971
 972 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
 973 static void
 974 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 975 {
 976         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 977         struct e1000_hw_stats *stats =
 978                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 979         int pause_frames;
 980
 981         if(hw->phy.media_type == e1000_media_type_copper ||
 982             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 983                 stats->symerrs +=
 984                     E1000_READ_REG(hw,E1000_SYMERRS);
 985                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 986         }
 987
 988         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 989         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 990         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 991         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 992
 993         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 994         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 995         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 996         stats->dc += E1000_READ_REG(hw, E1000_DC);
 997         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 998         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 999         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1000         /*
1001         ** For watchdog management we need to know if we have been
1002         ** paused during the last interval, so capture that here.
1003         */
1004         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1005         stats->xoffrxc += pause_frames;
1006         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1007         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1008         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1009         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1010         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1011         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1012         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1013         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1014         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1015         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1016         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1017         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1018
1019         /* For the 64-bit byte counters the low dword must be read first. */
1020         /* Both registers clear on the read of the high dword */
1021
1022         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1023         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1024         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1025         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1026
1027         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1028         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1029         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1030         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1031         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1032
1033         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1034         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1035
1036         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1037         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1038         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1039         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1040         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1041         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1042         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1043         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1044         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1045         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1046
1047         /* Interrupt Counts */
1048
1049         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1050         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1051         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1052         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1053         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1054         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1055         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1056         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1057         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1058
1059         /* Host to Card Statistics */
1060
1061         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1062         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1063         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1064         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1065         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1066         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1067         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1068         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1069         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1070         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1071         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1072         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1073         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1074         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1075
1076         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1077         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1078         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1079         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1080         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1081         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1082
1083         if (rte_stats == NULL)
1084                 return;
1085
1086         /* Rx Errors */
1087         rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
1088             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
1089
1090         /* Tx Errors */
1091         rte_stats->oerrors = stats->ecol + stats->latecol;
1092
1093         /* XON/XOFF pause frames */
1094         rte_stats->tx_pause_xon  = stats->xontxc;
1095         rte_stats->rx_pause_xon  = stats->xonrxc;
1096         rte_stats->tx_pause_xoff = stats->xofftxc;
1097         rte_stats->rx_pause_xoff = stats->xoffrxc;
1098
1099         rte_stats->ipackets = stats->gprc;
1100         rte_stats->opackets = stats->gptc;
1101         rte_stats->ibytes   = stats->gorc;
1102         rte_stats->obytes   = stats->gotc;
1103 }
1104
1105 static void
1106 eth_igb_stats_reset(struct rte_eth_dev *dev)
1107 {
1108         struct e1000_hw_stats *hw_stats =
1109                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1110
1111         /* HW registers are cleared on read */
1112         eth_igb_stats_get(dev, NULL);
1113
1114         /* Reset software totals */
1115         memset(hw_stats, 0, sizeof(*hw_stats));
1116 }
1117
1118 static void
1119 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1120 {
1121         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1122         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1123                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1124
1125         /* Good Rx packets, include VF loopback */
1126         UPDATE_VF_STAT(E1000_VFGPRC,
1127             hw_stats->last_gprc, hw_stats->gprc);
1128
1129         /* Good Rx octets, include VF loopback */
1130         UPDATE_VF_STAT(E1000_VFGORC,
1131             hw_stats->last_gorc, hw_stats->gorc);
1132
1133         /* Good Tx packets, include VF loopback */
1134         UPDATE_VF_STAT(E1000_VFGPTC,
1135             hw_stats->last_gptc, hw_stats->gptc);
1136
1137         /* Good Tx octets, include VF loopback */
1138         UPDATE_VF_STAT(E1000_VFGOTC,
1139             hw_stats->last_gotc, hw_stats->gotc);
1140
1141         /* Rx Multicst packets */
1142         UPDATE_VF_STAT(E1000_VFMPRC,
1143             hw_stats->last_mprc, hw_stats->mprc);
1144
1145         /* Good Rx loopback packets */
1146         UPDATE_VF_STAT(E1000_VFGPRLBC,
1147             hw_stats->last_gprlbc, hw_stats->gprlbc);
1148
1149         /* Good Rx loopback octets */
1150         UPDATE_VF_STAT(E1000_VFGORLBC,
1151             hw_stats->last_gorlbc, hw_stats->gorlbc);
1152
1153         /* Good Tx loopback packets */
1154         UPDATE_VF_STAT(E1000_VFGPTLBC,
1155             hw_stats->last_gptlbc, hw_stats->gptlbc);
1156
1157         /* Good Tx loopback octets */
1158         UPDATE_VF_STAT(E1000_VFGOTLBC,
1159             hw_stats->last_gotlbc, hw_stats->gotlbc);
1160
1161         if (rte_stats == NULL)
1162                 return;
1163
1164         memset(rte_stats, 0, sizeof(*rte_stats));
1165         rte_stats->ipackets = hw_stats->gprc;
1166         rte_stats->ibytes = hw_stats->gorc;
1167         rte_stats->opackets = hw_stats->gptc;
1168         rte_stats->obytes = hw_stats->gotc;
1169         rte_stats->imcasts = hw_stats->mprc;
1170         rte_stats->ilbpackets = hw_stats->gprlbc;
1171         rte_stats->ilbbytes = hw_stats->gorlbc;
1172         rte_stats->olbpackets = hw_stats->gptlbc;
1173         rte_stats->olbbytes = hw_stats->gotlbc;
1174
1175 }
1176
1177 static void
1178 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1179 {
1180         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1181                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1182
1183         /* Sync HW register to the last stats */
1184         eth_igbvf_stats_get(dev, NULL);
1185
1186         /* reset HW current stats*/
1187         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1188                offsetof(struct e1000_vf_stats, gprc));
1189
1190 }
1191
1192 static void
1193 eth_igb_infos_get(struct rte_eth_dev *dev,
1194                     struct rte_eth_dev_info *dev_info)
1195 {
1196         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1197
1198         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1199         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1200         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1201         dev_info->rx_offload_capa =
1202                 DEV_RX_OFFLOAD_VLAN_STRIP |
1203                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1204                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1205                 DEV_RX_OFFLOAD_TCP_CKSUM;
1206         dev_info->tx_offload_capa =
1207                 DEV_TX_OFFLOAD_VLAN_INSERT |
1208                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1209                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1210                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1211                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1212
1213         switch (hw->mac.type) {
1214         case e1000_82575:
1215                 dev_info->max_rx_queues = 4;
1216                 dev_info->max_tx_queues = 4;
1217                 dev_info->max_vmdq_pools = 0;
1218                 break;
1219
1220         case e1000_82576:
1221                 dev_info->max_rx_queues = 16;
1222                 dev_info->max_tx_queues = 16;
1223                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1224                 break;
1225
1226         case e1000_82580:
1227                 dev_info->max_rx_queues = 8;
1228                 dev_info->max_tx_queues = 8;
1229                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1230                 break;
1231
1232         case e1000_i350:
1233                 dev_info->max_rx_queues = 8;
1234                 dev_info->max_tx_queues = 8;
1235                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1236                 break;
1237
1238         case e1000_i354:
1239                 dev_info->max_rx_queues = 8;
1240                 dev_info->max_tx_queues = 8;
1241                 break;
1242
1243         case e1000_i210:
1244                 dev_info->max_rx_queues = 4;
1245                 dev_info->max_tx_queues = 4;
1246                 dev_info->max_vmdq_pools = 0;
1247                 break;
1248
1249         case e1000_vfadapt:
1250                 dev_info->max_rx_queues = 2;
1251                 dev_info->max_tx_queues = 2;
1252                 dev_info->max_vmdq_pools = 0;
1253                 break;
1254
1255         case e1000_vfadapt_i350:
1256                 dev_info->max_rx_queues = 1;
1257                 dev_info->max_tx_queues = 1;
1258                 dev_info->max_vmdq_pools = 0;
1259                 break;
1260
1261         default:
1262                 /* Should not happen */
1263                 dev_info->max_rx_queues = 0;
1264                 dev_info->max_tx_queues = 0;
1265                 dev_info->max_vmdq_pools = 0;
1266         }
1267 }
1268
1269 /* return 0 means link status changed, -1 means not changed */
1270 static int
1271 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1272 {
1273         struct e1000_hw *hw =
1274                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1275         struct rte_eth_link link, old;
1276         int link_check, count;
1277
1278         link_check = 0;
1279         hw->mac.get_link_status = 1;
1280
1281         /* possible wait-to-complete in up to 9 seconds */
1282         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1283                 /* Read the real link status */
1284                 switch (hw->phy.media_type) {
1285                 case e1000_media_type_copper:
1286                         /* Do the work to read phy */
1287                         e1000_check_for_link(hw);
1288                         link_check = !hw->mac.get_link_status;
1289                         break;
1290
1291                 case e1000_media_type_fiber:
1292                         e1000_check_for_link(hw);
1293                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1294                                       E1000_STATUS_LU);
1295                         break;
1296
1297                 case e1000_media_type_internal_serdes:
1298                         e1000_check_for_link(hw);
1299                         link_check = hw->mac.serdes_has_link;
1300                         break;
1301
1302                 /* VF device is type_unknown */
1303                 case e1000_media_type_unknown:
1304                         eth_igbvf_link_update(hw);
1305                         link_check = !hw->mac.get_link_status;
1306                         break;
1307
1308                 default:
1309                         break;
1310                 }
1311                 if (link_check || wait_to_complete == 0)
1312                         break;
1313                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1314         }
1315         memset(&link, 0, sizeof(link));
1316         rte_igb_dev_atomic_read_link_status(dev, &link);
1317         old = link;
1318
1319         /* Now we check if a transition has happened */
1320         if (link_check) {
1321                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1322                                           &link.link_duplex);
1323                 link.link_status = 1;
1324         } else if (!link_check) {
1325                 link.link_speed = 0;
1326                 link.link_duplex = 0;
1327                 link.link_status = 0;
1328         }
1329         rte_igb_dev_atomic_write_link_status(dev, &link);
1330
1331         /* not changed */
1332         if (old.link_status == link.link_status)
1333                 return -1;
1334
1335         /* changed */
1336         return 0;
1337 }
1338
1339 /*
1340  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1341  * For ASF and Pass Through versions of f/w this means
1342  * that the driver is loaded.
1343  */
1344 static void
1345 igb_hw_control_acquire(struct e1000_hw *hw)
1346 {
1347         uint32_t ctrl_ext;
1348
1349         /* Let firmware know the driver has taken over */
1350         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1351         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1352 }
1353
1354 /*
1355  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1356  * For ASF and Pass Through versions of f/w this means that the
1357  * driver is no longer loaded.
1358  */
1359 static void
1360 igb_hw_control_release(struct e1000_hw *hw)
1361 {
1362         uint32_t ctrl_ext;
1363
1364         /* Let firmware taken over control of h/w */
1365         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1366         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1367                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1368 }
1369
1370 /*
1371  * Bit of a misnomer, what this really means is
1372  * to enable OS management of the system... aka
1373  * to disable special hardware management features.
1374  */
1375 static void
1376 igb_init_manageability(struct e1000_hw *hw)
1377 {
1378         if (e1000_enable_mng_pass_thru(hw)) {
1379                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1380                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1381
1382                 /* disable hardware interception of ARP */
1383                 manc &= ~(E1000_MANC_ARP_EN);
1384
1385                 /* enable receiving management packets to the host */
1386                 manc |= E1000_MANC_EN_MNG2HOST;
1387                 manc2h |= 1 << 5;  /* Mng Port 623 */
1388                 manc2h |= 1 << 6;  /* Mng Port 664 */
1389                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1390                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1391         }
1392 }
1393
1394 static void
1395 igb_release_manageability(struct e1000_hw *hw)
1396 {
1397         if (e1000_enable_mng_pass_thru(hw)) {
1398                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1399
1400                 manc |= E1000_MANC_ARP_EN;
1401                 manc &= ~E1000_MANC_EN_MNG2HOST;
1402
1403                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1404         }
1405 }
1406
1407 static void
1408 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1409 {
1410         struct e1000_hw *hw =
1411                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1412         uint32_t rctl;
1413
1414         rctl = E1000_READ_REG(hw, E1000_RCTL);
1415         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1416         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1417 }
1418
1419 static void
1420 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1421 {
1422         struct e1000_hw *hw =
1423                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1424         uint32_t rctl;
1425
1426         rctl = E1000_READ_REG(hw, E1000_RCTL);
1427         rctl &= (~E1000_RCTL_UPE);
1428         if (dev->data->all_multicast == 1)
1429                 rctl |= E1000_RCTL_MPE;
1430         else
1431                 rctl &= (~E1000_RCTL_MPE);
1432         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1433 }
1434
1435 static void
1436 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1437 {
1438         struct e1000_hw *hw =
1439                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1440         uint32_t rctl;
1441
1442         rctl = E1000_READ_REG(hw, E1000_RCTL);
1443         rctl |= E1000_RCTL_MPE;
1444         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1445 }
1446
1447 static void
1448 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1449 {
1450         struct e1000_hw *hw =
1451                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1452         uint32_t rctl;
1453
1454         if (dev->data->promiscuous == 1)
1455                 return; /* must remain in all_multicast mode */
1456         rctl = E1000_READ_REG(hw, E1000_RCTL);
1457         rctl &= (~E1000_RCTL_MPE);
1458         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1459 }
1460
1461 static int
1462 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1463 {
1464         struct e1000_hw *hw =
1465                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1466         struct e1000_vfta * shadow_vfta =
1467                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1468         uint32_t vfta;
1469         uint32_t vid_idx;
1470         uint32_t vid_bit;
1471
1472         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1473                               E1000_VFTA_ENTRY_MASK);
1474         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1475         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1476         if (on)
1477                 vfta |= vid_bit;
1478         else
1479                 vfta &= ~vid_bit;
1480         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1481
1482         /* update local VFTA copy */
1483         shadow_vfta->vfta[vid_idx] = vfta;
1484
1485         return 0;
1486 }
1487
1488 static void
1489 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1490 {
1491         struct e1000_hw *hw =
1492                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1493         uint32_t reg = ETHER_TYPE_VLAN ;
1494
1495         reg |= (tpid << 16);
1496         E1000_WRITE_REG(hw, E1000_VET, reg);
1497 }
1498
1499 static void
1500 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1501 {
1502         struct e1000_hw *hw =
1503                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1504         uint32_t reg;
1505
1506         /* Filter Table Disable */
1507         reg = E1000_READ_REG(hw, E1000_RCTL);
1508         reg &= ~E1000_RCTL_CFIEN;
1509         reg &= ~E1000_RCTL_VFE;
1510         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1511 }
1512
1513 static void
1514 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1515 {
1516         struct e1000_hw *hw =
1517                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518         struct e1000_vfta * shadow_vfta =
1519                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1520         uint32_t reg;
1521         int i;
1522
1523         /* Filter Table Enable, CFI not used for packet acceptance */
1524         reg = E1000_READ_REG(hw, E1000_RCTL);
1525         reg &= ~E1000_RCTL_CFIEN;
1526         reg |= E1000_RCTL_VFE;
1527         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1528
1529         /* restore VFTA table */
1530         for (i = 0; i < IGB_VFTA_SIZE; i++)
1531                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1532 }
1533
1534 static void
1535 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1536 {
1537         struct e1000_hw *hw =
1538                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1539         uint32_t reg;
1540
1541         /* VLAN Mode Disable */
1542         reg = E1000_READ_REG(hw, E1000_CTRL);
1543         reg &= ~E1000_CTRL_VME;
1544         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1545 }
1546
1547 static void
1548 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1549 {
1550         struct e1000_hw *hw =
1551                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1552         uint32_t reg;
1553
1554         /* VLAN Mode Enable */
1555         reg = E1000_READ_REG(hw, E1000_CTRL);
1556         reg |= E1000_CTRL_VME;
1557         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1558 }
1559
1560 static void
1561 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1562 {
1563         struct e1000_hw *hw =
1564                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1565         uint32_t reg;
1566
1567         /* CTRL_EXT: Extended VLAN */
1568         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1569         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1570         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1571
1572         /* Update maximum packet length */
1573         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1574                 E1000_WRITE_REG(hw, E1000_RLPML,
1575                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1576                                                 VLAN_TAG_SIZE);
1577 }
1578
1579 static void
1580 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1581 {
1582         struct e1000_hw *hw =
1583                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584         uint32_t reg;
1585
1586         /* CTRL_EXT: Extended VLAN */
1587         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1588         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1589         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1590
1591         /* Update maximum packet length */
1592         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1593                 E1000_WRITE_REG(hw, E1000_RLPML,
1594                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1595                                                 2 * VLAN_TAG_SIZE);
1596 }
1597
1598 static void
1599 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1600 {
1601         if(mask & ETH_VLAN_STRIP_MASK){
1602                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1603                         igb_vlan_hw_strip_enable(dev);
1604                 else
1605                         igb_vlan_hw_strip_disable(dev);
1606         }
1607
1608         if(mask & ETH_VLAN_FILTER_MASK){
1609                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1610                         igb_vlan_hw_filter_enable(dev);
1611                 else
1612                         igb_vlan_hw_filter_disable(dev);
1613         }
1614
1615         if(mask & ETH_VLAN_EXTEND_MASK){
1616                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1617                         igb_vlan_hw_extend_enable(dev);
1618                 else
1619                         igb_vlan_hw_extend_disable(dev);
1620         }
1621 }
1622
1623
1624 /**
1625  * It enables the interrupt mask and then enable the interrupt.
1626  *
1627  * @param dev
1628  *  Pointer to struct rte_eth_dev.
1629  *
1630  * @return
1631  *  - On success, zero.
1632  *  - On failure, a negative value.
1633  */
1634 static int
1635 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1636 {
1637         struct e1000_interrupt *intr =
1638                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1639
1640         intr->mask |= E1000_ICR_LSC;
1641
1642         return 0;
1643 }
1644
1645 /*
1646  * It reads ICR and gets interrupt causes, check it and set a bit flag
1647  * to update link status.
1648  *
1649  * @param dev
1650  *  Pointer to struct rte_eth_dev.
1651  *
1652  * @return
1653  *  - On success, zero.
1654  *  - On failure, a negative value.
1655  */
1656 static int
1657 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1658 {
1659         uint32_t icr;
1660         struct e1000_hw *hw =
1661                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1662         struct e1000_interrupt *intr =
1663                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1664
1665         igb_intr_disable(hw);
1666
1667         /* read-on-clear nic registers here */
1668         icr = E1000_READ_REG(hw, E1000_ICR);
1669
1670         intr->flags = 0;
1671         if (icr & E1000_ICR_LSC) {
1672                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1673         }
1674
1675         if (icr & E1000_ICR_VMMB)
1676                 intr->flags |= E1000_FLAG_MAILBOX;
1677
1678         return 0;
1679 }
1680
1681 /*
1682  * It executes link_update after knowing an interrupt is prsent.
1683  *
1684  * @param dev
1685  *  Pointer to struct rte_eth_dev.
1686  *
1687  * @return
1688  *  - On success, zero.
1689  *  - On failure, a negative value.
1690  */
1691 static int
1692 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1693 {
1694         struct e1000_hw *hw =
1695                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1696         struct e1000_interrupt *intr =
1697                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1698         uint32_t tctl, rctl;
1699         struct rte_eth_link link;
1700         int ret;
1701
1702         if (intr->flags & E1000_FLAG_MAILBOX) {
1703                 igb_pf_mbx_process(dev);
1704                 intr->flags &= ~E1000_FLAG_MAILBOX;
1705         }
1706
1707         igb_intr_enable(dev);
1708         rte_intr_enable(&(dev->pci_dev->intr_handle));
1709
1710         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1711                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1712
1713                 /* set get_link_status to check register later */
1714                 hw->mac.get_link_status = 1;
1715                 ret = eth_igb_link_update(dev, 0);
1716
1717                 /* check if link has changed */
1718                 if (ret < 0)
1719                         return 0;
1720
1721                 memset(&link, 0, sizeof(link));
1722                 rte_igb_dev_atomic_read_link_status(dev, &link);
1723                 if (link.link_status) {
1724                         PMD_INIT_LOG(INFO,
1725                                 " Port %d: Link Up - speed %u Mbps - %s\n",
1726                                 dev->data->port_id, (unsigned)link.link_speed,
1727                                 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1728                                         "full-duplex" : "half-duplex");
1729                 } else {
1730                         PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1731                                                 dev->data->port_id);
1732                 }
1733                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1734                                         dev->pci_dev->addr.domain,
1735                                         dev->pci_dev->addr.bus,
1736                                         dev->pci_dev->addr.devid,
1737                                         dev->pci_dev->addr.function);
1738                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1739                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1740                 if (link.link_status) {
1741                         /* enable Tx/Rx */
1742                         tctl |= E1000_TCTL_EN;
1743                         rctl |= E1000_RCTL_EN;
1744                 } else {
1745                         /* disable Tx/Rx */
1746                         tctl &= ~E1000_TCTL_EN;
1747                         rctl &= ~E1000_RCTL_EN;
1748                 }
1749                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1750                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1751                 E1000_WRITE_FLUSH(hw);
1752                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1753         }
1754
1755         return 0;
1756 }
1757
1758 /**
1759  * Interrupt handler which shall be registered at first.
1760  *
1761  * @param handle
1762  *  Pointer to interrupt handle.
1763  * @param param
1764  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1765  *
1766  * @return
1767  *  void
1768  */
1769 static void
1770 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1771                                                         void *param)
1772 {
1773         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1774
1775         eth_igb_interrupt_get_status(dev);
1776         eth_igb_interrupt_action(dev);
1777 }
1778
1779 static int
1780 eth_igb_led_on(struct rte_eth_dev *dev)
1781 {
1782         struct e1000_hw *hw;
1783
1784         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1785         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1786 }
1787
1788 static int
1789 eth_igb_led_off(struct rte_eth_dev *dev)
1790 {
1791         struct e1000_hw *hw;
1792
1793         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1794         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1795 }
1796
1797 static int
1798 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1799 {
1800         struct e1000_hw *hw;
1801         int err;
1802         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1803                 e1000_fc_none,
1804                 e1000_fc_rx_pause,
1805                 e1000_fc_tx_pause,
1806                 e1000_fc_full
1807         };
1808         uint32_t rx_buf_size;
1809         uint32_t max_high_water;
1810         uint32_t rctl;
1811
1812         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1813         rx_buf_size = igb_get_rx_buffer_size(hw);
1814         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1815
1816         /* At least reserve one Ethernet frame for watermark */
1817         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1818         if ((fc_conf->high_water > max_high_water) ||
1819                 (fc_conf->high_water < fc_conf->low_water)) {
1820                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1821                 PMD_INIT_LOG(ERR, "high water must <=  0x%x \n", max_high_water);
1822                 return (-EINVAL);
1823         }
1824
1825         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1826         hw->fc.pause_time     = fc_conf->pause_time;
1827         hw->fc.high_water     = fc_conf->high_water;
1828         hw->fc.low_water      = fc_conf->low_water;
1829         hw->fc.send_xon       = fc_conf->send_xon;
1830
1831         err = e1000_setup_link_generic(hw);
1832         if (err == E1000_SUCCESS) {
1833
1834                 /* check if we want to forward MAC frames - driver doesn't have native
1835                  * capability to do that, so we'll write the registers ourselves */
1836
1837                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1838
1839                 /* set or clear MFLCN.PMCF bit depending on configuration */
1840                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1841                         rctl |= E1000_RCTL_PMCF;
1842                 else
1843                         rctl &= ~E1000_RCTL_PMCF;
1844
1845                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1846                 E1000_WRITE_FLUSH(hw);
1847
1848                 return 0;
1849         }
1850
1851         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1852         return (-EIO);
1853 }
1854
1855 #define E1000_RAH_POOLSEL_SHIFT      (18)
1856 static void
1857 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1858                 uint32_t index, __rte_unused uint32_t pool)
1859 {
1860         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1861         uint32_t rah;
1862
1863         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1864         rah = E1000_READ_REG(hw, E1000_RAH(index));
1865         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1866         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1867 }
1868
1869 static void
1870 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1871 {
1872         uint8_t addr[ETHER_ADDR_LEN];
1873         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1874
1875         memset(addr, 0, sizeof(addr));
1876
1877         e1000_rar_set(hw, addr, index);
1878 }
1879
1880 /*
1881  * Virtual Function operations
1882  */
1883 static void
1884 igbvf_intr_disable(struct e1000_hw *hw)
1885 {
1886         PMD_INIT_LOG(DEBUG, "igbvf_intr_disable");
1887
1888         /* Clear interrupt mask to stop from interrupts being generated */
1889         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
1890
1891         E1000_WRITE_FLUSH(hw);
1892 }
1893
1894 static void
1895 igbvf_stop_adapter(struct rte_eth_dev *dev)
1896 {
1897         u32 reg_val;
1898         u16 i;
1899         struct rte_eth_dev_info dev_info;
1900         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901
1902         memset(&dev_info, 0, sizeof(dev_info));
1903         eth_igb_infos_get(dev, &dev_info);
1904
1905         /* Clear interrupt mask to stop from interrupts being generated */
1906         igbvf_intr_disable(hw);
1907
1908         /* Clear any pending interrupts, flush previous writes */
1909         E1000_READ_REG(hw, E1000_EICR);
1910
1911         /* Disable the transmit unit.  Each queue must be disabled. */
1912         for (i = 0; i < dev_info.max_tx_queues; i++)
1913                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
1914
1915         /* Disable the receive unit by stopping each queue */
1916         for (i = 0; i < dev_info.max_rx_queues; i++) {
1917                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
1918                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
1919                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
1920                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
1921                         ;
1922         }
1923
1924         /* flush all queues disables */
1925         E1000_WRITE_FLUSH(hw);
1926         msec_delay(2);
1927 }
1928
1929 static int eth_igbvf_link_update(struct e1000_hw *hw)
1930 {
1931         struct e1000_mbx_info *mbx = &hw->mbx;
1932         struct e1000_mac_info *mac = &hw->mac;
1933         int ret_val = E1000_SUCCESS;
1934
1935         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
1936
1937         /*
1938          * We only want to run this if there has been a rst asserted.
1939          * in this case that could mean a link change, device reset,
1940          * or a virtual function reset
1941          */
1942
1943         /* If we were hit with a reset or timeout drop the link */
1944         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
1945                 mac->get_link_status = TRUE;
1946
1947         if (!mac->get_link_status)
1948                 goto out;
1949
1950         /* if link status is down no point in checking to see if pf is up */
1951         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
1952                 goto out;
1953
1954         /* if we passed all the tests above then the link is up and we no
1955          * longer need to check for link */
1956         mac->get_link_status = FALSE;
1957
1958 out:
1959         return ret_val;
1960 }
1961
1962
1963 static int
1964 igbvf_dev_configure(struct rte_eth_dev *dev)
1965 {
1966         struct rte_eth_conf* conf = &dev->data->dev_conf;
1967
1968         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
1969                 dev->data->port_id);
1970
1971         /*
1972          * VF has no ability to enable/disable HW CRC
1973          * Keep the persistent behavior the same as Host PF
1974          */
1975 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
1976         if (!conf->rxmode.hw_strip_crc) {
1977                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
1978                 conf->rxmode.hw_strip_crc = 1;
1979         }
1980 #else
1981         if (conf->rxmode.hw_strip_crc) {
1982                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
1983                 conf->rxmode.hw_strip_crc = 0;
1984         }
1985 #endif
1986
1987         return 0;
1988 }
1989
1990 static int
1991 igbvf_dev_start(struct rte_eth_dev *dev)
1992 {
1993         struct e1000_hw *hw =
1994                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1995         int ret;
1996
1997         PMD_INIT_LOG(DEBUG, "igbvf_dev_start");
1998
1999         hw->mac.ops.reset_hw(hw);
2000
2001         /* Set all vfta */
2002         igbvf_set_vfta_all(dev,1);
2003
2004         eth_igbvf_tx_init(dev);
2005
2006         /* This can fail when allocating mbufs for descriptor rings */
2007         ret = eth_igbvf_rx_init(dev);
2008         if (ret) {
2009                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2010                 igb_dev_clear_queues(dev);
2011                 return ret;
2012         }
2013
2014         return 0;
2015 }
2016
2017 static void
2018 igbvf_dev_stop(struct rte_eth_dev *dev)
2019 {
2020         PMD_INIT_LOG(DEBUG, "igbvf_dev_stop");
2021
2022         igbvf_stop_adapter(dev);
2023
2024         /*
2025           * Clear what we set, but we still keep shadow_vfta to
2026           * restore after device starts
2027           */
2028         igbvf_set_vfta_all(dev,0);
2029
2030         igb_dev_clear_queues(dev);
2031 }
2032
2033 static void
2034 igbvf_dev_close(struct rte_eth_dev *dev)
2035 {
2036         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2037
2038         PMD_INIT_LOG(DEBUG, "igbvf_dev_close");
2039
2040         e1000_reset_hw(hw);
2041
2042         igbvf_dev_stop(dev);
2043 }
2044
2045 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2046 {
2047         struct e1000_mbx_info *mbx = &hw->mbx;
2048         uint32_t msgbuf[2];
2049
2050         /* After set vlan, vlan strip will also be enabled in igb driver*/
2051         msgbuf[0] = E1000_VF_SET_VLAN;
2052         msgbuf[1] = vid;
2053         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2054         if (on)
2055                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2056
2057         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2058 }
2059
2060 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2061 {
2062         struct e1000_hw *hw =
2063                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2064         struct e1000_vfta * shadow_vfta =
2065                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2066         int i = 0, j = 0, vfta = 0, mask = 1;
2067
2068         for (i = 0; i < IGB_VFTA_SIZE; i++){
2069                 vfta = shadow_vfta->vfta[i];
2070                 if(vfta){
2071                         mask = 1;
2072                         for (j = 0; j < 32; j++){
2073                                 if(vfta & mask)
2074                                         igbvf_set_vfta(hw,
2075                                                 (uint16_t)((i<<5)+j), on);
2076                                 mask<<=1;
2077                         }
2078                 }
2079         }
2080
2081 }
2082
2083 static int
2084 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2085 {
2086         struct e1000_hw *hw =
2087                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088         struct e1000_vfta * shadow_vfta =
2089                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2090         uint32_t vid_idx = 0;
2091         uint32_t vid_bit = 0;
2092         int ret = 0;
2093
2094         PMD_INIT_LOG(DEBUG, "igbvf_vlan_filter_set");
2095
2096         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2097         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2098         if(ret){
2099                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2100                 return ret;
2101         }
2102         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2103         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2104
2105         /*Save what we set and retore it after device reset*/
2106         if (on)
2107                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2108         else
2109                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2110
2111         return 0;
2112 }
2113
2114 static int
2115 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2116                                 struct rte_eth_rss_reta *reta_conf)
2117 {
2118         uint8_t i,j,mask;
2119         uint32_t reta;
2120         struct e1000_hw *hw =
2121                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2122
2123         /*
2124          * Update Redirection Table RETA[n],n=0...31,The redirection table has
2125          * 128-entries in 32 registers
2126          */
2127         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2128                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2129                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2130                 else
2131                         mask = (uint8_t)((reta_conf->mask_hi >>
2132                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2133                 if (mask != 0) {
2134                         reta = 0;
2135                         /* If all 4 entries were set,don't need read RETA register */
2136                         if (mask != 0xF)
2137                                 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2138
2139                         for (j = 0; j < 4; j++) {
2140                                 if (mask & (0x1 << j)) {
2141                                         if (mask != 0xF)
2142                                                 reta &= ~(0xFF << 8 * j);
2143                                         reta |= reta_conf->reta[i + j] << 8 * j;
2144                                 }
2145                         }
2146                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2147                 }
2148         }
2149
2150         return 0;
2151 }
2152
2153 static int
2154 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2155                                 struct rte_eth_rss_reta *reta_conf)
2156 {
2157         uint8_t i,j,mask;
2158         uint32_t reta;
2159         struct e1000_hw *hw =
2160                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2161
2162         /*
2163          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2164          * 128-entries in 32 registers
2165          */
2166         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2167                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2168                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2169                 else
2170                         mask = (uint8_t)((reta_conf->mask_hi >>
2171                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2172
2173                 if (mask != 0) {
2174                         reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2175                         for (j = 0; j < 4; j++) {
2176                                 if (mask & (0x1 << j))
2177                                         reta_conf->reta[i + j] =
2178                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2179                         }
2180                 }
2181         }
2182
2183         return 0;
2184 }