lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 /* Bit shift and mask */
  73 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  74 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  75 #define IGB_8_BIT_WIDTH  CHAR_BIT
  76 #define IGB_8_BIT_MASK   UINT8_MAX
  77
  78 static int  eth_igb_configure(struct rte_eth_dev *dev);
  79 static int  eth_igb_start(struct rte_eth_dev *dev);
  80 static void eth_igb_stop(struct rte_eth_dev *dev);
  81 static void eth_igb_close(struct rte_eth_dev *dev);
  82 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  91 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  92                               struct rte_eth_dev_info *dev_info);
  93 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
  94                                 struct rte_eth_dev_info *dev_info);
  95 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
  96                                 struct rte_eth_fc_conf *fc_conf);
  97 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  98                                 struct rte_eth_fc_conf *fc_conf);
  99 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 100 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 101 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 102 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 103                                                         void *param);
 104 static int  igb_hardware_init(struct e1000_hw *hw);
 105 static void igb_hw_control_acquire(struct e1000_hw *hw);
 106 static void igb_hw_control_release(struct e1000_hw *hw);
 107 static void igb_init_manageability(struct e1000_hw *hw);
 108 static void igb_release_manageability(struct e1000_hw *hw);
 109
 110 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 111
 112 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 113                 uint16_t vlan_id, int on);
 114 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 115 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 116
 117 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 118 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 119 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 120 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 121 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 122 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 123
 124 static int eth_igb_led_on(struct rte_eth_dev *dev);
 125 static int eth_igb_led_off(struct rte_eth_dev *dev);
 126
 127 static void igb_intr_disable(struct e1000_hw *hw);
 128 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 129 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 130                 struct ether_addr *mac_addr,
 131                 uint32_t index, uint32_t pool);
 132 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 133
 134 static void igbvf_intr_disable(struct e1000_hw *hw);
 135 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 136 static int igbvf_dev_start(struct rte_eth_dev *dev);
 137 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 138 static void igbvf_dev_close(struct rte_eth_dev *dev);
 139 static int eth_igbvf_link_update(struct e1000_hw *hw);
 140 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 141 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 142 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 143                 uint16_t vlan_id, int on);
 144 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 145 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 146 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 147                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 148                                    uint16_t reta_size);
 149 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 150                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 151                                   uint16_t reta_size);
 152 static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,
 153                         struct rte_syn_filter *filter, uint16_t rx_queue);
 154 static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);
 155 static int eth_igb_get_syn_filter(struct rte_eth_dev *dev,
 156                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 157 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
 158                         uint16_t index,
 159                         struct rte_2tuple_filter *filter, uint16_t rx_queue);
 160 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 161                         uint16_t index);
 162 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
 163                         uint16_t index,
 164                         struct rte_2tuple_filter *filter, uint16_t *rx_queue);
 165 static int eth_igb_add_flex_filter(struct rte_eth_dev *dev,
 166                         uint16_t index,
 167                         struct rte_flex_filter *filter, uint16_t rx_queue);
 168 static int eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
 169                         uint16_t index);
 170 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 171                         uint16_t index,
 172                         struct rte_flex_filter *filter, uint16_t *rx_queue);
 173 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
 174                         uint16_t index,
 175                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 176 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
 177                         uint16_t index);
 178 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
 179                         uint16_t index,
 180                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 181 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 182                         struct rte_eth_ethertype_filter *filter,
 183                         bool add);
 184 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 185                                 enum rte_filter_op filter_op,
 186                                 void *arg);
 187 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 188                         struct rte_eth_ethertype_filter *filter);
 189 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 190                      enum rte_filter_type filter_type,
 191                      enum rte_filter_op filter_op,
 192                      void *arg);
 193
 194 /*
 195  * Define VF Stats MACRO for Non "cleared on read" register
 196  */
 197 #define UPDATE_VF_STAT(reg, last, cur)            \
 198 {                                                 \
 199         u32 latest = E1000_READ_REG(hw, reg);     \
 200         cur += latest - last;                     \
 201         last = latest;                            \
 202 }
 203
 204
 205 #define IGB_FC_PAUSE_TIME 0x0680
 206 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 207 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 208
 209 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 210
 211 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 212
 213 /*
 214  * The set of PCI devices this driver supports
 215  */
 216 static struct rte_pci_id pci_id_igb_map[] = {
 217
 218 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 219 #include "rte_pci_dev_ids.h"
 220
 221 {.device_id = 0},
 222 };
 223
 224 /*
 225  * The set of PCI devices this driver supports (for 82576&I350 VF)
 226  */
 227 static struct rte_pci_id pci_id_igbvf_map[] = {
 228
 229 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 230 #include "rte_pci_dev_ids.h"
 231
 232 {.device_id = 0},
 233 };
 234
 235 static struct eth_dev_ops eth_igb_ops = {
 236         .dev_configure        = eth_igb_configure,
 237         .dev_start            = eth_igb_start,
 238         .dev_stop             = eth_igb_stop,
 239         .dev_close            = eth_igb_close,
 240         .promiscuous_enable   = eth_igb_promiscuous_enable,
 241         .promiscuous_disable  = eth_igb_promiscuous_disable,
 242         .allmulticast_enable  = eth_igb_allmulticast_enable,
 243         .allmulticast_disable = eth_igb_allmulticast_disable,
 244         .link_update          = eth_igb_link_update,
 245         .stats_get            = eth_igb_stats_get,
 246         .stats_reset          = eth_igb_stats_reset,
 247         .dev_infos_get        = eth_igb_infos_get,
 248         .mtu_set              = eth_igb_mtu_set,
 249         .vlan_filter_set      = eth_igb_vlan_filter_set,
 250         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 251         .vlan_offload_set     = eth_igb_vlan_offload_set,
 252         .rx_queue_setup       = eth_igb_rx_queue_setup,
 253         .rx_queue_release     = eth_igb_rx_queue_release,
 254         .rx_queue_count       = eth_igb_rx_queue_count,
 255         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 256         .tx_queue_setup       = eth_igb_tx_queue_setup,
 257         .tx_queue_release     = eth_igb_tx_queue_release,
 258         .dev_led_on           = eth_igb_led_on,
 259         .dev_led_off          = eth_igb_led_off,
 260         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 261         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 262         .mac_addr_add         = eth_igb_rar_set,
 263         .mac_addr_remove      = eth_igb_rar_clear,
 264         .reta_update          = eth_igb_rss_reta_update,
 265         .reta_query           = eth_igb_rss_reta_query,
 266         .rss_hash_update      = eth_igb_rss_hash_update,
 267         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 268         .add_syn_filter          = eth_igb_add_syn_filter,
 269         .remove_syn_filter       = eth_igb_remove_syn_filter,
 270         .get_syn_filter          = eth_igb_get_syn_filter,
 271         .add_2tuple_filter       = eth_igb_add_2tuple_filter,
 272         .remove_2tuple_filter    = eth_igb_remove_2tuple_filter,
 273         .get_2tuple_filter       = eth_igb_get_2tuple_filter,
 274         .add_flex_filter         = eth_igb_add_flex_filter,
 275         .remove_flex_filter      = eth_igb_remove_flex_filter,
 276         .get_flex_filter         = eth_igb_get_flex_filter,
 277         .add_5tuple_filter       = eth_igb_add_5tuple_filter,
 278         .remove_5tuple_filter    = eth_igb_remove_5tuple_filter,
 279         .get_5tuple_filter       = eth_igb_get_5tuple_filter,
 280         .filter_ctrl             = eth_igb_filter_ctrl,
 281 };
 282
 283 /*
 284  * dev_ops for virtual function, bare necessities for basic vf
 285  * operation have been implemented
 286  */
 287 static struct eth_dev_ops igbvf_eth_dev_ops = {
 288         .dev_configure        = igbvf_dev_configure,
 289         .dev_start            = igbvf_dev_start,
 290         .dev_stop             = igbvf_dev_stop,
 291         .dev_close            = igbvf_dev_close,
 292         .link_update          = eth_igb_link_update,
 293         .stats_get            = eth_igbvf_stats_get,
 294         .stats_reset          = eth_igbvf_stats_reset,
 295         .vlan_filter_set      = igbvf_vlan_filter_set,
 296         .dev_infos_get        = eth_igbvf_infos_get,
 297         .rx_queue_setup       = eth_igb_rx_queue_setup,
 298         .rx_queue_release     = eth_igb_rx_queue_release,
 299         .tx_queue_setup       = eth_igb_tx_queue_setup,
 300         .tx_queue_release     = eth_igb_tx_queue_release,
 301 };
 302
 303 /**
 304  * Atomically reads the link status information from global
 305  * structure rte_eth_dev.
 306  *
 307  * @param dev
 308  *   - Pointer to the structure rte_eth_dev to read from.
 309  *   - Pointer to the buffer to be saved with the link status.
 310  *
 311  * @return
 312  *   - On success, zero.
 313  *   - On failure, negative value.
 314  */
 315 static inline int
 316 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 317                                 struct rte_eth_link *link)
 318 {
 319         struct rte_eth_link *dst = link;
 320         struct rte_eth_link *src = &(dev->data->dev_link);
 321
 322         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 323                                         *(uint64_t *)src) == 0)
 324                 return -1;
 325
 326         return 0;
 327 }
 328
 329 /**
 330  * Atomically writes the link status information into global
 331  * structure rte_eth_dev.
 332  *
 333  * @param dev
 334  *   - Pointer to the structure rte_eth_dev to read from.
 335  *   - Pointer to the buffer to be saved with the link status.
 336  *
 337  * @return
 338  *   - On success, zero.
 339  *   - On failure, negative value.
 340  */
 341 static inline int
 342 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 343                                 struct rte_eth_link *link)
 344 {
 345         struct rte_eth_link *dst = &(dev->data->dev_link);
 346         struct rte_eth_link *src = link;
 347
 348         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 349                                         *(uint64_t *)src) == 0)
 350                 return -1;
 351
 352         return 0;
 353 }
 354
 355 static inline void
 356 igb_intr_enable(struct rte_eth_dev *dev)
 357 {
 358         struct e1000_interrupt *intr =
 359                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 360         struct e1000_hw *hw =
 361                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 362
 363         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 364         E1000_WRITE_FLUSH(hw);
 365 }
 366
 367 static void
 368 igb_intr_disable(struct e1000_hw *hw)
 369 {
 370         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 371         E1000_WRITE_FLUSH(hw);
 372 }
 373
 374 static inline int32_t
 375 igb_pf_reset_hw(struct e1000_hw *hw)
 376 {
 377         uint32_t ctrl_ext;
 378         int32_t status;
 379
 380         status = e1000_reset_hw(hw);
 381
 382         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 383         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 384         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 385         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 386         E1000_WRITE_FLUSH(hw);
 387
 388         return status;
 389 }
 390
 391 static void
 392 igb_identify_hardware(struct rte_eth_dev *dev)
 393 {
 394         struct e1000_hw *hw =
 395                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 396
 397         hw->vendor_id = dev->pci_dev->id.vendor_id;
 398         hw->device_id = dev->pci_dev->id.device_id;
 399         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 400         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 401
 402         e1000_set_mac_type(hw);
 403
 404         /* need to check if it is a vf device below */
 405 }
 406
 407 static int
 408 igb_reset_swfw_lock(struct e1000_hw *hw)
 409 {
 410         int ret_val;
 411
 412         /*
 413          * Do mac ops initialization manually here, since we will need
 414          * some function pointers set by this call.
 415          */
 416         ret_val = e1000_init_mac_params(hw);
 417         if (ret_val)
 418                 return ret_val;
 419
 420         /*
 421          * SMBI lock should not fail in this early stage. If this is the case,
 422          * it is due to an improper exit of the application.
 423          * So force the release of the faulty lock.
 424          */
 425         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 426                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 427         }
 428         e1000_put_hw_semaphore_generic(hw);
 429
 430         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 431                 uint16_t mask;
 432
 433                 /*
 434                  * Phy lock should not fail in this early stage. If this is the case,
 435                  * it is due to an improper exit of the application.
 436                  * So force the release of the faulty lock.
 437                  */
 438                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 439                 if (hw->bus.func > E1000_FUNC_1)
 440                         mask <<= 2;
 441                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 442                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 443                                     hw->bus.func);
 444                 }
 445                 hw->mac.ops.release_swfw_sync(hw, mask);
 446
 447                 /*
 448                  * This one is more tricky since it is common to all ports; but
 449                  * swfw_sync retries last long enough (1s) to be almost sure that if
 450                  * lock can not be taken it is due to an improper lock of the
 451                  * semaphore.
 452                  */
 453                 mask = E1000_SWFW_EEP_SM;
 454                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 455                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 456                 }
 457                 hw->mac.ops.release_swfw_sync(hw, mask);
 458         }
 459
 460         return E1000_SUCCESS;
 461 }
 462
 463 static int
 464 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 465                    struct rte_eth_dev *eth_dev)
 466 {
 467         int error = 0;
 468         struct rte_pci_device *pci_dev;
 469         struct e1000_hw *hw =
 470                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 471         struct e1000_vfta * shadow_vfta =
 472                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 473         uint32_t ctrl_ext;
 474
 475         pci_dev = eth_dev->pci_dev;
 476         eth_dev->dev_ops = &eth_igb_ops;
 477         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 478         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 479
 480         /* for secondary processes, we don't initialise any further as primary
 481          * has already done this work. Only check we don't need a different
 482          * RX function */
 483         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 484                 if (eth_dev->data->scattered_rx)
 485                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 486                 return 0;
 487         }
 488
 489         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 490
 491         igb_identify_hardware(eth_dev);
 492         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 493                 error = -EIO;
 494                 goto err_late;
 495         }
 496
 497         e1000_get_bus_info(hw);
 498
 499         /* Reset any pending lock */
 500         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 501                 error = -EIO;
 502                 goto err_late;
 503         }
 504
 505         /* Finish initialization */
 506         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 507                 error = -EIO;
 508                 goto err_late;
 509         }
 510
 511         hw->mac.autoneg = 1;
 512         hw->phy.autoneg_wait_to_complete = 0;
 513         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 514
 515         /* Copper options */
 516         if (hw->phy.media_type == e1000_media_type_copper) {
 517                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 518                 hw->phy.disable_polarity_correction = 0;
 519                 hw->phy.ms_type = e1000_ms_hw_default;
 520         }
 521
 522         /*
 523          * Start from a known state, this is important in reading the nvm
 524          * and mac from that.
 525          */
 526         igb_pf_reset_hw(hw);
 527
 528         /* Make sure we have a good EEPROM before we read from it */
 529         if (e1000_validate_nvm_checksum(hw) < 0) {
 530                 /*
 531                  * Some PCI-E parts fail the first check due to
 532                  * the link being in sleep state, call it again,
 533                  * if it fails a second time its a real issue.
 534                  */
 535                 if (e1000_validate_nvm_checksum(hw) < 0) {
 536                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 537                         error = -EIO;
 538                         goto err_late;
 539                 }
 540         }
 541
 542         /* Read the permanent MAC address out of the EEPROM */
 543         if (e1000_read_mac_addr(hw) != 0) {
 544                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 545                 error = -EIO;
 546                 goto err_late;
 547         }
 548
 549         /* Allocate memory for storing MAC addresses */
 550         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 551                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 552         if (eth_dev->data->mac_addrs == NULL) {
 553                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 554                                                 "store MAC addresses",
 555                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 556                 error = -ENOMEM;
 557                 goto err_late;
 558         }
 559
 560         /* Copy the permanent MAC address */
 561         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 562
 563         /* initialize the vfta */
 564         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 565
 566         /* Now initialize the hardware */
 567         if (igb_hardware_init(hw) != 0) {
 568                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 569                 rte_free(eth_dev->data->mac_addrs);
 570                 eth_dev->data->mac_addrs = NULL;
 571                 error = -ENODEV;
 572                 goto err_late;
 573         }
 574         hw->mac.get_link_status = 1;
 575
 576         /* Indicate SOL/IDER usage */
 577         if (e1000_check_reset_block(hw) < 0) {
 578                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 579                                         "SOL/IDER session");
 580         }
 581
 582         /* initialize PF if max_vfs not zero */
 583         igb_pf_host_init(eth_dev);
 584
 585         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 586         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 587         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 588         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 589         E1000_WRITE_FLUSH(hw);
 590
 591         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 592                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 593                      pci_dev->id.device_id);
 594
 595         rte_intr_callback_register(&(pci_dev->intr_handle),
 596                 eth_igb_interrupt_handler, (void *)eth_dev);
 597
 598         /* enable uio intr after callback register */
 599         rte_intr_enable(&(pci_dev->intr_handle));
 600
 601         /* enable support intr */
 602         igb_intr_enable(eth_dev);
 603
 604         return 0;
 605
 606 err_late:
 607         igb_hw_control_release(hw);
 608
 609         return (error);
 610 }
 611
 612 /*
 613  * Virtual Function device init
 614  */
 615 static int
 616 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 617                 struct rte_eth_dev *eth_dev)
 618 {
 619         struct rte_pci_device *pci_dev;
 620         struct e1000_hw *hw =
 621                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 622         int diag;
 623
 624         PMD_INIT_FUNC_TRACE();
 625
 626         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 627         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 628         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 629
 630         /* for secondary processes, we don't initialise any further as primary
 631          * has already done this work. Only check we don't need a different
 632          * RX function */
 633         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 634                 if (eth_dev->data->scattered_rx)
 635                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 636                 return 0;
 637         }
 638
 639         pci_dev = eth_dev->pci_dev;
 640
 641         hw->device_id = pci_dev->id.device_id;
 642         hw->vendor_id = pci_dev->id.vendor_id;
 643         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 644
 645         /* Initialize the shared code (base driver) */
 646         diag = e1000_setup_init_funcs(hw, TRUE);
 647         if (diag != 0) {
 648                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 649                         diag);
 650                 return -EIO;
 651         }
 652
 653         /* init_mailbox_params */
 654         hw->mbx.ops.init_params(hw);
 655
 656         /* Disable the interrupts for VF */
 657         igbvf_intr_disable(hw);
 658
 659         diag = hw->mac.ops.reset_hw(hw);
 660
 661         /* Allocate memory for storing MAC addresses */
 662         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 663                 hw->mac.rar_entry_count, 0);
 664         if (eth_dev->data->mac_addrs == NULL) {
 665                 PMD_INIT_LOG(ERR,
 666                         "Failed to allocate %d bytes needed to store MAC "
 667                         "addresses",
 668                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 669                 return -ENOMEM;
 670         }
 671
 672         /* Copy the permanent MAC address */
 673         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 674                         &eth_dev->data->mac_addrs[0]);
 675
 676         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 677                      "mac.type=%s",
 678                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 679                      pci_dev->id.device_id, "igb_mac_82576_vf");
 680
 681         return 0;
 682 }
 683
 684 static struct eth_driver rte_igb_pmd = {
 685         {
 686                 .name = "rte_igb_pmd",
 687                 .id_table = pci_id_igb_map,
 688                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 689         },
 690         .eth_dev_init = eth_igb_dev_init,
 691         .dev_private_size = sizeof(struct e1000_adapter),
 692 };
 693
 694 /*
 695  * virtual function driver struct
 696  */
 697 static struct eth_driver rte_igbvf_pmd = {
 698         {
 699                 .name = "rte_igbvf_pmd",
 700                 .id_table = pci_id_igbvf_map,
 701                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 702         },
 703         .eth_dev_init = eth_igbvf_dev_init,
 704         .dev_private_size = sizeof(struct e1000_adapter),
 705 };
 706
 707 static int
 708 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 709 {
 710         rte_eth_driver_register(&rte_igb_pmd);
 711         return 0;
 712 }
 713
 714 static void
 715 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 716 {
 717         struct e1000_hw *hw =
 718                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 719         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 720         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 721         rctl |= E1000_RCTL_VFE;
 722         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 723 }
 724
 725 /*
 726  * VF Driver initialization routine.
 727  * Invoked one at EAL init time.
 728  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 729  */
 730 static int
 731 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 732 {
 733         PMD_INIT_FUNC_TRACE();
 734
 735         rte_eth_driver_register(&rte_igbvf_pmd);
 736         return (0);
 737 }
 738
 739 static int
 740 eth_igb_configure(struct rte_eth_dev *dev)
 741 {
 742         struct e1000_interrupt *intr =
 743                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 744
 745         PMD_INIT_FUNC_TRACE();
 746         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 747         PMD_INIT_FUNC_TRACE();
 748
 749         return (0);
 750 }
 751
 752 static int
 753 eth_igb_start(struct rte_eth_dev *dev)
 754 {
 755         struct e1000_hw *hw =
 756                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 757         int ret, i, mask;
 758         uint32_t ctrl_ext;
 759
 760         PMD_INIT_FUNC_TRACE();
 761
 762         /* Power up the phy. Needed to make the link go Up */
 763         e1000_power_up_phy(hw);
 764
 765         /*
 766          * Packet Buffer Allocation (PBA)
 767          * Writing PBA sets the receive portion of the buffer
 768          * the remainder is used for the transmit buffer.
 769          */
 770         if (hw->mac.type == e1000_82575) {
 771                 uint32_t pba;
 772
 773                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 774                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 775         }
 776
 777         /* Put the address into the Receive Address Array */
 778         e1000_rar_set(hw, hw->mac.addr, 0);
 779
 780         /* Initialize the hardware */
 781         if (igb_hardware_init(hw)) {
 782                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 783                 return (-EIO);
 784         }
 785
 786         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 787
 788         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 789         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 790         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 791         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 792         E1000_WRITE_FLUSH(hw);
 793
 794         /* configure PF module if SRIOV enabled */
 795         igb_pf_host_configure(dev);
 796
 797         /* Configure for OS presence */
 798         igb_init_manageability(hw);
 799
 800         eth_igb_tx_init(dev);
 801
 802         /* This can fail when allocating mbufs for descriptor rings */
 803         ret = eth_igb_rx_init(dev);
 804         if (ret) {
 805                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 806                 igb_dev_clear_queues(dev);
 807                 return ret;
 808         }
 809
 810         e1000_clear_hw_cntrs_base_generic(hw);
 811
 812         /*
 813          * VLAN Offload Settings
 814          */
 815         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 816                         ETH_VLAN_EXTEND_MASK;
 817         eth_igb_vlan_offload_set(dev, mask);
 818
 819         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 820                 /* Enable VLAN filter since VMDq always use VLAN filter */
 821                 igb_vmdq_vlan_hw_filter_enable(dev);
 822         }
 823
 824         /*
 825          * Configure the Interrupt Moderation register (EITR) with the maximum
 826          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 827          * spurious [DMA] memory updates of RX and TX ring descriptors.
 828          *
 829          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 830          * spurious memory updates per second should be expected.
 831          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 832          *
 833          * Because interrupts are not used at all, the MSI-X is not activated
 834          * and interrupt moderation is controlled by EITR[0].
 835          *
 836          * Note that having [almost] disabled memory updates of RX and TX ring
 837          * descriptors through the Interrupt Moderation mechanism, memory
 838          * updates of ring descriptors are now moderated by the configurable
 839          * value of Write-Back Threshold registers.
 840          */
 841         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 842                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
 843                 (hw->mac.type == e1000_i211)) {
 844                 uint32_t ivar;
 845
 846                 /* Enable all RX & TX queues in the IVAR registers */
 847                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 848                 for (i = 0; i < 8; i++)
 849                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 850
 851                 /* Configure EITR with the maximum possible value (0xFFFF) */
 852                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 853         }
 854
 855         /* Setup link speed and duplex */
 856         switch (dev->data->dev_conf.link_speed) {
 857         case ETH_LINK_SPEED_AUTONEG:
 858                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 859                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 860                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 861                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 862                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 863                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 864                 else
 865                         goto error_invalid_config;
 866                 break;
 867         case ETH_LINK_SPEED_10:
 868                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 869                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 870                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 871                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 872                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 873                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 874                 else
 875                         goto error_invalid_config;
 876                 break;
 877         case ETH_LINK_SPEED_100:
 878                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 879                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 880                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 881                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 882                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 883                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 884                 else
 885                         goto error_invalid_config;
 886                 break;
 887         case ETH_LINK_SPEED_1000:
 888                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 889                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 890                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 891                 else
 892                         goto error_invalid_config;
 893                 break;
 894         case ETH_LINK_SPEED_10000:
 895         default:
 896                 goto error_invalid_config;
 897         }
 898         e1000_setup_link(hw);
 899
 900         /* check if lsc interrupt feature is enabled */
 901         if (dev->data->dev_conf.intr_conf.lsc != 0)
 902                 ret = eth_igb_lsc_interrupt_setup(dev);
 903
 904         /* resume enabled intr since hw reset */
 905         igb_intr_enable(dev);
 906
 907         PMD_INIT_LOG(DEBUG, "<<");
 908
 909         return (0);
 910
 911 error_invalid_config:
 912         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 913                      dev->data->dev_conf.link_speed,
 914                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 915         igb_dev_clear_queues(dev);
 916         return (-EINVAL);
 917 }
 918
 919 /*********************************************************************
 920  *
 921  *  This routine disables all traffic on the adapter by issuing a
 922  *  global reset on the MAC.
 923  *
 924  **********************************************************************/
 925 static void
 926 eth_igb_stop(struct rte_eth_dev *dev)
 927 {
 928         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 929         struct rte_eth_link link;
 930
 931         igb_intr_disable(hw);
 932         igb_pf_reset_hw(hw);
 933         E1000_WRITE_REG(hw, E1000_WUC, 0);
 934
 935         /* Set bit for Go Link disconnect */
 936         if (hw->mac.type >= e1000_82580) {
 937                 uint32_t phpm_reg;
 938
 939                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 940                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 941                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 942         }
 943
 944         /* Power down the phy. Needed to make the link go Down */
 945         e1000_power_down_phy(hw);
 946
 947         igb_dev_clear_queues(dev);
 948
 949         /* clear the recorded link status */
 950         memset(&link, 0, sizeof(link));
 951         rte_igb_dev_atomic_write_link_status(dev, &link);
 952 }
 953
 954 static void
 955 eth_igb_close(struct rte_eth_dev *dev)
 956 {
 957         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 958         struct rte_eth_link link;
 959
 960         eth_igb_stop(dev);
 961         e1000_phy_hw_reset(hw);
 962         igb_release_manageability(hw);
 963         igb_hw_control_release(hw);
 964
 965         /* Clear bit for Go Link disconnect */
 966         if (hw->mac.type >= e1000_82580) {
 967                 uint32_t phpm_reg;
 968
 969                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 970                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 971                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 972         }
 973
 974         igb_dev_clear_queues(dev);
 975
 976         memset(&link, 0, sizeof(link));
 977         rte_igb_dev_atomic_write_link_status(dev, &link);
 978 }
 979
 980 static int
 981 igb_get_rx_buffer_size(struct e1000_hw *hw)
 982 {
 983         uint32_t rx_buf_size;
 984         if (hw->mac.type == e1000_82576) {
 985                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 986         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 987                 /* PBS needs to be translated according to a lookup table */
 988                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 989                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 990                 rx_buf_size = (rx_buf_size << 10);
 991         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
 992                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 993         } else {
 994                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 995         }
 996
 997         return rx_buf_size;
 998 }
 999
1000 /*********************************************************************
1001  *
1002  *  Initialize the hardware
1003  *
1004  **********************************************************************/
1005 static int
1006 igb_hardware_init(struct e1000_hw *hw)
1007 {
1008         uint32_t rx_buf_size;
1009         int diag;
1010
1011         /* Let the firmware know the OS is in control */
1012         igb_hw_control_acquire(hw);
1013
1014         /*
1015          * These parameters control the automatic generation (Tx) and
1016          * response (Rx) to Ethernet PAUSE frames.
1017          * - High water mark should allow for at least two standard size (1518)
1018          *   frames to be received after sending an XOFF.
1019          * - Low water mark works best when it is very near the high water mark.
1020          *   This allows the receiver to restart by sending XON when it has
1021          *   drained a bit. Here we use an arbitrary value of 1500 which will
1022          *   restart after one full frame is pulled from the buffer. There
1023          *   could be several smaller frames in the buffer and if so they will
1024          *   not trigger the XON until their total number reduces the buffer
1025          *   by 1500.
1026          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1027          */
1028         rx_buf_size = igb_get_rx_buffer_size(hw);
1029
1030         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1031         hw->fc.low_water = hw->fc.high_water - 1500;
1032         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1033         hw->fc.send_xon = 1;
1034
1035         /* Set Flow control, use the tunable location if sane */
1036         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1037                 hw->fc.requested_mode = igb_fc_setting;
1038         else
1039                 hw->fc.requested_mode = e1000_fc_none;
1040
1041         /* Issue a global reset */
1042         igb_pf_reset_hw(hw);
1043         E1000_WRITE_REG(hw, E1000_WUC, 0);
1044
1045         diag = e1000_init_hw(hw);
1046         if (diag < 0)
1047                 return (diag);
1048
1049         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1050         e1000_get_phy_info(hw);
1051         e1000_check_for_link(hw);
1052
1053         return (0);
1054 }
1055
1056 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1057 static void
1058 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1059 {
1060         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1061         struct e1000_hw_stats *stats =
1062                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1063         int pause_frames;
1064
1065         if(hw->phy.media_type == e1000_media_type_copper ||
1066             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1067                 stats->symerrs +=
1068                     E1000_READ_REG(hw,E1000_SYMERRS);
1069                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1070         }
1071
1072         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1073         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1074         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1075         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1076
1077         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1078         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1079         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1080         stats->dc += E1000_READ_REG(hw, E1000_DC);
1081         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1082         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1083         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1084         /*
1085         ** For watchdog management we need to know if we have been
1086         ** paused during the last interval, so capture that here.
1087         */
1088         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1089         stats->xoffrxc += pause_frames;
1090         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1091         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1092         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1093         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1094         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1095         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1096         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1097         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1098         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1099         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1100         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1101         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1102
1103         /* For the 64-bit byte counters the low dword must be read first. */
1104         /* Both registers clear on the read of the high dword */
1105
1106         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1107         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1108         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1109         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1110
1111         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1112         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1113         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1114         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1115         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1116
1117         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1118         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1119
1120         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1121         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1122         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1123         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1124         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1125         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1126         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1127         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1128         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1129         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1130
1131         /* Interrupt Counts */
1132
1133         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1134         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1135         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1136         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1137         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1138         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1139         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1140         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1141         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1142
1143         /* Host to Card Statistics */
1144
1145         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1146         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1147         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1148         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1149         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1150         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1151         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1152         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1153         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1154         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1155         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1156         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1157         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1158         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1159
1160         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1161         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1162         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1163         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1164         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1165         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1166
1167         if (rte_stats == NULL)
1168                 return;
1169
1170         /* Rx Errors */
1171         rte_stats->ibadcrc = stats->crcerrs;
1172         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1173         rte_stats->imissed = stats->mpc;
1174         rte_stats->ierrors = rte_stats->ibadcrc +
1175                              rte_stats->ibadlen +
1176                              rte_stats->imissed +
1177                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1178
1179         /* Tx Errors */
1180         rte_stats->oerrors = stats->ecol + stats->latecol;
1181
1182         /* XON/XOFF pause frames */
1183         rte_stats->tx_pause_xon  = stats->xontxc;
1184         rte_stats->rx_pause_xon  = stats->xonrxc;
1185         rte_stats->tx_pause_xoff = stats->xofftxc;
1186         rte_stats->rx_pause_xoff = stats->xoffrxc;
1187
1188         rte_stats->ipackets = stats->gprc;
1189         rte_stats->opackets = stats->gptc;
1190         rte_stats->ibytes   = stats->gorc;
1191         rte_stats->obytes   = stats->gotc;
1192 }
1193
1194 static void
1195 eth_igb_stats_reset(struct rte_eth_dev *dev)
1196 {
1197         struct e1000_hw_stats *hw_stats =
1198                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1199
1200         /* HW registers are cleared on read */
1201         eth_igb_stats_get(dev, NULL);
1202
1203         /* Reset software totals */
1204         memset(hw_stats, 0, sizeof(*hw_stats));
1205 }
1206
1207 static void
1208 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1209 {
1210         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1211         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1212                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1213
1214         /* Good Rx packets, include VF loopback */
1215         UPDATE_VF_STAT(E1000_VFGPRC,
1216             hw_stats->last_gprc, hw_stats->gprc);
1217
1218         /* Good Rx octets, include VF loopback */
1219         UPDATE_VF_STAT(E1000_VFGORC,
1220             hw_stats->last_gorc, hw_stats->gorc);
1221
1222         /* Good Tx packets, include VF loopback */
1223         UPDATE_VF_STAT(E1000_VFGPTC,
1224             hw_stats->last_gptc, hw_stats->gptc);
1225
1226         /* Good Tx octets, include VF loopback */
1227         UPDATE_VF_STAT(E1000_VFGOTC,
1228             hw_stats->last_gotc, hw_stats->gotc);
1229
1230         /* Rx Multicst packets */
1231         UPDATE_VF_STAT(E1000_VFMPRC,
1232             hw_stats->last_mprc, hw_stats->mprc);
1233
1234         /* Good Rx loopback packets */
1235         UPDATE_VF_STAT(E1000_VFGPRLBC,
1236             hw_stats->last_gprlbc, hw_stats->gprlbc);
1237
1238         /* Good Rx loopback octets */
1239         UPDATE_VF_STAT(E1000_VFGORLBC,
1240             hw_stats->last_gorlbc, hw_stats->gorlbc);
1241
1242         /* Good Tx loopback packets */
1243         UPDATE_VF_STAT(E1000_VFGPTLBC,
1244             hw_stats->last_gptlbc, hw_stats->gptlbc);
1245
1246         /* Good Tx loopback octets */
1247         UPDATE_VF_STAT(E1000_VFGOTLBC,
1248             hw_stats->last_gotlbc, hw_stats->gotlbc);
1249
1250         if (rte_stats == NULL)
1251                 return;
1252
1253         rte_stats->ipackets = hw_stats->gprc;
1254         rte_stats->ibytes = hw_stats->gorc;
1255         rte_stats->opackets = hw_stats->gptc;
1256         rte_stats->obytes = hw_stats->gotc;
1257         rte_stats->imcasts = hw_stats->mprc;
1258         rte_stats->ilbpackets = hw_stats->gprlbc;
1259         rte_stats->ilbbytes = hw_stats->gorlbc;
1260         rte_stats->olbpackets = hw_stats->gptlbc;
1261         rte_stats->olbbytes = hw_stats->gotlbc;
1262
1263 }
1264
1265 static void
1266 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1267 {
1268         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1269                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1270
1271         /* Sync HW register to the last stats */
1272         eth_igbvf_stats_get(dev, NULL);
1273
1274         /* reset HW current stats*/
1275         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1276                offsetof(struct e1000_vf_stats, gprc));
1277
1278 }
1279
1280 static void
1281 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1282 {
1283         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1284
1285         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1286         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1287         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1288         dev_info->rx_offload_capa =
1289                 DEV_RX_OFFLOAD_VLAN_STRIP |
1290                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1291                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1292                 DEV_RX_OFFLOAD_TCP_CKSUM;
1293         dev_info->tx_offload_capa =
1294                 DEV_TX_OFFLOAD_VLAN_INSERT |
1295                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1296                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1297                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1298                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1299
1300         switch (hw->mac.type) {
1301         case e1000_82575:
1302                 dev_info->max_rx_queues = 4;
1303                 dev_info->max_tx_queues = 4;
1304                 dev_info->max_vmdq_pools = 0;
1305                 break;
1306
1307         case e1000_82576:
1308                 dev_info->max_rx_queues = 16;
1309                 dev_info->max_tx_queues = 16;
1310                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1311                 dev_info->vmdq_queue_num = 16;
1312                 break;
1313
1314         case e1000_82580:
1315                 dev_info->max_rx_queues = 8;
1316                 dev_info->max_tx_queues = 8;
1317                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1318                 dev_info->vmdq_queue_num = 8;
1319                 break;
1320
1321         case e1000_i350:
1322                 dev_info->max_rx_queues = 8;
1323                 dev_info->max_tx_queues = 8;
1324                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1325                 dev_info->vmdq_queue_num = 8;
1326                 break;
1327
1328         case e1000_i354:
1329                 dev_info->max_rx_queues = 8;
1330                 dev_info->max_tx_queues = 8;
1331                 break;
1332
1333         case e1000_i210:
1334                 dev_info->max_rx_queues = 4;
1335                 dev_info->max_tx_queues = 4;
1336                 dev_info->max_vmdq_pools = 0;
1337                 break;
1338
1339         case e1000_i211:
1340                 dev_info->max_rx_queues = 2;
1341                 dev_info->max_tx_queues = 2;
1342                 dev_info->max_vmdq_pools = 0;
1343                 break;
1344
1345         default:
1346                 /* Should not happen */
1347                 break;
1348         }
1349         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1350
1351         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1352                 .rx_thresh = {
1353                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1354                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1355                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1356                 },
1357                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1358                 .rx_drop_en = 0,
1359         };
1360
1361         dev_info->default_txconf = (struct rte_eth_txconf) {
1362                 .tx_thresh = {
1363                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1364                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1365                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1366                 },
1367                 .txq_flags = 0,
1368         };
1369 }
1370
1371 static void
1372 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1373 {
1374         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1375
1376         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1377         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1378         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1379         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1380                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1381                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1382                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1383         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1384                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1385                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1386                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1387                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1388         switch (hw->mac.type) {
1389         case e1000_vfadapt:
1390                 dev_info->max_rx_queues = 2;
1391                 dev_info->max_tx_queues = 2;
1392                 break;
1393         case e1000_vfadapt_i350:
1394                 dev_info->max_rx_queues = 1;
1395                 dev_info->max_tx_queues = 1;
1396                 break;
1397         default:
1398                 /* Should not happen */
1399                 break;
1400         }
1401
1402         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1403                 .rx_thresh = {
1404                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1405                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1406                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1407                 },
1408                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1409                 .rx_drop_en = 0,
1410         };
1411
1412         dev_info->default_txconf = (struct rte_eth_txconf) {
1413                 .tx_thresh = {
1414                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1415                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1416                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1417                 },
1418                 .txq_flags = 0,
1419         };
1420 }
1421
1422 /* return 0 means link status changed, -1 means not changed */
1423 static int
1424 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1425 {
1426         struct e1000_hw *hw =
1427                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428         struct rte_eth_link link, old;
1429         int link_check, count;
1430
1431         link_check = 0;
1432         hw->mac.get_link_status = 1;
1433
1434         /* possible wait-to-complete in up to 9 seconds */
1435         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1436                 /* Read the real link status */
1437                 switch (hw->phy.media_type) {
1438                 case e1000_media_type_copper:
1439                         /* Do the work to read phy */
1440                         e1000_check_for_link(hw);
1441                         link_check = !hw->mac.get_link_status;
1442                         break;
1443
1444                 case e1000_media_type_fiber:
1445                         e1000_check_for_link(hw);
1446                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1447                                       E1000_STATUS_LU);
1448                         break;
1449
1450                 case e1000_media_type_internal_serdes:
1451                         e1000_check_for_link(hw);
1452                         link_check = hw->mac.serdes_has_link;
1453                         break;
1454
1455                 /* VF device is type_unknown */
1456                 case e1000_media_type_unknown:
1457                         eth_igbvf_link_update(hw);
1458                         link_check = !hw->mac.get_link_status;
1459                         break;
1460
1461                 default:
1462                         break;
1463                 }
1464                 if (link_check || wait_to_complete == 0)
1465                         break;
1466                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1467         }
1468         memset(&link, 0, sizeof(link));
1469         rte_igb_dev_atomic_read_link_status(dev, &link);
1470         old = link;
1471
1472         /* Now we check if a transition has happened */
1473         if (link_check) {
1474                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1475                                           &link.link_duplex);
1476                 link.link_status = 1;
1477         } else if (!link_check) {
1478                 link.link_speed = 0;
1479                 link.link_duplex = 0;
1480                 link.link_status = 0;
1481         }
1482         rte_igb_dev_atomic_write_link_status(dev, &link);
1483
1484         /* not changed */
1485         if (old.link_status == link.link_status)
1486                 return -1;
1487
1488         /* changed */
1489         return 0;
1490 }
1491
1492 /*
1493  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1494  * For ASF and Pass Through versions of f/w this means
1495  * that the driver is loaded.
1496  */
1497 static void
1498 igb_hw_control_acquire(struct e1000_hw *hw)
1499 {
1500         uint32_t ctrl_ext;
1501
1502         /* Let firmware know the driver has taken over */
1503         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1504         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1505 }
1506
1507 /*
1508  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1509  * For ASF and Pass Through versions of f/w this means that the
1510  * driver is no longer loaded.
1511  */
1512 static void
1513 igb_hw_control_release(struct e1000_hw *hw)
1514 {
1515         uint32_t ctrl_ext;
1516
1517         /* Let firmware taken over control of h/w */
1518         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1519         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1520                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1521 }
1522
1523 /*
1524  * Bit of a misnomer, what this really means is
1525  * to enable OS management of the system... aka
1526  * to disable special hardware management features.
1527  */
1528 static void
1529 igb_init_manageability(struct e1000_hw *hw)
1530 {
1531         if (e1000_enable_mng_pass_thru(hw)) {
1532                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1533                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1534
1535                 /* disable hardware interception of ARP */
1536                 manc &= ~(E1000_MANC_ARP_EN);
1537
1538                 /* enable receiving management packets to the host */
1539                 manc |= E1000_MANC_EN_MNG2HOST;
1540                 manc2h |= 1 << 5;  /* Mng Port 623 */
1541                 manc2h |= 1 << 6;  /* Mng Port 664 */
1542                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1543                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1544         }
1545 }
1546
1547 static void
1548 igb_release_manageability(struct e1000_hw *hw)
1549 {
1550         if (e1000_enable_mng_pass_thru(hw)) {
1551                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1552
1553                 manc |= E1000_MANC_ARP_EN;
1554                 manc &= ~E1000_MANC_EN_MNG2HOST;
1555
1556                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1557         }
1558 }
1559
1560 static void
1561 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1562 {
1563         struct e1000_hw *hw =
1564                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1565         uint32_t rctl;
1566
1567         rctl = E1000_READ_REG(hw, E1000_RCTL);
1568         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1569         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1570 }
1571
1572 static void
1573 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1574 {
1575         struct e1000_hw *hw =
1576                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1577         uint32_t rctl;
1578
1579         rctl = E1000_READ_REG(hw, E1000_RCTL);
1580         rctl &= (~E1000_RCTL_UPE);
1581         if (dev->data->all_multicast == 1)
1582                 rctl |= E1000_RCTL_MPE;
1583         else
1584                 rctl &= (~E1000_RCTL_MPE);
1585         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1586 }
1587
1588 static void
1589 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1590 {
1591         struct e1000_hw *hw =
1592                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1593         uint32_t rctl;
1594
1595         rctl = E1000_READ_REG(hw, E1000_RCTL);
1596         rctl |= E1000_RCTL_MPE;
1597         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1598 }
1599
1600 static void
1601 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1602 {
1603         struct e1000_hw *hw =
1604                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1605         uint32_t rctl;
1606
1607         if (dev->data->promiscuous == 1)
1608                 return; /* must remain in all_multicast mode */
1609         rctl = E1000_READ_REG(hw, E1000_RCTL);
1610         rctl &= (~E1000_RCTL_MPE);
1611         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1612 }
1613
1614 static int
1615 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1616 {
1617         struct e1000_hw *hw =
1618                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1619         struct e1000_vfta * shadow_vfta =
1620                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1621         uint32_t vfta;
1622         uint32_t vid_idx;
1623         uint32_t vid_bit;
1624
1625         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1626                               E1000_VFTA_ENTRY_MASK);
1627         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1628         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1629         if (on)
1630                 vfta |= vid_bit;
1631         else
1632                 vfta &= ~vid_bit;
1633         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1634
1635         /* update local VFTA copy */
1636         shadow_vfta->vfta[vid_idx] = vfta;
1637
1638         return 0;
1639 }
1640
1641 static void
1642 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1643 {
1644         struct e1000_hw *hw =
1645                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646         uint32_t reg = ETHER_TYPE_VLAN ;
1647
1648         reg |= (tpid << 16);
1649         E1000_WRITE_REG(hw, E1000_VET, reg);
1650 }
1651
1652 static void
1653 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1654 {
1655         struct e1000_hw *hw =
1656                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657         uint32_t reg;
1658
1659         /* Filter Table Disable */
1660         reg = E1000_READ_REG(hw, E1000_RCTL);
1661         reg &= ~E1000_RCTL_CFIEN;
1662         reg &= ~E1000_RCTL_VFE;
1663         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1664 }
1665
1666 static void
1667 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1668 {
1669         struct e1000_hw *hw =
1670                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1671         struct e1000_vfta * shadow_vfta =
1672                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1673         uint32_t reg;
1674         int i;
1675
1676         /* Filter Table Enable, CFI not used for packet acceptance */
1677         reg = E1000_READ_REG(hw, E1000_RCTL);
1678         reg &= ~E1000_RCTL_CFIEN;
1679         reg |= E1000_RCTL_VFE;
1680         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1681
1682         /* restore VFTA table */
1683         for (i = 0; i < IGB_VFTA_SIZE; i++)
1684                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1685 }
1686
1687 static void
1688 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1689 {
1690         struct e1000_hw *hw =
1691                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1692         uint32_t reg;
1693
1694         /* VLAN Mode Disable */
1695         reg = E1000_READ_REG(hw, E1000_CTRL);
1696         reg &= ~E1000_CTRL_VME;
1697         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1698 }
1699
1700 static void
1701 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1702 {
1703         struct e1000_hw *hw =
1704                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1705         uint32_t reg;
1706
1707         /* VLAN Mode Enable */
1708         reg = E1000_READ_REG(hw, E1000_CTRL);
1709         reg |= E1000_CTRL_VME;
1710         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1711 }
1712
1713 static void
1714 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1715 {
1716         struct e1000_hw *hw =
1717                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1718         uint32_t reg;
1719
1720         /* CTRL_EXT: Extended VLAN */
1721         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1722         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1723         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1724
1725         /* Update maximum packet length */
1726         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1727                 E1000_WRITE_REG(hw, E1000_RLPML,
1728                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1729                                                 VLAN_TAG_SIZE);
1730 }
1731
1732 static void
1733 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1734 {
1735         struct e1000_hw *hw =
1736                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737         uint32_t reg;
1738
1739         /* CTRL_EXT: Extended VLAN */
1740         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1741         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1742         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1743
1744         /* Update maximum packet length */
1745         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1746                 E1000_WRITE_REG(hw, E1000_RLPML,
1747                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1748                                                 2 * VLAN_TAG_SIZE);
1749 }
1750
1751 static void
1752 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1753 {
1754         if(mask & ETH_VLAN_STRIP_MASK){
1755                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1756                         igb_vlan_hw_strip_enable(dev);
1757                 else
1758                         igb_vlan_hw_strip_disable(dev);
1759         }
1760
1761         if(mask & ETH_VLAN_FILTER_MASK){
1762                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1763                         igb_vlan_hw_filter_enable(dev);
1764                 else
1765                         igb_vlan_hw_filter_disable(dev);
1766         }
1767
1768         if(mask & ETH_VLAN_EXTEND_MASK){
1769                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1770                         igb_vlan_hw_extend_enable(dev);
1771                 else
1772                         igb_vlan_hw_extend_disable(dev);
1773         }
1774 }
1775
1776
1777 /**
1778  * It enables the interrupt mask and then enable the interrupt.
1779  *
1780  * @param dev
1781  *  Pointer to struct rte_eth_dev.
1782  *
1783  * @return
1784  *  - On success, zero.
1785  *  - On failure, a negative value.
1786  */
1787 static int
1788 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1789 {
1790         struct e1000_interrupt *intr =
1791                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1792
1793         intr->mask |= E1000_ICR_LSC;
1794
1795         return 0;
1796 }
1797
1798 /*
1799  * It reads ICR and gets interrupt causes, check it and set a bit flag
1800  * to update link status.
1801  *
1802  * @param dev
1803  *  Pointer to struct rte_eth_dev.
1804  *
1805  * @return
1806  *  - On success, zero.
1807  *  - On failure, a negative value.
1808  */
1809 static int
1810 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1811 {
1812         uint32_t icr;
1813         struct e1000_hw *hw =
1814                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1815         struct e1000_interrupt *intr =
1816                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1817
1818         igb_intr_disable(hw);
1819
1820         /* read-on-clear nic registers here */
1821         icr = E1000_READ_REG(hw, E1000_ICR);
1822
1823         intr->flags = 0;
1824         if (icr & E1000_ICR_LSC) {
1825                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1826         }
1827
1828         if (icr & E1000_ICR_VMMB)
1829                 intr->flags |= E1000_FLAG_MAILBOX;
1830
1831         return 0;
1832 }
1833
1834 /*
1835  * It executes link_update after knowing an interrupt is prsent.
1836  *
1837  * @param dev
1838  *  Pointer to struct rte_eth_dev.
1839  *
1840  * @return
1841  *  - On success, zero.
1842  *  - On failure, a negative value.
1843  */
1844 static int
1845 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1846 {
1847         struct e1000_hw *hw =
1848                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1849         struct e1000_interrupt *intr =
1850                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1851         uint32_t tctl, rctl;
1852         struct rte_eth_link link;
1853         int ret;
1854
1855         if (intr->flags & E1000_FLAG_MAILBOX) {
1856                 igb_pf_mbx_process(dev);
1857                 intr->flags &= ~E1000_FLAG_MAILBOX;
1858         }
1859
1860         igb_intr_enable(dev);
1861         rte_intr_enable(&(dev->pci_dev->intr_handle));
1862
1863         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1864                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1865
1866                 /* set get_link_status to check register later */
1867                 hw->mac.get_link_status = 1;
1868                 ret = eth_igb_link_update(dev, 0);
1869
1870                 /* check if link has changed */
1871                 if (ret < 0)
1872                         return 0;
1873
1874                 memset(&link, 0, sizeof(link));
1875                 rte_igb_dev_atomic_read_link_status(dev, &link);
1876                 if (link.link_status) {
1877                         PMD_INIT_LOG(INFO,
1878                                      " Port %d: Link Up - speed %u Mbps - %s",
1879                                      dev->data->port_id,
1880                                      (unsigned)link.link_speed,
1881                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1882                                      "full-duplex" : "half-duplex");
1883                 } else {
1884                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
1885                                      dev->data->port_id);
1886                 }
1887                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1888                              dev->pci_dev->addr.domain,
1889                              dev->pci_dev->addr.bus,
1890                              dev->pci_dev->addr.devid,
1891                              dev->pci_dev->addr.function);
1892                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1893                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1894                 if (link.link_status) {
1895                         /* enable Tx/Rx */
1896                         tctl |= E1000_TCTL_EN;
1897                         rctl |= E1000_RCTL_EN;
1898                 } else {
1899                         /* disable Tx/Rx */
1900                         tctl &= ~E1000_TCTL_EN;
1901                         rctl &= ~E1000_RCTL_EN;
1902                 }
1903                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1904                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1905                 E1000_WRITE_FLUSH(hw);
1906                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1907         }
1908
1909         return 0;
1910 }
1911
1912 /**
1913  * Interrupt handler which shall be registered at first.
1914  *
1915  * @param handle
1916  *  Pointer to interrupt handle.
1917  * @param param
1918  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1919  *
1920  * @return
1921  *  void
1922  */
1923 static void
1924 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1925                                                         void *param)
1926 {
1927         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1928
1929         eth_igb_interrupt_get_status(dev);
1930         eth_igb_interrupt_action(dev);
1931 }
1932
1933 static int
1934 eth_igb_led_on(struct rte_eth_dev *dev)
1935 {
1936         struct e1000_hw *hw;
1937
1938         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1940 }
1941
1942 static int
1943 eth_igb_led_off(struct rte_eth_dev *dev)
1944 {
1945         struct e1000_hw *hw;
1946
1947         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1949 }
1950
1951 static int
1952 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1953 {
1954         struct e1000_hw *hw;
1955         uint32_t ctrl;
1956         int tx_pause;
1957         int rx_pause;
1958
1959         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1960         fc_conf->pause_time = hw->fc.pause_time;
1961         fc_conf->high_water = hw->fc.high_water;
1962         fc_conf->low_water = hw->fc.low_water;
1963         fc_conf->send_xon = hw->fc.send_xon;
1964         fc_conf->autoneg = hw->mac.autoneg;
1965
1966         /*
1967          * Return rx_pause and tx_pause status according to actual setting of
1968          * the TFCE and RFCE bits in the CTRL register.
1969          */
1970         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1971         if (ctrl & E1000_CTRL_TFCE)
1972                 tx_pause = 1;
1973         else
1974                 tx_pause = 0;
1975
1976         if (ctrl & E1000_CTRL_RFCE)
1977                 rx_pause = 1;
1978         else
1979                 rx_pause = 0;
1980
1981         if (rx_pause && tx_pause)
1982                 fc_conf->mode = RTE_FC_FULL;
1983         else if (rx_pause)
1984                 fc_conf->mode = RTE_FC_RX_PAUSE;
1985         else if (tx_pause)
1986                 fc_conf->mode = RTE_FC_TX_PAUSE;
1987         else
1988                 fc_conf->mode = RTE_FC_NONE;
1989
1990         return 0;
1991 }
1992
1993 static int
1994 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1995 {
1996         struct e1000_hw *hw;
1997         int err;
1998         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1999                 e1000_fc_none,
2000                 e1000_fc_rx_pause,
2001                 e1000_fc_tx_pause,
2002                 e1000_fc_full
2003         };
2004         uint32_t rx_buf_size;
2005         uint32_t max_high_water;
2006         uint32_t rctl;
2007
2008         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2009         if (fc_conf->autoneg != hw->mac.autoneg)
2010                 return -ENOTSUP;
2011         rx_buf_size = igb_get_rx_buffer_size(hw);
2012         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2013
2014         /* At least reserve one Ethernet frame for watermark */
2015         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2016         if ((fc_conf->high_water > max_high_water) ||
2017             (fc_conf->high_water < fc_conf->low_water)) {
2018                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2019                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2020                 return (-EINVAL);
2021         }
2022
2023         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2024         hw->fc.pause_time     = fc_conf->pause_time;
2025         hw->fc.high_water     = fc_conf->high_water;
2026         hw->fc.low_water      = fc_conf->low_water;
2027         hw->fc.send_xon       = fc_conf->send_xon;
2028
2029         err = e1000_setup_link_generic(hw);
2030         if (err == E1000_SUCCESS) {
2031
2032                 /* check if we want to forward MAC frames - driver doesn't have native
2033                  * capability to do that, so we'll write the registers ourselves */
2034
2035                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2036
2037                 /* set or clear MFLCN.PMCF bit depending on configuration */
2038                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2039                         rctl |= E1000_RCTL_PMCF;
2040                 else
2041                         rctl &= ~E1000_RCTL_PMCF;
2042
2043                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2044                 E1000_WRITE_FLUSH(hw);
2045
2046                 return 0;
2047         }
2048
2049         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2050         return (-EIO);
2051 }
2052
2053 #define E1000_RAH_POOLSEL_SHIFT      (18)
2054 static void
2055 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2056                 uint32_t index, __rte_unused uint32_t pool)
2057 {
2058         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2059         uint32_t rah;
2060
2061         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2062         rah = E1000_READ_REG(hw, E1000_RAH(index));
2063         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2064         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2065 }
2066
2067 static void
2068 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2069 {
2070         uint8_t addr[ETHER_ADDR_LEN];
2071         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2072
2073         memset(addr, 0, sizeof(addr));
2074
2075         e1000_rar_set(hw, addr, index);
2076 }
2077
2078 /*
2079  * Virtual Function operations
2080  */
2081 static void
2082 igbvf_intr_disable(struct e1000_hw *hw)
2083 {
2084         PMD_INIT_FUNC_TRACE();
2085
2086         /* Clear interrupt mask to stop from interrupts being generated */
2087         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2088
2089         E1000_WRITE_FLUSH(hw);
2090 }
2091
2092 static void
2093 igbvf_stop_adapter(struct rte_eth_dev *dev)
2094 {
2095         u32 reg_val;
2096         u16 i;
2097         struct rte_eth_dev_info dev_info;
2098         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099
2100         memset(&dev_info, 0, sizeof(dev_info));
2101         eth_igbvf_infos_get(dev, &dev_info);
2102
2103         /* Clear interrupt mask to stop from interrupts being generated */
2104         igbvf_intr_disable(hw);
2105
2106         /* Clear any pending interrupts, flush previous writes */
2107         E1000_READ_REG(hw, E1000_EICR);
2108
2109         /* Disable the transmit unit.  Each queue must be disabled. */
2110         for (i = 0; i < dev_info.max_tx_queues; i++)
2111                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2112
2113         /* Disable the receive unit by stopping each queue */
2114         for (i = 0; i < dev_info.max_rx_queues; i++) {
2115                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2116                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2117                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2118                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2119                         ;
2120         }
2121
2122         /* flush all queues disables */
2123         E1000_WRITE_FLUSH(hw);
2124         msec_delay(2);
2125 }
2126
2127 static int eth_igbvf_link_update(struct e1000_hw *hw)
2128 {
2129         struct e1000_mbx_info *mbx = &hw->mbx;
2130         struct e1000_mac_info *mac = &hw->mac;
2131         int ret_val = E1000_SUCCESS;
2132
2133         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2134
2135         /*
2136          * We only want to run this if there has been a rst asserted.
2137          * in this case that could mean a link change, device reset,
2138          * or a virtual function reset
2139          */
2140
2141         /* If we were hit with a reset or timeout drop the link */
2142         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2143                 mac->get_link_status = TRUE;
2144
2145         if (!mac->get_link_status)
2146                 goto out;
2147
2148         /* if link status is down no point in checking to see if pf is up */
2149         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2150                 goto out;
2151
2152         /* if we passed all the tests above then the link is up and we no
2153          * longer need to check for link */
2154         mac->get_link_status = FALSE;
2155
2156 out:
2157         return ret_val;
2158 }
2159
2160
2161 static int
2162 igbvf_dev_configure(struct rte_eth_dev *dev)
2163 {
2164         struct rte_eth_conf* conf = &dev->data->dev_conf;
2165
2166         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2167                      dev->data->port_id);
2168
2169         /*
2170          * VF has no ability to enable/disable HW CRC
2171          * Keep the persistent behavior the same as Host PF
2172          */
2173 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2174         if (!conf->rxmode.hw_strip_crc) {
2175                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2176                 conf->rxmode.hw_strip_crc = 1;
2177         }
2178 #else
2179         if (conf->rxmode.hw_strip_crc) {
2180                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2181                 conf->rxmode.hw_strip_crc = 0;
2182         }
2183 #endif
2184
2185         return 0;
2186 }
2187
2188 static int
2189 igbvf_dev_start(struct rte_eth_dev *dev)
2190 {
2191         struct e1000_hw *hw =
2192                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193         int ret;
2194
2195         PMD_INIT_FUNC_TRACE();
2196
2197         hw->mac.ops.reset_hw(hw);
2198
2199         /* Set all vfta */
2200         igbvf_set_vfta_all(dev,1);
2201
2202         eth_igbvf_tx_init(dev);
2203
2204         /* This can fail when allocating mbufs for descriptor rings */
2205         ret = eth_igbvf_rx_init(dev);
2206         if (ret) {
2207                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2208                 igb_dev_clear_queues(dev);
2209                 return ret;
2210         }
2211
2212         return 0;
2213 }
2214
2215 static void
2216 igbvf_dev_stop(struct rte_eth_dev *dev)
2217 {
2218         PMD_INIT_FUNC_TRACE();
2219
2220         igbvf_stop_adapter(dev);
2221
2222         /*
2223           * Clear what we set, but we still keep shadow_vfta to
2224           * restore after device starts
2225           */
2226         igbvf_set_vfta_all(dev,0);
2227
2228         igb_dev_clear_queues(dev);
2229 }
2230
2231 static void
2232 igbvf_dev_close(struct rte_eth_dev *dev)
2233 {
2234         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2235
2236         PMD_INIT_FUNC_TRACE();
2237
2238         e1000_reset_hw(hw);
2239
2240         igbvf_dev_stop(dev);
2241 }
2242
2243 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2244 {
2245         struct e1000_mbx_info *mbx = &hw->mbx;
2246         uint32_t msgbuf[2];
2247
2248         /* After set vlan, vlan strip will also be enabled in igb driver*/
2249         msgbuf[0] = E1000_VF_SET_VLAN;
2250         msgbuf[1] = vid;
2251         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2252         if (on)
2253                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2254
2255         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2256 }
2257
2258 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2259 {
2260         struct e1000_hw *hw =
2261                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262         struct e1000_vfta * shadow_vfta =
2263                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2264         int i = 0, j = 0, vfta = 0, mask = 1;
2265
2266         for (i = 0; i < IGB_VFTA_SIZE; i++){
2267                 vfta = shadow_vfta->vfta[i];
2268                 if(vfta){
2269                         mask = 1;
2270                         for (j = 0; j < 32; j++){
2271                                 if(vfta & mask)
2272                                         igbvf_set_vfta(hw,
2273                                                 (uint16_t)((i<<5)+j), on);
2274                                 mask<<=1;
2275                         }
2276                 }
2277         }
2278
2279 }
2280
2281 static int
2282 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2283 {
2284         struct e1000_hw *hw =
2285                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2286         struct e1000_vfta * shadow_vfta =
2287                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2288         uint32_t vid_idx = 0;
2289         uint32_t vid_bit = 0;
2290         int ret = 0;
2291
2292         PMD_INIT_FUNC_TRACE();
2293
2294         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2295         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2296         if(ret){
2297                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2298                 return ret;
2299         }
2300         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2301         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2302
2303         /*Save what we set and retore it after device reset*/
2304         if (on)
2305                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2306         else
2307                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2308
2309         return 0;
2310 }
2311
2312 static int
2313 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2314                         struct rte_eth_rss_reta_entry64 *reta_conf,
2315                         uint16_t reta_size)
2316 {
2317         uint8_t i, j, mask;
2318         uint32_t reta, r;
2319         uint16_t idx, shift;
2320         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2321
2322         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2323                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2324                         "(%d) doesn't match the number hardware can supported "
2325                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2326                 return -EINVAL;
2327         }
2328
2329         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2330                 idx = i / RTE_RETA_GROUP_SIZE;
2331                 shift = i % RTE_RETA_GROUP_SIZE;
2332                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2333                                                 IGB_4_BIT_MASK);
2334                 if (!mask)
2335                         continue;
2336                 if (mask == IGB_4_BIT_MASK)
2337                         r = 0;
2338                 else
2339                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2340                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2341                         if (mask & (0x1 << j))
2342                                 reta |= reta_conf[idx].reta[shift + j] <<
2343                                                         (CHAR_BIT * j);
2344                         else
2345                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2346                 }
2347                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2348         }
2349
2350         return 0;
2351 }
2352
2353 static int
2354 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2355                        struct rte_eth_rss_reta_entry64 *reta_conf,
2356                        uint16_t reta_size)
2357 {
2358         uint8_t i, j, mask;
2359         uint32_t reta;
2360         uint16_t idx, shift;
2361         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2362
2363         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2364                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2365                         "(%d) doesn't match the number hardware can supported "
2366                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2367                 return -EINVAL;
2368         }
2369
2370         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2371                 idx = i / RTE_RETA_GROUP_SIZE;
2372                 shift = i % RTE_RETA_GROUP_SIZE;
2373                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2374                                                 IGB_4_BIT_MASK);
2375                 if (!mask)
2376                         continue;
2377                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2378                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2379                         if (mask & (0x1 << j))
2380                                 reta_conf[idx].reta[shift + j] =
2381                                         ((reta >> (CHAR_BIT * j)) &
2382                                                 IGB_8_BIT_MASK);
2383                 }
2384         }
2385
2386         return 0;
2387 }
2388
2389 #define MAC_TYPE_FILTER_SUP(type)    do {\
2390         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2391                 (type) != e1000_82576)\
2392                 return -ENOTSUP;\
2393 } while (0)
2394
2395 /*
2396  * add the syn filter
2397  *
2398  * @param
2399  * dev: Pointer to struct rte_eth_dev.
2400  * filter: ponter to the filter that will be added.
2401  * rx_queue: the queue id the filter assigned to.
2402  *
2403  * @return
2404  *    - On success, zero.
2405  *    - On failure, a negative value.
2406  */
2407 static int
2408 eth_igb_add_syn_filter(struct rte_eth_dev *dev,
2409                         struct rte_syn_filter *filter, uint16_t rx_queue)
2410 {
2411         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412         uint32_t synqf, rfctl;
2413
2414         MAC_TYPE_FILTER_SUP(hw->mac.type);
2415
2416         if (rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2417                 return -EINVAL;
2418
2419         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2420         if (synqf & E1000_SYN_FILTER_ENABLE)
2421                 return -EINVAL;
2422
2423         synqf = (uint32_t)(((rx_queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2424                 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2425
2426         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2427         if (filter->hig_pri)
2428                 rfctl |= E1000_RFCTL_SYNQFP;
2429         else
2430                 rfctl &= ~E1000_RFCTL_SYNQFP;
2431
2432         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2433         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2434         return 0;
2435 }
2436
2437 /*
2438  * remove the syn filter
2439  *
2440  * @param
2441  * dev: Pointer to struct rte_eth_dev.
2442  *
2443  * @return
2444  *    - On success, zero.
2445  *    - On failure, a negative value.
2446  */
2447 static int
2448 eth_igb_remove_syn_filter(struct rte_eth_dev *dev)
2449 {
2450         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2451
2452         MAC_TYPE_FILTER_SUP(hw->mac.type);
2453
2454         E1000_WRITE_REG(hw, E1000_SYNQF(0), 0);
2455         return 0;
2456 }
2457
2458 /*
2459  * get the syn filter's info
2460  *
2461  * @param
2462  * dev: Pointer to struct rte_eth_dev.
2463  * filter: ponter to the filter that returns.
2464  * *rx_queue: pointer to the queue id the filter assigned to.
2465  *
2466  * @return
2467  *    - On success, zero.
2468  *    - On failure, a negative value.
2469  */
2470 static int
2471 eth_igb_get_syn_filter(struct rte_eth_dev *dev,
2472                         struct rte_syn_filter *filter, uint16_t *rx_queue)
2473 {
2474         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475         uint32_t synqf, rfctl;
2476
2477         MAC_TYPE_FILTER_SUP(hw->mac.type);
2478         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2479         if (synqf & E1000_SYN_FILTER_ENABLE) {
2480                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2481                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2482                 *rx_queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2483                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2484                 return 0;
2485         }
2486         return -ENOENT;
2487 }
2488
2489 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2490         if ((type) != e1000_82580 && (type) != e1000_i350)\
2491                 return -ENOSYS; \
2492 } while (0)
2493
2494 /*
2495  * add a 2tuple filter
2496  *
2497  * @param
2498  * dev: Pointer to struct rte_eth_dev.
2499  * index: the index the filter allocates.
2500  * filter: ponter to the filter that will be added.
2501  * rx_queue: the queue id the filter assigned to.
2502  *
2503  * @return
2504  *    - On success, zero.
2505  *    - On failure, a negative value.
2506  */
2507 static int
2508 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2509                         struct rte_2tuple_filter *filter, uint16_t rx_queue)
2510 {
2511         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2512         uint32_t ttqf, imir = 0;
2513         uint32_t imir_ext = 0;
2514
2515         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2516
2517         if (index >= E1000_MAX_TTQF_FILTERS ||
2518                 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2519                 filter->priority > E1000_2TUPLE_MAX_PRI)
2520                 return -EINVAL;  /* filter index is out of range. */
2521         if  (filter->tcp_flags > TCP_FLAG_ALL)
2522                 return -EINVAL;  /* flags is invalid. */
2523
2524         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2525         if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2526                 return -EINVAL;  /* filter index is in use. */
2527
2528         imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2529         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2530                 imir |= E1000_IMIR_PORT_BP;
2531         else
2532                 imir &= ~E1000_IMIR_PORT_BP;
2533
2534         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2535
2536         ttqf = 0;
2537         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2538         ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2539         ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2540         if (filter->protocol_mask == 1)
2541                 ttqf |= E1000_TTQF_MASK_ENABLE;
2542         else
2543                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2544
2545         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2546         /* tcp flags bits setting. */
2547         if (filter->tcp_flags & TCP_FLAG_ALL) {
2548                 if (filter->tcp_flags & TCP_UGR_FLAG)
2549                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2550                 if (filter->tcp_flags & TCP_ACK_FLAG)
2551                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2552                 if (filter->tcp_flags & TCP_PSH_FLAG)
2553                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2554                 if (filter->tcp_flags & TCP_RST_FLAG)
2555                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2556                 if (filter->tcp_flags & TCP_SYN_FLAG)
2557                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2558                 if (filter->tcp_flags & TCP_FIN_FLAG)
2559                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2560                 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2561         } else
2562                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2563         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2564         E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2565         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2566         return 0;
2567 }
2568
2569 /*
2570  * remove a 2tuple filter
2571  *
2572  * @param
2573  * dev: Pointer to struct rte_eth_dev.
2574  * index: the index the filter allocates.
2575  *
2576  * @return
2577  *    - On success, zero.
2578  *    - On failure, a negative value.
2579  */
2580 static int
2581 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2582                         uint16_t index)
2583 {
2584         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585
2586         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2587
2588         if (index >= E1000_MAX_TTQF_FILTERS)
2589                 return -EINVAL;  /* filter index is out of range */
2590
2591         E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2592         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2593         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2594         return 0;
2595 }
2596
2597 /*
2598  * get a 2tuple filter
2599  *
2600  * @param
2601  * dev: Pointer to struct rte_eth_dev.
2602  * index: the index the filter allocates.
2603  * filter: ponter to the filter that returns.
2604  * *rx_queue: pointer of the queue id the filter assigned to.
2605  *
2606  * @return
2607  *    - On success, zero.
2608  *    - On failure, a negative value.
2609  */
2610 static int
2611 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2612                         struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2613 {
2614         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615         uint32_t imir, ttqf, imir_ext;
2616
2617         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2618
2619         if (index >= E1000_MAX_TTQF_FILTERS)
2620                 return -EINVAL;  /* filter index is out of range. */
2621
2622         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2623         if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2624                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2625                 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2626                 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2627                 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2628                                 E1000_TTQF_QUEUE_SHIFT;
2629                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2630                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2631                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2632                         E1000_IMIR_PRIORITY_SHIFT;
2633
2634                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2635                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2636                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2637                                 filter->tcp_flags |= TCP_UGR_FLAG;
2638                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2639                                 filter->tcp_flags |= TCP_ACK_FLAG;
2640                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2641                                 filter->tcp_flags |= TCP_PSH_FLAG;
2642                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2643                                 filter->tcp_flags |= TCP_RST_FLAG;
2644                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2645                                 filter->tcp_flags |= TCP_SYN_FLAG;
2646                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2647                                 filter->tcp_flags |= TCP_FIN_FLAG;
2648                 } else
2649                         filter->tcp_flags = 0;
2650                 return 0;
2651         }
2652         return -ENOENT;
2653 }
2654
2655 /*
2656  * add a flex filter
2657  *
2658  * @param
2659  * dev: Pointer to struct rte_eth_dev.
2660  * index: the index the filter allocates.
2661  * filter: ponter to the filter that will be added.
2662  * rx_queue: the queue id the filter assigned to.
2663  *
2664  * @return
2665  *    - On success, zero.
2666  *     - On failure, a negative value.
2667  */
2668 static int
2669 eth_igb_add_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2670                         struct rte_flex_filter *filter, uint16_t rx_queue)
2671 {
2672         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2673         uint32_t wufc, en_bits = 0;
2674         uint32_t queueing = 0;
2675         uint32_t reg_off = 0;
2676         uint8_t i, j = 0;
2677
2678         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2679
2680         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2681                 return -EINVAL;  /* filter index is out of range. */
2682
2683         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN ||
2684                 filter->len % 8 != 0 ||
2685                 filter->priority > E1000_MAX_FLEX_FILTER_PRI)
2686                 return -EINVAL;
2687
2688         wufc = E1000_READ_REG(hw, E1000_WUFC);
2689         en_bits = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2690         if ((wufc & en_bits) == en_bits)
2691                 return -EINVAL;  /* the filter is in use. */
2692
2693         E1000_WRITE_REG(hw, E1000_WUFC,
2694                 wufc | E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index));
2695
2696         j = 0;
2697         if (index < E1000_MAX_FHFT)
2698                 reg_off = E1000_FHFT(index);
2699         else
2700                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2701
2702         for (i = 0; i < 16; i++) {
2703                 E1000_WRITE_REG(hw, reg_off + i*4*4, filter->dwords[j]);
2704                 E1000_WRITE_REG(hw, reg_off + (i*4+1)*4, filter->dwords[++j]);
2705                 E1000_WRITE_REG(hw, reg_off + (i*4+2)*4,
2706                                 (uint32_t)filter->mask[i]);
2707                 ++j;
2708         }
2709         queueing |= filter->len |
2710                 (rx_queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2711                 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2712         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, queueing);
2713         return 0;
2714 }
2715
2716 /*
2717  * remove a flex filter
2718  *
2719  * @param
2720  * dev: Pointer to struct rte_eth_dev.
2721  * index: the index the filter allocates.
2722  *
2723  * @return
2724  *    - On success, zero.
2725  *    - On failure, a negative value.
2726  */
2727 static int
2728 eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
2729                                 uint16_t index)
2730 {
2731         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2732         uint32_t wufc, reg_off = 0;
2733         uint8_t i;
2734
2735         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2736
2737         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2738                 return -EINVAL;  /* filter index is out of range. */
2739
2740         wufc = E1000_READ_REG(hw, E1000_WUFC);
2741         E1000_WRITE_REG(hw, E1000_WUFC, wufc & (~(E1000_WUFC_FLX0 << index)));
2742
2743         if (index < E1000_MAX_FHFT)
2744                 reg_off = E1000_FHFT(index);
2745         else
2746                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2747
2748         for (i = 0; i < 64; i++)
2749                 E1000_WRITE_REG(hw, reg_off + i*4, 0);
2750         return 0;
2751 }
2752
2753 /*
2754  * get a flex filter
2755  *
2756  * @param
2757  * dev: Pointer to struct rte_eth_dev.
2758  * index: the index the filter allocates.
2759  * filter: ponter to the filter that returns.
2760  * *rx_queue: the pointer of the queue id the filter assigned to.
2761  *
2762  * @return
2763  *    - On success, zero.
2764  *    - On failure, a negative value.
2765  */
2766 static int
2767 eth_igb_get_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2768                         struct rte_flex_filter *filter, uint16_t *rx_queue)
2769 {
2770         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2771         uint32_t wufc, queueing, wufc_en = 0;
2772         uint8_t i, j;
2773
2774         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2775
2776         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2777                 return -EINVAL;  /* filter index is out of range. */
2778
2779         wufc = E1000_READ_REG(hw, E1000_WUFC);
2780         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2781
2782         if ((wufc & wufc_en) == wufc_en) {
2783                 uint32_t reg_off = 0;
2784                 j = 0;
2785                 if (index < E1000_MAX_FHFT)
2786                         reg_off = E1000_FHFT(index);
2787                 else
2788                         reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2789
2790                 for (i = 0; i < 16; i++, j = i * 2) {
2791                         filter->dwords[j] =
2792                                 E1000_READ_REG(hw, reg_off + i*4*4);
2793                         filter->dwords[j+1] =
2794                                 E1000_READ_REG(hw, reg_off + (i*4+1)*4);
2795                         filter->mask[i] =
2796                                 E1000_READ_REG(hw, reg_off + (i*4+2)*4);
2797                 }
2798                 queueing = E1000_READ_REG(hw,
2799                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2800                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2801                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2802                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
2803                 *rx_queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2804                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2805                 return 0;
2806         }
2807         return -ENOENT;
2808 }
2809
2810 /*
2811  * add a 5tuple filter
2812  *
2813  * @param
2814  * dev: Pointer to struct rte_eth_dev.
2815  * index: the index the filter allocates.
2816  * filter: ponter to the filter that will be added.
2817  * rx_queue: the queue id the filter assigned to.
2818  *
2819  * @return
2820  *    - On success, zero.
2821  *    - On failure, a negative value.
2822  */
2823 static int
2824 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2825                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
2826 {
2827         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2828         uint32_t ftqf, spqf = 0;
2829         uint32_t imir = 0;
2830         uint32_t imir_ext = 0;
2831
2832         if (hw->mac.type != e1000_82576)
2833                 return -ENOSYS;
2834
2835         if (index >= E1000_MAX_FTQF_FILTERS ||
2836                 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2837                 return -EINVAL;  /* filter index is out of range. */
2838
2839         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2840         if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2841                 return -EINVAL;  /* filter index is in use. */
2842
2843         ftqf = 0;
2844         ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2845         if (filter->src_ip_mask == 1) /* 1b means not compare. */
2846                 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2847         if (filter->dst_ip_mask == 1)
2848                 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2849         if (filter->src_port_mask == 1)
2850                 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2851         if (filter->protocol_mask == 1)
2852                 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2853         ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2854         ftqf |= E1000_FTQF_VF_MASK_EN;
2855         ftqf |= E1000_FTQF_QUEUE_ENABLE;
2856         E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2857         E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2858         E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2859
2860         spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2861         E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2862
2863         imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2864         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2865                 imir |= E1000_IMIR_PORT_BP;
2866         else
2867                 imir &= ~E1000_IMIR_PORT_BP;
2868         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2869
2870         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2871         /* tcp flags bits setting. */
2872         if (filter->tcp_flags & TCP_FLAG_ALL) {
2873                 if (filter->tcp_flags & TCP_UGR_FLAG)
2874                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2875                 if (filter->tcp_flags & TCP_ACK_FLAG)
2876                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2877                 if (filter->tcp_flags & TCP_PSH_FLAG)
2878                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2879                 if (filter->tcp_flags & TCP_RST_FLAG)
2880                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2881                 if (filter->tcp_flags & TCP_SYN_FLAG)
2882                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2883                 if (filter->tcp_flags & TCP_FIN_FLAG)
2884                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2885         } else
2886                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2887         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2888         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2889         return 0;
2890 }
2891
2892 /*
2893  * remove a 5tuple filter
2894  *
2895  * @param
2896  * dev: Pointer to struct rte_eth_dev.
2897  * index: the index the filter allocates
2898  *
2899  * @return
2900  *    - On success, zero.
2901  *    - On failure, a negative value.
2902  */
2903 static int
2904 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2905                                 uint16_t index)
2906 {
2907         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2908
2909         if (hw->mac.type != e1000_82576)
2910                 return -ENOSYS;
2911
2912         if (index >= E1000_MAX_FTQF_FILTERS)
2913                 return -EINVAL;  /* filter index is out of range. */
2914
2915         E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
2916         E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
2917         E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
2918         E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
2919         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2920         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2921         return 0;
2922 }
2923
2924 /*
2925  * get a 5tuple filter
2926  *
2927  * @param
2928  * dev: Pointer to struct rte_eth_dev.
2929  * index: the index the filter allocates
2930  * filter: ponter to the filter that returns
2931  * *rx_queue: pointer of the queue id the filter assigned to
2932  *
2933  * @return
2934  *    - On success, zero.
2935  *    - On failure, a negative value.
2936  */
2937 static int
2938 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2939                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
2940 {
2941         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2942         uint32_t spqf, ftqf, imir, imir_ext;
2943
2944         if (hw->mac.type != e1000_82576)
2945                 return -ENOSYS;
2946
2947         if (index >= E1000_MAX_FTQF_FILTERS)
2948                 return -EINVAL;  /* filter index is out of range. */
2949
2950         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2951         if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
2952                 filter->src_ip_mask =
2953                         (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
2954                 filter->dst_ip_mask =
2955                         (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
2956                 filter->src_port_mask =
2957                         (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
2958                 filter->protocol_mask =
2959                         (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
2960                 filter->protocol =
2961                         (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
2962                 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
2963                                 E1000_FTQF_QUEUE_SHIFT);
2964
2965                 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
2966                 filter->src_port = spqf & E1000_SPQF_SRCPORT;
2967
2968                 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
2969                 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
2970
2971                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2972                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2973                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2974                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2975                         E1000_IMIR_PRIORITY_SHIFT;
2976
2977                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2978                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2979                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2980                                 filter->tcp_flags |= TCP_UGR_FLAG;
2981                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2982                                 filter->tcp_flags |= TCP_ACK_FLAG;
2983                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2984                                 filter->tcp_flags |= TCP_PSH_FLAG;
2985                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2986                                 filter->tcp_flags |= TCP_RST_FLAG;
2987                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2988                                 filter->tcp_flags |= TCP_SYN_FLAG;
2989                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2990                                 filter->tcp_flags |= TCP_FIN_FLAG;
2991                 } else
2992                         filter->tcp_flags = 0;
2993                 return 0;
2994         }
2995         return -ENOENT;
2996 }
2997
2998 static int
2999 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3000 {
3001         uint32_t rctl;
3002         struct e1000_hw *hw;
3003         struct rte_eth_dev_info dev_info;
3004         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3005                                      VLAN_TAG_SIZE);
3006
3007         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3008
3009 #ifdef RTE_LIBRTE_82571_SUPPORT
3010         /* XXX: not bigger than max_rx_pktlen */
3011         if (hw->mac.type == e1000_82571)
3012                 return -ENOTSUP;
3013 #endif
3014         eth_igb_infos_get(dev, &dev_info);
3015
3016         /* check that mtu is within the allowed range */
3017         if ((mtu < ETHER_MIN_MTU) ||
3018             (frame_size > dev_info.max_rx_pktlen))
3019                 return -EINVAL;
3020
3021         /* refuse mtu that requires the support of scattered packets when this
3022          * feature has not been enabled before. */
3023         if (!dev->data->scattered_rx &&
3024             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3025                 return -EINVAL;
3026
3027         rctl = E1000_READ_REG(hw, E1000_RCTL);
3028
3029         /* switch to jumbo mode if needed */
3030         if (frame_size > ETHER_MAX_LEN) {
3031                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3032                 rctl |= E1000_RCTL_LPE;
3033         } else {
3034                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3035                 rctl &= ~E1000_RCTL_LPE;
3036         }
3037         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3038
3039         /* update max frame size */
3040         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3041
3042         E1000_WRITE_REG(hw, E1000_RLPML,
3043                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3044
3045         return 0;
3046 }
3047
3048 static inline int
3049 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3050                         uint16_t ethertype)
3051 {
3052         int i;
3053
3054         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3055                 if (filter_info->ethertype_filters[i] == ethertype &&
3056                     (filter_info->ethertype_mask & (1 << i)))
3057                         return i;
3058         }
3059         return -1;
3060 }
3061
3062 static inline int
3063 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3064                         uint16_t ethertype)
3065 {
3066         int i;
3067
3068         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3069                 if (!(filter_info->ethertype_mask & (1 << i))) {
3070                         filter_info->ethertype_mask |= 1 << i;
3071                         filter_info->ethertype_filters[i] = ethertype;
3072                         return i;
3073                 }
3074         }
3075         return -1;
3076 }
3077
3078 static inline int
3079 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3080                         uint8_t idx)
3081 {
3082         if (idx >= E1000_MAX_ETQF_FILTERS)
3083                 return -1;
3084         filter_info->ethertype_mask &= ~(1 << idx);
3085         filter_info->ethertype_filters[idx] = 0;
3086         return idx;
3087 }
3088
3089
3090 static int
3091 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3092                         struct rte_eth_ethertype_filter *filter,
3093                         bool add)
3094 {
3095         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3096         struct e1000_filter_info *filter_info =
3097                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3098         uint32_t etqf = 0;
3099         int ret;
3100
3101         if (filter->ether_type == ETHER_TYPE_IPv4 ||
3102                 filter->ether_type == ETHER_TYPE_IPv6) {
3103                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3104                         " ethertype filter.", filter->ether_type);
3105                 return -EINVAL;
3106         }
3107
3108         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3109                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3110                 return -EINVAL;
3111         }
3112         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3113                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3114                 return -EINVAL;
3115         }
3116
3117         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3118         if (ret >= 0 && add) {
3119                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3120                             filter->ether_type);
3121                 return -EEXIST;
3122         }
3123         if (ret < 0 && !add) {
3124                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3125                             filter->ether_type);
3126                 return -ENOENT;
3127         }
3128
3129         if (add) {
3130                 ret = igb_ethertype_filter_insert(filter_info,
3131                         filter->ether_type);
3132                 if (ret < 0) {
3133                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
3134                         return -ENOSYS;
3135                 }
3136
3137                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3138                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3139                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3140         } else {
3141                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3142                 if (ret < 0)
3143                         return -ENOSYS;
3144         }
3145         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3146         E1000_WRITE_FLUSH(hw);
3147
3148         return 0;
3149 }
3150
3151 static int
3152 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3153                         struct rte_eth_ethertype_filter *filter)
3154 {
3155         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3156         struct e1000_filter_info *filter_info =
3157                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3158         uint32_t etqf;
3159         int ret;
3160
3161         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3162         if (ret < 0) {
3163                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3164                             filter->ether_type);
3165                 return -ENOENT;
3166         }
3167
3168         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3169         if (etqf & E1000_ETQF_FILTER_ENABLE) {
3170                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3171                 filter->flags = 0;
3172                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3173                                 E1000_ETQF_QUEUE_SHIFT;
3174                 return 0;
3175         }
3176
3177         return -ENOENT;
3178 }
3179
3180 /*
3181  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3182  * @dev: pointer to rte_eth_dev structure
3183  * @filter_op:operation will be taken.
3184  * @arg: a pointer to specific structure corresponding to the filter_op
3185  */
3186 static int
3187 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3188                                 enum rte_filter_op filter_op,
3189                                 void *arg)
3190 {
3191         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3192         int ret;
3193
3194         MAC_TYPE_FILTER_SUP(hw->mac.type);
3195
3196         if (filter_op == RTE_ETH_FILTER_NOP)
3197                 return 0;
3198
3199         if (arg == NULL) {
3200                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3201                             filter_op);
3202                 return -EINVAL;
3203         }
3204
3205         switch (filter_op) {
3206         case RTE_ETH_FILTER_ADD:
3207                 ret = igb_add_del_ethertype_filter(dev,
3208                         (struct rte_eth_ethertype_filter *)arg,
3209                         TRUE);
3210                 break;
3211         case RTE_ETH_FILTER_DELETE:
3212                 ret = igb_add_del_ethertype_filter(dev,
3213                         (struct rte_eth_ethertype_filter *)arg,
3214                         FALSE);
3215                 break;
3216         case RTE_ETH_FILTER_GET:
3217                 ret = igb_get_ethertype_filter(dev,
3218                         (struct rte_eth_ethertype_filter *)arg);
3219                 break;
3220         default:
3221                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3222                 ret = -EINVAL;
3223                 break;
3224         }
3225         return ret;
3226 }
3227
3228 static int
3229 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3230                      enum rte_filter_type filter_type,
3231                      enum rte_filter_op filter_op,
3232                      void *arg)
3233 {
3234         int ret = -EINVAL;
3235
3236         switch (filter_type) {
3237         case RTE_ETH_FILTER_ETHERTYPE:
3238                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3239                 break;
3240         default:
3241                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3242                                                         filter_type);
3243                 break;
3244         }
3245
3246         return ret;
3247 }
3248
3249 static struct rte_driver pmd_igb_drv = {
3250         .type = PMD_PDEV,
3251         .init = rte_igb_pmd_init,
3252 };
3253
3254 static struct rte_driver pmd_igbvf_drv = {
3255         .type = PMD_PDEV,
3256         .init = rte_igbvf_pmd_init,
3257 };
3258
3259 PMD_REGISTER_DRIVER(pmd_igb_drv);
3260 PMD_REGISTER_DRIVER(pmd_igbvf_drv);