lib/librte_pmd_e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_tailq.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "e1000/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 static int  eth_igb_configure(struct rte_eth_dev *dev);
  61 static int  eth_igb_start(struct rte_eth_dev *dev);
  62 static void eth_igb_stop(struct rte_eth_dev *dev);
  63 static void eth_igb_close(struct rte_eth_dev *dev);
  64 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  65 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  66 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  67 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  68 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  69                                 int wait_to_complete);
  70 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  71                                 struct rte_eth_stats *rte_stats);
  72 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  73 static void eth_igb_infos_get(struct rte_eth_dev *dev,
  74                                 struct rte_eth_dev_info *dev_info);
  75 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
  76                                 struct rte_eth_fc_conf *fc_conf);
  77 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
  78                                 struct rte_eth_fc_conf *fc_conf);
  79 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
  80 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
  81 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
  82 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
  83                                                         void *param);
  84 static int  igb_hardware_init(struct e1000_hw *hw);
  85 static void igb_hw_control_acquire(struct e1000_hw *hw);
  86 static void igb_hw_control_release(struct e1000_hw *hw);
  87 static void igb_init_manageability(struct e1000_hw *hw);
  88 static void igb_release_manageability(struct e1000_hw *hw);
  89
  90 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  91
  92 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
  93                 uint16_t vlan_id, int on);
  94 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
  95 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  96
  97 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  98 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  99 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 100 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 101 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 102 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 103
 104 static int eth_igb_led_on(struct rte_eth_dev *dev);
 105 static int eth_igb_led_off(struct rte_eth_dev *dev);
 106
 107 static void igb_intr_disable(struct e1000_hw *hw);
 108 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 109 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 110                 struct ether_addr *mac_addr,
 111                 uint32_t index, uint32_t pool);
 112 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 113
 114 static void igbvf_intr_disable(struct e1000_hw *hw);
 115 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 116 static int igbvf_dev_start(struct rte_eth_dev *dev);
 117 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 118 static void igbvf_dev_close(struct rte_eth_dev *dev);
 119 static int eth_igbvf_link_update(struct e1000_hw *hw);
 120 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 121 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 122 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 123                 uint16_t vlan_id, int on);
 124 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 125 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 126 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 127                  struct rte_eth_rss_reta *reta_conf);
 128 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 129                 struct rte_eth_rss_reta *reta_conf);
 130
 131 static int eth_igb_add_syn_filter(struct rte_eth_dev *dev,
 132                         struct rte_syn_filter *filter, uint16_t rx_queue);
 133 static int eth_igb_remove_syn_filter(struct rte_eth_dev *dev);
 134 static int eth_igb_get_syn_filter(struct rte_eth_dev *dev,
 135                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 136 static int eth_igb_add_ethertype_filter(struct rte_eth_dev *dev,
 137                         uint16_t index,
 138                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 139 static int eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev,
 140                         uint16_t index);
 141 static int eth_igb_get_ethertype_filter(struct rte_eth_dev *dev,
 142                         uint16_t index,
 143                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 144 static int eth_igb_add_2tuple_filter(struct rte_eth_dev *dev,
 145                         uint16_t index,
 146                         struct rte_2tuple_filter *filter, uint16_t rx_queue);
 147 static int eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 148                         uint16_t index);
 149 static int eth_igb_get_2tuple_filter(struct rte_eth_dev *dev,
 150                         uint16_t index,
 151                         struct rte_2tuple_filter *filter, uint16_t *rx_queue);
 152 static int eth_igb_add_flex_filter(struct rte_eth_dev *dev,
 153                         uint16_t index,
 154                         struct rte_flex_filter *filter, uint16_t rx_queue);
 155 static int eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
 156                         uint16_t index);
 157 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 158                         uint16_t index,
 159                         struct rte_flex_filter *filter, uint16_t *rx_queue);
 160 static int eth_igb_add_5tuple_filter(struct rte_eth_dev *dev,
 161                         uint16_t index,
 162                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 163 static int eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
 164                         uint16_t index);
 165 static int eth_igb_get_5tuple_filter(struct rte_eth_dev *dev,
 166                         uint16_t index,
 167                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 168
 169 /*
 170  * Define VF Stats MACRO for Non "cleared on read" register
 171  */
 172 #define UPDATE_VF_STAT(reg, last, cur)            \
 173 {                                                 \
 174         u32 latest = E1000_READ_REG(hw, reg);     \
 175         cur += latest - last;                     \
 176         last = latest;                            \
 177 }
 178
 179
 180 #define IGB_FC_PAUSE_TIME 0x0680
 181 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 182 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 183
 184 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 185
 186 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 187
 188 /*
 189  * The set of PCI devices this driver supports
 190  */
 191 static struct rte_pci_id pci_id_igb_map[] = {
 192
 193 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 194 #include "rte_pci_dev_ids.h"
 195
 196 {.device_id = 0},
 197 };
 198
 199 /*
 200  * The set of PCI devices this driver supports (for 82576&I350 VF)
 201  */
 202 static struct rte_pci_id pci_id_igbvf_map[] = {
 203
 204 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 205 #include "rte_pci_dev_ids.h"
 206
 207 {.device_id = 0},
 208 };
 209
 210 static struct eth_dev_ops eth_igb_ops = {
 211         .dev_configure        = eth_igb_configure,
 212         .dev_start            = eth_igb_start,
 213         .dev_stop             = eth_igb_stop,
 214         .dev_close            = eth_igb_close,
 215         .promiscuous_enable   = eth_igb_promiscuous_enable,
 216         .promiscuous_disable  = eth_igb_promiscuous_disable,
 217         .allmulticast_enable  = eth_igb_allmulticast_enable,
 218         .allmulticast_disable = eth_igb_allmulticast_disable,
 219         .link_update          = eth_igb_link_update,
 220         .stats_get            = eth_igb_stats_get,
 221         .stats_reset          = eth_igb_stats_reset,
 222         .dev_infos_get        = eth_igb_infos_get,
 223         .mtu_set              = eth_igb_mtu_set,
 224         .vlan_filter_set      = eth_igb_vlan_filter_set,
 225         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 226         .vlan_offload_set     = eth_igb_vlan_offload_set,
 227         .rx_queue_setup       = eth_igb_rx_queue_setup,
 228         .rx_queue_release     = eth_igb_rx_queue_release,
 229         .rx_queue_count       = eth_igb_rx_queue_count,
 230         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 231         .tx_queue_setup       = eth_igb_tx_queue_setup,
 232         .tx_queue_release     = eth_igb_tx_queue_release,
 233         .dev_led_on           = eth_igb_led_on,
 234         .dev_led_off          = eth_igb_led_off,
 235         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 236         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 237         .mac_addr_add         = eth_igb_rar_set,
 238         .mac_addr_remove      = eth_igb_rar_clear,
 239         .reta_update          = eth_igb_rss_reta_update,
 240         .reta_query           = eth_igb_rss_reta_query,
 241         .rss_hash_update      = eth_igb_rss_hash_update,
 242         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 243         .add_syn_filter          = eth_igb_add_syn_filter,
 244         .remove_syn_filter       = eth_igb_remove_syn_filter,
 245         .get_syn_filter          = eth_igb_get_syn_filter,
 246         .add_ethertype_filter    = eth_igb_add_ethertype_filter,
 247         .remove_ethertype_filter = eth_igb_remove_ethertype_filter,
 248         .get_ethertype_filter    = eth_igb_get_ethertype_filter,
 249         .add_2tuple_filter       = eth_igb_add_2tuple_filter,
 250         .remove_2tuple_filter    = eth_igb_remove_2tuple_filter,
 251         .get_2tuple_filter       = eth_igb_get_2tuple_filter,
 252         .add_flex_filter         = eth_igb_add_flex_filter,
 253         .remove_flex_filter      = eth_igb_remove_flex_filter,
 254         .get_flex_filter         = eth_igb_get_flex_filter,
 255         .add_5tuple_filter       = eth_igb_add_5tuple_filter,
 256         .remove_5tuple_filter    = eth_igb_remove_5tuple_filter,
 257         .get_5tuple_filter       = eth_igb_get_5tuple_filter,
 258 };
 259
 260 /*
 261  * dev_ops for virtual function, bare necessities for basic vf
 262  * operation have been implemented
 263  */
 264 static struct eth_dev_ops igbvf_eth_dev_ops = {
 265         .dev_configure        = igbvf_dev_configure,
 266         .dev_start            = igbvf_dev_start,
 267         .dev_stop             = igbvf_dev_stop,
 268         .dev_close            = igbvf_dev_close,
 269         .link_update          = eth_igb_link_update,
 270         .stats_get            = eth_igbvf_stats_get,
 271         .stats_reset          = eth_igbvf_stats_reset,
 272         .vlan_filter_set      = igbvf_vlan_filter_set,
 273         .dev_infos_get        = eth_igb_infos_get,
 274         .rx_queue_setup       = eth_igb_rx_queue_setup,
 275         .rx_queue_release     = eth_igb_rx_queue_release,
 276         .tx_queue_setup       = eth_igb_tx_queue_setup,
 277         .tx_queue_release     = eth_igb_tx_queue_release,
 278 };
 279
 280 /**
 281  * Atomically reads the link status information from global
 282  * structure rte_eth_dev.
 283  *
 284  * @param dev
 285  *   - Pointer to the structure rte_eth_dev to read from.
 286  *   - Pointer to the buffer to be saved with the link status.
 287  *
 288  * @return
 289  *   - On success, zero.
 290  *   - On failure, negative value.
 291  */
 292 static inline int
 293 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 294                                 struct rte_eth_link *link)
 295 {
 296         struct rte_eth_link *dst = link;
 297         struct rte_eth_link *src = &(dev->data->dev_link);
 298
 299         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 300                                         *(uint64_t *)src) == 0)
 301                 return -1;
 302
 303         return 0;
 304 }
 305
 306 /**
 307  * Atomically writes the link status information into global
 308  * structure rte_eth_dev.
 309  *
 310  * @param dev
 311  *   - Pointer to the structure rte_eth_dev to read from.
 312  *   - Pointer to the buffer to be saved with the link status.
 313  *
 314  * @return
 315  *   - On success, zero.
 316  *   - On failure, negative value.
 317  */
 318 static inline int
 319 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 320                                 struct rte_eth_link *link)
 321 {
 322         struct rte_eth_link *dst = &(dev->data->dev_link);
 323         struct rte_eth_link *src = link;
 324
 325         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 326                                         *(uint64_t *)src) == 0)
 327                 return -1;
 328
 329         return 0;
 330 }
 331
 332 static inline void
 333 igb_intr_enable(struct rte_eth_dev *dev)
 334 {
 335         struct e1000_interrupt *intr =
 336                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 337         struct e1000_hw *hw =
 338                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 339
 340         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 341         E1000_WRITE_FLUSH(hw);
 342 }
 343
 344 static void
 345 igb_intr_disable(struct e1000_hw *hw)
 346 {
 347         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 348         E1000_WRITE_FLUSH(hw);
 349 }
 350
 351 static inline int32_t
 352 igb_pf_reset_hw(struct e1000_hw *hw)
 353 {
 354         uint32_t ctrl_ext;
 355         int32_t status;
 356
 357         status = e1000_reset_hw(hw);
 358
 359         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 360         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 361         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 362         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 363         E1000_WRITE_FLUSH(hw);
 364
 365         return status;
 366 }
 367
 368 static void
 369 igb_identify_hardware(struct rte_eth_dev *dev)
 370 {
 371         struct e1000_hw *hw =
 372                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 373
 374         hw->vendor_id = dev->pci_dev->id.vendor_id;
 375         hw->device_id = dev->pci_dev->id.device_id;
 376         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 377         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 378
 379         e1000_set_mac_type(hw);
 380
 381         /* need to check if it is a vf device below */
 382 }
 383
 384 static int
 385 igb_reset_swfw_lock(struct e1000_hw *hw)
 386 {
 387         int ret_val;
 388
 389         /*
 390          * Do mac ops initialization manually here, since we will need
 391          * some function pointers set by this call.
 392          */
 393         ret_val = e1000_init_mac_params(hw);
 394         if (ret_val)
 395                 return ret_val;
 396
 397         /*
 398          * SMBI lock should not fail in this early stage. If this is the case,
 399          * it is due to an improper exit of the application.
 400          * So force the release of the faulty lock.
 401          */
 402         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 403                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 404         }
 405         e1000_put_hw_semaphore_generic(hw);
 406
 407         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 408                 uint16_t mask;
 409
 410                 /*
 411                  * Phy lock should not fail in this early stage. If this is the case,
 412                  * it is due to an improper exit of the application.
 413                  * So force the release of the faulty lock.
 414                  */
 415                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 416                 if (hw->bus.func > E1000_FUNC_1)
 417                         mask <<= 2;
 418                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 419                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 420                                     hw->bus.func);
 421                 }
 422                 hw->mac.ops.release_swfw_sync(hw, mask);
 423
 424                 /*
 425                  * This one is more tricky since it is common to all ports; but
 426                  * swfw_sync retries last long enough (1s) to be almost sure that if
 427                  * lock can not be taken it is due to an improper lock of the
 428                  * semaphore.
 429                  */
 430                 mask = E1000_SWFW_EEP_SM;
 431                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 432                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 433                 }
 434                 hw->mac.ops.release_swfw_sync(hw, mask);
 435         }
 436
 437         return E1000_SUCCESS;
 438 }
 439
 440 static int
 441 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 442                    struct rte_eth_dev *eth_dev)
 443 {
 444         int error = 0;
 445         struct rte_pci_device *pci_dev;
 446         struct e1000_hw *hw =
 447                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 448         struct e1000_vfta * shadow_vfta =
 449                         E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 450         uint32_t ctrl_ext;
 451
 452         pci_dev = eth_dev->pci_dev;
 453         eth_dev->dev_ops = &eth_igb_ops;
 454         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 455         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 456
 457         /* for secondary processes, we don't initialise any further as primary
 458          * has already done this work. Only check we don't need a different
 459          * RX function */
 460         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 461                 if (eth_dev->data->scattered_rx)
 462                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 463                 return 0;
 464         }
 465
 466         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 467
 468         igb_identify_hardware(eth_dev);
 469         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 470                 error = -EIO;
 471                 goto err_late;
 472         }
 473
 474         e1000_get_bus_info(hw);
 475
 476         /* Reset any pending lock */
 477         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 478                 error = -EIO;
 479                 goto err_late;
 480         }
 481
 482         /* Finish initialization */
 483         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 484                 error = -EIO;
 485                 goto err_late;
 486         }
 487
 488         hw->mac.autoneg = 1;
 489         hw->phy.autoneg_wait_to_complete = 0;
 490         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 491
 492         /* Copper options */
 493         if (hw->phy.media_type == e1000_media_type_copper) {
 494                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 495                 hw->phy.disable_polarity_correction = 0;
 496                 hw->phy.ms_type = e1000_ms_hw_default;
 497         }
 498
 499         /*
 500          * Start from a known state, this is important in reading the nvm
 501          * and mac from that.
 502          */
 503         igb_pf_reset_hw(hw);
 504
 505         /* Make sure we have a good EEPROM before we read from it */
 506         if (e1000_validate_nvm_checksum(hw) < 0) {
 507                 /*
 508                  * Some PCI-E parts fail the first check due to
 509                  * the link being in sleep state, call it again,
 510                  * if it fails a second time its a real issue.
 511                  */
 512                 if (e1000_validate_nvm_checksum(hw) < 0) {
 513                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 514                         error = -EIO;
 515                         goto err_late;
 516                 }
 517         }
 518
 519         /* Read the permanent MAC address out of the EEPROM */
 520         if (e1000_read_mac_addr(hw) != 0) {
 521                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 522                 error = -EIO;
 523                 goto err_late;
 524         }
 525
 526         /* Allocate memory for storing MAC addresses */
 527         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 528                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 529         if (eth_dev->data->mac_addrs == NULL) {
 530                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 531                                                 "store MAC addresses",
 532                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 533                 error = -ENOMEM;
 534                 goto err_late;
 535         }
 536
 537         /* Copy the permanent MAC address */
 538         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 539
 540         /* initialize the vfta */
 541         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 542
 543         /* Now initialize the hardware */
 544         if (igb_hardware_init(hw) != 0) {
 545                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 546                 rte_free(eth_dev->data->mac_addrs);
 547                 eth_dev->data->mac_addrs = NULL;
 548                 error = -ENODEV;
 549                 goto err_late;
 550         }
 551         hw->mac.get_link_status = 1;
 552
 553         /* Indicate SOL/IDER usage */
 554         if (e1000_check_reset_block(hw) < 0) {
 555                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 556                                         "SOL/IDER session");
 557         }
 558
 559         /* initialize PF if max_vfs not zero */
 560         igb_pf_host_init(eth_dev);
 561
 562         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 563         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 564         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 565         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 566         E1000_WRITE_FLUSH(hw);
 567
 568         PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x",
 569                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 570                      pci_dev->id.device_id);
 571
 572         rte_intr_callback_register(&(pci_dev->intr_handle),
 573                 eth_igb_interrupt_handler, (void *)eth_dev);
 574
 575         /* enable uio intr after callback register */
 576         rte_intr_enable(&(pci_dev->intr_handle));
 577
 578         /* enable support intr */
 579         igb_intr_enable(eth_dev);
 580
 581         return 0;
 582
 583 err_late:
 584         igb_hw_control_release(hw);
 585
 586         return (error);
 587 }
 588
 589 /*
 590  * Virtual Function device init
 591  */
 592 static int
 593 eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 594                 struct rte_eth_dev *eth_dev)
 595 {
 596         struct rte_pci_device *pci_dev;
 597         struct e1000_hw *hw =
 598                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 599         int diag;
 600
 601         PMD_INIT_FUNC_TRACE();
 602
 603         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 604         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 605         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 606
 607         /* for secondary processes, we don't initialise any further as primary
 608          * has already done this work. Only check we don't need a different
 609          * RX function */
 610         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 611                 if (eth_dev->data->scattered_rx)
 612                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 613                 return 0;
 614         }
 615
 616         pci_dev = eth_dev->pci_dev;
 617
 618         hw->device_id = pci_dev->id.device_id;
 619         hw->vendor_id = pci_dev->id.vendor_id;
 620         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 621
 622         /* Initialize the shared code (base driver) */
 623         diag = e1000_setup_init_funcs(hw, TRUE);
 624         if (diag != 0) {
 625                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 626                         diag);
 627                 return -EIO;
 628         }
 629
 630         /* init_mailbox_params */
 631         hw->mbx.ops.init_params(hw);
 632
 633         /* Disable the interrupts for VF */
 634         igbvf_intr_disable(hw);
 635
 636         diag = hw->mac.ops.reset_hw(hw);
 637
 638         /* Allocate memory for storing MAC addresses */
 639         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 640                 hw->mac.rar_entry_count, 0);
 641         if (eth_dev->data->mac_addrs == NULL) {
 642                 PMD_INIT_LOG(ERR,
 643                         "Failed to allocate %d bytes needed to store MAC "
 644                         "addresses",
 645                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 646                 return -ENOMEM;
 647         }
 648
 649         /* Copy the permanent MAC address */
 650         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 651                         &eth_dev->data->mac_addrs[0]);
 652
 653         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 654                      "mac.type=%s",
 655                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 656                      pci_dev->id.device_id, "igb_mac_82576_vf");
 657
 658         return 0;
 659 }
 660
 661 static struct eth_driver rte_igb_pmd = {
 662         {
 663                 .name = "rte_igb_pmd",
 664                 .id_table = pci_id_igb_map,
 665                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 666         },
 667         .eth_dev_init = eth_igb_dev_init,
 668         .dev_private_size = sizeof(struct e1000_adapter),
 669 };
 670
 671 /*
 672  * virtual function driver struct
 673  */
 674 static struct eth_driver rte_igbvf_pmd = {
 675         {
 676                 .name = "rte_igbvf_pmd",
 677                 .id_table = pci_id_igbvf_map,
 678                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 679         },
 680         .eth_dev_init = eth_igbvf_dev_init,
 681         .dev_private_size = sizeof(struct e1000_adapter),
 682 };
 683
 684 static int
 685 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 686 {
 687         rte_eth_driver_register(&rte_igb_pmd);
 688         return 0;
 689 }
 690
 691 static void
 692 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 693 {
 694         struct e1000_hw *hw =
 695                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 696         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 697         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 698         rctl |= E1000_RCTL_VFE;
 699         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 700 }
 701
 702 /*
 703  * VF Driver initialization routine.
 704  * Invoked one at EAL init time.
 705  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 706  */
 707 static int
 708 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 709 {
 710         PMD_INIT_FUNC_TRACE();
 711
 712         rte_eth_driver_register(&rte_igbvf_pmd);
 713         return (0);
 714 }
 715
 716 static int
 717 eth_igb_configure(struct rte_eth_dev *dev)
 718 {
 719         struct e1000_interrupt *intr =
 720                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 721
 722         PMD_INIT_FUNC_TRACE();
 723         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 724         PMD_INIT_FUNC_TRACE();
 725
 726         return (0);
 727 }
 728
 729 static int
 730 eth_igb_start(struct rte_eth_dev *dev)
 731 {
 732         struct e1000_hw *hw =
 733                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 734         int ret, i, mask;
 735         uint32_t ctrl_ext;
 736
 737         PMD_INIT_FUNC_TRACE();
 738
 739         /* Power up the phy. Needed to make the link go Up */
 740         e1000_power_up_phy(hw);
 741
 742         /*
 743          * Packet Buffer Allocation (PBA)
 744          * Writing PBA sets the receive portion of the buffer
 745          * the remainder is used for the transmit buffer.
 746          */
 747         if (hw->mac.type == e1000_82575) {
 748                 uint32_t pba;
 749
 750                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 751                 E1000_WRITE_REG(hw, E1000_PBA, pba);
 752         }
 753
 754         /* Put the address into the Receive Address Array */
 755         e1000_rar_set(hw, hw->mac.addr, 0);
 756
 757         /* Initialize the hardware */
 758         if (igb_hardware_init(hw)) {
 759                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 760                 return (-EIO);
 761         }
 762
 763         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
 764
 765         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 766         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 767         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 768         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 769         E1000_WRITE_FLUSH(hw);
 770
 771         /* configure PF module if SRIOV enabled */
 772         igb_pf_host_configure(dev);
 773
 774         /* Configure for OS presence */
 775         igb_init_manageability(hw);
 776
 777         eth_igb_tx_init(dev);
 778
 779         /* This can fail when allocating mbufs for descriptor rings */
 780         ret = eth_igb_rx_init(dev);
 781         if (ret) {
 782                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 783                 igb_dev_clear_queues(dev);
 784                 return ret;
 785         }
 786
 787         e1000_clear_hw_cntrs_base_generic(hw);
 788
 789         /*
 790          * VLAN Offload Settings
 791          */
 792         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 793                         ETH_VLAN_EXTEND_MASK;
 794         eth_igb_vlan_offload_set(dev, mask);
 795
 796         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 797                 /* Enable VLAN filter since VMDq always use VLAN filter */
 798                 igb_vmdq_vlan_hw_filter_enable(dev);
 799         }
 800
 801         /*
 802          * Configure the Interrupt Moderation register (EITR) with the maximum
 803          * possible value (0xFFFF) to minimize "System Partial Write" issued by
 804          * spurious [DMA] memory updates of RX and TX ring descriptors.
 805          *
 806          * With a EITR granularity of 2 microseconds in the 82576, only 7/8
 807          * spurious memory updates per second should be expected.
 808          * ((65535 * 2) / 1000.1000 ~= 0.131 second).
 809          *
 810          * Because interrupts are not used at all, the MSI-X is not activated
 811          * and interrupt moderation is controlled by EITR[0].
 812          *
 813          * Note that having [almost] disabled memory updates of RX and TX ring
 814          * descriptors through the Interrupt Moderation mechanism, memory
 815          * updates of ring descriptors are now moderated by the configurable
 816          * value of Write-Back Threshold registers.
 817          */
 818         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
 819                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210)) {
 820                 uint32_t ivar;
 821
 822                 /* Enable all RX & TX queues in the IVAR registers */
 823                 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
 824                 for (i = 0; i < 8; i++)
 825                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
 826
 827                 /* Configure EITR with the maximum possible value (0xFFFF) */
 828                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
 829         }
 830
 831         /* Setup link speed and duplex */
 832         switch (dev->data->dev_conf.link_speed) {
 833         case ETH_LINK_SPEED_AUTONEG:
 834                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 835                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 836                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 837                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
 838                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 839                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
 840                 else
 841                         goto error_invalid_config;
 842                 break;
 843         case ETH_LINK_SPEED_10:
 844                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 845                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
 846                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 847                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
 848                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 849                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
 850                 else
 851                         goto error_invalid_config;
 852                 break;
 853         case ETH_LINK_SPEED_100:
 854                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
 855                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
 856                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
 857                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
 858                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
 859                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
 860                 else
 861                         goto error_invalid_config;
 862                 break;
 863         case ETH_LINK_SPEED_1000:
 864                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
 865                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
 866                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
 867                 else
 868                         goto error_invalid_config;
 869                 break;
 870         case ETH_LINK_SPEED_10000:
 871         default:
 872                 goto error_invalid_config;
 873         }
 874         e1000_setup_link(hw);
 875
 876         /* check if lsc interrupt feature is enabled */
 877         if (dev->data->dev_conf.intr_conf.lsc != 0)
 878                 ret = eth_igb_lsc_interrupt_setup(dev);
 879
 880         /* resume enabled intr since hw reset */
 881         igb_intr_enable(dev);
 882
 883         PMD_INIT_LOG(DEBUG, "<<");
 884
 885         return (0);
 886
 887 error_invalid_config:
 888         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
 889                      dev->data->dev_conf.link_speed,
 890                      dev->data->dev_conf.link_duplex, dev->data->port_id);
 891         igb_dev_clear_queues(dev);
 892         return (-EINVAL);
 893 }
 894
 895 /*********************************************************************
 896  *
 897  *  This routine disables all traffic on the adapter by issuing a
 898  *  global reset on the MAC.
 899  *
 900  **********************************************************************/
 901 static void
 902 eth_igb_stop(struct rte_eth_dev *dev)
 903 {
 904         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 905         struct rte_eth_link link;
 906
 907         igb_intr_disable(hw);
 908         igb_pf_reset_hw(hw);
 909         E1000_WRITE_REG(hw, E1000_WUC, 0);
 910
 911         /* Set bit for Go Link disconnect */
 912         if (hw->mac.type >= e1000_82580) {
 913                 uint32_t phpm_reg;
 914
 915                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 916                 phpm_reg |= E1000_82580_PM_GO_LINKD;
 917                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 918         }
 919
 920         /* Power down the phy. Needed to make the link go Down */
 921         e1000_power_down_phy(hw);
 922
 923         igb_dev_clear_queues(dev);
 924
 925         /* clear the recorded link status */
 926         memset(&link, 0, sizeof(link));
 927         rte_igb_dev_atomic_write_link_status(dev, &link);
 928 }
 929
 930 static void
 931 eth_igb_close(struct rte_eth_dev *dev)
 932 {
 933         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 934         struct rte_eth_link link;
 935
 936         eth_igb_stop(dev);
 937         e1000_phy_hw_reset(hw);
 938         igb_release_manageability(hw);
 939         igb_hw_control_release(hw);
 940
 941         /* Clear bit for Go Link disconnect */
 942         if (hw->mac.type >= e1000_82580) {
 943                 uint32_t phpm_reg;
 944
 945                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 946                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
 947                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
 948         }
 949
 950         igb_dev_clear_queues(dev);
 951
 952         memset(&link, 0, sizeof(link));
 953         rte_igb_dev_atomic_write_link_status(dev, &link);
 954 }
 955
 956 static int
 957 igb_get_rx_buffer_size(struct e1000_hw *hw)
 958 {
 959         uint32_t rx_buf_size;
 960         if (hw->mac.type == e1000_82576) {
 961                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
 962         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
 963                 /* PBS needs to be translated according to a lookup table */
 964                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
 965                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
 966                 rx_buf_size = (rx_buf_size << 10);
 967         } else if (hw->mac.type == e1000_i210) {
 968                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
 969         } else {
 970                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
 971         }
 972
 973         return rx_buf_size;
 974 }
 975
 976 /*********************************************************************
 977  *
 978  *  Initialize the hardware
 979  *
 980  **********************************************************************/
 981 static int
 982 igb_hardware_init(struct e1000_hw *hw)
 983 {
 984         uint32_t rx_buf_size;
 985         int diag;
 986
 987         /* Let the firmware know the OS is in control */
 988         igb_hw_control_acquire(hw);
 989
 990         /*
 991          * These parameters control the automatic generation (Tx) and
 992          * response (Rx) to Ethernet PAUSE frames.
 993          * - High water mark should allow for at least two standard size (1518)
 994          *   frames to be received after sending an XOFF.
 995          * - Low water mark works best when it is very near the high water mark.
 996          *   This allows the receiver to restart by sending XON when it has
 997          *   drained a bit. Here we use an arbitrary value of 1500 which will
 998          *   restart after one full frame is pulled from the buffer. There
 999          *   could be several smaller frames in the buffer and if so they will
1000          *   not trigger the XON until their total number reduces the buffer
1001          *   by 1500.
1002          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1003          */
1004         rx_buf_size = igb_get_rx_buffer_size(hw);
1005
1006         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1007         hw->fc.low_water = hw->fc.high_water - 1500;
1008         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1009         hw->fc.send_xon = 1;
1010
1011         /* Set Flow control, use the tunable location if sane */
1012         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1013                 hw->fc.requested_mode = igb_fc_setting;
1014         else
1015                 hw->fc.requested_mode = e1000_fc_none;
1016
1017         /* Issue a global reset */
1018         igb_pf_reset_hw(hw);
1019         E1000_WRITE_REG(hw, E1000_WUC, 0);
1020
1021         diag = e1000_init_hw(hw);
1022         if (diag < 0)
1023                 return (diag);
1024
1025         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1026         e1000_get_phy_info(hw);
1027         e1000_check_for_link(hw);
1028
1029         return (0);
1030 }
1031
1032 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1033 static void
1034 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1035 {
1036         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         struct e1000_hw_stats *stats =
1038                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1039         int pause_frames;
1040
1041         if(hw->phy.media_type == e1000_media_type_copper ||
1042             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1043                 stats->symerrs +=
1044                     E1000_READ_REG(hw,E1000_SYMERRS);
1045                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1046         }
1047
1048         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1049         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1050         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1051         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1052
1053         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1054         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1055         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1056         stats->dc += E1000_READ_REG(hw, E1000_DC);
1057         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1058         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1059         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1060         /*
1061         ** For watchdog management we need to know if we have been
1062         ** paused during the last interval, so capture that here.
1063         */
1064         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1065         stats->xoffrxc += pause_frames;
1066         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1067         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1068         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1069         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1070         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1071         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1072         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1073         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1074         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1075         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1076         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1077         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1078
1079         /* For the 64-bit byte counters the low dword must be read first. */
1080         /* Both registers clear on the read of the high dword */
1081
1082         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1083         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1084         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1085         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1086
1087         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1088         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1089         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1090         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1091         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1092
1093         stats->tor += E1000_READ_REG(hw, E1000_TORH);
1094         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
1095
1096         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1097         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1098         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1099         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1100         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1101         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1102         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1103         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1104         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1105         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1106
1107         /* Interrupt Counts */
1108
1109         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1110         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1111         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1112         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1113         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1114         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1115         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1116         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1117         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1118
1119         /* Host to Card Statistics */
1120
1121         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1122         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1123         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1124         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1125         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1126         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1127         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1128         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1129         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1130         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1131         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1132         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1133         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1134         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1135
1136         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1137         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1138         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1139         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1140         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1141         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1142
1143         if (rte_stats == NULL)
1144                 return;
1145
1146         /* Rx Errors */
1147         rte_stats->ibadcrc = stats->crcerrs;
1148         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1149         rte_stats->imissed = stats->mpc;
1150         rte_stats->ierrors = rte_stats->ibadcrc +
1151                              rte_stats->ibadlen +
1152                              rte_stats->imissed +
1153                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1154
1155         /* Tx Errors */
1156         rte_stats->oerrors = stats->ecol + stats->latecol;
1157
1158         /* XON/XOFF pause frames */
1159         rte_stats->tx_pause_xon  = stats->xontxc;
1160         rte_stats->rx_pause_xon  = stats->xonrxc;
1161         rte_stats->tx_pause_xoff = stats->xofftxc;
1162         rte_stats->rx_pause_xoff = stats->xoffrxc;
1163
1164         rte_stats->ipackets = stats->gprc;
1165         rte_stats->opackets = stats->gptc;
1166         rte_stats->ibytes   = stats->gorc;
1167         rte_stats->obytes   = stats->gotc;
1168 }
1169
1170 static void
1171 eth_igb_stats_reset(struct rte_eth_dev *dev)
1172 {
1173         struct e1000_hw_stats *hw_stats =
1174                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1175
1176         /* HW registers are cleared on read */
1177         eth_igb_stats_get(dev, NULL);
1178
1179         /* Reset software totals */
1180         memset(hw_stats, 0, sizeof(*hw_stats));
1181 }
1182
1183 static void
1184 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1185 {
1186         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1187         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1188                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1189
1190         /* Good Rx packets, include VF loopback */
1191         UPDATE_VF_STAT(E1000_VFGPRC,
1192             hw_stats->last_gprc, hw_stats->gprc);
1193
1194         /* Good Rx octets, include VF loopback */
1195         UPDATE_VF_STAT(E1000_VFGORC,
1196             hw_stats->last_gorc, hw_stats->gorc);
1197
1198         /* Good Tx packets, include VF loopback */
1199         UPDATE_VF_STAT(E1000_VFGPTC,
1200             hw_stats->last_gptc, hw_stats->gptc);
1201
1202         /* Good Tx octets, include VF loopback */
1203         UPDATE_VF_STAT(E1000_VFGOTC,
1204             hw_stats->last_gotc, hw_stats->gotc);
1205
1206         /* Rx Multicst packets */
1207         UPDATE_VF_STAT(E1000_VFMPRC,
1208             hw_stats->last_mprc, hw_stats->mprc);
1209
1210         /* Good Rx loopback packets */
1211         UPDATE_VF_STAT(E1000_VFGPRLBC,
1212             hw_stats->last_gprlbc, hw_stats->gprlbc);
1213
1214         /* Good Rx loopback octets */
1215         UPDATE_VF_STAT(E1000_VFGORLBC,
1216             hw_stats->last_gorlbc, hw_stats->gorlbc);
1217
1218         /* Good Tx loopback packets */
1219         UPDATE_VF_STAT(E1000_VFGPTLBC,
1220             hw_stats->last_gptlbc, hw_stats->gptlbc);
1221
1222         /* Good Tx loopback octets */
1223         UPDATE_VF_STAT(E1000_VFGOTLBC,
1224             hw_stats->last_gotlbc, hw_stats->gotlbc);
1225
1226         if (rte_stats == NULL)
1227                 return;
1228
1229         memset(rte_stats, 0, sizeof(*rte_stats));
1230         rte_stats->ipackets = hw_stats->gprc;
1231         rte_stats->ibytes = hw_stats->gorc;
1232         rte_stats->opackets = hw_stats->gptc;
1233         rte_stats->obytes = hw_stats->gotc;
1234         rte_stats->imcasts = hw_stats->mprc;
1235         rte_stats->ilbpackets = hw_stats->gprlbc;
1236         rte_stats->ilbbytes = hw_stats->gorlbc;
1237         rte_stats->olbpackets = hw_stats->gptlbc;
1238         rte_stats->olbbytes = hw_stats->gotlbc;
1239
1240 }
1241
1242 static void
1243 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1244 {
1245         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1246                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1247
1248         /* Sync HW register to the last stats */
1249         eth_igbvf_stats_get(dev, NULL);
1250
1251         /* reset HW current stats*/
1252         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1253                offsetof(struct e1000_vf_stats, gprc));
1254
1255 }
1256
1257 static void
1258 eth_igb_infos_get(struct rte_eth_dev *dev,
1259                     struct rte_eth_dev_info *dev_info)
1260 {
1261         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1262
1263         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1264         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1265         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1266         dev_info->rx_offload_capa =
1267                 DEV_RX_OFFLOAD_VLAN_STRIP |
1268                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1269                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1270                 DEV_RX_OFFLOAD_TCP_CKSUM;
1271         dev_info->tx_offload_capa =
1272                 DEV_TX_OFFLOAD_VLAN_INSERT |
1273                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1274                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1275                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1276                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1277
1278         switch (hw->mac.type) {
1279         case e1000_82575:
1280                 dev_info->max_rx_queues = 4;
1281                 dev_info->max_tx_queues = 4;
1282                 dev_info->max_vmdq_pools = 0;
1283                 break;
1284
1285         case e1000_82576:
1286                 dev_info->max_rx_queues = 16;
1287                 dev_info->max_tx_queues = 16;
1288                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1289                 break;
1290
1291         case e1000_82580:
1292                 dev_info->max_rx_queues = 8;
1293                 dev_info->max_tx_queues = 8;
1294                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1295                 break;
1296
1297         case e1000_i350:
1298                 dev_info->max_rx_queues = 8;
1299                 dev_info->max_tx_queues = 8;
1300                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1301                 break;
1302
1303         case e1000_i354:
1304                 dev_info->max_rx_queues = 8;
1305                 dev_info->max_tx_queues = 8;
1306                 break;
1307
1308         case e1000_i210:
1309                 dev_info->max_rx_queues = 4;
1310                 dev_info->max_tx_queues = 4;
1311                 dev_info->max_vmdq_pools = 0;
1312                 break;
1313
1314         case e1000_vfadapt:
1315                 dev_info->max_rx_queues = 2;
1316                 dev_info->max_tx_queues = 2;
1317                 dev_info->max_vmdq_pools = 0;
1318                 break;
1319
1320         case e1000_vfadapt_i350:
1321                 dev_info->max_rx_queues = 1;
1322                 dev_info->max_tx_queues = 1;
1323                 dev_info->max_vmdq_pools = 0;
1324                 break;
1325
1326         default:
1327                 /* Should not happen */
1328                 dev_info->max_rx_queues = 0;
1329                 dev_info->max_tx_queues = 0;
1330                 dev_info->max_vmdq_pools = 0;
1331         }
1332 }
1333
1334 /* return 0 means link status changed, -1 means not changed */
1335 static int
1336 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1337 {
1338         struct e1000_hw *hw =
1339                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1340         struct rte_eth_link link, old;
1341         int link_check, count;
1342
1343         link_check = 0;
1344         hw->mac.get_link_status = 1;
1345
1346         /* possible wait-to-complete in up to 9 seconds */
1347         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1348                 /* Read the real link status */
1349                 switch (hw->phy.media_type) {
1350                 case e1000_media_type_copper:
1351                         /* Do the work to read phy */
1352                         e1000_check_for_link(hw);
1353                         link_check = !hw->mac.get_link_status;
1354                         break;
1355
1356                 case e1000_media_type_fiber:
1357                         e1000_check_for_link(hw);
1358                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1359                                       E1000_STATUS_LU);
1360                         break;
1361
1362                 case e1000_media_type_internal_serdes:
1363                         e1000_check_for_link(hw);
1364                         link_check = hw->mac.serdes_has_link;
1365                         break;
1366
1367                 /* VF device is type_unknown */
1368                 case e1000_media_type_unknown:
1369                         eth_igbvf_link_update(hw);
1370                         link_check = !hw->mac.get_link_status;
1371                         break;
1372
1373                 default:
1374                         break;
1375                 }
1376                 if (link_check || wait_to_complete == 0)
1377                         break;
1378                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1379         }
1380         memset(&link, 0, sizeof(link));
1381         rte_igb_dev_atomic_read_link_status(dev, &link);
1382         old = link;
1383
1384         /* Now we check if a transition has happened */
1385         if (link_check) {
1386                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1387                                           &link.link_duplex);
1388                 link.link_status = 1;
1389         } else if (!link_check) {
1390                 link.link_speed = 0;
1391                 link.link_duplex = 0;
1392                 link.link_status = 0;
1393         }
1394         rte_igb_dev_atomic_write_link_status(dev, &link);
1395
1396         /* not changed */
1397         if (old.link_status == link.link_status)
1398                 return -1;
1399
1400         /* changed */
1401         return 0;
1402 }
1403
1404 /*
1405  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1406  * For ASF and Pass Through versions of f/w this means
1407  * that the driver is loaded.
1408  */
1409 static void
1410 igb_hw_control_acquire(struct e1000_hw *hw)
1411 {
1412         uint32_t ctrl_ext;
1413
1414         /* Let firmware know the driver has taken over */
1415         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1416         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1417 }
1418
1419 /*
1420  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1421  * For ASF and Pass Through versions of f/w this means that the
1422  * driver is no longer loaded.
1423  */
1424 static void
1425 igb_hw_control_release(struct e1000_hw *hw)
1426 {
1427         uint32_t ctrl_ext;
1428
1429         /* Let firmware taken over control of h/w */
1430         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1431         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1432                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1433 }
1434
1435 /*
1436  * Bit of a misnomer, what this really means is
1437  * to enable OS management of the system... aka
1438  * to disable special hardware management features.
1439  */
1440 static void
1441 igb_init_manageability(struct e1000_hw *hw)
1442 {
1443         if (e1000_enable_mng_pass_thru(hw)) {
1444                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1445                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1446
1447                 /* disable hardware interception of ARP */
1448                 manc &= ~(E1000_MANC_ARP_EN);
1449
1450                 /* enable receiving management packets to the host */
1451                 manc |= E1000_MANC_EN_MNG2HOST;
1452                 manc2h |= 1 << 5;  /* Mng Port 623 */
1453                 manc2h |= 1 << 6;  /* Mng Port 664 */
1454                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1455                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1456         }
1457 }
1458
1459 static void
1460 igb_release_manageability(struct e1000_hw *hw)
1461 {
1462         if (e1000_enable_mng_pass_thru(hw)) {
1463                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1464
1465                 manc |= E1000_MANC_ARP_EN;
1466                 manc &= ~E1000_MANC_EN_MNG2HOST;
1467
1468                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1469         }
1470 }
1471
1472 static void
1473 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1474 {
1475         struct e1000_hw *hw =
1476                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477         uint32_t rctl;
1478
1479         rctl = E1000_READ_REG(hw, E1000_RCTL);
1480         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1481         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1482 }
1483
1484 static void
1485 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1486 {
1487         struct e1000_hw *hw =
1488                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1489         uint32_t rctl;
1490
1491         rctl = E1000_READ_REG(hw, E1000_RCTL);
1492         rctl &= (~E1000_RCTL_UPE);
1493         if (dev->data->all_multicast == 1)
1494                 rctl |= E1000_RCTL_MPE;
1495         else
1496                 rctl &= (~E1000_RCTL_MPE);
1497         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1498 }
1499
1500 static void
1501 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1502 {
1503         struct e1000_hw *hw =
1504                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1505         uint32_t rctl;
1506
1507         rctl = E1000_READ_REG(hw, E1000_RCTL);
1508         rctl |= E1000_RCTL_MPE;
1509         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1510 }
1511
1512 static void
1513 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1514 {
1515         struct e1000_hw *hw =
1516                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517         uint32_t rctl;
1518
1519         if (dev->data->promiscuous == 1)
1520                 return; /* must remain in all_multicast mode */
1521         rctl = E1000_READ_REG(hw, E1000_RCTL);
1522         rctl &= (~E1000_RCTL_MPE);
1523         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1524 }
1525
1526 static int
1527 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1528 {
1529         struct e1000_hw *hw =
1530                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1531         struct e1000_vfta * shadow_vfta =
1532                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1533         uint32_t vfta;
1534         uint32_t vid_idx;
1535         uint32_t vid_bit;
1536
1537         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1538                               E1000_VFTA_ENTRY_MASK);
1539         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1540         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1541         if (on)
1542                 vfta |= vid_bit;
1543         else
1544                 vfta &= ~vid_bit;
1545         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1546
1547         /* update local VFTA copy */
1548         shadow_vfta->vfta[vid_idx] = vfta;
1549
1550         return 0;
1551 }
1552
1553 static void
1554 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1555 {
1556         struct e1000_hw *hw =
1557                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1558         uint32_t reg = ETHER_TYPE_VLAN ;
1559
1560         reg |= (tpid << 16);
1561         E1000_WRITE_REG(hw, E1000_VET, reg);
1562 }
1563
1564 static void
1565 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1566 {
1567         struct e1000_hw *hw =
1568                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1569         uint32_t reg;
1570
1571         /* Filter Table Disable */
1572         reg = E1000_READ_REG(hw, E1000_RCTL);
1573         reg &= ~E1000_RCTL_CFIEN;
1574         reg &= ~E1000_RCTL_VFE;
1575         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1576 }
1577
1578 static void
1579 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1580 {
1581         struct e1000_hw *hw =
1582                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1583         struct e1000_vfta * shadow_vfta =
1584                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1585         uint32_t reg;
1586         int i;
1587
1588         /* Filter Table Enable, CFI not used for packet acceptance */
1589         reg = E1000_READ_REG(hw, E1000_RCTL);
1590         reg &= ~E1000_RCTL_CFIEN;
1591         reg |= E1000_RCTL_VFE;
1592         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1593
1594         /* restore VFTA table */
1595         for (i = 0; i < IGB_VFTA_SIZE; i++)
1596                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1597 }
1598
1599 static void
1600 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1601 {
1602         struct e1000_hw *hw =
1603                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604         uint32_t reg;
1605
1606         /* VLAN Mode Disable */
1607         reg = E1000_READ_REG(hw, E1000_CTRL);
1608         reg &= ~E1000_CTRL_VME;
1609         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1610 }
1611
1612 static void
1613 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1614 {
1615         struct e1000_hw *hw =
1616                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1617         uint32_t reg;
1618
1619         /* VLAN Mode Enable */
1620         reg = E1000_READ_REG(hw, E1000_CTRL);
1621         reg |= E1000_CTRL_VME;
1622         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1623 }
1624
1625 static void
1626 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1627 {
1628         struct e1000_hw *hw =
1629                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1630         uint32_t reg;
1631
1632         /* CTRL_EXT: Extended VLAN */
1633         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1634         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
1635         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1636
1637         /* Update maximum packet length */
1638         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1639                 E1000_WRITE_REG(hw, E1000_RLPML,
1640                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1641                                                 VLAN_TAG_SIZE);
1642 }
1643
1644 static void
1645 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1646 {
1647         struct e1000_hw *hw =
1648                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1649         uint32_t reg;
1650
1651         /* CTRL_EXT: Extended VLAN */
1652         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1653         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
1654         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1655
1656         /* Update maximum packet length */
1657         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
1658                 E1000_WRITE_REG(hw, E1000_RLPML,
1659                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1660                                                 2 * VLAN_TAG_SIZE);
1661 }
1662
1663 static void
1664 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1665 {
1666         if(mask & ETH_VLAN_STRIP_MASK){
1667                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1668                         igb_vlan_hw_strip_enable(dev);
1669                 else
1670                         igb_vlan_hw_strip_disable(dev);
1671         }
1672
1673         if(mask & ETH_VLAN_FILTER_MASK){
1674                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1675                         igb_vlan_hw_filter_enable(dev);
1676                 else
1677                         igb_vlan_hw_filter_disable(dev);
1678         }
1679
1680         if(mask & ETH_VLAN_EXTEND_MASK){
1681                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1682                         igb_vlan_hw_extend_enable(dev);
1683                 else
1684                         igb_vlan_hw_extend_disable(dev);
1685         }
1686 }
1687
1688
1689 /**
1690  * It enables the interrupt mask and then enable the interrupt.
1691  *
1692  * @param dev
1693  *  Pointer to struct rte_eth_dev.
1694  *
1695  * @return
1696  *  - On success, zero.
1697  *  - On failure, a negative value.
1698  */
1699 static int
1700 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
1701 {
1702         struct e1000_interrupt *intr =
1703                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1704
1705         intr->mask |= E1000_ICR_LSC;
1706
1707         return 0;
1708 }
1709
1710 /*
1711  * It reads ICR and gets interrupt causes, check it and set a bit flag
1712  * to update link status.
1713  *
1714  * @param dev
1715  *  Pointer to struct rte_eth_dev.
1716  *
1717  * @return
1718  *  - On success, zero.
1719  *  - On failure, a negative value.
1720  */
1721 static int
1722 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1723 {
1724         uint32_t icr;
1725         struct e1000_hw *hw =
1726                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727         struct e1000_interrupt *intr =
1728                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1729
1730         igb_intr_disable(hw);
1731
1732         /* read-on-clear nic registers here */
1733         icr = E1000_READ_REG(hw, E1000_ICR);
1734
1735         intr->flags = 0;
1736         if (icr & E1000_ICR_LSC) {
1737                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1738         }
1739
1740         if (icr & E1000_ICR_VMMB)
1741                 intr->flags |= E1000_FLAG_MAILBOX;
1742
1743         return 0;
1744 }
1745
1746 /*
1747  * It executes link_update after knowing an interrupt is prsent.
1748  *
1749  * @param dev
1750  *  Pointer to struct rte_eth_dev.
1751  *
1752  * @return
1753  *  - On success, zero.
1754  *  - On failure, a negative value.
1755  */
1756 static int
1757 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1758 {
1759         struct e1000_hw *hw =
1760                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1761         struct e1000_interrupt *intr =
1762                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1763         uint32_t tctl, rctl;
1764         struct rte_eth_link link;
1765         int ret;
1766
1767         if (intr->flags & E1000_FLAG_MAILBOX) {
1768                 igb_pf_mbx_process(dev);
1769                 intr->flags &= ~E1000_FLAG_MAILBOX;
1770         }
1771
1772         igb_intr_enable(dev);
1773         rte_intr_enable(&(dev->pci_dev->intr_handle));
1774
1775         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
1776                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1777
1778                 /* set get_link_status to check register later */
1779                 hw->mac.get_link_status = 1;
1780                 ret = eth_igb_link_update(dev, 0);
1781
1782                 /* check if link has changed */
1783                 if (ret < 0)
1784                         return 0;
1785
1786                 memset(&link, 0, sizeof(link));
1787                 rte_igb_dev_atomic_read_link_status(dev, &link);
1788                 if (link.link_status) {
1789                         PMD_INIT_LOG(INFO,
1790                                      " Port %d: Link Up - speed %u Mbps - %s",
1791                                      dev->data->port_id,
1792                                      (unsigned)link.link_speed,
1793                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1794                                      "full-duplex" : "half-duplex");
1795                 } else {
1796                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
1797                                      dev->data->port_id);
1798                 }
1799                 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1800                              dev->pci_dev->addr.domain,
1801                              dev->pci_dev->addr.bus,
1802                              dev->pci_dev->addr.devid,
1803                              dev->pci_dev->addr.function);
1804                 tctl = E1000_READ_REG(hw, E1000_TCTL);
1805                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1806                 if (link.link_status) {
1807                         /* enable Tx/Rx */
1808                         tctl |= E1000_TCTL_EN;
1809                         rctl |= E1000_RCTL_EN;
1810                 } else {
1811                         /* disable Tx/Rx */
1812                         tctl &= ~E1000_TCTL_EN;
1813                         rctl &= ~E1000_RCTL_EN;
1814                 }
1815                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1816                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1817                 E1000_WRITE_FLUSH(hw);
1818                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1819         }
1820
1821         return 0;
1822 }
1823
1824 /**
1825  * Interrupt handler which shall be registered at first.
1826  *
1827  * @param handle
1828  *  Pointer to interrupt handle.
1829  * @param param
1830  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1831  *
1832  * @return
1833  *  void
1834  */
1835 static void
1836 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1837                                                         void *param)
1838 {
1839         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1840
1841         eth_igb_interrupt_get_status(dev);
1842         eth_igb_interrupt_action(dev);
1843 }
1844
1845 static int
1846 eth_igb_led_on(struct rte_eth_dev *dev)
1847 {
1848         struct e1000_hw *hw;
1849
1850         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1851         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1852 }
1853
1854 static int
1855 eth_igb_led_off(struct rte_eth_dev *dev)
1856 {
1857         struct e1000_hw *hw;
1858
1859         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1860         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1861 }
1862
1863 static int
1864 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1865 {
1866         struct e1000_hw *hw;
1867         uint32_t ctrl;
1868         int tx_pause;
1869         int rx_pause;
1870
1871         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         fc_conf->pause_time = hw->fc.pause_time;
1873         fc_conf->high_water = hw->fc.high_water;
1874         fc_conf->low_water = hw->fc.low_water;
1875         fc_conf->send_xon = hw->fc.send_xon;
1876         fc_conf->autoneg = hw->mac.autoneg;
1877
1878         /*
1879          * Return rx_pause and tx_pause status according to actual setting of
1880          * the TFCE and RFCE bits in the CTRL register.
1881          */
1882         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1883         if (ctrl & E1000_CTRL_TFCE)
1884                 tx_pause = 1;
1885         else
1886                 tx_pause = 0;
1887
1888         if (ctrl & E1000_CTRL_RFCE)
1889                 rx_pause = 1;
1890         else
1891                 rx_pause = 0;
1892
1893         if (rx_pause && tx_pause)
1894                 fc_conf->mode = RTE_FC_FULL;
1895         else if (rx_pause)
1896                 fc_conf->mode = RTE_FC_RX_PAUSE;
1897         else if (tx_pause)
1898                 fc_conf->mode = RTE_FC_TX_PAUSE;
1899         else
1900                 fc_conf->mode = RTE_FC_NONE;
1901
1902         return 0;
1903 }
1904
1905 static int
1906 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1907 {
1908         struct e1000_hw *hw;
1909         int err;
1910         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1911                 e1000_fc_none,
1912                 e1000_fc_rx_pause,
1913                 e1000_fc_tx_pause,
1914                 e1000_fc_full
1915         };
1916         uint32_t rx_buf_size;
1917         uint32_t max_high_water;
1918         uint32_t rctl;
1919
1920         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1921         if (fc_conf->autoneg != hw->mac.autoneg)
1922                 return -ENOTSUP;
1923         rx_buf_size = igb_get_rx_buffer_size(hw);
1924         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1925
1926         /* At least reserve one Ethernet frame for watermark */
1927         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1928         if ((fc_conf->high_water > max_high_water) ||
1929             (fc_conf->high_water < fc_conf->low_water)) {
1930                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1931                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
1932                 return (-EINVAL);
1933         }
1934
1935         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1936         hw->fc.pause_time     = fc_conf->pause_time;
1937         hw->fc.high_water     = fc_conf->high_water;
1938         hw->fc.low_water      = fc_conf->low_water;
1939         hw->fc.send_xon       = fc_conf->send_xon;
1940
1941         err = e1000_setup_link_generic(hw);
1942         if (err == E1000_SUCCESS) {
1943
1944                 /* check if we want to forward MAC frames - driver doesn't have native
1945                  * capability to do that, so we'll write the registers ourselves */
1946
1947                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1948
1949                 /* set or clear MFLCN.PMCF bit depending on configuration */
1950                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1951                         rctl |= E1000_RCTL_PMCF;
1952                 else
1953                         rctl &= ~E1000_RCTL_PMCF;
1954
1955                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1956                 E1000_WRITE_FLUSH(hw);
1957
1958                 return 0;
1959         }
1960
1961         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1962         return (-EIO);
1963 }
1964
1965 #define E1000_RAH_POOLSEL_SHIFT      (18)
1966 static void
1967 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1968                 uint32_t index, __rte_unused uint32_t pool)
1969 {
1970         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1971         uint32_t rah;
1972
1973         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1974         rah = E1000_READ_REG(hw, E1000_RAH(index));
1975         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
1976         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
1977 }
1978
1979 static void
1980 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1981 {
1982         uint8_t addr[ETHER_ADDR_LEN];
1983         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1984
1985         memset(addr, 0, sizeof(addr));
1986
1987         e1000_rar_set(hw, addr, index);
1988 }
1989
1990 /*
1991  * Virtual Function operations
1992  */
1993 static void
1994 igbvf_intr_disable(struct e1000_hw *hw)
1995 {
1996         PMD_INIT_FUNC_TRACE();
1997
1998         /* Clear interrupt mask to stop from interrupts being generated */
1999         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2000
2001         E1000_WRITE_FLUSH(hw);
2002 }
2003
2004 static void
2005 igbvf_stop_adapter(struct rte_eth_dev *dev)
2006 {
2007         u32 reg_val;
2008         u16 i;
2009         struct rte_eth_dev_info dev_info;
2010         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2011
2012         memset(&dev_info, 0, sizeof(dev_info));
2013         eth_igb_infos_get(dev, &dev_info);
2014
2015         /* Clear interrupt mask to stop from interrupts being generated */
2016         igbvf_intr_disable(hw);
2017
2018         /* Clear any pending interrupts, flush previous writes */
2019         E1000_READ_REG(hw, E1000_EICR);
2020
2021         /* Disable the transmit unit.  Each queue must be disabled. */
2022         for (i = 0; i < dev_info.max_tx_queues; i++)
2023                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2024
2025         /* Disable the receive unit by stopping each queue */
2026         for (i = 0; i < dev_info.max_rx_queues; i++) {
2027                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2028                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2029                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2030                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2031                         ;
2032         }
2033
2034         /* flush all queues disables */
2035         E1000_WRITE_FLUSH(hw);
2036         msec_delay(2);
2037 }
2038
2039 static int eth_igbvf_link_update(struct e1000_hw *hw)
2040 {
2041         struct e1000_mbx_info *mbx = &hw->mbx;
2042         struct e1000_mac_info *mac = &hw->mac;
2043         int ret_val = E1000_SUCCESS;
2044
2045         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2046
2047         /*
2048          * We only want to run this if there has been a rst asserted.
2049          * in this case that could mean a link change, device reset,
2050          * or a virtual function reset
2051          */
2052
2053         /* If we were hit with a reset or timeout drop the link */
2054         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2055                 mac->get_link_status = TRUE;
2056
2057         if (!mac->get_link_status)
2058                 goto out;
2059
2060         /* if link status is down no point in checking to see if pf is up */
2061         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2062                 goto out;
2063
2064         /* if we passed all the tests above then the link is up and we no
2065          * longer need to check for link */
2066         mac->get_link_status = FALSE;
2067
2068 out:
2069         return ret_val;
2070 }
2071
2072
2073 static int
2074 igbvf_dev_configure(struct rte_eth_dev *dev)
2075 {
2076         struct rte_eth_conf* conf = &dev->data->dev_conf;
2077
2078         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2079                      dev->data->port_id);
2080
2081         /*
2082          * VF has no ability to enable/disable HW CRC
2083          * Keep the persistent behavior the same as Host PF
2084          */
2085 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2086         if (!conf->rxmode.hw_strip_crc) {
2087                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2088                 conf->rxmode.hw_strip_crc = 1;
2089         }
2090 #else
2091         if (conf->rxmode.hw_strip_crc) {
2092                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2093                 conf->rxmode.hw_strip_crc = 0;
2094         }
2095 #endif
2096
2097         return 0;
2098 }
2099
2100 static int
2101 igbvf_dev_start(struct rte_eth_dev *dev)
2102 {
2103         struct e1000_hw *hw =
2104                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105         int ret;
2106
2107         PMD_INIT_FUNC_TRACE();
2108
2109         hw->mac.ops.reset_hw(hw);
2110
2111         /* Set all vfta */
2112         igbvf_set_vfta_all(dev,1);
2113
2114         eth_igbvf_tx_init(dev);
2115
2116         /* This can fail when allocating mbufs for descriptor rings */
2117         ret = eth_igbvf_rx_init(dev);
2118         if (ret) {
2119                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2120                 igb_dev_clear_queues(dev);
2121                 return ret;
2122         }
2123
2124         return 0;
2125 }
2126
2127 static void
2128 igbvf_dev_stop(struct rte_eth_dev *dev)
2129 {
2130         PMD_INIT_FUNC_TRACE();
2131
2132         igbvf_stop_adapter(dev);
2133
2134         /*
2135           * Clear what we set, but we still keep shadow_vfta to
2136           * restore after device starts
2137           */
2138         igbvf_set_vfta_all(dev,0);
2139
2140         igb_dev_clear_queues(dev);
2141 }
2142
2143 static void
2144 igbvf_dev_close(struct rte_eth_dev *dev)
2145 {
2146         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2147
2148         PMD_INIT_FUNC_TRACE();
2149
2150         e1000_reset_hw(hw);
2151
2152         igbvf_dev_stop(dev);
2153 }
2154
2155 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2156 {
2157         struct e1000_mbx_info *mbx = &hw->mbx;
2158         uint32_t msgbuf[2];
2159
2160         /* After set vlan, vlan strip will also be enabled in igb driver*/
2161         msgbuf[0] = E1000_VF_SET_VLAN;
2162         msgbuf[1] = vid;
2163         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2164         if (on)
2165                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2166
2167         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2168 }
2169
2170 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2171 {
2172         struct e1000_hw *hw =
2173                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2174         struct e1000_vfta * shadow_vfta =
2175                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2176         int i = 0, j = 0, vfta = 0, mask = 1;
2177
2178         for (i = 0; i < IGB_VFTA_SIZE; i++){
2179                 vfta = shadow_vfta->vfta[i];
2180                 if(vfta){
2181                         mask = 1;
2182                         for (j = 0; j < 32; j++){
2183                                 if(vfta & mask)
2184                                         igbvf_set_vfta(hw,
2185                                                 (uint16_t)((i<<5)+j), on);
2186                                 mask<<=1;
2187                         }
2188                 }
2189         }
2190
2191 }
2192
2193 static int
2194 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2195 {
2196         struct e1000_hw *hw =
2197                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198         struct e1000_vfta * shadow_vfta =
2199                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2200         uint32_t vid_idx = 0;
2201         uint32_t vid_bit = 0;
2202         int ret = 0;
2203
2204         PMD_INIT_FUNC_TRACE();
2205
2206         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2207         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2208         if(ret){
2209                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2210                 return ret;
2211         }
2212         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2213         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2214
2215         /*Save what we set and retore it after device reset*/
2216         if (on)
2217                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2218         else
2219                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2220
2221         return 0;
2222 }
2223
2224 static int
2225 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2226                                 struct rte_eth_rss_reta *reta_conf)
2227 {
2228         uint8_t i,j,mask;
2229         uint32_t reta;
2230         struct e1000_hw *hw =
2231                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2232
2233         /*
2234          * Update Redirection Table RETA[n],n=0...31,The redirection table has
2235          * 128-entries in 32 registers
2236          */
2237         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2238                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2239                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2240                 else
2241                         mask = (uint8_t)((reta_conf->mask_hi >>
2242                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2243                 if (mask != 0) {
2244                         reta = 0;
2245                         /* If all 4 entries were set,don't need read RETA register */
2246                         if (mask != 0xF)
2247                                 reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2248
2249                         for (j = 0; j < 4; j++) {
2250                                 if (mask & (0x1 << j)) {
2251                                         if (mask != 0xF)
2252                                                 reta &= ~(0xFF << 8 * j);
2253                                         reta |= reta_conf->reta[i + j] << 8 * j;
2254                                 }
2255                         }
2256                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2),reta);
2257                 }
2258         }
2259
2260         return 0;
2261 }
2262
2263 static int
2264 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2265                                 struct rte_eth_rss_reta *reta_conf)
2266 {
2267         uint8_t i,j,mask;
2268         uint32_t reta;
2269         struct e1000_hw *hw =
2270                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2271
2272         /*
2273          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2274          * 128-entries in 32 registers
2275          */
2276         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2277                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2278                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2279                 else
2280                         mask = (uint8_t)((reta_conf->mask_hi >>
2281                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2282
2283                 if (mask != 0) {
2284                         reta = E1000_READ_REG(hw,E1000_RETA(i >> 2));
2285                         for (j = 0; j < 4; j++) {
2286                                 if (mask & (0x1 << j))
2287                                         reta_conf->reta[i + j] =
2288                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2289                         }
2290                 }
2291         }
2292
2293         return 0;
2294 }
2295
2296 #define MAC_TYPE_FILTER_SUP(type)    do {\
2297         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2298                 (type) != e1000_82576)\
2299                 return -ENOSYS;\
2300 } while (0)
2301
2302 /*
2303  * add the syn filter
2304  *
2305  * @param
2306  * dev: Pointer to struct rte_eth_dev.
2307  * filter: ponter to the filter that will be added.
2308  * rx_queue: the queue id the filter assigned to.
2309  *
2310  * @return
2311  *    - On success, zero.
2312  *    - On failure, a negative value.
2313  */
2314 static int
2315 eth_igb_add_syn_filter(struct rte_eth_dev *dev,
2316                         struct rte_syn_filter *filter, uint16_t rx_queue)
2317 {
2318         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2319         uint32_t synqf, rfctl;
2320
2321         MAC_TYPE_FILTER_SUP(hw->mac.type);
2322
2323         if (rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2324                 return -EINVAL;
2325
2326         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2327         if (synqf & E1000_SYN_FILTER_ENABLE)
2328                 return -EINVAL;
2329
2330         synqf = (uint32_t)(((rx_queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2331                 E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2332
2333         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2334         if (filter->hig_pri)
2335                 rfctl |= E1000_RFCTL_SYNQFP;
2336         else
2337                 rfctl &= ~E1000_RFCTL_SYNQFP;
2338
2339         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2340         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2341         return 0;
2342 }
2343
2344 /*
2345  * remove the syn filter
2346  *
2347  * @param
2348  * dev: Pointer to struct rte_eth_dev.
2349  *
2350  * @return
2351  *    - On success, zero.
2352  *    - On failure, a negative value.
2353  */
2354 static int
2355 eth_igb_remove_syn_filter(struct rte_eth_dev *dev)
2356 {
2357         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358
2359         MAC_TYPE_FILTER_SUP(hw->mac.type);
2360
2361         E1000_WRITE_REG(hw, E1000_SYNQF(0), 0);
2362         return 0;
2363 }
2364
2365 /*
2366  * get the syn filter's info
2367  *
2368  * @param
2369  * dev: Pointer to struct rte_eth_dev.
2370  * filter: ponter to the filter that returns.
2371  * *rx_queue: pointer to the queue id the filter assigned to.
2372  *
2373  * @return
2374  *    - On success, zero.
2375  *    - On failure, a negative value.
2376  */
2377 static int
2378 eth_igb_get_syn_filter(struct rte_eth_dev *dev,
2379                         struct rte_syn_filter *filter, uint16_t *rx_queue)
2380 {
2381         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2382         uint32_t synqf, rfctl;
2383
2384         MAC_TYPE_FILTER_SUP(hw->mac.type);
2385         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2386         if (synqf & E1000_SYN_FILTER_ENABLE) {
2387                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2388                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2389                 *rx_queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2390                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2391                 return 0;
2392         }
2393         return -ENOENT;
2394 }
2395
2396 /*
2397  * add an ethertype filter
2398  *
2399  * @param
2400  * dev: Pointer to struct rte_eth_dev.
2401  * index: the index the filter allocates.
2402  * filter: ponter to the filter that will be added.
2403  * rx_queue: the queue id the filter assigned to.
2404  *
2405  * @return
2406  *    - On success, zero.
2407  *    - On failure, a negative value.
2408  */
2409 static int
2410 eth_igb_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2411                         struct rte_ethertype_filter *filter, uint16_t rx_queue)
2412 {
2413         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414         uint32_t etqf;
2415
2416         MAC_TYPE_FILTER_SUP(hw->mac.type);
2417
2418         if (index >= E1000_MAX_ETQF_FILTERS || rx_queue >= IGB_MAX_RX_QUEUE_NUM)
2419                 return -EINVAL;
2420
2421         etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2422         if (etqf & E1000_ETQF_FILTER_ENABLE)
2423                 return -EINVAL;  /* filter index is in use. */
2424         else
2425                 etqf = 0;
2426
2427         etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
2428         etqf |= (uint32_t)(filter->ethertype & E1000_ETQF_ETHERTYPE);
2429         etqf |= rx_queue << E1000_ETQF_QUEUE_SHIFT;
2430
2431         if (filter->priority_en) {
2432                 PMD_INIT_LOG(ERR, "vlan and priority (%d) is not supported"
2433                         " in E1000.", filter->priority);
2434                 return -EINVAL;
2435         }
2436
2437         E1000_WRITE_REG(hw, E1000_ETQF(index), etqf);
2438         return 0;
2439 }
2440
2441 /*
2442  * remove an ethertype filter
2443  *
2444  * @param
2445  * dev: Pointer to struct rte_eth_dev.
2446  * index: the index the filter allocates.
2447  *
2448  * @return
2449  *    - On success, zero.
2450  *    - On failure, a negative value.
2451  */
2452 static int
2453 eth_igb_remove_ethertype_filter(struct rte_eth_dev *dev, uint16_t index)
2454 {
2455         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456
2457         MAC_TYPE_FILTER_SUP(hw->mac.type);
2458
2459         if (index >= E1000_MAX_ETQF_FILTERS)
2460                 return -EINVAL;
2461
2462         E1000_WRITE_REG(hw, E1000_ETQF(index), 0);
2463         return 0;
2464 }
2465
2466 /*
2467  * get an ethertype filter
2468  *
2469  * @param
2470  * dev: Pointer to struct rte_eth_dev.
2471  * index: the index the filter allocates.
2472  * filter: ponter to the filter that will be gotten.
2473  * *rx_queue: the ponited of the queue id the filter assigned to.
2474  *
2475  * @return
2476  *    - On success, zero.
2477  *    - On failure, a negative value.
2478  */
2479 static int
2480 eth_igb_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
2481                         struct rte_ethertype_filter *filter, uint16_t *rx_queue)
2482 {
2483         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2484         uint32_t etqf;
2485
2486         MAC_TYPE_FILTER_SUP(hw->mac.type);
2487
2488         if (index >= E1000_MAX_ETQF_FILTERS)
2489                 return -EINVAL;
2490
2491         etqf = E1000_READ_REG(hw, E1000_ETQF(index));
2492         if (etqf & E1000_ETQF_FILTER_ENABLE) {
2493                 filter->ethertype = etqf & E1000_ETQF_ETHERTYPE;
2494                 filter->priority_en = 0;
2495                 *rx_queue = (etqf & E1000_ETQF_QUEUE) >> E1000_ETQF_QUEUE_SHIFT;
2496                 return 0;
2497         }
2498         return -ENOENT;
2499 }
2500
2501 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2502         if ((type) != e1000_82580 && (type) != e1000_i350)\
2503                 return -ENOSYS; \
2504 } while (0)
2505
2506 /*
2507  * add a 2tuple filter
2508  *
2509  * @param
2510  * dev: Pointer to struct rte_eth_dev.
2511  * index: the index the filter allocates.
2512  * filter: ponter to the filter that will be added.
2513  * rx_queue: the queue id the filter assigned to.
2514  *
2515  * @return
2516  *    - On success, zero.
2517  *    - On failure, a negative value.
2518  */
2519 static int
2520 eth_igb_add_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2521                         struct rte_2tuple_filter *filter, uint16_t rx_queue)
2522 {
2523         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2524         uint32_t ttqf, imir = 0;
2525         uint32_t imir_ext = 0;
2526
2527         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2528
2529         if (index >= E1000_MAX_TTQF_FILTERS ||
2530                 rx_queue >= IGB_MAX_RX_QUEUE_NUM ||
2531                 filter->priority > E1000_2TUPLE_MAX_PRI)
2532                 return -EINVAL;  /* filter index is out of range. */
2533         if  (filter->tcp_flags > TCP_FLAG_ALL)
2534                 return -EINVAL;  /* flags is invalid. */
2535
2536         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2537         if (ttqf & E1000_TTQF_QUEUE_ENABLE)
2538                 return -EINVAL;  /* filter index is in use. */
2539
2540         imir = (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2541         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2542                 imir |= E1000_IMIR_PORT_BP;
2543         else
2544                 imir &= ~E1000_IMIR_PORT_BP;
2545
2546         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2547
2548         ttqf = 0;
2549         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2550         ttqf |= (uint32_t)(rx_queue << E1000_TTQF_QUEUE_SHIFT);
2551         ttqf |= (uint32_t)(filter->protocol & E1000_TTQF_PROTOCOL_MASK);
2552         if (filter->protocol_mask == 1)
2553                 ttqf |= E1000_TTQF_MASK_ENABLE;
2554         else
2555                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
2556
2557         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2558         /* tcp flags bits setting. */
2559         if (filter->tcp_flags & TCP_FLAG_ALL) {
2560                 if (filter->tcp_flags & TCP_UGR_FLAG)
2561                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2562                 if (filter->tcp_flags & TCP_ACK_FLAG)
2563                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2564                 if (filter->tcp_flags & TCP_PSH_FLAG)
2565                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2566                 if (filter->tcp_flags & TCP_RST_FLAG)
2567                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2568                 if (filter->tcp_flags & TCP_SYN_FLAG)
2569                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2570                 if (filter->tcp_flags & TCP_FIN_FLAG)
2571                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2572                 imir_ext &= ~E1000_IMIR_EXT_CTRL_BP;
2573         } else
2574                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2575         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2576         E1000_WRITE_REG(hw, E1000_TTQF(index), ttqf);
2577         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2578         return 0;
2579 }
2580
2581 /*
2582  * remove a 2tuple filter
2583  *
2584  * @param
2585  * dev: Pointer to struct rte_eth_dev.
2586  * index: the index the filter allocates.
2587  *
2588  * @return
2589  *    - On success, zero.
2590  *    - On failure, a negative value.
2591  */
2592 static int
2593 eth_igb_remove_2tuple_filter(struct rte_eth_dev *dev,
2594                         uint16_t index)
2595 {
2596         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2597
2598         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2599
2600         if (index >= E1000_MAX_TTQF_FILTERS)
2601                 return -EINVAL;  /* filter index is out of range */
2602
2603         E1000_WRITE_REG(hw, E1000_TTQF(index), 0);
2604         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2605         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2606         return 0;
2607 }
2608
2609 /*
2610  * get a 2tuple filter
2611  *
2612  * @param
2613  * dev: Pointer to struct rte_eth_dev.
2614  * index: the index the filter allocates.
2615  * filter: ponter to the filter that returns.
2616  * *rx_queue: pointer of the queue id the filter assigned to.
2617  *
2618  * @return
2619  *    - On success, zero.
2620  *    - On failure, a negative value.
2621  */
2622 static int
2623 eth_igb_get_2tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2624                         struct rte_2tuple_filter *filter, uint16_t *rx_queue)
2625 {
2626         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2627         uint32_t imir, ttqf, imir_ext;
2628
2629         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2630
2631         if (index >= E1000_MAX_TTQF_FILTERS)
2632                 return -EINVAL;  /* filter index is out of range. */
2633
2634         ttqf = E1000_READ_REG(hw, E1000_TTQF(index));
2635         if (ttqf & E1000_TTQF_QUEUE_ENABLE) {
2636                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2637                 filter->protocol = ttqf & E1000_TTQF_PROTOCOL_MASK;
2638                 filter->protocol_mask = (ttqf & E1000_TTQF_MASK_ENABLE) ? 1 : 0;
2639                 *rx_queue = (ttqf & E1000_TTQF_RX_QUEUE_MASK) >>
2640                                 E1000_TTQF_QUEUE_SHIFT;
2641                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2642                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2643                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2644                         E1000_IMIR_PRIORITY_SHIFT;
2645
2646                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2647                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2648                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2649                                 filter->tcp_flags |= TCP_UGR_FLAG;
2650                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2651                                 filter->tcp_flags |= TCP_ACK_FLAG;
2652                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2653                                 filter->tcp_flags |= TCP_PSH_FLAG;
2654                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2655                                 filter->tcp_flags |= TCP_RST_FLAG;
2656                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
2657                                 filter->tcp_flags |= TCP_SYN_FLAG;
2658                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
2659                                 filter->tcp_flags |= TCP_FIN_FLAG;
2660                 } else
2661                         filter->tcp_flags = 0;
2662                 return 0;
2663         }
2664         return -ENOENT;
2665 }
2666
2667 /*
2668  * add a flex filter
2669  *
2670  * @param
2671  * dev: Pointer to struct rte_eth_dev.
2672  * index: the index the filter allocates.
2673  * filter: ponter to the filter that will be added.
2674  * rx_queue: the queue id the filter assigned to.
2675  *
2676  * @return
2677  *    - On success, zero.
2678  *     - On failure, a negative value.
2679  */
2680 static int
2681 eth_igb_add_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2682                         struct rte_flex_filter *filter, uint16_t rx_queue)
2683 {
2684         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2685         uint32_t wufc, en_bits = 0;
2686         uint32_t queueing = 0;
2687         uint32_t reg_off = 0;
2688         uint8_t i, j = 0;
2689
2690         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2691
2692         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2693                 return -EINVAL;  /* filter index is out of range. */
2694
2695         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN ||
2696                 filter->len % 8 != 0 ||
2697                 filter->priority > E1000_MAX_FLEX_FILTER_PRI)
2698                 return -EINVAL;
2699
2700         wufc = E1000_READ_REG(hw, E1000_WUFC);
2701         en_bits = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2702         if ((wufc & en_bits) == en_bits)
2703                 return -EINVAL;  /* the filter is in use. */
2704
2705         E1000_WRITE_REG(hw, E1000_WUFC,
2706                 wufc | E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index));
2707
2708         j = 0;
2709         if (index < E1000_MAX_FHFT)
2710                 reg_off = E1000_FHFT(index);
2711         else
2712                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2713
2714         for (i = 0; i < 16; i++) {
2715                 E1000_WRITE_REG(hw, reg_off + i*4*4, filter->dwords[j]);
2716                 E1000_WRITE_REG(hw, reg_off + (i*4+1)*4, filter->dwords[++j]);
2717                 E1000_WRITE_REG(hw, reg_off + (i*4+2)*4,
2718                                 (uint32_t)filter->mask[i]);
2719                 ++j;
2720         }
2721         queueing |= filter->len |
2722                 (rx_queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
2723                 (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
2724         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET, queueing);
2725         return 0;
2726 }
2727
2728 /*
2729  * remove a flex filter
2730  *
2731  * @param
2732  * dev: Pointer to struct rte_eth_dev.
2733  * index: the index the filter allocates.
2734  *
2735  * @return
2736  *    - On success, zero.
2737  *    - On failure, a negative value.
2738  */
2739 static int
2740 eth_igb_remove_flex_filter(struct rte_eth_dev *dev,
2741                                 uint16_t index)
2742 {
2743         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2744         uint32_t wufc, reg_off = 0;
2745         uint8_t i;
2746
2747         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2748
2749         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2750                 return -EINVAL;  /* filter index is out of range. */
2751
2752         wufc = E1000_READ_REG(hw, E1000_WUFC);
2753         E1000_WRITE_REG(hw, E1000_WUFC, wufc & (~(E1000_WUFC_FLX0 << index)));
2754
2755         if (index < E1000_MAX_FHFT)
2756                 reg_off = E1000_FHFT(index);
2757         else
2758                 reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2759
2760         for (i = 0; i < 64; i++)
2761                 E1000_WRITE_REG(hw, reg_off + i*4, 0);
2762         return 0;
2763 }
2764
2765 /*
2766  * get a flex filter
2767  *
2768  * @param
2769  * dev: Pointer to struct rte_eth_dev.
2770  * index: the index the filter allocates.
2771  * filter: ponter to the filter that returns.
2772  * *rx_queue: the pointer of the queue id the filter assigned to.
2773  *
2774  * @return
2775  *    - On success, zero.
2776  *    - On failure, a negative value.
2777  */
2778 static int
2779 eth_igb_get_flex_filter(struct rte_eth_dev *dev, uint16_t index,
2780                         struct rte_flex_filter *filter, uint16_t *rx_queue)
2781 {
2782         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2783         uint32_t wufc, queueing, wufc_en = 0;
2784         uint8_t i, j;
2785
2786         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
2787
2788         if (index >= E1000_MAX_FLEXIBLE_FILTERS)
2789                 return -EINVAL;  /* filter index is out of range. */
2790
2791         wufc = E1000_READ_REG(hw, E1000_WUFC);
2792         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << index);
2793
2794         if ((wufc & wufc_en) == wufc_en) {
2795                 uint32_t reg_off = 0;
2796                 j = 0;
2797                 if (index < E1000_MAX_FHFT)
2798                         reg_off = E1000_FHFT(index);
2799                 else
2800                         reg_off = E1000_FHFT_EXT(index - E1000_MAX_FHFT);
2801
2802                 for (i = 0; i < 16; i++, j = i * 2) {
2803                         filter->dwords[j] =
2804                                 E1000_READ_REG(hw, reg_off + i*4*4);
2805                         filter->dwords[j+1] =
2806                                 E1000_READ_REG(hw, reg_off + (i*4+1)*4);
2807                         filter->mask[i] =
2808                                 E1000_READ_REG(hw, reg_off + (i*4+2)*4);
2809                 }
2810                 queueing = E1000_READ_REG(hw,
2811                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
2812                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
2813                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
2814                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
2815                 *rx_queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
2816                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
2817                 return 0;
2818         }
2819         return -ENOENT;
2820 }
2821
2822 /*
2823  * add a 5tuple filter
2824  *
2825  * @param
2826  * dev: Pointer to struct rte_eth_dev.
2827  * index: the index the filter allocates.
2828  * filter: ponter to the filter that will be added.
2829  * rx_queue: the queue id the filter assigned to.
2830  *
2831  * @return
2832  *    - On success, zero.
2833  *    - On failure, a negative value.
2834  */
2835 static int
2836 eth_igb_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2837                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
2838 {
2839         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840         uint32_t ftqf, spqf = 0;
2841         uint32_t imir = 0;
2842         uint32_t imir_ext = 0;
2843
2844         if (hw->mac.type != e1000_82576)
2845                 return -ENOSYS;
2846
2847         if (index >= E1000_MAX_FTQF_FILTERS ||
2848                 rx_queue >= IGB_MAX_RX_QUEUE_NUM_82576)
2849                 return -EINVAL;  /* filter index is out of range. */
2850
2851         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2852         if (ftqf & E1000_FTQF_QUEUE_ENABLE)
2853                 return -EINVAL;  /* filter index is in use. */
2854
2855         ftqf = 0;
2856         ftqf |= filter->protocol & E1000_FTQF_PROTOCOL_MASK;
2857         if (filter->src_ip_mask == 1) /* 1b means not compare. */
2858                 ftqf |= E1000_FTQF_SOURCE_ADDR_MASK;
2859         if (filter->dst_ip_mask == 1)
2860                 ftqf |= E1000_FTQF_DEST_ADDR_MASK;
2861         if (filter->src_port_mask == 1)
2862                 ftqf |= E1000_FTQF_SOURCE_PORT_MASK;
2863         if (filter->protocol_mask == 1)
2864                 ftqf |= E1000_FTQF_PROTOCOL_COMP_MASK;
2865         ftqf |= (rx_queue << E1000_FTQF_QUEUE_SHIFT) & E1000_FTQF_QUEUE_MASK;
2866         ftqf |= E1000_FTQF_VF_MASK_EN;
2867         ftqf |= E1000_FTQF_QUEUE_ENABLE;
2868         E1000_WRITE_REG(hw, E1000_FTQF(index), ftqf);
2869         E1000_WRITE_REG(hw, E1000_DAQF(index), filter->dst_ip);
2870         E1000_WRITE_REG(hw, E1000_SAQF(index), filter->src_ip);
2871
2872         spqf |= filter->src_port & E1000_SPQF_SRCPORT;
2873         E1000_WRITE_REG(hw, E1000_SPQF(index), spqf);
2874
2875         imir |= (uint32_t)(filter->dst_port & E1000_IMIR_DSTPORT);
2876         if (filter->dst_port_mask == 1) /* 1b means not compare. */
2877                 imir |= E1000_IMIR_PORT_BP;
2878         else
2879                 imir &= ~E1000_IMIR_PORT_BP;
2880         imir |= filter->priority << E1000_IMIR_PRIORITY_SHIFT;
2881
2882         imir_ext |= E1000_IMIR_EXT_SIZE_BP;
2883         /* tcp flags bits setting. */
2884         if (filter->tcp_flags & TCP_FLAG_ALL) {
2885                 if (filter->tcp_flags & TCP_UGR_FLAG)
2886                         imir_ext |= E1000_IMIR_EXT_CTRL_UGR;
2887                 if (filter->tcp_flags & TCP_ACK_FLAG)
2888                         imir_ext |= E1000_IMIR_EXT_CTRL_ACK;
2889                 if (filter->tcp_flags & TCP_PSH_FLAG)
2890                         imir_ext |= E1000_IMIR_EXT_CTRL_PSH;
2891                 if (filter->tcp_flags & TCP_RST_FLAG)
2892                         imir_ext |= E1000_IMIR_EXT_CTRL_RST;
2893                 if (filter->tcp_flags & TCP_SYN_FLAG)
2894                         imir_ext |= E1000_IMIR_EXT_CTRL_SYN;
2895                 if (filter->tcp_flags & TCP_FIN_FLAG)
2896                         imir_ext |= E1000_IMIR_EXT_CTRL_FIN;
2897         } else
2898                 imir_ext |= E1000_IMIR_EXT_CTRL_BP;
2899         E1000_WRITE_REG(hw, E1000_IMIR(index), imir);
2900         E1000_WRITE_REG(hw, E1000_IMIREXT(index), imir_ext);
2901         return 0;
2902 }
2903
2904 /*
2905  * remove a 5tuple filter
2906  *
2907  * @param
2908  * dev: Pointer to struct rte_eth_dev.
2909  * index: the index the filter allocates
2910  *
2911  * @return
2912  *    - On success, zero.
2913  *    - On failure, a negative value.
2914  */
2915 static int
2916 eth_igb_remove_5tuple_filter(struct rte_eth_dev *dev,
2917                                 uint16_t index)
2918 {
2919         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2920
2921         if (hw->mac.type != e1000_82576)
2922                 return -ENOSYS;
2923
2924         if (index >= E1000_MAX_FTQF_FILTERS)
2925                 return -EINVAL;  /* filter index is out of range. */
2926
2927         E1000_WRITE_REG(hw, E1000_FTQF(index), 0);
2928         E1000_WRITE_REG(hw, E1000_DAQF(index), 0);
2929         E1000_WRITE_REG(hw, E1000_SAQF(index), 0);
2930         E1000_WRITE_REG(hw, E1000_SPQF(index), 0);
2931         E1000_WRITE_REG(hw, E1000_IMIR(index), 0);
2932         E1000_WRITE_REG(hw, E1000_IMIREXT(index), 0);
2933         return 0;
2934 }
2935
2936 /*
2937  * get a 5tuple filter
2938  *
2939  * @param
2940  * dev: Pointer to struct rte_eth_dev.
2941  * index: the index the filter allocates
2942  * filter: ponter to the filter that returns
2943  * *rx_queue: pointer of the queue id the filter assigned to
2944  *
2945  * @return
2946  *    - On success, zero.
2947  *    - On failure, a negative value.
2948  */
2949 static int
2950 eth_igb_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
2951                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
2952 {
2953         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2954         uint32_t spqf, ftqf, imir, imir_ext;
2955
2956         if (hw->mac.type != e1000_82576)
2957                 return -ENOSYS;
2958
2959         if (index >= E1000_MAX_FTQF_FILTERS)
2960                 return -EINVAL;  /* filter index is out of range. */
2961
2962         ftqf = E1000_READ_REG(hw, E1000_FTQF(index));
2963         if (ftqf & E1000_FTQF_QUEUE_ENABLE) {
2964                 filter->src_ip_mask =
2965                         (ftqf & E1000_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
2966                 filter->dst_ip_mask =
2967                         (ftqf & E1000_FTQF_DEST_ADDR_MASK) ? 1 : 0;
2968                 filter->src_port_mask =
2969                         (ftqf & E1000_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
2970                 filter->protocol_mask =
2971                         (ftqf & E1000_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
2972                 filter->protocol =
2973                         (uint8_t)ftqf & E1000_FTQF_PROTOCOL_MASK;
2974                 *rx_queue = (uint16_t)((ftqf & E1000_FTQF_QUEUE_MASK) >>
2975                                 E1000_FTQF_QUEUE_SHIFT);
2976
2977                 spqf = E1000_READ_REG(hw, E1000_SPQF(index));
2978                 filter->src_port = spqf & E1000_SPQF_SRCPORT;
2979
2980                 filter->dst_ip = E1000_READ_REG(hw, E1000_DAQF(index));
2981                 filter->src_ip = E1000_READ_REG(hw, E1000_SAQF(index));
2982
2983                 imir = E1000_READ_REG(hw, E1000_IMIR(index));
2984                 filter->dst_port_mask = (imir & E1000_IMIR_PORT_BP) ? 1 : 0;
2985                 filter->dst_port = (uint16_t)(imir & E1000_IMIR_DSTPORT);
2986                 filter->priority = (imir & E1000_IMIR_PRIORITY) >>
2987                         E1000_IMIR_PRIORITY_SHIFT;
2988
2989                 imir_ext = E1000_READ_REG(hw, E1000_IMIREXT(index));
2990                 if (!(imir_ext & E1000_IMIR_EXT_CTRL_BP)) {
2991                         if (imir_ext & E1000_IMIR_EXT_CTRL_UGR)
2992                                 filter->tcp_flags |= TCP_UGR_FLAG;
2993                         if (imir_ext & E1000_IMIR_EXT_CTRL_ACK)
2994                                 filter->tcp_flags |= TCP_ACK_FLAG;
2995                         if (imir_ext & E1000_IMIR_EXT_CTRL_PSH)
2996                                 filter->tcp_flags |= TCP_PSH_FLAG;
2997                         if (imir_ext & E1000_IMIR_EXT_CTRL_RST)
2998                                 filter->tcp_flags |= TCP_RST_FLAG;
2999                         if (imir_ext & E1000_IMIR_EXT_CTRL_SYN)
3000                                 filter->tcp_flags |= TCP_SYN_FLAG;
3001                         if (imir_ext & E1000_IMIR_EXT_CTRL_FIN)
3002                                 filter->tcp_flags |= TCP_FIN_FLAG;
3003                 } else
3004                         filter->tcp_flags = 0;
3005                 return 0;
3006         }
3007         return -ENOENT;
3008 }
3009
3010 static int
3011 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3012 {
3013         uint32_t rctl;
3014         struct e1000_hw *hw;
3015         struct rte_eth_dev_info dev_info;
3016         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3017                                      VLAN_TAG_SIZE);
3018
3019         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3020
3021 #ifdef RTE_LIBRTE_82571_SUPPORT
3022         /* XXX: not bigger than max_rx_pktlen */
3023         if (hw->mac.type == e1000_82571)
3024                 return -ENOTSUP;
3025 #endif
3026         eth_igb_infos_get(dev, &dev_info);
3027
3028         /* check that mtu is within the allowed range */
3029         if ((mtu < ETHER_MIN_MTU) ||
3030             (frame_size > dev_info.max_rx_pktlen))
3031                 return -EINVAL;
3032
3033         /* refuse mtu that requires the support of scattered packets when this
3034          * feature has not been enabled before. */
3035         if (!dev->data->scattered_rx &&
3036             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3037                 return -EINVAL;
3038
3039         rctl = E1000_READ_REG(hw, E1000_RCTL);
3040
3041         /* switch to jumbo mode if needed */
3042         if (frame_size > ETHER_MAX_LEN) {
3043                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3044                 rctl |= E1000_RCTL_LPE;
3045         } else {
3046                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3047                 rctl &= ~E1000_RCTL_LPE;
3048         }
3049         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3050
3051         /* update max frame size */
3052         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3053
3054         E1000_WRITE_REG(hw, E1000_RLPML,
3055                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3056
3057         return 0;
3058 }
3059
3060 static struct rte_driver pmd_igb_drv = {
3061         .type = PMD_PDEV,
3062         .init = rte_igb_pmd_init,
3063 };
3064
3065 static struct rte_driver pmd_igbvf_drv = {
3066         .type = PMD_PDEV,
3067         .init = rte_igbvf_pmd_init,
3068 };
3069
3070 PMD_REGISTER_DRIVER(pmd_igb_drv);
3071 PMD_REGISTER_DRIVER(pmd_igbvf_drv);