lib/librte_pmd_e1000/igb_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35
  36 #include <stdio.h>
  37 #include <stdlib.h>
  38 #include <string.h>
  39 #include <errno.h>
  40 #include <stdint.h>
  41 #include <stdarg.h>
  42 #include <inttypes.h>
  43
  44 #include <rte_interrupts.h>
  45 #include <rte_byteorder.h>
  46 #include <rte_common.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_memory.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_memzone.h>
  53 #include <rte_launch.h>
  54 #include <rte_tailq.h>
  55 #include <rte_eal.h>
  56 #include <rte_per_lcore.h>
  57 #include <rte_lcore.h>
  58 #include <rte_atomic.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ring.h>
  61 #include <rte_mempool.h>
  62 #include <rte_malloc.h>
  63 #include <rte_mbuf.h>
  64 #include <rte_ether.h>
  65 #include <rte_ethdev.h>
  66 #include <rte_prefetch.h>
  67 #include <rte_udp.h>
  68 #include <rte_tcp.h>
  69 #include <rte_sctp.h>
  70 #include <rte_string_fns.h>
  71
  72 #include "e1000_logs.h"
  73 #include "e1000/e1000_api.h"
  74 #include "e1000_ethdev.h"
  75
  76 #define IGB_RSS_OFFLOAD_ALL ( \
  77                 ETH_RSS_IPV4 | \
  78                 ETH_RSS_IPV4_TCP | \
  79                 ETH_RSS_IPV6 | \
  80                 ETH_RSS_IPV6_EX | \
  81                 ETH_RSS_IPV6_TCP | \
  82                 ETH_RSS_IPV6_TCP_EX | \
  83                 ETH_RSS_IPV4_UDP | \
  84                 ETH_RSS_IPV6_UDP | \
  85                 ETH_RSS_IPV6_UDP_EX)
  86
  87 static inline struct rte_mbuf *
  88 rte_rxmbuf_alloc(struct rte_mempool *mp)
  89 {
  90         struct rte_mbuf *m;
  91
  92         m = __rte_mbuf_raw_alloc(mp);
  93         __rte_mbuf_sanity_check_raw(m, 0);
  94         return (m);
  95 }
  96
  97 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  98         (uint64_t) ((mb)->buf_physaddr + (mb)->data_off)
  99
 100 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
 101         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
 102
 103 /**
 104  * Structure associated with each descriptor of the RX ring of a RX queue.
 105  */
 106 struct igb_rx_entry {
 107         struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
 108 };
 109
 110 /**
 111  * Structure associated with each descriptor of the TX ring of a TX queue.
 112  */
 113 struct igb_tx_entry {
 114         struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
 115         uint16_t next_id; /**< Index of next descriptor in ring. */
 116         uint16_t last_id; /**< Index of last scattered descriptor. */
 117 };
 118
 119 /**
 120  * Structure associated with each RX queue.
 121  */
 122 struct igb_rx_queue {
 123         struct rte_mempool  *mb_pool;   /**< mbuf pool to populate RX ring. */
 124         volatile union e1000_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
 125         uint64_t            rx_ring_phys_addr; /**< RX ring DMA address. */
 126         volatile uint32_t   *rdt_reg_addr; /**< RDT register address. */
 127         volatile uint32_t   *rdh_reg_addr; /**< RDH register address. */
 128         struct igb_rx_entry *sw_ring;   /**< address of RX software ring. */
 129         struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
 130         struct rte_mbuf *pkt_last_seg;  /**< Last segment of current packet. */
 131         uint16_t            nb_rx_desc; /**< number of RX descriptors. */
 132         uint16_t            rx_tail;    /**< current value of RDT register. */
 133         uint16_t            nb_rx_hold; /**< number of held free RX desc. */
 134         uint16_t            rx_free_thresh; /**< max free RX desc to hold. */
 135         uint16_t            queue_id;   /**< RX queue index. */
 136         uint16_t            reg_idx;    /**< RX queue register index. */
 137         uint8_t             port_id;    /**< Device port identifier. */
 138         uint8_t             pthresh;    /**< Prefetch threshold register. */
 139         uint8_t             hthresh;    /**< Host threshold register. */
 140         uint8_t             wthresh;    /**< Write-back threshold register. */
 141         uint8_t             crc_len;    /**< 0 if CRC stripped, 4 otherwise. */
 142         uint8_t             drop_en;  /**< If not 0, set SRRCTL.Drop_En. */
 143 };
 144
 145 /**
 146  * Hardware context number
 147  */
 148 enum igb_advctx_num {
 149         IGB_CTX_0    = 0, /**< CTX0    */
 150         IGB_CTX_1    = 1, /**< CTX1    */
 151         IGB_CTX_NUM  = 2, /**< CTX_NUM */
 152 };
 153
 154 /** Offload features */
 155 union igb_vlan_macip {
 156         uint32_t data;
 157         struct {
 158                 uint16_t l2_l3_len; /**< 7bit L2 and 9b L3 lengths combined */
 159                 uint16_t vlan_tci;
 160                 /**< VLAN Tag Control Identifier (CPU order). */
 161         } f;
 162 };
 163
 164 /*
 165  * Compare mask for vlan_macip_len.data,
 166  * should be in sync with igb_vlan_macip.f layout.
 167  * */
 168 #define TX_VLAN_CMP_MASK        0xFFFF0000  /**< VLAN length - 16-bits. */
 169 #define TX_MAC_LEN_CMP_MASK     0x0000FE00  /**< MAC length - 7-bits. */
 170 #define TX_IP_LEN_CMP_MASK      0x000001FF  /**< IP  length - 9-bits. */
 171 /** MAC+IP  length. */
 172 #define TX_MACIP_LEN_CMP_MASK   (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)
 173
 174 /**
 175  * Strucutre to check if new context need be built
 176  */
 177 struct igb_advctx_info {
 178         uint64_t flags;           /**< ol_flags related to context build. */
 179         uint32_t cmp_mask;        /**< compare mask for vlan_macip_lens */
 180         union igb_vlan_macip vlan_macip_lens; /**< vlan, mac & ip length. */
 181 };
 182
 183 /**
 184  * Structure associated with each TX queue.
 185  */
 186 struct igb_tx_queue {
 187         volatile union e1000_adv_tx_desc *tx_ring; /**< TX ring address */
 188         uint64_t               tx_ring_phys_addr; /**< TX ring DMA address. */
 189         struct igb_tx_entry    *sw_ring; /**< virtual address of SW ring. */
 190         volatile uint32_t      *tdt_reg_addr; /**< Address of TDT register. */
 191         uint32_t               txd_type;      /**< Device-specific TXD type */
 192         uint16_t               nb_tx_desc;    /**< number of TX descriptors. */
 193         uint16_t               tx_tail; /**< Current value of TDT register. */
 194         uint16_t               tx_head;
 195         /**< Index of first used TX descriptor. */
 196         uint16_t               queue_id; /**< TX queue index. */
 197         uint16_t               reg_idx;  /**< TX queue register index. */
 198         uint8_t                port_id;  /**< Device port identifier. */
 199         uint8_t                pthresh;  /**< Prefetch threshold register. */
 200         uint8_t                hthresh;  /**< Host threshold register. */
 201         uint8_t                wthresh;  /**< Write-back threshold register. */
 202         uint32_t               ctx_curr;
 203         /**< Current used hardware descriptor. */
 204         uint32_t               ctx_start;
 205         /**< Start context position for transmit queue. */
 206         struct igb_advctx_info ctx_cache[IGB_CTX_NUM];
 207         /**< Hardware context history.*/
 208 };
 209
 210 #if 1
 211 #define RTE_PMD_USE_PREFETCH
 212 #endif
 213
 214 #ifdef RTE_PMD_USE_PREFETCH
 215 #define rte_igb_prefetch(p)     rte_prefetch0(p)
 216 #else
 217 #define rte_igb_prefetch(p)     do {} while(0)
 218 #endif
 219
 220 #ifdef RTE_PMD_PACKET_PREFETCH
 221 #define rte_packet_prefetch(p) rte_prefetch1(p)
 222 #else
 223 #define rte_packet_prefetch(p)  do {} while(0)
 224 #endif
 225
 226 /*
 227  * Macro for VMDq feature for 1 GbE NIC.
 228  */
 229 #define E1000_VMOLR_SIZE                        (8)
 230
 231 /*********************************************************************
 232  *
 233  *  TX function
 234  *
 235  **********************************************************************/
 236
 237 /*
 238  * Advanced context descriptor are almost same between igb/ixgbe
 239  * This is a separate function, looking for optimization opportunity here
 240  * Rework required to go with the pre-defined values.
 241  */
 242
 243 static inline void
 244 igbe_set_xmit_ctx(struct igb_tx_queue* txq,
 245                 volatile struct e1000_adv_tx_context_desc *ctx_txd,
 246                 uint64_t ol_flags, uint32_t vlan_macip_lens)
 247 {
 248         uint32_t type_tucmd_mlhl;
 249         uint32_t mss_l4len_idx;
 250         uint32_t ctx_idx, ctx_curr;
 251         uint32_t cmp_mask;
 252
 253         ctx_curr = txq->ctx_curr;
 254         ctx_idx = ctx_curr + txq->ctx_start;
 255
 256         cmp_mask = 0;
 257         type_tucmd_mlhl = 0;
 258
 259         if (ol_flags & PKT_TX_VLAN_PKT) {
 260                 cmp_mask |= TX_VLAN_CMP_MASK;
 261         }
 262
 263         if (ol_flags & PKT_TX_IP_CKSUM) {
 264                 type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4;
 265                 cmp_mask |= TX_MAC_LEN_CMP_MASK;
 266         }
 267
 268         /* Specify which HW CTX to upload. */
 269         mss_l4len_idx = (ctx_idx << E1000_ADVTXD_IDX_SHIFT);
 270         switch (ol_flags & PKT_TX_L4_MASK) {
 271         case PKT_TX_UDP_CKSUM:
 272                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP |
 273                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 274                 mss_l4len_idx |= sizeof(struct udp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 275                 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
 276                 break;
 277         case PKT_TX_TCP_CKSUM:
 278                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP |
 279                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 280                 mss_l4len_idx |= sizeof(struct tcp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 281                 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
 282                 break;
 283         case PKT_TX_SCTP_CKSUM:
 284                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP |
 285                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 286                 mss_l4len_idx |= sizeof(struct sctp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 287                 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
 288                 break;
 289         default:
 290                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_RSV |
 291                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 292                 break;
 293         }
 294
 295         txq->ctx_cache[ctx_curr].flags           = ol_flags;
 296         txq->ctx_cache[ctx_curr].cmp_mask        = cmp_mask;
 297         txq->ctx_cache[ctx_curr].vlan_macip_lens.data =
 298                 vlan_macip_lens & cmp_mask;
 299
 300         ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
 301         ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
 302         ctx_txd->mss_l4len_idx   = rte_cpu_to_le_32(mss_l4len_idx);
 303         ctx_txd->seqnum_seed     = 0;
 304 }
 305
 306 /*
 307  * Check which hardware context can be used. Use the existing match
 308  * or create a new context descriptor.
 309  */
 310 static inline uint32_t
 311 what_advctx_update(struct igb_tx_queue *txq, uint64_t flags,
 312                 uint32_t vlan_macip_lens)
 313 {
 314         /* If match with the current context */
 315         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 316                 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
 317                 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
 318                         return txq->ctx_curr;
 319         }
 320
 321         /* If match with the second context */
 322         txq->ctx_curr ^= 1;
 323         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 324                 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
 325                 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
 326                         return txq->ctx_curr;
 327         }
 328
 329         /* Mismatch, use the previous context */
 330         return (IGB_CTX_NUM);
 331 }
 332
 333 static inline uint32_t
 334 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
 335 {
 336         static const uint32_t l4_olinfo[2] = {0, E1000_ADVTXD_POPTS_TXSM};
 337         static const uint32_t l3_olinfo[2] = {0, E1000_ADVTXD_POPTS_IXSM};
 338         uint32_t tmp;
 339
 340         tmp  = l4_olinfo[(ol_flags & PKT_TX_L4_MASK)  != PKT_TX_L4_NO_CKSUM];
 341         tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
 342         return tmp;
 343 }
 344
 345 static inline uint32_t
 346 tx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags)
 347 {
 348         static uint32_t vlan_cmd[2] = {0, E1000_ADVTXD_DCMD_VLE};
 349         return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
 350 }
 351
 352 uint16_t
 353 eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 354                uint16_t nb_pkts)
 355 {
 356         struct igb_tx_queue *txq;
 357         struct igb_tx_entry *sw_ring;
 358         struct igb_tx_entry *txe, *txn;
 359         volatile union e1000_adv_tx_desc *txr;
 360         volatile union e1000_adv_tx_desc *txd;
 361         struct rte_mbuf     *tx_pkt;
 362         struct rte_mbuf     *m_seg;
 363         union igb_vlan_macip vlan_macip_lens;
 364         uint64_t buf_dma_addr;
 365         uint32_t olinfo_status;
 366         uint32_t cmd_type_len;
 367         uint32_t pkt_len;
 368         uint16_t slen;
 369         uint64_t ol_flags;
 370         uint16_t tx_end;
 371         uint16_t tx_id;
 372         uint16_t tx_last;
 373         uint16_t nb_tx;
 374         uint64_t tx_ol_req;
 375         uint32_t new_ctx = 0;
 376         uint32_t ctx = 0;
 377
 378         txq = tx_queue;
 379         sw_ring = txq->sw_ring;
 380         txr     = txq->tx_ring;
 381         tx_id   = txq->tx_tail;
 382         txe = &sw_ring[tx_id];
 383
 384         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
 385                 tx_pkt = *tx_pkts++;
 386                 pkt_len = tx_pkt->pkt_len;
 387
 388                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
 389
 390                 /*
 391                  * The number of descriptors that must be allocated for a
 392                  * packet is the number of segments of that packet, plus 1
 393                  * Context Descriptor for the VLAN Tag Identifier, if any.
 394                  * Determine the last TX descriptor to allocate in the TX ring
 395                  * for the packet, starting from the current position (tx_id)
 396                  * in the ring.
 397                  */
 398                 tx_last = (uint16_t) (tx_id + tx_pkt->nb_segs - 1);
 399
 400                 ol_flags = tx_pkt->ol_flags;
 401                 vlan_macip_lens.f.vlan_tci = tx_pkt->vlan_tci;
 402                 vlan_macip_lens.f.l2_l3_len = tx_pkt->l2_l3_len;
 403                 tx_ol_req = ol_flags & PKT_TX_OFFLOAD_MASK;
 404
 405                 /* If a Context Descriptor need be built . */
 406                 if (tx_ol_req) {
 407                         ctx = what_advctx_update(txq, tx_ol_req,
 408                                 vlan_macip_lens.data);
 409                         /* Only allocate context descriptor if required*/
 410                         new_ctx = (ctx == IGB_CTX_NUM);
 411                         ctx = txq->ctx_curr;
 412                         tx_last = (uint16_t) (tx_last + new_ctx);
 413                 }
 414                 if (tx_last >= txq->nb_tx_desc)
 415                         tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
 416
 417                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
 418                            " tx_first=%u tx_last=%u\n",
 419                            (unsigned) txq->port_id,
 420                            (unsigned) txq->queue_id,
 421                            (unsigned) pkt_len,
 422                            (unsigned) tx_id,
 423                            (unsigned) tx_last);
 424
 425                 /*
 426                  * Check if there are enough free descriptors in the TX ring
 427                  * to transmit the next packet.
 428                  * This operation is based on the two following rules:
 429                  *
 430                  *   1- Only check that the last needed TX descriptor can be
 431                  *      allocated (by construction, if that descriptor is free,
 432                  *      all intermediate ones are also free).
 433                  *
 434                  *      For this purpose, the index of the last TX descriptor
 435                  *      used for a packet (the "last descriptor" of a packet)
 436                  *      is recorded in the TX entries (the last one included)
 437                  *      that are associated with all TX descriptors allocated
 438                  *      for that packet.
 439                  *
 440                  *   2- Avoid to allocate the last free TX descriptor of the
 441                  *      ring, in order to never set the TDT register with the
 442                  *      same value stored in parallel by the NIC in the TDH
 443                  *      register, which makes the TX engine of the NIC enter
 444                  *      in a deadlock situation.
 445                  *
 446                  *      By extension, avoid to allocate a free descriptor that
 447                  *      belongs to the last set of free descriptors allocated
 448                  *      to the same packet previously transmitted.
 449                  */
 450
 451                 /*
 452                  * The "last descriptor" of the previously sent packet, if any,
 453                  * which used the last descriptor to allocate.
 454                  */
 455                 tx_end = sw_ring[tx_last].last_id;
 456
 457                 /*
 458                  * The next descriptor following that "last descriptor" in the
 459                  * ring.
 460                  */
 461                 tx_end = sw_ring[tx_end].next_id;
 462
 463                 /*
 464                  * The "last descriptor" associated with that next descriptor.
 465                  */
 466                 tx_end = sw_ring[tx_end].last_id;
 467
 468                 /*
 469                  * Check that this descriptor is free.
 470                  */
 471                 if (! (txr[tx_end].wb.status & E1000_TXD_STAT_DD)) {
 472                         if (nb_tx == 0)
 473                                 return (0);
 474                         goto end_of_tx;
 475                 }
 476
 477                 /*
 478                  * Set common flags of all TX Data Descriptors.
 479                  *
 480                  * The following bits must be set in all Data Descriptors:
 481                  *   - E1000_ADVTXD_DTYP_DATA
 482                  *   - E1000_ADVTXD_DCMD_DEXT
 483                  *
 484                  * The following bits must be set in the first Data Descriptor
 485                  * and are ignored in the other ones:
 486                  *   - E1000_ADVTXD_DCMD_IFCS
 487                  *   - E1000_ADVTXD_MAC_1588
 488                  *   - E1000_ADVTXD_DCMD_VLE
 489                  *
 490                  * The following bits must only be set in the last Data
 491                  * Descriptor:
 492                  *   - E1000_TXD_CMD_EOP
 493                  *
 494                  * The following bits can be set in any Data Descriptor, but
 495                  * are only set in the last Data Descriptor:
 496                  *   - E1000_TXD_CMD_RS
 497                  */
 498                 cmd_type_len = txq->txd_type |
 499                         E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
 500                 olinfo_status = (pkt_len << E1000_ADVTXD_PAYLEN_SHIFT);
 501 #if defined(RTE_LIBRTE_IEEE1588)
 502                 if (ol_flags & PKT_TX_IEEE1588_TMST)
 503                         cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
 504 #endif
 505                 if (tx_ol_req) {
 506                         /* Setup TX Advanced context descriptor if required */
 507                         if (new_ctx) {
 508                                 volatile struct e1000_adv_tx_context_desc *
 509                                     ctx_txd;
 510
 511                                 ctx_txd = (volatile struct
 512                                     e1000_adv_tx_context_desc *)
 513                                     &txr[tx_id];
 514
 515                                 txn = &sw_ring[txe->next_id];
 516                                 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
 517
 518                                 if (txe->mbuf != NULL) {
 519                                         rte_pktmbuf_free_seg(txe->mbuf);
 520                                         txe->mbuf = NULL;
 521                                 }
 522
 523                                 igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
 524                                     vlan_macip_lens.data);
 525
 526                                 txe->last_id = tx_last;
 527                                 tx_id = txe->next_id;
 528                                 txe = txn;
 529                         }
 530
 531                         /* Setup the TX Advanced Data Descriptor */
 532                         cmd_type_len  |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
 533                         olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
 534                         olinfo_status |= (ctx << E1000_ADVTXD_IDX_SHIFT);
 535                 }
 536
 537                 m_seg = tx_pkt;
 538                 do {
 539                         txn = &sw_ring[txe->next_id];
 540                         txd = &txr[tx_id];
 541
 542                         if (txe->mbuf != NULL)
 543                                 rte_pktmbuf_free_seg(txe->mbuf);
 544                         txe->mbuf = m_seg;
 545
 546                         /*
 547                          * Set up transmit descriptor.
 548                          */
 549                         slen = (uint16_t) m_seg->data_len;
 550                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
 551                         txd->read.buffer_addr =
 552                                 rte_cpu_to_le_64(buf_dma_addr);
 553                         txd->read.cmd_type_len =
 554                                 rte_cpu_to_le_32(cmd_type_len | slen);
 555                         txd->read.olinfo_status =
 556                                 rte_cpu_to_le_32(olinfo_status);
 557                         txe->last_id = tx_last;
 558                         tx_id = txe->next_id;
 559                         txe = txn;
 560                         m_seg = m_seg->next;
 561                 } while (m_seg != NULL);
 562
 563                 /*
 564                  * The last packet data descriptor needs End Of Packet (EOP)
 565                  * and Report Status (RS).
 566                  */
 567                 txd->read.cmd_type_len |=
 568                         rte_cpu_to_le_32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS);
 569         }
 570  end_of_tx:
 571         rte_wmb();
 572
 573         /*
 574          * Set the Transmit Descriptor Tail (TDT).
 575          */
 576         E1000_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
 577         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
 578                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
 579                    (unsigned) tx_id, (unsigned) nb_tx);
 580         txq->tx_tail = tx_id;
 581
 582         return (nb_tx);
 583 }
 584
 585 /*********************************************************************
 586  *
 587  *  RX functions
 588  *
 589  **********************************************************************/
 590 static inline uint64_t
 591 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
 592 {
 593         uint64_t pkt_flags;
 594
 595         static uint64_t ip_pkt_types_map[16] = {
 596                 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
 597                 PKT_RX_IPV6_HDR, 0, 0, 0,
 598                 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
 599                 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
 600         };
 601
 602 #if defined(RTE_LIBRTE_IEEE1588)
 603         static uint32_t ip_pkt_etqf_map[8] = {
 604                 0, 0, 0, PKT_RX_IEEE1588_PTP,
 605                 0, 0, 0, 0,
 606         };
 607
 608         pkt_flags = (hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ?
 609                                 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
 610                                 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
 611 #else
 612         pkt_flags = (hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ? 0 :
 613                                 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
 614 #endif
 615         return pkt_flags | (((hl_tp_rs & 0x0F) == 0) ?  0 : PKT_RX_RSS_HASH);
 616 }
 617
 618 static inline uint64_t
 619 rx_desc_status_to_pkt_flags(uint32_t rx_status)
 620 {
 621         uint64_t pkt_flags;
 622
 623         /* Check if VLAN present */
 624         pkt_flags = (rx_status & E1000_RXD_STAT_VP) ?  PKT_RX_VLAN_PKT : 0;
 625
 626 #if defined(RTE_LIBRTE_IEEE1588)
 627         if (rx_status & E1000_RXD_STAT_TMST)
 628                 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
 629 #endif
 630         return pkt_flags;
 631 }
 632
 633 static inline uint64_t
 634 rx_desc_error_to_pkt_flags(uint32_t rx_status)
 635 {
 636         /*
 637          * Bit 30: IPE, IPv4 checksum error
 638          * Bit 29: L4I, L4I integrity error
 639          */
 640
 641         static uint64_t error_to_pkt_flags_map[4] = {
 642                 0,  PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
 643                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
 644         };
 645         return error_to_pkt_flags_map[(rx_status >>
 646                 E1000_RXD_ERR_CKSUM_BIT) & E1000_RXD_ERR_CKSUM_MSK];
 647 }
 648
 649 uint16_t
 650 eth_igb_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 651                uint16_t nb_pkts)
 652 {
 653         struct igb_rx_queue *rxq;
 654         volatile union e1000_adv_rx_desc *rx_ring;
 655         volatile union e1000_adv_rx_desc *rxdp;
 656         struct igb_rx_entry *sw_ring;
 657         struct igb_rx_entry *rxe;
 658         struct rte_mbuf *rxm;
 659         struct rte_mbuf *nmb;
 660         union e1000_adv_rx_desc rxd;
 661         uint64_t dma_addr;
 662         uint32_t staterr;
 663         uint32_t hlen_type_rss;
 664         uint16_t pkt_len;
 665         uint16_t rx_id;
 666         uint16_t nb_rx;
 667         uint16_t nb_hold;
 668         uint64_t pkt_flags;
 669
 670         nb_rx = 0;
 671         nb_hold = 0;
 672         rxq = rx_queue;
 673         rx_id = rxq->rx_tail;
 674         rx_ring = rxq->rx_ring;
 675         sw_ring = rxq->sw_ring;
 676         while (nb_rx < nb_pkts) {
 677                 /*
 678                  * The order of operations here is important as the DD status
 679                  * bit must not be read after any other descriptor fields.
 680                  * rx_ring and rxdp are pointing to volatile data so the order
 681                  * of accesses cannot be reordered by the compiler. If they were
 682                  * not volatile, they could be reordered which could lead to
 683                  * using invalid descriptor fields when read from rxd.
 684                  */
 685                 rxdp = &rx_ring[rx_id];
 686                 staterr = rxdp->wb.upper.status_error;
 687                 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
 688                         break;
 689                 rxd = *rxdp;
 690
 691                 /*
 692                  * End of packet.
 693                  *
 694                  * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
 695                  * likely to be invalid and to be dropped by the various
 696                  * validation checks performed by the network stack.
 697                  *
 698                  * Allocate a new mbuf to replenish the RX ring descriptor.
 699                  * If the allocation fails:
 700                  *    - arrange for that RX descriptor to be the first one
 701                  *      being parsed the next time the receive function is
 702                  *      invoked [on the same queue].
 703                  *
 704                  *    - Stop parsing the RX ring and return immediately.
 705                  *
 706                  * This policy do not drop the packet received in the RX
 707                  * descriptor for which the allocation of a new mbuf failed.
 708                  * Thus, it allows that packet to be later retrieved if
 709                  * mbuf have been freed in the mean time.
 710                  * As a side effect, holding RX descriptors instead of
 711                  * systematically giving them back to the NIC may lead to
 712                  * RX ring exhaustion situations.
 713                  * However, the NIC can gracefully prevent such situations
 714                  * to happen by sending specific "back-pressure" flow control
 715                  * frames to its peer(s).
 716                  */
 717                 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
 718                            "staterr=0x%x pkt_len=%u\n",
 719                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 720                            (unsigned) rx_id, (unsigned) staterr,
 721                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
 722
 723                 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
 724                 if (nmb == NULL) {
 725                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 726                                    "queue_id=%u\n", (unsigned) rxq->port_id,
 727                                    (unsigned) rxq->queue_id);
 728                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 729                         break;
 730                 }
 731
 732                 nb_hold++;
 733                 rxe = &sw_ring[rx_id];
 734                 rx_id++;
 735                 if (rx_id == rxq->nb_rx_desc)
 736                         rx_id = 0;
 737
 738                 /* Prefetch next mbuf while processing current one. */
 739                 rte_igb_prefetch(sw_ring[rx_id].mbuf);
 740
 741                 /*
 742                  * When next RX descriptor is on a cache-line boundary,
 743                  * prefetch the next 4 RX descriptors and the next 8 pointers
 744                  * to mbufs.
 745                  */
 746                 if ((rx_id & 0x3) == 0) {
 747                         rte_igb_prefetch(&rx_ring[rx_id]);
 748                         rte_igb_prefetch(&sw_ring[rx_id]);
 749                 }
 750
 751                 rxm = rxe->mbuf;
 752                 rxe->mbuf = nmb;
 753                 dma_addr =
 754                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 755                 rxdp->read.hdr_addr = dma_addr;
 756                 rxdp->read.pkt_addr = dma_addr;
 757
 758                 /*
 759                  * Initialize the returned mbuf.
 760                  * 1) setup generic mbuf fields:
 761                  *    - number of segments,
 762                  *    - next segment,
 763                  *    - packet length,
 764                  *    - RX port identifier.
 765                  * 2) integrate hardware offload data, if any:
 766                  *    - RSS flag & hash,
 767                  *    - IP checksum flag,
 768                  *    - VLAN TCI, if any,
 769                  *    - error flags.
 770                  */
 771                 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
 772                                       rxq->crc_len);
 773                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 774                 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
 775                 rxm->nb_segs = 1;
 776                 rxm->next = NULL;
 777                 rxm->pkt_len = pkt_len;
 778                 rxm->data_len = pkt_len;
 779                 rxm->port = rxq->port_id;
 780
 781                 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
 782                 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
 783                 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
 784                 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
 785
 786                 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
 787                 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
 788                 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
 789                 rxm->ol_flags = pkt_flags;
 790
 791                 /*
 792                  * Store the mbuf address into the next entry of the array
 793                  * of returned packets.
 794                  */
 795                 rx_pkts[nb_rx++] = rxm;
 796         }
 797         rxq->rx_tail = rx_id;
 798
 799         /*
 800          * If the number of free RX descriptors is greater than the RX free
 801          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 802          * register.
 803          * Update the RDT with the value of the last processed RX descriptor
 804          * minus 1, to guarantee that the RDT register is never equal to the
 805          * RDH register, which creates a "full" ring situtation from the
 806          * hardware point of view...
 807          */
 808         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
 809         if (nb_hold > rxq->rx_free_thresh) {
 810                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
 811                            "nb_hold=%u nb_rx=%u\n",
 812                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 813                            (unsigned) rx_id, (unsigned) nb_hold,
 814                            (unsigned) nb_rx);
 815                 rx_id = (uint16_t) ((rx_id == 0) ?
 816                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
 817                 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
 818                 nb_hold = 0;
 819         }
 820         rxq->nb_rx_hold = nb_hold;
 821         return (nb_rx);
 822 }
 823
 824 uint16_t
 825 eth_igb_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 826                          uint16_t nb_pkts)
 827 {
 828         struct igb_rx_queue *rxq;
 829         volatile union e1000_adv_rx_desc *rx_ring;
 830         volatile union e1000_adv_rx_desc *rxdp;
 831         struct igb_rx_entry *sw_ring;
 832         struct igb_rx_entry *rxe;
 833         struct rte_mbuf *first_seg;
 834         struct rte_mbuf *last_seg;
 835         struct rte_mbuf *rxm;
 836         struct rte_mbuf *nmb;
 837         union e1000_adv_rx_desc rxd;
 838         uint64_t dma; /* Physical address of mbuf data buffer */
 839         uint32_t staterr;
 840         uint32_t hlen_type_rss;
 841         uint16_t rx_id;
 842         uint16_t nb_rx;
 843         uint16_t nb_hold;
 844         uint16_t data_len;
 845         uint64_t pkt_flags;
 846
 847         nb_rx = 0;
 848         nb_hold = 0;
 849         rxq = rx_queue;
 850         rx_id = rxq->rx_tail;
 851         rx_ring = rxq->rx_ring;
 852         sw_ring = rxq->sw_ring;
 853
 854         /*
 855          * Retrieve RX context of current packet, if any.
 856          */
 857         first_seg = rxq->pkt_first_seg;
 858         last_seg = rxq->pkt_last_seg;
 859
 860         while (nb_rx < nb_pkts) {
 861         next_desc:
 862                 /*
 863                  * The order of operations here is important as the DD status
 864                  * bit must not be read after any other descriptor fields.
 865                  * rx_ring and rxdp are pointing to volatile data so the order
 866                  * of accesses cannot be reordered by the compiler. If they were
 867                  * not volatile, they could be reordered which could lead to
 868                  * using invalid descriptor fields when read from rxd.
 869                  */
 870                 rxdp = &rx_ring[rx_id];
 871                 staterr = rxdp->wb.upper.status_error;
 872                 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
 873                         break;
 874                 rxd = *rxdp;
 875
 876                 /*
 877                  * Descriptor done.
 878                  *
 879                  * Allocate a new mbuf to replenish the RX ring descriptor.
 880                  * If the allocation fails:
 881                  *    - arrange for that RX descriptor to be the first one
 882                  *      being parsed the next time the receive function is
 883                  *      invoked [on the same queue].
 884                  *
 885                  *    - Stop parsing the RX ring and return immediately.
 886                  *
 887                  * This policy does not drop the packet received in the RX
 888                  * descriptor for which the allocation of a new mbuf failed.
 889                  * Thus, it allows that packet to be later retrieved if
 890                  * mbuf have been freed in the mean time.
 891                  * As a side effect, holding RX descriptors instead of
 892                  * systematically giving them back to the NIC may lead to
 893                  * RX ring exhaustion situations.
 894                  * However, the NIC can gracefully prevent such situations
 895                  * to happen by sending specific "back-pressure" flow control
 896                  * frames to its peer(s).
 897                  */
 898                 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
 899                            "staterr=0x%x data_len=%u\n",
 900                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 901                            (unsigned) rx_id, (unsigned) staterr,
 902                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
 903
 904                 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
 905                 if (nmb == NULL) {
 906                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 907                                    "queue_id=%u\n", (unsigned) rxq->port_id,
 908                                    (unsigned) rxq->queue_id);
 909                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 910                         break;
 911                 }
 912
 913                 nb_hold++;
 914                 rxe = &sw_ring[rx_id];
 915                 rx_id++;
 916                 if (rx_id == rxq->nb_rx_desc)
 917                         rx_id = 0;
 918
 919                 /* Prefetch next mbuf while processing current one. */
 920                 rte_igb_prefetch(sw_ring[rx_id].mbuf);
 921
 922                 /*
 923                  * When next RX descriptor is on a cache-line boundary,
 924                  * prefetch the next 4 RX descriptors and the next 8 pointers
 925                  * to mbufs.
 926                  */
 927                 if ((rx_id & 0x3) == 0) {
 928                         rte_igb_prefetch(&rx_ring[rx_id]);
 929                         rte_igb_prefetch(&sw_ring[rx_id]);
 930                 }
 931
 932                 /*
 933                  * Update RX descriptor with the physical address of the new
 934                  * data buffer of the new allocated mbuf.
 935                  */
 936                 rxm = rxe->mbuf;
 937                 rxe->mbuf = nmb;
 938                 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 939                 rxdp->read.pkt_addr = dma;
 940                 rxdp->read.hdr_addr = dma;
 941
 942                 /*
 943                  * Set data length & data buffer address of mbuf.
 944                  */
 945                 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
 946                 rxm->data_len = data_len;
 947                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 948
 949                 /*
 950                  * If this is the first buffer of the received packet,
 951                  * set the pointer to the first mbuf of the packet and
 952                  * initialize its context.
 953                  * Otherwise, update the total length and the number of segments
 954                  * of the current scattered packet, and update the pointer to
 955                  * the last mbuf of the current packet.
 956                  */
 957                 if (first_seg == NULL) {
 958                         first_seg = rxm;
 959                         first_seg->pkt_len = data_len;
 960                         first_seg->nb_segs = 1;
 961                 } else {
 962                         first_seg->pkt_len += data_len;
 963                         first_seg->nb_segs++;
 964                         last_seg->next = rxm;
 965                 }
 966
 967                 /*
 968                  * If this is not the last buffer of the received packet,
 969                  * update the pointer to the last mbuf of the current scattered
 970                  * packet and continue to parse the RX ring.
 971                  */
 972                 if (! (staterr & E1000_RXD_STAT_EOP)) {
 973                         last_seg = rxm;
 974                         goto next_desc;
 975                 }
 976
 977                 /*
 978                  * This is the last buffer of the received packet.
 979                  * If the CRC is not stripped by the hardware:
 980                  *   - Subtract the CRC length from the total packet length.
 981                  *   - If the last buffer only contains the whole CRC or a part
 982                  *     of it, free the mbuf associated to the last buffer.
 983                  *     If part of the CRC is also contained in the previous
 984                  *     mbuf, subtract the length of that CRC part from the
 985                  *     data length of the previous mbuf.
 986                  */
 987                 rxm->next = NULL;
 988                 if (unlikely(rxq->crc_len > 0)) {
 989                         first_seg->pkt_len -= ETHER_CRC_LEN;
 990                         if (data_len <= ETHER_CRC_LEN) {
 991                                 rte_pktmbuf_free_seg(rxm);
 992                                 first_seg->nb_segs--;
 993                                 last_seg->data_len = (uint16_t)
 994                                         (last_seg->data_len -
 995                                          (ETHER_CRC_LEN - data_len));
 996                                 last_seg->next = NULL;
 997                         } else
 998                                 rxm->data_len =
 999                                         (uint16_t) (data_len - ETHER_CRC_LEN);
1000                 }
1001
1002                 /*
1003                  * Initialize the first mbuf of the returned packet:
1004                  *    - RX port identifier,
1005                  *    - hardware offload data, if any:
1006                  *      - RSS flag & hash,
1007                  *      - IP checksum flag,
1008                  *      - VLAN TCI, if any,
1009                  *      - error flags.
1010                  */
1011                 first_seg->port = rxq->port_id;
1012                 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1013
1014                 /*
1015                  * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1016                  * set in the pkt_flags field.
1017                  */
1018                 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1019                 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1020                 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1021                 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1022                 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1023                 first_seg->ol_flags = pkt_flags;
1024
1025                 /* Prefetch data of first segment, if configured to do so. */
1026                 rte_packet_prefetch((char *)first_seg->buf_addr +
1027                         first_seg->data_off);
1028
1029                 /*
1030                  * Store the mbuf address into the next entry of the array
1031                  * of returned packets.
1032                  */
1033                 rx_pkts[nb_rx++] = first_seg;
1034
1035                 /*
1036                  * Setup receipt context for a new packet.
1037                  */
1038                 first_seg = NULL;
1039         }
1040
1041         /*
1042          * Record index of the next RX descriptor to probe.
1043          */
1044         rxq->rx_tail = rx_id;
1045
1046         /*
1047          * Save receive context.
1048          */
1049         rxq->pkt_first_seg = first_seg;
1050         rxq->pkt_last_seg = last_seg;
1051
1052         /*
1053          * If the number of free RX descriptors is greater than the RX free
1054          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1055          * register.
1056          * Update the RDT with the value of the last processed RX descriptor
1057          * minus 1, to guarantee that the RDT register is never equal to the
1058          * RDH register, which creates a "full" ring situtation from the
1059          * hardware point of view...
1060          */
1061         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1062         if (nb_hold > rxq->rx_free_thresh) {
1063                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1064                            "nb_hold=%u nb_rx=%u\n",
1065                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1066                            (unsigned) rx_id, (unsigned) nb_hold,
1067                            (unsigned) nb_rx);
1068                 rx_id = (uint16_t) ((rx_id == 0) ?
1069                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
1070                 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1071                 nb_hold = 0;
1072         }
1073         rxq->nb_rx_hold = nb_hold;
1074         return (nb_rx);
1075 }
1076
1077 /*
1078  * Rings setup and release.
1079  *
1080  * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1081  * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
1082  * This will also optimize cache line size effect.
1083  * H/W supports up to cache line size 128.
1084  */
1085 #define IGB_ALIGN 128
1086
1087 /*
1088  * Maximum number of Ring Descriptors.
1089  *
1090  * Since RDLEN/TDLEN should be multiple of 128bytes, the number of ring
1091  * desscriptors should meet the following condition:
1092  *      (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0
1093  */
1094 #define IGB_MIN_RING_DESC 32
1095 #define IGB_MAX_RING_DESC 4096
1096
1097 static const struct rte_memzone *
1098 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1099                       uint16_t queue_id, uint32_t ring_size, int socket_id)
1100 {
1101         char z_name[RTE_MEMZONE_NAMESIZE];
1102         const struct rte_memzone *mz;
1103
1104         snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1105                         dev->driver->pci_drv.name, ring_name,
1106                                 dev->data->port_id, queue_id);
1107         mz = rte_memzone_lookup(z_name);
1108         if (mz)
1109                 return mz;
1110
1111 #ifdef RTE_LIBRTE_XEN_DOM0
1112         return rte_memzone_reserve_bounded(z_name, ring_size,
1113                         socket_id, 0, IGB_ALIGN, RTE_PGSIZE_2M);
1114 #else
1115         return rte_memzone_reserve_aligned(z_name, ring_size,
1116                         socket_id, 0, IGB_ALIGN);
1117 #endif
1118 }
1119
1120 static void
1121 igb_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1122 {
1123         unsigned i;
1124
1125         if (txq->sw_ring != NULL) {
1126                 for (i = 0; i < txq->nb_tx_desc; i++) {
1127                         if (txq->sw_ring[i].mbuf != NULL) {
1128                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1129                                 txq->sw_ring[i].mbuf = NULL;
1130                         }
1131                 }
1132         }
1133 }
1134
1135 static void
1136 igb_tx_queue_release(struct igb_tx_queue *txq)
1137 {
1138         if (txq != NULL) {
1139                 igb_tx_queue_release_mbufs(txq);
1140                 rte_free(txq->sw_ring);
1141                 rte_free(txq);
1142         }
1143 }
1144
1145 void
1146 eth_igb_tx_queue_release(void *txq)
1147 {
1148         igb_tx_queue_release(txq);
1149 }
1150
1151 static void
1152 igb_reset_tx_queue_stat(struct igb_tx_queue *txq)
1153 {
1154         txq->tx_head = 0;
1155         txq->tx_tail = 0;
1156         txq->ctx_curr = 0;
1157         memset((void*)&txq->ctx_cache, 0,
1158                 IGB_CTX_NUM * sizeof(struct igb_advctx_info));
1159 }
1160
1161 static void
1162 igb_reset_tx_queue(struct igb_tx_queue *txq, struct rte_eth_dev *dev)
1163 {
1164         static const union e1000_adv_tx_desc zeroed_desc = { .read = {
1165                         .buffer_addr = 0}};
1166         struct igb_tx_entry *txe = txq->sw_ring;
1167         uint16_t i, prev;
1168         struct e1000_hw *hw;
1169
1170         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1171         /* Zero out HW ring memory */
1172         for (i = 0; i < txq->nb_tx_desc; i++) {
1173                 txq->tx_ring[i] = zeroed_desc;
1174         }
1175
1176         /* Initialize ring entries */
1177         prev = (uint16_t)(txq->nb_tx_desc - 1);
1178         for (i = 0; i < txq->nb_tx_desc; i++) {
1179                 volatile union e1000_adv_tx_desc *txd = &(txq->tx_ring[i]);
1180
1181                 txd->wb.status = E1000_TXD_STAT_DD;
1182                 txe[i].mbuf = NULL;
1183                 txe[i].last_id = i;
1184                 txe[prev].next_id = i;
1185                 prev = i;
1186         }
1187
1188         txq->txd_type = E1000_ADVTXD_DTYP_DATA;
1189         /* 82575 specific, each tx queue will use 2 hw contexts */
1190         if (hw->mac.type == e1000_82575)
1191                 txq->ctx_start = txq->queue_id * IGB_CTX_NUM;
1192
1193         igb_reset_tx_queue_stat(txq);
1194 }
1195
1196 int
1197 eth_igb_tx_queue_setup(struct rte_eth_dev *dev,
1198                          uint16_t queue_idx,
1199                          uint16_t nb_desc,
1200                          unsigned int socket_id,
1201                          const struct rte_eth_txconf *tx_conf)
1202 {
1203         const struct rte_memzone *tz;
1204         struct igb_tx_queue *txq;
1205         struct e1000_hw     *hw;
1206         uint32_t size;
1207
1208         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1209
1210         /*
1211          * Validate number of transmit descriptors.
1212          * It must not exceed hardware maximum, and must be multiple
1213          * of IGB_ALIGN.
1214          */
1215         if (((nb_desc * sizeof(union e1000_adv_tx_desc)) % IGB_ALIGN) != 0 ||
1216             (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {
1217                 return -EINVAL;
1218         }
1219
1220         /*
1221          * The tx_free_thresh and tx_rs_thresh values are not used in the 1G
1222          * driver.
1223          */
1224         if (tx_conf->tx_free_thresh != 0)
1225                 RTE_LOG(WARNING, PMD,
1226                         "The tx_free_thresh parameter is not "
1227                         "used for the 1G driver.\n");
1228         if (tx_conf->tx_rs_thresh != 0)
1229                 RTE_LOG(WARNING, PMD,
1230                         "The tx_rs_thresh parameter is not "
1231                         "used for the 1G driver.\n");
1232         if (tx_conf->tx_thresh.wthresh == 0)
1233                 RTE_LOG(WARNING, PMD,
1234                         "To improve 1G driver performance, consider setting "
1235                         "the TX WTHRESH value to 4, 8, or 16.\n");
1236
1237         /* Free memory prior to re-allocation if needed */
1238         if (dev->data->tx_queues[queue_idx] != NULL) {
1239                 igb_tx_queue_release(dev->data->tx_queues[queue_idx]);
1240                 dev->data->tx_queues[queue_idx] = NULL;
1241         }
1242
1243         /* First allocate the tx queue data structure */
1244         txq = rte_zmalloc("ethdev TX queue", sizeof(struct igb_tx_queue),
1245                                                         CACHE_LINE_SIZE);
1246         if (txq == NULL)
1247                 return (-ENOMEM);
1248
1249         /*
1250          * Allocate TX ring hardware descriptors. A memzone large enough to
1251          * handle the maximum ring size is allocated in order to allow for
1252          * resizing in later calls to the queue setup function.
1253          */
1254         size = sizeof(union e1000_adv_tx_desc) * IGB_MAX_RING_DESC;
1255         tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1256                                         size, socket_id);
1257         if (tz == NULL) {
1258                 igb_tx_queue_release(txq);
1259                 return (-ENOMEM);
1260         }
1261
1262         txq->nb_tx_desc = nb_desc;
1263         txq->pthresh = tx_conf->tx_thresh.pthresh;
1264         txq->hthresh = tx_conf->tx_thresh.hthresh;
1265         txq->wthresh = tx_conf->tx_thresh.wthresh;
1266         if (txq->wthresh > 0 && hw->mac.type == e1000_82576)
1267                 txq->wthresh = 1;
1268         txq->queue_id = queue_idx;
1269         txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1270                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1271         txq->port_id = dev->data->port_id;
1272
1273         txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(txq->reg_idx));
1274 #ifndef RTE_LIBRTE_XEN_DOM0
1275         txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1276 #else
1277         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1278 #endif
1279          txq->tx_ring = (union e1000_adv_tx_desc *) tz->addr;
1280         /* Allocate software ring */
1281         txq->sw_ring = rte_zmalloc("txq->sw_ring",
1282                                    sizeof(struct igb_tx_entry) * nb_desc,
1283                                    CACHE_LINE_SIZE);
1284         if (txq->sw_ring == NULL) {
1285                 igb_tx_queue_release(txq);
1286                 return (-ENOMEM);
1287         }
1288         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1289                      txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1290
1291         igb_reset_tx_queue(txq, dev);
1292         dev->tx_pkt_burst = eth_igb_xmit_pkts;
1293         dev->data->tx_queues[queue_idx] = txq;
1294
1295         return (0);
1296 }
1297
1298 static void
1299 igb_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1300 {
1301         unsigned i;
1302
1303         if (rxq->sw_ring != NULL) {
1304                 for (i = 0; i < rxq->nb_rx_desc; i++) {
1305                         if (rxq->sw_ring[i].mbuf != NULL) {
1306                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1307                                 rxq->sw_ring[i].mbuf = NULL;
1308                         }
1309                 }
1310         }
1311 }
1312
1313 static void
1314 igb_rx_queue_release(struct igb_rx_queue *rxq)
1315 {
1316         if (rxq != NULL) {
1317                 igb_rx_queue_release_mbufs(rxq);
1318                 rte_free(rxq->sw_ring);
1319                 rte_free(rxq);
1320         }
1321 }
1322
1323 void
1324 eth_igb_rx_queue_release(void *rxq)
1325 {
1326         igb_rx_queue_release(rxq);
1327 }
1328
1329 static void
1330 igb_reset_rx_queue(struct igb_rx_queue *rxq)
1331 {
1332         static const union e1000_adv_rx_desc zeroed_desc = { .read = {
1333                         .pkt_addr = 0}};
1334         unsigned i;
1335
1336         /* Zero out HW ring memory */
1337         for (i = 0; i < rxq->nb_rx_desc; i++) {
1338                 rxq->rx_ring[i] = zeroed_desc;
1339         }
1340
1341         rxq->rx_tail = 0;
1342         rxq->pkt_first_seg = NULL;
1343         rxq->pkt_last_seg = NULL;
1344 }
1345
1346 int
1347 eth_igb_rx_queue_setup(struct rte_eth_dev *dev,
1348                          uint16_t queue_idx,
1349                          uint16_t nb_desc,
1350                          unsigned int socket_id,
1351                          const struct rte_eth_rxconf *rx_conf,
1352                          struct rte_mempool *mp)
1353 {
1354         const struct rte_memzone *rz;
1355         struct igb_rx_queue *rxq;
1356         struct e1000_hw     *hw;
1357         unsigned int size;
1358
1359         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1360
1361         /*
1362          * Validate number of receive descriptors.
1363          * It must not exceed hardware maximum, and must be multiple
1364          * of IGB_ALIGN.
1365          */
1366         if (((nb_desc * sizeof(union e1000_adv_rx_desc)) % IGB_ALIGN) != 0 ||
1367             (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {
1368                 return (-EINVAL);
1369         }
1370
1371         /* Free memory prior to re-allocation if needed */
1372         if (dev->data->rx_queues[queue_idx] != NULL) {
1373                 igb_rx_queue_release(dev->data->rx_queues[queue_idx]);
1374                 dev->data->rx_queues[queue_idx] = NULL;
1375         }
1376
1377         /* First allocate the RX queue data structure. */
1378         rxq = rte_zmalloc("ethdev RX queue", sizeof(struct igb_rx_queue),
1379                           CACHE_LINE_SIZE);
1380         if (rxq == NULL)
1381                 return (-ENOMEM);
1382         rxq->mb_pool = mp;
1383         rxq->nb_rx_desc = nb_desc;
1384         rxq->pthresh = rx_conf->rx_thresh.pthresh;
1385         rxq->hthresh = rx_conf->rx_thresh.hthresh;
1386         rxq->wthresh = rx_conf->rx_thresh.wthresh;
1387         if (rxq->wthresh > 0 && hw->mac.type == e1000_82576)
1388                 rxq->wthresh = 1;
1389         rxq->drop_en = rx_conf->rx_drop_en;
1390         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1391         rxq->queue_id = queue_idx;
1392         rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1393                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1394         rxq->port_id = dev->data->port_id;
1395         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
1396                                   ETHER_CRC_LEN);
1397
1398         /*
1399          *  Allocate RX ring hardware descriptors. A memzone large enough to
1400          *  handle the maximum ring size is allocated in order to allow for
1401          *  resizing in later calls to the queue setup function.
1402          */
1403         size = sizeof(union e1000_adv_rx_desc) * IGB_MAX_RING_DESC;
1404         rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx, size, socket_id);
1405         if (rz == NULL) {
1406                 igb_rx_queue_release(rxq);
1407                 return (-ENOMEM);
1408         }
1409         rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(rxq->reg_idx));
1410         rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(rxq->reg_idx));
1411 #ifndef RTE_LIBRTE_XEN_DOM0
1412         rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
1413 #else
1414         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1415 #endif
1416         rxq->rx_ring = (union e1000_adv_rx_desc *) rz->addr;
1417
1418         /* Allocate software ring. */
1419         rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1420                                    sizeof(struct igb_rx_entry) * nb_desc,
1421                                    CACHE_LINE_SIZE);
1422         if (rxq->sw_ring == NULL) {
1423                 igb_rx_queue_release(rxq);
1424                 return (-ENOMEM);
1425         }
1426         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1427                      rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1428
1429         dev->data->rx_queues[queue_idx] = rxq;
1430         igb_reset_rx_queue(rxq);
1431
1432         return 0;
1433 }
1434
1435 uint32_t
1436 eth_igb_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1437 {
1438 #define IGB_RXQ_SCAN_INTERVAL 4
1439         volatile union e1000_adv_rx_desc *rxdp;
1440         struct igb_rx_queue *rxq;
1441         uint32_t desc = 0;
1442
1443         if (rx_queue_id >= dev->data->nb_rx_queues) {
1444                 PMD_RX_LOG(ERR, "Invalid RX queue id=%d\n", rx_queue_id);
1445                 return 0;
1446         }
1447
1448         rxq = dev->data->rx_queues[rx_queue_id];
1449         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1450
1451         while ((desc < rxq->nb_rx_desc) &&
1452                 (rxdp->wb.upper.status_error & E1000_RXD_STAT_DD)) {
1453                 desc += IGB_RXQ_SCAN_INTERVAL;
1454                 rxdp += IGB_RXQ_SCAN_INTERVAL;
1455                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1456                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1457                                 desc - rxq->nb_rx_desc]);
1458         }
1459
1460         return 0;
1461 }
1462
1463 int
1464 eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset)
1465 {
1466         volatile union e1000_adv_rx_desc *rxdp;
1467         struct igb_rx_queue *rxq = rx_queue;
1468         uint32_t desc;
1469
1470         if (unlikely(offset >= rxq->nb_rx_desc))
1471                 return 0;
1472         desc = rxq->rx_tail + offset;
1473         if (desc >= rxq->nb_rx_desc)
1474                 desc -= rxq->nb_rx_desc;
1475
1476         rxdp = &rxq->rx_ring[desc];
1477         return !!(rxdp->wb.upper.status_error & E1000_RXD_STAT_DD);
1478 }
1479
1480 void
1481 igb_dev_clear_queues(struct rte_eth_dev *dev)
1482 {
1483         uint16_t i;
1484         struct igb_tx_queue *txq;
1485         struct igb_rx_queue *rxq;
1486
1487         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1488                 txq = dev->data->tx_queues[i];
1489                 if (txq != NULL) {
1490                         igb_tx_queue_release_mbufs(txq);
1491                         igb_reset_tx_queue(txq, dev);
1492                 }
1493         }
1494
1495         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1496                 rxq = dev->data->rx_queues[i];
1497                 if (rxq != NULL) {
1498                         igb_rx_queue_release_mbufs(rxq);
1499                         igb_reset_rx_queue(rxq);
1500                 }
1501         }
1502 }
1503
1504 /**
1505  * Receive Side Scaling (RSS).
1506  * See section 7.1.1.7 in the following document:
1507  *     "Intel 82576 GbE Controller Datasheet" - Revision 2.45 October 2009
1508  *
1509  * Principles:
1510  * The source and destination IP addresses of the IP header and the source and
1511  * destination ports of TCP/UDP headers, if any, of received packets are hashed
1512  * against a configurable random key to compute a 32-bit RSS hash result.
1513  * The seven (7) LSBs of the 32-bit hash result are used as an index into a
1514  * 128-entry redirection table (RETA).  Each entry of the RETA provides a 3-bit
1515  * RSS output index which is used as the RX queue index where to store the
1516  * received packets.
1517  * The following output is supplied in the RX write-back descriptor:
1518  *     - 32-bit result of the Microsoft RSS hash function,
1519  *     - 4-bit RSS type field.
1520  */
1521
1522 /*
1523  * RSS random key supplied in section 7.1.1.7.3 of the Intel 82576 datasheet.
1524  * Used as the default key.
1525  */
1526 static uint8_t rss_intel_key[40] = {
1527         0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
1528         0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
1529         0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
1530         0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
1531         0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
1532 };
1533
1534 static void
1535 igb_rss_disable(struct rte_eth_dev *dev)
1536 {
1537         struct e1000_hw *hw;
1538         uint32_t mrqc;
1539
1540         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1541         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1542         mrqc &= ~E1000_MRQC_ENABLE_MASK;
1543         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1544 }
1545
1546 static void
1547 igb_hw_rss_hash_set(struct e1000_hw *hw, struct rte_eth_rss_conf *rss_conf)
1548 {
1549         uint8_t  *hash_key;
1550         uint32_t rss_key;
1551         uint32_t mrqc;
1552         uint64_t rss_hf;
1553         uint16_t i;
1554
1555         hash_key = rss_conf->rss_key;
1556         if (hash_key != NULL) {
1557                 /* Fill in RSS hash key */
1558                 for (i = 0; i < 10; i++) {
1559                         rss_key  = hash_key[(i * 4)];
1560                         rss_key |= hash_key[(i * 4) + 1] << 8;
1561                         rss_key |= hash_key[(i * 4) + 2] << 16;
1562                         rss_key |= hash_key[(i * 4) + 3] << 24;
1563                         E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key);
1564                 }
1565         }
1566
1567         /* Set configured hashing protocols in MRQC register */
1568         rss_hf = rss_conf->rss_hf;
1569         mrqc = E1000_MRQC_ENABLE_RSS_4Q; /* RSS enabled. */
1570         if (rss_hf & ETH_RSS_IPV4)
1571                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4;
1572         if (rss_hf & ETH_RSS_IPV4_TCP)
1573                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_TCP;
1574         if (rss_hf & ETH_RSS_IPV6)
1575                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6;
1576         if (rss_hf & ETH_RSS_IPV6_EX)
1577                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_EX;
1578         if (rss_hf & ETH_RSS_IPV6_TCP)
1579                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP;
1580         if (rss_hf & ETH_RSS_IPV6_TCP_EX)
1581                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
1582         if (rss_hf & ETH_RSS_IPV4_UDP)
1583                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
1584         if (rss_hf & ETH_RSS_IPV6_UDP)
1585                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
1586         if (rss_hf & ETH_RSS_IPV6_UDP_EX)
1587                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP_EX;
1588         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1589 }
1590
1591 int
1592 eth_igb_rss_hash_update(struct rte_eth_dev *dev,
1593                         struct rte_eth_rss_conf *rss_conf)
1594 {
1595         struct e1000_hw *hw;
1596         uint32_t mrqc;
1597         uint64_t rss_hf;
1598
1599         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1600
1601         /*
1602          * Before changing anything, first check that the update RSS operation
1603          * does not attempt to disable RSS, if RSS was enabled at
1604          * initialization time, or does not attempt to enable RSS, if RSS was
1605          * disabled at initialization time.
1606          */
1607         rss_hf = rss_conf->rss_hf & IGB_RSS_OFFLOAD_ALL;
1608         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1609         if (!(mrqc & E1000_MRQC_ENABLE_MASK)) { /* RSS disabled */
1610                 if (rss_hf != 0) /* Enable RSS */
1611                         return -(EINVAL);
1612                 return 0; /* Nothing to do */
1613         }
1614         /* RSS enabled */
1615         if (rss_hf == 0) /* Disable RSS */
1616                 return -(EINVAL);
1617         igb_hw_rss_hash_set(hw, rss_conf);
1618         return 0;
1619 }
1620
1621 int eth_igb_rss_hash_conf_get(struct rte_eth_dev *dev,
1622                               struct rte_eth_rss_conf *rss_conf)
1623 {
1624         struct e1000_hw *hw;
1625         uint8_t *hash_key;
1626         uint32_t rss_key;
1627         uint32_t mrqc;
1628         uint64_t rss_hf;
1629         uint16_t i;
1630
1631         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1632         hash_key = rss_conf->rss_key;
1633         if (hash_key != NULL) {
1634                 /* Return RSS hash key */
1635                 for (i = 0; i < 10; i++) {
1636                         rss_key = E1000_READ_REG_ARRAY(hw, E1000_RSSRK(0), i);
1637                         hash_key[(i * 4)] = rss_key & 0x000000FF;
1638                         hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
1639                         hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
1640                         hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
1641                 }
1642         }
1643
1644         /* Get RSS functions configured in MRQC register */
1645         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1646         if ((mrqc & E1000_MRQC_ENABLE_RSS_4Q) == 0) { /* RSS is disabled */
1647                 rss_conf->rss_hf = 0;
1648                 return 0;
1649         }
1650         rss_hf = 0;
1651         if (mrqc & E1000_MRQC_RSS_FIELD_IPV4)
1652                 rss_hf |= ETH_RSS_IPV4;
1653         if (mrqc & E1000_MRQC_RSS_FIELD_IPV4_TCP)
1654                 rss_hf |= ETH_RSS_IPV4_TCP;
1655         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6)
1656                 rss_hf |= ETH_RSS_IPV6;
1657         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_EX)
1658                 rss_hf |= ETH_RSS_IPV6_EX;
1659         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP)
1660                 rss_hf |= ETH_RSS_IPV6_TCP;
1661         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP_EX)
1662                 rss_hf |= ETH_RSS_IPV6_TCP_EX;
1663         if (mrqc & E1000_MRQC_RSS_FIELD_IPV4_UDP)
1664                 rss_hf |= ETH_RSS_IPV4_UDP;
1665         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP)
1666                 rss_hf |= ETH_RSS_IPV6_UDP;
1667         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP_EX)
1668                 rss_hf |= ETH_RSS_IPV6_UDP_EX;
1669         rss_conf->rss_hf = rss_hf;
1670         return 0;
1671 }
1672
1673 static void
1674 igb_rss_configure(struct rte_eth_dev *dev)
1675 {
1676         struct rte_eth_rss_conf rss_conf;
1677         struct e1000_hw *hw;
1678         uint32_t shift;
1679         uint16_t i;
1680
1681         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1682
1683         /* Fill in redirection table. */
1684         shift = (hw->mac.type == e1000_82575) ? 6 : 0;
1685         for (i = 0; i < 128; i++) {
1686                 union e1000_reta {
1687                         uint32_t dword;
1688                         uint8_t  bytes[4];
1689                 } reta;
1690                 uint8_t q_idx;
1691
1692                 q_idx = (uint8_t) ((dev->data->nb_rx_queues > 1) ?
1693                                    i % dev->data->nb_rx_queues : 0);
1694                 reta.bytes[i & 3] = (uint8_t) (q_idx << shift);
1695                 if ((i & 3) == 3)
1696                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta.dword);
1697         }
1698
1699         /*
1700          * Configure the RSS key and the RSS protocols used to compute
1701          * the RSS hash of input packets.
1702          */
1703         rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
1704         if ((rss_conf.rss_hf & IGB_RSS_OFFLOAD_ALL) == 0) {
1705                 igb_rss_disable(dev);
1706                 return;
1707         }
1708         if (rss_conf.rss_key == NULL)
1709                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
1710         igb_hw_rss_hash_set(hw, &rss_conf);
1711 }
1712
1713 /*
1714  * Check if the mac type support VMDq or not.
1715  * Return 1 if it supports, otherwise, return 0.
1716  */
1717 static int
1718 igb_is_vmdq_supported(const struct rte_eth_dev *dev)
1719 {
1720         const struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1721
1722         switch (hw->mac.type) {
1723         case e1000_82576:
1724         case e1000_82580:
1725         case e1000_i350:
1726                 return 1;
1727         case e1000_82540:
1728         case e1000_82541:
1729         case e1000_82542:
1730         case e1000_82543:
1731         case e1000_82544:
1732         case e1000_82545:
1733         case e1000_82546:
1734         case e1000_82547:
1735         case e1000_82571:
1736         case e1000_82572:
1737         case e1000_82573:
1738         case e1000_82574:
1739         case e1000_82583:
1740         case e1000_i210:
1741         case e1000_i211:
1742         default:
1743                 PMD_INIT_LOG(ERR, "Cannot support VMDq feature\n");
1744                 return 0;
1745         }
1746 }
1747
1748 static int
1749 igb_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
1750 {
1751         struct rte_eth_vmdq_rx_conf *cfg;
1752         struct e1000_hw *hw;
1753         uint32_t mrqc, vt_ctl, vmolr, rctl;
1754         int i;
1755
1756         PMD_INIT_LOG(DEBUG, ">>");
1757         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1758         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1759
1760         /* Check if mac type can support VMDq, return value of 0 means NOT support */
1761         if (igb_is_vmdq_supported(dev) == 0)
1762                 return -1;
1763
1764         igb_rss_disable(dev);
1765
1766         /* RCTL: eanble VLAN filter */
1767         rctl = E1000_READ_REG(hw, E1000_RCTL);
1768         rctl |= E1000_RCTL_VFE;
1769         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1770
1771         /* MRQC: enable vmdq */
1772         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1773         mrqc |= E1000_MRQC_ENABLE_VMDQ;
1774         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1775
1776         /* VTCTL:  pool selection according to VLAN tag */
1777         vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
1778         if (cfg->enable_default_pool)
1779                 vt_ctl |= (cfg->default_pool << E1000_VT_CTL_DEFAULT_POOL_SHIFT);
1780         vt_ctl |= E1000_VT_CTL_IGNORE_MAC;
1781         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
1782
1783         /*
1784          * VMOLR: set STRVLAN as 1 if IGMAC in VTCTL is set as 1
1785          * Both 82576 and 82580 support it
1786          */
1787         if (hw->mac.type != e1000_i350) {
1788                 for (i = 0; i < E1000_VMOLR_SIZE; i++) {
1789                         vmolr = E1000_READ_REG(hw, E1000_VMOLR(i));
1790                         vmolr |= E1000_VMOLR_STRVLAN;
1791                         E1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);
1792                 }
1793         }
1794
1795         /* VFTA - enable all vlan filters */
1796         for (i = 0; i < IGB_VFTA_SIZE; i++)
1797                 E1000_WRITE_REG(hw, (E1000_VFTA+(i*4)), UINT32_MAX);
1798
1799         /* VFRE: 8 pools enabling for rx, both 82576 and i350 support it */
1800         if (hw->mac.type != e1000_82580)
1801                 E1000_WRITE_REG(hw, E1000_VFRE, E1000_MBVFICR_VFREQ_MASK);
1802
1803         /*
1804          * RAH/RAL - allow pools to read specific mac addresses
1805          * In this case, all pools should be able to read from mac addr 0
1806          */
1807         E1000_WRITE_REG(hw, E1000_RAH(0), (E1000_RAH_AV | UINT16_MAX));
1808         E1000_WRITE_REG(hw, E1000_RAL(0), UINT32_MAX);
1809
1810         /* VLVF: set up filters for vlan tags as configured */
1811         for (i = 0; i < cfg->nb_pool_maps; i++) {
1812                 /* set vlan id in VF register and set the valid bit */
1813                 E1000_WRITE_REG(hw, E1000_VLVF(i), (E1000_VLVF_VLANID_ENABLE | \
1814                         (cfg->pool_map[i].vlan_id & ETH_VLAN_ID_MAX) | \
1815                         ((cfg->pool_map[i].pools << E1000_VLVF_POOLSEL_SHIFT ) & \
1816                         E1000_VLVF_POOLSEL_MASK)));
1817         }
1818
1819         E1000_WRITE_FLUSH(hw);
1820
1821         return 0;
1822 }
1823
1824
1825 /*********************************************************************
1826  *
1827  *  Enable receive unit.
1828  *
1829  **********************************************************************/
1830
1831 static int
1832 igb_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
1833 {
1834         struct igb_rx_entry *rxe = rxq->sw_ring;
1835         uint64_t dma_addr;
1836         unsigned i;
1837
1838         /* Initialize software ring entries. */
1839         for (i = 0; i < rxq->nb_rx_desc; i++) {
1840                 volatile union e1000_adv_rx_desc *rxd;
1841                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
1842
1843                 if (mbuf == NULL) {
1844                         PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
1845                                 "queue_id=%hu\n", rxq->queue_id);
1846                         return (-ENOMEM);
1847                 }
1848                 dma_addr =
1849                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
1850                 rxd = &rxq->rx_ring[i];
1851                 rxd->read.hdr_addr = dma_addr;
1852                 rxd->read.pkt_addr = dma_addr;
1853                 rxe[i].mbuf = mbuf;
1854         }
1855
1856         return 0;
1857 }
1858
1859 #define E1000_MRQC_DEF_Q_SHIFT               (3)
1860 static int
1861 igb_dev_mq_rx_configure(struct rte_eth_dev *dev)
1862 {
1863         struct e1000_hw *hw =
1864                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1865         uint32_t mrqc;
1866
1867         if (RTE_ETH_DEV_SRIOV(dev).active == ETH_8_POOLS) {
1868                 /*
1869                  * SRIOV active scheme
1870                  * FIXME if support RSS together with VMDq & SRIOV
1871                  */
1872                 mrqc = E1000_MRQC_ENABLE_VMDQ;
1873                 /* 011b Def_Q ignore, according to VT_CTL.DEF_PL */
1874                 mrqc |= 0x3 << E1000_MRQC_DEF_Q_SHIFT;
1875                 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1876         } else if(RTE_ETH_DEV_SRIOV(dev).active == 0) {
1877                 /*
1878                  * SRIOV inactive scheme
1879                  */
1880                 switch (dev->data->dev_conf.rxmode.mq_mode) {
1881                         case ETH_MQ_RX_RSS:
1882                                 igb_rss_configure(dev);
1883                                 break;
1884                         case ETH_MQ_RX_VMDQ_ONLY:
1885                                 /*Configure general VMDQ only RX parameters*/
1886                                 igb_vmdq_rx_hw_configure(dev);
1887                                 break;
1888                         case ETH_MQ_RX_NONE:
1889                                 /* if mq_mode is none, disable rss mode.*/
1890                         default:
1891                                 igb_rss_disable(dev);
1892                                 break;
1893                 }
1894         }
1895
1896         return 0;
1897 }
1898
1899 int
1900 eth_igb_rx_init(struct rte_eth_dev *dev)
1901 {
1902         struct e1000_hw     *hw;
1903         struct igb_rx_queue *rxq;
1904         struct rte_pktmbuf_pool_private *mbp_priv;
1905         uint32_t rctl;
1906         uint32_t rxcsum;
1907         uint32_t srrctl;
1908         uint16_t buf_size;
1909         uint16_t rctl_bsize;
1910         uint16_t i;
1911         int ret;
1912
1913         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1914         srrctl = 0;
1915
1916         /*
1917          * Make sure receives are disabled while setting
1918          * up the descriptor ring.
1919          */
1920         rctl = E1000_READ_REG(hw, E1000_RCTL);
1921         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
1922
1923         /*
1924          * Configure support of jumbo frames, if any.
1925          */
1926         if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
1927                 rctl |= E1000_RCTL_LPE;
1928
1929                 /*
1930                  * Set maximum packet length by default, and might be updated
1931                  * together with enabling/disabling dual VLAN.
1932                  */
1933                 E1000_WRITE_REG(hw, E1000_RLPML,
1934                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
1935                                                 VLAN_TAG_SIZE);
1936         } else
1937                 rctl &= ~E1000_RCTL_LPE;
1938
1939         /* Configure and enable each RX queue. */
1940         rctl_bsize = 0;
1941         dev->rx_pkt_burst = eth_igb_recv_pkts;
1942         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1943                 uint64_t bus_addr;
1944                 uint32_t rxdctl;
1945
1946                 rxq = dev->data->rx_queues[i];
1947
1948                 /* Allocate buffers for descriptor rings and set up queue */
1949                 ret = igb_alloc_rx_queue_mbufs(rxq);
1950                 if (ret)
1951                         return ret;
1952
1953                 /*
1954                  * Reset crc_len in case it was changed after queue setup by a
1955                  *  call to configure
1956                  */
1957                 rxq->crc_len =
1958                         (uint8_t)(dev->data->dev_conf.rxmode.hw_strip_crc ?
1959                                                         0 : ETHER_CRC_LEN);
1960
1961                 bus_addr = rxq->rx_ring_phys_addr;
1962                 E1000_WRITE_REG(hw, E1000_RDLEN(rxq->reg_idx),
1963                                 rxq->nb_rx_desc *
1964                                 sizeof(union e1000_adv_rx_desc));
1965                 E1000_WRITE_REG(hw, E1000_RDBAH(rxq->reg_idx),
1966                                 (uint32_t)(bus_addr >> 32));
1967                 E1000_WRITE_REG(hw, E1000_RDBAL(rxq->reg_idx), (uint32_t)bus_addr);
1968
1969                 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1970
1971                 /*
1972                  * Configure RX buffer size.
1973                  */
1974                 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
1975                 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
1976                                        RTE_PKTMBUF_HEADROOM);
1977                 if (buf_size >= 1024) {
1978                         /*
1979                          * Configure the BSIZEPACKET field of the SRRCTL
1980                          * register of the queue.
1981                          * Value is in 1 KB resolution, from 1 KB to 127 KB.
1982                          * If this field is equal to 0b, then RCTL.BSIZE
1983                          * determines the RX packet buffer size.
1984                          */
1985                         srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
1986                                    E1000_SRRCTL_BSIZEPKT_MASK);
1987                         buf_size = (uint16_t) ((srrctl &
1988                                                 E1000_SRRCTL_BSIZEPKT_MASK) <<
1989                                                E1000_SRRCTL_BSIZEPKT_SHIFT);
1990
1991                         /* It adds dual VLAN length for supporting dual VLAN */
1992                         if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
1993                                                 2 * VLAN_TAG_SIZE) > buf_size){
1994                                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
1995                                 dev->data->scattered_rx = 1;
1996                         }
1997                 } else {
1998                         /*
1999                          * Use BSIZE field of the device RCTL register.
2000                          */
2001                         if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
2002                                 rctl_bsize = buf_size;
2003                         dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2004                         dev->data->scattered_rx = 1;
2005                 }
2006
2007                 /* Set if packets are dropped when no descriptors available */
2008                 if (rxq->drop_en)
2009                         srrctl |= E1000_SRRCTL_DROP_EN;
2010
2011                 E1000_WRITE_REG(hw, E1000_SRRCTL(rxq->reg_idx), srrctl);
2012
2013                 /* Enable this RX queue. */
2014                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rxq->reg_idx));
2015                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2016                 rxdctl &= 0xFFF00000;
2017                 rxdctl |= (rxq->pthresh & 0x1F);
2018                 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
2019                 rxdctl |= ((rxq->wthresh & 0x1F) << 16);
2020                 E1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl);
2021         }
2022
2023         if (dev->data->dev_conf.rxmode.enable_scatter) {
2024                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2025                 dev->data->scattered_rx = 1;
2026         }
2027
2028         /*
2029          * Setup BSIZE field of RCTL register, if needed.
2030          * Buffer sizes >= 1024 are not [supposed to be] setup in the RCTL
2031          * register, since the code above configures the SRRCTL register of
2032          * the RX queue in such a case.
2033          * All configurable sizes are:
2034          * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
2035          *  8192: rctl |= (E1000_RCTL_SZ_8192  | E1000_RCTL_BSEX);
2036          *  4096: rctl |= (E1000_RCTL_SZ_4096  | E1000_RCTL_BSEX);
2037          *  2048: rctl |= E1000_RCTL_SZ_2048;
2038          *  1024: rctl |= E1000_RCTL_SZ_1024;
2039          *   512: rctl |= E1000_RCTL_SZ_512;
2040          *   256: rctl |= E1000_RCTL_SZ_256;
2041          */
2042         if (rctl_bsize > 0) {
2043                 if (rctl_bsize >= 512) /* 512 <= buf_size < 1024 - use 512 */
2044                         rctl |= E1000_RCTL_SZ_512;
2045                 else /* 256 <= buf_size < 512 - use 256 */
2046                         rctl |= E1000_RCTL_SZ_256;
2047         }
2048
2049         /*
2050          * Configure RSS if device configured with multiple RX queues.
2051          */
2052         igb_dev_mq_rx_configure(dev);
2053
2054         /* Update the rctl since igb_dev_mq_rx_configure may change its value */
2055         rctl |= E1000_READ_REG(hw, E1000_RCTL);
2056
2057         /*
2058          * Setup the Checksum Register.
2059          * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
2060          */
2061         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2062         rxcsum |= E1000_RXCSUM_PCSD;
2063
2064         /* Enable both L3/L4 rx checksum offload */
2065         if (dev->data->dev_conf.rxmode.hw_ip_checksum)
2066                 rxcsum |= (E1000_RXCSUM_IPOFL  | E1000_RXCSUM_TUOFL);
2067         else
2068                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
2069         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2070
2071         /* Setup the Receive Control Register. */
2072         if (dev->data->dev_conf.rxmode.hw_strip_crc) {
2073                 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
2074
2075                 /* set STRCRC bit in all queues */
2076                 if (hw->mac.type == e1000_i350 ||
2077                     hw->mac.type == e1000_i210 ||
2078                     hw->mac.type == e1000_i211 ||
2079                     hw->mac.type == e1000_i354) {
2080                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2081                                 rxq = dev->data->rx_queues[i];
2082                                 uint32_t dvmolr = E1000_READ_REG(hw,
2083                                         E1000_DVMOLR(rxq->reg_idx));
2084                                 dvmolr |= E1000_DVMOLR_STRCRC;
2085                                 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
2086                         }
2087                 }
2088         } else {
2089                 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
2090
2091                 /* clear STRCRC bit in all queues */
2092                 if (hw->mac.type == e1000_i350 ||
2093                     hw->mac.type == e1000_i210 ||
2094                     hw->mac.type == e1000_i211 ||
2095                     hw->mac.type == e1000_i354) {
2096                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2097                                 rxq = dev->data->rx_queues[i];
2098                                 uint32_t dvmolr = E1000_READ_REG(hw,
2099                                         E1000_DVMOLR(rxq->reg_idx));
2100                                 dvmolr &= ~E1000_DVMOLR_STRCRC;
2101                                 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
2102                         }
2103                 }
2104         }
2105
2106         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2107         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2108                 E1000_RCTL_RDMTS_HALF |
2109                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2110
2111         /* Make sure VLAN Filters are off. */
2112         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_VMDQ_ONLY)
2113                 rctl &= ~E1000_RCTL_VFE;
2114         /* Don't store bad packets. */
2115         rctl &= ~E1000_RCTL_SBP;
2116
2117         /* Enable Receives. */
2118         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2119
2120         /*
2121          * Setup the HW Rx Head and Tail Descriptor Pointers.
2122          * This needs to be done after enable.
2123          */
2124         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2125                 rxq = dev->data->rx_queues[i];
2126                 E1000_WRITE_REG(hw, E1000_RDH(rxq->reg_idx), 0);
2127                 E1000_WRITE_REG(hw, E1000_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
2128         }
2129
2130         return 0;
2131 }
2132
2133 /*********************************************************************
2134  *
2135  *  Enable transmit unit.
2136  *
2137  **********************************************************************/
2138 void
2139 eth_igb_tx_init(struct rte_eth_dev *dev)
2140 {
2141         struct e1000_hw     *hw;
2142         struct igb_tx_queue *txq;
2143         uint32_t tctl;
2144         uint32_t txdctl;
2145         uint16_t i;
2146
2147         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148
2149         /* Setup the Base and Length of the Tx Descriptor Rings. */
2150         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2151                 uint64_t bus_addr;
2152                 txq = dev->data->tx_queues[i];
2153                 bus_addr = txq->tx_ring_phys_addr;
2154
2155                 E1000_WRITE_REG(hw, E1000_TDLEN(txq->reg_idx),
2156                                 txq->nb_tx_desc *
2157                                 sizeof(union e1000_adv_tx_desc));
2158                 E1000_WRITE_REG(hw, E1000_TDBAH(txq->reg_idx),
2159                                 (uint32_t)(bus_addr >> 32));
2160                 E1000_WRITE_REG(hw, E1000_TDBAL(txq->reg_idx), (uint32_t)bus_addr);
2161
2162                 /* Setup the HW Tx Head and Tail descriptor pointers. */
2163                 E1000_WRITE_REG(hw, E1000_TDT(txq->reg_idx), 0);
2164                 E1000_WRITE_REG(hw, E1000_TDH(txq->reg_idx), 0);
2165
2166                 /* Setup Transmit threshold registers. */
2167                 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(txq->reg_idx));
2168                 txdctl |= txq->pthresh & 0x1F;
2169                 txdctl |= ((txq->hthresh & 0x1F) << 8);
2170                 txdctl |= ((txq->wthresh & 0x1F) << 16);
2171                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2172                 E1000_WRITE_REG(hw, E1000_TXDCTL(txq->reg_idx), txdctl);
2173         }
2174
2175         /* Program the Transmit Control Register. */
2176         tctl = E1000_READ_REG(hw, E1000_TCTL);
2177         tctl &= ~E1000_TCTL_CT;
2178         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2179                  (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2180
2181         e1000_config_collision_dist(hw);
2182
2183         /* This write will effectively turn on the transmit unit. */
2184         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2185 }
2186
2187 /*********************************************************************
2188  *
2189  *  Enable VF receive unit.
2190  *
2191  **********************************************************************/
2192 int
2193 eth_igbvf_rx_init(struct rte_eth_dev *dev)
2194 {
2195         struct e1000_hw     *hw;
2196         struct igb_rx_queue *rxq;
2197         struct rte_pktmbuf_pool_private *mbp_priv;
2198         uint32_t srrctl;
2199         uint16_t buf_size;
2200         uint16_t rctl_bsize;
2201         uint16_t i;
2202         int ret;
2203
2204         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2205
2206         /* setup MTU */
2207         e1000_rlpml_set_vf(hw,
2208                 (uint16_t)(dev->data->dev_conf.rxmode.max_rx_pkt_len +
2209                 VLAN_TAG_SIZE));
2210
2211         /* Configure and enable each RX queue. */
2212         rctl_bsize = 0;
2213         dev->rx_pkt_burst = eth_igb_recv_pkts;
2214         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2215                 uint64_t bus_addr;
2216                 uint32_t rxdctl;
2217
2218                 rxq = dev->data->rx_queues[i];
2219
2220                 /* Allocate buffers for descriptor rings and set up queue */
2221                 ret = igb_alloc_rx_queue_mbufs(rxq);
2222                 if (ret)
2223                         return ret;
2224
2225                 bus_addr = rxq->rx_ring_phys_addr;
2226                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2227                                 rxq->nb_rx_desc *
2228                                 sizeof(union e1000_adv_rx_desc));
2229                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2230                                 (uint32_t)(bus_addr >> 32));
2231                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
2232
2233                 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2234
2235                 /*
2236                  * Configure RX buffer size.
2237                  */
2238                 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
2239                 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
2240                                        RTE_PKTMBUF_HEADROOM);
2241                 if (buf_size >= 1024) {
2242                         /*
2243                          * Configure the BSIZEPACKET field of the SRRCTL
2244                          * register of the queue.
2245                          * Value is in 1 KB resolution, from 1 KB to 127 KB.
2246                          * If this field is equal to 0b, then RCTL.BSIZE
2247                          * determines the RX packet buffer size.
2248                          */
2249                         srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
2250                                    E1000_SRRCTL_BSIZEPKT_MASK);
2251                         buf_size = (uint16_t) ((srrctl &
2252                                                 E1000_SRRCTL_BSIZEPKT_MASK) <<
2253                                                E1000_SRRCTL_BSIZEPKT_SHIFT);
2254
2255                         /* It adds dual VLAN length for supporting dual VLAN */
2256                         if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
2257                                                 2 * VLAN_TAG_SIZE) > buf_size){
2258                                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2259                                 dev->data->scattered_rx = 1;
2260                         }
2261                 } else {
2262                         /*
2263                          * Use BSIZE field of the device RCTL register.
2264                          */
2265                         if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
2266                                 rctl_bsize = buf_size;
2267                         dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2268                         dev->data->scattered_rx = 1;
2269                 }
2270
2271                 /* Set if packets are dropped when no descriptors available */
2272                 if (rxq->drop_en)
2273                         srrctl |= E1000_SRRCTL_DROP_EN;
2274
2275                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2276
2277                 /* Enable this RX queue. */
2278                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2279                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2280                 rxdctl &= 0xFFF00000;
2281                 rxdctl |= (rxq->pthresh & 0x1F);
2282                 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
2283                 if (hw->mac.type == e1000_vfadapt) {
2284                         /*
2285                          * Workaround of 82576 VF Erratum
2286                          * force set WTHRESH to 1
2287                          * to avoid Write-Back not triggered sometimes
2288                          */
2289                         rxdctl |= 0x10000;
2290                         PMD_INIT_LOG(DEBUG, "Force set RX WTHRESH to 1 !\n");
2291                 }
2292                 else
2293                         rxdctl |= ((rxq->wthresh & 0x1F) << 16);
2294                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2295         }
2296
2297         if (dev->data->dev_conf.rxmode.enable_scatter) {
2298                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2299                 dev->data->scattered_rx = 1;
2300         }
2301
2302         /*
2303          * Setup the HW Rx Head and Tail Descriptor Pointers.
2304          * This needs to be done after enable.
2305          */
2306         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2307                 rxq = dev->data->rx_queues[i];
2308                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2309                 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
2310         }
2311
2312         return 0;
2313 }
2314
2315 /*********************************************************************
2316  *
2317  *  Enable VF transmit unit.
2318  *
2319  **********************************************************************/
2320 void
2321 eth_igbvf_tx_init(struct rte_eth_dev *dev)
2322 {
2323         struct e1000_hw     *hw;
2324         struct igb_tx_queue *txq;
2325         uint32_t txdctl;
2326         uint16_t i;
2327
2328         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2329
2330         /* Setup the Base and Length of the Tx Descriptor Rings. */
2331         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2332                 uint64_t bus_addr;
2333
2334                 txq = dev->data->tx_queues[i];
2335                 bus_addr = txq->tx_ring_phys_addr;
2336                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2337                                 txq->nb_tx_desc *
2338                                 sizeof(union e1000_adv_tx_desc));
2339                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2340                                 (uint32_t)(bus_addr >> 32));
2341                 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
2342
2343                 /* Setup the HW Tx Head and Tail descriptor pointers. */
2344                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2345                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2346
2347                 /* Setup Transmit threshold registers. */
2348                 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
2349                 txdctl |= txq->pthresh & 0x1F;
2350                 txdctl |= ((txq->hthresh & 0x1F) << 8);
2351                 if (hw->mac.type == e1000_82576) {
2352                         /*
2353                          * Workaround of 82576 VF Erratum
2354                          * force set WTHRESH to 1
2355                          * to avoid Write-Back not triggered sometimes
2356                          */
2357                         txdctl |= 0x10000;
2358                         PMD_INIT_LOG(DEBUG, "Force set TX WTHRESH to 1 !\n");
2359                 }
2360                 else
2361                         txdctl |= ((txq->wthresh & 0x1F) << 16);
2362                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2363                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2364         }
2365
2366 }
2367