1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 #ifndef _I40E_ADMINQ_CMD_H_
35 #define _I40E_ADMINQ_CMD_H_
37 /* This header file defines the i40e Admin Queue commands and is shared between
38 * i40e Firmware and Software.
40 * This file needs to comply with the Linux Kernel coding style.
43 #define I40E_FW_API_VERSION_MAJOR 0x0001
44 #define I40E_FW_API_VERSION_MINOR 0x0002
70 /* Flags sub-structure
71 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
72 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
75 /* command flags and offsets*/
76 #define I40E_AQ_FLAG_DD_SHIFT 0
77 #define I40E_AQ_FLAG_CMP_SHIFT 1
78 #define I40E_AQ_FLAG_ERR_SHIFT 2
79 #define I40E_AQ_FLAG_VFE_SHIFT 3
80 #define I40E_AQ_FLAG_LB_SHIFT 9
81 #define I40E_AQ_FLAG_RD_SHIFT 10
82 #define I40E_AQ_FLAG_VFC_SHIFT 11
83 #define I40E_AQ_FLAG_BUF_SHIFT 12
84 #define I40E_AQ_FLAG_SI_SHIFT 13
85 #define I40E_AQ_FLAG_EI_SHIFT 14
86 #define I40E_AQ_FLAG_FE_SHIFT 15
88 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
89 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
90 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
91 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
92 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
93 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
94 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
95 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
96 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
97 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
98 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
101 enum i40e_admin_queue_err {
102 I40E_AQ_RC_OK = 0, /* success */
103 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
104 I40E_AQ_RC_ENOENT = 2, /* No such element */
105 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
106 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
107 I40E_AQ_RC_EIO = 5, /* I/O error */
108 I40E_AQ_RC_ENXIO = 6, /* No such resource */
109 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
110 I40E_AQ_RC_EAGAIN = 8, /* Try again */
111 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
112 I40E_AQ_RC_EACCES = 10, /* Permission denied */
113 I40E_AQ_RC_EFAULT = 11, /* Bad address */
114 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
115 I40E_AQ_RC_EEXIST = 13, /* object already exists */
116 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
117 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
118 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
119 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
120 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
121 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
122 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
123 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
124 I40E_AQ_RC_EFBIG = 22, /* File too large */
127 /* Admin Queue command opcodes */
128 enum i40e_admin_queue_opc {
130 i40e_aqc_opc_get_version = 0x0001,
131 i40e_aqc_opc_driver_version = 0x0002,
132 i40e_aqc_opc_queue_shutdown = 0x0003,
133 i40e_aqc_opc_set_pf_context = 0x0004,
135 /* resource ownership */
136 i40e_aqc_opc_request_resource = 0x0008,
137 i40e_aqc_opc_release_resource = 0x0009,
139 i40e_aqc_opc_list_func_capabilities = 0x000A,
140 i40e_aqc_opc_list_dev_capabilities = 0x000B,
142 i40e_aqc_opc_set_cppm_configuration = 0x0103,
143 i40e_aqc_opc_set_arp_proxy_entry = 0x0104,
144 i40e_aqc_opc_set_ns_proxy_entry = 0x0105,
147 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */
148 i40e_aqc_opc_mac_address_read = 0x0107,
149 i40e_aqc_opc_mac_address_write = 0x0108,
152 i40e_aqc_opc_clear_pxe_mode = 0x0110,
154 /* internal switch commands */
155 i40e_aqc_opc_get_switch_config = 0x0200,
156 i40e_aqc_opc_add_statistics = 0x0201,
157 i40e_aqc_opc_remove_statistics = 0x0202,
158 i40e_aqc_opc_set_port_parameters = 0x0203,
159 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
161 i40e_aqc_opc_add_vsi = 0x0210,
162 i40e_aqc_opc_update_vsi_parameters = 0x0211,
163 i40e_aqc_opc_get_vsi_parameters = 0x0212,
165 i40e_aqc_opc_add_pv = 0x0220,
166 i40e_aqc_opc_update_pv_parameters = 0x0221,
167 i40e_aqc_opc_get_pv_parameters = 0x0222,
169 i40e_aqc_opc_add_veb = 0x0230,
170 i40e_aqc_opc_update_veb_parameters = 0x0231,
171 i40e_aqc_opc_get_veb_parameters = 0x0232,
173 i40e_aqc_opc_delete_element = 0x0243,
175 i40e_aqc_opc_add_macvlan = 0x0250,
176 i40e_aqc_opc_remove_macvlan = 0x0251,
177 i40e_aqc_opc_add_vlan = 0x0252,
178 i40e_aqc_opc_remove_vlan = 0x0253,
179 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
180 i40e_aqc_opc_add_tag = 0x0255,
181 i40e_aqc_opc_remove_tag = 0x0256,
182 i40e_aqc_opc_add_multicast_etag = 0x0257,
183 i40e_aqc_opc_remove_multicast_etag = 0x0258,
184 i40e_aqc_opc_update_tag = 0x0259,
185 i40e_aqc_opc_add_control_packet_filter = 0x025A,
186 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
187 i40e_aqc_opc_add_cloud_filters = 0x025C,
188 i40e_aqc_opc_remove_cloud_filters = 0x025D,
190 i40e_aqc_opc_add_mirror_rule = 0x0260,
191 i40e_aqc_opc_delete_mirror_rule = 0x0261,
194 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
195 i40e_aqc_opc_dcb_updated = 0x0302,
198 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
199 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
200 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
201 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
202 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
203 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
205 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
206 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
207 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
208 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
209 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
210 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
211 i40e_aqc_opc_query_port_ets_config = 0x0419,
212 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
213 i40e_aqc_opc_suspend_port_tx = 0x041B,
214 i40e_aqc_opc_resume_port_tx = 0x041C,
215 i40e_aqc_opc_configure_partition_bw = 0x041D,
218 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
219 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
222 i40e_aqc_opc_get_phy_abilities = 0x0600,
223 i40e_aqc_opc_set_phy_config = 0x0601,
224 i40e_aqc_opc_set_mac_config = 0x0603,
225 i40e_aqc_opc_set_link_restart_an = 0x0605,
226 i40e_aqc_opc_get_link_status = 0x0607,
227 i40e_aqc_opc_set_phy_int_mask = 0x0613,
228 i40e_aqc_opc_get_local_advt_reg = 0x0614,
229 i40e_aqc_opc_set_local_advt_reg = 0x0615,
230 i40e_aqc_opc_get_partner_advt = 0x0616,
231 i40e_aqc_opc_set_lb_modes = 0x0618,
232 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
233 i40e_aqc_opc_set_phy_debug = 0x0622,
234 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
237 i40e_aqc_opc_nvm_read = 0x0701,
238 i40e_aqc_opc_nvm_erase = 0x0702,
239 i40e_aqc_opc_nvm_update = 0x0703,
240 i40e_aqc_opc_nvm_config_read = 0x0704,
241 i40e_aqc_opc_nvm_config_write = 0x0705,
243 /* virtualization commands */
244 i40e_aqc_opc_send_msg_to_pf = 0x0801,
245 i40e_aqc_opc_send_msg_to_vf = 0x0802,
246 i40e_aqc_opc_send_msg_to_peer = 0x0803,
248 /* alternate structure */
249 i40e_aqc_opc_alternate_write = 0x0900,
250 i40e_aqc_opc_alternate_write_indirect = 0x0901,
251 i40e_aqc_opc_alternate_read = 0x0902,
252 i40e_aqc_opc_alternate_read_indirect = 0x0903,
253 i40e_aqc_opc_alternate_write_done = 0x0904,
254 i40e_aqc_opc_alternate_set_mode = 0x0905,
255 i40e_aqc_opc_alternate_clear_port = 0x0906,
258 i40e_aqc_opc_lldp_get_mib = 0x0A00,
259 i40e_aqc_opc_lldp_update_mib = 0x0A01,
260 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
261 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
262 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
263 i40e_aqc_opc_lldp_stop = 0x0A05,
264 i40e_aqc_opc_lldp_start = 0x0A06,
265 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
266 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
267 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
269 /* Tunnel commands */
270 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
271 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
272 i40e_aqc_opc_tunnel_key_structure = 0x0B10,
275 i40e_aqc_opc_event_lan_overflow = 0x1001,
278 i40e_aqc_opc_oem_parameter_change = 0xFE00,
279 i40e_aqc_opc_oem_device_status_change = 0xFE01,
280 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
281 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
284 i40e_aqc_opc_debug_get_deviceid = 0xFF00,
285 i40e_aqc_opc_debug_set_mode = 0xFF01,
286 i40e_aqc_opc_debug_read_reg = 0xFF03,
287 i40e_aqc_opc_debug_write_reg = 0xFF04,
288 i40e_aqc_opc_debug_modify_reg = 0xFF07,
289 i40e_aqc_opc_debug_dump_internals = 0xFF08,
292 /* command structures and indirect data structures */
294 /* Structure naming conventions:
295 * - no suffix for direct command descriptor structures
296 * - _data for indirect sent data
297 * - _resp for indirect return data (data which is both will use _data)
298 * - _completion for direct return data
299 * - _element_ for repeated elements (may also be _data or _resp)
301 * Command structures are expected to overlay the params.raw member of the basic
302 * descriptor, and as such cannot exceed 16 bytes in length.
305 /* This macro is used to generate a compilation error if a structure
306 * is not exactly the correct length. It gives a divide by zero error if the
307 * structure is not of the correct size, otherwise it creates an enum that is
310 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
311 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
313 /* This macro is used extensively to ensure that command structures are 16
314 * bytes in length as they have to map to the raw array of that size.
316 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
318 /* internal (0x00XX) commands */
320 /* Get version (direct 0x0001) */
321 struct i40e_aqc_get_version {
330 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
332 /* Send driver version (indirect 0x0002) */
333 struct i40e_aqc_driver_version {
337 u8 driver_subbuild_ver;
343 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
345 /* Queue Shutdown (direct 0x0003) */
346 struct i40e_aqc_queue_shutdown {
347 __le32 driver_unloading;
348 #define I40E_AQ_DRIVER_UNLOADING 0x1
352 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
354 /* Set PF context (0x0004, direct) */
355 struct i40e_aqc_set_pf_context {
360 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
362 /* Request resource ownership (direct 0x0008)
363 * Release resource ownership (direct 0x0009)
365 #define I40E_AQ_RESOURCE_NVM 1
366 #define I40E_AQ_RESOURCE_SDP 2
367 #define I40E_AQ_RESOURCE_ACCESS_READ 1
368 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
369 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
370 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
372 struct i40e_aqc_request_resource {
376 __le32 resource_number;
380 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
382 /* Get function capabilities (indirect 0x000A)
383 * Get device capabilities (indirect 0x000B)
385 struct i40e_aqc_list_capabilites {
387 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
395 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
397 struct i40e_aqc_list_capabilities_element_resp {
409 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
410 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
411 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
412 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
413 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
414 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
415 #define I40E_AQ_CAP_ID_SRIOV 0x0012
416 #define I40E_AQ_CAP_ID_VF 0x0013
417 #define I40E_AQ_CAP_ID_VMDQ 0x0014
418 #define I40E_AQ_CAP_ID_8021QBG 0x0015
419 #define I40E_AQ_CAP_ID_8021QBR 0x0016
420 #define I40E_AQ_CAP_ID_VSI 0x0017
421 #define I40E_AQ_CAP_ID_DCB 0x0018
422 #define I40E_AQ_CAP_ID_FCOE 0x0021
423 #define I40E_AQ_CAP_ID_ISCSI 0x0022
424 #define I40E_AQ_CAP_ID_RSS 0x0040
425 #define I40E_AQ_CAP_ID_RXQ 0x0041
426 #define I40E_AQ_CAP_ID_TXQ 0x0042
427 #define I40E_AQ_CAP_ID_MSIX 0x0043
428 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
429 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
430 #define I40E_AQ_CAP_ID_1588 0x0046
431 #define I40E_AQ_CAP_ID_IWARP 0x0051
432 #define I40E_AQ_CAP_ID_LED 0x0061
433 #define I40E_AQ_CAP_ID_SDP 0x0062
434 #define I40E_AQ_CAP_ID_MDIO 0x0063
435 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
436 #define I40E_AQ_CAP_ID_CEM 0x00F2
438 /* Set CPPM Configuration (direct 0x0103) */
439 struct i40e_aqc_cppm_configuration {
440 __le16 command_flags;
441 #define I40E_AQ_CPPM_EN_LTRC 0x0800
442 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
443 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
444 #define I40E_AQ_CPPM_EN_HPTC 0x4000
445 #define I40E_AQ_CPPM_EN_DMARC 0x8000
454 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
456 /* Set ARP Proxy command / response (indirect 0x0104) */
457 struct i40e_aqc_arp_proxy_data {
458 __le16 command_flags;
459 #define I40E_AQ_ARP_INIT_IPV4 0x0008
460 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
461 #define I40E_AQ_ARP_ENA 0x0020
462 #define I40E_AQ_ARP_ADD_IPV4 0x0040
463 #define I40E_AQ_ARP_DEL_IPV4 0x0080
471 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
473 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
474 struct i40e_aqc_ns_proxy_data {
475 __le16 table_idx_mac_addr_0;
476 __le16 table_idx_mac_addr_1;
477 __le16 table_idx_ipv6_0;
478 __le16 table_idx_ipv6_1;
480 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
481 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
482 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
483 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
484 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
485 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
486 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
487 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
488 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
489 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
490 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
493 u8 local_mac_addr[6];
494 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
498 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
500 /* Manage LAA Command (0x0106) - obsolete */
501 struct i40e_aqc_mng_laa {
502 __le16 command_flags;
503 #define I40E_AQ_LAA_FLAG_WR 0x8000
510 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
512 /* Manage MAC Address Read Command (indirect 0x0107) */
513 struct i40e_aqc_mac_address_read {
514 __le16 command_flags;
515 #define I40E_AQC_LAN_ADDR_VALID 0x10
516 #define I40E_AQC_SAN_ADDR_VALID 0x20
517 #define I40E_AQC_PORT_ADDR_VALID 0x40
518 #define I40E_AQC_WOL_ADDR_VALID 0x80
519 #define I40E_AQC_ADDR_VALID_MASK 0xf0
525 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
527 struct i40e_aqc_mac_address_read_data {
534 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
536 /* Manage MAC Address Write Command (0x0108) */
537 struct i40e_aqc_mac_address_write {
538 __le16 command_flags;
539 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
540 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
541 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
542 #define I40E_AQC_WRITE_TYPE_MASK 0xc000
548 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
550 /* PXE commands (0x011x) */
552 /* Clear PXE Command and response (direct 0x0110) */
553 struct i40e_aqc_clear_pxe {
558 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
560 /* Switch configuration commands (0x02xx) */
562 /* Used by many indirect commands that only pass an seid and a buffer in the
565 struct i40e_aqc_switch_seid {
572 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
574 /* Get Switch Configuration command (indirect 0x0200)
575 * uses i40e_aqc_switch_seid for the descriptor
577 struct i40e_aqc_get_switch_config_header_resp {
583 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
585 struct i40e_aqc_switch_config_element_resp {
587 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
588 #define I40E_AQ_SW_ELEM_TYPE_PF 2
589 #define I40E_AQ_SW_ELEM_TYPE_VF 3
590 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
591 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
592 #define I40E_AQ_SW_ELEM_TYPE_PV 16
593 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
594 #define I40E_AQ_SW_ELEM_TYPE_PA 18
595 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
597 #define I40E_AQ_SW_ELEM_REV_1 1
600 __le16 downlink_seid;
603 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
604 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
605 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
610 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
612 /* Get Switch Configuration (indirect 0x0200)
613 * an array of elements are returned in the response buffer
614 * the first in the array is the header, remainder are elements
616 struct i40e_aqc_get_switch_config_resp {
617 struct i40e_aqc_get_switch_config_header_resp header;
618 struct i40e_aqc_switch_config_element_resp element[1];
621 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
623 /* Add Statistics (direct 0x0201)
624 * Remove Statistics (direct 0x0202)
626 struct i40e_aqc_add_remove_statistics {
633 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
635 /* Set Port Parameters command (direct 0x0203) */
636 struct i40e_aqc_set_port_parameters {
637 __le16 command_flags;
638 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
639 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
640 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
641 __le16 bad_frame_vsi;
642 __le16 default_seid; /* reserved for command */
646 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
648 /* Get Switch Resource Allocation (indirect 0x0204) */
649 struct i40e_aqc_get_switch_resource_alloc {
650 u8 num_entries; /* reserved for command */
656 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
658 /* expect an array of these structs in the response buffer */
659 struct i40e_aqc_switch_resource_alloc_element_resp {
661 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
662 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
663 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
664 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
665 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
666 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
667 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
668 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
669 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
670 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
671 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
672 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
673 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
674 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
675 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
676 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
677 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
678 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
679 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
684 __le16 total_unalloced;
688 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
690 /* Add VSI (indirect 0x0210)
691 * this indirect command uses struct i40e_aqc_vsi_properties_data
692 * as the indirect buffer (128 bytes)
694 * Update VSI (indirect 0x211)
695 * uses the same data structure as Add VSI
697 * Get VSI (indirect 0x0212)
698 * uses the same completion and data structure as Add VSI
700 struct i40e_aqc_add_get_update_vsi {
703 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
704 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
705 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
710 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
711 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
712 #define I40E_AQ_VSI_TYPE_VF 0x0
713 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
714 #define I40E_AQ_VSI_TYPE_PF 0x2
715 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
716 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
721 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
723 struct i40e_aqc_add_get_update_vsi_completion {
732 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
734 struct i40e_aqc_vsi_properties_data {
735 /* first 96 byte are written by SW */
736 __le16 valid_sections;
737 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
738 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
739 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
740 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
741 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
742 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
743 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
744 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
745 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
746 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
748 __le16 switch_id; /* 12bit id combined with flags below */
749 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
750 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
751 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
752 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
753 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
755 /* security section */
757 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
758 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
759 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
762 __le16 pvid; /* VLANS include priority bits */
765 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
766 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
767 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
768 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
769 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
770 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
771 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
772 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
773 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
774 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
775 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
776 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
777 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
778 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
779 u8 pvlan_reserved[3];
780 /* ingress egress up sections */
781 __le32 ingress_table; /* bitmap, 3 bits per up */
782 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
783 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
784 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
785 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
786 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
787 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
788 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
789 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
790 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
791 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
792 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
793 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
794 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
795 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
796 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
797 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
798 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
799 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
800 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
801 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
802 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
803 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
804 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
805 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
806 __le32 egress_table; /* same defines as for ingress table */
807 /* cascaded PV section */
810 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
811 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
812 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
813 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
814 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
815 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
816 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
817 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
818 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
820 /* queue mapping section */
821 __le16 mapping_flags;
822 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
823 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
824 __le16 queue_mapping[16];
825 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
826 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
827 __le16 tc_mapping[8];
828 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
829 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
830 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
831 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
832 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
833 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
834 /* queueing option section */
835 u8 queueing_opt_flags;
836 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
837 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
838 u8 queueing_opt_reserved[3];
839 /* scheduler section */
842 /* outer up section */
843 __le32 outer_up_table; /* same structure and defines as ingress table */
845 /* last 32 bytes are written by FW */
847 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
848 __le16 stat_counter_idx;
850 u8 resp_reserved[12];
853 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
855 /* Add Port Virtualizer (direct 0x0220)
856 * also used for update PV (direct 0x0221) but only flags are used
857 * (IS_CTRL_PORT only works on add PV)
859 struct i40e_aqc_add_update_pv {
860 __le16 command_flags;
861 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
862 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
863 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
864 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
866 __le16 connected_seid;
870 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
872 struct i40e_aqc_add_update_pv_completion {
873 /* reserved for update; for add also encodes error if rc == ENOSPC */
875 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
876 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
877 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
878 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
882 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
884 /* Get PV Params (direct 0x0222)
885 * uses i40e_aqc_switch_seid for the descriptor
888 struct i40e_aqc_get_pv_params_completion {
891 __le16 pv_flags; /* same flags as add_pv */
892 #define I40E_AQC_GET_PV_PV_TYPE 0x1
893 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
894 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
896 __le16 default_port_seid;
899 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
901 /* Add VEB (direct 0x0230) */
902 struct i40e_aqc_add_veb {
904 __le16 downlink_seid;
906 #define I40E_AQC_ADD_VEB_FLOATING 0x1
907 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
908 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
909 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
910 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
911 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
912 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
917 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
919 struct i40e_aqc_add_veb_completion {
922 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
924 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
925 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
926 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
927 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
928 __le16 statistic_index;
933 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
935 /* Get VEB Parameters (direct 0x0232)
936 * uses i40e_aqc_switch_seid for the descriptor
938 struct i40e_aqc_get_veb_parameters_completion {
941 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
942 __le16 statistic_index;
948 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
950 /* Delete Element (direct 0x0243)
951 * uses the generic i40e_aqc_switch_seid
954 /* Add MAC-VLAN (indirect 0x0250) */
956 /* used for the command for most vlan commands */
957 struct i40e_aqc_macvlan {
958 __le16 num_addresses;
960 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
961 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
962 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
963 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
968 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
970 /* indirect data for command and response */
971 struct i40e_aqc_add_macvlan_element_data {
975 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
976 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
977 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
978 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
980 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
981 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
982 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
983 /* response section */
985 #define I40E_AQC_MM_PERFECT_MATCH 0x01
986 #define I40E_AQC_MM_HASH_MATCH 0x02
987 #define I40E_AQC_MM_ERR_NO_RES 0xFF
991 struct i40e_aqc_add_remove_macvlan_completion {
992 __le16 perfect_mac_used;
993 __le16 perfect_mac_free;
994 __le16 unicast_hash_free;
995 __le16 multicast_hash_free;
1000 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1002 /* Remove MAC-VLAN (indirect 0x0251)
1003 * uses i40e_aqc_macvlan for the descriptor
1004 * data points to an array of num_addresses of elements
1007 struct i40e_aqc_remove_macvlan_element_data {
1011 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1012 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1013 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1014 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1018 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1019 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1020 u8 reply_reserved[3];
1023 /* Add VLAN (indirect 0x0252)
1024 * Remove VLAN (indirect 0x0253)
1025 * use the generic i40e_aqc_macvlan for the command
1027 struct i40e_aqc_add_remove_vlan_element_data {
1030 /* flags for add VLAN */
1031 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1032 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1033 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1034 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1035 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1036 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1037 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1038 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1039 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1040 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1041 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1042 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1043 /* flags for remove VLAN */
1044 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1047 /* flags for add VLAN */
1048 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1049 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1050 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1051 /* flags for remove VLAN */
1052 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1053 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1057 struct i40e_aqc_add_remove_vlan_completion {
1065 /* Set VSI Promiscuous Modes (direct 0x0254) */
1066 struct i40e_aqc_set_vsi_promiscuous_modes {
1067 __le16 promiscuous_flags;
1069 /* flags used for both fields above */
1070 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1071 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1072 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1073 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1074 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1076 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1078 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1082 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1084 /* Add S/E-tag command (direct 0x0255)
1085 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1087 struct i40e_aqc_add_tag {
1089 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1091 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1092 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1093 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1095 __le16 queue_number;
1099 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1101 struct i40e_aqc_add_remove_tag_completion {
1107 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1109 /* Remove S/E-tag command (direct 0x0256)
1110 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1112 struct i40e_aqc_remove_tag {
1114 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1115 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1116 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1121 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1123 /* Add multicast E-Tag (direct 0x0257)
1124 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1125 * and no external data
1127 struct i40e_aqc_add_remove_mcast_etag {
1130 u8 num_unicast_etags;
1132 __le32 addr_high; /* address of array of 2-byte s-tags */
1136 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1138 struct i40e_aqc_add_remove_mcast_etag_completion {
1140 __le16 mcast_etags_used;
1141 __le16 mcast_etags_free;
1147 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1149 /* Update S/E-Tag (direct 0x0259) */
1150 struct i40e_aqc_update_tag {
1152 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1153 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1154 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1160 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1162 struct i40e_aqc_update_tag_completion {
1168 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1170 /* Add Control Packet filter (direct 0x025A)
1171 * Remove Control Packet filter (direct 0x025B)
1172 * uses the i40e_aqc_add_oveb_cloud,
1173 * and the generic direct completion structure
1175 struct i40e_aqc_add_remove_control_packet_filter {
1179 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1180 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1181 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1182 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1183 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1185 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1186 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1187 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1192 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1194 struct i40e_aqc_add_remove_control_packet_filter_completion {
1195 __le16 mac_etype_used;
1197 __le16 mac_etype_free;
1202 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1204 /* Add Cloud filters (indirect 0x025C)
1205 * Remove Cloud filters (indirect 0x025D)
1206 * uses the i40e_aqc_add_remove_cloud_filters,
1207 * and the generic indirect completion structure
1209 struct i40e_aqc_add_remove_cloud_filters {
1213 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1214 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1215 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1221 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1223 struct i40e_aqc_add_remove_cloud_filters_element_data {
1237 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1238 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1239 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1240 /* 0x0000 reserved */
1241 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1242 /* 0x0002 reserved */
1243 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1244 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1245 /* 0x0005 reserved */
1246 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1247 /* 0x0007 reserved */
1248 /* 0x0008 reserved */
1249 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1250 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1251 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1252 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1254 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1255 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1256 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1257 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1258 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1260 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1261 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1262 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
1263 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1264 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
1265 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1269 __le16 queue_number;
1270 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1271 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1272 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1274 /* response section */
1275 u8 allocation_result;
1276 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1277 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1278 u8 response_reserved[7];
1281 struct i40e_aqc_remove_cloud_filters_completion {
1282 __le16 perfect_ovlan_used;
1283 __le16 perfect_ovlan_free;
1290 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1292 /* Add Mirror Rule (indirect or direct 0x0260)
1293 * Delete Mirror Rule (indirect or direct 0x0261)
1294 * note: some rule types (4,5) do not use an external buffer.
1295 * take care to set the flags correctly.
1297 struct i40e_aqc_add_delete_mirror_rule {
1300 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1301 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1302 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1303 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1304 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1305 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1306 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1307 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1309 __le16 destination; /* VSI for add, rule id for delete */
1310 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1314 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1316 struct i40e_aqc_add_delete_mirror_rule_completion {
1318 __le16 rule_id; /* only used on add */
1319 __le16 mirror_rules_used;
1320 __le16 mirror_rules_free;
1325 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1329 /* PFC Ignore (direct 0x0301)
1330 * the command and response use the same descriptor structure
1332 struct i40e_aqc_pfc_ignore {
1334 u8 command_flags; /* unused on response */
1335 #define I40E_AQC_PFC_IGNORE_SET 0x80
1336 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1340 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1342 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1343 * with no parameters
1346 /* TX scheduler 0x04xx */
1348 /* Almost all the indirect commands use
1349 * this generic struct to pass the SEID in param0
1351 struct i40e_aqc_tx_sched_ind {
1358 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1360 /* Several commands respond with a set of queue set handles */
1361 struct i40e_aqc_qs_handles_resp {
1362 __le16 qs_handles[8];
1365 /* Configure VSI BW limits (direct 0x0400) */
1366 struct i40e_aqc_configure_vsi_bw_limit {
1371 u8 max_credit; /* 0-3, limit = 2^max */
1375 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1377 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1378 * responds with i40e_aqc_qs_handles_resp
1380 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1383 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1385 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1386 __le16 tc_bw_max[2];
1390 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1392 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1393 * responds with i40e_aqc_qs_handles_resp
1395 struct i40e_aqc_configure_vsi_tc_bw_data {
1398 u8 tc_bw_credits[8];
1400 __le16 qs_handles[8];
1403 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1405 /* Query vsi bw configuration (indirect 0x0408) */
1406 struct i40e_aqc_query_vsi_bw_config_resp {
1408 u8 tc_suspended_bits;
1410 __le16 qs_handles[8];
1412 __le16 port_bw_limit;
1414 u8 max_bw; /* 0-3, limit = 2^max */
1418 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1420 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1421 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1424 u8 share_credits[8];
1427 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1428 __le16 tc_bw_max[2];
1431 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1433 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1434 struct i40e_aqc_configure_switching_comp_bw_limit {
1439 u8 max_bw; /* 0-3, limit = 2^max */
1443 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1445 /* Enable Physical Port ETS (indirect 0x0413)
1446 * Modify Physical Port ETS (indirect 0x0414)
1447 * Disable Physical Port ETS (indirect 0x0415)
1449 struct i40e_aqc_configure_switching_comp_ets_data {
1453 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1454 u8 tc_strict_priority_flags;
1456 u8 tc_bw_share_credits[8];
1460 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1462 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1463 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1466 __le16 tc_bw_credit[8];
1468 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1469 __le16 tc_bw_max[2];
1473 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1475 /* Configure Switching Component Bandwidth Allocation per Tc
1478 struct i40e_aqc_configure_switching_comp_bw_config_data {
1481 u8 absolute_credits; /* bool */
1482 u8 tc_bw_share_credits[8];
1486 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1488 /* Query Switching Component Configuration (indirect 0x0418) */
1489 struct i40e_aqc_query_switching_comp_ets_config_resp {
1492 __le16 port_bw_limit;
1494 u8 tc_bw_max; /* 0-3, limit = 2^max */
1498 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1500 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1501 struct i40e_aqc_query_port_ets_config_resp {
1505 u8 tc_strict_priority_bits;
1507 u8 tc_bw_share_credits[8];
1508 __le16 tc_bw_limits[8];
1510 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1511 __le16 tc_bw_max[2];
1515 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1517 /* Query Switching Component Bandwidth Allocation per Traffic Type
1520 struct i40e_aqc_query_switching_comp_bw_config_resp {
1523 u8 absolute_credits_enable; /* bool */
1524 u8 tc_bw_share_credits[8];
1525 __le16 tc_bw_limits[8];
1527 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1528 __le16 tc_bw_max[2];
1531 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1533 /* Suspend/resume port TX traffic
1534 * (direct 0x041B and 0x041C) uses the generic SEID struct
1537 /* Configure partition BW
1540 struct i40e_aqc_configure_partition_bw_data {
1541 __le16 pf_valid_bits;
1542 u8 min_bw[16]; /* guaranteed bandwidth */
1543 u8 max_bw[16]; /* bandwidth limit */
1546 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1548 /* Get and set the active HMC resource profile and status.
1549 * (direct 0x0500) and (direct 0x0501)
1551 struct i40e_aq_get_set_hmc_resource_profile {
1557 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1559 enum i40e_aq_hmc_profile {
1560 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1561 I40E_HMC_PROFILE_DEFAULT = 1,
1562 I40E_HMC_PROFILE_FAVOR_VF = 2,
1563 I40E_HMC_PROFILE_EQUAL = 3,
1566 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1567 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1569 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1571 /* set in param0 for get phy abilities to report qualified modules */
1572 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1573 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1575 enum i40e_aq_phy_type {
1576 I40E_PHY_TYPE_SGMII = 0x0,
1577 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1578 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1579 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1580 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1581 I40E_PHY_TYPE_XAUI = 0x5,
1582 I40E_PHY_TYPE_XFI = 0x6,
1583 I40E_PHY_TYPE_SFI = 0x7,
1584 I40E_PHY_TYPE_XLAUI = 0x8,
1585 I40E_PHY_TYPE_XLPPI = 0x9,
1586 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1587 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1588 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1589 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1590 I40E_PHY_TYPE_100BASE_TX = 0x11,
1591 I40E_PHY_TYPE_1000BASE_T = 0x12,
1592 I40E_PHY_TYPE_10GBASE_T = 0x13,
1593 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1594 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1595 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1596 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1597 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1598 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1599 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1600 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1601 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1602 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1603 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1607 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1608 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1609 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1610 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1611 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1613 enum i40e_aq_link_speed {
1614 I40E_LINK_SPEED_UNKNOWN = 0,
1615 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1616 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1617 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1618 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1619 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1622 struct i40e_aqc_module_desc {
1630 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1632 struct i40e_aq_get_phy_abilities_resp {
1633 __le32 phy_type; /* bitmap using the above enum for offsets */
1634 u8 link_speed; /* bitmap using the above enum bit patterns */
1636 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1637 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1638 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1639 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1640 #define I40E_AQ_PHY_AN_ENABLED 0x10
1641 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1642 __le16 eee_capability;
1643 #define I40E_AQ_EEE_100BASE_TX 0x0002
1644 #define I40E_AQ_EEE_1000BASE_T 0x0004
1645 #define I40E_AQ_EEE_10GBASE_T 0x0008
1646 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1647 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1648 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1651 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1655 u8 qualified_module_count;
1656 #define I40E_AQ_PHY_MAX_QMS 16
1657 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1660 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1662 /* Set PHY Config (direct 0x0601) */
1663 struct i40e_aq_set_phy_config { /* same bits as above in all */
1667 /* bits 0-2 use the values from get_phy_abilities_resp */
1668 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1669 #define I40E_AQ_PHY_ENABLE_AN 0x10
1670 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1671 __le16 eee_capability;
1677 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1679 /* Set MAC Config command data structure (direct 0x0603) */
1680 struct i40e_aq_set_mac_config {
1681 __le16 max_frame_size;
1683 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1684 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1685 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1686 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1687 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1688 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1689 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1690 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1691 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1692 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1693 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1694 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1695 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1696 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1697 u8 tx_timer_priority; /* bitmap */
1698 __le16 tx_timer_value;
1699 __le16 fc_refresh_threshold;
1703 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1705 /* Restart Auto-Negotiation (direct 0x605) */
1706 struct i40e_aqc_set_link_restart_an {
1708 #define I40E_AQ_PHY_RESTART_AN 0x02
1709 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1713 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1715 /* Get Link Status cmd & response data structure (direct 0x0607) */
1716 struct i40e_aqc_get_link_status {
1717 __le16 command_flags; /* only field set on command */
1718 #define I40E_AQ_LSE_MASK 0x3
1719 #define I40E_AQ_LSE_NOP 0x0
1720 #define I40E_AQ_LSE_DISABLE 0x2
1721 #define I40E_AQ_LSE_ENABLE 0x3
1722 /* only response uses this flag */
1723 #define I40E_AQ_LSE_IS_ENABLED 0x1
1724 u8 phy_type; /* i40e_aq_phy_type */
1725 u8 link_speed; /* i40e_aq_link_speed */
1727 #define I40E_AQ_LINK_UP 0x01
1728 #define I40E_AQ_LINK_FAULT 0x02
1729 #define I40E_AQ_LINK_FAULT_TX 0x04
1730 #define I40E_AQ_LINK_FAULT_RX 0x08
1731 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1732 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1733 #define I40E_AQ_SIGNAL_DETECT 0x80
1735 #define I40E_AQ_AN_COMPLETED 0x01
1736 #define I40E_AQ_LP_AN_ABILITY 0x02
1737 #define I40E_AQ_PD_FAULT 0x04
1738 #define I40E_AQ_FEC_EN 0x08
1739 #define I40E_AQ_PHY_LOW_POWER 0x10
1740 #define I40E_AQ_LINK_PAUSE_TX 0x20
1741 #define I40E_AQ_LINK_PAUSE_RX 0x40
1742 #define I40E_AQ_QUALIFIED_MODULE 0x80
1744 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1745 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1746 #define I40E_AQ_LINK_TX_SHIFT 0x02
1747 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1748 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1749 #define I40E_AQ_LINK_TX_DRAINED 0x01
1750 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1751 #define I40E_AQ_LINK_FORCED_40G 0x10
1752 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1753 __le16 max_frame_size;
1755 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1756 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1760 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1762 /* Set event mask command (direct 0x613) */
1763 struct i40e_aqc_set_phy_int_mask {
1766 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1767 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1768 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1769 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1770 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1771 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1772 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1773 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1774 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1778 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1780 /* Get Local AN advt register (direct 0x0614)
1781 * Set Local AN advt register (direct 0x0615)
1782 * Get Link Partner AN advt register (direct 0x0616)
1784 struct i40e_aqc_an_advt_reg {
1785 __le32 local_an_reg0;
1786 __le16 local_an_reg1;
1790 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1792 /* Set Loopback mode (0x0618) */
1793 struct i40e_aqc_set_lb_mode {
1795 #define I40E_AQ_LB_PHY_LOCAL 0x01
1796 #define I40E_AQ_LB_PHY_REMOTE 0x02
1797 #define I40E_AQ_LB_MAC_LOCAL 0x04
1801 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1803 /* Set PHY Debug command (0x0622) */
1804 struct i40e_aqc_set_phy_debug {
1806 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1807 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1808 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1809 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1810 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1811 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1812 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1813 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1817 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1819 enum i40e_aq_phy_reg_type {
1820 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1821 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1822 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1825 /* NVM Read command (indirect 0x0701)
1826 * NVM Erase commands (direct 0x0702)
1827 * NVM Update commands (indirect 0x0703)
1829 struct i40e_aqc_nvm_update {
1831 #define I40E_AQ_NVM_LAST_CMD 0x01
1832 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1840 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1842 /* NVM Config Read (indirect 0x0704) */
1843 struct i40e_aqc_nvm_config_read {
1845 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1846 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1847 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1848 __le16 element_count;
1849 __le16 element_id; /* Feature/field ID */
1850 __le16 element_id_msw; /* MSWord of field ID */
1851 __le32 address_high;
1855 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1857 /* NVM Config Write (indirect 0x0705) */
1858 struct i40e_aqc_nvm_config_write {
1860 __le16 element_count;
1862 __le32 address_high;
1866 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1868 /* Used for 0x0704 as well as for 0x0705 commands */
1869 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1870 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1871 #define I40E_AQ_ANVM_FEATURE 0
1872 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
1873 struct i40e_aqc_nvm_config_data_feature {
1875 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1876 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1877 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1878 __le16 feature_options;
1879 __le16 feature_selection;
1882 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1884 struct i40e_aqc_nvm_config_data_immediate_field {
1887 __le16 field_options;
1891 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1893 /* Send to PF command (indirect 0x0801) id is only used by PF
1894 * Send to VF command (indirect 0x0802) id is only used by PF
1895 * Send to Peer PF command (indirect 0x0803)
1897 struct i40e_aqc_pf_vf_message {
1904 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1906 /* Alternate structure */
1908 /* Direct write (direct 0x0900)
1909 * Direct read (direct 0x0902)
1911 struct i40e_aqc_alternate_write {
1918 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1920 /* Indirect write (indirect 0x0901)
1921 * Indirect read (indirect 0x0903)
1924 struct i40e_aqc_alternate_ind_write {
1931 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1933 /* Done alternate write (direct 0x0904)
1936 struct i40e_aqc_alternate_write_done {
1938 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1939 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1940 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1941 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1945 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1947 /* Set OEM mode (direct 0x0905) */
1948 struct i40e_aqc_alternate_set_mode {
1950 #define I40E_AQ_ALTERNATE_MODE_NONE 0
1951 #define I40E_AQ_ALTERNATE_MODE_OEM 1
1955 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1957 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1959 /* async events 0x10xx */
1961 /* Lan Queue Overflow Event (direct, 0x1001) */
1962 struct i40e_aqc_lan_overflow {
1963 __le32 prtdcb_rupto;
1968 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1970 /* Get LLDP MIB (indirect 0x0A00) */
1971 struct i40e_aqc_lldp_get_mib {
1974 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1975 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
1976 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
1977 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
1978 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1979 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1980 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
1981 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
1982 #define I40E_AQ_LLDP_TX_SHIFT 0x4
1983 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
1984 /* TX pause flags use I40E_AQ_LINK_TX_* above */
1992 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
1994 /* Configure LLDP MIB Change Event (direct 0x0A01)
1995 * also used for the event (with type in the command field)
1997 struct i40e_aqc_lldp_update_mib {
1999 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2000 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2006 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2008 /* Add LLDP TLV (indirect 0x0A02)
2009 * Delete LLDP TLV (indirect 0x0A04)
2011 struct i40e_aqc_lldp_add_tlv {
2012 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2020 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2022 /* Update LLDP TLV (indirect 0x0A03) */
2023 struct i40e_aqc_lldp_update_tlv {
2024 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2033 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2035 /* Stop LLDP (direct 0x0A05) */
2036 struct i40e_aqc_lldp_stop {
2038 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2039 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2043 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2045 /* Start LLDP (direct 0x0A06) */
2047 struct i40e_aqc_lldp_start {
2049 #define I40E_AQ_LLDP_AGENT_START 0x1
2053 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2055 /* Get CEE DCBX Oper Config (0x0A07)
2056 * uses the generic descriptor struct
2057 * returns below as indirect response
2060 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2061 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2062 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2063 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2064 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2065 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2066 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2067 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2068 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2069 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2070 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2071 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2072 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2080 __le16 oper_app_prio;
2085 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2087 struct i40e_aqc_get_cee_dcb_cfg_resp {
2092 __le16 oper_app_prio;
2097 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2099 /* Set Local LLDP MIB (indirect 0x0A08)
2100 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2102 struct i40e_aqc_lldp_set_local_mib {
2103 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2104 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2109 __le32 address_high;
2113 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2115 /* Stop/Start LLDP Agent (direct 0x0A09)
2116 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2118 struct i40e_aqc_lldp_stop_start_specific_agent {
2119 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2120 #define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2125 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2127 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2128 struct i40e_aqc_add_udp_tunnel {
2132 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2133 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2134 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2138 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2140 struct i40e_aqc_add_udp_tunnel_completion {
2142 u8 filter_entry_index;
2144 #define I40E_AQC_SINGLE_PF 0x0
2145 #define I40E_AQC_MULTIPLE_PFS 0x1
2150 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2152 /* remove UDP Tunnel command (0x0B01) */
2153 struct i40e_aqc_remove_udp_tunnel {
2155 u8 index; /* 0 to 15 */
2159 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2161 struct i40e_aqc_del_udp_tunnel_completion {
2163 u8 index; /* 0 to 15 */
2165 u8 total_filters_used;
2169 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2171 /* tunnel key structure 0x0B10 */
2173 struct i40e_aqc_tunnel_key_structure {
2176 u8 key1_len; /* 0 to 15 */
2177 u8 key2_len; /* 0 to 15 */
2179 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2180 /* response flags */
2181 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2182 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2183 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2184 u8 network_key_index;
2185 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2186 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2187 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2188 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2192 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2194 /* OEM mode commands (direct 0xFE0x) */
2195 struct i40e_aqc_oem_param_change {
2197 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2198 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2199 #define I40E_AQ_OEM_PARAM_MAC 2
2200 __le32 param_value1;
2201 __le16 param_value2;
2205 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2207 struct i40e_aqc_oem_state_change {
2209 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2210 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2214 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2216 /* Initialize OCSD (0xFE02, direct) */
2217 struct i40e_aqc_opc_oem_ocsd_initialize {
2220 __le32 ocsd_memory_block_addr_high;
2221 __le32 ocsd_memory_block_addr_low;
2222 __le32 requested_update_interval;
2225 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2227 /* Initialize OCBB (0xFE03, direct) */
2228 struct i40e_aqc_opc_oem_ocbb_initialize {
2231 __le32 ocbb_memory_block_addr_high;
2232 __le32 ocbb_memory_block_addr_low;
2236 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2238 /* debug commands */
2240 /* get device id (0xFF00) uses the generic structure */
2242 /* set test more (0xFF01, internal) */
2244 struct i40e_acq_set_test_mode {
2246 #define I40E_AQ_TEST_PARTIAL 0
2247 #define I40E_AQ_TEST_FULL 1
2248 #define I40E_AQ_TEST_NVM 2
2251 #define I40E_AQ_TEST_OPEN 0
2252 #define I40E_AQ_TEST_CLOSE 1
2253 #define I40E_AQ_TEST_INC 2
2255 __le32 address_high;
2259 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2261 /* Debug Read Register command (0xFF03)
2262 * Debug Write Register command (0xFF04)
2264 struct i40e_aqc_debug_reg_read_write {
2271 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2273 /* Scatter/gather Reg Read (indirect 0xFF05)
2274 * Scatter/gather Reg Write (indirect 0xFF06)
2277 /* i40e_aq_desc is used for the command */
2278 struct i40e_aqc_debug_reg_sg_element_data {
2283 /* Debug Modify register (direct 0xFF07) */
2284 struct i40e_aqc_debug_modify_reg {
2291 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2293 /* dump internal data (0xFF08, indirect) */
2295 #define I40E_AQ_CLUSTER_ID_AUX 0
2296 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2297 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2298 #define I40E_AQ_CLUSTER_ID_HMC 3
2299 #define I40E_AQ_CLUSTER_ID_MAC0 4
2300 #define I40E_AQ_CLUSTER_ID_MAC1 5
2301 #define I40E_AQ_CLUSTER_ID_MAC2 6
2302 #define I40E_AQ_CLUSTER_ID_MAC3 7
2303 #define I40E_AQ_CLUSTER_ID_DCB 8
2304 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2305 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2306 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2308 struct i40e_aqc_debug_dump_internals {
2313 __le32 address_high;
2317 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2319 struct i40e_aqc_debug_modify_internals {
2321 u8 cluster_specific_params[7];
2322 __le32 address_high;
2326 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);