4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define I40E_MIN_RING_DESC 64
61 #define I40E_MAX_RING_DESC 4096
62 #define I40E_ALIGN 128
63 #define DEFAULT_TX_RS_THRESH 32
64 #define DEFAULT_TX_FREE_THRESH 32
65 #define I40E_MAX_PKT_TYPE 256
67 #define I40E_VLAN_TAG_SIZE 4
68 #define I40E_TX_MAX_BURST 32
70 #define I40E_DMA_MEM_ALIGN 4096
72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
73 ETH_TXQ_FLAGS_NOOFFLOADS)
75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
77 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
78 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
80 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
81 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
83 static const struct rte_memzone *
84 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
85 const char *ring_name,
89 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
90 struct rte_mbuf **tx_pkts,
93 /* Translate the rx descriptor status to pkt flags */
94 static inline uint16_t
95 i40e_rxd_status_to_pkt_flags(uint64_t qword)
99 /* Check if VLAN packet */
100 flags = (uint16_t)(qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
101 PKT_RX_VLAN_PKT : 0);
103 /* Check if RSS_HASH */
104 flags |= (uint16_t)((((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
105 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
106 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0);
111 static inline uint16_t
112 i40e_rxd_error_to_pkt_flags(uint64_t qword)
115 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
117 #define I40E_RX_ERR_BITS 0x3f
118 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
120 /* If RXE bit set, all other status bits are meaningless */
121 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
122 flags |= PKT_RX_MAC_ERR;
126 /* If RECIPE bit set, all other status indications should be ignored */
127 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
128 flags |= PKT_RX_RECIP_ERR;
131 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
132 flags |= PKT_RX_HBUF_OVERFLOW;
133 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
134 flags |= PKT_RX_IP_CKSUM_BAD;
135 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
136 flags |= PKT_RX_L4_CKSUM_BAD;
137 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
138 flags |= PKT_RX_EIP_CKSUM_BAD;
139 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
140 flags |= PKT_RX_OVERSIZE;
145 /* Translate pkt types to pkt flags */
146 static inline uint16_t
147 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
149 uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
150 I40E_RXD_QW1_PTYPE_SHIFT);
151 static const uint16_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
174 PKT_RX_IPV4_HDR, /* PTYPE 22 */
175 PKT_RX_IPV4_HDR, /* PTYPE 23 */
176 PKT_RX_IPV4_HDR, /* PTYPE 24 */
178 PKT_RX_IPV4_HDR, /* PTYPE 26 */
179 PKT_RX_IPV4_HDR, /* PTYPE 27 */
180 PKT_RX_IPV4_HDR, /* PTYPE 28 */
181 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
182 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
183 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
185 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
186 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
187 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
188 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
189 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
190 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
192 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
193 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
194 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
195 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
196 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
197 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
198 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
200 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
201 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
202 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
203 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
204 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
205 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
207 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
208 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
209 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
210 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
211 PKT_RX_IPV4_HDR_EXT, /* PTYPE 59 */
212 PKT_RX_IPV4_HDR_EXT, /* PTYPE 60 */
213 PKT_RX_IPV4_HDR_EXT, /* PTYPE 61 */
215 PKT_RX_IPV4_HDR_EXT, /* PTYPE 63 */
216 PKT_RX_IPV4_HDR_EXT, /* PTYPE 64 */
217 PKT_RX_IPV4_HDR_EXT, /* PTYPE 65 */
218 PKT_RX_IPV4_HDR_EXT, /* PTYPE 66 */
219 PKT_RX_IPV4_HDR_EXT, /* PTYPE 67 */
220 PKT_RX_IPV4_HDR_EXT, /* PTYPE 68 */
222 PKT_RX_IPV4_HDR_EXT, /* PTYPE 70 */
223 PKT_RX_IPV4_HDR_EXT, /* PTYPE 71 */
224 PKT_RX_IPV4_HDR_EXT, /* PTYPE 72 */
225 PKT_RX_IPV4_HDR_EXT, /* PTYPE 73 */
226 PKT_RX_IPV4_HDR_EXT, /* PTYPE 74 */
227 PKT_RX_IPV4_HDR_EXT, /* PTYPE 75 */
228 PKT_RX_IPV4_HDR_EXT, /* PTYPE 76 */
230 PKT_RX_IPV4_HDR_EXT, /* PTYPE 78 */
231 PKT_RX_IPV4_HDR_EXT, /* PTYPE 79 */
232 PKT_RX_IPV4_HDR_EXT, /* PTYPE 80 */
233 PKT_RX_IPV4_HDR_EXT, /* PTYPE 81 */
234 PKT_RX_IPV4_HDR_EXT, /* PTYPE 82 */
235 PKT_RX_IPV4_HDR_EXT, /* PTYPE 83 */
237 PKT_RX_IPV4_HDR_EXT, /* PTYPE 85 */
238 PKT_RX_IPV4_HDR_EXT, /* PTYPE 86 */
239 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
240 PKT_RX_IPV6_HDR, /* PTYPE 88 */
241 PKT_RX_IPV6_HDR, /* PTYPE 89 */
242 PKT_RX_IPV6_HDR, /* PTYPE 90 */
244 PKT_RX_IPV6_HDR, /* PTYPE 92 */
245 PKT_RX_IPV6_HDR, /* PTYPE 93 */
246 PKT_RX_IPV6_HDR, /* PTYPE 94 */
247 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
248 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
249 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
251 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
252 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
253 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
254 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
255 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
256 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
258 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
259 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
260 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
261 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
262 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
263 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
264 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
266 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
267 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
268 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
269 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
270 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
271 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
273 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
274 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
275 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
276 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
277 PKT_RX_IPV6_HDR_EXT, /* PTYPE 125 */
278 PKT_RX_IPV6_HDR_EXT, /* PTYPE 126 */
279 PKT_RX_IPV6_HDR_EXT, /* PTYPE 127 */
281 PKT_RX_IPV6_HDR_EXT, /* PTYPE 129 */
282 PKT_RX_IPV6_HDR_EXT, /* PTYPE 130 */
283 PKT_RX_IPV6_HDR_EXT, /* PTYPE 131 */
284 PKT_RX_IPV6_HDR_EXT, /* PTYPE 132 */
285 PKT_RX_IPV6_HDR_EXT, /* PTYPE 133 */
286 PKT_RX_IPV6_HDR_EXT, /* PTYPE 134 */
288 PKT_RX_IPV6_HDR_EXT, /* PTYPE 136 */
289 PKT_RX_IPV6_HDR_EXT, /* PTYPE 137 */
290 PKT_RX_IPV6_HDR_EXT, /* PTYPE 138 */
291 PKT_RX_IPV6_HDR_EXT, /* PTYPE 139 */
292 PKT_RX_IPV6_HDR_EXT, /* PTYPE 140 */
293 PKT_RX_IPV6_HDR_EXT, /* PTYPE 141 */
294 PKT_RX_IPV6_HDR_EXT, /* PTYPE 142 */
296 PKT_RX_IPV6_HDR_EXT, /* PTYPE 144 */
297 PKT_RX_IPV6_HDR_EXT, /* PTYPE 145 */
298 PKT_RX_IPV6_HDR_EXT, /* PTYPE 146 */
299 PKT_RX_IPV6_HDR_EXT, /* PTYPE 147 */
300 PKT_RX_IPV6_HDR_EXT, /* PTYPE 148 */
301 PKT_RX_IPV6_HDR_EXT, /* PTYPE 149 */
303 PKT_RX_IPV6_HDR_EXT, /* PTYPE 151 */
304 PKT_RX_IPV6_HDR_EXT, /* PTYPE 152 */
305 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
410 return ip_ptype_map[ptype];
414 i40e_txd_enable_checksum(uint32_t ol_flags,
421 PMD_DRV_LOG(DEBUG, "L2 length set to 0\n");
424 *td_offset |= (l2_len >> 1) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
427 PMD_DRV_LOG(DEBUG, "L3 length set to 0\n");
431 /* Enable L3 checksum offloads */
432 if (ol_flags & PKT_TX_IPV4_CSUM) {
433 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
434 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
435 } else if (ol_flags & PKT_TX_IPV4) {
436 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
437 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
438 } else if (ol_flags & PKT_TX_IPV6) {
439 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
440 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
443 /* Enable L4 checksum offloads */
444 switch (ol_flags & PKT_TX_L4_MASK) {
445 case PKT_TX_TCP_CKSUM:
446 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
447 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
448 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
450 case PKT_TX_SCTP_CKSUM:
451 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
452 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
453 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
455 case PKT_TX_UDP_CKSUM:
456 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
457 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
458 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
465 static inline struct rte_mbuf *
466 rte_rxmbuf_alloc(struct rte_mempool *mp)
470 m = __rte_mbuf_raw_alloc(mp);
471 __rte_mbuf_sanity_check_raw(m, 0);
476 /* Construct the tx flags */
477 static inline uint64_t
478 i40e_build_ctob(uint32_t td_cmd,
483 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
484 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
485 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
486 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
487 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
491 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
493 struct i40e_tx_entry *sw_ring = txq->sw_ring;
494 volatile struct i40e_tx_desc *txd = txq->tx_ring;
495 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
496 uint16_t nb_tx_desc = txq->nb_tx_desc;
497 uint16_t desc_to_clean_to;
498 uint16_t nb_tx_to_clean;
500 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
501 if (desc_to_clean_to >= nb_tx_desc)
502 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
504 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
505 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
506 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
507 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
508 "(port=%d queue=%d)", desc_to_clean_to,
509 txq->port_id, txq->queue_id);
513 if (last_desc_cleaned > desc_to_clean_to)
514 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
517 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
520 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
522 txq->last_desc_cleaned = desc_to_clean_to;
523 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
529 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
530 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
532 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
537 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
538 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST))
540 else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc))
542 else if (!(rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)
544 else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
545 RTE_PMD_I40E_RX_MAX_BURST)))
554 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
555 #define I40E_LOOK_AHEAD 8
556 #if (I40E_LOOK_AHEAD != 8)
557 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
560 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
562 volatile union i40e_rx_desc *rxdp;
563 struct i40e_rx_entry *rxep;
568 int32_t s[I40E_LOOK_AHEAD], nb_dd;
569 int32_t i, j, nb_rx = 0;
572 rxdp = &rxq->rx_ring[rxq->rx_tail];
573 rxep = &rxq->sw_ring[rxq->rx_tail];
575 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
576 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
577 I40E_RXD_QW1_STATUS_SHIFT;
579 /* Make sure there is at least 1 packet to receive */
580 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
584 * Scan LOOK_AHEAD descriptors at a time to determine which
585 * descriptors reference packets that are ready to be received.
587 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
588 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
589 /* Read desc statuses backwards to avoid race condition */
590 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
591 qword1 = rte_le_to_cpu_64(\
592 rxdp[j].wb.qword1.status_error_len);
593 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
594 I40E_RXD_QW1_STATUS_SHIFT;
597 /* Compute how many status bits were set */
598 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
599 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
603 /* Translate descriptor info to mbuf parameters */
604 for (j = 0; j < nb_dd; j++) {
606 qword1 = rte_le_to_cpu_64(\
607 rxdp[j].wb.qword1.status_error_len);
608 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
609 I40E_RXD_QW1_STATUS_SHIFT;
610 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
611 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
612 mb->data_len = pkt_len;
613 mb->pkt_len = pkt_len;
614 mb->vlan_tci = rx_status &
615 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
617 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
618 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
619 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
620 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
621 mb->ol_flags = pkt_flags;
622 if (pkt_flags & PKT_RX_RSS_HASH)
623 mb->hash.rss = rte_le_to_cpu_32(\
624 rxdp->wb.qword0.hi_dword.rss);
627 for (j = 0; j < I40E_LOOK_AHEAD; j++)
628 rxq->rx_stage[i + j] = rxep[j].mbuf;
630 if (nb_dd != I40E_LOOK_AHEAD)
634 /* Clear software ring entries */
635 for (i = 0; i < nb_rx; i++)
636 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
641 static inline uint16_t
642 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
643 struct rte_mbuf **rx_pkts,
647 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
649 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
651 for (i = 0; i < nb_pkts; i++)
652 rx_pkts[i] = stage[i];
654 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
655 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
661 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
663 volatile union i40e_rx_desc *rxdp;
664 struct i40e_rx_entry *rxep;
666 uint16_t alloc_idx, i;
670 /* Allocate buffers in bulk */
671 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
672 (rxq->rx_free_thresh - 1));
673 rxep = &(rxq->sw_ring[alloc_idx]);
674 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
675 rxq->rx_free_thresh);
676 if (unlikely(diag != 0)) {
677 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk\n");
681 rxdp = &rxq->rx_ring[alloc_idx];
682 for (i = 0; i < rxq->rx_free_thresh; i++) {
684 rte_mbuf_refcnt_set(mb, 1);
686 mb->data_off = RTE_PKTMBUF_HEADROOM;
688 mb->port = rxq->port_id;
689 dma_addr = rte_cpu_to_le_64(\
690 RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
691 rxdp[i].read.hdr_addr = dma_addr;
692 rxdp[i].read.pkt_addr = dma_addr;
695 /* Update rx tail regsiter */
697 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
699 rxq->rx_free_trigger =
700 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
701 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
702 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
707 static inline uint16_t
708 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
710 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
716 if (rxq->rx_nb_avail)
717 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
719 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
720 rxq->rx_next_avail = 0;
721 rxq->rx_nb_avail = nb_rx;
722 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
724 if (rxq->rx_tail > rxq->rx_free_trigger) {
725 if (i40e_rx_alloc_bufs(rxq) != 0) {
728 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
729 "port_id=%u, queue_id=%u\n",
730 rxq->port_id, rxq->queue_id);
731 rxq->rx_nb_avail = 0;
732 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
733 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
734 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
740 if (rxq->rx_tail >= rxq->nb_rx_desc)
743 if (rxq->rx_nb_avail)
744 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
750 i40e_recv_pkts_bulk_alloc(void *rx_queue,
751 struct rte_mbuf **rx_pkts,
754 uint16_t nb_rx = 0, n, count;
756 if (unlikely(nb_pkts == 0))
759 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
760 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
763 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
764 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
765 nb_rx = (uint16_t)(nb_rx + count);
766 nb_pkts = (uint16_t)(nb_pkts - count);
773 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
776 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
778 struct i40e_rx_queue *rxq;
779 volatile union i40e_rx_desc *rx_ring;
780 volatile union i40e_rx_desc *rxdp;
781 union i40e_rx_desc rxd;
782 struct i40e_rx_entry *sw_ring;
783 struct i40e_rx_entry *rxe;
784 struct rte_mbuf *rxm;
785 struct rte_mbuf *nmb;
789 uint16_t rx_packet_len;
790 uint16_t rx_id, nb_hold;
797 rx_id = rxq->rx_tail;
798 rx_ring = rxq->rx_ring;
799 sw_ring = rxq->sw_ring;
801 while (nb_rx < nb_pkts) {
802 rxdp = &rx_ring[rx_id];
803 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
804 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
805 >> I40E_RXD_QW1_STATUS_SHIFT;
806 /* Check the DD bit first */
807 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
810 nmb = rte_rxmbuf_alloc(rxq->mp);
816 rxe = &sw_ring[rx_id];
818 if (unlikely(rx_id == rxq->nb_rx_desc))
821 /* Prefetch next mbuf */
822 rte_prefetch0(sw_ring[rx_id].mbuf);
825 * When next RX descriptor is on a cache line boundary,
826 * prefetch the next 4 RX descriptors and next 8 pointers
829 if ((rx_id & 0x3) == 0) {
830 rte_prefetch0(&rx_ring[rx_id]);
831 rte_prefetch0(&sw_ring[rx_id]);
836 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
837 rxdp->read.hdr_addr = dma_addr;
838 rxdp->read.pkt_addr = dma_addr;
840 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
841 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
843 rxm->data_off = RTE_PKTMBUF_HEADROOM;
844 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
847 rxm->pkt_len = rx_packet_len;
848 rxm->data_len = rx_packet_len;
849 rxm->port = rxq->port_id;
851 rxm->vlan_tci = rx_status &
852 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
853 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
854 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
855 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
856 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
857 rxm->ol_flags = pkt_flags;
858 if (pkt_flags & PKT_RX_RSS_HASH)
860 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
862 rx_pkts[nb_rx++] = rxm;
864 rxq->rx_tail = rx_id;
867 * If the number of free RX descriptors is greater than the RX free
868 * threshold of the queue, advance the receive tail register of queue.
869 * Update that register with the value of the last processed RX
870 * descriptor minus 1.
872 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
873 if (nb_hold > rxq->rx_free_thresh) {
874 rx_id = (uint16_t) ((rx_id == 0) ?
875 (rxq->nb_rx_desc - 1) : (rx_id - 1));
876 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
879 rxq->nb_rx_hold = nb_hold;
885 i40e_recv_scattered_pkts(void *rx_queue,
886 struct rte_mbuf **rx_pkts,
889 struct i40e_rx_queue *rxq = rx_queue;
890 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
891 volatile union i40e_rx_desc *rxdp;
892 union i40e_rx_desc rxd;
893 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
894 struct i40e_rx_entry *rxe;
895 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
896 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
897 struct rte_mbuf *nmb, *rxm;
898 uint16_t rx_id = rxq->rx_tail;
899 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len, pkt_flags;
904 while (nb_rx < nb_pkts) {
905 rxdp = &rx_ring[rx_id];
906 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
907 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
908 I40E_RXD_QW1_STATUS_SHIFT;
909 /* Check the DD bit */
910 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
913 nmb = rte_rxmbuf_alloc(rxq->mp);
918 rxe = &sw_ring[rx_id];
920 if (rx_id == rxq->nb_rx_desc)
923 /* Prefetch next mbuf */
924 rte_prefetch0(sw_ring[rx_id].mbuf);
927 * When next RX descriptor is on a cache line boundary,
928 * prefetch the next 4 RX descriptors and next 8 pointers
931 if ((rx_id & 0x3) == 0) {
932 rte_prefetch0(&rx_ring[rx_id]);
933 rte_prefetch0(&sw_ring[rx_id]);
939 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
941 /* Set data buffer address and data length of the mbuf */
942 rxdp->read.hdr_addr = dma_addr;
943 rxdp->read.pkt_addr = dma_addr;
944 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
945 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
946 rxm->data_len = rx_packet_len;
947 rxm->data_off = RTE_PKTMBUF_HEADROOM;
950 * If this is the first buffer of the received packet, set the
951 * pointer to the first mbuf of the packet and initialize its
952 * context. Otherwise, update the total length and the number
953 * of segments of the current scattered packet, and update the
954 * pointer to the last mbuf of the current packet.
958 first_seg->nb_segs = 1;
959 first_seg->pkt_len = rx_packet_len;
962 (uint16_t)(first_seg->pkt_len +
964 first_seg->nb_segs++;
965 last_seg->next = rxm;
969 * If this is not the last buffer of the received packet,
970 * update the pointer to the last mbuf of the current scattered
971 * packet and continue to parse the RX ring.
973 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
979 * This is the last buffer of the received packet. If the CRC
980 * is not stripped by the hardware:
981 * - Subtract the CRC length from the total packet length.
982 * - If the last buffer only contains the whole CRC or a part
983 * of it, free the mbuf associated to the last buffer. If part
984 * of the CRC is also contained in the previous mbuf, subtract
985 * the length of that CRC part from the data length of the
989 if (unlikely(rxq->crc_len > 0)) {
990 first_seg->pkt_len -= ETHER_CRC_LEN;
991 if (rx_packet_len <= ETHER_CRC_LEN) {
992 rte_pktmbuf_free_seg(rxm);
993 first_seg->nb_segs--;
995 (uint16_t)(last_seg->data_len -
996 (ETHER_CRC_LEN - rx_packet_len));
997 last_seg->next = NULL;
999 rxm->data_len = (uint16_t)(rx_packet_len -
1003 first_seg->port = rxq->port_id;
1004 first_seg->vlan_tci = (rx_status &
1005 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1006 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1007 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1008 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1009 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1010 first_seg->ol_flags = pkt_flags;
1011 if (pkt_flags & PKT_RX_RSS_HASH)
1013 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1015 /* Prefetch data of first segment, if configured to do so. */
1016 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1017 first_seg->data_off));
1018 rx_pkts[nb_rx++] = first_seg;
1022 /* Record index of the next RX descriptor to probe. */
1023 rxq->rx_tail = rx_id;
1024 rxq->pkt_first_seg = first_seg;
1025 rxq->pkt_last_seg = last_seg;
1028 * If the number of free RX descriptors is greater than the RX free
1029 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1030 * register. Update the RDT with the value of the last processed RX
1031 * descriptor minus 1, to guarantee that the RDT register is never
1032 * equal to the RDH register, which creates a "full" ring situtation
1033 * from the hardware point of view.
1035 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1036 if (nb_hold > rxq->rx_free_thresh) {
1037 rx_id = (uint16_t)(rx_id == 0 ?
1038 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1039 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1042 rxq->nb_rx_hold = nb_hold;
1047 /* Check if the context descriptor is needed for TX offloading */
1048 static inline uint16_t
1049 i40e_calc_context_desc(uint16_t flags)
1053 #ifdef RTE_LIBRTE_IEEE1588
1054 mask |= PKT_TX_IEEE1588_TMST;
1063 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1065 struct i40e_tx_queue *txq;
1066 struct i40e_tx_entry *sw_ring;
1067 struct i40e_tx_entry *txe, *txn;
1068 volatile struct i40e_tx_desc *txd;
1069 volatile struct i40e_tx_desc *txr;
1070 struct rte_mbuf *tx_pkt;
1071 struct rte_mbuf *m_seg;
1085 uint64_t buf_dma_addr;
1088 sw_ring = txq->sw_ring;
1090 tx_id = txq->tx_tail;
1091 txe = &sw_ring[tx_id];
1093 /* Check if the descriptor ring needs to be cleaned. */
1094 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1095 i40e_xmit_cleanup(txq);
1097 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1103 tx_pkt = *tx_pkts++;
1104 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1106 ol_flags = tx_pkt->ol_flags;
1107 l2_len = tx_pkt->l2_len;
1108 l3_len = tx_pkt->l3_len;
1110 /* Calculate the number of context descriptors needed. */
1111 nb_ctx = i40e_calc_context_desc(ol_flags);
1114 * The number of descriptors that must be allocated for
1115 * a packet equals to the number of the segments of that
1116 * packet plus 1 context descriptor if needed.
1118 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1119 tx_last = (uint16_t)(tx_id + nb_used - 1);
1122 if (tx_last >= txq->nb_tx_desc)
1123 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1125 if (nb_used > txq->nb_tx_free) {
1126 if (i40e_xmit_cleanup(txq) != 0) {
1131 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1132 while (nb_used > txq->nb_tx_free) {
1133 if (i40e_xmit_cleanup(txq) != 0) {
1142 /* Descriptor based VLAN insertion */
1143 if (ol_flags & PKT_TX_VLAN_PKT) {
1144 tx_flags |= tx_pkt->vlan_tci <<
1145 I40E_TX_FLAG_L2TAG1_SHIFT;
1146 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1147 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1148 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1149 I40E_TX_FLAG_L2TAG1_SHIFT;
1152 /* Always enable CRC offload insertion */
1153 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1155 /* Enable checksum offloading */
1156 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1159 if (unlikely(nb_ctx)) {
1160 /* Setup TX context descriptor if required */
1161 volatile struct i40e_tx_context_desc *ctx_txd =
1162 (volatile struct i40e_tx_context_desc *)\
1164 uint32_t cd_tunneling_params = 0;
1165 uint16_t cd_l2tag2 = 0;
1166 uint64_t cd_type_cmd_tso_mss =
1167 I40E_TX_DESC_DTYPE_CONTEXT;
1169 txn = &sw_ring[txe->next_id];
1170 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1171 if (txe->mbuf != NULL) {
1172 rte_pktmbuf_free_seg(txe->mbuf);
1175 #ifdef RTE_LIBRTE_IEEE1588
1176 if (ol_flags & PKT_TX_IEEE1588_TMST)
1177 cd_type_cmd_tso_mss |=
1178 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1179 I40E_TXD_CTX_QW1_CMD_SHIFT);
1181 ctx_txd->tunneling_params =
1182 rte_cpu_to_le_32(cd_tunneling_params);
1183 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1184 ctx_txd->type_cmd_tso_mss =
1185 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1186 txe->last_id = tx_last;
1187 tx_id = txe->next_id;
1194 txn = &sw_ring[txe->next_id];
1197 rte_pktmbuf_free_seg(txe->mbuf);
1200 /* Setup TX Descriptor */
1201 slen = m_seg->data_len;
1202 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1203 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1204 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1205 td_offset, slen, td_tag);
1206 txe->last_id = tx_last;
1207 tx_id = txe->next_id;
1209 m_seg = m_seg->next;
1210 } while (m_seg != NULL);
1212 /* The last packet data descriptor needs End Of Packet (EOP) */
1213 td_cmd |= I40E_TX_DESC_CMD_EOP;
1214 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1215 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1217 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1218 PMD_TX_FREE_LOG(DEBUG,
1219 "Setting RS bit on TXD id="
1220 "%4u (port=%d queue=%d)",
1221 tx_last, txq->port_id, txq->queue_id);
1223 td_cmd |= I40E_TX_DESC_CMD_RS;
1225 /* Update txq RS bit counters */
1226 txq->nb_tx_used = 0;
1229 txd->cmd_type_offset_bsz |=
1230 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1231 I40E_TXD_QW1_CMD_SHIFT);
1237 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1238 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1239 (unsigned) tx_id, (unsigned) nb_tx);
1241 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1242 txq->tx_tail = tx_id;
1247 static inline int __attribute__((always_inline))
1248 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1250 struct i40e_tx_entry *txep;
1253 if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1254 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1257 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1259 for (i = 0; i < txq->tx_rs_thresh; i++)
1260 rte_prefetch0((txep + i)->mbuf);
1262 if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1263 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1264 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1268 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1269 rte_pktmbuf_free_seg(txep->mbuf);
1274 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1275 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1276 if (txq->tx_next_dd >= txq->nb_tx_desc)
1277 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1279 return txq->tx_rs_thresh;
1282 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1283 I40E_TX_DESC_CMD_EOP)
1285 /* Populate 4 descriptors with data from 4 mbufs */
1287 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1292 for (i = 0; i < 4; i++, txdp++, pkts++) {
1293 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1294 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1295 txdp->cmd_type_offset_bsz =
1296 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1297 (*pkts)->data_len, 0);
1301 /* Populate 1 descriptor with data from 1 mbuf */
1303 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1307 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1308 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1309 txdp->cmd_type_offset_bsz =
1310 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1311 (*pkts)->data_len, 0);
1314 /* Fill hardware descriptor ring with mbuf data */
1316 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1317 struct rte_mbuf **pkts,
1320 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1321 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1322 const int N_PER_LOOP = 4;
1323 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1324 int mainpart, leftover;
1327 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1328 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1329 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1330 for (j = 0; j < N_PER_LOOP; ++j) {
1331 (txep + i + j)->mbuf = *(pkts + i + j);
1333 tx4(txdp + i, pkts + i);
1335 if (unlikely(leftover > 0)) {
1336 for (i = 0; i < leftover; ++i) {
1337 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1338 tx1(txdp + mainpart + i, pkts + mainpart + i);
1343 static inline uint16_t
1344 tx_xmit_pkts(struct i40e_tx_queue *txq,
1345 struct rte_mbuf **tx_pkts,
1348 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1352 * Begin scanning the H/W ring for done descriptors when the number
1353 * of available descriptors drops below tx_free_thresh. For each done
1354 * descriptor, free the associated buffer.
1356 if (txq->nb_tx_free < txq->tx_free_thresh)
1357 i40e_tx_free_bufs(txq);
1359 /* Use available descriptor only */
1360 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1361 if (unlikely(!nb_pkts))
1364 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1365 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1366 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1367 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1368 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1369 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1370 I40E_TXD_QW1_CMD_SHIFT);
1371 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1375 /* Fill hardware descriptor ring with mbuf data */
1376 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1377 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1379 /* Determin if RS bit needs to be set */
1380 if (txq->tx_tail > txq->tx_next_rs) {
1381 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1382 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1383 I40E_TXD_QW1_CMD_SHIFT);
1385 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1386 if (txq->tx_next_rs >= txq->nb_tx_desc)
1387 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1390 if (txq->tx_tail >= txq->nb_tx_desc)
1393 /* Update the tx tail register */
1395 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1401 i40e_xmit_pkts_simple(void *tx_queue,
1402 struct rte_mbuf **tx_pkts,
1407 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1408 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1412 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1415 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1416 &tx_pkts[nb_tx], num);
1417 nb_tx = (uint16_t)(nb_tx + ret);
1418 nb_pkts = (uint16_t)(nb_pkts - ret);
1427 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1429 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1430 struct i40e_rx_queue *rxq;
1432 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1433 uint16_t q_base = vsi->base_queue;
1435 PMD_INIT_FUNC_TRACE();
1437 if (rx_queue_id < dev->data->nb_rx_queues) {
1438 rxq = dev->data->rx_queues[rx_queue_id];
1440 err = i40e_alloc_rx_queue_mbufs(rxq);
1442 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf\n");
1448 /* Init the RX tail regieter. */
1449 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1451 err = i40e_switch_rx_queue(hw, rx_queue_id + q_base, TRUE);
1454 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on\n",
1457 i40e_rx_queue_release_mbufs(rxq);
1458 i40e_reset_rx_queue(rxq);
1466 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1468 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1469 struct i40e_rx_queue *rxq;
1471 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1472 uint16_t q_base = vsi->base_queue;
1474 if (rx_queue_id < dev->data->nb_rx_queues) {
1475 rxq = dev->data->rx_queues[rx_queue_id];
1477 err = i40e_switch_rx_queue(hw, rx_queue_id + q_base, FALSE);
1480 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off\n",
1484 i40e_rx_queue_release_mbufs(rxq);
1485 i40e_reset_rx_queue(rxq);
1492 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1494 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1496 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1497 uint16_t q_base = vsi->base_queue;
1499 PMD_INIT_FUNC_TRACE();
1501 if (tx_queue_id < dev->data->nb_tx_queues) {
1502 err = i40e_switch_tx_queue(hw, tx_queue_id + q_base, TRUE);
1504 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on\n",
1512 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1514 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1515 struct i40e_tx_queue *txq;
1517 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1518 uint16_t q_base = vsi->base_queue;
1520 if (tx_queue_id < dev->data->nb_tx_queues) {
1521 txq = dev->data->tx_queues[tx_queue_id];
1523 err = i40e_switch_tx_queue(hw, tx_queue_id + q_base, FALSE);
1526 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of\n",
1531 i40e_tx_queue_release_mbufs(txq);
1532 i40e_reset_tx_queue(txq);
1539 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1542 unsigned int socket_id,
1543 const struct rte_eth_rxconf *rx_conf,
1544 struct rte_mempool *mp)
1546 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1547 struct i40e_rx_queue *rxq;
1548 const struct rte_memzone *rz;
1551 int use_def_burst_func = 1;
1553 if (!vsi || queue_idx >= vsi->nb_qps) {
1554 PMD_DRV_LOG(ERR, "VSI not available or queue "
1555 "index exceeds the maximum\n");
1556 return I40E_ERR_PARAM;
1558 if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1559 (nb_desc > I40E_MAX_RING_DESC) ||
1560 (nb_desc < I40E_MIN_RING_DESC)) {
1561 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1562 "invalid\n", nb_desc);
1563 return I40E_ERR_PARAM;
1566 /* Free memory if needed */
1567 if (dev->data->rx_queues[queue_idx]) {
1568 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1569 dev->data->rx_queues[queue_idx] = NULL;
1572 /* Allocate the rx queue data structure */
1573 rxq = rte_zmalloc_socket("i40e rx queue",
1574 sizeof(struct i40e_rx_queue),
1578 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1579 "rx queue data structure\n");
1583 rxq->nb_rx_desc = nb_desc;
1584 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1585 rxq->queue_id = queue_idx;
1586 rxq->reg_idx = vsi->base_queue + queue_idx;
1587 rxq->port_id = dev->data->port_id;
1588 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1590 rxq->drop_en = rx_conf->rx_drop_en;
1592 rxq->start_rx_per_q = rx_conf->start_rx_per_q;
1594 /* Allocate the maximun number of RX ring hardware descriptor. */
1595 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1596 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1597 rz = i40e_ring_dma_zone_reserve(dev,
1603 i40e_dev_rx_queue_release(rxq);
1604 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX\n");
1608 /* Zero all the descriptors in the ring. */
1609 memset(rz->addr, 0, ring_size);
1611 #ifdef RTE_LIBRTE_XEN_DOM0
1612 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1614 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1617 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1619 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1620 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1625 /* Allocate the software ring. */
1627 rte_zmalloc_socket("i40e rx sw ring",
1628 sizeof(struct i40e_rx_entry) * len,
1631 if (!rxq->sw_ring) {
1632 i40e_dev_rx_queue_release(rxq);
1633 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring\n");
1637 i40e_reset_rx_queue(rxq);
1639 dev->data->rx_queues[queue_idx] = rxq;
1641 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1643 if (!use_def_burst_func && !dev->data->scattered_rx) {
1644 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1645 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1646 "satisfied. Rx Burst Bulk Alloc function will be "
1647 "used on port=%d, queue=%d.\n",
1648 rxq->port_id, rxq->queue_id);
1649 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1650 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1652 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1653 "not satisfied, Scattered Rx is requested, "
1654 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1655 "not enabled on port=%d, queue=%d.\n",
1656 rxq->port_id, rxq->queue_id);
1663 i40e_dev_rx_queue_release(void *rxq)
1665 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1668 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL\n");
1672 i40e_rx_queue_release_mbufs(q);
1673 rte_free(q->sw_ring);
1678 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1680 #define I40E_RXQ_SCAN_INTERVAL 4
1681 volatile union i40e_rx_desc *rxdp;
1682 struct i40e_rx_queue *rxq;
1685 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1686 PMD_DRV_LOG(ERR, "Invalid RX queue id %u\n", rx_queue_id);
1690 rxq = dev->data->rx_queues[rx_queue_id];
1691 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1692 while ((desc < rxq->nb_rx_desc) &&
1693 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1694 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1695 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1697 * Check the DD bit of a rx descriptor of each 4 in a group,
1698 * to avoid checking too frequently and downgrading performance
1701 desc += I40E_RXQ_SCAN_INTERVAL;
1702 rxdp += I40E_RXQ_SCAN_INTERVAL;
1703 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1704 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1705 desc - rxq->nb_rx_desc]);
1712 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1714 volatile union i40e_rx_desc *rxdp;
1715 struct i40e_rx_queue *rxq = rx_queue;
1719 if (unlikely(offset >= rxq->nb_rx_desc)) {
1720 PMD_DRV_LOG(ERR, "Invalid RX queue id %u\n", offset);
1724 desc = rxq->rx_tail + offset;
1725 if (desc >= rxq->nb_rx_desc)
1726 desc -= rxq->nb_rx_desc;
1728 rxdp = &(rxq->rx_ring[desc]);
1730 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1731 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1732 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1738 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1741 unsigned int socket_id,
1742 const struct rte_eth_txconf *tx_conf)
1744 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1745 struct i40e_tx_queue *txq;
1746 const struct rte_memzone *tz;
1748 uint16_t tx_rs_thresh, tx_free_thresh;
1750 if (!vsi || queue_idx >= vsi->nb_qps) {
1751 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1752 "exceeds the maximum\n", queue_idx);
1753 return I40E_ERR_PARAM;
1756 if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
1757 (nb_desc > I40E_MAX_RING_DESC) ||
1758 (nb_desc < I40E_MIN_RING_DESC)) {
1759 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1760 "invalid\n", nb_desc);
1761 return I40E_ERR_PARAM;
1765 * The following two parameters control the setting of the RS bit on
1766 * transmit descriptors. TX descriptors will have their RS bit set
1767 * after txq->tx_rs_thresh descriptors have been used. The TX
1768 * descriptor ring will be cleaned after txq->tx_free_thresh
1769 * descriptors are used or if the number of descriptors required to
1770 * transmit a packet is greater than the number of free TX descriptors.
1772 * The following constraints must be satisfied:
1773 * - tx_rs_thresh must be greater than 0.
1774 * - tx_rs_thresh must be less than the size of the ring minus 2.
1775 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1776 * - tx_rs_thresh must be a divisor of the ring size.
1777 * - tx_free_thresh must be greater than 0.
1778 * - tx_free_thresh must be less than the size of the ring minus 3.
1780 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1781 * race condition, hence the maximum threshold constraints. When set
1782 * to zero use default values.
1784 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1785 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1786 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1787 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1788 if (tx_rs_thresh >= (nb_desc - 2)) {
1789 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1790 "number of TX descriptors minus 2. "
1791 "(tx_rs_thresh=%u port=%d queue=%d)\n",
1792 (unsigned int)tx_rs_thresh,
1793 (int)dev->data->port_id,
1795 return I40E_ERR_PARAM;
1797 if (tx_free_thresh >= (nb_desc - 3)) {
1798 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than the "
1799 "tx_free_thresh must be less than the "
1800 "number of TX descriptors minus 3. "
1801 "(tx_free_thresh=%u port=%d queue=%d)\n",
1802 (unsigned int)tx_free_thresh,
1803 (int)dev->data->port_id,
1805 return I40E_ERR_PARAM;
1807 if (tx_rs_thresh > tx_free_thresh) {
1808 RTE_LOG(ERR, PMD, "tx_rs_thresh must be less than or "
1809 "equal to tx_free_thresh. (tx_free_thresh=%u"
1810 " tx_rs_thresh=%u port=%d queue=%d)\n",
1811 (unsigned int)tx_free_thresh,
1812 (unsigned int)tx_rs_thresh,
1813 (int)dev->data->port_id,
1815 return I40E_ERR_PARAM;
1817 if ((nb_desc % tx_rs_thresh) != 0) {
1818 RTE_LOG(ERR, PMD, "tx_rs_thresh must be a divisor of the "
1819 "number of TX descriptors. (tx_rs_thresh=%u"
1820 " port=%d queue=%d)\n",
1821 (unsigned int)tx_rs_thresh,
1822 (int)dev->data->port_id,
1824 return I40E_ERR_PARAM;
1826 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1827 RTE_LOG(ERR, PMD, "TX WTHRESH must be set to 0 if "
1828 "tx_rs_thresh is greater than 1. "
1829 "(tx_rs_thresh=%u port=%d queue=%d)\n",
1830 (unsigned int)tx_rs_thresh,
1831 (int)dev->data->port_id,
1833 return I40E_ERR_PARAM;
1836 /* Free memory if needed. */
1837 if (dev->data->tx_queues[queue_idx]) {
1838 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
1839 dev->data->tx_queues[queue_idx] = NULL;
1842 /* Allocate the TX queue data structure. */
1843 txq = rte_zmalloc_socket("i40e tx queue",
1844 sizeof(struct i40e_tx_queue),
1848 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1849 "tx queue structure\n");
1853 /* Allocate TX hardware ring descriptors. */
1854 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
1855 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1856 tz = i40e_ring_dma_zone_reserve(dev,
1862 i40e_dev_tx_queue_release(txq);
1863 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX\n");
1867 txq->nb_tx_desc = nb_desc;
1868 txq->tx_rs_thresh = tx_rs_thresh;
1869 txq->tx_free_thresh = tx_free_thresh;
1870 txq->pthresh = tx_conf->tx_thresh.pthresh;
1871 txq->hthresh = tx_conf->tx_thresh.hthresh;
1872 txq->wthresh = tx_conf->tx_thresh.wthresh;
1873 txq->queue_id = queue_idx;
1874 txq->reg_idx = vsi->base_queue + queue_idx;
1875 txq->port_id = dev->data->port_id;
1876 txq->txq_flags = tx_conf->txq_flags;
1878 txq->start_tx_per_q = tx_conf->start_tx_per_q;
1880 #ifdef RTE_LIBRTE_XEN_DOM0
1881 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1883 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
1885 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
1887 /* Allocate software ring */
1889 rte_zmalloc_socket("i40e tx sw ring",
1890 sizeof(struct i40e_tx_entry) * nb_desc,
1893 if (!txq->sw_ring) {
1894 i40e_dev_tx_queue_release(txq);
1895 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring\n");
1899 i40e_reset_tx_queue(txq);
1901 dev->data->tx_queues[queue_idx] = txq;
1903 /* Use a simple TX queue without offloads or multi segs if possible */
1904 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
1905 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
1906 PMD_INIT_LOG(INFO, "Using simple tx path\n");
1907 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
1909 PMD_INIT_LOG(INFO, "Using full-featured tx path\n");
1910 dev->tx_pkt_burst = i40e_xmit_pkts;
1917 i40e_dev_tx_queue_release(void *txq)
1919 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
1922 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL\n");
1926 i40e_tx_queue_release_mbufs(q);
1927 rte_free(q->sw_ring);
1931 static const struct rte_memzone *
1932 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
1933 const char *ring_name,
1938 char z_name[RTE_MEMZONE_NAMESIZE];
1939 const struct rte_memzone *mz;
1941 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1942 dev->driver->pci_drv.name, ring_name,
1943 dev->data->port_id, queue_id);
1944 mz = rte_memzone_lookup(z_name);
1948 #ifdef RTE_LIBRTE_XEN_DOM0
1949 return rte_memzone_reserve_bounded(z_name, ring_size,
1950 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
1952 return rte_memzone_reserve_aligned(z_name, ring_size,
1953 socket_id, 0, I40E_ALIGN);
1958 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
1962 if (!rxq || !rxq->sw_ring) {
1963 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL\n");
1967 for (i = 0; i < rxq->nb_rx_desc; i++) {
1968 if (rxq->sw_ring[i].mbuf) {
1969 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1970 rxq->sw_ring[i].mbuf = NULL;
1973 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1974 if (rxq->rx_nb_avail == 0)
1976 for (i = 0; i < rxq->rx_nb_avail; i++) {
1977 struct rte_mbuf *mbuf;
1979 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
1980 rte_pktmbuf_free_seg(mbuf);
1982 rxq->rx_nb_avail = 0;
1983 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1987 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
1992 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1993 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
1994 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
1996 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1997 len = rxq->nb_rx_desc;
1999 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2000 ((volatile char *)rxq->rx_ring)[i] = 0;
2002 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2003 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2004 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2005 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2007 rxq->rx_nb_avail = 0;
2008 rxq->rx_next_avail = 0;
2009 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2010 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2012 rxq->nb_rx_hold = 0;
2013 rxq->pkt_first_seg = NULL;
2014 rxq->pkt_last_seg = NULL;
2018 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2022 if (!txq || !txq->sw_ring) {
2023 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL\n");
2027 for (i = 0; i < txq->nb_tx_desc; i++) {
2028 if (txq->sw_ring[i].mbuf) {
2029 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2030 txq->sw_ring[i].mbuf = NULL;
2036 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2038 struct i40e_tx_entry *txe;
2039 uint16_t i, prev, size;
2042 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL\n");
2047 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2048 for (i = 0; i < size; i++)
2049 ((volatile char *)txq->tx_ring)[i] = 0;
2051 prev = (uint16_t)(txq->nb_tx_desc - 1);
2052 for (i = 0; i < txq->nb_tx_desc; i++) {
2053 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2055 txd[i].cmd_type_offset_bsz =
2056 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2059 txe[prev].next_id = i;
2063 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2064 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2067 txq->nb_tx_used = 0;
2069 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2070 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2073 /* Init the TX queue in hardware */
2075 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2077 enum i40e_status_code err = I40E_SUCCESS;
2078 struct i40e_vsi *vsi = txq->vsi;
2079 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2080 uint16_t pf_q = txq->reg_idx;
2081 struct i40e_hmc_obj_txq tx_ctx;
2084 /* clear the context structure first */
2085 memset(&tx_ctx, 0, sizeof(tx_ctx));
2086 tx_ctx.new_context = 1;
2087 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2088 tx_ctx.qlen = txq->nb_tx_desc;
2089 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2091 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2092 if (err != I40E_SUCCESS) {
2093 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context\n");
2097 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2098 if (err != I40E_SUCCESS) {
2099 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context\n");
2103 /* Now associate this queue with this PCI function */
2104 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2105 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2106 I40E_QTX_CTL_PF_INDX_MASK);
2107 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2108 I40E_WRITE_FLUSH(hw);
2110 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2116 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2118 struct i40e_rx_entry *rxe = rxq->sw_ring;
2122 for (i = 0; i < rxq->nb_rx_desc; i++) {
2123 volatile union i40e_rx_desc *rxd;
2124 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2126 if (unlikely(!mbuf)) {
2127 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX\n");
2131 rte_mbuf_refcnt_set(mbuf, 1);
2133 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2135 mbuf->port = rxq->port_id;
2138 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2140 rxd = &rxq->rx_ring[i];
2141 rxd->read.pkt_addr = dma_addr;
2142 rxd->read.hdr_addr = dma_addr;
2143 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2144 rxd->read.rsvd1 = 0;
2145 rxd->read.rsvd2 = 0;
2146 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2155 * Calculate the buffer length, and check the jumbo frame
2156 * and maximum packet length.
2159 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2161 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2162 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2163 struct rte_eth_dev_data *data = pf->dev_data;
2164 struct rte_pktmbuf_pool_private *mbp_priv =
2165 rte_mempool_get_priv(rxq->mp);
2166 uint16_t buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2167 RTE_PKTMBUF_HEADROOM);
2170 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2171 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2172 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2173 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2174 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2175 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2176 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2177 rxq->hs_mode = i40e_header_split_enabled;
2179 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2181 rxq->rx_hdr_len = 0;
2182 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2183 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2184 rxq->hs_mode = i40e_header_split_none;
2188 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2189 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2190 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2191 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2192 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2193 PMD_DRV_LOG(ERR, "maximum packet length must "
2194 "be larger than %u and smaller than %u,"
2195 "as jumbo frame is enabled\n",
2196 (uint32_t)ETHER_MAX_LEN,
2197 (uint32_t)I40E_FRAME_SIZE_MAX);
2198 return I40E_ERR_CONFIG;
2201 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2202 rxq->max_pkt_len > ETHER_MAX_LEN) {
2203 PMD_DRV_LOG(ERR, "maximum packet length must be "
2204 "larger than %u and smaller than %u, "
2205 "as jumbo frame is disabled\n",
2206 (uint32_t)ETHER_MIN_LEN,
2207 (uint32_t)ETHER_MAX_LEN);
2208 return I40E_ERR_CONFIG;
2215 /* Init the RX queue in hardware */
2217 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2219 int err = I40E_SUCCESS;
2220 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2221 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2222 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2223 uint16_t pf_q = rxq->reg_idx;
2225 struct i40e_hmc_obj_rxq rx_ctx;
2226 struct rte_pktmbuf_pool_private *mbp_priv;
2228 err = i40e_rx_queue_config(rxq);
2230 PMD_DRV_LOG(ERR, "Failed to config RX queue\n");
2234 /* Clear the context structure first */
2235 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2236 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2237 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2239 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2240 rx_ctx.qlen = rxq->nb_rx_desc;
2241 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2244 rx_ctx.dtype = rxq->hs_mode;
2246 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2248 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2249 rx_ctx.rxmax = rxq->max_pkt_len;
2250 rx_ctx.tphrdesc_ena = 1;
2251 rx_ctx.tphwdesc_ena = 1;
2252 rx_ctx.tphdata_ena = 1;
2253 rx_ctx.tphhead_ena = 1;
2254 rx_ctx.lrxqthresh = 2;
2255 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2260 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2261 if (err != I40E_SUCCESS) {
2262 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context\n");
2265 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2266 if (err != I40E_SUCCESS) {
2267 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context\n");
2271 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2273 mbp_priv = rte_mempool_get_priv(rxq->mp);
2274 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2275 RTE_PKTMBUF_HEADROOM);
2277 /* Check if scattered RX needs to be used. */
2278 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2279 dev_data->scattered_rx = 1;
2280 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2283 /* Init the RX tail regieter. */
2284 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2290 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2294 PMD_INIT_FUNC_TRACE();
2296 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2297 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2298 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2301 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2302 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2303 i40e_reset_rx_queue(dev->data->rx_queues[i]);