lib/librte_pmd_i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define I40E_MIN_RING_DESC     64
  61 #define I40E_MAX_RING_DESC     4096
  62 #define I40E_ALIGN             128
  63 #define DEFAULT_TX_RS_THRESH   32
  64 #define DEFAULT_TX_FREE_THRESH 32
  65 #define I40E_MAX_PKT_TYPE      256
  66
  67 #define I40E_VLAN_TAG_SIZE 4
  68 #define I40E_TX_MAX_BURST  32
  69
  70 #define I40E_DMA_MEM_ALIGN 4096
  71
  72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  73                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  74
  75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  76
  77 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  78                 PKT_TX_IP_CKSUM |                \
  79                 PKT_TX_L4_MASK |                 \
  80                 PKT_TX_OUTER_IP_CKSUM)
  81
  82 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
  83         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
  84
  85 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  86         ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
  87
  88 static const struct rte_memzone *
  89 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
  90                            const char *ring_name,
  91                            uint16_t queue_id,
  92                            uint32_t ring_size,
  93                            int socket_id);
  94 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  95                                       struct rte_mbuf **tx_pkts,
  96                                       uint16_t nb_pkts);
  97
  98 /* Translate the rx descriptor status to pkt flags */
  99 static inline uint64_t
 100 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 101 {
 102         uint64_t flags;
 103
 104         /* Check if VLAN packet */
 105         flags = qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 106                                                         PKT_RX_VLAN_PKT : 0;
 107
 108         /* Check if RSS_HASH */
 109         flags |= (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 110                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 111                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 112
 113         /* Check if FDIR Match */
 114         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 115                                                         PKT_RX_FDIR : 0);
 116
 117         return flags;
 118 }
 119
 120 static inline uint64_t
 121 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 122 {
 123         uint64_t flags = 0;
 124         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 125
 126 #define I40E_RX_ERR_BITS 0x3f
 127         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 128                 return flags;
 129         /* If RXE bit set, all other status bits are meaningless */
 130         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 131                 flags |= PKT_RX_MAC_ERR;
 132                 return flags;
 133         }
 134
 135         /* If RECIPE bit set, all other status indications should be ignored */
 136         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 137                 flags |= PKT_RX_RECIP_ERR;
 138                 return flags;
 139         }
 140         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 141                 flags |= PKT_RX_HBUF_OVERFLOW;
 142         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 143                 flags |= PKT_RX_IP_CKSUM_BAD;
 144         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 145                 flags |= PKT_RX_L4_CKSUM_BAD;
 146         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 147                 flags |= PKT_RX_EIP_CKSUM_BAD;
 148         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 149                 flags |= PKT_RX_OVERSIZE;
 150
 151         return flags;
 152 }
 153
 154 /* Translate pkt types to pkt flags */
 155 static inline uint64_t
 156 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
 157 {
 158         uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
 159                                         I40E_RXD_QW1_PTYPE_SHIFT);
 160         static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
 161                 0, /* PTYPE 0 */
 162                 0, /* PTYPE 1 */
 163                 0, /* PTYPE 2 */
 164                 0, /* PTYPE 3 */
 165                 0, /* PTYPE 4 */
 166                 0, /* PTYPE 5 */
 167                 0, /* PTYPE 6 */
 168                 0, /* PTYPE 7 */
 169                 0, /* PTYPE 8 */
 170                 0, /* PTYPE 9 */
 171                 0, /* PTYPE 10 */
 172                 0, /* PTYPE 11 */
 173                 0, /* PTYPE 12 */
 174                 0, /* PTYPE 13 */
 175                 0, /* PTYPE 14 */
 176                 0, /* PTYPE 15 */
 177                 0, /* PTYPE 16 */
 178                 0, /* PTYPE 17 */
 179                 0, /* PTYPE 18 */
 180                 0, /* PTYPE 19 */
 181                 0, /* PTYPE 20 */
 182                 0, /* PTYPE 21 */
 183                 PKT_RX_IPV4_HDR, /* PTYPE 22 */
 184                 PKT_RX_IPV4_HDR, /* PTYPE 23 */
 185                 PKT_RX_IPV4_HDR, /* PTYPE 24 */
 186                 0, /* PTYPE 25 */
 187                 PKT_RX_IPV4_HDR, /* PTYPE 26 */
 188                 PKT_RX_IPV4_HDR, /* PTYPE 27 */
 189                 PKT_RX_IPV4_HDR, /* PTYPE 28 */
 190                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
 191                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
 192                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
 193                 0, /* PTYPE 32 */
 194                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
 195                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
 196                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
 197                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
 198                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
 199                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
 200                 0, /* PTYPE 39 */
 201                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
 202                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
 203                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
 204                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
 205                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
 206                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
 207                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
 208                 0, /* PTYPE 47 */
 209                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
 210                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
 211                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
 212                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
 213                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
 214                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
 215                 0, /* PTYPE 54 */
 216                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
 217                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
 218                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
 219                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
 220                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
 221                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
 222                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
 223                 0, /* PTYPE 62 */
 224                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
 225                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
 226                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
 227                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
 228                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
 229                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
 230                 0, /* PTYPE 69 */
 231                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
 232                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
 233                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
 234                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
 235                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
 236                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
 237                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
 238                 0, /* PTYPE 77 */
 239                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
 240                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
 241                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
 242                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
 243                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
 244                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
 245                 0, /* PTYPE 84 */
 246                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
 247                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
 248                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
 249                 PKT_RX_IPV6_HDR, /* PTYPE 88 */
 250                 PKT_RX_IPV6_HDR, /* PTYPE 89 */
 251                 PKT_RX_IPV6_HDR, /* PTYPE 90 */
 252                 0, /* PTYPE 91 */
 253                 PKT_RX_IPV6_HDR, /* PTYPE 92 */
 254                 PKT_RX_IPV6_HDR, /* PTYPE 93 */
 255                 PKT_RX_IPV6_HDR, /* PTYPE 94 */
 256                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
 257                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
 258                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
 259                 0, /* PTYPE 98 */
 260                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
 261                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
 262                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
 263                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
 264                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
 265                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
 266                 0, /* PTYPE 105 */
 267                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
 268                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
 269                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
 270                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
 271                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
 272                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
 273                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
 274                 0, /* PTYPE 113 */
 275                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
 276                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
 277                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
 278                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
 279                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
 280                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
 281                 0, /* PTYPE 120 */
 282                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
 283                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
 284                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
 285                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
 286                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
 287                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
 288                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
 289                 0, /* PTYPE 128 */
 290                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
 291                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
 292                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
 293                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
 294                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
 295                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
 296                 0, /* PTYPE 135 */
 297                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
 298                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
 299                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
 300                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
 301                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
 302                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
 303                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
 304                 0, /* PTYPE 143 */
 305                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
 306                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
 307                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
 308                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
 309                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
 310                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
 311                 0, /* PTYPE 150 */
 312                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
 313                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
 314                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
 315                 0, /* PTYPE 154 */
 316                 0, /* PTYPE 155 */
 317                 0, /* PTYPE 156 */
 318                 0, /* PTYPE 157 */
 319                 0, /* PTYPE 158 */
 320                 0, /* PTYPE 159 */
 321                 0, /* PTYPE 160 */
 322                 0, /* PTYPE 161 */
 323                 0, /* PTYPE 162 */
 324                 0, /* PTYPE 163 */
 325                 0, /* PTYPE 164 */
 326                 0, /* PTYPE 165 */
 327                 0, /* PTYPE 166 */
 328                 0, /* PTYPE 167 */
 329                 0, /* PTYPE 168 */
 330                 0, /* PTYPE 169 */
 331                 0, /* PTYPE 170 */
 332                 0, /* PTYPE 171 */
 333                 0, /* PTYPE 172 */
 334                 0, /* PTYPE 173 */
 335                 0, /* PTYPE 174 */
 336                 0, /* PTYPE 175 */
 337                 0, /* PTYPE 176 */
 338                 0, /* PTYPE 177 */
 339                 0, /* PTYPE 178 */
 340                 0, /* PTYPE 179 */
 341                 0, /* PTYPE 180 */
 342                 0, /* PTYPE 181 */
 343                 0, /* PTYPE 182 */
 344                 0, /* PTYPE 183 */
 345                 0, /* PTYPE 184 */
 346                 0, /* PTYPE 185 */
 347                 0, /* PTYPE 186 */
 348                 0, /* PTYPE 187 */
 349                 0, /* PTYPE 188 */
 350                 0, /* PTYPE 189 */
 351                 0, /* PTYPE 190 */
 352                 0, /* PTYPE 191 */
 353                 0, /* PTYPE 192 */
 354                 0, /* PTYPE 193 */
 355                 0, /* PTYPE 194 */
 356                 0, /* PTYPE 195 */
 357                 0, /* PTYPE 196 */
 358                 0, /* PTYPE 197 */
 359                 0, /* PTYPE 198 */
 360                 0, /* PTYPE 199 */
 361                 0, /* PTYPE 200 */
 362                 0, /* PTYPE 201 */
 363                 0, /* PTYPE 202 */
 364                 0, /* PTYPE 203 */
 365                 0, /* PTYPE 204 */
 366                 0, /* PTYPE 205 */
 367                 0, /* PTYPE 206 */
 368                 0, /* PTYPE 207 */
 369                 0, /* PTYPE 208 */
 370                 0, /* PTYPE 209 */
 371                 0, /* PTYPE 210 */
 372                 0, /* PTYPE 211 */
 373                 0, /* PTYPE 212 */
 374                 0, /* PTYPE 213 */
 375                 0, /* PTYPE 214 */
 376                 0, /* PTYPE 215 */
 377                 0, /* PTYPE 216 */
 378                 0, /* PTYPE 217 */
 379                 0, /* PTYPE 218 */
 380                 0, /* PTYPE 219 */
 381                 0, /* PTYPE 220 */
 382                 0, /* PTYPE 221 */
 383                 0, /* PTYPE 222 */
 384                 0, /* PTYPE 223 */
 385                 0, /* PTYPE 224 */
 386                 0, /* PTYPE 225 */
 387                 0, /* PTYPE 226 */
 388                 0, /* PTYPE 227 */
 389                 0, /* PTYPE 228 */
 390                 0, /* PTYPE 229 */
 391                 0, /* PTYPE 230 */
 392                 0, /* PTYPE 231 */
 393                 0, /* PTYPE 232 */
 394                 0, /* PTYPE 233 */
 395                 0, /* PTYPE 234 */
 396                 0, /* PTYPE 235 */
 397                 0, /* PTYPE 236 */
 398                 0, /* PTYPE 237 */
 399                 0, /* PTYPE 238 */
 400                 0, /* PTYPE 239 */
 401                 0, /* PTYPE 240 */
 402                 0, /* PTYPE 241 */
 403                 0, /* PTYPE 242 */
 404                 0, /* PTYPE 243 */
 405                 0, /* PTYPE 244 */
 406                 0, /* PTYPE 245 */
 407                 0, /* PTYPE 246 */
 408                 0, /* PTYPE 247 */
 409                 0, /* PTYPE 248 */
 410                 0, /* PTYPE 249 */
 411                 0, /* PTYPE 250 */
 412                 0, /* PTYPE 251 */
 413                 0, /* PTYPE 252 */
 414                 0, /* PTYPE 253 */
 415                 0, /* PTYPE 254 */
 416                 0, /* PTYPE 255 */
 417         };
 418
 419         return ip_ptype_map[ptype];
 420 }
 421
 422 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 423 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 424 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 425 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 426 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 427
 428 static inline uint64_t
 429 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 430 {
 431         uint64_t flags = 0;
 432 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 433         uint16_t flexbh, flexbl;
 434
 435         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 436                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 437                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 438         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 439                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 440                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 441
 442
 443         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 444                 mb->hash.fdir.hi =
 445                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 446                 flags |= PKT_RX_FDIR_ID;
 447         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 448                 mb->hash.fdir.hi =
 449                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 450                 flags |= PKT_RX_FDIR_FLX;
 451         }
 452         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 453                 mb->hash.fdir.lo =
 454                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 455                 flags |= PKT_RX_FDIR_FLX;
 456         }
 457 #else
 458         mb->hash.fdir.hi =
 459                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 460         flags |= PKT_RX_FDIR_ID;
 461 #endif
 462         return flags;
 463 }
 464 static inline void
 465 i40e_txd_enable_checksum(uint64_t ol_flags,
 466                         uint32_t *td_cmd,
 467                         uint32_t *td_offset,
 468                         uint8_t l2_len,
 469                         uint16_t l3_len,
 470                         uint8_t outer_l2_len,
 471                         uint16_t outer_l3_len,
 472                         uint32_t *cd_tunneling)
 473 {
 474         if (!l2_len) {
 475                 PMD_DRV_LOG(DEBUG, "L2 length set to 0");
 476                 return;
 477         }
 478
 479         if (!l3_len) {
 480                 PMD_DRV_LOG(DEBUG, "L3 length set to 0");
 481                 return;
 482         }
 483
 484         /* UDP tunneling packet TX checksum offload */
 485         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 486
 487                 *td_offset |= (outer_l2_len >> 1)
 488                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 489
 490                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 491                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 492                 else if (ol_flags & PKT_TX_OUTER_IPV4)
 493                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 494                 else if (ol_flags & PKT_TX_OUTER_IPV6)
 495                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 496
 497                 /* Now set the ctx descriptor fields */
 498                 *cd_tunneling |= (outer_l3_len >> 2) <<
 499                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 500                                 (l2_len >> 1) <<
 501                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 502
 503         } else
 504                 *td_offset |= (l2_len >> 1)
 505                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 506
 507         /* Enable L3 checksum offloads */
 508         if (ol_flags & PKT_TX_IP_CKSUM) {
 509                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 510                 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 511         } else if (ol_flags & PKT_TX_IPV4) {
 512                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 513                 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 514         } else if (ol_flags & PKT_TX_IPV6) {
 515                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 516                 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 517         }
 518
 519         /* Enable L4 checksum offloads */
 520         switch (ol_flags & PKT_TX_L4_MASK) {
 521         case PKT_TX_TCP_CKSUM:
 522                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 523                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 524                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 525                 break;
 526         case PKT_TX_SCTP_CKSUM:
 527                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 528                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 529                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 530                 break;
 531         case PKT_TX_UDP_CKSUM:
 532                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 533                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 534                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 535                 break;
 536         default:
 537                 break;
 538         }
 539 }
 540
 541 static inline struct rte_mbuf *
 542 rte_rxmbuf_alloc(struct rte_mempool *mp)
 543 {
 544         struct rte_mbuf *m;
 545
 546         m = __rte_mbuf_raw_alloc(mp);
 547         __rte_mbuf_sanity_check_raw(m, 0);
 548
 549         return m;
 550 }
 551
 552 /* Construct the tx flags */
 553 static inline uint64_t
 554 i40e_build_ctob(uint32_t td_cmd,
 555                 uint32_t td_offset,
 556                 unsigned int size,
 557                 uint32_t td_tag)
 558 {
 559         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 560                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 561                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 562                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 563                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 564 }
 565
 566 static inline int
 567 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 568 {
 569         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 570         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 571         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 572         uint16_t nb_tx_desc = txq->nb_tx_desc;
 573         uint16_t desc_to_clean_to;
 574         uint16_t nb_tx_to_clean;
 575
 576         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 577         if (desc_to_clean_to >= nb_tx_desc)
 578                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 579
 580         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 581         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
 582                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
 583                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 584                         "(port=%d queue=%d)", desc_to_clean_to,
 585                                 txq->port_id, txq->queue_id);
 586                 return -1;
 587         }
 588
 589         if (last_desc_cleaned > desc_to_clean_to)
 590                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 591                                                         desc_to_clean_to);
 592         else
 593                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 594                                         last_desc_cleaned);
 595
 596         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 597
 598         txq->last_desc_cleaned = desc_to_clean_to;
 599         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 600
 601         return 0;
 602 }
 603
 604 static inline int
 605 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 606 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 607 #else
 608 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 609 #endif
 610 {
 611         int ret = 0;
 612
 613 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 614         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 615                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 616                              "rxq->rx_free_thresh=%d, "
 617                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 618                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 619                 ret = -EINVAL;
 620         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 621                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 622                              "rxq->rx_free_thresh=%d, "
 623                              "rxq->nb_rx_desc=%d",
 624                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 625                 ret = -EINVAL;
 626         } else if (!(rxq->nb_rx_desc % rxq->rx_free_thresh) == 0) {
 627                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 628                              "rxq->nb_rx_desc=%d, "
 629                              "rxq->rx_free_thresh=%d",
 630                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 631                 ret = -EINVAL;
 632         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 633                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 634                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 635                              "rxq->nb_rx_desc=%d, "
 636                              "I40E_MAX_RING_DESC=%d, "
 637                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 638                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 639                              RTE_PMD_I40E_RX_MAX_BURST);
 640                 ret = -EINVAL;
 641         }
 642 #else
 643         ret = -EINVAL;
 644 #endif
 645
 646         return ret;
 647 }
 648
 649 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 650 #define I40E_LOOK_AHEAD 8
 651 #if (I40E_LOOK_AHEAD != 8)
 652 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 653 #endif
 654 static inline int
 655 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 656 {
 657         volatile union i40e_rx_desc *rxdp;
 658         struct i40e_rx_entry *rxep;
 659         struct rte_mbuf *mb;
 660         uint16_t pkt_len;
 661         uint64_t qword1;
 662         uint32_t rx_status;
 663         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 664         int32_t i, j, nb_rx = 0;
 665         uint64_t pkt_flags;
 666
 667         rxdp = &rxq->rx_ring[rxq->rx_tail];
 668         rxep = &rxq->sw_ring[rxq->rx_tail];
 669
 670         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 671         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 672                                 I40E_RXD_QW1_STATUS_SHIFT;
 673
 674         /* Make sure there is at least 1 packet to receive */
 675         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 676                 return 0;
 677
 678         /**
 679          * Scan LOOK_AHEAD descriptors at a time to determine which
 680          * descriptors reference packets that are ready to be received.
 681          */
 682         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 683                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 684                 /* Read desc statuses backwards to avoid race condition */
 685                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 686                         qword1 = rte_le_to_cpu_64(\
 687                                 rxdp[j].wb.qword1.status_error_len);
 688                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 689                                         I40E_RXD_QW1_STATUS_SHIFT;
 690                 }
 691
 692                 /* Compute how many status bits were set */
 693                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 694                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 695
 696                 nb_rx += nb_dd;
 697
 698                 /* Translate descriptor info to mbuf parameters */
 699                 for (j = 0; j < nb_dd; j++) {
 700                         mb = rxep[j].mbuf;
 701                         qword1 = rte_le_to_cpu_64(\
 702                                 rxdp[j].wb.qword1.status_error_len);
 703                         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 704                                                 I40E_RXD_QW1_STATUS_SHIFT;
 705                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 706                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 707                         mb->data_len = pkt_len;
 708                         mb->pkt_len = pkt_len;
 709                         mb->vlan_tci = rx_status &
 710                                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 711                         rte_le_to_cpu_16(\
 712                                 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
 713                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 714                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 715                         pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 716
 717                         mb->packet_type = (uint16_t)((qword1 &
 718                                         I40E_RXD_QW1_PTYPE_MASK) >>
 719                                         I40E_RXD_QW1_PTYPE_SHIFT);
 720                         if (pkt_flags & PKT_RX_RSS_HASH)
 721                                 mb->hash.rss = rte_le_to_cpu_32(\
 722                                         rxdp[j].wb.qword0.hi_dword.rss);
 723                         if (pkt_flags & PKT_RX_FDIR)
 724                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 725
 726                         mb->ol_flags = pkt_flags;
 727                 }
 728
 729                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 730                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 731
 732                 if (nb_dd != I40E_LOOK_AHEAD)
 733                         break;
 734         }
 735
 736         /* Clear software ring entries */
 737         for (i = 0; i < nb_rx; i++)
 738                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 739
 740         return nb_rx;
 741 }
 742
 743 static inline uint16_t
 744 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 745                         struct rte_mbuf **rx_pkts,
 746                         uint16_t nb_pkts)
 747 {
 748         uint16_t i;
 749         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 750
 751         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 752
 753         for (i = 0; i < nb_pkts; i++)
 754                 rx_pkts[i] = stage[i];
 755
 756         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 757         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 758
 759         return nb_pkts;
 760 }
 761
 762 static inline int
 763 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 764 {
 765         volatile union i40e_rx_desc *rxdp;
 766         struct i40e_rx_entry *rxep;
 767         struct rte_mbuf *mb;
 768         uint16_t alloc_idx, i;
 769         uint64_t dma_addr;
 770         int diag;
 771
 772         /* Allocate buffers in bulk */
 773         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 774                                 (rxq->rx_free_thresh - 1));
 775         rxep = &(rxq->sw_ring[alloc_idx]);
 776         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 777                                         rxq->rx_free_thresh);
 778         if (unlikely(diag != 0)) {
 779                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 780                 return -ENOMEM;
 781         }
 782
 783         rxdp = &rxq->rx_ring[alloc_idx];
 784         for (i = 0; i < rxq->rx_free_thresh; i++) {
 785                 mb = rxep[i].mbuf;
 786                 rte_mbuf_refcnt_set(mb, 1);
 787                 mb->next = NULL;
 788                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 789                 mb->nb_segs = 1;
 790                 mb->port = rxq->port_id;
 791                 dma_addr = rte_cpu_to_le_64(\
 792                         RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
 793                 rxdp[i].read.hdr_addr = dma_addr;
 794                 rxdp[i].read.pkt_addr = dma_addr;
 795         }
 796
 797         /* Update rx tail regsiter */
 798         rte_wmb();
 799         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 800
 801         rxq->rx_free_trigger =
 802                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 803         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 804                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 805
 806         return 0;
 807 }
 808
 809 static inline uint16_t
 810 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 811 {
 812         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 813         uint16_t nb_rx = 0;
 814
 815         if (!nb_pkts)
 816                 return 0;
 817
 818         if (rxq->rx_nb_avail)
 819                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 820
 821         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 822         rxq->rx_next_avail = 0;
 823         rxq->rx_nb_avail = nb_rx;
 824         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 825
 826         if (rxq->rx_tail > rxq->rx_free_trigger) {
 827                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 828                         uint16_t i, j;
 829
 830                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
 831                                    "port_id=%u, queue_id=%u",
 832                                    rxq->port_id, rxq->queue_id);
 833                         rxq->rx_nb_avail = 0;
 834                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 835                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 836                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 837
 838                         return 0;
 839                 }
 840         }
 841
 842         if (rxq->rx_tail >= rxq->nb_rx_desc)
 843                 rxq->rx_tail = 0;
 844
 845         if (rxq->rx_nb_avail)
 846                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 847
 848         return 0;
 849 }
 850
 851 static uint16_t
 852 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 853                           struct rte_mbuf **rx_pkts,
 854                           uint16_t nb_pkts)
 855 {
 856         uint16_t nb_rx = 0, n, count;
 857
 858         if (unlikely(nb_pkts == 0))
 859                 return 0;
 860
 861         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 862                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 863
 864         while (nb_pkts) {
 865                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 866                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 867                 nb_rx = (uint16_t)(nb_rx + count);
 868                 nb_pkts = (uint16_t)(nb_pkts - count);
 869                 if (count < n)
 870                         break;
 871         }
 872
 873         return nb_rx;
 874 }
 875 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 876
 877 uint16_t
 878 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 879 {
 880         struct i40e_rx_queue *rxq;
 881         volatile union i40e_rx_desc *rx_ring;
 882         volatile union i40e_rx_desc *rxdp;
 883         union i40e_rx_desc rxd;
 884         struct i40e_rx_entry *sw_ring;
 885         struct i40e_rx_entry *rxe;
 886         struct rte_mbuf *rxm;
 887         struct rte_mbuf *nmb;
 888         uint16_t nb_rx;
 889         uint32_t rx_status;
 890         uint64_t qword1;
 891         uint16_t rx_packet_len;
 892         uint16_t rx_id, nb_hold;
 893         uint64_t dma_addr;
 894         uint64_t pkt_flags;
 895
 896         nb_rx = 0;
 897         nb_hold = 0;
 898         rxq = rx_queue;
 899         rx_id = rxq->rx_tail;
 900         rx_ring = rxq->rx_ring;
 901         sw_ring = rxq->sw_ring;
 902
 903         while (nb_rx < nb_pkts) {
 904                 rxdp = &rx_ring[rx_id];
 905                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 906                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 907                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 908                 /* Check the DD bit first */
 909                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 910                         break;
 911
 912                 nmb = rte_rxmbuf_alloc(rxq->mp);
 913                 if (unlikely(!nmb))
 914                         break;
 915                 rxd = *rxdp;
 916
 917                 nb_hold++;
 918                 rxe = &sw_ring[rx_id];
 919                 rx_id++;
 920                 if (unlikely(rx_id == rxq->nb_rx_desc))
 921                         rx_id = 0;
 922
 923                 /* Prefetch next mbuf */
 924                 rte_prefetch0(sw_ring[rx_id].mbuf);
 925
 926                 /**
 927                  * When next RX descriptor is on a cache line boundary,
 928                  * prefetch the next 4 RX descriptors and next 8 pointers
 929                  * to mbufs.
 930                  */
 931                 if ((rx_id & 0x3) == 0) {
 932                         rte_prefetch0(&rx_ring[rx_id]);
 933                         rte_prefetch0(&sw_ring[rx_id]);
 934                 }
 935                 rxm = rxe->mbuf;
 936                 rxe->mbuf = nmb;
 937                 dma_addr =
 938                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 939                 rxdp->read.hdr_addr = dma_addr;
 940                 rxdp->read.pkt_addr = dma_addr;
 941
 942                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 943                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 944
 945                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 946                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 947                 rxm->nb_segs = 1;
 948                 rxm->next = NULL;
 949                 rxm->pkt_len = rx_packet_len;
 950                 rxm->data_len = rx_packet_len;
 951                 rxm->port = rxq->port_id;
 952
 953                 rxm->vlan_tci = rx_status &
 954                         (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 955                         rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
 956                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 957                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 958                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 959                 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
 960                                 I40E_RXD_QW1_PTYPE_SHIFT);
 961                 if (pkt_flags & PKT_RX_RSS_HASH)
 962                         rxm->hash.rss =
 963                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 964                 if (pkt_flags & PKT_RX_FDIR)
 965                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 966
 967                 rxm->ol_flags = pkt_flags;
 968
 969                 rx_pkts[nb_rx++] = rxm;
 970         }
 971         rxq->rx_tail = rx_id;
 972
 973         /**
 974          * If the number of free RX descriptors is greater than the RX free
 975          * threshold of the queue, advance the receive tail register of queue.
 976          * Update that register with the value of the last processed RX
 977          * descriptor minus 1.
 978          */
 979         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 980         if (nb_hold > rxq->rx_free_thresh) {
 981                 rx_id = (uint16_t) ((rx_id == 0) ?
 982                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 983                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 984                 nb_hold = 0;
 985         }
 986         rxq->nb_rx_hold = nb_hold;
 987
 988         return nb_rx;
 989 }
 990
 991 uint16_t
 992 i40e_recv_scattered_pkts(void *rx_queue,
 993                          struct rte_mbuf **rx_pkts,
 994                          uint16_t nb_pkts)
 995 {
 996         struct i40e_rx_queue *rxq = rx_queue;
 997         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 998         volatile union i40e_rx_desc *rxdp;
 999         union i40e_rx_desc rxd;
1000         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1001         struct i40e_rx_entry *rxe;
1002         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1003         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1004         struct rte_mbuf *nmb, *rxm;
1005         uint16_t rx_id = rxq->rx_tail;
1006         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1007         uint32_t rx_status;
1008         uint64_t qword1;
1009         uint64_t dma_addr;
1010         uint64_t pkt_flags;
1011
1012         while (nb_rx < nb_pkts) {
1013                 rxdp = &rx_ring[rx_id];
1014                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1015                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1016                                         I40E_RXD_QW1_STATUS_SHIFT;
1017                 /* Check the DD bit */
1018                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1019                         break;
1020
1021                 nmb = rte_rxmbuf_alloc(rxq->mp);
1022                 if (unlikely(!nmb))
1023                         break;
1024                 rxd = *rxdp;
1025                 nb_hold++;
1026                 rxe = &sw_ring[rx_id];
1027                 rx_id++;
1028                 if (rx_id == rxq->nb_rx_desc)
1029                         rx_id = 0;
1030
1031                 /* Prefetch next mbuf */
1032                 rte_prefetch0(sw_ring[rx_id].mbuf);
1033
1034                 /**
1035                  * When next RX descriptor is on a cache line boundary,
1036                  * prefetch the next 4 RX descriptors and next 8 pointers
1037                  * to mbufs.
1038                  */
1039                 if ((rx_id & 0x3) == 0) {
1040                         rte_prefetch0(&rx_ring[rx_id]);
1041                         rte_prefetch0(&sw_ring[rx_id]);
1042                 }
1043
1044                 rxm = rxe->mbuf;
1045                 rxe->mbuf = nmb;
1046                 dma_addr =
1047                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1048
1049                 /* Set data buffer address and data length of the mbuf */
1050                 rxdp->read.hdr_addr = dma_addr;
1051                 rxdp->read.pkt_addr = dma_addr;
1052                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1053                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1054                 rxm->data_len = rx_packet_len;
1055                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1056
1057                 /**
1058                  * If this is the first buffer of the received packet, set the
1059                  * pointer to the first mbuf of the packet and initialize its
1060                  * context. Otherwise, update the total length and the number
1061                  * of segments of the current scattered packet, and update the
1062                  * pointer to the last mbuf of the current packet.
1063                  */
1064                 if (!first_seg) {
1065                         first_seg = rxm;
1066                         first_seg->nb_segs = 1;
1067                         first_seg->pkt_len = rx_packet_len;
1068                 } else {
1069                         first_seg->pkt_len =
1070                                 (uint16_t)(first_seg->pkt_len +
1071                                                 rx_packet_len);
1072                         first_seg->nb_segs++;
1073                         last_seg->next = rxm;
1074                 }
1075
1076                 /**
1077                  * If this is not the last buffer of the received packet,
1078                  * update the pointer to the last mbuf of the current scattered
1079                  * packet and continue to parse the RX ring.
1080                  */
1081                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1082                         last_seg = rxm;
1083                         continue;
1084                 }
1085
1086                 /**
1087                  * This is the last buffer of the received packet. If the CRC
1088                  * is not stripped by the hardware:
1089                  *  - Subtract the CRC length from the total packet length.
1090                  *  - If the last buffer only contains the whole CRC or a part
1091                  *  of it, free the mbuf associated to the last buffer. If part
1092                  *  of the CRC is also contained in the previous mbuf, subtract
1093                  *  the length of that CRC part from the data length of the
1094                  *  previous mbuf.
1095                  */
1096                 rxm->next = NULL;
1097                 if (unlikely(rxq->crc_len > 0)) {
1098                         first_seg->pkt_len -= ETHER_CRC_LEN;
1099                         if (rx_packet_len <= ETHER_CRC_LEN) {
1100                                 rte_pktmbuf_free_seg(rxm);
1101                                 first_seg->nb_segs--;
1102                                 last_seg->data_len =
1103                                         (uint16_t)(last_seg->data_len -
1104                                         (ETHER_CRC_LEN - rx_packet_len));
1105                                 last_seg->next = NULL;
1106                         } else
1107                                 rxm->data_len = (uint16_t)(rx_packet_len -
1108                                                                 ETHER_CRC_LEN);
1109                 }
1110
1111                 first_seg->port = rxq->port_id;
1112                 first_seg->vlan_tci = (rx_status &
1113                         (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1114                         rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1115                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1116                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1117                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1118                 first_seg->packet_type = (uint16_t)((qword1 &
1119                                         I40E_RXD_QW1_PTYPE_MASK) >>
1120                                         I40E_RXD_QW1_PTYPE_SHIFT);
1121                 if (pkt_flags & PKT_RX_RSS_HASH)
1122                         rxm->hash.rss =
1123                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1124                 if (pkt_flags & PKT_RX_FDIR)
1125                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1126
1127                 first_seg->ol_flags = pkt_flags;
1128
1129                 /* Prefetch data of first segment, if configured to do so. */
1130                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1131                         first_seg->data_off));
1132                 rx_pkts[nb_rx++] = first_seg;
1133                 first_seg = NULL;
1134         }
1135
1136         /* Record index of the next RX descriptor to probe. */
1137         rxq->rx_tail = rx_id;
1138         rxq->pkt_first_seg = first_seg;
1139         rxq->pkt_last_seg = last_seg;
1140
1141         /**
1142          * If the number of free RX descriptors is greater than the RX free
1143          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1144          * register. Update the RDT with the value of the last processed RX
1145          * descriptor minus 1, to guarantee that the RDT register is never
1146          * equal to the RDH register, which creates a "full" ring situtation
1147          * from the hardware point of view.
1148          */
1149         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1150         if (nb_hold > rxq->rx_free_thresh) {
1151                 rx_id = (uint16_t)(rx_id == 0 ?
1152                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1153                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1154                 nb_hold = 0;
1155         }
1156         rxq->nb_rx_hold = nb_hold;
1157
1158         return nb_rx;
1159 }
1160
1161 /* Check if the context descriptor is needed for TX offloading */
1162 static inline uint16_t
1163 i40e_calc_context_desc(uint64_t flags)
1164 {
1165         uint64_t mask = 0ULL;
1166
1167         mask |= PKT_TX_OUTER_IP_CKSUM;
1168
1169 #ifdef RTE_LIBRTE_IEEE1588
1170         mask |= PKT_TX_IEEE1588_TMST;
1171 #endif
1172         if (flags & mask)
1173                 return 1;
1174
1175         return 0;
1176 }
1177
1178 uint16_t
1179 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1180 {
1181         struct i40e_tx_queue *txq;
1182         struct i40e_tx_entry *sw_ring;
1183         struct i40e_tx_entry *txe, *txn;
1184         volatile struct i40e_tx_desc *txd;
1185         volatile struct i40e_tx_desc *txr;
1186         struct rte_mbuf *tx_pkt;
1187         struct rte_mbuf *m_seg;
1188         uint32_t cd_tunneling_params;
1189         uint16_t tx_id;
1190         uint16_t nb_tx;
1191         uint32_t td_cmd;
1192         uint32_t td_offset;
1193         uint32_t tx_flags;
1194         uint32_t td_tag;
1195         uint64_t ol_flags;
1196         uint8_t l2_len;
1197         uint16_t l3_len;
1198         uint8_t outer_l2_len;
1199         uint16_t outer_l3_len;
1200         uint16_t nb_used;
1201         uint16_t nb_ctx;
1202         uint16_t tx_last;
1203         uint16_t slen;
1204         uint64_t buf_dma_addr;
1205
1206         txq = tx_queue;
1207         sw_ring = txq->sw_ring;
1208         txr = txq->tx_ring;
1209         tx_id = txq->tx_tail;
1210         txe = &sw_ring[tx_id];
1211
1212         /* Check if the descriptor ring needs to be cleaned. */
1213         if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1214                 i40e_xmit_cleanup(txq);
1215
1216         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1217                 td_cmd = 0;
1218                 td_tag = 0;
1219                 td_offset = 0;
1220                 tx_flags = 0;
1221
1222                 tx_pkt = *tx_pkts++;
1223                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1224
1225                 ol_flags = tx_pkt->ol_flags;
1226                 l2_len = tx_pkt->l2_len;
1227                 l3_len = tx_pkt->l3_len;
1228                 outer_l2_len = tx_pkt->outer_l2_len;
1229                 outer_l3_len = tx_pkt->outer_l3_len;
1230
1231                 /* Calculate the number of context descriptors needed. */
1232                 nb_ctx = i40e_calc_context_desc(ol_flags);
1233
1234                 /**
1235                  * The number of descriptors that must be allocated for
1236                  * a packet equals to the number of the segments of that
1237                  * packet plus 1 context descriptor if needed.
1238                  */
1239                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1240                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1241
1242                 /* Circular ring */
1243                 if (tx_last >= txq->nb_tx_desc)
1244                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1245
1246                 if (nb_used > txq->nb_tx_free) {
1247                         if (i40e_xmit_cleanup(txq) != 0) {
1248                                 if (nb_tx == 0)
1249                                         return 0;
1250                                 goto end_of_tx;
1251                         }
1252                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1253                                 while (nb_used > txq->nb_tx_free) {
1254                                         if (i40e_xmit_cleanup(txq) != 0) {
1255                                                 if (nb_tx == 0)
1256                                                         return 0;
1257                                                 goto end_of_tx;
1258                                         }
1259                                 }
1260                         }
1261                 }
1262
1263                 /* Descriptor based VLAN insertion */
1264                 if (ol_flags & PKT_TX_VLAN_PKT) {
1265                         tx_flags |= tx_pkt->vlan_tci <<
1266                                         I40E_TX_FLAG_L2TAG1_SHIFT;
1267                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1268                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1269                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1270                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1271                 }
1272
1273                 /* Always enable CRC offload insertion */
1274                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1275
1276                 /* Enable checksum offloading */
1277                 cd_tunneling_params = 0;
1278                 if (unlikely(ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)) {
1279                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1280                                 l2_len, l3_len, outer_l2_len,
1281                                 outer_l3_len,
1282                                 &cd_tunneling_params);
1283                 }
1284
1285                 if (unlikely(nb_ctx)) {
1286                         /* Setup TX context descriptor if required */
1287                         volatile struct i40e_tx_context_desc *ctx_txd =
1288                                 (volatile struct i40e_tx_context_desc *)\
1289                                                         &txr[tx_id];
1290                         uint16_t cd_l2tag2 = 0;
1291                         uint64_t cd_type_cmd_tso_mss =
1292                                 I40E_TX_DESC_DTYPE_CONTEXT;
1293
1294                         txn = &sw_ring[txe->next_id];
1295                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1296                         if (txe->mbuf != NULL) {
1297                                 rte_pktmbuf_free_seg(txe->mbuf);
1298                                 txe->mbuf = NULL;
1299                         }
1300 #ifdef RTE_LIBRTE_IEEE1588
1301                         if (ol_flags & PKT_TX_IEEE1588_TMST)
1302                                 cd_type_cmd_tso_mss |=
1303                                         ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1304                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1305 #endif
1306                         ctx_txd->tunneling_params =
1307                                 rte_cpu_to_le_32(cd_tunneling_params);
1308                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1309                         ctx_txd->type_cmd_tso_mss =
1310                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1311                         txe->last_id = tx_last;
1312                         tx_id = txe->next_id;
1313                         txe = txn;
1314                 }
1315
1316                 m_seg = tx_pkt;
1317                 do {
1318                         txd = &txr[tx_id];
1319                         txn = &sw_ring[txe->next_id];
1320
1321                         if (txe->mbuf)
1322                                 rte_pktmbuf_free_seg(txe->mbuf);
1323                         txe->mbuf = m_seg;
1324
1325                         /* Setup TX Descriptor */
1326                         slen = m_seg->data_len;
1327                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1328                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1329                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1330                                                 td_offset, slen, td_tag);
1331                         txe->last_id = tx_last;
1332                         tx_id = txe->next_id;
1333                         txe = txn;
1334                         m_seg = m_seg->next;
1335                 } while (m_seg != NULL);
1336
1337                 /* The last packet data descriptor needs End Of Packet (EOP) */
1338                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1339                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1340                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1341
1342                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1343                         PMD_TX_FREE_LOG(DEBUG,
1344                                         "Setting RS bit on TXD id="
1345                                         "%4u (port=%d queue=%d)",
1346                                         tx_last, txq->port_id, txq->queue_id);
1347
1348                         td_cmd |= I40E_TX_DESC_CMD_RS;
1349
1350                         /* Update txq RS bit counters */
1351                         txq->nb_tx_used = 0;
1352                 }
1353
1354                 txd->cmd_type_offset_bsz |=
1355                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1356                                         I40E_TXD_QW1_CMD_SHIFT);
1357         }
1358
1359 end_of_tx:
1360         rte_wmb();
1361
1362         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1363                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1364                    (unsigned) tx_id, (unsigned) nb_tx);
1365
1366         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1367         txq->tx_tail = tx_id;
1368
1369         return nb_tx;
1370 }
1371
1372 static inline int __attribute__((always_inline))
1373 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1374 {
1375         struct i40e_tx_entry *txep;
1376         uint16_t i;
1377
1378         if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1379                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1380                 return 0;
1381
1382         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1383
1384         for (i = 0; i < txq->tx_rs_thresh; i++)
1385                 rte_prefetch0((txep + i)->mbuf);
1386
1387         if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1388                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1389                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1390                         txep->mbuf = NULL;
1391                 }
1392         } else {
1393                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1394                         rte_pktmbuf_free_seg(txep->mbuf);
1395                         txep->mbuf = NULL;
1396                 }
1397         }
1398
1399         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1400         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1401         if (txq->tx_next_dd >= txq->nb_tx_desc)
1402                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1403
1404         return txq->tx_rs_thresh;
1405 }
1406
1407 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1408                      I40E_TX_DESC_CMD_EOP)
1409
1410 /* Populate 4 descriptors with data from 4 mbufs */
1411 static inline void
1412 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1413 {
1414         uint64_t dma_addr;
1415         uint32_t i;
1416
1417         for (i = 0; i < 4; i++, txdp++, pkts++) {
1418                 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1419                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1420                 txdp->cmd_type_offset_bsz =
1421                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1422                                         (*pkts)->data_len, 0);
1423         }
1424 }
1425
1426 /* Populate 1 descriptor with data from 1 mbuf */
1427 static inline void
1428 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1429 {
1430         uint64_t dma_addr;
1431
1432         dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1433         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1434         txdp->cmd_type_offset_bsz =
1435                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1436                                 (*pkts)->data_len, 0);
1437 }
1438
1439 /* Fill hardware descriptor ring with mbuf data */
1440 static inline void
1441 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1442                      struct rte_mbuf **pkts,
1443                      uint16_t nb_pkts)
1444 {
1445         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1446         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1447         const int N_PER_LOOP = 4;
1448         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1449         int mainpart, leftover;
1450         int i, j;
1451
1452         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1453         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1454         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1455                 for (j = 0; j < N_PER_LOOP; ++j) {
1456                         (txep + i + j)->mbuf = *(pkts + i + j);
1457                 }
1458                 tx4(txdp + i, pkts + i);
1459         }
1460         if (unlikely(leftover > 0)) {
1461                 for (i = 0; i < leftover; ++i) {
1462                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1463                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1464                 }
1465         }
1466 }
1467
1468 static inline uint16_t
1469 tx_xmit_pkts(struct i40e_tx_queue *txq,
1470              struct rte_mbuf **tx_pkts,
1471              uint16_t nb_pkts)
1472 {
1473         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1474         uint16_t n = 0;
1475
1476         /**
1477          * Begin scanning the H/W ring for done descriptors when the number
1478          * of available descriptors drops below tx_free_thresh. For each done
1479          * descriptor, free the associated buffer.
1480          */
1481         if (txq->nb_tx_free < txq->tx_free_thresh)
1482                 i40e_tx_free_bufs(txq);
1483
1484         /* Use available descriptor only */
1485         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1486         if (unlikely(!nb_pkts))
1487                 return 0;
1488
1489         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1490         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1491                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1492                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1493                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1494                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1495                                                 I40E_TXD_QW1_CMD_SHIFT);
1496                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1497                 txq->tx_tail = 0;
1498         }
1499
1500         /* Fill hardware descriptor ring with mbuf data */
1501         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1502         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1503
1504         /* Determin if RS bit needs to be set */
1505         if (txq->tx_tail > txq->tx_next_rs) {
1506                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1507                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1508                                                 I40E_TXD_QW1_CMD_SHIFT);
1509                 txq->tx_next_rs =
1510                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1511                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1512                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1513         }
1514
1515         if (txq->tx_tail >= txq->nb_tx_desc)
1516                 txq->tx_tail = 0;
1517
1518         /* Update the tx tail register */
1519         rte_wmb();
1520         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1521
1522         return nb_pkts;
1523 }
1524
1525 static uint16_t
1526 i40e_xmit_pkts_simple(void *tx_queue,
1527                       struct rte_mbuf **tx_pkts,
1528                       uint16_t nb_pkts)
1529 {
1530         uint16_t nb_tx = 0;
1531
1532         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1533                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1534                                                 tx_pkts, nb_pkts);
1535
1536         while (nb_pkts) {
1537                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1538                                                 I40E_TX_MAX_BURST);
1539
1540                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1541                                                 &tx_pkts[nb_tx], num);
1542                 nb_tx = (uint16_t)(nb_tx + ret);
1543                 nb_pkts = (uint16_t)(nb_pkts - ret);
1544                 if (ret < num)
1545                         break;
1546         }
1547
1548         return nb_tx;
1549 }
1550
1551 /*
1552  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1553  * application used, which assume having sequential ones. But from driver's
1554  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1555  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1556  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1557  * use queue_idx from 0 to 95 to access queues, while real queue would be
1558  * different. This function will do a queue mapping to find VSI the queue
1559  * belongs to.
1560  */
1561 static struct i40e_vsi*
1562 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1563 {
1564         /* the queue in MAIN VSI range */
1565         if (queue_idx < pf->main_vsi->nb_qps)
1566                 return pf->main_vsi;
1567
1568         queue_idx -= pf->main_vsi->nb_qps;
1569
1570         /* queue_idx is greater than VMDQ VSIs range */
1571         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1572                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1573                 return NULL;
1574         }
1575
1576         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1577 }
1578
1579 static uint16_t
1580 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1581 {
1582         /* the queue in MAIN VSI range */
1583         if (queue_idx < pf->main_vsi->nb_qps)
1584                 return queue_idx;
1585
1586         /* It's VMDQ queues */
1587         queue_idx -= pf->main_vsi->nb_qps;
1588
1589         if (pf->nb_cfg_vmdq_vsi)
1590                 return queue_idx % pf->vmdq_nb_qps;
1591         else {
1592                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1593                 return (uint16_t)(-1);
1594         }
1595 }
1596
1597 int
1598 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1599 {
1600         struct i40e_rx_queue *rxq;
1601         int err = -1;
1602         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1603
1604         PMD_INIT_FUNC_TRACE();
1605
1606         if (rx_queue_id < dev->data->nb_rx_queues) {
1607                 rxq = dev->data->rx_queues[rx_queue_id];
1608
1609                 err = i40e_alloc_rx_queue_mbufs(rxq);
1610                 if (err) {
1611                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1612                         return err;
1613                 }
1614
1615                 rte_wmb();
1616
1617                 /* Init the RX tail regieter. */
1618                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1619
1620                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1621
1622                 if (err) {
1623                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1624                                     rx_queue_id);
1625
1626                         i40e_rx_queue_release_mbufs(rxq);
1627                         i40e_reset_rx_queue(rxq);
1628                 }
1629         }
1630
1631         return err;
1632 }
1633
1634 int
1635 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1636 {
1637         struct i40e_rx_queue *rxq;
1638         int err;
1639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640
1641         if (rx_queue_id < dev->data->nb_rx_queues) {
1642                 rxq = dev->data->rx_queues[rx_queue_id];
1643
1644                 /*
1645                 * rx_queue_id is queue id aplication refers to, while
1646                 * rxq->reg_idx is the real queue index.
1647                 */
1648                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1649
1650                 if (err) {
1651                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1652                                     rx_queue_id);
1653                         return err;
1654                 }
1655                 i40e_rx_queue_release_mbufs(rxq);
1656                 i40e_reset_rx_queue(rxq);
1657         }
1658
1659         return 0;
1660 }
1661
1662 int
1663 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1664 {
1665         int err = -1;
1666         struct i40e_tx_queue *txq;
1667         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1668
1669         PMD_INIT_FUNC_TRACE();
1670
1671         if (tx_queue_id < dev->data->nb_tx_queues) {
1672                 txq = dev->data->tx_queues[tx_queue_id];
1673
1674                 /*
1675                 * tx_queue_id is queue id aplication refers to, while
1676                 * rxq->reg_idx is the real queue index.
1677                 */
1678                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1679                 if (err)
1680                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1681                                     tx_queue_id);
1682         }
1683
1684         return err;
1685 }
1686
1687 int
1688 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1689 {
1690         struct i40e_tx_queue *txq;
1691         int err;
1692         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1693
1694         if (tx_queue_id < dev->data->nb_tx_queues) {
1695                 txq = dev->data->tx_queues[tx_queue_id];
1696
1697                 /*
1698                 * tx_queue_id is queue id aplication refers to, while
1699                 * txq->reg_idx is the real queue index.
1700                 */
1701                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1702
1703                 if (err) {
1704                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1705                                     tx_queue_id);
1706                         return err;
1707                 }
1708
1709                 i40e_tx_queue_release_mbufs(txq);
1710                 i40e_reset_tx_queue(txq);
1711         }
1712
1713         return 0;
1714 }
1715
1716 int
1717 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1718                         uint16_t queue_idx,
1719                         uint16_t nb_desc,
1720                         unsigned int socket_id,
1721                         const struct rte_eth_rxconf *rx_conf,
1722                         struct rte_mempool *mp)
1723 {
1724         struct i40e_vsi *vsi;
1725         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1727         struct i40e_rx_queue *rxq;
1728         const struct rte_memzone *rz;
1729         uint32_t ring_size;
1730         uint16_t len;
1731         int use_def_burst_func = 1;
1732
1733         if (hw->mac.type == I40E_MAC_VF) {
1734                 struct i40e_vf *vf =
1735                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1736                 vsi = &vf->vsi;
1737         } else
1738                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1739
1740         if (vsi == NULL) {
1741                 PMD_DRV_LOG(ERR, "VSI not available or queue "
1742                             "index exceeds the maximum");
1743                 return I40E_ERR_PARAM;
1744         }
1745         if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1746                                         (nb_desc > I40E_MAX_RING_DESC) ||
1747                                         (nb_desc < I40E_MIN_RING_DESC)) {
1748                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1749                             "invalid", nb_desc);
1750                 return I40E_ERR_PARAM;
1751         }
1752
1753         /* Free memory if needed */
1754         if (dev->data->rx_queues[queue_idx]) {
1755                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1756                 dev->data->rx_queues[queue_idx] = NULL;
1757         }
1758
1759         /* Allocate the rx queue data structure */
1760         rxq = rte_zmalloc_socket("i40e rx queue",
1761                                  sizeof(struct i40e_rx_queue),
1762                                  RTE_CACHE_LINE_SIZE,
1763                                  socket_id);
1764         if (!rxq) {
1765                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1766                             "rx queue data structure");
1767                 return (-ENOMEM);
1768         }
1769         rxq->mp = mp;
1770         rxq->nb_rx_desc = nb_desc;
1771         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1772         rxq->queue_id = queue_idx;
1773         if (hw->mac.type == I40E_MAC_VF)
1774                 rxq->reg_idx = queue_idx;
1775         else /* PF device */
1776                 rxq->reg_idx = vsi->base_queue +
1777                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
1778
1779         rxq->port_id = dev->data->port_id;
1780         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1781                                                         0 : ETHER_CRC_LEN);
1782         rxq->drop_en = rx_conf->rx_drop_en;
1783         rxq->vsi = vsi;
1784         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1785
1786         /* Allocate the maximun number of RX ring hardware descriptor. */
1787         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1788         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1789         rz = i40e_ring_dma_zone_reserve(dev,
1790                                         "rx_ring",
1791                                         queue_idx,
1792                                         ring_size,
1793                                         socket_id);
1794         if (!rz) {
1795                 i40e_dev_rx_queue_release(rxq);
1796                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1797                 return (-ENOMEM);
1798         }
1799
1800         /* Zero all the descriptors in the ring. */
1801         memset(rz->addr, 0, ring_size);
1802
1803 #ifdef RTE_LIBRTE_XEN_DOM0
1804         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1805 #else
1806         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1807 #endif
1808
1809         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1810
1811 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1812         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1813 #else
1814         len = nb_desc;
1815 #endif
1816
1817         /* Allocate the software ring. */
1818         rxq->sw_ring =
1819                 rte_zmalloc_socket("i40e rx sw ring",
1820                                    sizeof(struct i40e_rx_entry) * len,
1821                                    RTE_CACHE_LINE_SIZE,
1822                                    socket_id);
1823         if (!rxq->sw_ring) {
1824                 i40e_dev_rx_queue_release(rxq);
1825                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1826                 return (-ENOMEM);
1827         }
1828
1829         i40e_reset_rx_queue(rxq);
1830         rxq->q_set = TRUE;
1831         dev->data->rx_queues[queue_idx] = rxq;
1832
1833         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1834
1835         if (!use_def_burst_func && !dev->data->scattered_rx) {
1836 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1837                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1838                              "satisfied. Rx Burst Bulk Alloc function will be "
1839                              "used on port=%d, queue=%d.",
1840                              rxq->port_id, rxq->queue_id);
1841                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1842 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1843         } else {
1844                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1845                              "not satisfied, Scattered Rx is requested, "
1846                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1847                              "not enabled on port=%d, queue=%d.",
1848                              rxq->port_id, rxq->queue_id);
1849         }
1850
1851         return 0;
1852 }
1853
1854 void
1855 i40e_dev_rx_queue_release(void *rxq)
1856 {
1857         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1858
1859         if (!q) {
1860                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1861                 return;
1862         }
1863
1864         i40e_rx_queue_release_mbufs(q);
1865         rte_free(q->sw_ring);
1866         rte_free(q);
1867 }
1868
1869 uint32_t
1870 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1871 {
1872 #define I40E_RXQ_SCAN_INTERVAL 4
1873         volatile union i40e_rx_desc *rxdp;
1874         struct i40e_rx_queue *rxq;
1875         uint16_t desc = 0;
1876
1877         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1878                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1879                 return 0;
1880         }
1881
1882         rxq = dev->data->rx_queues[rx_queue_id];
1883         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1884         while ((desc < rxq->nb_rx_desc) &&
1885                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1886                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1887                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1888                 /**
1889                  * Check the DD bit of a rx descriptor of each 4 in a group,
1890                  * to avoid checking too frequently and downgrading performance
1891                  * too much.
1892                  */
1893                 desc += I40E_RXQ_SCAN_INTERVAL;
1894                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1895                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1896                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1897                                         desc - rxq->nb_rx_desc]);
1898         }
1899
1900         return desc;
1901 }
1902
1903 int
1904 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1905 {
1906         volatile union i40e_rx_desc *rxdp;
1907         struct i40e_rx_queue *rxq = rx_queue;
1908         uint16_t desc;
1909         int ret;
1910
1911         if (unlikely(offset >= rxq->nb_rx_desc)) {
1912                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1913                 return 0;
1914         }
1915
1916         desc = rxq->rx_tail + offset;
1917         if (desc >= rxq->nb_rx_desc)
1918                 desc -= rxq->nb_rx_desc;
1919
1920         rxdp = &(rxq->rx_ring[desc]);
1921
1922         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1923                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1924                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1925
1926         return ret;
1927 }
1928
1929 int
1930 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1931                         uint16_t queue_idx,
1932                         uint16_t nb_desc,
1933                         unsigned int socket_id,
1934                         const struct rte_eth_txconf *tx_conf)
1935 {
1936         struct i40e_vsi *vsi;
1937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1939         struct i40e_tx_queue *txq;
1940         const struct rte_memzone *tz;
1941         uint32_t ring_size;
1942         uint16_t tx_rs_thresh, tx_free_thresh;
1943
1944         if (hw->mac.type == I40E_MAC_VF) {
1945                 struct i40e_vf *vf =
1946                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1947                 vsi = &vf->vsi;
1948         } else
1949                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1950
1951         if (vsi == NULL) {
1952                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1953                             "exceeds the maximum", queue_idx);
1954                 return I40E_ERR_PARAM;
1955         }
1956
1957         if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
1958                                         (nb_desc > I40E_MAX_RING_DESC) ||
1959                                         (nb_desc < I40E_MIN_RING_DESC)) {
1960                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1961                             "invalid", nb_desc);
1962                 return I40E_ERR_PARAM;
1963         }
1964
1965         /**
1966          * The following two parameters control the setting of the RS bit on
1967          * transmit descriptors. TX descriptors will have their RS bit set
1968          * after txq->tx_rs_thresh descriptors have been used. The TX
1969          * descriptor ring will be cleaned after txq->tx_free_thresh
1970          * descriptors are used or if the number of descriptors required to
1971          * transmit a packet is greater than the number of free TX descriptors.
1972          *
1973          * The following constraints must be satisfied:
1974          *  - tx_rs_thresh must be greater than 0.
1975          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1976          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1977          *  - tx_rs_thresh must be a divisor of the ring size.
1978          *  - tx_free_thresh must be greater than 0.
1979          *  - tx_free_thresh must be less than the size of the ring minus 3.
1980          *
1981          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1982          * race condition, hence the maximum threshold constraints. When set
1983          * to zero use default values.
1984          */
1985         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1986                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1987         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1988                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1989         if (tx_rs_thresh >= (nb_desc - 2)) {
1990                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1991                              "number of TX descriptors minus 2. "
1992                              "(tx_rs_thresh=%u port=%d queue=%d)",
1993                              (unsigned int)tx_rs_thresh,
1994                              (int)dev->data->port_id,
1995                              (int)queue_idx);
1996                 return I40E_ERR_PARAM;
1997         }
1998         if (tx_free_thresh >= (nb_desc - 3)) {
1999                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2000                              "tx_free_thresh must be less than the "
2001                              "number of TX descriptors minus 3. "
2002                              "(tx_free_thresh=%u port=%d queue=%d)",
2003                              (unsigned int)tx_free_thresh,
2004                              (int)dev->data->port_id,
2005                              (int)queue_idx);
2006                 return I40E_ERR_PARAM;
2007         }
2008         if (tx_rs_thresh > tx_free_thresh) {
2009                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2010                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2011                              " tx_rs_thresh=%u port=%d queue=%d)",
2012                              (unsigned int)tx_free_thresh,
2013                              (unsigned int)tx_rs_thresh,
2014                              (int)dev->data->port_id,
2015                              (int)queue_idx);
2016                 return I40E_ERR_PARAM;
2017         }
2018         if ((nb_desc % tx_rs_thresh) != 0) {
2019                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2020                              "number of TX descriptors. (tx_rs_thresh=%u"
2021                              " port=%d queue=%d)",
2022                              (unsigned int)tx_rs_thresh,
2023                              (int)dev->data->port_id,
2024                              (int)queue_idx);
2025                 return I40E_ERR_PARAM;
2026         }
2027         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2028                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2029                              "tx_rs_thresh is greater than 1. "
2030                              "(tx_rs_thresh=%u port=%d queue=%d)",
2031                              (unsigned int)tx_rs_thresh,
2032                              (int)dev->data->port_id,
2033                              (int)queue_idx);
2034                 return I40E_ERR_PARAM;
2035         }
2036
2037         /* Free memory if needed. */
2038         if (dev->data->tx_queues[queue_idx]) {
2039                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2040                 dev->data->tx_queues[queue_idx] = NULL;
2041         }
2042
2043         /* Allocate the TX queue data structure. */
2044         txq = rte_zmalloc_socket("i40e tx queue",
2045                                   sizeof(struct i40e_tx_queue),
2046                                   RTE_CACHE_LINE_SIZE,
2047                                   socket_id);
2048         if (!txq) {
2049                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2050                             "tx queue structure");
2051                 return (-ENOMEM);
2052         }
2053
2054         /* Allocate TX hardware ring descriptors. */
2055         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2056         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2057         tz = i40e_ring_dma_zone_reserve(dev,
2058                                         "tx_ring",
2059                                         queue_idx,
2060                                         ring_size,
2061                                         socket_id);
2062         if (!tz) {
2063                 i40e_dev_tx_queue_release(txq);
2064                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2065                 return (-ENOMEM);
2066         }
2067
2068         txq->nb_tx_desc = nb_desc;
2069         txq->tx_rs_thresh = tx_rs_thresh;
2070         txq->tx_free_thresh = tx_free_thresh;
2071         txq->pthresh = tx_conf->tx_thresh.pthresh;
2072         txq->hthresh = tx_conf->tx_thresh.hthresh;
2073         txq->wthresh = tx_conf->tx_thresh.wthresh;
2074         txq->queue_id = queue_idx;
2075         if (hw->mac.type == I40E_MAC_VF)
2076                 txq->reg_idx = queue_idx;
2077         else /* PF device */
2078                 txq->reg_idx = vsi->base_queue +
2079                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2080
2081         txq->port_id = dev->data->port_id;
2082         txq->txq_flags = tx_conf->txq_flags;
2083         txq->vsi = vsi;
2084         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2085
2086 #ifdef RTE_LIBRTE_XEN_DOM0
2087         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2088 #else
2089         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2090 #endif
2091         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2092
2093         /* Allocate software ring */
2094         txq->sw_ring =
2095                 rte_zmalloc_socket("i40e tx sw ring",
2096                                    sizeof(struct i40e_tx_entry) * nb_desc,
2097                                    RTE_CACHE_LINE_SIZE,
2098                                    socket_id);
2099         if (!txq->sw_ring) {
2100                 i40e_dev_tx_queue_release(txq);
2101                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2102                 return (-ENOMEM);
2103         }
2104
2105         i40e_reset_tx_queue(txq);
2106         txq->q_set = TRUE;
2107         dev->data->tx_queues[queue_idx] = txq;
2108
2109         /* Use a simple TX queue without offloads or multi segs if possible */
2110         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2111                                 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2112                 PMD_INIT_LOG(INFO, "Using simple tx path");
2113                 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2114         } else {
2115                 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2116                 dev->tx_pkt_burst = i40e_xmit_pkts;
2117         }
2118
2119         return 0;
2120 }
2121
2122 void
2123 i40e_dev_tx_queue_release(void *txq)
2124 {
2125         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2126
2127         if (!q) {
2128                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2129                 return;
2130         }
2131
2132         i40e_tx_queue_release_mbufs(q);
2133         rte_free(q->sw_ring);
2134         rte_free(q);
2135 }
2136
2137 static const struct rte_memzone *
2138 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2139                            const char *ring_name,
2140                            uint16_t queue_id,
2141                            uint32_t ring_size,
2142                            int socket_id)
2143 {
2144         char z_name[RTE_MEMZONE_NAMESIZE];
2145         const struct rte_memzone *mz;
2146
2147         snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2148                         dev->driver->pci_drv.name, ring_name,
2149                                 dev->data->port_id, queue_id);
2150         mz = rte_memzone_lookup(z_name);
2151         if (mz)
2152                 return mz;
2153
2154 #ifdef RTE_LIBRTE_XEN_DOM0
2155         return rte_memzone_reserve_bounded(z_name, ring_size,
2156                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2157 #else
2158         return rte_memzone_reserve_aligned(z_name, ring_size,
2159                                 socket_id, 0, I40E_ALIGN);
2160 #endif
2161 }
2162
2163 const struct rte_memzone *
2164 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2165 {
2166         const struct rte_memzone *mz = NULL;
2167
2168         mz = rte_memzone_lookup(name);
2169         if (mz)
2170                 return mz;
2171 #ifdef RTE_LIBRTE_XEN_DOM0
2172         mz = rte_memzone_reserve_bounded(name, len,
2173                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2174 #else
2175         mz = rte_memzone_reserve_aligned(name, len,
2176                                 socket_id, 0, I40E_ALIGN);
2177 #endif
2178         return mz;
2179 }
2180
2181 void
2182 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2183 {
2184         uint16_t i;
2185
2186         if (!rxq || !rxq->sw_ring) {
2187                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2188                 return;
2189         }
2190
2191         for (i = 0; i < rxq->nb_rx_desc; i++) {
2192                 if (rxq->sw_ring[i].mbuf) {
2193                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2194                         rxq->sw_ring[i].mbuf = NULL;
2195                 }
2196         }
2197 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2198         if (rxq->rx_nb_avail == 0)
2199                 return;
2200         for (i = 0; i < rxq->rx_nb_avail; i++) {
2201                 struct rte_mbuf *mbuf;
2202
2203                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2204                 rte_pktmbuf_free_seg(mbuf);
2205         }
2206         rxq->rx_nb_avail = 0;
2207 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2208 }
2209
2210 void
2211 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2212 {
2213         unsigned i;
2214         uint16_t len;
2215
2216 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2217         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2218                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2219         else
2220 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2221                 len = rxq->nb_rx_desc;
2222
2223         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2224                 ((volatile char *)rxq->rx_ring)[i] = 0;
2225
2226 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2227         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2228         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2229                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2230
2231         rxq->rx_nb_avail = 0;
2232         rxq->rx_next_avail = 0;
2233         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2234 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2235         rxq->rx_tail = 0;
2236         rxq->nb_rx_hold = 0;
2237         rxq->pkt_first_seg = NULL;
2238         rxq->pkt_last_seg = NULL;
2239 }
2240
2241 void
2242 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2243 {
2244         uint16_t i;
2245
2246         if (!txq || !txq->sw_ring) {
2247                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2248                 return;
2249         }
2250
2251         for (i = 0; i < txq->nb_tx_desc; i++) {
2252                 if (txq->sw_ring[i].mbuf) {
2253                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2254                         txq->sw_ring[i].mbuf = NULL;
2255                 }
2256         }
2257 }
2258
2259 void
2260 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2261 {
2262         struct i40e_tx_entry *txe;
2263         uint16_t i, prev, size;
2264
2265         if (!txq) {
2266                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2267                 return;
2268         }
2269
2270         txe = txq->sw_ring;
2271         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2272         for (i = 0; i < size; i++)
2273                 ((volatile char *)txq->tx_ring)[i] = 0;
2274
2275         prev = (uint16_t)(txq->nb_tx_desc - 1);
2276         for (i = 0; i < txq->nb_tx_desc; i++) {
2277                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2278
2279                 txd->cmd_type_offset_bsz =
2280                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2281                 txe[i].mbuf =  NULL;
2282                 txe[i].last_id = i;
2283                 txe[prev].next_id = i;
2284                 prev = i;
2285         }
2286
2287         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2288         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2289
2290         txq->tx_tail = 0;
2291         txq->nb_tx_used = 0;
2292
2293         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2294         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2295 }
2296
2297 /* Init the TX queue in hardware */
2298 int
2299 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2300 {
2301         enum i40e_status_code err = I40E_SUCCESS;
2302         struct i40e_vsi *vsi = txq->vsi;
2303         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2304         uint16_t pf_q = txq->reg_idx;
2305         struct i40e_hmc_obj_txq tx_ctx;
2306         uint32_t qtx_ctl;
2307
2308         /* clear the context structure first */
2309         memset(&tx_ctx, 0, sizeof(tx_ctx));
2310         tx_ctx.new_context = 1;
2311         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2312         tx_ctx.qlen = txq->nb_tx_desc;
2313         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2314         if (vsi->type == I40E_VSI_FDIR)
2315                 tx_ctx.fd_ena = TRUE;
2316
2317         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2318         if (err != I40E_SUCCESS) {
2319                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2320                 return err;
2321         }
2322
2323         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2324         if (err != I40E_SUCCESS) {
2325                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2326                 return err;
2327         }
2328
2329         /* Now associate this queue with this PCI function */
2330         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2331         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2332                                         I40E_QTX_CTL_PF_INDX_MASK);
2333         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2334         I40E_WRITE_FLUSH(hw);
2335
2336         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2337
2338         return err;
2339 }
2340
2341 int
2342 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2343 {
2344         struct i40e_rx_entry *rxe = rxq->sw_ring;
2345         uint64_t dma_addr;
2346         uint16_t i;
2347
2348         for (i = 0; i < rxq->nb_rx_desc; i++) {
2349                 volatile union i40e_rx_desc *rxd;
2350                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2351
2352                 if (unlikely(!mbuf)) {
2353                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2354                         return -ENOMEM;
2355                 }
2356
2357                 rte_mbuf_refcnt_set(mbuf, 1);
2358                 mbuf->next = NULL;
2359                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2360                 mbuf->nb_segs = 1;
2361                 mbuf->port = rxq->port_id;
2362
2363                 dma_addr =
2364                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2365
2366                 rxd = &rxq->rx_ring[i];
2367                 rxd->read.pkt_addr = dma_addr;
2368                 rxd->read.hdr_addr = dma_addr;
2369 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2370                 rxd->read.rsvd1 = 0;
2371                 rxd->read.rsvd2 = 0;
2372 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2373
2374                 rxe[i].mbuf = mbuf;
2375         }
2376
2377         return 0;
2378 }
2379
2380 /*
2381  * Calculate the buffer length, and check the jumbo frame
2382  * and maximum packet length.
2383  */
2384 static int
2385 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2386 {
2387         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2388         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2389         struct rte_eth_dev_data *data = pf->dev_data;
2390         struct rte_pktmbuf_pool_private *mbp_priv =
2391                         rte_mempool_get_priv(rxq->mp);
2392         uint16_t buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2393                                                 RTE_PKTMBUF_HEADROOM);
2394         uint16_t len;
2395
2396         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2397                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2398         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2399                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2400                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2401                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2402                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2403                 rxq->hs_mode = i40e_header_split_enabled;
2404                 break;
2405         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2406         default:
2407                 rxq->rx_hdr_len = 0;
2408                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2409                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2410                 rxq->hs_mode = i40e_header_split_none;
2411                 break;
2412         }
2413
2414         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2415         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2416         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2417                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2418                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2419                         PMD_DRV_LOG(ERR, "maximum packet length must "
2420                                     "be larger than %u and smaller than %u,"
2421                                     "as jumbo frame is enabled",
2422                                     (uint32_t)ETHER_MAX_LEN,
2423                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2424                         return I40E_ERR_CONFIG;
2425                 }
2426         } else {
2427                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2428                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2429                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2430                                     "larger than %u and smaller than %u, "
2431                                     "as jumbo frame is disabled",
2432                                     (uint32_t)ETHER_MIN_LEN,
2433                                     (uint32_t)ETHER_MAX_LEN);
2434                         return I40E_ERR_CONFIG;
2435                 }
2436         }
2437
2438         return 0;
2439 }
2440
2441 /* Init the RX queue in hardware */
2442 int
2443 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2444 {
2445         int err = I40E_SUCCESS;
2446         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2447         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2448         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2449         uint16_t pf_q = rxq->reg_idx;
2450         uint16_t buf_size;
2451         struct i40e_hmc_obj_rxq rx_ctx;
2452         struct rte_pktmbuf_pool_private *mbp_priv;
2453
2454         err = i40e_rx_queue_config(rxq);
2455         if (err < 0) {
2456                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2457                 return err;
2458         }
2459
2460         /* Clear the context structure first */
2461         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2462         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2463         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2464
2465         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2466         rx_ctx.qlen = rxq->nb_rx_desc;
2467 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2468         rx_ctx.dsize = 1;
2469 #endif
2470         rx_ctx.dtype = rxq->hs_mode;
2471         if (rxq->hs_mode)
2472                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2473         else
2474                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2475         rx_ctx.rxmax = rxq->max_pkt_len;
2476         rx_ctx.tphrdesc_ena = 1;
2477         rx_ctx.tphwdesc_ena = 1;
2478         rx_ctx.tphdata_ena = 1;
2479         rx_ctx.tphhead_ena = 1;
2480         rx_ctx.lrxqthresh = 2;
2481         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2482         rx_ctx.l2tsel = 1;
2483         rx_ctx.showiv = 1;
2484         rx_ctx.prefena = 1;
2485
2486         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2487         if (err != I40E_SUCCESS) {
2488                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2489                 return err;
2490         }
2491         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2492         if (err != I40E_SUCCESS) {
2493                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2494                 return err;
2495         }
2496
2497         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2498
2499         mbp_priv = rte_mempool_get_priv(rxq->mp);
2500         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2501                                         RTE_PKTMBUF_HEADROOM);
2502
2503         /* Check if scattered RX needs to be used. */
2504         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2505                 dev_data->scattered_rx = 1;
2506                 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2507         }
2508
2509         /* Init the RX tail regieter. */
2510         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2511
2512         return 0;
2513 }
2514
2515 void
2516 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2517 {
2518         uint16_t i;
2519
2520         PMD_INIT_FUNC_TRACE();
2521
2522         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2523                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2524                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2525         }
2526
2527         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2528                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2529                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2530         }
2531 }
2532
2533 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2534 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2535
2536 enum i40e_status_code
2537 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2538 {
2539         struct i40e_tx_queue *txq;
2540         const struct rte_memzone *tz = NULL;
2541         uint32_t ring_size;
2542         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2543
2544         if (!pf) {
2545                 PMD_DRV_LOG(ERR, "PF is not available");
2546                 return I40E_ERR_BAD_PTR;
2547         }
2548
2549         /* Allocate the TX queue data structure. */
2550         txq = rte_zmalloc_socket("i40e fdir tx queue",
2551                                   sizeof(struct i40e_tx_queue),
2552                                   RTE_CACHE_LINE_SIZE,
2553                                   SOCKET_ID_ANY);
2554         if (!txq) {
2555                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2556                                         "tx queue structure.");
2557                 return I40E_ERR_NO_MEMORY;
2558         }
2559
2560         /* Allocate TX hardware ring descriptors. */
2561         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2562         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2563
2564         tz = i40e_ring_dma_zone_reserve(dev,
2565                                         "fdir_tx_ring",
2566                                         I40E_FDIR_QUEUE_ID,
2567                                         ring_size,
2568                                         SOCKET_ID_ANY);
2569         if (!tz) {
2570                 i40e_dev_tx_queue_release(txq);
2571                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2572                 return I40E_ERR_NO_MEMORY;
2573         }
2574
2575         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2576         txq->queue_id = I40E_FDIR_QUEUE_ID;
2577         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2578         txq->vsi = pf->fdir.fdir_vsi;
2579
2580 #ifdef RTE_LIBRTE_XEN_DOM0
2581         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2582 #else
2583         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2584 #endif
2585         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2586         /*
2587          * don't need to allocate software ring and reset for the fdir
2588          * program queue just set the queue has been configured.
2589          */
2590         txq->q_set = TRUE;
2591         pf->fdir.txq = txq;
2592
2593         return I40E_SUCCESS;
2594 }
2595
2596 enum i40e_status_code
2597 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2598 {
2599         struct i40e_rx_queue *rxq;
2600         const struct rte_memzone *rz = NULL;
2601         uint32_t ring_size;
2602         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2603
2604         if (!pf) {
2605                 PMD_DRV_LOG(ERR, "PF is not available");
2606                 return I40E_ERR_BAD_PTR;
2607         }
2608
2609         /* Allocate the RX queue data structure. */
2610         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2611                                   sizeof(struct i40e_rx_queue),
2612                                   RTE_CACHE_LINE_SIZE,
2613                                   SOCKET_ID_ANY);
2614         if (!rxq) {
2615                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2616                                         "rx queue structure.");
2617                 return I40E_ERR_NO_MEMORY;
2618         }
2619
2620         /* Allocate RX hardware ring descriptors. */
2621         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2622         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2623
2624         rz = i40e_ring_dma_zone_reserve(dev,
2625                                         "fdir_rx_ring",
2626                                         I40E_FDIR_QUEUE_ID,
2627                                         ring_size,
2628                                         SOCKET_ID_ANY);
2629         if (!rz) {
2630                 i40e_dev_rx_queue_release(rxq);
2631                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2632                 return I40E_ERR_NO_MEMORY;
2633         }
2634
2635         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2636         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2637         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2638         rxq->vsi = pf->fdir.fdir_vsi;
2639
2640 #ifdef RTE_LIBRTE_XEN_DOM0
2641         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2642 #else
2643         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2644 #endif
2645         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2646
2647         /*
2648          * Don't need to allocate software ring and reset for the fdir
2649          * rx queue, just set the queue has been configured.
2650          */
2651         rxq->q_set = TRUE;
2652         pf->fdir.rxq = rxq;
2653
2654         return I40E_SUCCESS;
2655 }