lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37
  38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  50                                           u8 *sff8472_data);
  51
  52 /**
  53  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  54  * @hw: pointer to the hardware structure
  55  * @byte: byte to send
  56  *
  57  * Returns an error code on error.
  58  */
  59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  60 {
  61         s32 status;
  62
  63         status = ixgbe_clock_out_i2c_byte(hw, byte);
  64         if (status)
  65                 return status;
  66         return ixgbe_get_i2c_ack(hw);
  67 }
  68
  69 /**
  70  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  71  * @hw: pointer to the hardware structure
  72  * @byte: pointer to a u8 to receive the byte
  73  *
  74  * Returns an error code on error.
  75  */
  76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  77 {
  78         s32 status;
  79
  80         status = ixgbe_clock_in_i2c_byte(hw, byte);
  81         if (status)
  82                 return status;
  83         /* ACK */
  84         return ixgbe_clock_out_i2c_bit(hw, false);
  85 }
  86
  87 /**
  88  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  89  * @add1 - addend 1
  90  * @add2 - addend 2
  91  *
  92  * Returns one's complement 8-bit sum.
  93  */
  94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  95 {
  96         u16 sum = add1 + add2;
  97
  98         sum = (sum & 0xFF) + (sum >> 8);
  99         return sum & 0xFF;
 100 }
 101
 102 /**
 103  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 104  * @hw: pointer to the hardware structure
 105  * @addr: I2C bus address to read from
 106  * @reg: I2C device register to read from
 107  * @val: pointer to location to receive read value
 108  *
 109  * Returns an error code on error.
 110  */
 111 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 112                                            u16 reg, u16 *val)
 113 {
 114         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 115         int max_retry = 10;
 116         int retry = 0;
 117         u8 csum_byte;
 118         u8 high_bits;
 119         u8 low_bits;
 120         u8 reg_high;
 121         u8 csum;
 122
 123         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 124         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 125         csum = ~csum;
 126         do {
 127                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 128                         return IXGBE_ERR_SWFW_SYNC;
 129                 ixgbe_i2c_start(hw);
 130                 /* Device Address and write indication */
 131                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 132                         goto fail;
 133                 /* Write bits 14:8 */
 134                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 135                         goto fail;
 136                 /* Write bits 7:0 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 138                         goto fail;
 139                 /* Write csum */
 140                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 141                         goto fail;
 142                 /* Re-start condition */
 143                 ixgbe_i2c_start(hw);
 144                 /* Device Address and read indication */
 145                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 146                         goto fail;
 147                 /* Get upper bits */
 148                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 149                         goto fail;
 150                 /* Get low bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 152                         goto fail;
 153                 /* Get csum */
 154                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 155                         goto fail;
 156                 /* NACK */
 157                 if (ixgbe_clock_out_i2c_bit(hw, false))
 158                         goto fail;
 159                 ixgbe_i2c_stop(hw);
 160                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 161                 *val = (high_bits << 8) | low_bits;
 162                 return 0;
 163
 164 fail:
 165                 ixgbe_i2c_bus_clear(hw);
 166                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 167                 retry++;
 168                 if (retry < max_retry)
 169                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 170                 else
 171                         DEBUGOUT("I2C byte read combined error.\n");
 172         } while (retry < max_retry);
 173
 174         return IXGBE_ERR_I2C;
 175 }
 176
 177 /**
 178  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 179  * @hw: pointer to the hardware structure
 180  * @addr: I2C bus address to write to
 181  * @reg: I2C device register to write to
 182  * @val: value to write
 183  *
 184  * Returns an error code on error.
 185  */
 186 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 187                                             u8 addr, u16 reg, u16 val)
 188 {
 189         int max_retry = 1;
 190         int retry = 0;
 191         u8 reg_high;
 192         u8 csum;
 193
 194         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 195         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 196         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 197         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 198         csum = ~csum;
 199         do {
 200                 ixgbe_i2c_start(hw);
 201                 /* Device Address and write indication */
 202                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 203                         goto fail;
 204                 /* Write bits 14:8 */
 205                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 206                         goto fail;
 207                 /* Write bits 7:0 */
 208                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 209                         goto fail;
 210                 /* Write data 15:8 */
 211                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 212                         goto fail;
 213                 /* Write data 7:0 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 215                         goto fail;
 216                 /* Write csum */
 217                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 218                         goto fail;
 219                 ixgbe_i2c_stop(hw);
 220                 return 0;
 221
 222 fail:
 223                 ixgbe_i2c_bus_clear(hw);
 224                 retry++;
 225                 if (retry < max_retry)
 226                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 227                 else
 228                         DEBUGOUT("I2C byte write combined error.\n");
 229         } while (retry < max_retry);
 230
 231         return IXGBE_ERR_I2C;
 232 }
 233
 234 /**
 235  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 236  *  @hw: pointer to the hardware structure
 237  *
 238  *  Initialize the function pointers.
 239  **/
 240 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 241 {
 242         struct ixgbe_phy_info *phy = &hw->phy;
 243
 244         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 245
 246         /* PHY */
 247         phy->ops.identify = ixgbe_identify_phy_generic;
 248         phy->ops.reset = ixgbe_reset_phy_generic;
 249         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 250         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 251         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 252         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 253         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 254         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 255         phy->ops.check_link = NULL;
 256         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 257         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 258         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 259         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 260         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 261         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 262         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 263         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 264         phy->sfp_type = ixgbe_sfp_type_unknown;
 265         phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
 266         phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
 267         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 268         return IXGBE_SUCCESS;
 269 }
 270
 271 /**
 272  *  ixgbe_identify_phy_generic - Get physical layer module
 273  *  @hw: pointer to hardware structure
 274  *
 275  *  Determines the physical layer module found on the current adapter.
 276  **/
 277 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 278 {
 279         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 280         u32 phy_addr;
 281         u16 ext_ability = 0;
 282
 283         DEBUGFUNC("ixgbe_identify_phy_generic");
 284
 285         if (!hw->phy.phy_semaphore_mask) {
 286                 if (hw->bus.lan_id)
 287                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 288                 else
 289                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 290         }
 291
 292         if (hw->phy.type == ixgbe_phy_unknown) {
 293                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 294                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 295                                 hw->phy.addr = phy_addr;
 296                                 ixgbe_get_phy_id(hw);
 297                                 hw->phy.type =
 298                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 299
 300                                 if (hw->phy.type == ixgbe_phy_unknown) {
 301                                         hw->phy.ops.read_reg(hw,
 302                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 303                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 304                                                   &ext_ability);
 305                                         if (ext_ability &
 306                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 307                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 308                                                 hw->phy.type =
 309                                                          ixgbe_phy_cu_unknown;
 310                                         else
 311                                                 hw->phy.type =
 312                                                          ixgbe_phy_generic;
 313                                 }
 314
 315                                 status = IXGBE_SUCCESS;
 316                                 break;
 317                         }
 318                 }
 319
 320                 /* Certain media types do not have a phy so an address will not
 321                  * be found and the code will take this path.  Caller has to
 322                  * decide if it is an error or not.
 323                  */
 324                 if (status != IXGBE_SUCCESS) {
 325                         hw->phy.addr = 0;
 326                 }
 327         } else {
 328                 status = IXGBE_SUCCESS;
 329         }
 330
 331         return status;
 332 }
 333
 334 /**
 335  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 336  * @hw: pointer to the hardware structure
 337  *
 338  * This function checks the MMNGC.MNG_VETO bit to see if there are
 339  * any constraints on link from manageability.  For MAC's that don't
 340  * have this bit just return faluse since the link can not be blocked
 341  * via this method.
 342  **/
 343 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 344 {
 345         u32 mmngc;
 346
 347         DEBUGFUNC("ixgbe_check_reset_blocked");
 348
 349         /* If we don't have this bit, it can't be blocking */
 350         if (hw->mac.type == ixgbe_mac_82598EB)
 351                 return false;
 352
 353         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 354         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 355                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 356                               "MNG_VETO bit detected.\n");
 357                 return true;
 358         }
 359
 360         return false;
 361 }
 362
 363 /**
 364  *  ixgbe_validate_phy_addr - Determines phy address is valid
 365  *  @hw: pointer to hardware structure
 366  *
 367  **/
 368 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 369 {
 370         u16 phy_id = 0;
 371         bool valid = false;
 372
 373         DEBUGFUNC("ixgbe_validate_phy_addr");
 374
 375         hw->phy.addr = phy_addr;
 376         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 377                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 378
 379         if (phy_id != 0xFFFF && phy_id != 0x0)
 380                 valid = true;
 381
 382         return valid;
 383 }
 384
 385 /**
 386  *  ixgbe_get_phy_id - Get the phy type
 387  *  @hw: pointer to hardware structure
 388  *
 389  **/
 390 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 391 {
 392         u32 status;
 393         u16 phy_id_high = 0;
 394         u16 phy_id_low = 0;
 395
 396         DEBUGFUNC("ixgbe_get_phy_id");
 397
 398         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 399                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 400                                       &phy_id_high);
 401
 402         if (status == IXGBE_SUCCESS) {
 403                 hw->phy.id = (u32)(phy_id_high << 16);
 404                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 405                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 406                                               &phy_id_low);
 407                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 408                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 409         }
 410         return status;
 411 }
 412
 413 /**
 414  *  ixgbe_get_phy_type_from_id - Get the phy type
 415  *  @hw: pointer to hardware structure
 416  *
 417  **/
 418 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 419 {
 420         enum ixgbe_phy_type phy_type;
 421
 422         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 423
 424         switch (phy_id) {
 425         case TN1010_PHY_ID:
 426                 phy_type = ixgbe_phy_tn;
 427                 break;
 428         case X550_PHY_ID:
 429         case X540_PHY_ID:
 430                 phy_type = ixgbe_phy_aq;
 431                 break;
 432         case QT2022_PHY_ID:
 433                 phy_type = ixgbe_phy_qt;
 434                 break;
 435         case ATH_PHY_ID:
 436                 phy_type = ixgbe_phy_nl;
 437                 break;
 438         case X557_PHY_ID:
 439                 phy_type = ixgbe_phy_x550em_ext_t;
 440                 break;
 441         default:
 442                 phy_type = ixgbe_phy_unknown;
 443                 break;
 444         }
 445
 446         DEBUGOUT1("phy type found is %d\n", phy_type);
 447         return phy_type;
 448 }
 449
 450 /**
 451  *  ixgbe_reset_phy_generic - Performs a PHY reset
 452  *  @hw: pointer to hardware structure
 453  **/
 454 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 455 {
 456         u32 i;
 457         u16 ctrl = 0;
 458         s32 status = IXGBE_SUCCESS;
 459
 460         DEBUGFUNC("ixgbe_reset_phy_generic");
 461
 462         if (hw->phy.type == ixgbe_phy_unknown)
 463                 status = ixgbe_identify_phy_generic(hw);
 464
 465         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 466                 goto out;
 467
 468         /* Don't reset PHY if it's shut down due to overtemp. */
 469         if (!hw->phy.reset_if_overtemp &&
 470             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 471                 goto out;
 472
 473         /* Blocked by MNG FW so bail */
 474         if (ixgbe_check_reset_blocked(hw))
 475                 goto out;
 476
 477         /*
 478          * Perform soft PHY reset to the PHY_XS.
 479          * This will cause a soft reset to the PHY
 480          */
 481         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 482                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 483                               IXGBE_MDIO_PHY_XS_RESET);
 484
 485         /*
 486          * Poll for reset bit to self-clear indicating reset is complete.
 487          * Some PHYs could take up to 3 seconds to complete and need about
 488          * 1.7 usec delay after the reset is complete.
 489          */
 490         for (i = 0; i < 30; i++) {
 491                 msec_delay(100);
 492                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 493                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 494                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 495                         usec_delay(2);
 496                         break;
 497                 }
 498         }
 499
 500         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 501                 status = IXGBE_ERR_RESET_FAILED;
 502                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 503                              "PHY reset polling failed to complete.\n");
 504         }
 505
 506 out:
 507         return status;
 508 }
 509
 510 /**
 511  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 512  *  the SWFW lock
 513  *  @hw: pointer to hardware structure
 514  *  @reg_addr: 32 bit address of PHY register to read
 515  *  @phy_data: Pointer to read data from PHY register
 516  **/
 517 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 518                        u16 *phy_data)
 519 {
 520         u32 i, data, command;
 521
 522         /* Setup and write the address cycle command */
 523         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 524                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 525                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 526                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 527
 528         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 529
 530         /*
 531          * Check every 10 usec to see if the address cycle completed.
 532          * The MDI Command bit will clear when the operation is
 533          * complete
 534          */
 535         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 536                 usec_delay(10);
 537
 538                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 539                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 540                                 break;
 541         }
 542
 543
 544         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 545                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 546                 return IXGBE_ERR_PHY;
 547         }
 548
 549         /*
 550          * Address cycle complete, setup and write the read
 551          * command
 552          */
 553         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 554                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 555                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 556                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 557
 558         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 559
 560         /*
 561          * Check every 10 usec to see if the address cycle
 562          * completed. The MDI Command bit will clear when the
 563          * operation is complete
 564          */
 565         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 566                 usec_delay(10);
 567
 568                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 569                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 570                         break;
 571         }
 572
 573         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 574                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 575                 return IXGBE_ERR_PHY;
 576         }
 577
 578         /*
 579          * Read operation is complete.  Get the data
 580          * from MSRWD
 581          */
 582         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 583         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 584         *phy_data = (u16)(data);
 585
 586         return IXGBE_SUCCESS;
 587 }
 588
 589 /**
 590  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 591  *  using the SWFW lock - this function is needed in most cases
 592  *  @hw: pointer to hardware structure
 593  *  @reg_addr: 32 bit address of PHY register to read
 594  *  @phy_data: Pointer to read data from PHY register
 595  **/
 596 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 597                                u32 device_type, u16 *phy_data)
 598 {
 599         s32 status;
 600         u32 gssr = hw->phy.phy_semaphore_mask;
 601
 602         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 603
 604         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 605                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 606                                                 phy_data);
 607                 hw->mac.ops.release_swfw_sync(hw, gssr);
 608         } else {
 609                 status = IXGBE_ERR_SWFW_SYNC;
 610         }
 611
 612         return status;
 613 }
 614
 615 /**
 616  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 617  *  without SWFW lock
 618  *  @hw: pointer to hardware structure
 619  *  @reg_addr: 32 bit PHY register to write
 620  *  @device_type: 5 bit device type
 621  *  @phy_data: Data to write to the PHY register
 622  **/
 623 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 624                                 u32 device_type, u16 phy_data)
 625 {
 626         u32 i, command;
 627
 628         /* Put the data in the MDI single read and write data register*/
 629         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 630
 631         /* Setup and write the address cycle command */
 632         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 633                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 634                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 635                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 636
 637         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 638
 639         /*
 640          * Check every 10 usec to see if the address cycle completed.
 641          * The MDI Command bit will clear when the operation is
 642          * complete
 643          */
 644         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 645                 usec_delay(10);
 646
 647                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 648                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 649                         break;
 650         }
 651
 652         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 653                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 654                 return IXGBE_ERR_PHY;
 655         }
 656
 657         /*
 658          * Address cycle complete, setup and write the write
 659          * command
 660          */
 661         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 662                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 663                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 664                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 665
 666         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 667
 668         /*
 669          * Check every 10 usec to see if the address cycle
 670          * completed. The MDI Command bit will clear when the
 671          * operation is complete
 672          */
 673         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 674                 usec_delay(10);
 675
 676                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 677                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 678                         break;
 679         }
 680
 681         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 682                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 683                 return IXGBE_ERR_PHY;
 684         }
 685
 686         return IXGBE_SUCCESS;
 687 }
 688
 689 /**
 690  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 691  *  using SWFW lock- this function is needed in most cases
 692  *  @hw: pointer to hardware structure
 693  *  @reg_addr: 32 bit PHY register to write
 694  *  @device_type: 5 bit device type
 695  *  @phy_data: Data to write to the PHY register
 696  **/
 697 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 698                                 u32 device_type, u16 phy_data)
 699 {
 700         s32 status;
 701         u32 gssr = hw->phy.phy_semaphore_mask;
 702
 703         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 704
 705         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 706                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 707                                                  phy_data);
 708                 hw->mac.ops.release_swfw_sync(hw, gssr);
 709         } else {
 710                 status = IXGBE_ERR_SWFW_SYNC;
 711         }
 712
 713         return status;
 714 }
 715
 716 /**
 717  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 718  *  @hw: pointer to hardware structure
 719  *
 720  *  Restart auto-negotiation and PHY and waits for completion.
 721  **/
 722 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 723 {
 724         s32 status = IXGBE_SUCCESS;
 725         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 726         bool autoneg = false;
 727         ixgbe_link_speed speed;
 728
 729         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 730
 731         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 732
 733         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 734                 /* Set or unset auto-negotiation 10G advertisement */
 735                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 736                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 737                                      &autoneg_reg);
 738
 739                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 740                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 741                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 742
 743                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 744                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 745                                       autoneg_reg);
 746         }
 747
 748         if (hw->mac.type == ixgbe_mac_X550) {
 749                 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
 750                         /* Set or unset auto-negotiation 1G advertisement */
 751                         hw->phy.ops.read_reg(hw,
 752                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 753                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 754                                 &autoneg_reg);
 755
 756                         autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 757                         if (hw->phy.autoneg_advertised &
 758                              IXGBE_LINK_SPEED_5GB_FULL)
 759                                 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 760
 761                         hw->phy.ops.write_reg(hw,
 762                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 763                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 764                                 autoneg_reg);
 765                 }
 766
 767                 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
 768                         /* Set or unset auto-negotiation 1G advertisement */
 769                         hw->phy.ops.read_reg(hw,
 770                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 771                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 772                                 &autoneg_reg);
 773
 774                         autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 775                         if (hw->phy.autoneg_advertised &
 776                             IXGBE_LINK_SPEED_2_5GB_FULL)
 777                                 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 778
 779                         hw->phy.ops.write_reg(hw,
 780                                 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 781                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 782                                 autoneg_reg);
 783                 }
 784         }
 785
 786         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 787                 /* Set or unset auto-negotiation 1G advertisement */
 788                 hw->phy.ops.read_reg(hw,
 789                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 790                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 791                                      &autoneg_reg);
 792
 793                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 794                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 795                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 796
 797                 hw->phy.ops.write_reg(hw,
 798                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 799                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 800                                       autoneg_reg);
 801         }
 802
 803         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 804                 /* Set or unset auto-negotiation 100M advertisement */
 805                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 806                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 807                                      &autoneg_reg);
 808
 809                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 810                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 811                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 812                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 813
 814                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 815                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 816                                       autoneg_reg);
 817         }
 818
 819         /* Blocked by MNG FW so don't reset PHY */
 820         if (ixgbe_check_reset_blocked(hw))
 821                 return status;
 822
 823         /* Restart PHY auto-negotiation. */
 824         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 825                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 826
 827         autoneg_reg |= IXGBE_MII_RESTART;
 828
 829         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 830                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 831
 832         return status;
 833 }
 834
 835 /**
 836  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 837  *  @hw: pointer to hardware structure
 838  *  @speed: new link speed
 839  **/
 840 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 841                                        ixgbe_link_speed speed,
 842                                        bool autoneg_wait_to_complete)
 843 {
 844         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 845
 846         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 847
 848         /*
 849          * Clear autoneg_advertised and set new values based on input link
 850          * speed.
 851          */
 852         hw->phy.autoneg_advertised = 0;
 853
 854         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 855                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 856
 857         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 858                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 859
 860         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 861                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 862
 863         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 864                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 865
 866         if (speed & IXGBE_LINK_SPEED_100_FULL)
 867                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 868
 869         /* Setup link based on the new speed settings */
 870         hw->phy.ops.setup_link(hw);
 871
 872         return IXGBE_SUCCESS;
 873 }
 874
 875 /**
 876  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 877  *  @hw: pointer to hardware structure
 878  *  @speed: pointer to link speed
 879  *  @autoneg: boolean auto-negotiation value
 880  *
 881  *  Determines the supported link capabilities by reading the PHY auto
 882  *  negotiation register.
 883  **/
 884 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 885                                                ixgbe_link_speed *speed,
 886                                                bool *autoneg)
 887 {
 888         s32 status;
 889         u16 speed_ability;
 890
 891         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 892
 893         *speed = 0;
 894         *autoneg = true;
 895
 896         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 897                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 898                                       &speed_ability);
 899
 900         if (status == IXGBE_SUCCESS) {
 901                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 902                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 903                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 904                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 905                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 906                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 907         }
 908
 909         /* Internal PHY does not support 100 Mbps */
 910         if (hw->mac.type == ixgbe_mac_X550EM_x)
 911                 *speed &= ~IXGBE_LINK_SPEED_100_FULL;
 912
 913         if (hw->mac.type == ixgbe_mac_X550) {
 914                 *speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
 915                 *speed |= IXGBE_LINK_SPEED_5GB_FULL;
 916         }
 917
 918         return status;
 919 }
 920
 921 /**
 922  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 923  *  @hw: pointer to hardware structure
 924  *
 925  *  Reads the VS1 register to determine if link is up and the current speed for
 926  *  the PHY.
 927  **/
 928 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 929                              bool *link_up)
 930 {
 931         s32 status = IXGBE_SUCCESS;
 932         u32 time_out;
 933         u32 max_time_out = 10;
 934         u16 phy_link = 0;
 935         u16 phy_speed = 0;
 936         u16 phy_data = 0;
 937
 938         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 939
 940         /* Initialize speed and link to default case */
 941         *link_up = false;
 942         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 943
 944         /*
 945          * Check current speed and link status of the PHY register.
 946          * This is a vendor specific register and may have to
 947          * be changed for other copper PHYs.
 948          */
 949         for (time_out = 0; time_out < max_time_out; time_out++) {
 950                 usec_delay(10);
 951                 status = hw->phy.ops.read_reg(hw,
 952                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 953                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 954                                         &phy_data);
 955                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 956                 phy_speed = phy_data &
 957                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 958                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 959                         *link_up = true;
 960                         if (phy_speed ==
 961                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 962                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 963                         break;
 964                 }
 965         }
 966
 967         return status;
 968 }
 969
 970 /**
 971  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
 972  *      @hw: pointer to hardware structure
 973  *
 974  *      Restart auto-negotiation and PHY and waits for completion.
 975  **/
 976 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 977 {
 978         s32 status = IXGBE_SUCCESS;
 979         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 980         bool autoneg = false;
 981         ixgbe_link_speed speed;
 982
 983         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 984
 985         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 986
 987         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 988                 /* Set or unset auto-negotiation 10G advertisement */
 989                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 990                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 991                                      &autoneg_reg);
 992
 993                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 994                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 995                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 996
 997                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 998                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 999                                       autoneg_reg);
1000         }
1001
1002         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1003                 /* Set or unset auto-negotiation 1G advertisement */
1004                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1005                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1006                                      &autoneg_reg);
1007
1008                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1009                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1010                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1011
1012                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1013                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1014                                       autoneg_reg);
1015         }
1016
1017         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1018                 /* Set or unset auto-negotiation 100M advertisement */
1019                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1020                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1021                                      &autoneg_reg);
1022
1023                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1024                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1025                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1026
1027                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1028                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1029                                       autoneg_reg);
1030         }
1031
1032         /* Blocked by MNG FW so don't reset PHY */
1033         if (ixgbe_check_reset_blocked(hw))
1034                 return status;
1035
1036         /* Restart PHY auto-negotiation. */
1037         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1038                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1039
1040         autoneg_reg |= IXGBE_MII_RESTART;
1041
1042         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1043                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1044
1045         return status;
1046 }
1047
1048 /**
1049  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1050  *  @hw: pointer to hardware structure
1051  *  @firmware_version: pointer to the PHY Firmware Version
1052  **/
1053 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1054                                        u16 *firmware_version)
1055 {
1056         s32 status;
1057
1058         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1059
1060         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1061                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1062                                       firmware_version);
1063
1064         return status;
1065 }
1066
1067 /**
1068  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1069  *  @hw: pointer to hardware structure
1070  *  @firmware_version: pointer to the PHY Firmware Version
1071  **/
1072 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1073                                            u16 *firmware_version)
1074 {
1075         s32 status;
1076
1077         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1078
1079         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1080                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1081                                       firmware_version);
1082
1083         return status;
1084 }
1085
1086 /**
1087  *  ixgbe_reset_phy_nl - Performs a PHY reset
1088  *  @hw: pointer to hardware structure
1089  **/
1090 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1091 {
1092         u16 phy_offset, control, eword, edata, block_crc;
1093         bool end_data = false;
1094         u16 list_offset, data_offset;
1095         u16 phy_data = 0;
1096         s32 ret_val = IXGBE_SUCCESS;
1097         u32 i;
1098
1099         DEBUGFUNC("ixgbe_reset_phy_nl");
1100
1101         /* Blocked by MNG FW so bail */
1102         if (ixgbe_check_reset_blocked(hw))
1103                 goto out;
1104
1105         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1106                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1107
1108         /* reset the PHY and poll for completion */
1109         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1110                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1111                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1112
1113         for (i = 0; i < 100; i++) {
1114                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1115                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1116                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1117                         break;
1118                 msec_delay(10);
1119         }
1120
1121         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1122                 DEBUGOUT("PHY reset did not complete.\n");
1123                 ret_val = IXGBE_ERR_PHY;
1124                 goto out;
1125         }
1126
1127         /* Get init offsets */
1128         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1129                                                       &data_offset);
1130         if (ret_val != IXGBE_SUCCESS)
1131                 goto out;
1132
1133         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1134         data_offset++;
1135         while (!end_data) {
1136                 /*
1137                  * Read control word from PHY init contents offset
1138                  */
1139                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1140                 if (ret_val)
1141                         goto err_eeprom;
1142                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1143                            IXGBE_CONTROL_SHIFT_NL;
1144                 edata = eword & IXGBE_DATA_MASK_NL;
1145                 switch (control) {
1146                 case IXGBE_DELAY_NL:
1147                         data_offset++;
1148                         DEBUGOUT1("DELAY: %d MS\n", edata);
1149                         msec_delay(edata);
1150                         break;
1151                 case IXGBE_DATA_NL:
1152                         DEBUGOUT("DATA:\n");
1153                         data_offset++;
1154                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1155                                                       &phy_offset);
1156                         if (ret_val)
1157                                 goto err_eeprom;
1158                         data_offset++;
1159                         for (i = 0; i < edata; i++) {
1160                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1161                                                               &eword);
1162                                 if (ret_val)
1163                                         goto err_eeprom;
1164                                 hw->phy.ops.write_reg(hw, phy_offset,
1165                                                       IXGBE_TWINAX_DEV, eword);
1166                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1167                                           phy_offset);
1168                                 data_offset++;
1169                                 phy_offset++;
1170                         }
1171                         break;
1172                 case IXGBE_CONTROL_NL:
1173                         data_offset++;
1174                         DEBUGOUT("CONTROL:\n");
1175                         if (edata == IXGBE_CONTROL_EOL_NL) {
1176                                 DEBUGOUT("EOL\n");
1177                                 end_data = true;
1178                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1179                                 DEBUGOUT("SOL\n");
1180                         } else {
1181                                 DEBUGOUT("Bad control value\n");
1182                                 ret_val = IXGBE_ERR_PHY;
1183                                 goto out;
1184                         }
1185                         break;
1186                 default:
1187                         DEBUGOUT("Bad control type\n");
1188                         ret_val = IXGBE_ERR_PHY;
1189                         goto out;
1190                 }
1191         }
1192
1193 out:
1194         return ret_val;
1195
1196 err_eeprom:
1197         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1198                       "eeprom read at offset %d failed", data_offset);
1199         return IXGBE_ERR_PHY;
1200 }
1201
1202 /**
1203  *  ixgbe_identify_module_generic - Identifies module type
1204  *  @hw: pointer to hardware structure
1205  *
1206  *  Determines HW type and calls appropriate function.
1207  **/
1208 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1209 {
1210         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1211
1212         DEBUGFUNC("ixgbe_identify_module_generic");
1213
1214         switch (hw->mac.ops.get_media_type(hw)) {
1215         case ixgbe_media_type_fiber:
1216                 status = ixgbe_identify_sfp_module_generic(hw);
1217                 break;
1218
1219         case ixgbe_media_type_fiber_qsfp:
1220                 status = ixgbe_identify_qsfp_module_generic(hw);
1221                 break;
1222
1223         default:
1224                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1225                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1226                 break;
1227         }
1228
1229         return status;
1230 }
1231
1232 /**
1233  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1234  *  @hw: pointer to hardware structure
1235  *
1236  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1237  **/
1238 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1239 {
1240         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1241         u32 vendor_oui = 0;
1242         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1243         u8 identifier = 0;
1244         u8 comp_codes_1g = 0;
1245         u8 comp_codes_10g = 0;
1246         u8 oui_bytes[3] = {0, 0, 0};
1247         u8 cable_tech = 0;
1248         u8 cable_spec = 0;
1249         u16 enforce_sfp = 0;
1250
1251         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1252
1253         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1254                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1255                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1256                 goto out;
1257         }
1258
1259         /* LAN ID is needed for I2C access */
1260         hw->mac.ops.set_lan_id(hw);
1261
1262         status = hw->phy.ops.read_i2c_eeprom(hw,
1263                                              IXGBE_SFF_IDENTIFIER,
1264                                              &identifier);
1265
1266         if (status != IXGBE_SUCCESS)
1267                 goto err_read_i2c_eeprom;
1268
1269         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1270                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1271                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1272         } else {
1273                 status = hw->phy.ops.read_i2c_eeprom(hw,
1274                                                      IXGBE_SFF_1GBE_COMP_CODES,
1275                                                      &comp_codes_1g);
1276
1277                 if (status != IXGBE_SUCCESS)
1278                         goto err_read_i2c_eeprom;
1279
1280                 status = hw->phy.ops.read_i2c_eeprom(hw,
1281                                                      IXGBE_SFF_10GBE_COMP_CODES,
1282                                                      &comp_codes_10g);
1283
1284                 if (status != IXGBE_SUCCESS)
1285                         goto err_read_i2c_eeprom;
1286                 status = hw->phy.ops.read_i2c_eeprom(hw,
1287                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1288                                                      &cable_tech);
1289
1290                 if (status != IXGBE_SUCCESS)
1291                         goto err_read_i2c_eeprom;
1292
1293                  /* ID Module
1294                   * =========
1295                   * 0   SFP_DA_CU
1296                   * 1   SFP_SR
1297                   * 2   SFP_LR
1298                   * 3   SFP_DA_CORE0 - 82599-specific
1299                   * 4   SFP_DA_CORE1 - 82599-specific
1300                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1301                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1302                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1303                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1304                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1305                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1306                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1307                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1308                   */
1309                 if (hw->mac.type == ixgbe_mac_82598EB) {
1310                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1311                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1312                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1313                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1314                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1315                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1316                         else
1317                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1318                 } else {
1319                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1320                                 if (hw->bus.lan_id == 0)
1321                                         hw->phy.sfp_type =
1322                                                      ixgbe_sfp_type_da_cu_core0;
1323                                 else
1324                                         hw->phy.sfp_type =
1325                                                      ixgbe_sfp_type_da_cu_core1;
1326                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1327                                 hw->phy.ops.read_i2c_eeprom(
1328                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1329                                                 &cable_spec);
1330                                 if (cable_spec &
1331                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1332                                         if (hw->bus.lan_id == 0)
1333                                                 hw->phy.sfp_type =
1334                                                 ixgbe_sfp_type_da_act_lmt_core0;
1335                                         else
1336                                                 hw->phy.sfp_type =
1337                                                 ixgbe_sfp_type_da_act_lmt_core1;
1338                                 } else {
1339                                         hw->phy.sfp_type =
1340                                                         ixgbe_sfp_type_unknown;
1341                                 }
1342                         } else if (comp_codes_10g &
1343                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1344                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1345                                 if (hw->bus.lan_id == 0)
1346                                         hw->phy.sfp_type =
1347                                                       ixgbe_sfp_type_srlr_core0;
1348                                 else
1349                                         hw->phy.sfp_type =
1350                                                       ixgbe_sfp_type_srlr_core1;
1351                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1352                                 if (hw->bus.lan_id == 0)
1353                                         hw->phy.sfp_type =
1354                                                 ixgbe_sfp_type_1g_cu_core0;
1355                                 else
1356                                         hw->phy.sfp_type =
1357                                                 ixgbe_sfp_type_1g_cu_core1;
1358                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1359                                 if (hw->bus.lan_id == 0)
1360                                         hw->phy.sfp_type =
1361                                                 ixgbe_sfp_type_1g_sx_core0;
1362                                 else
1363                                         hw->phy.sfp_type =
1364                                                 ixgbe_sfp_type_1g_sx_core1;
1365                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1366                                 if (hw->bus.lan_id == 0)
1367                                         hw->phy.sfp_type =
1368                                                 ixgbe_sfp_type_1g_lx_core0;
1369                                 else
1370                                         hw->phy.sfp_type =
1371                                                 ixgbe_sfp_type_1g_lx_core1;
1372                         } else {
1373                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1374                         }
1375                 }
1376
1377                 if (hw->phy.sfp_type != stored_sfp_type)
1378                         hw->phy.sfp_setup_needed = true;
1379
1380                 /* Determine if the SFP+ PHY is dual speed or not. */
1381                 hw->phy.multispeed_fiber = false;
1382                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1383                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1384                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1385                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1386                         hw->phy.multispeed_fiber = true;
1387
1388                 /* Determine PHY vendor */
1389                 if (hw->phy.type != ixgbe_phy_nl) {
1390                         hw->phy.id = identifier;
1391                         status = hw->phy.ops.read_i2c_eeprom(hw,
1392                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1393                                                     &oui_bytes[0]);
1394
1395                         if (status != IXGBE_SUCCESS)
1396                                 goto err_read_i2c_eeprom;
1397
1398                         status = hw->phy.ops.read_i2c_eeprom(hw,
1399                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1400                                                     &oui_bytes[1]);
1401
1402                         if (status != IXGBE_SUCCESS)
1403                                 goto err_read_i2c_eeprom;
1404
1405                         status = hw->phy.ops.read_i2c_eeprom(hw,
1406                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1407                                                     &oui_bytes[2]);
1408
1409                         if (status != IXGBE_SUCCESS)
1410                                 goto err_read_i2c_eeprom;
1411
1412                         vendor_oui =
1413                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1414                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1415                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1416
1417                         switch (vendor_oui) {
1418                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1419                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1420                                         hw->phy.type =
1421                                                     ixgbe_phy_sfp_passive_tyco;
1422                                 break;
1423                         case IXGBE_SFF_VENDOR_OUI_FTL:
1424                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1425                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1426                                 else
1427                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1428                                 break;
1429                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1430                                 hw->phy.type = ixgbe_phy_sfp_avago;
1431                                 break;
1432                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1433                                 hw->phy.type = ixgbe_phy_sfp_intel;
1434                                 break;
1435                         default:
1436                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1437                                         hw->phy.type =
1438                                                  ixgbe_phy_sfp_passive_unknown;
1439                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1440                                         hw->phy.type =
1441                                                 ixgbe_phy_sfp_active_unknown;
1442                                 else
1443                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1444                                 break;
1445                         }
1446                 }
1447
1448                 /* Allow any DA cable vendor */
1449                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1450                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1451                         status = IXGBE_SUCCESS;
1452                         goto out;
1453                 }
1454
1455                 /* Verify supported 1G SFP modules */
1456                 if (comp_codes_10g == 0 &&
1457                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1458                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1459                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1460                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1461                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1462                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1463                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1464                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1465                         goto out;
1466                 }
1467
1468                 /* Anything else 82598-based is supported */
1469                 if (hw->mac.type == ixgbe_mac_82598EB) {
1470                         status = IXGBE_SUCCESS;
1471                         goto out;
1472                 }
1473
1474                 ixgbe_get_device_caps(hw, &enforce_sfp);
1475                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1476                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1477                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1478                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1479                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1480                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1481                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1482                         /* Make sure we're a supported PHY type */
1483                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1484                                 status = IXGBE_SUCCESS;
1485                         } else {
1486                                 if (hw->allow_unsupported_sfp == true) {
1487                                         EWARN(hw, "WARNING: Intel (R) Network "
1488                                               "Connections are quality tested "
1489                                               "using Intel (R) Ethernet Optics."
1490                                               " Using untested modules is not "
1491                                               "supported and may cause unstable"
1492                                               " operation or damage to the "
1493                                               "module or the adapter. Intel "
1494                                               "Corporation is not responsible "
1495                                               "for any harm caused by using "
1496                                               "untested modules.\n", status);
1497                                         status = IXGBE_SUCCESS;
1498                                 } else {
1499                                         DEBUGOUT("SFP+ module not supported\n");
1500                                         hw->phy.type =
1501                                                 ixgbe_phy_sfp_unsupported;
1502                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1503                                 }
1504                         }
1505                 } else {
1506                         status = IXGBE_SUCCESS;
1507                 }
1508         }
1509
1510 out:
1511         return status;
1512
1513 err_read_i2c_eeprom:
1514         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1515         if (hw->phy.type != ixgbe_phy_nl) {
1516                 hw->phy.id = 0;
1517                 hw->phy.type = ixgbe_phy_unknown;
1518         }
1519         return IXGBE_ERR_SFP_NOT_PRESENT;
1520 }
1521
1522 /**
1523  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1524  *  @hw: pointer to hardware structure
1525  *
1526  *  Determines physical layer capabilities of the current SFP.
1527  */
1528 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1529 {
1530         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1531         u8 comp_codes_10g = 0;
1532         u8 comp_codes_1g = 0;
1533
1534         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1535
1536         hw->phy.ops.identify_sfp(hw);
1537         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1538                 return physical_layer;
1539
1540         switch (hw->phy.type) {
1541         case ixgbe_phy_sfp_passive_tyco:
1542         case ixgbe_phy_sfp_passive_unknown:
1543         case ixgbe_phy_qsfp_passive_unknown:
1544                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1545                 break;
1546         case ixgbe_phy_sfp_ftl_active:
1547         case ixgbe_phy_sfp_active_unknown:
1548         case ixgbe_phy_qsfp_active_unknown:
1549                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1550                 break;
1551         case ixgbe_phy_sfp_avago:
1552         case ixgbe_phy_sfp_ftl:
1553         case ixgbe_phy_sfp_intel:
1554         case ixgbe_phy_sfp_unknown:
1555                 hw->phy.ops.read_i2c_eeprom(hw,
1556                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1557                 hw->phy.ops.read_i2c_eeprom(hw,
1558                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1559                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1560                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1561                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1562                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1563                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1564                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1565                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1566                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1567                 break;
1568         case ixgbe_phy_qsfp_intel:
1569         case ixgbe_phy_qsfp_unknown:
1570                 hw->phy.ops.read_i2c_eeprom(hw,
1571                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1572                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1573                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1574                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1575                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1576                 break;
1577         default:
1578                 break;
1579         }
1580
1581         return physical_layer;
1582 }
1583
1584 /**
1585  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1586  *  @hw: pointer to hardware structure
1587  *
1588  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1589  **/
1590 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1591 {
1592         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1593         u32 vendor_oui = 0;
1594         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1595         u8 identifier = 0;
1596         u8 comp_codes_1g = 0;
1597         u8 comp_codes_10g = 0;
1598         u8 oui_bytes[3] = {0, 0, 0};
1599         u16 enforce_sfp = 0;
1600         u8 connector = 0;
1601         u8 cable_length = 0;
1602         u8 device_tech = 0;
1603         bool active_cable = false;
1604
1605         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1606
1607         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1608                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1609                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1610                 goto out;
1611         }
1612
1613         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1614                                              &identifier);
1615
1616         if (status != IXGBE_SUCCESS)
1617                 goto err_read_i2c_eeprom;
1618
1619         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1620                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1621                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1622                 goto out;
1623         }
1624
1625         hw->phy.id = identifier;
1626
1627         /* LAN ID is needed for sfp_type determination */
1628         hw->mac.ops.set_lan_id(hw);
1629
1630         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1631                                              &comp_codes_10g);
1632
1633         if (status != IXGBE_SUCCESS)
1634                 goto err_read_i2c_eeprom;
1635
1636         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1637                                              &comp_codes_1g);
1638
1639         if (status != IXGBE_SUCCESS)
1640                 goto err_read_i2c_eeprom;
1641
1642         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1643                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1644                 if (hw->bus.lan_id == 0)
1645                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1646                 else
1647                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1648         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1649                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1650                 if (hw->bus.lan_id == 0)
1651                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1652                 else
1653                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1654         } else {
1655                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1656                         active_cable = true;
1657
1658                 if (!active_cable) {
1659                         /* check for active DA cables that pre-date
1660                          * SFF-8436 v3.6 */
1661                         hw->phy.ops.read_i2c_eeprom(hw,
1662                                         IXGBE_SFF_QSFP_CONNECTOR,
1663                                         &connector);
1664
1665                         hw->phy.ops.read_i2c_eeprom(hw,
1666                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1667                                         &cable_length);
1668
1669                         hw->phy.ops.read_i2c_eeprom(hw,
1670                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1671                                         &device_tech);
1672
1673                         if ((connector ==
1674                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1675                             (cable_length > 0) &&
1676                             ((device_tech >> 4) ==
1677                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1678                                 active_cable = true;
1679                 }
1680
1681                 if (active_cable) {
1682                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1683                         if (hw->bus.lan_id == 0)
1684                                 hw->phy.sfp_type =
1685                                                 ixgbe_sfp_type_da_act_lmt_core0;
1686                         else
1687                                 hw->phy.sfp_type =
1688                                                 ixgbe_sfp_type_da_act_lmt_core1;
1689                 } else {
1690                         /* unsupported module type */
1691                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1692                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1693                         goto out;
1694                 }
1695         }
1696
1697         if (hw->phy.sfp_type != stored_sfp_type)
1698                 hw->phy.sfp_setup_needed = true;
1699
1700         /* Determine if the QSFP+ PHY is dual speed or not. */
1701         hw->phy.multispeed_fiber = false;
1702         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1703            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1704            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1705            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1706                 hw->phy.multispeed_fiber = true;
1707
1708         /* Determine PHY vendor for optical modules */
1709         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1710                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1711                 status = hw->phy.ops.read_i2c_eeprom(hw,
1712                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1713                                             &oui_bytes[0]);
1714
1715                 if (status != IXGBE_SUCCESS)
1716                         goto err_read_i2c_eeprom;
1717
1718                 status = hw->phy.ops.read_i2c_eeprom(hw,
1719                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1720                                             &oui_bytes[1]);
1721
1722                 if (status != IXGBE_SUCCESS)
1723                         goto err_read_i2c_eeprom;
1724
1725                 status = hw->phy.ops.read_i2c_eeprom(hw,
1726                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1727                                             &oui_bytes[2]);
1728
1729                 if (status != IXGBE_SUCCESS)
1730                         goto err_read_i2c_eeprom;
1731
1732                 vendor_oui =
1733                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1734                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1735                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1736
1737                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1738                         hw->phy.type = ixgbe_phy_qsfp_intel;
1739                 else
1740                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1741
1742                 ixgbe_get_device_caps(hw, &enforce_sfp);
1743                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1744                         /* Make sure we're a supported PHY type */
1745                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1746                                 status = IXGBE_SUCCESS;
1747                         } else {
1748                                 if (hw->allow_unsupported_sfp == true) {
1749                                         EWARN(hw, "WARNING: Intel (R) Network "
1750                                               "Connections are quality tested "
1751                                               "using Intel (R) Ethernet Optics."
1752                                               " Using untested modules is not "
1753                                               "supported and may cause unstable"
1754                                               " operation or damage to the "
1755                                               "module or the adapter. Intel "
1756                                               "Corporation is not responsible "
1757                                               "for any harm caused by using "
1758                                               "untested modules.\n", status);
1759                                         status = IXGBE_SUCCESS;
1760                                 } else {
1761                                         DEBUGOUT("QSFP module not supported\n");
1762                                         hw->phy.type =
1763                                                 ixgbe_phy_sfp_unsupported;
1764                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1765                                 }
1766                         }
1767                 } else {
1768                         status = IXGBE_SUCCESS;
1769                 }
1770         }
1771
1772 out:
1773         return status;
1774
1775 err_read_i2c_eeprom:
1776         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1777         hw->phy.id = 0;
1778         hw->phy.type = ixgbe_phy_unknown;
1779
1780         return IXGBE_ERR_SFP_NOT_PRESENT;
1781 }
1782
1783
1784 /**
1785  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1786  *  @hw: pointer to hardware structure
1787  *  @list_offset: offset to the SFP ID list
1788  *  @data_offset: offset to the SFP data block
1789  *
1790  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1791  *  so it returns the offsets to the phy init sequence block.
1792  **/
1793 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1794                                         u16 *list_offset,
1795                                         u16 *data_offset)
1796 {
1797         u16 sfp_id;
1798         u16 sfp_type = hw->phy.sfp_type;
1799
1800         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1801
1802         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1803                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1804
1805         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1806                 return IXGBE_ERR_SFP_NOT_PRESENT;
1807
1808         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1809             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1810                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1811
1812         /*
1813          * Limiting active cables and 1G Phys must be initialized as
1814          * SR modules
1815          */
1816         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1817             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1818             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1819             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1820                 sfp_type = ixgbe_sfp_type_srlr_core0;
1821         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1822                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1823                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1824                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1825                 sfp_type = ixgbe_sfp_type_srlr_core1;
1826
1827         /* Read offset to PHY init contents */
1828         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1829                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1830                               "eeprom read at offset %d failed",
1831                               IXGBE_PHY_INIT_OFFSET_NL);
1832                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1833         }
1834
1835         if ((!*list_offset) || (*list_offset == 0xFFFF))
1836                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1837
1838         /* Shift offset to first ID word */
1839         (*list_offset)++;
1840
1841         /*
1842          * Find the matching SFP ID in the EEPROM
1843          * and program the init sequence
1844          */
1845         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1846                 goto err_phy;
1847
1848         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1849                 if (sfp_id == sfp_type) {
1850                         (*list_offset)++;
1851                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1852                                 goto err_phy;
1853                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1854                                 DEBUGOUT("SFP+ module not supported\n");
1855                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1856                         } else {
1857                                 break;
1858                         }
1859                 } else {
1860                         (*list_offset) += 2;
1861                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1862                                 goto err_phy;
1863                 }
1864         }
1865
1866         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1867                 DEBUGOUT("No matching SFP+ module found\n");
1868                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1869         }
1870
1871         return IXGBE_SUCCESS;
1872
1873 err_phy:
1874         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1875                       "eeprom read at offset %d failed", *list_offset);
1876         return IXGBE_ERR_PHY;
1877 }
1878
1879 /**
1880  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1881  *  @hw: pointer to hardware structure
1882  *  @byte_offset: EEPROM byte offset to read
1883  *  @eeprom_data: value read
1884  *
1885  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1886  **/
1887 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1888                                   u8 *eeprom_data)
1889 {
1890         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1891
1892         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1893                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1894                                          eeprom_data);
1895 }
1896
1897 /**
1898  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1899  *  @hw: pointer to hardware structure
1900  *  @byte_offset: byte offset at address 0xA2
1901  *  @eeprom_data: value read
1902  *
1903  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1904  **/
1905 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1906                                           u8 *sff8472_data)
1907 {
1908         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1909                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1910                                          sff8472_data);
1911 }
1912
1913 /**
1914  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1915  *  @hw: pointer to hardware structure
1916  *  @byte_offset: EEPROM byte offset to write
1917  *  @eeprom_data: value to write
1918  *
1919  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1920  **/
1921 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1922                                    u8 eeprom_data)
1923 {
1924         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1925
1926         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1927                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1928                                           eeprom_data);
1929 }
1930
1931 /**
1932  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1933  * @hw: pointer to hardware structure
1934  * @offset: eeprom offset to be read
1935  * @addr: I2C address to be read
1936  */
1937 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1938 {
1939         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1940             offset == IXGBE_SFF_IDENTIFIER &&
1941             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1942                 return true;
1943         return false;
1944 }
1945
1946 /**
1947  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1948  *  @hw: pointer to hardware structure
1949  *  @byte_offset: byte offset to read
1950  *  @data: value read
1951  *
1952  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1953  *  a specified device address.
1954  **/
1955 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1956                                 u8 dev_addr, u8 *data)
1957 {
1958         s32 status;
1959         u32 max_retry = 10;
1960         u32 retry = 0;
1961         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1962         bool nack = 1;
1963         *data = 0;
1964
1965         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1966
1967         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
1968                 max_retry = IXGBE_SFP_DETECT_RETRIES;
1969
1970         do {
1971                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1972                         return IXGBE_ERR_SWFW_SYNC;
1973
1974                 ixgbe_i2c_start(hw);
1975
1976                 /* Device Address and write indication */
1977                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1978                 if (status != IXGBE_SUCCESS)
1979                         goto fail;
1980
1981                 status = ixgbe_get_i2c_ack(hw);
1982                 if (status != IXGBE_SUCCESS)
1983                         goto fail;
1984
1985                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1986                 if (status != IXGBE_SUCCESS)
1987                         goto fail;
1988
1989                 status = ixgbe_get_i2c_ack(hw);
1990                 if (status != IXGBE_SUCCESS)
1991                         goto fail;
1992
1993                 ixgbe_i2c_start(hw);
1994
1995                 /* Device Address and read indication */
1996                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1997                 if (status != IXGBE_SUCCESS)
1998                         goto fail;
1999
2000                 status = ixgbe_get_i2c_ack(hw);
2001                 if (status != IXGBE_SUCCESS)
2002                         goto fail;
2003
2004                 status = ixgbe_clock_in_i2c_byte(hw, data);
2005                 if (status != IXGBE_SUCCESS)
2006                         goto fail;
2007
2008                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2009                 if (status != IXGBE_SUCCESS)
2010                         goto fail;
2011
2012                 ixgbe_i2c_stop(hw);
2013                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2014                 return IXGBE_SUCCESS;
2015
2016 fail:
2017                 ixgbe_i2c_bus_clear(hw);
2018                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2019                 msec_delay(100);
2020                 retry++;
2021                 if (retry < max_retry)
2022                         DEBUGOUT("I2C byte read error - Retrying.\n");
2023                 else
2024                         DEBUGOUT("I2C byte read error.\n");
2025
2026         } while (retry < max_retry);
2027
2028         return status;
2029 }
2030
2031 /**
2032  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2033  *  @hw: pointer to hardware structure
2034  *  @byte_offset: byte offset to write
2035  *  @data: value to write
2036  *
2037  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2038  *  a specified device address.
2039  **/
2040 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2041                                  u8 dev_addr, u8 data)
2042 {
2043         s32 status = IXGBE_SUCCESS;
2044         u32 max_retry = 1;
2045         u32 retry = 0;
2046         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2047
2048         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2049
2050         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
2051                 status = IXGBE_ERR_SWFW_SYNC;
2052                 goto write_byte_out;
2053         }
2054
2055         do {
2056                 ixgbe_i2c_start(hw);
2057
2058                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2059                 if (status != IXGBE_SUCCESS)
2060                         goto fail;
2061
2062                 status = ixgbe_get_i2c_ack(hw);
2063                 if (status != IXGBE_SUCCESS)
2064                         goto fail;
2065
2066                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2067                 if (status != IXGBE_SUCCESS)
2068                         goto fail;
2069
2070                 status = ixgbe_get_i2c_ack(hw);
2071                 if (status != IXGBE_SUCCESS)
2072                         goto fail;
2073
2074                 status = ixgbe_clock_out_i2c_byte(hw, data);
2075                 if (status != IXGBE_SUCCESS)
2076                         goto fail;
2077
2078                 status = ixgbe_get_i2c_ack(hw);
2079                 if (status != IXGBE_SUCCESS)
2080                         goto fail;
2081
2082                 ixgbe_i2c_stop(hw);
2083                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2084                 return IXGBE_SUCCESS;
2085
2086 fail:
2087                 ixgbe_i2c_bus_clear(hw);
2088                 retry++;
2089                 if (retry < max_retry)
2090                         DEBUGOUT("I2C byte write error - Retrying.\n");
2091                 else
2092                         DEBUGOUT("I2C byte write error.\n");
2093         } while (retry < max_retry);
2094
2095         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2096
2097 write_byte_out:
2098         return status;
2099 }
2100
2101 /**
2102  *  ixgbe_i2c_start - Sets I2C start condition
2103  *  @hw: pointer to hardware structure
2104  *
2105  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2106  *  Set bit-bang mode on X550 hardware.
2107  **/
2108 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2109 {
2110         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2111
2112         DEBUGFUNC("ixgbe_i2c_start");
2113
2114         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2115
2116         /* Start condition must begin with data and clock high */
2117         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2118         ixgbe_raise_i2c_clk(hw, &i2cctl);
2119
2120         /* Setup time for start condition (4.7us) */
2121         usec_delay(IXGBE_I2C_T_SU_STA);
2122
2123         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2124
2125         /* Hold time for start condition (4us) */
2126         usec_delay(IXGBE_I2C_T_HD_STA);
2127
2128         ixgbe_lower_i2c_clk(hw, &i2cctl);
2129
2130         /* Minimum low period of clock is 4.7 us */
2131         usec_delay(IXGBE_I2C_T_LOW);
2132
2133 }
2134
2135 /**
2136  *  ixgbe_i2c_stop - Sets I2C stop condition
2137  *  @hw: pointer to hardware structure
2138  *
2139  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2140  *  Disables bit-bang mode and negates data output enable on X550
2141  *  hardware.
2142  **/
2143 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2144 {
2145         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2146         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2147         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2148         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2149
2150         DEBUGFUNC("ixgbe_i2c_stop");
2151
2152         /* Stop condition must begin with data low and clock high */
2153         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2154         ixgbe_raise_i2c_clk(hw, &i2cctl);
2155
2156         /* Setup time for stop condition (4us) */
2157         usec_delay(IXGBE_I2C_T_SU_STO);
2158
2159         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2160
2161         /* bus free time between stop and start (4.7us)*/
2162         usec_delay(IXGBE_I2C_T_BUF);
2163
2164         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2165                 i2cctl &= ~bb_en_bit;
2166                 i2cctl |= data_oe_bit | clk_oe_bit;
2167                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2168                 IXGBE_WRITE_FLUSH(hw);
2169         }
2170 }
2171
2172 /**
2173  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2174  *  @hw: pointer to hardware structure
2175  *  @data: data byte to clock in
2176  *
2177  *  Clocks in one byte data via I2C data/clock
2178  **/
2179 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2180 {
2181         s32 i;
2182         bool bit = 0;
2183
2184         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2185
2186         *data = 0;
2187         for (i = 7; i >= 0; i--) {
2188                 ixgbe_clock_in_i2c_bit(hw, &bit);
2189                 *data |= bit << i;
2190         }
2191
2192         return IXGBE_SUCCESS;
2193 }
2194
2195 /**
2196  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2197  *  @hw: pointer to hardware structure
2198  *  @data: data byte clocked out
2199  *
2200  *  Clocks out one byte data via I2C data/clock
2201  **/
2202 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2203 {
2204         s32 status = IXGBE_SUCCESS;
2205         s32 i;
2206         u32 i2cctl;
2207         bool bit;
2208
2209         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2210
2211         for (i = 7; i >= 0; i--) {
2212                 bit = (data >> i) & 0x1;
2213                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2214
2215                 if (status != IXGBE_SUCCESS)
2216                         break;
2217         }
2218
2219         /* Release SDA line (set high) */
2220         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2221         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2222         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2223         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2224         IXGBE_WRITE_FLUSH(hw);
2225
2226         return status;
2227 }
2228
2229 /**
2230  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2231  *  @hw: pointer to hardware structure
2232  *
2233  *  Clocks in/out one bit via I2C data/clock
2234  **/
2235 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2236 {
2237         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2238         s32 status = IXGBE_SUCCESS;
2239         u32 i = 0;
2240         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2241         u32 timeout = 10;
2242         bool ack = 1;
2243
2244         DEBUGFUNC("ixgbe_get_i2c_ack");
2245
2246         if (data_oe_bit) {
2247                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2248                 i2cctl |= data_oe_bit;
2249                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2250                 IXGBE_WRITE_FLUSH(hw);
2251         }
2252         ixgbe_raise_i2c_clk(hw, &i2cctl);
2253
2254         /* Minimum high period of clock is 4us */
2255         usec_delay(IXGBE_I2C_T_HIGH);
2256
2257         /* Poll for ACK.  Note that ACK in I2C spec is
2258          * transition from 1 to 0 */
2259         for (i = 0; i < timeout; i++) {
2260                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2261                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2262
2263                 usec_delay(1);
2264                 if (!ack)
2265                         break;
2266         }
2267
2268         if (ack) {
2269                 DEBUGOUT("I2C ack was not received.\n");
2270                 status = IXGBE_ERR_I2C;
2271         }
2272
2273         ixgbe_lower_i2c_clk(hw, &i2cctl);
2274
2275         /* Minimum low period of clock is 4.7 us */
2276         usec_delay(IXGBE_I2C_T_LOW);
2277
2278         return status;
2279 }
2280
2281 /**
2282  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2283  *  @hw: pointer to hardware structure
2284  *  @data: read data value
2285  *
2286  *  Clocks in one bit via I2C data/clock
2287  **/
2288 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2289 {
2290         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2291         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2292
2293         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2294
2295         if (data_oe_bit) {
2296                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2297                 i2cctl |= data_oe_bit;
2298                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2299                 IXGBE_WRITE_FLUSH(hw);
2300         }
2301         ixgbe_raise_i2c_clk(hw, &i2cctl);
2302
2303         /* Minimum high period of clock is 4us */
2304         usec_delay(IXGBE_I2C_T_HIGH);
2305
2306         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2307         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2308
2309         ixgbe_lower_i2c_clk(hw, &i2cctl);
2310
2311         /* Minimum low period of clock is 4.7 us */
2312         usec_delay(IXGBE_I2C_T_LOW);
2313
2314         return IXGBE_SUCCESS;
2315 }
2316
2317 /**
2318  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2319  *  @hw: pointer to hardware structure
2320  *  @data: data value to write
2321  *
2322  *  Clocks out one bit via I2C data/clock
2323  **/
2324 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2325 {
2326         s32 status;
2327         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2328
2329         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2330
2331         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2332         if (status == IXGBE_SUCCESS) {
2333                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2334
2335                 /* Minimum high period of clock is 4us */
2336                 usec_delay(IXGBE_I2C_T_HIGH);
2337
2338                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2339
2340                 /* Minimum low period of clock is 4.7 us.
2341                  * This also takes care of the data hold time.
2342                  */
2343                 usec_delay(IXGBE_I2C_T_LOW);
2344         } else {
2345                 status = IXGBE_ERR_I2C;
2346                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2347                              "I2C data was not set to %X\n", data);
2348         }
2349
2350         return status;
2351 }
2352
2353 /**
2354  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2355  *  @hw: pointer to hardware structure
2356  *  @i2cctl: Current value of I2CCTL register
2357  *
2358  *  Raises the I2C clock line '0'->'1'
2359  *  Negates the I2C clock output enable on X550 hardware.
2360  **/
2361 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2362 {
2363         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2364         u32 i = 0;
2365         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2366         u32 i2cctl_r = 0;
2367
2368         DEBUGFUNC("ixgbe_raise_i2c_clk");
2369
2370         if (clk_oe_bit) {
2371                 *i2cctl |= clk_oe_bit;
2372                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2373         }
2374
2375         for (i = 0; i < timeout; i++) {
2376                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2377
2378                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2379                 IXGBE_WRITE_FLUSH(hw);
2380                 /* SCL rise time (1000ns) */
2381                 usec_delay(IXGBE_I2C_T_RISE);
2382
2383                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2384                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2385                         break;
2386         }
2387 }
2388
2389 /**
2390  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2391  *  @hw: pointer to hardware structure
2392  *  @i2cctl: Current value of I2CCTL register
2393  *
2394  *  Lowers the I2C clock line '1'->'0'
2395  *  Asserts the I2C clock output enable on X550 hardware.
2396  **/
2397 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2398 {
2399         DEBUGFUNC("ixgbe_lower_i2c_clk");
2400
2401         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2402         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2403
2404         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2405         IXGBE_WRITE_FLUSH(hw);
2406
2407         /* SCL fall time (300ns) */
2408         usec_delay(IXGBE_I2C_T_FALL);
2409 }
2410
2411 /**
2412  *  ixgbe_set_i2c_data - Sets the I2C data bit
2413  *  @hw: pointer to hardware structure
2414  *  @i2cctl: Current value of I2CCTL register
2415  *  @data: I2C data value (0 or 1) to set
2416  *
2417  *  Sets the I2C data bit
2418  *  Asserts the I2C data output enable on X550 hardware.
2419  **/
2420 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2421 {
2422         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2423         s32 status = IXGBE_SUCCESS;
2424
2425         DEBUGFUNC("ixgbe_set_i2c_data");
2426
2427         if (data)
2428                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2429         else
2430                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2431         *i2cctl &= ~data_oe_bit;
2432
2433         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2434         IXGBE_WRITE_FLUSH(hw);
2435
2436         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2437         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2438
2439         if (!data)      /* Can't verify data in this case */
2440                 return IXGBE_SUCCESS;
2441         if (data_oe_bit) {
2442                 *i2cctl |= data_oe_bit;
2443                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2444                 IXGBE_WRITE_FLUSH(hw);
2445         }
2446
2447         /* Verify data was set correctly */
2448         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2449         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2450                 status = IXGBE_ERR_I2C;
2451                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2452                              "Error - I2C data was not set to %X.\n",
2453                              data);
2454         }
2455
2456         return status;
2457 }
2458
2459 /**
2460  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2461  *  @hw: pointer to hardware structure
2462  *  @i2cctl: Current value of I2CCTL register
2463  *
2464  *  Returns the I2C data bit value
2465  *  Negates the I2C data output enable on X550 hardware.
2466  **/
2467 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2468 {
2469         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2470         bool data;
2471
2472         DEBUGFUNC("ixgbe_get_i2c_data");
2473
2474         if (data_oe_bit) {
2475                 *i2cctl |= data_oe_bit;
2476                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2477                 IXGBE_WRITE_FLUSH(hw);
2478                 usec_delay(IXGBE_I2C_T_FALL);
2479         }
2480
2481         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2482                 data = 1;
2483         else
2484                 data = 0;
2485
2486         return data;
2487 }
2488
2489 /**
2490  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2491  *  @hw: pointer to hardware structure
2492  *
2493  *  Clears the I2C bus by sending nine clock pulses.
2494  *  Used when data line is stuck low.
2495  **/
2496 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2497 {
2498         u32 i2cctl;
2499         u32 i;
2500
2501         DEBUGFUNC("ixgbe_i2c_bus_clear");
2502
2503         ixgbe_i2c_start(hw);
2504         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2505
2506         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2507
2508         for (i = 0; i < 9; i++) {
2509                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2510
2511                 /* Min high period of clock is 4us */
2512                 usec_delay(IXGBE_I2C_T_HIGH);
2513
2514                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2515
2516                 /* Min low period of clock is 4.7us*/
2517                 usec_delay(IXGBE_I2C_T_LOW);
2518         }
2519
2520         ixgbe_i2c_start(hw);
2521
2522         /* Put the i2c bus back to default state */
2523         ixgbe_i2c_stop(hw);
2524 }
2525
2526 /**
2527  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2528  *  @hw: pointer to hardware structure
2529  *
2530  *  Checks if the LASI temp alarm status was triggered due to overtemp
2531  **/
2532 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2533 {
2534         s32 status = IXGBE_SUCCESS;
2535         u16 phy_data = 0;
2536
2537         DEBUGFUNC("ixgbe_tn_check_overtemp");
2538
2539         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2540                 goto out;
2541
2542         /* Check that the LASI temp alarm status was triggered */
2543         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2544                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2545
2546         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2547                 goto out;
2548
2549         status = IXGBE_ERR_OVERTEMP;
2550         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2551 out:
2552         return status;
2553 }
2554
2555 /**
2556  * ixgbe_set_copper_phy_power - Control power for copper phy
2557  * @hw: pointer to hardware structure
2558  * @on: true for on, false for off
2559  */
2560 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2561 {
2562         u32 status;
2563         u16 reg;
2564
2565         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2566                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2567                                       &reg);
2568         if (status)
2569                 return status;
2570
2571         if (on) {
2572                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2573         } else {
2574                 if (ixgbe_check_reset_blocked(hw))
2575                         return 0;
2576                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2577         }
2578
2579         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2580                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2581                                        reg);
2582         return status;
2583 }