4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
65 #include "ixgbe_logs.h"
66 #include "ixgbe/ixgbe_api.h"
67 #include "ixgbe/ixgbe_vf.h"
68 #include "ixgbe/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
73 * High threshold controlling when to start sending XOFF frames. Must be at
74 * least 8 bytes less than receive packet buffer size. This value is in units
77 #define IXGBE_FC_HI 0x80
80 * Low threshold controlling when to start sending XON frames. This value is
81 * in units of 1024 bytes.
83 #define IXGBE_FC_LO 0x40
85 /* Timer value included in XOFF frames. */
86 #define IXGBE_FC_PAUSE 0x680
88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
89 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
90 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
92 #define IXGBE_MMW_SIZE_DEFAULT 0x4
93 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
96 * Default values for RX/TX configuration
98 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
99 #define IXGBE_DEFAULT_RX_PTHRESH 8
100 #define IXGBE_DEFAULT_RX_HTHRESH 8
101 #define IXGBE_DEFAULT_RX_WTHRESH 0
103 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
104 #define IXGBE_DEFAULT_TX_PTHRESH 32
105 #define IXGBE_DEFAULT_TX_HTHRESH 0
106 #define IXGBE_DEFAULT_TX_WTHRESH 0
107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
109 /* Bit shift and mask */
110 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
111 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
112 #define IXGBE_8_BIT_WIDTH CHAR_BIT
113 #define IXGBE_8_BIT_MASK UINT8_MAX
115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
119 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
120 struct rte_eth_dev *eth_dev);
121 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
122 static int ixgbe_dev_start(struct rte_eth_dev *dev);
123 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
124 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
125 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
126 static void ixgbe_dev_close(struct rte_eth_dev *dev);
127 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
128 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
129 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
130 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
131 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
132 int wait_to_complete);
133 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
134 struct rte_eth_stats *stats);
135 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
136 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
140 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
141 struct rte_eth_dev_info *dev_info);
142 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
143 struct rte_eth_dev_info *dev_info);
144 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
146 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
147 uint16_t vlan_id, int on);
148 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
149 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
150 uint16_t queue, bool on);
151 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
153 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
154 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
155 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
156 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
157 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
159 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
160 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
161 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
162 struct rte_eth_fc_conf *fc_conf);
163 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
164 struct rte_eth_fc_conf *fc_conf);
165 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
166 struct rte_eth_pfc_conf *pfc_conf);
167 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
168 struct rte_eth_rss_reta_entry64 *reta_conf,
170 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
171 struct rte_eth_rss_reta_entry64 *reta_conf,
173 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
174 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
175 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
176 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
177 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
179 static void ixgbe_dev_interrupt_delayed_handler(void *param);
180 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
181 uint32_t index, uint32_t pool);
182 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
183 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
185 /* For Virtual Function support */
186 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
187 struct rte_eth_dev *eth_dev);
188 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
189 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
190 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
191 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
192 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
193 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
194 struct rte_eth_stats *stats);
195 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
196 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
197 uint16_t vlan_id, int on);
198 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
199 uint16_t queue, int on);
200 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
201 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
203 /* For Eth VMDQ APIs support */
204 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
205 ether_addr* mac_addr,uint8_t on);
206 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
207 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
208 uint16_t rx_mask, uint8_t on);
209 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
210 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
211 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
212 uint64_t pool_mask,uint8_t vlan_on);
213 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
214 struct rte_eth_vmdq_mirror_conf *mirror_conf,
215 uint8_t rule_id, uint8_t on);
216 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
219 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
220 uint16_t queue_idx, uint16_t tx_rate);
221 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
222 uint16_t tx_rate, uint64_t q_msk);
224 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
225 struct ether_addr *mac_addr,
226 uint32_t index, uint32_t pool);
227 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
228 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
229 struct rte_syn_filter *filter, uint16_t rx_queue);
230 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
231 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
232 struct rte_syn_filter *filter, uint16_t *rx_queue);
233 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
234 struct rte_ethertype_filter *filter, uint16_t rx_queue);
235 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
237 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
238 struct rte_ethertype_filter *filter, uint16_t *rx_queue);
239 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
240 struct rte_5tuple_filter *filter, uint16_t rx_queue);
241 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
243 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
244 struct rte_5tuple_filter *filter, uint16_t *rx_queue);
246 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
249 * Define VF Stats MACRO for Non "cleared on read" register
251 #define UPDATE_VF_STAT(reg, last, cur) \
253 u32 latest = IXGBE_READ_REG(hw, reg); \
254 cur += latest - last; \
258 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
260 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
261 u64 new_msb = IXGBE_READ_REG(hw, msb); \
262 u64 latest = ((new_msb << 32) | new_lsb); \
263 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
267 #define IXGBE_SET_HWSTRIP(h, q) do{\
268 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
269 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
270 (h)->bitmap[idx] |= 1 << bit;\
273 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
274 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
275 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
276 (h)->bitmap[idx] &= ~(1 << bit);\
279 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
280 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
281 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
282 (r) = (h)->bitmap[idx] >> bit & 1;\
286 * The set of PCI devices this driver supports
288 static struct rte_pci_id pci_id_ixgbe_map[] = {
290 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
291 #include "rte_pci_dev_ids.h"
293 { .vendor_id = 0, /* sentinel */ },
298 * The set of PCI devices this driver supports (for 82599 VF)
300 static struct rte_pci_id pci_id_ixgbevf_map[] = {
302 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
303 #include "rte_pci_dev_ids.h"
304 { .vendor_id = 0, /* sentinel */ },
308 static struct eth_dev_ops ixgbe_eth_dev_ops = {
309 .dev_configure = ixgbe_dev_configure,
310 .dev_start = ixgbe_dev_start,
311 .dev_stop = ixgbe_dev_stop,
312 .dev_set_link_up = ixgbe_dev_set_link_up,
313 .dev_set_link_down = ixgbe_dev_set_link_down,
314 .dev_close = ixgbe_dev_close,
315 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
316 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
317 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
318 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
319 .link_update = ixgbe_dev_link_update,
320 .stats_get = ixgbe_dev_stats_get,
321 .stats_reset = ixgbe_dev_stats_reset,
322 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
323 .dev_infos_get = ixgbe_dev_info_get,
324 .mtu_set = ixgbe_dev_mtu_set,
325 .vlan_filter_set = ixgbe_vlan_filter_set,
326 .vlan_tpid_set = ixgbe_vlan_tpid_set,
327 .vlan_offload_set = ixgbe_vlan_offload_set,
328 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
329 .rx_queue_start = ixgbe_dev_rx_queue_start,
330 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
331 .tx_queue_start = ixgbe_dev_tx_queue_start,
332 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
333 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
334 .rx_queue_release = ixgbe_dev_rx_queue_release,
335 .rx_queue_count = ixgbe_dev_rx_queue_count,
336 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
337 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
338 .tx_queue_release = ixgbe_dev_tx_queue_release,
339 .dev_led_on = ixgbe_dev_led_on,
340 .dev_led_off = ixgbe_dev_led_off,
341 .flow_ctrl_get = ixgbe_flow_ctrl_get,
342 .flow_ctrl_set = ixgbe_flow_ctrl_set,
343 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
344 .mac_addr_add = ixgbe_add_rar,
345 .mac_addr_remove = ixgbe_remove_rar,
346 .uc_hash_table_set = ixgbe_uc_hash_table_set,
347 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
348 .mirror_rule_set = ixgbe_mirror_rule_set,
349 .mirror_rule_reset = ixgbe_mirror_rule_reset,
350 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
351 .set_vf_rx = ixgbe_set_pool_rx,
352 .set_vf_tx = ixgbe_set_pool_tx,
353 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
354 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
355 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
356 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
357 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
358 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
359 .fdir_infos_get = ixgbe_fdir_info_get,
360 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
361 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
362 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
363 .fdir_set_masks = ixgbe_fdir_set_masks,
364 .reta_update = ixgbe_dev_rss_reta_update,
365 .reta_query = ixgbe_dev_rss_reta_query,
366 #ifdef RTE_NIC_BYPASS
367 .bypass_init = ixgbe_bypass_init,
368 .bypass_state_set = ixgbe_bypass_state_store,
369 .bypass_state_show = ixgbe_bypass_state_show,
370 .bypass_event_set = ixgbe_bypass_event_store,
371 .bypass_event_show = ixgbe_bypass_event_show,
372 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
373 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
374 .bypass_ver_show = ixgbe_bypass_ver_show,
375 .bypass_wd_reset = ixgbe_bypass_wd_reset,
376 #endif /* RTE_NIC_BYPASS */
377 .rss_hash_update = ixgbe_dev_rss_hash_update,
378 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
379 .add_syn_filter = ixgbe_add_syn_filter,
380 .remove_syn_filter = ixgbe_remove_syn_filter,
381 .get_syn_filter = ixgbe_get_syn_filter,
382 .add_ethertype_filter = ixgbe_add_ethertype_filter,
383 .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
384 .get_ethertype_filter = ixgbe_get_ethertype_filter,
385 .add_5tuple_filter = ixgbe_add_5tuple_filter,
386 .remove_5tuple_filter = ixgbe_remove_5tuple_filter,
387 .get_5tuple_filter = ixgbe_get_5tuple_filter,
391 * dev_ops for virtual function, bare necessities for basic vf
392 * operation have been implemented
394 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
396 .dev_configure = ixgbevf_dev_configure,
397 .dev_start = ixgbevf_dev_start,
398 .dev_stop = ixgbevf_dev_stop,
399 .link_update = ixgbe_dev_link_update,
400 .stats_get = ixgbevf_dev_stats_get,
401 .stats_reset = ixgbevf_dev_stats_reset,
402 .dev_close = ixgbevf_dev_close,
403 .dev_infos_get = ixgbevf_dev_info_get,
404 .mtu_set = ixgbevf_dev_set_mtu,
405 .vlan_filter_set = ixgbevf_vlan_filter_set,
406 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
407 .vlan_offload_set = ixgbevf_vlan_offload_set,
408 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
409 .rx_queue_release = ixgbe_dev_rx_queue_release,
410 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
411 .tx_queue_release = ixgbe_dev_tx_queue_release,
412 .mac_addr_add = ixgbevf_add_mac_addr,
413 .mac_addr_remove = ixgbevf_remove_mac_addr,
417 * Atomically reads the link status information from global
418 * structure rte_eth_dev.
421 * - Pointer to the structure rte_eth_dev to read from.
422 * - Pointer to the buffer to be saved with the link status.
425 * - On success, zero.
426 * - On failure, negative value.
429 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
430 struct rte_eth_link *link)
432 struct rte_eth_link *dst = link;
433 struct rte_eth_link *src = &(dev->data->dev_link);
435 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
436 *(uint64_t *)src) == 0)
443 * Atomically writes the link status information into global
444 * structure rte_eth_dev.
447 * - Pointer to the structure rte_eth_dev to read from.
448 * - Pointer to the buffer to be saved with the link status.
451 * - On success, zero.
452 * - On failure, negative value.
455 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
456 struct rte_eth_link *link)
458 struct rte_eth_link *dst = &(dev->data->dev_link);
459 struct rte_eth_link *src = link;
461 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
462 *(uint64_t *)src) == 0)
469 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
472 ixgbe_is_sfp(struct ixgbe_hw *hw)
474 switch (hw->phy.type) {
475 case ixgbe_phy_sfp_avago:
476 case ixgbe_phy_sfp_ftl:
477 case ixgbe_phy_sfp_intel:
478 case ixgbe_phy_sfp_unknown:
479 case ixgbe_phy_sfp_passive_tyco:
480 case ixgbe_phy_sfp_passive_unknown:
487 static inline int32_t
488 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
493 status = ixgbe_reset_hw(hw);
495 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
496 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
497 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
498 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
499 IXGBE_WRITE_FLUSH(hw);
505 ixgbe_enable_intr(struct rte_eth_dev *dev)
507 struct ixgbe_interrupt *intr =
508 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
509 struct ixgbe_hw *hw =
510 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
512 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
513 IXGBE_WRITE_FLUSH(hw);
517 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
520 ixgbe_disable_intr(struct ixgbe_hw *hw)
522 PMD_INIT_FUNC_TRACE();
524 if (hw->mac.type == ixgbe_mac_82598EB) {
525 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
527 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
528 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
529 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
531 IXGBE_WRITE_FLUSH(hw);
535 * This function resets queue statistics mapping registers.
536 * From Niantic datasheet, Initialization of Statistics section:
537 * "...if software requires the queue counters, the RQSMR and TQSM registers
538 * must be re-programmed following a device reset.
541 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
545 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
546 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
547 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
553 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
558 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
559 #define NB_QMAP_FIELDS_PER_QSM_REG 4
560 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
562 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
563 struct ixgbe_stat_mapping_registers *stat_mappings =
564 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
565 uint32_t qsmr_mask = 0;
566 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
570 if ((hw->mac.type != ixgbe_mac_82599EB) &&
571 (hw->mac.type != ixgbe_mac_X540) &&
572 (hw->mac.type != ixgbe_mac_X550) &&
573 (hw->mac.type != ixgbe_mac_X550EM_x))
576 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
577 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
580 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
581 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
582 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
585 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
587 /* Now clear any previous stat_idx set */
588 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
590 stat_mappings->tqsm[n] &= ~clearing_mask;
592 stat_mappings->rqsmr[n] &= ~clearing_mask;
594 q_map = (uint32_t)stat_idx;
595 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
596 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
598 stat_mappings->tqsm[n] |= qsmr_mask;
600 stat_mappings->rqsmr[n] |= qsmr_mask;
602 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
603 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
605 PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
606 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
608 /* Now write the mapping in the appropriate register */
610 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
611 stat_mappings->rqsmr[n], n);
612 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
615 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
616 stat_mappings->tqsm[n], n);
617 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
623 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
625 struct ixgbe_stat_mapping_registers *stat_mappings =
626 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
627 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
630 /* write whatever was in stat mapping table to the NIC */
631 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
633 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
636 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
641 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
644 struct ixgbe_dcb_tc_config *tc;
645 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
647 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
648 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
649 for (i = 0; i < dcb_max_tc; i++) {
650 tc = &dcb_config->tc_config[i];
651 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
652 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
653 (uint8_t)(100/dcb_max_tc + (i & 1));
654 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
655 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
656 (uint8_t)(100/dcb_max_tc + (i & 1));
657 tc->pfc = ixgbe_dcb_pfc_disabled;
660 /* Initialize default user to priority mapping, UPx->TC0 */
661 tc = &dcb_config->tc_config[0];
662 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
663 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
664 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
665 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
666 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
668 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
669 dcb_config->pfc_mode_enable = false;
670 dcb_config->vt_mode = true;
671 dcb_config->round_robin_enable = false;
672 /* support all DCB capabilities in 82599 */
673 dcb_config->support.capabilities = 0xFF;
675 /*we only support 4 Tcs for X540, X550 */
676 if (hw->mac.type == ixgbe_mac_X540 ||
677 hw->mac.type == ixgbe_mac_X550 ||
678 hw->mac.type == ixgbe_mac_X550EM_x) {
679 dcb_config->num_tcs.pg_tcs = 4;
680 dcb_config->num_tcs.pfc_tcs = 4;
685 * Ensure that all locks are released before first NVM or PHY access
688 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
693 * Phy lock should not fail in this early stage. If this is the case,
694 * it is due to an improper exit of the application.
695 * So force the release of the faulty lock. Release of common lock
696 * is done automatically by swfw_sync function.
698 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
699 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
700 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
702 ixgbe_release_swfw_semaphore(hw, mask);
705 * These ones are more tricky since they are common to all ports; but
706 * swfw_sync retries last long enough (1s) to be almost sure that if
707 * lock can not be taken it is due to an improper lock of the
710 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
711 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
712 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
714 ixgbe_release_swfw_semaphore(hw, mask);
718 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
719 * It returns 0 on success.
722 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
723 struct rte_eth_dev *eth_dev)
725 struct rte_pci_device *pci_dev;
726 struct ixgbe_hw *hw =
727 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
728 struct ixgbe_vfta * shadow_vfta =
729 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
730 struct ixgbe_hwstrip *hwstrip =
731 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
732 struct ixgbe_dcb_config *dcb_config =
733 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
738 PMD_INIT_FUNC_TRACE();
740 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
741 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
742 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
744 /* for secondary processes, we don't initialise any further as primary
745 * has already done this work. Only check we don't need a different
747 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
748 if (eth_dev->data->scattered_rx)
749 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
752 pci_dev = eth_dev->pci_dev;
754 /* Vendor and Device ID need to be set before init of shared code */
755 hw->device_id = pci_dev->id.device_id;
756 hw->vendor_id = pci_dev->id.vendor_id;
757 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
758 hw->allow_unsupported_sfp = 1;
760 /* Initialize the shared code (base driver) */
761 #ifdef RTE_NIC_BYPASS
762 diag = ixgbe_bypass_init_shared_code(hw);
764 diag = ixgbe_init_shared_code(hw);
765 #endif /* RTE_NIC_BYPASS */
767 if (diag != IXGBE_SUCCESS) {
768 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
772 /* pick up the PCI bus settings for reporting later */
773 ixgbe_get_bus_info(hw);
775 /* Unlock any pending hardware semaphore */
776 ixgbe_swfw_lock_reset(hw);
778 /* Initialize DCB configuration*/
779 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
780 ixgbe_dcb_init(hw,dcb_config);
781 /* Get Hardware Flow Control setting */
782 hw->fc.requested_mode = ixgbe_fc_full;
783 hw->fc.current_mode = ixgbe_fc_full;
784 hw->fc.pause_time = IXGBE_FC_PAUSE;
785 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
786 hw->fc.low_water[i] = IXGBE_FC_LO;
787 hw->fc.high_water[i] = IXGBE_FC_HI;
791 /* Make sure we have a good EEPROM before we read from it */
792 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
793 if (diag != IXGBE_SUCCESS) {
794 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
798 #ifdef RTE_NIC_BYPASS
799 diag = ixgbe_bypass_init_hw(hw);
801 diag = ixgbe_init_hw(hw);
802 #endif /* RTE_NIC_BYPASS */
805 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
806 * is called too soon after the kernel driver unbinding/binding occurs.
807 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
808 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
809 * also called. See ixgbe_identify_phy_82599(). The reason for the
810 * failure is not known, and only occuts when virtualisation features
811 * are disabled in the bios. A delay of 100ms was found to be enough by
812 * trial-and-error, and is doubled to be safe.
814 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
816 diag = ixgbe_init_hw(hw);
819 if (diag == IXGBE_ERR_EEPROM_VERSION) {
820 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
821 "LOM. Please be aware there may be issues associated "
822 "with your hardware.");
823 PMD_INIT_LOG(ERR, "If you are experiencing problems "
824 "please contact your Intel or hardware representative "
825 "who provided you with this hardware.");
826 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
827 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
829 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
833 /* disable interrupt */
834 ixgbe_disable_intr(hw);
836 /* reset mappings for queue statistics hw counters*/
837 ixgbe_reset_qstat_mappings(hw);
839 /* Allocate memory for storing MAC addresses */
840 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
841 hw->mac.num_rar_entries, 0);
842 if (eth_dev->data->mac_addrs == NULL) {
844 "Failed to allocate %u bytes needed to store "
846 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
849 /* Copy the permanent MAC address */
850 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
851 ð_dev->data->mac_addrs[0]);
853 /* Allocate memory for storing hash filter MAC addresses */
854 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
855 IXGBE_VMDQ_NUM_UC_MAC, 0);
856 if (eth_dev->data->hash_mac_addrs == NULL) {
858 "Failed to allocate %d bytes needed to store MAC addresses",
859 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
863 /* initialize the vfta */
864 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
866 /* initialize the hw strip bitmap*/
867 memset(hwstrip, 0, sizeof(*hwstrip));
869 /* initialize PF if max_vfs not zero */
870 ixgbe_pf_host_init(eth_dev);
872 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
873 /* let hardware know driver is loaded */
874 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
875 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
876 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
877 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
878 IXGBE_WRITE_FLUSH(hw);
880 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
881 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
882 (int) hw->mac.type, (int) hw->phy.type,
883 (int) hw->phy.sfp_type);
885 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
886 (int) hw->mac.type, (int) hw->phy.type);
888 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
889 eth_dev->data->port_id, pci_dev->id.vendor_id,
890 pci_dev->id.device_id);
892 rte_intr_callback_register(&(pci_dev->intr_handle),
893 ixgbe_dev_interrupt_handler, (void *)eth_dev);
895 /* enable uio intr after callback register */
896 rte_intr_enable(&(pci_dev->intr_handle));
898 /* enable support intr */
899 ixgbe_enable_intr(eth_dev);
906 * Negotiate mailbox API version with the PF.
907 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
908 * Then we try to negotiate starting with the most recent one.
909 * If all negotiation attempts fail, then we will proceed with
910 * the default one (ixgbe_mbox_api_10).
913 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
917 /* start with highest supported, proceed down */
918 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
924 i != RTE_DIM(sup_ver) &&
925 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
931 generate_random_mac_addr(struct ether_addr *mac_addr)
935 /* Set Organizationally Unique Identifier (OUI) prefix. */
936 mac_addr->addr_bytes[0] = 0x00;
937 mac_addr->addr_bytes[1] = 0x09;
938 mac_addr->addr_bytes[2] = 0xC0;
939 /* Force indication of locally assigned MAC address. */
940 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
941 /* Generate the last 3 bytes of the MAC address with a random number. */
943 memcpy(&mac_addr->addr_bytes[3], &random, 3);
947 * Virtual Function device init
950 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
951 struct rte_eth_dev *eth_dev)
955 struct rte_pci_device *pci_dev;
956 struct ixgbe_hw *hw =
957 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
958 struct ixgbe_vfta * shadow_vfta =
959 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
960 struct ixgbe_hwstrip *hwstrip =
961 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
962 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
964 PMD_INIT_FUNC_TRACE();
966 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
967 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
968 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
970 /* for secondary processes, we don't initialise any further as primary
971 * has already done this work. Only check we don't need a different
973 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
974 if (eth_dev->data->scattered_rx)
975 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
979 pci_dev = eth_dev->pci_dev;
981 hw->device_id = pci_dev->id.device_id;
982 hw->vendor_id = pci_dev->id.vendor_id;
983 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
985 /* initialize the vfta */
986 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
988 /* initialize the hw strip bitmap*/
989 memset(hwstrip, 0, sizeof(*hwstrip));
991 /* Initialize the shared code (base driver) */
992 diag = ixgbe_init_shared_code(hw);
993 if (diag != IXGBE_SUCCESS) {
994 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
998 /* init_mailbox_params */
999 hw->mbx.ops.init_params(hw);
1001 /* Disable the interrupts for VF */
1002 ixgbevf_intr_disable(hw);
1004 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1005 diag = hw->mac.ops.reset_hw(hw);
1008 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1009 * the underlying PF driver has not assigned a MAC address to the VF.
1010 * In this case, assign a random MAC address.
1012 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1013 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1017 /* negotiate mailbox API version to use with the PF. */
1018 ixgbevf_negotiate_api(hw);
1020 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1021 ixgbevf_get_queues(hw, &tcs, &tc);
1023 /* Allocate memory for storing MAC addresses */
1024 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1025 hw->mac.num_rar_entries, 0);
1026 if (eth_dev->data->mac_addrs == NULL) {
1028 "Failed to allocate %u bytes needed to store "
1030 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1034 /* Generate a random MAC address, if none was assigned by PF. */
1035 if (is_zero_ether_addr(perm_addr)) {
1036 generate_random_mac_addr(perm_addr);
1037 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1039 rte_free(eth_dev->data->mac_addrs);
1040 eth_dev->data->mac_addrs = NULL;
1043 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1044 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1045 "%02x:%02x:%02x:%02x:%02x:%02x",
1046 perm_addr->addr_bytes[0],
1047 perm_addr->addr_bytes[1],
1048 perm_addr->addr_bytes[2],
1049 perm_addr->addr_bytes[3],
1050 perm_addr->addr_bytes[4],
1051 perm_addr->addr_bytes[5]);
1054 /* Copy the permanent MAC address */
1055 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1057 /* reset the hardware with the new settings */
1058 diag = hw->mac.ops.start_hw(hw);
1064 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1068 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1069 eth_dev->data->port_id, pci_dev->id.vendor_id,
1070 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1075 static struct eth_driver rte_ixgbe_pmd = {
1077 .name = "rte_ixgbe_pmd",
1078 .id_table = pci_id_ixgbe_map,
1079 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1081 .eth_dev_init = eth_ixgbe_dev_init,
1082 .dev_private_size = sizeof(struct ixgbe_adapter),
1086 * virtual function driver struct
1088 static struct eth_driver rte_ixgbevf_pmd = {
1090 .name = "rte_ixgbevf_pmd",
1091 .id_table = pci_id_ixgbevf_map,
1092 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1094 .eth_dev_init = eth_ixgbevf_dev_init,
1095 .dev_private_size = sizeof(struct ixgbe_adapter),
1099 * Driver initialization routine.
1100 * Invoked once at EAL init time.
1101 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1104 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1106 PMD_INIT_FUNC_TRACE();
1108 rte_eth_driver_register(&rte_ixgbe_pmd);
1113 * VF Driver initialization routine.
1114 * Invoked one at EAL init time.
1115 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1118 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1120 PMD_INIT_FUNC_TRACE();
1122 rte_eth_driver_register(&rte_ixgbevf_pmd);
1127 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1129 struct ixgbe_hw *hw =
1130 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1131 struct ixgbe_vfta * shadow_vfta =
1132 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1137 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1138 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1139 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1144 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1146 /* update local VFTA copy */
1147 shadow_vfta->vfta[vid_idx] = vfta;
1153 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1156 ixgbe_vlan_hw_strip_enable(dev, queue);
1158 ixgbe_vlan_hw_strip_disable(dev, queue);
1162 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1164 struct ixgbe_hw *hw =
1165 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1167 /* Only the high 16-bits is valid */
1168 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1172 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1174 struct ixgbe_hw *hw =
1175 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1178 PMD_INIT_FUNC_TRACE();
1180 /* Filter Table Disable */
1181 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1182 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1184 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1188 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1190 struct ixgbe_hw *hw =
1191 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1192 struct ixgbe_vfta * shadow_vfta =
1193 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1197 PMD_INIT_FUNC_TRACE();
1199 /* Filter Table Enable */
1200 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1201 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1202 vlnctrl |= IXGBE_VLNCTRL_VFE;
1204 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1206 /* write whatever is in local vfta copy */
1207 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1208 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1212 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1214 struct ixgbe_hwstrip *hwstrip =
1215 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1217 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1221 IXGBE_SET_HWSTRIP(hwstrip, queue);
1223 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1227 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1229 struct ixgbe_hw *hw =
1230 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1233 PMD_INIT_FUNC_TRACE();
1235 if (hw->mac.type == ixgbe_mac_82598EB) {
1236 /* No queue level support */
1237 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1241 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1242 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1243 ctrl &= ~IXGBE_RXDCTL_VME;
1244 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1246 /* record those setting for HW strip per queue */
1247 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1251 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1253 struct ixgbe_hw *hw =
1254 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1257 PMD_INIT_FUNC_TRACE();
1259 if (hw->mac.type == ixgbe_mac_82598EB) {
1260 /* No queue level supported */
1261 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1265 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1266 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1267 ctrl |= IXGBE_RXDCTL_VME;
1268 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1270 /* record those setting for HW strip per queue */
1271 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1275 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1277 struct ixgbe_hw *hw =
1278 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1282 PMD_INIT_FUNC_TRACE();
1284 if (hw->mac.type == ixgbe_mac_82598EB) {
1285 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1286 ctrl &= ~IXGBE_VLNCTRL_VME;
1287 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1290 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1291 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1292 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1293 ctrl &= ~IXGBE_RXDCTL_VME;
1294 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1296 /* record those setting for HW strip per queue */
1297 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1303 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1305 struct ixgbe_hw *hw =
1306 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1310 PMD_INIT_FUNC_TRACE();
1312 if (hw->mac.type == ixgbe_mac_82598EB) {
1313 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1314 ctrl |= IXGBE_VLNCTRL_VME;
1315 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1318 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1319 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1320 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1321 ctrl |= IXGBE_RXDCTL_VME;
1322 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1324 /* record those setting for HW strip per queue */
1325 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1331 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1333 struct ixgbe_hw *hw =
1334 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1337 PMD_INIT_FUNC_TRACE();
1339 /* DMATXCTRL: Geric Double VLAN Disable */
1340 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1341 ctrl &= ~IXGBE_DMATXCTL_GDV;
1342 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1344 /* CTRL_EXT: Global Double VLAN Disable */
1345 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1346 ctrl &= ~IXGBE_EXTENDED_VLAN;
1347 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1352 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1354 struct ixgbe_hw *hw =
1355 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1358 PMD_INIT_FUNC_TRACE();
1360 /* DMATXCTRL: Geric Double VLAN Enable */
1361 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1362 ctrl |= IXGBE_DMATXCTL_GDV;
1363 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1365 /* CTRL_EXT: Global Double VLAN Enable */
1366 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1367 ctrl |= IXGBE_EXTENDED_VLAN;
1368 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1371 * VET EXT field in the EXVET register = 0x8100 by default
1372 * So no need to change. Same to VT field of DMATXCTL register
1377 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1379 if(mask & ETH_VLAN_STRIP_MASK){
1380 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1381 ixgbe_vlan_hw_strip_enable_all(dev);
1383 ixgbe_vlan_hw_strip_disable_all(dev);
1386 if(mask & ETH_VLAN_FILTER_MASK){
1387 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1388 ixgbe_vlan_hw_filter_enable(dev);
1390 ixgbe_vlan_hw_filter_disable(dev);
1393 if(mask & ETH_VLAN_EXTEND_MASK){
1394 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1395 ixgbe_vlan_hw_extend_enable(dev);
1397 ixgbe_vlan_hw_extend_disable(dev);
1402 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1404 struct ixgbe_hw *hw =
1405 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1406 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1407 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1408 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1409 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1413 ixgbe_dev_configure(struct rte_eth_dev *dev)
1415 struct ixgbe_interrupt *intr =
1416 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1418 PMD_INIT_FUNC_TRACE();
1420 /* set flag to update link status after init */
1421 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1427 * Configure device link speed and setup link.
1428 * It returns 0 on success.
1431 ixgbe_dev_start(struct rte_eth_dev *dev)
1433 struct ixgbe_hw *hw =
1434 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1435 struct ixgbe_vf_info *vfinfo =
1436 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1437 int err, link_up = 0, negotiate = 0;
1443 PMD_INIT_FUNC_TRACE();
1445 /* IXGBE devices don't support half duplex */
1446 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1447 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1448 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1449 dev->data->dev_conf.link_duplex,
1450 dev->data->port_id);
1455 hw->adapter_stopped = FALSE;
1456 ixgbe_stop_adapter(hw);
1458 /* reinitialize adapter
1459 * this calls reset and start */
1460 status = ixgbe_pf_reset_hw(hw);
1463 hw->mac.ops.start_hw(hw);
1465 /* configure PF module if SRIOV enabled */
1466 ixgbe_pf_host_configure(dev);
1468 /* initialize transmission unit */
1469 ixgbe_dev_tx_init(dev);
1471 /* This can fail when allocating mbufs for descriptor rings */
1472 err = ixgbe_dev_rx_init(dev);
1474 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1478 ixgbe_dev_rxtx_start(dev);
1480 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1481 err = hw->mac.ops.setup_sfp(hw);
1486 /* Turn on the laser */
1487 ixgbe_enable_tx_laser(hw);
1489 /* Skip link setup if loopback mode is enabled for 82599. */
1490 if (hw->mac.type == ixgbe_mac_82599EB &&
1491 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1492 goto skip_link_setup;
1494 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1497 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1501 switch(dev->data->dev_conf.link_speed) {
1502 case ETH_LINK_SPEED_AUTONEG:
1503 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1504 IXGBE_LINK_SPEED_82599_AUTONEG :
1505 IXGBE_LINK_SPEED_82598_AUTONEG;
1507 case ETH_LINK_SPEED_100:
1509 * Invalid for 82598 but error will be detected by
1510 * ixgbe_setup_link()
1512 speed = IXGBE_LINK_SPEED_100_FULL;
1514 case ETH_LINK_SPEED_1000:
1515 speed = IXGBE_LINK_SPEED_1GB_FULL;
1517 case ETH_LINK_SPEED_10000:
1518 speed = IXGBE_LINK_SPEED_10GB_FULL;
1521 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1522 dev->data->dev_conf.link_speed,
1523 dev->data->port_id);
1527 err = ixgbe_setup_link(hw, speed, link_up);
1533 /* check if lsc interrupt is enabled */
1534 if (dev->data->dev_conf.intr_conf.lsc != 0)
1535 ixgbe_dev_lsc_interrupt_setup(dev);
1537 /* resume enabled intr since hw reset */
1538 ixgbe_enable_intr(dev);
1540 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1541 ETH_VLAN_EXTEND_MASK;
1542 ixgbe_vlan_offload_set(dev, mask);
1544 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1545 /* Enable vlan filtering for VMDq */
1546 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1549 /* Configure DCB hw */
1550 ixgbe_configure_dcb(dev);
1552 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1553 err = ixgbe_fdir_configure(dev);
1558 /* Restore vf rate limit */
1559 if (vfinfo != NULL) {
1560 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1561 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1562 if (vfinfo[vf].tx_rate[idx] != 0)
1563 ixgbe_set_vf_rate_limit(dev, vf,
1564 vfinfo[vf].tx_rate[idx],
1568 ixgbe_restore_statistics_mapping(dev);
1573 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1574 ixgbe_dev_clear_queues(dev);
1579 * Stop device: disable rx and tx functions to allow for reconfiguring.
1582 ixgbe_dev_stop(struct rte_eth_dev *dev)
1584 struct rte_eth_link link;
1585 struct ixgbe_hw *hw =
1586 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587 struct ixgbe_vf_info *vfinfo =
1588 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1591 PMD_INIT_FUNC_TRACE();
1593 /* disable interrupts */
1594 ixgbe_disable_intr(hw);
1597 ixgbe_pf_reset_hw(hw);
1598 hw->adapter_stopped = FALSE;
1601 ixgbe_stop_adapter(hw);
1603 for (vf = 0; vfinfo != NULL &&
1604 vf < dev->pci_dev->max_vfs; vf++)
1605 vfinfo[vf].clear_to_send = false;
1607 /* Turn off the laser */
1608 ixgbe_disable_tx_laser(hw);
1610 ixgbe_dev_clear_queues(dev);
1612 /* Clear stored conf */
1613 dev->data->scattered_rx = 0;
1615 /* Clear recorded link status */
1616 memset(&link, 0, sizeof(link));
1617 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1621 * Set device link up: enable tx laser.
1624 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1626 struct ixgbe_hw *hw =
1627 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628 if (hw->mac.type == ixgbe_mac_82599EB) {
1629 #ifdef RTE_NIC_BYPASS
1630 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1631 /* Not suported in bypass mode */
1632 PMD_INIT_LOG(ERR, "Set link up is not supported "
1633 "by device id 0x%x", hw->device_id);
1637 /* Turn on the laser */
1638 ixgbe_enable_tx_laser(hw);
1642 PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1648 * Set device link down: disable tx laser.
1651 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1653 struct ixgbe_hw *hw =
1654 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655 if (hw->mac.type == ixgbe_mac_82599EB) {
1656 #ifdef RTE_NIC_BYPASS
1657 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1658 /* Not suported in bypass mode */
1659 PMD_INIT_LOG(ERR, "Set link down is not supported "
1660 "by device id 0x%x", hw->device_id);
1664 /* Turn off the laser */
1665 ixgbe_disable_tx_laser(hw);
1669 PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1675 * Reest and stop device.
1678 ixgbe_dev_close(struct rte_eth_dev *dev)
1680 struct ixgbe_hw *hw =
1681 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1683 PMD_INIT_FUNC_TRACE();
1685 ixgbe_pf_reset_hw(hw);
1687 ixgbe_dev_stop(dev);
1688 hw->adapter_stopped = 1;
1690 ixgbe_disable_pcie_master(hw);
1692 /* reprogram the RAR[0] in case user changed it. */
1693 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1697 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1700 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1702 struct ixgbe_hw *hw =
1703 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704 struct ixgbe_hw_stats *hw_stats =
1705 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1706 uint32_t bprc, lxon, lxoff, total;
1707 uint64_t total_missed_rx, total_qbrc, total_qprc;
1710 total_missed_rx = 0;
1714 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1715 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1716 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1717 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1719 for (i = 0; i < 8; i++) {
1721 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1722 /* global total per queue */
1723 hw_stats->mpc[i] += mp;
1724 /* Running comprehensive total for stats display */
1725 total_missed_rx += hw_stats->mpc[i];
1726 if (hw->mac.type == ixgbe_mac_82598EB)
1727 hw_stats->rnbc[i] +=
1728 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1729 hw_stats->pxontxc[i] +=
1730 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1731 hw_stats->pxonrxc[i] +=
1732 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1733 hw_stats->pxofftxc[i] +=
1734 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1735 hw_stats->pxoffrxc[i] +=
1736 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1737 hw_stats->pxon2offc[i] +=
1738 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1740 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1741 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1742 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1743 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1744 hw_stats->qbrc[i] +=
1745 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1746 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1747 hw_stats->qbtc[i] +=
1748 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1749 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1751 total_qprc += hw_stats->qprc[i];
1752 total_qbrc += hw_stats->qbrc[i];
1754 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1755 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1756 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1758 /* Note that gprc counts missed packets */
1759 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1761 if (hw->mac.type != ixgbe_mac_82598EB) {
1762 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1763 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1764 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1765 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1766 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1767 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1768 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1769 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1771 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1772 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1773 /* 82598 only has a counter in the high register */
1774 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1775 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1776 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1780 * Workaround: mprc hardware is incorrectly counting
1781 * broadcasts, so for now we subtract those.
1783 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1784 hw_stats->bprc += bprc;
1785 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1786 if (hw->mac.type == ixgbe_mac_82598EB)
1787 hw_stats->mprc -= bprc;
1789 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1790 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1791 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1792 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1793 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1794 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1796 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1797 hw_stats->lxontxc += lxon;
1798 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1799 hw_stats->lxofftxc += lxoff;
1800 total = lxon + lxoff;
1802 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1803 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1804 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1805 hw_stats->gptc -= total;
1806 hw_stats->mptc -= total;
1807 hw_stats->ptc64 -= total;
1808 hw_stats->gotc -= total * ETHER_MIN_LEN;
1810 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1811 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1812 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1813 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1814 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1815 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1816 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1817 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1818 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1819 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1820 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1821 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1822 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1823 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1824 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1825 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1826 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1827 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1828 /* Only read FCOE on 82599 */
1829 if (hw->mac.type != ixgbe_mac_82598EB) {
1830 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1831 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1832 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1833 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1834 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1840 /* Fill out the rte_eth_stats statistics structure */
1841 stats->ipackets = total_qprc;
1842 stats->ibytes = total_qbrc;
1843 stats->opackets = hw_stats->gptc;
1844 stats->obytes = hw_stats->gotc;
1845 stats->imcasts = hw_stats->mprc;
1847 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1848 stats->q_ipackets[i] = hw_stats->qprc[i];
1849 stats->q_opackets[i] = hw_stats->qptc[i];
1850 stats->q_ibytes[i] = hw_stats->qbrc[i];
1851 stats->q_obytes[i] = hw_stats->qbtc[i];
1852 stats->q_errors[i] = hw_stats->qprdc[i];
1856 stats->ibadcrc = hw_stats->crcerrs;
1857 stats->ibadlen = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1858 stats->imissed = total_missed_rx;
1859 stats->ierrors = stats->ibadcrc +
1862 hw_stats->illerrc + hw_stats->errbc;
1867 /* XON/XOFF pause frames */
1868 stats->tx_pause_xon = hw_stats->lxontxc;
1869 stats->rx_pause_xon = hw_stats->lxonrxc;
1870 stats->tx_pause_xoff = hw_stats->lxofftxc;
1871 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1873 /* Flow Director Stats registers */
1874 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1875 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1876 stats->fdirmatch = hw_stats->fdirmatch;
1877 stats->fdirmiss = hw_stats->fdirmiss;
1881 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1883 struct ixgbe_hw_stats *stats =
1884 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1886 /* HW registers are cleared on read */
1887 ixgbe_dev_stats_get(dev, NULL);
1889 /* Reset software totals */
1890 memset(stats, 0, sizeof(*stats));
1894 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1896 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1897 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1898 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1900 /* Good Rx packet, include VF loopback */
1901 UPDATE_VF_STAT(IXGBE_VFGPRC,
1902 hw_stats->last_vfgprc, hw_stats->vfgprc);
1904 /* Good Rx octets, include VF loopback */
1905 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1906 hw_stats->last_vfgorc, hw_stats->vfgorc);
1908 /* Good Tx packet, include VF loopback */
1909 UPDATE_VF_STAT(IXGBE_VFGPTC,
1910 hw_stats->last_vfgptc, hw_stats->vfgptc);
1912 /* Good Tx octets, include VF loopback */
1913 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1914 hw_stats->last_vfgotc, hw_stats->vfgotc);
1916 /* Rx Multicst Packet */
1917 UPDATE_VF_STAT(IXGBE_VFMPRC,
1918 hw_stats->last_vfmprc, hw_stats->vfmprc);
1923 memset(stats, 0, sizeof(*stats));
1924 stats->ipackets = hw_stats->vfgprc;
1925 stats->ibytes = hw_stats->vfgorc;
1926 stats->opackets = hw_stats->vfgptc;
1927 stats->obytes = hw_stats->vfgotc;
1928 stats->imcasts = hw_stats->vfmprc;
1932 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1934 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1935 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1937 /* Sync HW register to the last stats */
1938 ixgbevf_dev_stats_get(dev, NULL);
1940 /* reset HW current stats*/
1941 hw_stats->vfgprc = 0;
1942 hw_stats->vfgorc = 0;
1943 hw_stats->vfgptc = 0;
1944 hw_stats->vfgotc = 0;
1945 hw_stats->vfmprc = 0;
1950 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1952 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1954 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1955 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1956 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1957 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1958 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1959 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1960 dev_info->max_vfs = dev->pci_dev->max_vfs;
1961 if (hw->mac.type == ixgbe_mac_82598EB)
1962 dev_info->max_vmdq_pools = ETH_16_POOLS;
1964 dev_info->max_vmdq_pools = ETH_64_POOLS;
1965 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1966 dev_info->rx_offload_capa =
1967 DEV_RX_OFFLOAD_VLAN_STRIP |
1968 DEV_RX_OFFLOAD_IPV4_CKSUM |
1969 DEV_RX_OFFLOAD_UDP_CKSUM |
1970 DEV_RX_OFFLOAD_TCP_CKSUM;
1971 dev_info->tx_offload_capa =
1972 DEV_TX_OFFLOAD_VLAN_INSERT |
1973 DEV_TX_OFFLOAD_IPV4_CKSUM |
1974 DEV_TX_OFFLOAD_UDP_CKSUM |
1975 DEV_TX_OFFLOAD_TCP_CKSUM |
1976 DEV_TX_OFFLOAD_SCTP_CKSUM;
1978 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1980 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
1981 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
1982 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
1984 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
1988 dev_info->default_txconf = (struct rte_eth_txconf) {
1990 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
1991 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
1992 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
1994 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
1995 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
1996 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1997 ETH_TXQ_FLAGS_NOOFFLOADS,
1999 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2003 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2004 struct rte_eth_dev_info *dev_info)
2006 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2008 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2009 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2010 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2011 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2012 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2013 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2014 dev_info->max_vfs = dev->pci_dev->max_vfs;
2015 if (hw->mac.type == ixgbe_mac_82598EB)
2016 dev_info->max_vmdq_pools = ETH_16_POOLS;
2018 dev_info->max_vmdq_pools = ETH_64_POOLS;
2019 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2020 DEV_RX_OFFLOAD_IPV4_CKSUM |
2021 DEV_RX_OFFLOAD_UDP_CKSUM |
2022 DEV_RX_OFFLOAD_TCP_CKSUM;
2023 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2024 DEV_TX_OFFLOAD_IPV4_CKSUM |
2025 DEV_TX_OFFLOAD_UDP_CKSUM |
2026 DEV_TX_OFFLOAD_TCP_CKSUM |
2027 DEV_TX_OFFLOAD_SCTP_CKSUM;
2029 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2031 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2032 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2033 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2035 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2039 dev_info->default_txconf = (struct rte_eth_txconf) {
2041 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2042 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2043 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2045 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2046 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2047 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2048 ETH_TXQ_FLAGS_NOOFFLOADS,
2052 /* return 0 means link status changed, -1 means not changed */
2054 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2056 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057 struct rte_eth_link link, old;
2058 ixgbe_link_speed link_speed;
2062 link.link_status = 0;
2063 link.link_speed = 0;
2064 link.link_duplex = 0;
2065 memset(&old, 0, sizeof(old));
2066 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2068 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2069 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2070 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2072 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2074 link.link_speed = ETH_LINK_SPEED_100;
2075 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2076 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2077 if (link.link_status == old.link_status)
2083 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2084 if (link.link_status == old.link_status)
2088 link.link_status = 1;
2089 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2091 switch (link_speed) {
2093 case IXGBE_LINK_SPEED_UNKNOWN:
2094 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2095 link.link_speed = ETH_LINK_SPEED_100;
2098 case IXGBE_LINK_SPEED_100_FULL:
2099 link.link_speed = ETH_LINK_SPEED_100;
2102 case IXGBE_LINK_SPEED_1GB_FULL:
2103 link.link_speed = ETH_LINK_SPEED_1000;
2106 case IXGBE_LINK_SPEED_10GB_FULL:
2107 link.link_speed = ETH_LINK_SPEED_10000;
2110 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2112 if (link.link_status == old.link_status)
2119 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2124 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2125 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2126 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2130 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2132 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2135 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2136 fctrl &= (~IXGBE_FCTRL_UPE);
2137 if (dev->data->all_multicast == 1)
2138 fctrl |= IXGBE_FCTRL_MPE;
2140 fctrl &= (~IXGBE_FCTRL_MPE);
2141 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2145 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2147 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2151 fctrl |= IXGBE_FCTRL_MPE;
2152 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2156 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2158 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2161 if (dev->data->promiscuous == 1)
2162 return; /* must remain in all_multicast mode */
2164 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2165 fctrl &= (~IXGBE_FCTRL_MPE);
2166 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2170 * It clears the interrupt causes and enables the interrupt.
2171 * It will be called once only during nic initialized.
2174 * Pointer to struct rte_eth_dev.
2177 * - On success, zero.
2178 * - On failure, a negative value.
2181 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2183 struct ixgbe_interrupt *intr =
2184 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2186 ixgbe_dev_link_status_print(dev);
2187 intr->mask |= IXGBE_EICR_LSC;
2193 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2196 * Pointer to struct rte_eth_dev.
2199 * - On success, zero.
2200 * - On failure, a negative value.
2203 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2206 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207 struct ixgbe_interrupt *intr =
2208 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2210 /* clear all cause mask */
2211 ixgbe_disable_intr(hw);
2213 /* read-on-clear nic registers here */
2214 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2215 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2218 if (eicr & IXGBE_EICR_LSC) {
2219 /* set flag for async link update */
2220 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2223 if (eicr & IXGBE_EICR_MAILBOX)
2224 intr->flags |= IXGBE_FLAG_MAILBOX;
2230 * It gets and then prints the link status.
2233 * Pointer to struct rte_eth_dev.
2236 * - On success, zero.
2237 * - On failure, a negative value.
2240 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2242 struct rte_eth_link link;
2244 memset(&link, 0, sizeof(link));
2245 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2246 if (link.link_status) {
2247 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2248 (int)(dev->data->port_id),
2249 (unsigned)link.link_speed,
2250 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2251 "full-duplex" : "half-duplex");
2253 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2254 (int)(dev->data->port_id));
2256 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2257 dev->pci_dev->addr.domain,
2258 dev->pci_dev->addr.bus,
2259 dev->pci_dev->addr.devid,
2260 dev->pci_dev->addr.function);
2264 * It executes link_update after knowing an interrupt occurred.
2267 * Pointer to struct rte_eth_dev.
2270 * - On success, zero.
2271 * - On failure, a negative value.
2274 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2276 struct ixgbe_interrupt *intr =
2277 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2279 struct rte_eth_link link;
2280 int intr_enable_delay = false;
2282 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2284 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2285 ixgbe_pf_mbx_process(dev);
2286 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2289 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2290 /* get the link status before link update, for predicting later */
2291 memset(&link, 0, sizeof(link));
2292 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2294 ixgbe_dev_link_update(dev, 0);
2297 if (!link.link_status)
2298 /* handle it 1 sec later, wait it being stable */
2299 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2300 /* likely to down */
2302 /* handle it 4 sec later, wait it being stable */
2303 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2305 ixgbe_dev_link_status_print(dev);
2307 intr_enable_delay = true;
2310 if (intr_enable_delay) {
2311 if (rte_eal_alarm_set(timeout * 1000,
2312 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2313 PMD_DRV_LOG(ERR, "Error setting alarm");
2315 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2316 ixgbe_enable_intr(dev);
2317 rte_intr_enable(&(dev->pci_dev->intr_handle));
2325 * Interrupt handler which shall be registered for alarm callback for delayed
2326 * handling specific interrupt to wait for the stable nic state. As the
2327 * NIC interrupt state is not stable for ixgbe after link is just down,
2328 * it needs to wait 4 seconds to get the stable status.
2331 * Pointer to interrupt handle.
2333 * The address of parameter (struct rte_eth_dev *) regsitered before.
2339 ixgbe_dev_interrupt_delayed_handler(void *param)
2341 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2342 struct ixgbe_interrupt *intr =
2343 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2344 struct ixgbe_hw *hw =
2345 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2348 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2349 if (eicr & IXGBE_EICR_MAILBOX)
2350 ixgbe_pf_mbx_process(dev);
2352 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2353 ixgbe_dev_link_update(dev, 0);
2354 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2355 ixgbe_dev_link_status_print(dev);
2356 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2359 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2360 ixgbe_enable_intr(dev);
2361 rte_intr_enable(&(dev->pci_dev->intr_handle));
2365 * Interrupt handler triggered by NIC for handling
2366 * specific interrupt.
2369 * Pointer to interrupt handle.
2371 * The address of parameter (struct rte_eth_dev *) regsitered before.
2377 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2380 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2381 ixgbe_dev_interrupt_get_status(dev);
2382 ixgbe_dev_interrupt_action(dev);
2386 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2388 struct ixgbe_hw *hw;
2390 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2395 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2397 struct ixgbe_hw *hw;
2399 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2404 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2406 struct ixgbe_hw *hw;
2412 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414 fc_conf->pause_time = hw->fc.pause_time;
2415 fc_conf->high_water = hw->fc.high_water[0];
2416 fc_conf->low_water = hw->fc.low_water[0];
2417 fc_conf->send_xon = hw->fc.send_xon;
2418 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2421 * Return rx_pause status according to actual setting of
2424 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2425 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2431 * Return tx_pause status according to actual setting of
2434 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2435 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2440 if (rx_pause && tx_pause)
2441 fc_conf->mode = RTE_FC_FULL;
2443 fc_conf->mode = RTE_FC_RX_PAUSE;
2445 fc_conf->mode = RTE_FC_TX_PAUSE;
2447 fc_conf->mode = RTE_FC_NONE;
2453 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2455 struct ixgbe_hw *hw;
2457 uint32_t rx_buf_size;
2458 uint32_t max_high_water;
2460 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2467 PMD_INIT_FUNC_TRACE();
2469 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2470 if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2472 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2473 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2476 * At least reserve one Ethernet frame for watermark
2477 * high_water/low_water in kilo bytes for ixgbe
2479 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2480 if ((fc_conf->high_water > max_high_water) ||
2481 (fc_conf->high_water < fc_conf->low_water)) {
2482 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2483 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2487 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2488 hw->fc.pause_time = fc_conf->pause_time;
2489 hw->fc.high_water[0] = fc_conf->high_water;
2490 hw->fc.low_water[0] = fc_conf->low_water;
2491 hw->fc.send_xon = fc_conf->send_xon;
2493 err = ixgbe_fc_enable(hw);
2495 /* Not negotiated is not an error case */
2496 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2498 /* check if we want to forward MAC frames - driver doesn't have native
2499 * capability to do that, so we'll write the registers ourselves */
2501 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2503 /* set or clear MFLCN.PMCF bit depending on configuration */
2504 if (fc_conf->mac_ctrl_frame_fwd != 0)
2505 mflcn |= IXGBE_MFLCN_PMCF;
2507 mflcn &= ~IXGBE_MFLCN_PMCF;
2509 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2510 IXGBE_WRITE_FLUSH(hw);
2515 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2520 * ixgbe_pfc_enable_generic - Enable flow control
2521 * @hw: pointer to hardware structure
2522 * @tc_num: traffic class number
2523 * Enable flow control according to the current settings.
2526 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2529 uint32_t mflcn_reg, fccfg_reg;
2531 uint32_t fcrtl, fcrth;
2535 /* Validate the water mark configuration */
2536 if (!hw->fc.pause_time) {
2537 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2541 /* Low water mark of zero causes XOFF floods */
2542 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2543 /* High/Low water can not be 0 */
2544 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2545 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2546 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2550 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2551 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2552 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2556 /* Negotiate the fc mode to use */
2557 ixgbe_fc_autoneg(hw);
2559 /* Disable any previous flow control settings */
2560 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2561 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2563 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2564 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2566 switch (hw->fc.current_mode) {
2569 * If the count of enabled RX Priority Flow control >1,
2570 * and the TX pause can not be disabled
2573 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2574 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2575 if (reg & IXGBE_FCRTH_FCEN)
2579 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2581 case ixgbe_fc_rx_pause:
2583 * Rx Flow control is enabled and Tx Flow control is
2584 * disabled by software override. Since there really
2585 * isn't a way to advertise that we are capable of RX
2586 * Pause ONLY, we will advertise that we support both
2587 * symmetric and asymmetric Rx PAUSE. Later, we will
2588 * disable the adapter's ability to send PAUSE frames.
2590 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2592 * If the count of enabled RX Priority Flow control >1,
2593 * and the TX pause can not be disabled
2596 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2597 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2598 if (reg & IXGBE_FCRTH_FCEN)
2602 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2604 case ixgbe_fc_tx_pause:
2606 * Tx Flow control is enabled, and Rx Flow control is
2607 * disabled by software override.
2609 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2612 /* Flow control (both Rx and Tx) is enabled by SW override. */
2613 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2614 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2617 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2618 ret_val = IXGBE_ERR_CONFIG;
2623 /* Set 802.3x based flow control settings. */
2624 mflcn_reg |= IXGBE_MFLCN_DPF;
2625 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2626 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2628 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2629 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2630 hw->fc.high_water[tc_num]) {
2631 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2632 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2633 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2635 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2637 * In order to prevent Tx hangs when the internal Tx
2638 * switch is enabled we must set the high water mark
2639 * to the maximum FCRTH value. This allows the Tx
2640 * switch to function even under heavy Rx workloads.
2642 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2644 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2646 /* Configure pause time (2 TCs per register) */
2647 reg = hw->fc.pause_time * 0x00010001;
2648 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2649 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2651 /* Configure flow control refresh threshold value */
2652 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2659 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2661 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2662 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2664 if(hw->mac.type != ixgbe_mac_82598EB) {
2665 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2671 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2674 uint32_t rx_buf_size;
2675 uint32_t max_high_water;
2677 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2678 struct ixgbe_hw *hw =
2679 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2680 struct ixgbe_dcb_config *dcb_config =
2681 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2683 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2690 PMD_INIT_FUNC_TRACE();
2692 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2693 tc_num = map[pfc_conf->priority];
2694 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2695 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2697 * At least reserve one Ethernet frame for watermark
2698 * high_water/low_water in kilo bytes for ixgbe
2700 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2701 if ((pfc_conf->fc.high_water > max_high_water) ||
2702 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2703 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2704 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2708 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2709 hw->fc.pause_time = pfc_conf->fc.pause_time;
2710 hw->fc.send_xon = pfc_conf->fc.send_xon;
2711 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2712 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2714 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2716 /* Not negotiated is not an error case */
2717 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2720 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2725 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2726 struct rte_eth_rss_reta_entry64 *reta_conf,
2731 uint16_t idx, shift;
2732 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2734 PMD_INIT_FUNC_TRACE();
2735 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2736 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2737 "(%d) doesn't match the number hardware can supported "
2738 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2742 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2743 idx = i / RTE_RETA_GROUP_SIZE;
2744 shift = i % RTE_RETA_GROUP_SIZE;
2745 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2749 if (mask == IXGBE_4_BIT_MASK)
2752 r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2753 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2754 if (mask & (0x1 << j))
2755 reta |= reta_conf[idx].reta[shift + j] <<
2758 reta |= r & (IXGBE_8_BIT_MASK <<
2761 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2768 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2769 struct rte_eth_rss_reta_entry64 *reta_conf,
2774 uint16_t idx, shift;
2775 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2777 PMD_INIT_FUNC_TRACE();
2778 if (reta_size != ETH_RSS_RETA_SIZE_128) {
2779 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2780 "(%d) doesn't match the number hardware can supported "
2781 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2785 for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2786 idx = i / RTE_RETA_GROUP_SIZE;
2787 shift = i % RTE_RETA_GROUP_SIZE;
2788 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2793 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2794 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2795 if (mask & (0x1 << j))
2796 reta_conf[idx].reta[shift + j] =
2797 ((reta >> (CHAR_BIT * j)) &
2806 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2807 uint32_t index, uint32_t pool)
2809 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810 uint32_t enable_addr = 1;
2812 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2816 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2818 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820 ixgbe_clear_rar(hw, index);
2824 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2828 struct ixgbe_hw *hw;
2829 struct rte_eth_dev_info dev_info;
2830 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2832 ixgbe_dev_info_get(dev, &dev_info);
2834 /* check that mtu is within the allowed range */
2835 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2838 /* refuse mtu that requires the support of scattered packets when this
2839 * feature has not been enabled before. */
2840 if (!dev->data->scattered_rx &&
2841 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2842 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2845 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2846 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2848 /* switch to jumbo mode if needed */
2849 if (frame_size > ETHER_MAX_LEN) {
2850 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2851 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2853 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2854 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2856 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2858 /* update max frame size */
2859 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2861 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2862 maxfrs &= 0x0000FFFF;
2863 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2864 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2870 * Virtual Function operations
2873 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2875 PMD_INIT_FUNC_TRACE();
2877 /* Clear interrupt mask to stop from interrupts being generated */
2878 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2880 IXGBE_WRITE_FLUSH(hw);
2884 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2886 struct rte_eth_conf* conf = &dev->data->dev_conf;
2888 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2889 dev->data->port_id);
2892 * VF has no ability to enable/disable HW CRC
2893 * Keep the persistent behavior the same as Host PF
2895 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2896 if (!conf->rxmode.hw_strip_crc) {
2897 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2898 conf->rxmode.hw_strip_crc = 1;
2901 if (conf->rxmode.hw_strip_crc) {
2902 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2903 conf->rxmode.hw_strip_crc = 0;
2911 ixgbevf_dev_start(struct rte_eth_dev *dev)
2913 struct ixgbe_hw *hw =
2914 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2917 PMD_INIT_FUNC_TRACE();
2919 hw->mac.ops.reset_hw(hw);
2921 /* negotiate mailbox API version to use with the PF. */
2922 ixgbevf_negotiate_api(hw);
2924 ixgbevf_dev_tx_init(dev);
2926 /* This can fail when allocating mbufs for descriptor rings */
2927 err = ixgbevf_dev_rx_init(dev);
2929 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2930 ixgbe_dev_clear_queues(dev);
2935 ixgbevf_set_vfta_all(dev,1);
2938 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2939 ETH_VLAN_EXTEND_MASK;
2940 ixgbevf_vlan_offload_set(dev, mask);
2942 ixgbevf_dev_rxtx_start(dev);
2948 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2950 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952 PMD_INIT_FUNC_TRACE();
2954 hw->adapter_stopped = TRUE;
2955 ixgbe_stop_adapter(hw);
2958 * Clear what we set, but we still keep shadow_vfta to
2959 * restore after device starts
2961 ixgbevf_set_vfta_all(dev,0);
2963 /* Clear stored conf */
2964 dev->data->scattered_rx = 0;
2966 ixgbe_dev_clear_queues(dev);
2970 ixgbevf_dev_close(struct rte_eth_dev *dev)
2972 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974 PMD_INIT_FUNC_TRACE();
2978 ixgbevf_dev_stop(dev);
2980 /* reprogram the RAR[0] in case user changed it. */
2981 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2984 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2986 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2987 struct ixgbe_vfta * shadow_vfta =
2988 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2989 int i = 0, j = 0, vfta = 0, mask = 1;
2991 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2992 vfta = shadow_vfta->vfta[i];
2995 for (j = 0; j < 32; j++){
2997 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3006 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3008 struct ixgbe_hw *hw =
3009 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3010 struct ixgbe_vfta * shadow_vfta =
3011 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3012 uint32_t vid_idx = 0;
3013 uint32_t vid_bit = 0;
3016 PMD_INIT_FUNC_TRACE();
3018 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3019 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3021 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3024 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3025 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3027 /* Save what we set and retore it after device reset */
3029 shadow_vfta->vfta[vid_idx] |= vid_bit;
3031 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3037 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3039 struct ixgbe_hw *hw =
3040 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3043 PMD_INIT_FUNC_TRACE();
3045 if(queue >= hw->mac.max_rx_queues)
3048 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3050 ctrl |= IXGBE_RXDCTL_VME;
3052 ctrl &= ~IXGBE_RXDCTL_VME;
3053 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3055 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3059 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3061 struct ixgbe_hw *hw =
3062 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3066 /* VF function only support hw strip feature, others are not support */
3067 if(mask & ETH_VLAN_STRIP_MASK){
3068 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3070 for(i=0; i < hw->mac.max_rx_queues; i++)
3071 ixgbevf_vlan_strip_queue_set(dev,i,on);
3076 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3080 /* we only need to do this if VMDq is enabled */
3081 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3082 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3083 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3091 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3093 uint32_t vector = 0;
3094 switch (hw->mac.mc_filter_type) {
3095 case 0: /* use bits [47:36] of the address */
3096 vector = ((uc_addr->addr_bytes[4] >> 4) |
3097 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3099 case 1: /* use bits [46:35] of the address */
3100 vector = ((uc_addr->addr_bytes[4] >> 3) |
3101 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3103 case 2: /* use bits [45:34] of the address */
3104 vector = ((uc_addr->addr_bytes[4] >> 2) |
3105 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3107 case 3: /* use bits [43:32] of the address */
3108 vector = ((uc_addr->addr_bytes[4]) |
3109 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3111 default: /* Invalid mc_filter_type */
3115 /* vector can only be 12-bits or boundary will be exceeded */
3121 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3129 const uint32_t ixgbe_uta_idx_mask = 0x7F;
3130 const uint32_t ixgbe_uta_bit_shift = 5;
3131 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3132 const uint32_t bit1 = 0x1;
3134 struct ixgbe_hw *hw =
3135 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3136 struct ixgbe_uta_info *uta_info =
3137 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3139 /* The UTA table only exists on 82599 hardware and newer */
3140 if (hw->mac.type < ixgbe_mac_82599EB)
3143 vector = ixgbe_uta_vector(hw,mac_addr);
3144 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3145 uta_shift = vector & ixgbe_uta_bit_mask;
3147 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3151 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3153 uta_info->uta_in_use++;
3154 reg_val |= (bit1 << uta_shift);
3155 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3157 uta_info->uta_in_use--;
3158 reg_val &= ~(bit1 << uta_shift);
3159 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3162 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3164 if (uta_info->uta_in_use > 0)
3165 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3166 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3168 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3174 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3177 struct ixgbe_hw *hw =
3178 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3179 struct ixgbe_uta_info *uta_info =
3180 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3182 /* The UTA table only exists on 82599 hardware and newer */
3183 if (hw->mac.type < ixgbe_mac_82599EB)
3187 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3188 uta_info->uta_shadow[i] = ~0;
3189 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3192 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3193 uta_info->uta_shadow[i] = 0;
3194 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3202 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3204 uint32_t new_val = orig_val;
3206 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3207 new_val |= IXGBE_VMOLR_AUPE;
3208 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3209 new_val |= IXGBE_VMOLR_ROMPE;
3210 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3211 new_val |= IXGBE_VMOLR_ROPE;
3212 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3213 new_val |= IXGBE_VMOLR_BAM;
3214 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3215 new_val |= IXGBE_VMOLR_MPE;
3221 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3222 uint16_t rx_mask, uint8_t on)
3226 struct ixgbe_hw *hw =
3227 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3228 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3230 if (hw->mac.type == ixgbe_mac_82598EB) {
3231 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3232 " on 82599 hardware and newer");
3235 if (ixgbe_vmdq_mode_check(hw) < 0)
3238 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3245 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3251 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3255 const uint8_t bit1 = 0x1;
3257 struct ixgbe_hw *hw =
3258 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3260 if (ixgbe_vmdq_mode_check(hw) < 0)
3263 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3264 reg = IXGBE_READ_REG(hw, addr);
3272 IXGBE_WRITE_REG(hw, addr,reg);
3278 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3282 const uint8_t bit1 = 0x1;
3284 struct ixgbe_hw *hw =
3285 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3287 if (ixgbe_vmdq_mode_check(hw) < 0)
3290 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3291 reg = IXGBE_READ_REG(hw, addr);
3299 IXGBE_WRITE_REG(hw, addr,reg);
3305 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3306 uint64_t pool_mask, uint8_t vlan_on)
3310 struct ixgbe_hw *hw =
3311 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313 if (ixgbe_vmdq_mode_check(hw) < 0)
3315 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3316 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3317 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3326 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3327 struct rte_eth_vmdq_mirror_conf *mirror_conf,
3328 uint8_t rule_id, uint8_t on)
3330 uint32_t mr_ctl,vlvf;
3331 uint32_t mp_lsb = 0;
3332 uint32_t mv_msb = 0;
3333 uint32_t mv_lsb = 0;
3334 uint32_t mp_msb = 0;
3337 uint64_t vlan_mask = 0;
3339 const uint8_t pool_mask_offset = 32;
3340 const uint8_t vlan_mask_offset = 32;
3341 const uint8_t dst_pool_offset = 8;
3342 const uint8_t rule_mr_offset = 4;
3343 const uint8_t mirror_rule_mask= 0x0F;
3345 struct ixgbe_mirror_info *mr_info =
3346 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3347 struct ixgbe_hw *hw =
3348 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3350 if (ixgbe_vmdq_mode_check(hw) < 0)
3353 /* Check if vlan mask is valid */
3354 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3355 if (mirror_conf->vlan.vlan_mask == 0)
3359 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3360 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3361 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3362 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3363 /* search vlan id related pool vlan filter index */
3364 reg_index = ixgbe_find_vlvf_slot(hw,
3365 mirror_conf->vlan.vlan_id[i]);
3368 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3369 if ((vlvf & IXGBE_VLVF_VIEN) &&
3370 ((vlvf & IXGBE_VLVF_VLANID_MASK)
3371 == mirror_conf->vlan.vlan_id[i]))
3372 vlan_mask |= (1ULL << reg_index);
3379 mv_lsb = vlan_mask & 0xFFFFFFFF;
3380 mv_msb = vlan_mask >> vlan_mask_offset;
3382 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3383 mirror_conf->vlan.vlan_mask;
3384 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3385 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3386 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3387 mirror_conf->vlan.vlan_id[i];
3392 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3393 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3394 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3399 * if enable pool mirror, write related pool mask register,if disable
3400 * pool mirror, clear PFMRVM register
3402 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3404 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3405 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3406 mr_info->mr_conf[rule_id].pool_mask =
3407 mirror_conf->pool_mask;
3412 mr_info->mr_conf[rule_id].pool_mask = 0;
3416 /* read mirror control register and recalculate it */
3417 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3420 mr_ctl |= mirror_conf->rule_type_mask;
3421 mr_ctl &= mirror_rule_mask;
3422 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3424 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3426 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3427 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3429 /* write mirrror control register */
3430 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3432 /* write pool mirrror control register */
3433 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3434 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3435 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3438 /* write VLAN mirrror control register */
3439 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3440 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3441 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3449 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3452 uint32_t lsb_val = 0;
3453 uint32_t msb_val = 0;
3454 const uint8_t rule_mr_offset = 4;
3456 struct ixgbe_hw *hw =
3457 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3458 struct ixgbe_mirror_info *mr_info =
3459 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3461 if (ixgbe_vmdq_mode_check(hw) < 0)
3464 memset(&mr_info->mr_conf[rule_id], 0,
3465 sizeof(struct rte_eth_vmdq_mirror_conf));
3467 /* clear PFVMCTL register */
3468 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3470 /* clear pool mask register */
3471 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3472 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3474 /* clear vlan mask register */
3475 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3476 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3481 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3482 uint16_t queue_idx, uint16_t tx_rate)
3484 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3485 uint32_t rf_dec, rf_int;
3487 uint16_t link_speed = dev->data->dev_link.link_speed;
3489 if (queue_idx >= hw->mac.max_tx_queues)
3493 /* Calculate the rate factor values to set */
3494 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3495 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3496 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3498 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3499 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3500 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3501 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3507 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3508 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3511 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3512 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3513 IXGBE_MAX_JUMBO_FRAME_SIZE))
3514 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3515 IXGBE_MMW_SIZE_JUMBO_FRAME);
3517 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3518 IXGBE_MMW_SIZE_DEFAULT);
3520 /* Set RTTBCNRC of queue X */
3521 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3522 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3523 IXGBE_WRITE_FLUSH(hw);
3528 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3529 uint16_t tx_rate, uint64_t q_msk)
3531 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3532 struct ixgbe_vf_info *vfinfo =
3533 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3534 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3535 uint32_t queue_stride =
3536 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3537 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3538 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3539 uint16_t total_rate = 0;
3541 if (queue_end >= hw->mac.max_tx_queues)
3544 if (vfinfo != NULL) {
3545 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3548 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3550 total_rate += vfinfo[vf_idx].tx_rate[idx];
3555 /* Store tx_rate for this vf. */
3556 for (idx = 0; idx < nb_q_per_pool; idx++) {
3557 if (((uint64_t)0x1 << idx) & q_msk) {
3558 if (vfinfo[vf].tx_rate[idx] != tx_rate)
3559 vfinfo[vf].tx_rate[idx] = tx_rate;
3560 total_rate += tx_rate;
3564 if (total_rate > dev->data->dev_link.link_speed) {
3566 * Reset stored TX rate of the VF if it causes exceed
3569 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3573 /* Set RTTBCNRC of each queue/pool for vf X */
3574 for (; queue_idx <= queue_end; queue_idx++) {
3576 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3584 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3585 __attribute__((unused)) uint32_t index,
3586 __attribute__((unused)) uint32_t pool)
3588 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3592 * On a 82599 VF, adding again the same MAC addr is not an idempotent
3593 * operation. Trap this case to avoid exhausting the [very limited]
3594 * set of PF resources used to store VF MAC addresses.
3596 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3598 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3601 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3605 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3607 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3609 struct ether_addr *mac_addr;
3614 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3615 * not support the deletion of a given MAC address.
3616 * Instead, it imposes to delete all MAC addresses, then to add again
3617 * all MAC addresses with the exception of the one to be deleted.
3619 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3622 * Add again all MAC addresses, with the exception of the deleted one
3623 * and of the permanent MAC address.
3625 for (i = 0, mac_addr = dev->data->mac_addrs;
3626 i < hw->mac.num_rar_entries; i++, mac_addr++) {
3627 /* Skip the deleted MAC address */
3630 /* Skip NULL MAC addresses */
3631 if (is_zero_ether_addr(mac_addr))
3633 /* Skip the permanent MAC address */
3634 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3636 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3639 "Adding again MAC address "
3640 "%02x:%02x:%02x:%02x:%02x:%02x failed "
3642 mac_addr->addr_bytes[0],
3643 mac_addr->addr_bytes[1],
3644 mac_addr->addr_bytes[2],
3645 mac_addr->addr_bytes[3],
3646 mac_addr->addr_bytes[4],
3647 mac_addr->addr_bytes[5],
3656 * dev: Pointer to struct rte_eth_dev.
3657 * filter: ponter to the filter that will be added.
3658 * rx_queue: the queue id the filter assigned to.
3661 * - On success, zero.
3662 * - On failure, a negative value.
3665 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3666 struct rte_syn_filter *filter, uint16_t rx_queue)
3668 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3671 if (hw->mac.type != ixgbe_mac_82599EB)
3674 if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3677 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3679 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3682 synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3683 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3685 if (filter->hig_pri)
3686 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3688 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3690 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3698 * dev: Pointer to struct rte_eth_dev.
3701 * - On success, zero.
3702 * - On failure, a negative value.
3705 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3707 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710 if (hw->mac.type != ixgbe_mac_82599EB)
3713 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3715 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3717 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3722 * get the syn filter's info
3725 * dev: Pointer to struct rte_eth_dev.
3726 * filter: ponter to the filter that returns.
3727 * *rx_queue: pointer to the queue id the filter assigned to.
3730 * - On success, zero.
3731 * - On failure, a negative value.
3734 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3735 struct rte_syn_filter *filter, uint16_t *rx_queue)
3738 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3741 if (hw->mac.type != ixgbe_mac_82599EB)
3744 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3745 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3746 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3747 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3754 * add an ethertype filter
3757 * dev: Pointer to struct rte_eth_dev.
3758 * index: the index the filter allocates.
3759 * filter: ponter to the filter that will be added.
3760 * rx_queue: the queue id the filter assigned to.
3763 * - On success, zero.
3764 * - On failure, a negative value.
3767 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3768 uint16_t index, struct rte_ethertype_filter *filter,
3771 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3772 uint32_t etqf, etqs = 0;
3774 if (hw->mac.type != ixgbe_mac_82599EB)
3777 if (index >= IXGBE_MAX_ETQF_FILTERS ||
3778 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3781 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3782 if (etqf & IXGBE_ETQF_FILTER_EN)
3783 return -EINVAL; /* filter index is in use. */
3786 etqf |= IXGBE_ETQF_FILTER_EN;
3787 etqf |= (uint32_t)filter->ethertype;
3789 if (filter->priority_en) {
3790 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3792 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3793 etqf |= IXGBE_ETQF_UP_EN;
3795 etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3796 etqs |= IXGBE_ETQS_QUEUE_EN;
3798 IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3799 IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3804 * remove an ethertype filter
3807 * dev: Pointer to struct rte_eth_dev.
3808 * index: the index the filter allocates.
3811 * - On success, zero.
3812 * - On failure, a negative value.
3815 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3818 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3820 if (hw->mac.type != ixgbe_mac_82599EB)
3823 if (index >= IXGBE_MAX_ETQF_FILTERS)
3826 IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3827 IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3833 * get an ethertype filter
3836 * dev: Pointer to struct rte_eth_dev.
3837 * index: the index the filter allocates.
3838 * filter: ponter to the filter that will be gotten.
3839 * *rx_queue: the ponited of the queue id the filter assigned to.
3842 * - On success, zero.
3843 * - On failure, a negative value.
3846 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3847 uint16_t index, struct rte_ethertype_filter *filter,
3850 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3851 uint32_t etqf, etqs;
3853 if (hw->mac.type != ixgbe_mac_82599EB)
3856 if (index >= IXGBE_MAX_ETQF_FILTERS)
3859 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3860 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3861 if (etqf & IXGBE_ETQF_FILTER_EN) {
3862 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3863 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3864 if (filter->priority_en)
3865 filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3866 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3872 static inline enum ixgbe_5tuple_protocol
3873 convert_protocol_type(uint8_t protocol_value)
3875 if (protocol_value == IPPROTO_TCP)
3876 return IXGBE_FILTER_PROTOCOL_TCP;
3877 else if (protocol_value == IPPROTO_UDP)
3878 return IXGBE_FILTER_PROTOCOL_UDP;
3879 else if (protocol_value == IPPROTO_SCTP)
3880 return IXGBE_FILTER_PROTOCOL_SCTP;
3882 return IXGBE_FILTER_PROTOCOL_NONE;
3885 static inline uint8_t
3886 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3888 if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3890 else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3892 else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3893 return IPPROTO_SCTP;
3899 * add a 5tuple filter
3902 * dev: Pointer to struct rte_eth_dev.
3903 * index: the index the filter allocates.
3904 * filter: ponter to the filter that will be added.
3905 * rx_queue: the queue id the filter assigned to.
3908 * - On success, zero.
3909 * - On failure, a negative value.
3912 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3913 struct rte_5tuple_filter *filter, uint16_t rx_queue)
3915 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3916 uint32_t ftqf, sdpqf = 0;
3917 uint32_t l34timir = 0;
3918 uint8_t mask = 0xff;
3920 if (hw->mac.type != ixgbe_mac_82599EB)
3923 if (index >= IXGBE_MAX_FTQF_FILTERS ||
3924 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3925 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3926 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3927 return -EINVAL; /* filter index is out of range. */
3929 if (filter->tcp_flags) {
3930 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3934 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3935 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3936 return -EINVAL; /* filter index is in use. */
3939 sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3940 sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3942 ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3943 IXGBE_FTQF_PROTOCOL_MASK);
3944 ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3945 IXGBE_FTQF_PRIORITY_SHIFT);
3946 if (filter->src_ip_mask == 0) /* 0 means compare. */
3947 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3948 if (filter->dst_ip_mask == 0)
3949 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3950 if (filter->src_port_mask == 0)
3951 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3952 if (filter->dst_port_mask == 0)
3953 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3954 if (filter->protocol_mask == 0)
3955 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3956 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3957 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3958 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3960 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3961 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3962 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3963 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3965 l34timir |= IXGBE_L34T_IMIR_RESERVE;
3966 l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3967 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3972 * remove a 5tuple filter
3975 * dev: Pointer to struct rte_eth_dev.
3976 * index: the index the filter allocates.
3979 * - On success, zero.
3980 * - On failure, a negative value.
3983 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3986 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3988 if (hw->mac.type != ixgbe_mac_82599EB)
3991 if (index >= IXGBE_MAX_FTQF_FILTERS)
3992 return -EINVAL; /* filter index is out of range. */
3994 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3995 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3996 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3997 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3998 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4003 * get a 5tuple filter
4006 * dev: Pointer to struct rte_eth_dev.
4007 * index: the index the filter allocates
4008 * filter: ponter to the filter that returns.
4009 * *rx_queue: pointer of the queue id the filter assigned to.
4012 * - On success, zero.
4013 * - On failure, a negative value.
4016 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
4017 struct rte_5tuple_filter *filter, uint16_t *rx_queue)
4019 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4020 uint32_t sdpqf, ftqf, l34timir;
4022 enum ixgbe_5tuple_protocol proto;
4024 if (hw->mac.type != ixgbe_mac_82599EB)
4027 if (index >= IXGBE_MAX_FTQF_FILTERS)
4028 return -EINVAL; /* filter index is out of range. */
4030 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
4031 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
4032 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
4033 filter->protocol = revert_protocol_type(proto);
4034 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
4035 IXGBE_FTQF_PRIORITY_MASK;
4036 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
4037 IXGBE_FTQF_5TUPLE_MASK_MASK);
4038 filter->src_ip_mask =
4039 (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
4040 filter->dst_ip_mask =
4041 (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
4042 filter->src_port_mask =
4043 (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
4044 filter->dst_port_mask =
4045 (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
4046 filter->protocol_mask =
4047 (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
4049 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
4050 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
4051 IXGBE_SDPQF_DSTPORT_SHIFT;
4052 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
4053 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
4054 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
4056 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
4057 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
4058 IXGBE_L34T_IMIR_QUEUE_SHIFT;
4065 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4067 struct ixgbe_hw *hw;
4068 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4070 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4072 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4075 /* refuse mtu that requires the support of scattered packets when this
4076 * feature has not been enabled before. */
4077 if (!dev->data->scattered_rx &&
4078 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4079 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4083 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4084 * request of the version 2.0 of the mailbox API.
4085 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4086 * of the mailbox API.
4087 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4088 * prior to 3.11.33 which contains the following change:
4089 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4091 ixgbevf_rlpml_set_vf(hw, max_frame);
4093 /* update max frame size */
4094 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4098 static struct rte_driver rte_ixgbe_driver = {
4100 .init = rte_ixgbe_pmd_init,
4103 static struct rte_driver rte_ixgbevf_driver = {
4105 .init = rte_ixgbevf_pmd_init,
4108 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4109 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);