lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "ixgbe/ixgbe_api.h"
  67 #include "ixgbe/ixgbe_vf.h"
  68 #include "ixgbe/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 /*
  96  *  Default values for RX/TX configuration
  97  */
  98 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  99 #define IXGBE_DEFAULT_RX_PTHRESH      8
 100 #define IXGBE_DEFAULT_RX_HTHRESH      8
 101 #define IXGBE_DEFAULT_RX_WTHRESH      0
 102
 103 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 104 #define IXGBE_DEFAULT_TX_PTHRESH      32
 105 #define IXGBE_DEFAULT_TX_HTHRESH      0
 106 #define IXGBE_DEFAULT_TX_WTHRESH      0
 107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 108
 109 /* Bit shift and mask */
 110 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 111 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 112 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 113 #define IXGBE_8_BIT_MASK   UINT8_MAX
 114
 115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 116
 117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 118
 119 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
 120                 struct rte_eth_dev *eth_dev);
 121 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 122 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 123 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 124 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 125 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 126 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 130 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 131 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 132                                 int wait_to_complete);
 133 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 134                                 struct rte_eth_stats *stats);
 135 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 136 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 137                                              uint16_t queue_id,
 138                                              uint8_t stat_idx,
 139                                              uint8_t is_rx);
 140 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 141                                struct rte_eth_dev_info *dev_info);
 142 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 143                                  struct rte_eth_dev_info *dev_info);
 144 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 145
 146 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 147                 uint16_t vlan_id, int on);
 148 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 149 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 150                 uint16_t queue, bool on);
 151 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 152                 int on);
 153 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 154 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 155 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 156 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 157 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 158
 159 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 161 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 162                                struct rte_eth_fc_conf *fc_conf);
 163 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 164                                struct rte_eth_fc_conf *fc_conf);
 165 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 166                 struct rte_eth_pfc_conf *pfc_conf);
 167 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 168                         struct rte_eth_rss_reta_entry64 *reta_conf,
 169                         uint16_t reta_size);
 170 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 171                         struct rte_eth_rss_reta_entry64 *reta_conf,
 172                         uint16_t reta_size);
 173 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 174 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 178                 void *param);
 179 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 180 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 181                 uint32_t index, uint32_t pool);
 182 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 183 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 184
 185 /* For Virtual Function support */
 186 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 187                 struct rte_eth_dev *eth_dev);
 188 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 189 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 190 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 191 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 192 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 193 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 194                 struct rte_eth_stats *stats);
 195 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 196 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 197                 uint16_t vlan_id, int on);
 198 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 199                 uint16_t queue, int on);
 200 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 201 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 202
 203 /* For Eth VMDQ APIs support */
 204 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 205                 ether_addr* mac_addr,uint8_t on);
 206 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 207 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 208                 uint16_t rx_mask, uint8_t on);
 209 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 210 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 211 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 212                 uint64_t pool_mask,uint8_t vlan_on);
 213 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 214                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 215                 uint8_t rule_id, uint8_t on);
 216 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 217                 uint8_t rule_id);
 218
 219 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 220                 uint16_t queue_idx, uint16_t tx_rate);
 221 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 222                 uint16_t tx_rate, uint64_t q_msk);
 223
 224 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 225                                  struct ether_addr *mac_addr,
 226                                  uint32_t index, uint32_t pool);
 227 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 228 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
 229                         struct rte_syn_filter *filter, uint16_t rx_queue);
 230 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
 231 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
 232                         struct rte_syn_filter *filter, uint16_t *rx_queue);
 233 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 234                         struct rte_ethertype_filter *filter, uint16_t rx_queue);
 235 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
 236                         uint16_t index);
 237 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
 238                         struct rte_ethertype_filter *filter, uint16_t *rx_queue);
 239 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 240                         struct rte_5tuple_filter *filter, uint16_t rx_queue);
 241 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 242                         uint16_t index);
 243 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
 244                         struct rte_5tuple_filter *filter, uint16_t *rx_queue);
 245
 246 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 247
 248 /*
 249  * Define VF Stats MACRO for Non "cleared on read" register
 250  */
 251 #define UPDATE_VF_STAT(reg, last, cur)                          \
 252 {                                                               \
 253         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 254         cur += latest - last;                                   \
 255         last = latest;                                          \
 256 }
 257
 258 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 259 {                                                                \
 260         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 261         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 262         u64 latest = ((new_msb << 32) | new_lsb);                \
 263         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 264         last = latest;                                           \
 265 }
 266
 267 #define IXGBE_SET_HWSTRIP(h, q) do{\
 268                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 269                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 270                 (h)->bitmap[idx] |= 1 << bit;\
 271         }while(0)
 272
 273 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 274                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 275                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 276                 (h)->bitmap[idx] &= ~(1 << bit);\
 277         }while(0)
 278
 279 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 280                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 281                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 282                 (r) = (h)->bitmap[idx] >> bit & 1;\
 283         }while(0)
 284
 285 /*
 286  * The set of PCI devices this driver supports
 287  */
 288 static struct rte_pci_id pci_id_ixgbe_map[] = {
 289
 290 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 291 #include "rte_pci_dev_ids.h"
 292
 293 { .vendor_id = 0, /* sentinel */ },
 294 };
 295
 296
 297 /*
 298  * The set of PCI devices this driver supports (for 82599 VF)
 299  */
 300 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 301
 302 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 303 #include "rte_pci_dev_ids.h"
 304 { .vendor_id = 0, /* sentinel */ },
 305
 306 };
 307
 308 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 309         .dev_configure        = ixgbe_dev_configure,
 310         .dev_start            = ixgbe_dev_start,
 311         .dev_stop             = ixgbe_dev_stop,
 312         .dev_set_link_up    = ixgbe_dev_set_link_up,
 313         .dev_set_link_down  = ixgbe_dev_set_link_down,
 314         .dev_close            = ixgbe_dev_close,
 315         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 316         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 317         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 318         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 319         .link_update          = ixgbe_dev_link_update,
 320         .stats_get            = ixgbe_dev_stats_get,
 321         .stats_reset          = ixgbe_dev_stats_reset,
 322         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 323         .dev_infos_get        = ixgbe_dev_info_get,
 324         .mtu_set              = ixgbe_dev_mtu_set,
 325         .vlan_filter_set      = ixgbe_vlan_filter_set,
 326         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 327         .vlan_offload_set     = ixgbe_vlan_offload_set,
 328         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 329         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 330         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 331         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 332         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 333         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 334         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 335         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 336         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 337         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 338         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 339         .dev_led_on           = ixgbe_dev_led_on,
 340         .dev_led_off          = ixgbe_dev_led_off,
 341         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 342         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 343         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 344         .mac_addr_add         = ixgbe_add_rar,
 345         .mac_addr_remove      = ixgbe_remove_rar,
 346         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 347         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 348         .mirror_rule_set      = ixgbe_mirror_rule_set,
 349         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 350         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 351         .set_vf_rx            = ixgbe_set_pool_rx,
 352         .set_vf_tx            = ixgbe_set_pool_tx,
 353         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 354         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 355         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 356         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 357         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 358         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 359         .fdir_infos_get               = ixgbe_fdir_info_get,
 360         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 361         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 362         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 363         .fdir_set_masks               = ixgbe_fdir_set_masks,
 364         .reta_update          = ixgbe_dev_rss_reta_update,
 365         .reta_query           = ixgbe_dev_rss_reta_query,
 366 #ifdef RTE_NIC_BYPASS
 367         .bypass_init          = ixgbe_bypass_init,
 368         .bypass_state_set     = ixgbe_bypass_state_store,
 369         .bypass_state_show    = ixgbe_bypass_state_show,
 370         .bypass_event_set     = ixgbe_bypass_event_store,
 371         .bypass_event_show    = ixgbe_bypass_event_show,
 372         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 373         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 374         .bypass_ver_show      = ixgbe_bypass_ver_show,
 375         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 376 #endif /* RTE_NIC_BYPASS */
 377         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 378         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 379         .add_syn_filter          = ixgbe_add_syn_filter,
 380         .remove_syn_filter       = ixgbe_remove_syn_filter,
 381         .get_syn_filter          = ixgbe_get_syn_filter,
 382         .add_ethertype_filter    = ixgbe_add_ethertype_filter,
 383         .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
 384         .get_ethertype_filter    = ixgbe_get_ethertype_filter,
 385         .add_5tuple_filter       = ixgbe_add_5tuple_filter,
 386         .remove_5tuple_filter    = ixgbe_remove_5tuple_filter,
 387         .get_5tuple_filter       = ixgbe_get_5tuple_filter,
 388 };
 389
 390 /*
 391  * dev_ops for virtual function, bare necessities for basic vf
 392  * operation have been implemented
 393  */
 394 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 395
 396         .dev_configure        = ixgbevf_dev_configure,
 397         .dev_start            = ixgbevf_dev_start,
 398         .dev_stop             = ixgbevf_dev_stop,
 399         .link_update          = ixgbe_dev_link_update,
 400         .stats_get            = ixgbevf_dev_stats_get,
 401         .stats_reset          = ixgbevf_dev_stats_reset,
 402         .dev_close            = ixgbevf_dev_close,
 403         .dev_infos_get        = ixgbevf_dev_info_get,
 404         .mtu_set              = ixgbevf_dev_set_mtu,
 405         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 406         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 407         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 408         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 409         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 410         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 411         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 412         .mac_addr_add         = ixgbevf_add_mac_addr,
 413         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 414 };
 415
 416 /**
 417  * Atomically reads the link status information from global
 418  * structure rte_eth_dev.
 419  *
 420  * @param dev
 421  *   - Pointer to the structure rte_eth_dev to read from.
 422  *   - Pointer to the buffer to be saved with the link status.
 423  *
 424  * @return
 425  *   - On success, zero.
 426  *   - On failure, negative value.
 427  */
 428 static inline int
 429 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 430                                 struct rte_eth_link *link)
 431 {
 432         struct rte_eth_link *dst = link;
 433         struct rte_eth_link *src = &(dev->data->dev_link);
 434
 435         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 436                                         *(uint64_t *)src) == 0)
 437                 return -1;
 438
 439         return 0;
 440 }
 441
 442 /**
 443  * Atomically writes the link status information into global
 444  * structure rte_eth_dev.
 445  *
 446  * @param dev
 447  *   - Pointer to the structure rte_eth_dev to read from.
 448  *   - Pointer to the buffer to be saved with the link status.
 449  *
 450  * @return
 451  *   - On success, zero.
 452  *   - On failure, negative value.
 453  */
 454 static inline int
 455 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 456                                 struct rte_eth_link *link)
 457 {
 458         struct rte_eth_link *dst = &(dev->data->dev_link);
 459         struct rte_eth_link *src = link;
 460
 461         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 462                                         *(uint64_t *)src) == 0)
 463                 return -1;
 464
 465         return 0;
 466 }
 467
 468 /*
 469  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 470  */
 471 static inline int
 472 ixgbe_is_sfp(struct ixgbe_hw *hw)
 473 {
 474         switch (hw->phy.type) {
 475         case ixgbe_phy_sfp_avago:
 476         case ixgbe_phy_sfp_ftl:
 477         case ixgbe_phy_sfp_intel:
 478         case ixgbe_phy_sfp_unknown:
 479         case ixgbe_phy_sfp_passive_tyco:
 480         case ixgbe_phy_sfp_passive_unknown:
 481                 return 1;
 482         default:
 483                 return 0;
 484         }
 485 }
 486
 487 static inline int32_t
 488 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 489 {
 490         uint32_t ctrl_ext;
 491         int32_t status;
 492
 493         status = ixgbe_reset_hw(hw);
 494
 495         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 496         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 497         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 498         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 499         IXGBE_WRITE_FLUSH(hw);
 500
 501         return status;
 502 }
 503
 504 static inline void
 505 ixgbe_enable_intr(struct rte_eth_dev *dev)
 506 {
 507         struct ixgbe_interrupt *intr =
 508                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 509         struct ixgbe_hw *hw =
 510                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 511
 512         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 513         IXGBE_WRITE_FLUSH(hw);
 514 }
 515
 516 /*
 517  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 518  */
 519 static void
 520 ixgbe_disable_intr(struct ixgbe_hw *hw)
 521 {
 522         PMD_INIT_FUNC_TRACE();
 523
 524         if (hw->mac.type == ixgbe_mac_82598EB) {
 525                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 526         } else {
 527                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 528                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 529                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 530         }
 531         IXGBE_WRITE_FLUSH(hw);
 532 }
 533
 534 /*
 535  * This function resets queue statistics mapping registers.
 536  * From Niantic datasheet, Initialization of Statistics section:
 537  * "...if software requires the queue counters, the RQSMR and TQSM registers
 538  * must be re-programmed following a device reset.
 539  */
 540 static void
 541 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 542 {
 543         uint32_t i;
 544
 545         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 546                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 547                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 548         }
 549 }
 550
 551
 552 static int
 553 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 554                                   uint16_t queue_id,
 555                                   uint8_t stat_idx,
 556                                   uint8_t is_rx)
 557 {
 558 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 559 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 560 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 561
 562         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 563         struct ixgbe_stat_mapping_registers *stat_mappings =
 564                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 565         uint32_t qsmr_mask = 0;
 566         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 567         uint32_t q_map;
 568         uint8_t n, offset;
 569
 570         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 571                 (hw->mac.type != ixgbe_mac_X540) &&
 572                 (hw->mac.type != ixgbe_mac_X550) &&
 573                 (hw->mac.type != ixgbe_mac_X550EM_x))
 574                 return -ENOSYS;
 575
 576         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 577                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 578                      queue_id, stat_idx);
 579
 580         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 581         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 582                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 583                 return -EIO;
 584         }
 585         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 586
 587         /* Now clear any previous stat_idx set */
 588         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 589         if (!is_rx)
 590                 stat_mappings->tqsm[n] &= ~clearing_mask;
 591         else
 592                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 593
 594         q_map = (uint32_t)stat_idx;
 595         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 596         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 597         if (!is_rx)
 598                 stat_mappings->tqsm[n] |= qsmr_mask;
 599         else
 600                 stat_mappings->rqsmr[n] |= qsmr_mask;
 601
 602         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 603                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 604                      queue_id, stat_idx);
 605         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 606                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 607
 608         /* Now write the mapping in the appropriate register */
 609         if (is_rx) {
 610                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 611                              stat_mappings->rqsmr[n], n);
 612                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 613         }
 614         else {
 615                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 616                              stat_mappings->tqsm[n], n);
 617                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 618         }
 619         return 0;
 620 }
 621
 622 static void
 623 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 624 {
 625         struct ixgbe_stat_mapping_registers *stat_mappings =
 626                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 627         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 628         int i;
 629
 630         /* write whatever was in stat mapping table to the NIC */
 631         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 632                 /* rx */
 633                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 634
 635                 /* tx */
 636                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 637         }
 638 }
 639
 640 static void
 641 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 642 {
 643         uint8_t i;
 644         struct ixgbe_dcb_tc_config *tc;
 645         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 646
 647         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 648         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 649         for (i = 0; i < dcb_max_tc; i++) {
 650                 tc = &dcb_config->tc_config[i];
 651                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 652                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 653                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 654                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 655                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 656                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 657                 tc->pfc = ixgbe_dcb_pfc_disabled;
 658         }
 659
 660         /* Initialize default user to priority mapping, UPx->TC0 */
 661         tc = &dcb_config->tc_config[0];
 662         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 663         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 664         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 665                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 666                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 667         }
 668         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 669         dcb_config->pfc_mode_enable = false;
 670         dcb_config->vt_mode = true;
 671         dcb_config->round_robin_enable = false;
 672         /* support all DCB capabilities in 82599 */
 673         dcb_config->support.capabilities = 0xFF;
 674
 675         /*we only support 4 Tcs for X540, X550 */
 676         if (hw->mac.type == ixgbe_mac_X540 ||
 677                 hw->mac.type == ixgbe_mac_X550 ||
 678                 hw->mac.type == ixgbe_mac_X550EM_x) {
 679                 dcb_config->num_tcs.pg_tcs = 4;
 680                 dcb_config->num_tcs.pfc_tcs = 4;
 681         }
 682 }
 683
 684 /*
 685  * Ensure that all locks are released before first NVM or PHY access
 686  */
 687 static void
 688 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 689 {
 690         uint16_t mask;
 691
 692         /*
 693          * Phy lock should not fail in this early stage. If this is the case,
 694          * it is due to an improper exit of the application.
 695          * So force the release of the faulty lock. Release of common lock
 696          * is done automatically by swfw_sync function.
 697          */
 698         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 699         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 700                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 701         }
 702         ixgbe_release_swfw_semaphore(hw, mask);
 703
 704         /*
 705          * These ones are more tricky since they are common to all ports; but
 706          * swfw_sync retries last long enough (1s) to be almost sure that if
 707          * lock can not be taken it is due to an improper lock of the
 708          * semaphore.
 709          */
 710         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 711         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 712                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 713         }
 714         ixgbe_release_swfw_semaphore(hw, mask);
 715 }
 716
 717 /*
 718  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 719  * It returns 0 on success.
 720  */
 721 static int
 722 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 723                      struct rte_eth_dev *eth_dev)
 724 {
 725         struct rte_pci_device *pci_dev;
 726         struct ixgbe_hw *hw =
 727                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 728         struct ixgbe_vfta * shadow_vfta =
 729                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 730         struct ixgbe_hwstrip *hwstrip =
 731                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 732         struct ixgbe_dcb_config *dcb_config =
 733                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 734         uint32_t ctrl_ext;
 735         uint16_t csum;
 736         int diag, i;
 737
 738         PMD_INIT_FUNC_TRACE();
 739
 740         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 741         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 742         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 743
 744         /* for secondary processes, we don't initialise any further as primary
 745          * has already done this work. Only check we don't need a different
 746          * RX function */
 747         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 748                 if (eth_dev->data->scattered_rx)
 749                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 750                 return 0;
 751         }
 752         pci_dev = eth_dev->pci_dev;
 753
 754         /* Vendor and Device ID need to be set before init of shared code */
 755         hw->device_id = pci_dev->id.device_id;
 756         hw->vendor_id = pci_dev->id.vendor_id;
 757         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 758         hw->allow_unsupported_sfp = 1;
 759
 760         /* Initialize the shared code (base driver) */
 761 #ifdef RTE_NIC_BYPASS
 762         diag = ixgbe_bypass_init_shared_code(hw);
 763 #else
 764         diag = ixgbe_init_shared_code(hw);
 765 #endif /* RTE_NIC_BYPASS */
 766
 767         if (diag != IXGBE_SUCCESS) {
 768                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 769                 return -EIO;
 770         }
 771
 772         /* pick up the PCI bus settings for reporting later */
 773         ixgbe_get_bus_info(hw);
 774
 775         /* Unlock any pending hardware semaphore */
 776         ixgbe_swfw_lock_reset(hw);
 777
 778         /* Initialize DCB configuration*/
 779         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 780         ixgbe_dcb_init(hw,dcb_config);
 781         /* Get Hardware Flow Control setting */
 782         hw->fc.requested_mode = ixgbe_fc_full;
 783         hw->fc.current_mode = ixgbe_fc_full;
 784         hw->fc.pause_time = IXGBE_FC_PAUSE;
 785         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 786                 hw->fc.low_water[i] = IXGBE_FC_LO;
 787                 hw->fc.high_water[i] = IXGBE_FC_HI;
 788         }
 789         hw->fc.send_xon = 1;
 790
 791         /* Make sure we have a good EEPROM before we read from it */
 792         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 793         if (diag != IXGBE_SUCCESS) {
 794                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 795                 return -EIO;
 796         }
 797
 798 #ifdef RTE_NIC_BYPASS
 799         diag = ixgbe_bypass_init_hw(hw);
 800 #else
 801         diag = ixgbe_init_hw(hw);
 802 #endif /* RTE_NIC_BYPASS */
 803
 804         /*
 805          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 806          * is called too soon after the kernel driver unbinding/binding occurs.
 807          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 808          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 809          * also called. See ixgbe_identify_phy_82599(). The reason for the
 810          * failure is not known, and only occuts when virtualisation features
 811          * are disabled in the bios. A delay of 100ms  was found to be enough by
 812          * trial-and-error, and is doubled to be safe.
 813          */
 814         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 815                 rte_delay_ms(200);
 816                 diag = ixgbe_init_hw(hw);
 817         }
 818
 819         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 820                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 821                     "LOM.  Please be aware there may be issues associated "
 822                     "with your hardware.");
 823                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 824                     "please contact your Intel or hardware representative "
 825                     "who provided you with this hardware.");
 826         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 827                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 828         if (diag) {
 829                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 830                 return -EIO;
 831         }
 832
 833         /* disable interrupt */
 834         ixgbe_disable_intr(hw);
 835
 836         /* reset mappings for queue statistics hw counters*/
 837         ixgbe_reset_qstat_mappings(hw);
 838
 839         /* Allocate memory for storing MAC addresses */
 840         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 841                         hw->mac.num_rar_entries, 0);
 842         if (eth_dev->data->mac_addrs == NULL) {
 843                 PMD_INIT_LOG(ERR,
 844                         "Failed to allocate %u bytes needed to store "
 845                         "MAC addresses",
 846                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 847                 return -ENOMEM;
 848         }
 849         /* Copy the permanent MAC address */
 850         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 851                         &eth_dev->data->mac_addrs[0]);
 852
 853         /* Allocate memory for storing hash filter MAC addresses */
 854         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 855                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 856         if (eth_dev->data->hash_mac_addrs == NULL) {
 857                 PMD_INIT_LOG(ERR,
 858                         "Failed to allocate %d bytes needed to store MAC addresses",
 859                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 860                 return -ENOMEM;
 861         }
 862
 863         /* initialize the vfta */
 864         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 865
 866         /* initialize the hw strip bitmap*/
 867         memset(hwstrip, 0, sizeof(*hwstrip));
 868
 869         /* initialize PF if max_vfs not zero */
 870         ixgbe_pf_host_init(eth_dev);
 871
 872         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 873         /* let hardware know driver is loaded */
 874         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 875         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 876         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 877         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 878         IXGBE_WRITE_FLUSH(hw);
 879
 880         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 881                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 882                              (int) hw->mac.type, (int) hw->phy.type,
 883                              (int) hw->phy.sfp_type);
 884         else
 885                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 886                              (int) hw->mac.type, (int) hw->phy.type);
 887
 888         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 889                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 890                         pci_dev->id.device_id);
 891
 892         rte_intr_callback_register(&(pci_dev->intr_handle),
 893                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 894
 895         /* enable uio intr after callback register */
 896         rte_intr_enable(&(pci_dev->intr_handle));
 897
 898         /* enable support intr */
 899         ixgbe_enable_intr(eth_dev);
 900
 901         return 0;
 902 }
 903
 904
 905 /*
 906  * Negotiate mailbox API version with the PF.
 907  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 908  * Then we try to negotiate starting with the most recent one.
 909  * If all negotiation attempts fail, then we will proceed with
 910  * the default one (ixgbe_mbox_api_10).
 911  */
 912 static void
 913 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 914 {
 915         int32_t i;
 916
 917         /* start with highest supported, proceed down */
 918         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 919                 ixgbe_mbox_api_11,
 920                 ixgbe_mbox_api_10,
 921         };
 922
 923         for (i = 0;
 924                         i != RTE_DIM(sup_ver) &&
 925                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 926                         i++)
 927                 ;
 928 }
 929
 930 static void
 931 generate_random_mac_addr(struct ether_addr *mac_addr)
 932 {
 933         uint64_t random;
 934
 935         /* Set Organizationally Unique Identifier (OUI) prefix. */
 936         mac_addr->addr_bytes[0] = 0x00;
 937         mac_addr->addr_bytes[1] = 0x09;
 938         mac_addr->addr_bytes[2] = 0xC0;
 939         /* Force indication of locally assigned MAC address. */
 940         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 941         /* Generate the last 3 bytes of the MAC address with a random number. */
 942         random = rte_rand();
 943         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 944 }
 945
 946 /*
 947  * Virtual Function device init
 948  */
 949 static int
 950 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 951                      struct rte_eth_dev *eth_dev)
 952 {
 953         int diag;
 954         uint32_t tc, tcs;
 955         struct rte_pci_device *pci_dev;
 956         struct ixgbe_hw *hw =
 957                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 958         struct ixgbe_vfta * shadow_vfta =
 959                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 960         struct ixgbe_hwstrip *hwstrip =
 961                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 962         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 963
 964         PMD_INIT_FUNC_TRACE();
 965
 966         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 967         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 968         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 969
 970         /* for secondary processes, we don't initialise any further as primary
 971          * has already done this work. Only check we don't need a different
 972          * RX function */
 973         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 974                 if (eth_dev->data->scattered_rx)
 975                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 976                 return 0;
 977         }
 978
 979         pci_dev = eth_dev->pci_dev;
 980
 981         hw->device_id = pci_dev->id.device_id;
 982         hw->vendor_id = pci_dev->id.vendor_id;
 983         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 984
 985         /* initialize the vfta */
 986         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 987
 988         /* initialize the hw strip bitmap*/
 989         memset(hwstrip, 0, sizeof(*hwstrip));
 990
 991         /* Initialize the shared code (base driver) */
 992         diag = ixgbe_init_shared_code(hw);
 993         if (diag != IXGBE_SUCCESS) {
 994                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 995                 return -EIO;
 996         }
 997
 998         /* init_mailbox_params */
 999         hw->mbx.ops.init_params(hw);
1000
1001         /* Disable the interrupts for VF */
1002         ixgbevf_intr_disable(hw);
1003
1004         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1005         diag = hw->mac.ops.reset_hw(hw);
1006
1007         /*
1008          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1009          * the underlying PF driver has not assigned a MAC address to the VF.
1010          * In this case, assign a random MAC address.
1011          */
1012         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1013                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1014                 return (diag);
1015         }
1016
1017         /* negotiate mailbox API version to use with the PF. */
1018         ixgbevf_negotiate_api(hw);
1019
1020         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1021         ixgbevf_get_queues(hw, &tcs, &tc);
1022
1023         /* Allocate memory for storing MAC addresses */
1024         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1025                         hw->mac.num_rar_entries, 0);
1026         if (eth_dev->data->mac_addrs == NULL) {
1027                 PMD_INIT_LOG(ERR,
1028                         "Failed to allocate %u bytes needed to store "
1029                         "MAC addresses",
1030                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1031                 return -ENOMEM;
1032         }
1033
1034         /* Generate a random MAC address, if none was assigned by PF. */
1035         if (is_zero_ether_addr(perm_addr)) {
1036                 generate_random_mac_addr(perm_addr);
1037                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1038                 if (diag) {
1039                         rte_free(eth_dev->data->mac_addrs);
1040                         eth_dev->data->mac_addrs = NULL;
1041                         return diag;
1042                 }
1043                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1044                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1045                              "%02x:%02x:%02x:%02x:%02x:%02x",
1046                              perm_addr->addr_bytes[0],
1047                              perm_addr->addr_bytes[1],
1048                              perm_addr->addr_bytes[2],
1049                              perm_addr->addr_bytes[3],
1050                              perm_addr->addr_bytes[4],
1051                              perm_addr->addr_bytes[5]);
1052         }
1053
1054         /* Copy the permanent MAC address */
1055         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1056
1057         /* reset the hardware with the new settings */
1058         diag = hw->mac.ops.start_hw(hw);
1059         switch (diag) {
1060                 case  0:
1061                         break;
1062
1063                 default:
1064                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1065                         return (-EIO);
1066         }
1067
1068         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1069                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1070                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1071
1072         return 0;
1073 }
1074
1075 static struct eth_driver rte_ixgbe_pmd = {
1076         {
1077                 .name = "rte_ixgbe_pmd",
1078                 .id_table = pci_id_ixgbe_map,
1079                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1080         },
1081         .eth_dev_init = eth_ixgbe_dev_init,
1082         .dev_private_size = sizeof(struct ixgbe_adapter),
1083 };
1084
1085 /*
1086  * virtual function driver struct
1087  */
1088 static struct eth_driver rte_ixgbevf_pmd = {
1089         {
1090                 .name = "rte_ixgbevf_pmd",
1091                 .id_table = pci_id_ixgbevf_map,
1092                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1093         },
1094         .eth_dev_init = eth_ixgbevf_dev_init,
1095         .dev_private_size = sizeof(struct ixgbe_adapter),
1096 };
1097
1098 /*
1099  * Driver initialization routine.
1100  * Invoked once at EAL init time.
1101  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1102  */
1103 static int
1104 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1105 {
1106         PMD_INIT_FUNC_TRACE();
1107
1108         rte_eth_driver_register(&rte_ixgbe_pmd);
1109         return 0;
1110 }
1111
1112 /*
1113  * VF Driver initialization routine.
1114  * Invoked one at EAL init time.
1115  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1116  */
1117 static int
1118 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1119 {
1120         PMD_INIT_FUNC_TRACE();
1121
1122         rte_eth_driver_register(&rte_ixgbevf_pmd);
1123         return (0);
1124 }
1125
1126 static int
1127 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1128 {
1129         struct ixgbe_hw *hw =
1130                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1131         struct ixgbe_vfta * shadow_vfta =
1132                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1133         uint32_t vfta;
1134         uint32_t vid_idx;
1135         uint32_t vid_bit;
1136
1137         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1138         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1139         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1140         if (on)
1141                 vfta |= vid_bit;
1142         else
1143                 vfta &= ~vid_bit;
1144         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1145
1146         /* update local VFTA copy */
1147         shadow_vfta->vfta[vid_idx] = vfta;
1148
1149         return 0;
1150 }
1151
1152 static void
1153 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1154 {
1155         if (on)
1156                 ixgbe_vlan_hw_strip_enable(dev, queue);
1157         else
1158                 ixgbe_vlan_hw_strip_disable(dev, queue);
1159 }
1160
1161 static void
1162 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1163 {
1164         struct ixgbe_hw *hw =
1165                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1166
1167         /* Only the high 16-bits is valid */
1168         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1169 }
1170
1171 void
1172 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1173 {
1174         struct ixgbe_hw *hw =
1175                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1176         uint32_t vlnctrl;
1177
1178         PMD_INIT_FUNC_TRACE();
1179
1180         /* Filter Table Disable */
1181         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1182         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1183
1184         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1185 }
1186
1187 void
1188 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1189 {
1190         struct ixgbe_hw *hw =
1191                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1192         struct ixgbe_vfta * shadow_vfta =
1193                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1194         uint32_t vlnctrl;
1195         uint16_t i;
1196
1197         PMD_INIT_FUNC_TRACE();
1198
1199         /* Filter Table Enable */
1200         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1201         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1202         vlnctrl |= IXGBE_VLNCTRL_VFE;
1203
1204         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1205
1206         /* write whatever is in local vfta copy */
1207         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1208                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1209 }
1210
1211 static void
1212 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1213 {
1214         struct ixgbe_hwstrip *hwstrip =
1215                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1216
1217         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1218                 return;
1219
1220         if (on)
1221                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1222         else
1223                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1224 }
1225
1226 static void
1227 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1228 {
1229         struct ixgbe_hw *hw =
1230                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231         uint32_t ctrl;
1232
1233         PMD_INIT_FUNC_TRACE();
1234
1235         if (hw->mac.type == ixgbe_mac_82598EB) {
1236                 /* No queue level support */
1237                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1238                 return;
1239         }
1240         else {
1241                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1242                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1243                 ctrl &= ~IXGBE_RXDCTL_VME;
1244                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1245         }
1246         /* record those setting for HW strip per queue */
1247         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1248 }
1249
1250 static void
1251 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1252 {
1253         struct ixgbe_hw *hw =
1254                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1255         uint32_t ctrl;
1256
1257         PMD_INIT_FUNC_TRACE();
1258
1259         if (hw->mac.type == ixgbe_mac_82598EB) {
1260                 /* No queue level supported */
1261                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1262                 return;
1263         }
1264         else {
1265                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1266                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1267                 ctrl |= IXGBE_RXDCTL_VME;
1268                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1269         }
1270         /* record those setting for HW strip per queue */
1271         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1272 }
1273
1274 void
1275 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1276 {
1277         struct ixgbe_hw *hw =
1278                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1279         uint32_t ctrl;
1280         uint16_t i;
1281
1282         PMD_INIT_FUNC_TRACE();
1283
1284         if (hw->mac.type == ixgbe_mac_82598EB) {
1285                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1286                 ctrl &= ~IXGBE_VLNCTRL_VME;
1287                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1288         }
1289         else {
1290                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1291                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1292                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1293                         ctrl &= ~IXGBE_RXDCTL_VME;
1294                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1295
1296                         /* record those setting for HW strip per queue */
1297                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1298                 }
1299         }
1300 }
1301
1302 void
1303 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1304 {
1305         struct ixgbe_hw *hw =
1306                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307         uint32_t ctrl;
1308         uint16_t i;
1309
1310         PMD_INIT_FUNC_TRACE();
1311
1312         if (hw->mac.type == ixgbe_mac_82598EB) {
1313                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1314                 ctrl |= IXGBE_VLNCTRL_VME;
1315                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1316         }
1317         else {
1318                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1319                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1320                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1321                         ctrl |= IXGBE_RXDCTL_VME;
1322                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1323
1324                         /* record those setting for HW strip per queue */
1325                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1326                 }
1327         }
1328 }
1329
1330 static void
1331 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1332 {
1333         struct ixgbe_hw *hw =
1334                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1335         uint32_t ctrl;
1336
1337         PMD_INIT_FUNC_TRACE();
1338
1339         /* DMATXCTRL: Geric Double VLAN Disable */
1340         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1341         ctrl &= ~IXGBE_DMATXCTL_GDV;
1342         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1343
1344         /* CTRL_EXT: Global Double VLAN Disable */
1345         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1346         ctrl &= ~IXGBE_EXTENDED_VLAN;
1347         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1348
1349 }
1350
1351 static void
1352 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1353 {
1354         struct ixgbe_hw *hw =
1355                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1356         uint32_t ctrl;
1357
1358         PMD_INIT_FUNC_TRACE();
1359
1360         /* DMATXCTRL: Geric Double VLAN Enable */
1361         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1362         ctrl |= IXGBE_DMATXCTL_GDV;
1363         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1364
1365         /* CTRL_EXT: Global Double VLAN Enable */
1366         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1367         ctrl |= IXGBE_EXTENDED_VLAN;
1368         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1369
1370         /*
1371          * VET EXT field in the EXVET register = 0x8100 by default
1372          * So no need to change. Same to VT field of DMATXCTL register
1373          */
1374 }
1375
1376 static void
1377 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1378 {
1379         if(mask & ETH_VLAN_STRIP_MASK){
1380                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1381                         ixgbe_vlan_hw_strip_enable_all(dev);
1382                 else
1383                         ixgbe_vlan_hw_strip_disable_all(dev);
1384         }
1385
1386         if(mask & ETH_VLAN_FILTER_MASK){
1387                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1388                         ixgbe_vlan_hw_filter_enable(dev);
1389                 else
1390                         ixgbe_vlan_hw_filter_disable(dev);
1391         }
1392
1393         if(mask & ETH_VLAN_EXTEND_MASK){
1394                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1395                         ixgbe_vlan_hw_extend_enable(dev);
1396                 else
1397                         ixgbe_vlan_hw_extend_disable(dev);
1398         }
1399 }
1400
1401 static void
1402 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1403 {
1404         struct ixgbe_hw *hw =
1405                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1406         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1407         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1408         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1409         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1410 }
1411
1412 static int
1413 ixgbe_dev_configure(struct rte_eth_dev *dev)
1414 {
1415         struct ixgbe_interrupt *intr =
1416                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1417
1418         PMD_INIT_FUNC_TRACE();
1419
1420         /* set flag to update link status after init */
1421         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1422
1423         return 0;
1424 }
1425
1426 /*
1427  * Configure device link speed and setup link.
1428  * It returns 0 on success.
1429  */
1430 static int
1431 ixgbe_dev_start(struct rte_eth_dev *dev)
1432 {
1433         struct ixgbe_hw *hw =
1434                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1435         struct ixgbe_vf_info *vfinfo =
1436                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1437         int err, link_up = 0, negotiate = 0;
1438         uint32_t speed = 0;
1439         int mask = 0;
1440         int status;
1441         uint16_t vf, idx;
1442
1443         PMD_INIT_FUNC_TRACE();
1444
1445         /* IXGBE devices don't support half duplex */
1446         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1447                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1448                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1449                              dev->data->dev_conf.link_duplex,
1450                              dev->data->port_id);
1451                 return -EINVAL;
1452         }
1453
1454         /* stop adapter */
1455         hw->adapter_stopped = FALSE;
1456         ixgbe_stop_adapter(hw);
1457
1458         /* reinitialize adapter
1459          * this calls reset and start */
1460         status = ixgbe_pf_reset_hw(hw);
1461         if (status != 0)
1462                 return -1;
1463         hw->mac.ops.start_hw(hw);
1464
1465         /* configure PF module if SRIOV enabled */
1466         ixgbe_pf_host_configure(dev);
1467
1468         /* initialize transmission unit */
1469         ixgbe_dev_tx_init(dev);
1470
1471         /* This can fail when allocating mbufs for descriptor rings */
1472         err = ixgbe_dev_rx_init(dev);
1473         if (err) {
1474                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1475                 goto error;
1476         }
1477
1478         ixgbe_dev_rxtx_start(dev);
1479
1480         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1481                 err = hw->mac.ops.setup_sfp(hw);
1482                 if (err)
1483                         goto error;
1484         }
1485
1486         /* Turn on the laser */
1487         ixgbe_enable_tx_laser(hw);
1488
1489         /* Skip link setup if loopback mode is enabled for 82599. */
1490         if (hw->mac.type == ixgbe_mac_82599EB &&
1491                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1492                 goto skip_link_setup;
1493
1494         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1495         if (err)
1496                 goto error;
1497         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1498         if (err)
1499                 goto error;
1500
1501         switch(dev->data->dev_conf.link_speed) {
1502         case ETH_LINK_SPEED_AUTONEG:
1503                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1504                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1505                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1506                 break;
1507         case ETH_LINK_SPEED_100:
1508                 /*
1509                  * Invalid for 82598 but error will be detected by
1510                  * ixgbe_setup_link()
1511                  */
1512                 speed = IXGBE_LINK_SPEED_100_FULL;
1513                 break;
1514         case ETH_LINK_SPEED_1000:
1515                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1516                 break;
1517         case ETH_LINK_SPEED_10000:
1518                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1519                 break;
1520         default:
1521                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1522                              dev->data->dev_conf.link_speed,
1523                              dev->data->port_id);
1524                 goto error;
1525         }
1526
1527         err = ixgbe_setup_link(hw, speed, link_up);
1528         if (err)
1529                 goto error;
1530
1531 skip_link_setup:
1532
1533         /* check if lsc interrupt is enabled */
1534         if (dev->data->dev_conf.intr_conf.lsc != 0)
1535                 ixgbe_dev_lsc_interrupt_setup(dev);
1536
1537         /* resume enabled intr since hw reset */
1538         ixgbe_enable_intr(dev);
1539
1540         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1541                 ETH_VLAN_EXTEND_MASK;
1542         ixgbe_vlan_offload_set(dev, mask);
1543
1544         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1545                 /* Enable vlan filtering for VMDq */
1546                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1547         }
1548
1549         /* Configure DCB hw */
1550         ixgbe_configure_dcb(dev);
1551
1552         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1553                 err = ixgbe_fdir_configure(dev);
1554                 if (err)
1555                         goto error;
1556         }
1557
1558         /* Restore vf rate limit */
1559         if (vfinfo != NULL) {
1560                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1561                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1562                                 if (vfinfo[vf].tx_rate[idx] != 0)
1563                                         ixgbe_set_vf_rate_limit(dev, vf,
1564                                                 vfinfo[vf].tx_rate[idx],
1565                                                 1 << idx);
1566         }
1567
1568         ixgbe_restore_statistics_mapping(dev);
1569
1570         return (0);
1571
1572 error:
1573         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1574         ixgbe_dev_clear_queues(dev);
1575         return -EIO;
1576 }
1577
1578 /*
1579  * Stop device: disable rx and tx functions to allow for reconfiguring.
1580  */
1581 static void
1582 ixgbe_dev_stop(struct rte_eth_dev *dev)
1583 {
1584         struct rte_eth_link link;
1585         struct ixgbe_hw *hw =
1586                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587         struct ixgbe_vf_info *vfinfo =
1588                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1589         int vf;
1590
1591         PMD_INIT_FUNC_TRACE();
1592
1593         /* disable interrupts */
1594         ixgbe_disable_intr(hw);
1595
1596         /* reset the NIC */
1597         ixgbe_pf_reset_hw(hw);
1598         hw->adapter_stopped = FALSE;
1599
1600         /* stop adapter */
1601         ixgbe_stop_adapter(hw);
1602
1603         for (vf = 0; vfinfo != NULL &&
1604                      vf < dev->pci_dev->max_vfs; vf++)
1605                 vfinfo[vf].clear_to_send = false;
1606
1607         /* Turn off the laser */
1608         ixgbe_disable_tx_laser(hw);
1609
1610         ixgbe_dev_clear_queues(dev);
1611
1612         /* Clear stored conf */
1613         dev->data->scattered_rx = 0;
1614
1615         /* Clear recorded link status */
1616         memset(&link, 0, sizeof(link));
1617         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1618 }
1619
1620 /*
1621  * Set device link up: enable tx laser.
1622  */
1623 static int
1624 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1625 {
1626         struct ixgbe_hw *hw =
1627                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628         if (hw->mac.type == ixgbe_mac_82599EB) {
1629 #ifdef RTE_NIC_BYPASS
1630                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1631                         /* Not suported in bypass mode */
1632                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1633                                      "by device id 0x%x", hw->device_id);
1634                         return -ENOTSUP;
1635                 }
1636 #endif
1637                 /* Turn on the laser */
1638                 ixgbe_enable_tx_laser(hw);
1639                 return 0;
1640         }
1641
1642         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1643                      hw->device_id);
1644         return -ENOTSUP;
1645 }
1646
1647 /*
1648  * Set device link down: disable tx laser.
1649  */
1650 static int
1651 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1652 {
1653         struct ixgbe_hw *hw =
1654                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655         if (hw->mac.type == ixgbe_mac_82599EB) {
1656 #ifdef RTE_NIC_BYPASS
1657                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1658                         /* Not suported in bypass mode */
1659                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1660                                      "by device id 0x%x", hw->device_id);
1661                         return -ENOTSUP;
1662                 }
1663 #endif
1664                 /* Turn off the laser */
1665                 ixgbe_disable_tx_laser(hw);
1666                 return 0;
1667         }
1668
1669         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1670                      hw->device_id);
1671         return -ENOTSUP;
1672 }
1673
1674 /*
1675  * Reest and stop device.
1676  */
1677 static void
1678 ixgbe_dev_close(struct rte_eth_dev *dev)
1679 {
1680         struct ixgbe_hw *hw =
1681                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1682
1683         PMD_INIT_FUNC_TRACE();
1684
1685         ixgbe_pf_reset_hw(hw);
1686
1687         ixgbe_dev_stop(dev);
1688         hw->adapter_stopped = 1;
1689
1690         ixgbe_disable_pcie_master(hw);
1691
1692         /* reprogram the RAR[0] in case user changed it. */
1693         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1694 }
1695
1696 /*
1697  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1698  */
1699 static void
1700 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1701 {
1702         struct ixgbe_hw *hw =
1703                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1704         struct ixgbe_hw_stats *hw_stats =
1705                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1706         uint32_t bprc, lxon, lxoff, total;
1707         uint64_t total_missed_rx, total_qbrc, total_qprc;
1708         unsigned i;
1709
1710         total_missed_rx = 0;
1711         total_qbrc = 0;
1712         total_qprc = 0;
1713
1714         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1715         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1716         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1717         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1718
1719         for (i = 0; i < 8; i++) {
1720                 uint32_t mp;
1721                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1722                 /* global total per queue */
1723                 hw_stats->mpc[i] += mp;
1724                 /* Running comprehensive total for stats display */
1725                 total_missed_rx += hw_stats->mpc[i];
1726                 if (hw->mac.type == ixgbe_mac_82598EB)
1727                         hw_stats->rnbc[i] +=
1728                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1729                 hw_stats->pxontxc[i] +=
1730                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1731                 hw_stats->pxonrxc[i] +=
1732                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1733                 hw_stats->pxofftxc[i] +=
1734                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1735                 hw_stats->pxoffrxc[i] +=
1736                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1737                 hw_stats->pxon2offc[i] +=
1738                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1739         }
1740         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1741                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1742                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1743                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1744                 hw_stats->qbrc[i] +=
1745                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1746                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1747                 hw_stats->qbtc[i] +=
1748                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1749                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1750
1751                 total_qprc += hw_stats->qprc[i];
1752                 total_qbrc += hw_stats->qbrc[i];
1753         }
1754         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1755         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1756         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1757
1758         /* Note that gprc counts missed packets */
1759         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1760
1761         if (hw->mac.type != ixgbe_mac_82598EB) {
1762                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1763                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1764                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1765                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1766                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1767                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1768                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1769                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1770         } else {
1771                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1772                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1773                 /* 82598 only has a counter in the high register */
1774                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1775                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1776                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1777         }
1778
1779         /*
1780          * Workaround: mprc hardware is incorrectly counting
1781          * broadcasts, so for now we subtract those.
1782          */
1783         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1784         hw_stats->bprc += bprc;
1785         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1786         if (hw->mac.type == ixgbe_mac_82598EB)
1787                 hw_stats->mprc -= bprc;
1788
1789         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1790         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1791         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1792         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1793         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1794         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1795
1796         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1797         hw_stats->lxontxc += lxon;
1798         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1799         hw_stats->lxofftxc += lxoff;
1800         total = lxon + lxoff;
1801
1802         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1803         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1804         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1805         hw_stats->gptc -= total;
1806         hw_stats->mptc -= total;
1807         hw_stats->ptc64 -= total;
1808         hw_stats->gotc -= total * ETHER_MIN_LEN;
1809
1810         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1811         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1812         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1813         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1814         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1815         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1816         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1817         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1818         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1819         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1820         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1821         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1822         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1823         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1824         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1825         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1826         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1827         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1828         /* Only read FCOE on 82599 */
1829         if (hw->mac.type != ixgbe_mac_82598EB) {
1830                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1831                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1832                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1833                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1834                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1835         }
1836
1837         if (stats == NULL)
1838                 return;
1839
1840         /* Fill out the rte_eth_stats statistics structure */
1841         stats->ipackets = total_qprc;
1842         stats->ibytes = total_qbrc;
1843         stats->opackets = hw_stats->gptc;
1844         stats->obytes = hw_stats->gotc;
1845         stats->imcasts = hw_stats->mprc;
1846
1847         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1848                 stats->q_ipackets[i] = hw_stats->qprc[i];
1849                 stats->q_opackets[i] = hw_stats->qptc[i];
1850                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1851                 stats->q_obytes[i] = hw_stats->qbtc[i];
1852                 stats->q_errors[i] = hw_stats->qprdc[i];
1853         }
1854
1855         /* Rx Errors */
1856         stats->ibadcrc  = hw_stats->crcerrs;
1857         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1858         stats->imissed  = total_missed_rx;
1859         stats->ierrors  = stats->ibadcrc +
1860                           stats->ibadlen +
1861                           stats->imissed +
1862                           hw_stats->illerrc + hw_stats->errbc;
1863
1864         /* Tx Errors */
1865         stats->oerrors  = 0;
1866
1867         /* XON/XOFF pause frames */
1868         stats->tx_pause_xon  = hw_stats->lxontxc;
1869         stats->rx_pause_xon  = hw_stats->lxonrxc;
1870         stats->tx_pause_xoff = hw_stats->lxofftxc;
1871         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1872
1873         /* Flow Director Stats registers */
1874         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1875         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1876         stats->fdirmatch = hw_stats->fdirmatch;
1877         stats->fdirmiss = hw_stats->fdirmiss;
1878 }
1879
1880 static void
1881 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1882 {
1883         struct ixgbe_hw_stats *stats =
1884                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1885
1886         /* HW registers are cleared on read */
1887         ixgbe_dev_stats_get(dev, NULL);
1888
1889         /* Reset software totals */
1890         memset(stats, 0, sizeof(*stats));
1891 }
1892
1893 static void
1894 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1895 {
1896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1897         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1898                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1899
1900         /* Good Rx packet, include VF loopback */
1901         UPDATE_VF_STAT(IXGBE_VFGPRC,
1902             hw_stats->last_vfgprc, hw_stats->vfgprc);
1903
1904         /* Good Rx octets, include VF loopback */
1905         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1906             hw_stats->last_vfgorc, hw_stats->vfgorc);
1907
1908         /* Good Tx packet, include VF loopback */
1909         UPDATE_VF_STAT(IXGBE_VFGPTC,
1910             hw_stats->last_vfgptc, hw_stats->vfgptc);
1911
1912         /* Good Tx octets, include VF loopback */
1913         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1914             hw_stats->last_vfgotc, hw_stats->vfgotc);
1915
1916         /* Rx Multicst Packet */
1917         UPDATE_VF_STAT(IXGBE_VFMPRC,
1918             hw_stats->last_vfmprc, hw_stats->vfmprc);
1919
1920         if (stats == NULL)
1921                 return;
1922
1923         memset(stats, 0, sizeof(*stats));
1924         stats->ipackets = hw_stats->vfgprc;
1925         stats->ibytes = hw_stats->vfgorc;
1926         stats->opackets = hw_stats->vfgptc;
1927         stats->obytes = hw_stats->vfgotc;
1928         stats->imcasts = hw_stats->vfmprc;
1929 }
1930
1931 static void
1932 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1933 {
1934         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1935                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1936
1937         /* Sync HW register to the last stats */
1938         ixgbevf_dev_stats_get(dev, NULL);
1939
1940         /* reset HW current stats*/
1941         hw_stats->vfgprc = 0;
1942         hw_stats->vfgorc = 0;
1943         hw_stats->vfgptc = 0;
1944         hw_stats->vfgotc = 0;
1945         hw_stats->vfmprc = 0;
1946
1947 }
1948
1949 static void
1950 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1951 {
1952         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953
1954         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1955         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1956         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1957         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1958         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1959         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1960         dev_info->max_vfs = dev->pci_dev->max_vfs;
1961         if (hw->mac.type == ixgbe_mac_82598EB)
1962                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1963         else
1964                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1965         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
1966         dev_info->rx_offload_capa =
1967                 DEV_RX_OFFLOAD_VLAN_STRIP |
1968                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1969                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1970                 DEV_RX_OFFLOAD_TCP_CKSUM;
1971         dev_info->tx_offload_capa =
1972                 DEV_TX_OFFLOAD_VLAN_INSERT |
1973                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1974                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1975                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1976                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1977                 DEV_TX_OFFLOAD_TCP_TSO;
1978
1979         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1980                 .rx_thresh = {
1981                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
1982                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
1983                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
1984                 },
1985                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
1986                 .rx_drop_en = 0,
1987         };
1988
1989         dev_info->default_txconf = (struct rte_eth_txconf) {
1990                 .tx_thresh = {
1991                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
1992                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
1993                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
1994                 },
1995                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
1996                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
1997                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1998                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1999         };
2000         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2001 }
2002
2003 static void
2004 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2005                      struct rte_eth_dev_info *dev_info)
2006 {
2007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2008
2009         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2010         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2011         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2012         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2013         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2014         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2015         dev_info->max_vfs = dev->pci_dev->max_vfs;
2016         if (hw->mac.type == ixgbe_mac_82598EB)
2017                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2018         else
2019                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2020         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2021                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2022                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2023                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2024         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2025                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2026                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2027                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2028                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2029
2030         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2031                 .rx_thresh = {
2032                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2033                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2034                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2035                 },
2036                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2037                 .rx_drop_en = 0,
2038         };
2039
2040         dev_info->default_txconf = (struct rte_eth_txconf) {
2041                 .tx_thresh = {
2042                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2043                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2044                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2045                 },
2046                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2047                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2048                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2049                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2050         };
2051 }
2052
2053 /* return 0 means link status changed, -1 means not changed */
2054 static int
2055 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2056 {
2057         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2058         struct rte_eth_link link, old;
2059         ixgbe_link_speed link_speed;
2060         int link_up;
2061         int diag;
2062
2063         link.link_status = 0;
2064         link.link_speed = 0;
2065         link.link_duplex = 0;
2066         memset(&old, 0, sizeof(old));
2067         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2068
2069         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2070         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2071                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2072         else
2073                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2074         if (diag != 0) {
2075                 link.link_speed = ETH_LINK_SPEED_100;
2076                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2077                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2078                 if (link.link_status == old.link_status)
2079                         return -1;
2080                 return 0;
2081         }
2082
2083         if (link_up == 0) {
2084                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2085                 if (link.link_status == old.link_status)
2086                         return -1;
2087                 return 0;
2088         }
2089         link.link_status = 1;
2090         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2091
2092         switch (link_speed) {
2093         default:
2094         case IXGBE_LINK_SPEED_UNKNOWN:
2095                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2096                 link.link_speed = ETH_LINK_SPEED_100;
2097                 break;
2098
2099         case IXGBE_LINK_SPEED_100_FULL:
2100                 link.link_speed = ETH_LINK_SPEED_100;
2101                 break;
2102
2103         case IXGBE_LINK_SPEED_1GB_FULL:
2104                 link.link_speed = ETH_LINK_SPEED_1000;
2105                 break;
2106
2107         case IXGBE_LINK_SPEED_10GB_FULL:
2108                 link.link_speed = ETH_LINK_SPEED_10000;
2109                 break;
2110         }
2111         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2112
2113         if (link.link_status == old.link_status)
2114                 return -1;
2115
2116         return 0;
2117 }
2118
2119 static void
2120 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2121 {
2122         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2123         uint32_t fctrl;
2124
2125         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2126         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2127         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2128 }
2129
2130 static void
2131 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2132 {
2133         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         uint32_t fctrl;
2135
2136         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2137         fctrl &= (~IXGBE_FCTRL_UPE);
2138         if (dev->data->all_multicast == 1)
2139                 fctrl |= IXGBE_FCTRL_MPE;
2140         else
2141                 fctrl &= (~IXGBE_FCTRL_MPE);
2142         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2143 }
2144
2145 static void
2146 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2147 {
2148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149         uint32_t fctrl;
2150
2151         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2152         fctrl |= IXGBE_FCTRL_MPE;
2153         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2154 }
2155
2156 static void
2157 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2158 {
2159         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2160         uint32_t fctrl;
2161
2162         if (dev->data->promiscuous == 1)
2163                 return; /* must remain in all_multicast mode */
2164
2165         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2166         fctrl &= (~IXGBE_FCTRL_MPE);
2167         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2168 }
2169
2170 /**
2171  * It clears the interrupt causes and enables the interrupt.
2172  * It will be called once only during nic initialized.
2173  *
2174  * @param dev
2175  *  Pointer to struct rte_eth_dev.
2176  *
2177  * @return
2178  *  - On success, zero.
2179  *  - On failure, a negative value.
2180  */
2181 static int
2182 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2183 {
2184         struct ixgbe_interrupt *intr =
2185                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2186
2187         ixgbe_dev_link_status_print(dev);
2188         intr->mask |= IXGBE_EICR_LSC;
2189
2190         return 0;
2191 }
2192
2193 /*
2194  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2195  *
2196  * @param dev
2197  *  Pointer to struct rte_eth_dev.
2198  *
2199  * @return
2200  *  - On success, zero.
2201  *  - On failure, a negative value.
2202  */
2203 static int
2204 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2205 {
2206         uint32_t eicr;
2207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2208         struct ixgbe_interrupt *intr =
2209                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2210
2211         /* clear all cause mask */
2212         ixgbe_disable_intr(hw);
2213
2214         /* read-on-clear nic registers here */
2215         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2216         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2217
2218         intr->flags = 0;
2219         if (eicr & IXGBE_EICR_LSC) {
2220                 /* set flag for async link update */
2221                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2222         }
2223
2224         if (eicr & IXGBE_EICR_MAILBOX)
2225                 intr->flags |= IXGBE_FLAG_MAILBOX;
2226
2227         return 0;
2228 }
2229
2230 /**
2231  * It gets and then prints the link status.
2232  *
2233  * @param dev
2234  *  Pointer to struct rte_eth_dev.
2235  *
2236  * @return
2237  *  - On success, zero.
2238  *  - On failure, a negative value.
2239  */
2240 static void
2241 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2242 {
2243         struct rte_eth_link link;
2244
2245         memset(&link, 0, sizeof(link));
2246         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2247         if (link.link_status) {
2248                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2249                                         (int)(dev->data->port_id),
2250                                         (unsigned)link.link_speed,
2251                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2252                                         "full-duplex" : "half-duplex");
2253         } else {
2254                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2255                                 (int)(dev->data->port_id));
2256         }
2257         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2258                                 dev->pci_dev->addr.domain,
2259                                 dev->pci_dev->addr.bus,
2260                                 dev->pci_dev->addr.devid,
2261                                 dev->pci_dev->addr.function);
2262 }
2263
2264 /*
2265  * It executes link_update after knowing an interrupt occurred.
2266  *
2267  * @param dev
2268  *  Pointer to struct rte_eth_dev.
2269  *
2270  * @return
2271  *  - On success, zero.
2272  *  - On failure, a negative value.
2273  */
2274 static int
2275 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2276 {
2277         struct ixgbe_interrupt *intr =
2278                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2279         int64_t timeout;
2280         struct rte_eth_link link;
2281         int intr_enable_delay = false;
2282
2283         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2284
2285         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2286                 ixgbe_pf_mbx_process(dev);
2287                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2288         }
2289
2290         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2291                 /* get the link status before link update, for predicting later */
2292                 memset(&link, 0, sizeof(link));
2293                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2294
2295                 ixgbe_dev_link_update(dev, 0);
2296
2297                 /* likely to up */
2298                 if (!link.link_status)
2299                         /* handle it 1 sec later, wait it being stable */
2300                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2301                 /* likely to down */
2302                 else
2303                         /* handle it 4 sec later, wait it being stable */
2304                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2305
2306                 ixgbe_dev_link_status_print(dev);
2307
2308                 intr_enable_delay = true;
2309         }
2310
2311         if (intr_enable_delay) {
2312                 if (rte_eal_alarm_set(timeout * 1000,
2313                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2314                         PMD_DRV_LOG(ERR, "Error setting alarm");
2315         } else {
2316                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2317                 ixgbe_enable_intr(dev);
2318                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2319         }
2320
2321
2322         return 0;
2323 }
2324
2325 /**
2326  * Interrupt handler which shall be registered for alarm callback for delayed
2327  * handling specific interrupt to wait for the stable nic state. As the
2328  * NIC interrupt state is not stable for ixgbe after link is just down,
2329  * it needs to wait 4 seconds to get the stable status.
2330  *
2331  * @param handle
2332  *  Pointer to interrupt handle.
2333  * @param param
2334  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2335  *
2336  * @return
2337  *  void
2338  */
2339 static void
2340 ixgbe_dev_interrupt_delayed_handler(void *param)
2341 {
2342         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2343         struct ixgbe_interrupt *intr =
2344                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2345         struct ixgbe_hw *hw =
2346                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347         uint32_t eicr;
2348
2349         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2350         if (eicr & IXGBE_EICR_MAILBOX)
2351                 ixgbe_pf_mbx_process(dev);
2352
2353         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2354                 ixgbe_dev_link_update(dev, 0);
2355                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2356                 ixgbe_dev_link_status_print(dev);
2357                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2358         }
2359
2360         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2361         ixgbe_enable_intr(dev);
2362         rte_intr_enable(&(dev->pci_dev->intr_handle));
2363 }
2364
2365 /**
2366  * Interrupt handler triggered by NIC  for handling
2367  * specific interrupt.
2368  *
2369  * @param handle
2370  *  Pointer to interrupt handle.
2371  * @param param
2372  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2373  *
2374  * @return
2375  *  void
2376  */
2377 static void
2378 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2379                                                         void *param)
2380 {
2381         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2382         ixgbe_dev_interrupt_get_status(dev);
2383         ixgbe_dev_interrupt_action(dev);
2384 }
2385
2386 static int
2387 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2388 {
2389         struct ixgbe_hw *hw;
2390
2391         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2393 }
2394
2395 static int
2396 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2397 {
2398         struct ixgbe_hw *hw;
2399
2400         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2401         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2402 }
2403
2404 static int
2405 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2406 {
2407         struct ixgbe_hw *hw;
2408         uint32_t mflcn_reg;
2409         uint32_t fccfg_reg;
2410         int rx_pause;
2411         int tx_pause;
2412
2413         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414
2415         fc_conf->pause_time = hw->fc.pause_time;
2416         fc_conf->high_water = hw->fc.high_water[0];
2417         fc_conf->low_water = hw->fc.low_water[0];
2418         fc_conf->send_xon = hw->fc.send_xon;
2419         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2420
2421         /*
2422          * Return rx_pause status according to actual setting of
2423          * MFLCN register.
2424          */
2425         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2426         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2427                 rx_pause = 1;
2428         else
2429                 rx_pause = 0;
2430
2431         /*
2432          * Return tx_pause status according to actual setting of
2433          * FCCFG register.
2434          */
2435         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2436         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2437                 tx_pause = 1;
2438         else
2439                 tx_pause = 0;
2440
2441         if (rx_pause && tx_pause)
2442                 fc_conf->mode = RTE_FC_FULL;
2443         else if (rx_pause)
2444                 fc_conf->mode = RTE_FC_RX_PAUSE;
2445         else if (tx_pause)
2446                 fc_conf->mode = RTE_FC_TX_PAUSE;
2447         else
2448                 fc_conf->mode = RTE_FC_NONE;
2449
2450         return 0;
2451 }
2452
2453 static int
2454 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2455 {
2456         struct ixgbe_hw *hw;
2457         int err;
2458         uint32_t rx_buf_size;
2459         uint32_t max_high_water;
2460         uint32_t mflcn;
2461         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2462                 ixgbe_fc_none,
2463                 ixgbe_fc_rx_pause,
2464                 ixgbe_fc_tx_pause,
2465                 ixgbe_fc_full
2466         };
2467
2468         PMD_INIT_FUNC_TRACE();
2469
2470         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2472                 return -ENOTSUP;
2473         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2474         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2475
2476         /*
2477          * At least reserve one Ethernet frame for watermark
2478          * high_water/low_water in kilo bytes for ixgbe
2479          */
2480         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2481         if ((fc_conf->high_water > max_high_water) ||
2482                 (fc_conf->high_water < fc_conf->low_water)) {
2483                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2484                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2485                 return (-EINVAL);
2486         }
2487
2488         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2489         hw->fc.pause_time     = fc_conf->pause_time;
2490         hw->fc.high_water[0]  = fc_conf->high_water;
2491         hw->fc.low_water[0]   = fc_conf->low_water;
2492         hw->fc.send_xon       = fc_conf->send_xon;
2493
2494         err = ixgbe_fc_enable(hw);
2495
2496         /* Not negotiated is not an error case */
2497         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2498
2499                 /* check if we want to forward MAC frames - driver doesn't have native
2500                  * capability to do that, so we'll write the registers ourselves */
2501
2502                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2503
2504                 /* set or clear MFLCN.PMCF bit depending on configuration */
2505                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2506                         mflcn |= IXGBE_MFLCN_PMCF;
2507                 else
2508                         mflcn &= ~IXGBE_MFLCN_PMCF;
2509
2510                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2511                 IXGBE_WRITE_FLUSH(hw);
2512
2513                 return 0;
2514         }
2515
2516         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2517         return -EIO;
2518 }
2519
2520 /**
2521  *  ixgbe_pfc_enable_generic - Enable flow control
2522  *  @hw: pointer to hardware structure
2523  *  @tc_num: traffic class number
2524  *  Enable flow control according to the current settings.
2525  */
2526 static int
2527 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2528 {
2529         int ret_val = 0;
2530         uint32_t mflcn_reg, fccfg_reg;
2531         uint32_t reg;
2532         uint32_t fcrtl, fcrth;
2533         uint8_t i;
2534         uint8_t nb_rx_en;
2535
2536         /* Validate the water mark configuration */
2537         if (!hw->fc.pause_time) {
2538                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2539                 goto out;
2540         }
2541
2542         /* Low water mark of zero causes XOFF floods */
2543         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2544                  /* High/Low water can not be 0 */
2545                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2546                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2547                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2548                         goto out;
2549                 }
2550
2551                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2552                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2553                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2554                         goto out;
2555                 }
2556         }
2557         /* Negotiate the fc mode to use */
2558         ixgbe_fc_autoneg(hw);
2559
2560         /* Disable any previous flow control settings */
2561         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2562         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2563
2564         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2565         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2566
2567         switch (hw->fc.current_mode) {
2568         case ixgbe_fc_none:
2569                 /*
2570                  * If the count of enabled RX Priority Flow control >1,
2571                  * and the TX pause can not be disabled
2572                  */
2573                 nb_rx_en = 0;
2574                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2575                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2576                         if (reg & IXGBE_FCRTH_FCEN)
2577                                 nb_rx_en++;
2578                 }
2579                 if (nb_rx_en > 1)
2580                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2581                 break;
2582         case ixgbe_fc_rx_pause:
2583                 /*
2584                  * Rx Flow control is enabled and Tx Flow control is
2585                  * disabled by software override. Since there really
2586                  * isn't a way to advertise that we are capable of RX
2587                  * Pause ONLY, we will advertise that we support both
2588                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2589                  * disable the adapter's ability to send PAUSE frames.
2590                  */
2591                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2592                 /*
2593                  * If the count of enabled RX Priority Flow control >1,
2594                  * and the TX pause can not be disabled
2595                  */
2596                 nb_rx_en = 0;
2597                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2598                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2599                         if (reg & IXGBE_FCRTH_FCEN)
2600                                 nb_rx_en++;
2601                 }
2602                 if (nb_rx_en > 1)
2603                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2604                 break;
2605         case ixgbe_fc_tx_pause:
2606                 /*
2607                  * Tx Flow control is enabled, and Rx Flow control is
2608                  * disabled by software override.
2609                  */
2610                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2611                 break;
2612         case ixgbe_fc_full:
2613                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2614                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2615                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2616                 break;
2617         default:
2618                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2619                 ret_val = IXGBE_ERR_CONFIG;
2620                 goto out;
2621                 break;
2622         }
2623
2624         /* Set 802.3x based flow control settings. */
2625         mflcn_reg |= IXGBE_MFLCN_DPF;
2626         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2627         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2628
2629         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2630         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2631                 hw->fc.high_water[tc_num]) {
2632                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2633                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2634                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2635         } else {
2636                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2637                 /*
2638                  * In order to prevent Tx hangs when the internal Tx
2639                  * switch is enabled we must set the high water mark
2640                  * to the maximum FCRTH value.  This allows the Tx
2641                  * switch to function even under heavy Rx workloads.
2642                  */
2643                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2644         }
2645         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2646
2647         /* Configure pause time (2 TCs per register) */
2648         reg = hw->fc.pause_time * 0x00010001;
2649         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2650                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2651
2652         /* Configure flow control refresh threshold value */
2653         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2654
2655 out:
2656         return ret_val;
2657 }
2658
2659 static int
2660 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2661 {
2662         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2663         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2664
2665         if(hw->mac.type != ixgbe_mac_82598EB) {
2666                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2667         }
2668         return ret_val;
2669 }
2670
2671 static int
2672 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2673 {
2674         int err;
2675         uint32_t rx_buf_size;
2676         uint32_t max_high_water;
2677         uint8_t tc_num;
2678         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2679         struct ixgbe_hw *hw =
2680                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681         struct ixgbe_dcb_config *dcb_config =
2682                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2683
2684         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2685                 ixgbe_fc_none,
2686                 ixgbe_fc_rx_pause,
2687                 ixgbe_fc_tx_pause,
2688                 ixgbe_fc_full
2689         };
2690
2691         PMD_INIT_FUNC_TRACE();
2692
2693         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2694         tc_num = map[pfc_conf->priority];
2695         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2696         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2697         /*
2698          * At least reserve one Ethernet frame for watermark
2699          * high_water/low_water in kilo bytes for ixgbe
2700          */
2701         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2702         if ((pfc_conf->fc.high_water > max_high_water) ||
2703             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2704                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2705                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2706                 return (-EINVAL);
2707         }
2708
2709         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2710         hw->fc.pause_time = pfc_conf->fc.pause_time;
2711         hw->fc.send_xon = pfc_conf->fc.send_xon;
2712         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2713         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2714
2715         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2716
2717         /* Not negotiated is not an error case */
2718         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2719                 return 0;
2720
2721         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2722         return -EIO;
2723 }
2724
2725 static int
2726 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2727                           struct rte_eth_rss_reta_entry64 *reta_conf,
2728                           uint16_t reta_size)
2729 {
2730         uint8_t i, j, mask;
2731         uint32_t reta, r;
2732         uint16_t idx, shift;
2733         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2734
2735         PMD_INIT_FUNC_TRACE();
2736         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2737                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2738                         "(%d) doesn't match the number hardware can supported "
2739                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2740                 return -EINVAL;
2741         }
2742
2743         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2744                 idx = i / RTE_RETA_GROUP_SIZE;
2745                 shift = i % RTE_RETA_GROUP_SIZE;
2746                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2747                                                 IXGBE_4_BIT_MASK);
2748                 if (!mask)
2749                         continue;
2750                 if (mask == IXGBE_4_BIT_MASK)
2751                         r = 0;
2752                 else
2753                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2754                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2755                         if (mask & (0x1 << j))
2756                                 reta |= reta_conf[idx].reta[shift + j] <<
2757                                                         (CHAR_BIT * j);
2758                         else
2759                                 reta |= r & (IXGBE_8_BIT_MASK <<
2760                                                 (CHAR_BIT * j));
2761                 }
2762                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2763         }
2764
2765         return 0;
2766 }
2767
2768 static int
2769 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2770                          struct rte_eth_rss_reta_entry64 *reta_conf,
2771                          uint16_t reta_size)
2772 {
2773         uint8_t i, j, mask;
2774         uint32_t reta;
2775         uint16_t idx, shift;
2776         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2777
2778         PMD_INIT_FUNC_TRACE();
2779         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2780                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2781                         "(%d) doesn't match the number hardware can supported "
2782                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2783                 return -EINVAL;
2784         }
2785
2786         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2787                 idx = i / RTE_RETA_GROUP_SIZE;
2788                 shift = i % RTE_RETA_GROUP_SIZE;
2789                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2790                                                 IXGBE_4_BIT_MASK);
2791                 if (!mask)
2792                         continue;
2793
2794                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2795                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2796                         if (mask & (0x1 << j))
2797                                 reta_conf[idx].reta[shift + j] =
2798                                         ((reta >> (CHAR_BIT * j)) &
2799                                                 IXGBE_8_BIT_MASK);
2800                 }
2801         }
2802
2803         return 0;
2804 }
2805
2806 static void
2807 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2808                                 uint32_t index, uint32_t pool)
2809 {
2810         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811         uint32_t enable_addr = 1;
2812
2813         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2814 }
2815
2816 static void
2817 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2818 {
2819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820
2821         ixgbe_clear_rar(hw, index);
2822 }
2823
2824 static int
2825 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2826 {
2827         uint32_t hlreg0;
2828         uint32_t maxfrs;
2829         struct ixgbe_hw *hw;
2830         struct rte_eth_dev_info dev_info;
2831         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2832
2833         ixgbe_dev_info_get(dev, &dev_info);
2834
2835         /* check that mtu is within the allowed range */
2836         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2837                 return -EINVAL;
2838
2839         /* refuse mtu that requires the support of scattered packets when this
2840          * feature has not been enabled before. */
2841         if (!dev->data->scattered_rx &&
2842             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2843              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2844                 return -EINVAL;
2845
2846         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2847         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2848
2849         /* switch to jumbo mode if needed */
2850         if (frame_size > ETHER_MAX_LEN) {
2851                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2852                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2853         } else {
2854                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2855                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2856         }
2857         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2858
2859         /* update max frame size */
2860         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2861
2862         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2863         maxfrs &= 0x0000FFFF;
2864         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2865         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2866
2867         return 0;
2868 }
2869
2870 /*
2871  * Virtual Function operations
2872  */
2873 static void
2874 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2875 {
2876         PMD_INIT_FUNC_TRACE();
2877
2878         /* Clear interrupt mask to stop from interrupts being generated */
2879         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2880
2881         IXGBE_WRITE_FLUSH(hw);
2882 }
2883
2884 static int
2885 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2886 {
2887         struct rte_eth_conf* conf = &dev->data->dev_conf;
2888
2889         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2890                      dev->data->port_id);
2891
2892         /*
2893          * VF has no ability to enable/disable HW CRC
2894          * Keep the persistent behavior the same as Host PF
2895          */
2896 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2897         if (!conf->rxmode.hw_strip_crc) {
2898                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2899                 conf->rxmode.hw_strip_crc = 1;
2900         }
2901 #else
2902         if (conf->rxmode.hw_strip_crc) {
2903                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2904                 conf->rxmode.hw_strip_crc = 0;
2905         }
2906 #endif
2907
2908         return 0;
2909 }
2910
2911 static int
2912 ixgbevf_dev_start(struct rte_eth_dev *dev)
2913 {
2914         struct ixgbe_hw *hw =
2915                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2916         int err, mask = 0;
2917
2918         PMD_INIT_FUNC_TRACE();
2919
2920         hw->mac.ops.reset_hw(hw);
2921
2922         /* negotiate mailbox API version to use with the PF. */
2923         ixgbevf_negotiate_api(hw);
2924
2925         ixgbevf_dev_tx_init(dev);
2926
2927         /* This can fail when allocating mbufs for descriptor rings */
2928         err = ixgbevf_dev_rx_init(dev);
2929         if (err) {
2930                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2931                 ixgbe_dev_clear_queues(dev);
2932                 return err;
2933         }
2934
2935         /* Set vfta */
2936         ixgbevf_set_vfta_all(dev,1);
2937
2938         /* Set HW strip */
2939         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2940                 ETH_VLAN_EXTEND_MASK;
2941         ixgbevf_vlan_offload_set(dev, mask);
2942
2943         ixgbevf_dev_rxtx_start(dev);
2944
2945         return 0;
2946 }
2947
2948 static void
2949 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2950 {
2951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952
2953         PMD_INIT_FUNC_TRACE();
2954
2955         hw->adapter_stopped = TRUE;
2956         ixgbe_stop_adapter(hw);
2957
2958         /*
2959           * Clear what we set, but we still keep shadow_vfta to
2960           * restore after device starts
2961           */
2962         ixgbevf_set_vfta_all(dev,0);
2963
2964         /* Clear stored conf */
2965         dev->data->scattered_rx = 0;
2966
2967         ixgbe_dev_clear_queues(dev);
2968 }
2969
2970 static void
2971 ixgbevf_dev_close(struct rte_eth_dev *dev)
2972 {
2973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974
2975         PMD_INIT_FUNC_TRACE();
2976
2977         ixgbe_reset_hw(hw);
2978
2979         ixgbevf_dev_stop(dev);
2980
2981         /* reprogram the RAR[0] in case user changed it. */
2982         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2983 }
2984
2985 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2986 {
2987         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2988         struct ixgbe_vfta * shadow_vfta =
2989                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2990         int i = 0, j = 0, vfta = 0, mask = 1;
2991
2992         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2993                 vfta = shadow_vfta->vfta[i];
2994                 if(vfta){
2995                         mask = 1;
2996                         for (j = 0; j < 32; j++){
2997                                 if(vfta & mask)
2998                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2999                                 mask<<=1;
3000                         }
3001                 }
3002         }
3003
3004 }
3005
3006 static int
3007 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3008 {
3009         struct ixgbe_hw *hw =
3010                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3011         struct ixgbe_vfta * shadow_vfta =
3012                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3013         uint32_t vid_idx = 0;
3014         uint32_t vid_bit = 0;
3015         int ret = 0;
3016
3017         PMD_INIT_FUNC_TRACE();
3018
3019         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3020         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3021         if(ret){
3022                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3023                 return ret;
3024         }
3025         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3026         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3027
3028         /* Save what we set and retore it after device reset */
3029         if (on)
3030                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3031         else
3032                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3033
3034         return 0;
3035 }
3036
3037 static void
3038 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3039 {
3040         struct ixgbe_hw *hw =
3041                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3042         uint32_t ctrl;
3043
3044         PMD_INIT_FUNC_TRACE();
3045
3046         if(queue >= hw->mac.max_rx_queues)
3047                 return;
3048
3049         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3050         if(on)
3051                 ctrl |= IXGBE_RXDCTL_VME;
3052         else
3053                 ctrl &= ~IXGBE_RXDCTL_VME;
3054         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3055
3056         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3057 }
3058
3059 static void
3060 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3061 {
3062         struct ixgbe_hw *hw =
3063                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3064         uint16_t i;
3065         int on = 0;
3066
3067         /* VF function only support hw strip feature, others are not support */
3068         if(mask & ETH_VLAN_STRIP_MASK){
3069                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3070
3071                 for(i=0; i < hw->mac.max_rx_queues; i++)
3072                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3073         }
3074 }
3075
3076 static int
3077 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3078 {
3079         uint32_t reg_val;
3080
3081         /* we only need to do this if VMDq is enabled */
3082         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3083         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3084                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3085                 return (-1);
3086         }
3087
3088         return 0;
3089 }
3090
3091 static uint32_t
3092 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3093 {
3094         uint32_t vector = 0;
3095         switch (hw->mac.mc_filter_type) {
3096         case 0:   /* use bits [47:36] of the address */
3097                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3098                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3099                 break;
3100         case 1:   /* use bits [46:35] of the address */
3101                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3102                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3103                 break;
3104         case 2:   /* use bits [45:34] of the address */
3105                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3106                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3107                 break;
3108         case 3:   /* use bits [43:32] of the address */
3109                 vector = ((uc_addr->addr_bytes[4]) |
3110                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3111                 break;
3112         default:  /* Invalid mc_filter_type */
3113                 break;
3114         }
3115
3116         /* vector can only be 12-bits or boundary will be exceeded */
3117         vector &= 0xFFF;
3118         return vector;
3119 }
3120
3121 static int
3122 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3123                                uint8_t on)
3124 {
3125         uint32_t vector;
3126         uint32_t uta_idx;
3127         uint32_t reg_val;
3128         uint32_t uta_shift;
3129         uint32_t rc;
3130         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3131         const uint32_t ixgbe_uta_bit_shift = 5;
3132         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3133         const uint32_t bit1 = 0x1;
3134
3135         struct ixgbe_hw *hw =
3136                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3137         struct ixgbe_uta_info *uta_info =
3138                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3139
3140         /* The UTA table only exists on 82599 hardware and newer */
3141         if (hw->mac.type < ixgbe_mac_82599EB)
3142                 return (-ENOTSUP);
3143
3144         vector = ixgbe_uta_vector(hw,mac_addr);
3145         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3146         uta_shift = vector & ixgbe_uta_bit_mask;
3147
3148         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3149         if(rc == on)
3150                 return 0;
3151
3152         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3153         if (on) {
3154                 uta_info->uta_in_use++;
3155                 reg_val |= (bit1 << uta_shift);
3156                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3157         } else {
3158                 uta_info->uta_in_use--;
3159                 reg_val &= ~(bit1 << uta_shift);
3160                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3161         }
3162
3163         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3164
3165         if (uta_info->uta_in_use > 0)
3166                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3167                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3168         else
3169                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3170
3171         return 0;
3172 }
3173
3174 static int
3175 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3176 {
3177         int i;
3178         struct ixgbe_hw *hw =
3179                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3180         struct ixgbe_uta_info *uta_info =
3181                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3182
3183         /* The UTA table only exists on 82599 hardware and newer */
3184         if (hw->mac.type < ixgbe_mac_82599EB)
3185                 return (-ENOTSUP);
3186
3187         if(on) {
3188                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3189                         uta_info->uta_shadow[i] = ~0;
3190                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3191                 }
3192         } else {
3193                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3194                         uta_info->uta_shadow[i] = 0;
3195                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3196                 }
3197         }
3198         return 0;
3199
3200 }
3201
3202 uint32_t
3203 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3204 {
3205         uint32_t new_val = orig_val;
3206
3207         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3208                 new_val |= IXGBE_VMOLR_AUPE;
3209         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3210                 new_val |= IXGBE_VMOLR_ROMPE;
3211         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3212                 new_val |= IXGBE_VMOLR_ROPE;
3213         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3214                 new_val |= IXGBE_VMOLR_BAM;
3215         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3216                 new_val |= IXGBE_VMOLR_MPE;
3217
3218         return new_val;
3219 }
3220
3221 static int
3222 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3223                                uint16_t rx_mask, uint8_t on)
3224 {
3225         int val = 0;
3226
3227         struct ixgbe_hw *hw =
3228                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3229         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3230
3231         if (hw->mac.type == ixgbe_mac_82598EB) {
3232                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3233                              " on 82599 hardware and newer");
3234                 return (-ENOTSUP);
3235         }
3236         if (ixgbe_vmdq_mode_check(hw) < 0)
3237                 return (-ENOTSUP);
3238
3239         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3240
3241         if (on)
3242                 vmolr |= val;
3243         else
3244                 vmolr &= ~val;
3245
3246         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3247
3248         return 0;
3249 }
3250
3251 static int
3252 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3253 {
3254         uint32_t reg,addr;
3255         uint32_t val;
3256         const uint8_t bit1 = 0x1;
3257
3258         struct ixgbe_hw *hw =
3259                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3260
3261         if (ixgbe_vmdq_mode_check(hw) < 0)
3262                 return (-ENOTSUP);
3263
3264         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3265         reg = IXGBE_READ_REG(hw, addr);
3266         val = bit1 << pool;
3267
3268         if (on)
3269                 reg |= val;
3270         else
3271                 reg &= ~val;
3272
3273         IXGBE_WRITE_REG(hw, addr,reg);
3274
3275         return 0;
3276 }
3277
3278 static int
3279 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3280 {
3281         uint32_t reg,addr;
3282         uint32_t val;
3283         const uint8_t bit1 = 0x1;
3284
3285         struct ixgbe_hw *hw =
3286                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3287
3288         if (ixgbe_vmdq_mode_check(hw) < 0)
3289                 return (-ENOTSUP);
3290
3291         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3292         reg = IXGBE_READ_REG(hw, addr);
3293         val = bit1 << pool;
3294
3295         if (on)
3296                 reg |= val;
3297         else
3298                 reg &= ~val;
3299
3300         IXGBE_WRITE_REG(hw, addr,reg);
3301
3302         return 0;
3303 }
3304
3305 static int
3306 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3307                         uint64_t pool_mask, uint8_t vlan_on)
3308 {
3309         int ret = 0;
3310         uint16_t pool_idx;
3311         struct ixgbe_hw *hw =
3312                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313
3314         if (ixgbe_vmdq_mode_check(hw) < 0)
3315                 return (-ENOTSUP);
3316         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3317                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3318                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3319                         if (ret < 0)
3320                                 return ret;
3321         }
3322
3323         return ret;
3324 }
3325
3326 static int
3327 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3328                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3329                         uint8_t rule_id, uint8_t on)
3330 {
3331         uint32_t mr_ctl,vlvf;
3332         uint32_t mp_lsb = 0;
3333         uint32_t mv_msb = 0;
3334         uint32_t mv_lsb = 0;
3335         uint32_t mp_msb = 0;
3336         uint8_t i = 0;
3337         int reg_index = 0;
3338         uint64_t vlan_mask = 0;
3339
3340         const uint8_t pool_mask_offset = 32;
3341         const uint8_t vlan_mask_offset = 32;
3342         const uint8_t dst_pool_offset = 8;
3343         const uint8_t rule_mr_offset  = 4;
3344         const uint8_t mirror_rule_mask= 0x0F;
3345
3346         struct ixgbe_mirror_info *mr_info =
3347                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3348         struct ixgbe_hw *hw =
3349                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3350
3351         if (ixgbe_vmdq_mode_check(hw) < 0)
3352                 return (-ENOTSUP);
3353
3354         /* Check if vlan mask is valid */
3355         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3356                 if (mirror_conf->vlan.vlan_mask == 0)
3357                         return (-EINVAL);
3358         }
3359
3360         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3361         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3362                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3363                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3364                                 /* search vlan id related pool vlan filter index */
3365                                 reg_index = ixgbe_find_vlvf_slot(hw,
3366                                                 mirror_conf->vlan.vlan_id[i]);
3367                                 if(reg_index < 0)
3368                                         return (-EINVAL);
3369                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3370                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3371                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3372                                                 == mirror_conf->vlan.vlan_id[i]))
3373                                         vlan_mask |= (1ULL << reg_index);
3374                                 else
3375                                         return (-EINVAL);
3376                         }
3377                 }
3378
3379                 if (on) {
3380                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3381                         mv_msb = vlan_mask >> vlan_mask_offset;
3382
3383                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3384                                                 mirror_conf->vlan.vlan_mask;
3385                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3386                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3387                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3388                                                 mirror_conf->vlan.vlan_id[i];
3389                         }
3390                 } else {
3391                         mv_lsb = 0;
3392                         mv_msb = 0;
3393                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3394                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3395                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3396                 }
3397         }
3398
3399         /*
3400          * if enable pool mirror, write related pool mask register,if disable
3401          * pool mirror, clear PFMRVM register
3402          */
3403         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3404                 if (on) {
3405                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3406                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3407                         mr_info->mr_conf[rule_id].pool_mask =
3408                                         mirror_conf->pool_mask;
3409
3410                 } else {
3411                         mp_lsb = 0;
3412                         mp_msb = 0;
3413                         mr_info->mr_conf[rule_id].pool_mask = 0;
3414                 }
3415         }
3416
3417         /* read  mirror control register and recalculate it */
3418         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3419
3420         if (on) {
3421                 mr_ctl |= mirror_conf->rule_type_mask;
3422                 mr_ctl &= mirror_rule_mask;
3423                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3424         } else
3425                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3426
3427         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3428         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3429
3430         /* write mirrror control  register */
3431         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3432
3433         /* write pool mirrror control  register */
3434         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3435                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3436                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3437                                 mp_msb);
3438         }
3439         /* write VLAN mirrror control  register */
3440         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3441                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3442                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3443                                 mv_msb);
3444         }
3445
3446         return 0;
3447 }
3448
3449 static int
3450 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3451 {
3452         int mr_ctl = 0;
3453         uint32_t lsb_val = 0;
3454         uint32_t msb_val = 0;
3455         const uint8_t rule_mr_offset = 4;
3456
3457         struct ixgbe_hw *hw =
3458                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3459         struct ixgbe_mirror_info *mr_info =
3460                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3461
3462         if (ixgbe_vmdq_mode_check(hw) < 0)
3463                 return (-ENOTSUP);
3464
3465         memset(&mr_info->mr_conf[rule_id], 0,
3466                 sizeof(struct rte_eth_vmdq_mirror_conf));
3467
3468         /* clear PFVMCTL register */
3469         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3470
3471         /* clear pool mask register */
3472         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3473         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3474
3475         /* clear vlan mask register */
3476         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3477         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3478
3479         return 0;
3480 }
3481
3482 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3483         uint16_t queue_idx, uint16_t tx_rate)
3484 {
3485         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3486         uint32_t rf_dec, rf_int;
3487         uint32_t bcnrc_val;
3488         uint16_t link_speed = dev->data->dev_link.link_speed;
3489
3490         if (queue_idx >= hw->mac.max_tx_queues)
3491                 return -EINVAL;
3492
3493         if (tx_rate != 0) {
3494                 /* Calculate the rate factor values to set */
3495                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3496                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3497                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3498
3499                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3500                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3501                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3502                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3503         } else {
3504                 bcnrc_val = 0;
3505         }
3506
3507         /*
3508          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3509          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3510          * set as 0x4.
3511          */
3512         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3513                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3514                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3515                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3516                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3517         else
3518                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3519                         IXGBE_MMW_SIZE_DEFAULT);
3520
3521         /* Set RTTBCNRC of queue X */
3522         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3523         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3524         IXGBE_WRITE_FLUSH(hw);
3525
3526         return 0;
3527 }
3528
3529 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3530         uint16_t tx_rate, uint64_t q_msk)
3531 {
3532         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3533         struct ixgbe_vf_info *vfinfo =
3534                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3535         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3536         uint32_t queue_stride =
3537                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3538         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3539         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3540         uint16_t total_rate = 0;
3541
3542         if (queue_end >= hw->mac.max_tx_queues)
3543                 return -EINVAL;
3544
3545         if (vfinfo != NULL) {
3546                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3547                         if (vf_idx == vf)
3548                                 continue;
3549                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3550                                 idx++)
3551                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3552                 }
3553         } else
3554                 return -EINVAL;
3555
3556         /* Store tx_rate for this vf. */
3557         for (idx = 0; idx < nb_q_per_pool; idx++) {
3558                 if (((uint64_t)0x1 << idx) & q_msk) {
3559                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3560                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3561                         total_rate += tx_rate;
3562                 }
3563         }
3564
3565         if (total_rate > dev->data->dev_link.link_speed) {
3566                 /*
3567                  * Reset stored TX rate of the VF if it causes exceed
3568                  * link speed.
3569                  */
3570                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3571                 return -EINVAL;
3572         }
3573
3574         /* Set RTTBCNRC of each queue/pool for vf X  */
3575         for (; queue_idx <= queue_end; queue_idx++) {
3576                 if (0x1 & q_msk)
3577                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3578                 q_msk = q_msk >> 1;
3579         }
3580
3581         return 0;
3582 }
3583
3584 static void
3585 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3586                      __attribute__((unused)) uint32_t index,
3587                      __attribute__((unused)) uint32_t pool)
3588 {
3589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3590         int diag;
3591
3592         /*
3593          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3594          * operation. Trap this case to avoid exhausting the [very limited]
3595          * set of PF resources used to store VF MAC addresses.
3596          */
3597         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3598                 return;
3599         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3600         if (diag == 0)
3601                 return;
3602         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3603 }
3604
3605 static void
3606 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3607 {
3608         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3609         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3610         struct ether_addr *mac_addr;
3611         uint32_t i;
3612         int diag;
3613
3614         /*
3615          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3616          * not support the deletion of a given MAC address.
3617          * Instead, it imposes to delete all MAC addresses, then to add again
3618          * all MAC addresses with the exception of the one to be deleted.
3619          */
3620         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3621
3622         /*
3623          * Add again all MAC addresses, with the exception of the deleted one
3624          * and of the permanent MAC address.
3625          */
3626         for (i = 0, mac_addr = dev->data->mac_addrs;
3627              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3628                 /* Skip the deleted MAC address */
3629                 if (i == index)
3630                         continue;
3631                 /* Skip NULL MAC addresses */
3632                 if (is_zero_ether_addr(mac_addr))
3633                         continue;
3634                 /* Skip the permanent MAC address */
3635                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3636                         continue;
3637                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3638                 if (diag != 0)
3639                         PMD_DRV_LOG(ERR,
3640                                     "Adding again MAC address "
3641                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3642                                     "diag=%d",
3643                                     mac_addr->addr_bytes[0],
3644                                     mac_addr->addr_bytes[1],
3645                                     mac_addr->addr_bytes[2],
3646                                     mac_addr->addr_bytes[3],
3647                                     mac_addr->addr_bytes[4],
3648                                     mac_addr->addr_bytes[5],
3649                                     diag);
3650         }
3651 }
3652
3653 /*
3654  * add syn filter
3655  *
3656  * @param
3657  * dev: Pointer to struct rte_eth_dev.
3658  * filter: ponter to the filter that will be added.
3659  * rx_queue: the queue id the filter assigned to.
3660  *
3661  * @return
3662  *    - On success, zero.
3663  *    - On failure, a negative value.
3664  */
3665 static int
3666 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3667                         struct rte_syn_filter *filter, uint16_t rx_queue)
3668 {
3669         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3670         uint32_t synqf;
3671
3672         if (hw->mac.type != ixgbe_mac_82599EB)
3673                 return -ENOSYS;
3674
3675         if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3676                 return -EINVAL;
3677
3678         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3679
3680         if (synqf & IXGBE_SYN_FILTER_ENABLE)
3681                 return -EINVAL;
3682
3683         synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3684                 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3685
3686         if (filter->hig_pri)
3687                 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3688         else
3689                 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3690
3691         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3692         return 0;
3693 }
3694
3695 /*
3696  * remove syn filter
3697  *
3698  * @param
3699  * dev: Pointer to struct rte_eth_dev.
3700  *
3701  * @return
3702  *    - On success, zero.
3703  *    - On failure, a negative value.
3704  */
3705 static int
3706 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3707 {
3708         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3709         uint32_t synqf;
3710
3711         if (hw->mac.type != ixgbe_mac_82599EB)
3712                 return -ENOSYS;
3713
3714         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3715
3716         synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3717
3718         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3719         return 0;
3720 }
3721
3722 /*
3723  * get the syn filter's info
3724  *
3725  * @param
3726  * dev: Pointer to struct rte_eth_dev.
3727  * filter: ponter to the filter that returns.
3728  * *rx_queue: pointer to the queue id the filter assigned to.
3729  *
3730  * @return
3731  *    - On success, zero.
3732  *    - On failure, a negative value.
3733  */
3734 static int
3735 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3736                         struct rte_syn_filter *filter, uint16_t *rx_queue)
3737
3738 {
3739         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3740         uint32_t synqf;
3741
3742         if (hw->mac.type != ixgbe_mac_82599EB)
3743                 return -ENOSYS;
3744
3745         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3746         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3747                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3748                 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3749                 return 0;
3750         }
3751         return -ENOENT;
3752 }
3753
3754 /*
3755  * add an ethertype filter
3756  *
3757  * @param
3758  * dev: Pointer to struct rte_eth_dev.
3759  * index: the index the filter allocates.
3760  * filter: ponter to the filter that will be added.
3761  * rx_queue: the queue id the filter assigned to.
3762  *
3763  * @return
3764  *    - On success, zero.
3765  *    - On failure, a negative value.
3766  */
3767 static int
3768 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3769                         uint16_t index, struct rte_ethertype_filter *filter,
3770                         uint16_t rx_queue)
3771 {
3772         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3773         uint32_t etqf, etqs = 0;
3774
3775         if (hw->mac.type != ixgbe_mac_82599EB)
3776                 return -ENOSYS;
3777
3778         if (index >= IXGBE_MAX_ETQF_FILTERS ||
3779                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3780                 return -EINVAL;
3781
3782         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3783         if (etqf & IXGBE_ETQF_FILTER_EN)
3784                 return -EINVAL;  /* filter index is in use. */
3785
3786         etqf = 0;
3787         etqf |= IXGBE_ETQF_FILTER_EN;
3788         etqf |= (uint32_t)filter->ethertype;
3789
3790         if (filter->priority_en) {
3791                 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3792                         return -EINVAL;
3793                 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3794                 etqf |= IXGBE_ETQF_UP_EN;
3795         }
3796         etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3797         etqs |= IXGBE_ETQS_QUEUE_EN;
3798
3799         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3800         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3801         return 0;
3802 }
3803
3804 /*
3805  * remove an ethertype filter
3806  *
3807  * @param
3808  * dev: Pointer to struct rte_eth_dev.
3809  * index: the index the filter allocates.
3810  *
3811  * @return
3812  *    - On success, zero.
3813  *    - On failure, a negative value.
3814  */
3815 static int
3816 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3817                         uint16_t index)
3818 {
3819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3820
3821         if (hw->mac.type != ixgbe_mac_82599EB)
3822                 return -ENOSYS;
3823
3824         if (index >= IXGBE_MAX_ETQF_FILTERS)
3825                 return -EINVAL;
3826
3827         IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3828         IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3829
3830         return 0;
3831 }
3832
3833 /*
3834  * get an ethertype filter
3835  *
3836  * @param
3837  * dev: Pointer to struct rte_eth_dev.
3838  * index: the index the filter allocates.
3839  * filter: ponter to the filter that will be gotten.
3840  * *rx_queue: the ponited of the queue id the filter assigned to.
3841  *
3842  * @return
3843  *    - On success, zero.
3844  *    - On failure, a negative value.
3845  */
3846 static int
3847 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3848                         uint16_t index, struct rte_ethertype_filter *filter,
3849                         uint16_t *rx_queue)
3850 {
3851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3852         uint32_t etqf, etqs;
3853
3854         if (hw->mac.type != ixgbe_mac_82599EB)
3855                 return -ENOSYS;
3856
3857         if (index >= IXGBE_MAX_ETQF_FILTERS)
3858                 return -EINVAL;
3859
3860         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3861         etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3862         if (etqf & IXGBE_ETQF_FILTER_EN) {
3863                 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3864                 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3865                 if (filter->priority_en)
3866                         filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3867                 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3868                 return 0;
3869         }
3870         return -ENOENT;
3871 }
3872
3873 static inline enum ixgbe_5tuple_protocol
3874 convert_protocol_type(uint8_t protocol_value)
3875 {
3876         if (protocol_value == IPPROTO_TCP)
3877                 return IXGBE_FILTER_PROTOCOL_TCP;
3878         else if (protocol_value == IPPROTO_UDP)
3879                 return IXGBE_FILTER_PROTOCOL_UDP;
3880         else if (protocol_value == IPPROTO_SCTP)
3881                 return IXGBE_FILTER_PROTOCOL_SCTP;
3882         else
3883                 return IXGBE_FILTER_PROTOCOL_NONE;
3884 }
3885
3886 static inline uint8_t
3887 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3888 {
3889         if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3890                 return IPPROTO_TCP;
3891         else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3892                 return IPPROTO_UDP;
3893         else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3894                 return IPPROTO_SCTP;
3895         else
3896                 return 0;
3897 }
3898
3899 /*
3900  * add a 5tuple filter
3901  *
3902  * @param
3903  * dev: Pointer to struct rte_eth_dev.
3904  * index: the index the filter allocates.
3905  * filter: ponter to the filter that will be added.
3906  * rx_queue: the queue id the filter assigned to.
3907  *
3908  * @return
3909  *    - On success, zero.
3910  *    - On failure, a negative value.
3911  */
3912 static int
3913 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3914                         struct rte_5tuple_filter *filter, uint16_t rx_queue)
3915 {
3916         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3917         uint32_t ftqf, sdpqf = 0;
3918         uint32_t l34timir = 0;
3919         uint8_t mask = 0xff;
3920
3921         if (hw->mac.type != ixgbe_mac_82599EB)
3922                 return -ENOSYS;
3923
3924         if (index >= IXGBE_MAX_FTQF_FILTERS ||
3925                 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3926                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3927                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3928                 return -EINVAL;  /* filter index is out of range. */
3929
3930         if (filter->tcp_flags) {
3931                 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3932                 return -EINVAL;
3933         }
3934
3935         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3936         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3937                 return -EINVAL;  /* filter index is in use. */
3938
3939         ftqf = 0;
3940         sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3941         sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3942
3943         ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3944                 IXGBE_FTQF_PROTOCOL_MASK);
3945         ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3946                 IXGBE_FTQF_PRIORITY_SHIFT);
3947         if (filter->src_ip_mask == 0) /* 0 means compare. */
3948                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3949         if (filter->dst_ip_mask == 0)
3950                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3951         if (filter->src_port_mask == 0)
3952                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3953         if (filter->dst_port_mask == 0)
3954                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3955         if (filter->protocol_mask == 0)
3956                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3957         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3958         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3959         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3960
3961         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3962         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3963         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3964         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3965
3966         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3967         l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3968         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3969         return 0;
3970 }
3971
3972 /*
3973  * remove a 5tuple filter
3974  *
3975  * @param
3976  * dev: Pointer to struct rte_eth_dev.
3977  * index: the index the filter allocates.
3978  *
3979  * @return
3980  *    - On success, zero.
3981  *    - On failure, a negative value.
3982  */
3983 static int
3984 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3985                         uint16_t index)
3986 {
3987         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3988
3989         if (hw->mac.type != ixgbe_mac_82599EB)
3990                 return -ENOSYS;
3991
3992         if (index >= IXGBE_MAX_FTQF_FILTERS)
3993                 return -EINVAL;  /* filter index is out of range. */
3994
3995         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3996         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3997         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3998         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3999         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4000         return 0;
4001 }
4002
4003 /*
4004  * get a 5tuple filter
4005  *
4006  * @param
4007  * dev: Pointer to struct rte_eth_dev.
4008  * index: the index the filter allocates
4009  * filter: ponter to the filter that returns.
4010  * *rx_queue: pointer of the queue id the filter assigned to.
4011  *
4012  * @return
4013  *    - On success, zero.
4014  *    - On failure, a negative value.
4015  */
4016 static int
4017 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
4018                         struct rte_5tuple_filter *filter, uint16_t *rx_queue)
4019 {
4020         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4021         uint32_t sdpqf, ftqf, l34timir;
4022         uint8_t mask;
4023         enum ixgbe_5tuple_protocol proto;
4024
4025         if (hw->mac.type != ixgbe_mac_82599EB)
4026                 return -ENOSYS;
4027
4028         if (index >= IXGBE_MAX_FTQF_FILTERS)
4029                 return -EINVAL;  /* filter index is out of range. */
4030
4031         ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
4032         if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
4033                 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
4034                 filter->protocol = revert_protocol_type(proto);
4035                 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
4036                                         IXGBE_FTQF_PRIORITY_MASK;
4037                 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
4038                                         IXGBE_FTQF_5TUPLE_MASK_MASK);
4039                 filter->src_ip_mask =
4040                         (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
4041                 filter->dst_ip_mask =
4042                         (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
4043                 filter->src_port_mask =
4044                         (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
4045                 filter->dst_port_mask =
4046                         (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
4047                 filter->protocol_mask =
4048                         (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
4049
4050                 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
4051                 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
4052                                         IXGBE_SDPQF_DSTPORT_SHIFT;
4053                 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
4054                 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
4055                 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
4056
4057                 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
4058                 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
4059                                         IXGBE_L34T_IMIR_QUEUE_SHIFT;
4060                 return 0;
4061         }
4062         return -ENOENT;
4063 }
4064
4065 static int
4066 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4067 {
4068         struct ixgbe_hw *hw;
4069         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4070
4071         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4072
4073         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4074                 return -EINVAL;
4075
4076         /* refuse mtu that requires the support of scattered packets when this
4077          * feature has not been enabled before. */
4078         if (!dev->data->scattered_rx &&
4079             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4080              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4081                 return -EINVAL;
4082
4083         /*
4084          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4085          * request of the version 2.0 of the mailbox API.
4086          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4087          * of the mailbox API.
4088          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4089          * prior to 3.11.33 which contains the following change:
4090          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4091          */
4092         ixgbevf_rlpml_set_vf(hw, max_frame);
4093
4094         /* update max frame size */
4095         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4096         return 0;
4097 }
4098
4099 static struct rte_driver rte_ixgbe_driver = {
4100         .type = PMD_PDEV,
4101         .init = rte_ixgbe_pmd_init,
4102 };
4103
4104 static struct rte_driver rte_ixgbevf_driver = {
4105         .type = PMD_PDEV,
4106         .init = rte_ixgbevf_pmd_init,
4107 };
4108
4109 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4110 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);