lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  */
  34
  35 #include <sys/queue.h>
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <string.h>
  40 #include <unistd.h>
  41 #include <stdarg.h>
  42 #include <inttypes.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_atomic.h>
  61 #include <rte_malloc.h>
  62
  63 #include "ixgbe_logs.h"
  64 #include "ixgbe/ixgbe_api.h"
  65 #include "ixgbe/ixgbe_vf.h"
  66 #include "ixgbe/ixgbe_common.h"
  67 #include "ixgbe_ethdev.h"
  68
  69 /*
  70  * High threshold controlling when to start sending XOFF frames. Must be at
  71  * least 8 bytes less than receive packet buffer size. This value is in units
  72  * of 1024 bytes.
  73  */
  74 #define IXGBE_FC_HI    0x80
  75
  76 /*
  77  * Low threshold controlling when to start sending XON frames. This value is
  78  * in units of 1024 bytes.
  79  */
  80 #define IXGBE_FC_LO    0x40
  81
  82 /* Timer value included in XOFF frames. */
  83 #define IXGBE_FC_PAUSE 0x680
  84
  85 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  86 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  87
  88 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  89
  90 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
  91                 struct rte_eth_dev *eth_dev);
  92 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
  93 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
  94 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
  95 static void ixgbe_dev_close(struct rte_eth_dev *dev);
  96 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
  97 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
  98 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
  99 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 100 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 101                                 int wait_to_complete);
 102 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 103                                 struct rte_eth_stats *stats);
 104 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 105 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 106                                              uint16_t queue_id,
 107                                              uint8_t stat_idx,
 108                                              uint8_t is_rx);
 109 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 110                                 struct rte_eth_dev_info *dev_info);
 111 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 112                 uint16_t vlan_id, int on);
 113 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 114 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 115                 uint16_t queue, bool on);
 116 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 117                 int on);
 118 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 119 static void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 120 static void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 121 static void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
 122 static void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
 123 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 124 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 125 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 126 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 127
 128 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 129 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 130 static int  ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 131                 struct rte_eth_fc_conf *fc_conf);
 132 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 133                 struct rte_eth_pfc_conf *pfc_conf);
 134 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 135 static int ixgbe_dev_interrupt_setup(struct rte_eth_dev *dev);
 136 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 137 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 139                 void *param);
 140 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 141 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 142                 uint32_t index, uint32_t pool);
 143 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 144 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 145
 146 /* For Virtual Function support */
 147 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 148                 struct rte_eth_dev *eth_dev);
 149 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 150 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 151 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 152 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 153 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 154 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 155                 struct rte_eth_stats *stats);
 156 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 157 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 158                 uint16_t vlan_id, int on);
 159 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 160                 uint16_t queue, int on);
 161 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 162 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 163
 164
 165 /*
 166  * Define VF Stats MACRO for Non "cleared on read" register
 167  */
 168 #define UPDATE_VF_STAT(reg, last, cur)                          \
 169 {                                                               \
 170         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 171         cur += latest - last;                                   \
 172         last = latest;                                          \
 173 }
 174
 175 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 176 {                                                                \
 177         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 178         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 179         u64 latest = ((new_msb << 32) | new_lsb);                \
 180         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 181         last = latest;                                           \
 182 }
 183
 184 #define IXGBE_SET_HWSTRIP(h, q) do{\
 185                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 186                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 187                 (h)->bitmap[idx] |= 1 << bit;\
 188         }while(0)
 189
 190 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 191                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 192                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 193                 (h)->bitmap[idx] &= ~(1 << bit);\
 194         }while(0)
 195
 196 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 197                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 198                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 199                 (r) = (h)->bitmap[idx] >> bit & 1;\
 200         }while(0)
 201
 202 /*
 203  * The set of PCI devices this driver supports
 204  */
 205 static struct rte_pci_id pci_id_ixgbe_map[] = {
 206
 207 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 208 #include "rte_pci_dev_ids.h"
 209
 210 { .vendor_id = 0, /* sentinel */ },
 211 };
 212
 213
 214 /*
 215  * The set of PCI devices this driver supports (for 82599 VF)
 216  */
 217 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 218
 219 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 220 #include "rte_pci_dev_ids.h"
 221 { .vendor_id = 0, /* sentinel */ },
 222
 223 };
 224
 225 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 226         .dev_configure        = ixgbe_dev_configure,
 227         .dev_start            = ixgbe_dev_start,
 228         .dev_stop             = ixgbe_dev_stop,
 229         .dev_close            = ixgbe_dev_close,
 230         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 231         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 232         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 233         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 234         .link_update          = ixgbe_dev_link_update,
 235         .stats_get            = ixgbe_dev_stats_get,
 236         .stats_reset          = ixgbe_dev_stats_reset,
 237         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 238         .dev_infos_get        = ixgbe_dev_info_get,
 239         .vlan_filter_set      = ixgbe_vlan_filter_set,
 240         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 241         .vlan_offload_set     = ixgbe_vlan_offload_set,
 242         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 243         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 244         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 245         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 246         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 247         .dev_led_on           = ixgbe_dev_led_on,
 248         .dev_led_off          = ixgbe_dev_led_off,
 249         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 250         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 251         .mac_addr_add         = ixgbe_add_rar,
 252         .mac_addr_remove      = ixgbe_remove_rar,
 253         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 254         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 255         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 256         .fdir_infos_get               = ixgbe_fdir_info_get,
 257         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 258         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 259         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 260         .fdir_set_masks               = ixgbe_fdir_set_masks,
 261 };
 262
 263 /*
 264  * dev_ops for virtual function, bare necessities for basic vf
 265  * operation have been implemented
 266  */
 267 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 268
 269         .dev_configure        = ixgbevf_dev_configure,
 270         .dev_start            = ixgbevf_dev_start,
 271         .dev_stop             = ixgbevf_dev_stop,
 272         .link_update          = ixgbe_dev_link_update,
 273         .stats_get            = ixgbevf_dev_stats_get,
 274         .stats_reset          = ixgbevf_dev_stats_reset,
 275         .dev_close            = ixgbevf_dev_close,
 276         .dev_infos_get        = ixgbe_dev_info_get,
 277         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 278         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 279         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 280         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 281         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 282         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 283         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 284 };
 285
 286 /**
 287  * Atomically reads the link status information from global
 288  * structure rte_eth_dev.
 289  *
 290  * @param dev
 291  *   - Pointer to the structure rte_eth_dev to read from.
 292  *   - Pointer to the buffer to be saved with the link status.
 293  *
 294  * @return
 295  *   - On success, zero.
 296  *   - On failure, negative value.
 297  */
 298 static inline int
 299 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 300                                 struct rte_eth_link *link)
 301 {
 302         struct rte_eth_link *dst = link;
 303         struct rte_eth_link *src = &(dev->data->dev_link);
 304
 305         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 306                                         *(uint64_t *)src) == 0)
 307                 return -1;
 308
 309         return 0;
 310 }
 311
 312 /**
 313  * Atomically writes the link status information into global
 314  * structure rte_eth_dev.
 315  *
 316  * @param dev
 317  *   - Pointer to the structure rte_eth_dev to read from.
 318  *   - Pointer to the buffer to be saved with the link status.
 319  *
 320  * @return
 321  *   - On success, zero.
 322  *   - On failure, negative value.
 323  */
 324 static inline int
 325 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 326                                 struct rte_eth_link *link)
 327 {
 328         struct rte_eth_link *dst = &(dev->data->dev_link);
 329         struct rte_eth_link *src = link;
 330
 331         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 332                                         *(uint64_t *)src) == 0)
 333                 return -1;
 334
 335         return 0;
 336 }
 337
 338 /*
 339  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 340  */
 341 static inline int
 342 ixgbe_is_sfp(struct ixgbe_hw *hw)
 343 {
 344         switch (hw->phy.type) {
 345         case ixgbe_phy_sfp_avago:
 346         case ixgbe_phy_sfp_ftl:
 347         case ixgbe_phy_sfp_intel:
 348         case ixgbe_phy_sfp_unknown:
 349         case ixgbe_phy_sfp_passive_tyco:
 350         case ixgbe_phy_sfp_passive_unknown:
 351                 return 1;
 352         default:
 353                 return 0;
 354         }
 355 }
 356
 357 /*
 358  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 359  */
 360 static void
 361 ixgbe_disable_intr(struct ixgbe_hw *hw)
 362 {
 363         PMD_INIT_FUNC_TRACE();
 364
 365         if (hw->mac.type == ixgbe_mac_82598EB) {
 366                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 367         } else {
 368                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 369                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 370                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 371         }
 372         IXGBE_WRITE_FLUSH(hw);
 373 }
 374
 375 /*
 376  * This function resets queue statistics mapping registers.
 377  * From Niantic datasheet, Initialization of Statistics section:
 378  * "...if software requires the queue counters, the RQSMR and TQSM registers
 379  * must be re-programmed following a device reset.
 380  */
 381 static void
 382 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 383 {
 384         uint32_t i;
 385
 386         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 387                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 388                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 389         }
 390 }
 391
 392
 393 static int
 394 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 395                                   uint16_t queue_id,
 396                                   uint8_t stat_idx,
 397                                   uint8_t is_rx)
 398 {
 399 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 400 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 401 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 402
 403         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 404         struct ixgbe_stat_mapping_registers *stat_mappings =
 405                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 406         uint32_t qsmr_mask = 0;
 407         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 408         uint32_t q_map;
 409         uint8_t n, offset;
 410
 411         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 412                 return -ENOSYS;
 413
 414         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 415                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
 416
 417         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 418         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 419                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 420                 return -EIO;
 421         }
 422         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 423
 424         /* Now clear any previous stat_idx set */
 425         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 426         if (!is_rx)
 427                 stat_mappings->tqsm[n] &= ~clearing_mask;
 428         else
 429                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 430
 431         q_map = (uint32_t)stat_idx;
 432         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 433         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 434         if (!is_rx)
 435                 stat_mappings->tqsm[n] |= qsmr_mask;
 436         else
 437                 stat_mappings->rqsmr[n] |= qsmr_mask;
 438
 439         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 440                      "%s[%d] = 0x%08x\n",
 441                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
 442                      is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 443
 444         /* Now write the mapping in the appropriate register */
 445         if (is_rx) {
 446                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 447                              stat_mappings->rqsmr[n], n);
 448                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 449         }
 450         else {
 451                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 452                              stat_mappings->tqsm[n], n);
 453                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 454         }
 455         return 0;
 456 }
 457
 458 static void
 459 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 460 {
 461         struct ixgbe_stat_mapping_registers *stat_mappings =
 462                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 463         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 464         int i;
 465
 466         /* write whatever was in stat mapping table to the NIC */
 467         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 468                 /* rx */
 469                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 470
 471                 /* tx */
 472                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 473         }
 474 }
 475
 476 static void
 477 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 478 {
 479         uint8_t i;
 480         struct ixgbe_dcb_tc_config *tc;
 481         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 482
 483         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 484         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 485         for (i = 0; i < dcb_max_tc; i++) {
 486                 tc = &dcb_config->tc_config[i];
 487                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 488                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 489                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 490                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 491                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 492                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 493                 tc->pfc = ixgbe_dcb_pfc_disabled;
 494         }
 495
 496         /* Initialize default user to priority mapping, UPx->TC0 */
 497         tc = &dcb_config->tc_config[0];
 498         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 499         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 500         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 501                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 502                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 503         }
 504         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 505         dcb_config->pfc_mode_enable = false;
 506         dcb_config->vt_mode = true;
 507         dcb_config->round_robin_enable = false;
 508         /* support all DCB capabilities in 82599 */
 509         dcb_config->support.capabilities = 0xFF;
 510
 511         /*we only support 4 Tcs for X540*/
 512         if (hw->mac.type == ixgbe_mac_X540) {
 513                 dcb_config->num_tcs.pg_tcs = 4;
 514                 dcb_config->num_tcs.pfc_tcs = 4;
 515         }
 516 }
 517
 518 /*
 519  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 520  * It returns 0 on success.
 521  */
 522 static int
 523 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 524                      struct rte_eth_dev *eth_dev)
 525 {
 526         struct rte_pci_device *pci_dev;
 527         struct ixgbe_hw *hw =
 528                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 529         struct ixgbe_vfta * shadow_vfta =
 530                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 531         struct ixgbe_hwstrip *hwstrip =
 532                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 533         struct ixgbe_dcb_config *dcb_config =
 534                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 535         uint32_t ctrl_ext;
 536         uint16_t csum;
 537         int diag, i;
 538
 539         PMD_INIT_FUNC_TRACE();
 540
 541         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 542         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 543         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 544
 545         /* for secondary processes, we don't initialise any further as primary
 546          * has already done this work. Only check we don't need a different
 547          * RX function */
 548         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 549                 if (eth_dev->data->scattered_rx)
 550                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 551                 return 0;
 552         }
 553         pci_dev = eth_dev->pci_dev;
 554
 555         /* Vendor and Device ID need to be set before init of shared code */
 556         hw->device_id = pci_dev->id.device_id;
 557         hw->vendor_id = pci_dev->id.vendor_id;
 558         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 559
 560         /* Initialize the shared code */
 561         diag = ixgbe_init_shared_code(hw);
 562         if (diag != IXGBE_SUCCESS) {
 563                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 564                 return -EIO;
 565         }
 566
 567         /* Initialize DCB configuration*/
 568         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 569         ixgbe_dcb_init(hw,dcb_config);
 570         /* Get Hardware Flow Control setting */
 571         hw->fc.requested_mode = ixgbe_fc_full;
 572         hw->fc.current_mode = ixgbe_fc_full;
 573         hw->fc.pause_time = IXGBE_FC_PAUSE;
 574         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 575                 hw->fc.low_water[i] = IXGBE_FC_LO;
 576                 hw->fc.high_water[i] = IXGBE_FC_HI;
 577         }
 578         hw->fc.send_xon = 1;
 579
 580         ixgbe_disable_intr(hw);
 581
 582         /* Make sure we have a good EEPROM before we read from it */
 583         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 584         if (diag != IXGBE_SUCCESS) {
 585                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 586                 return -EIO;
 587         }
 588
 589         diag = ixgbe_init_hw(hw);
 590
 591         /*
 592          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 593          * is called too soon after the kernel driver unbinding/binding occurs.
 594          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 595          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 596          * also called. See ixgbe_identify_phy_82599(). The reason for the
 597          * failure is not known, and only occuts when virtualisation features
 598          * are disabled in the bios. A delay of 100ms  was found to be enough by
 599          * trial-and-error, and is doubled to be safe.
 600          */
 601         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 602                 rte_delay_ms(200);
 603                 diag = ixgbe_init_hw(hw);
 604         }
 605
 606         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 607                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 608                     "LOM.  Please be aware there may be issues associated "
 609                     "with your hardware.\n If you are experiencing problems "
 610                     "please contact your Intel or hardware representative "
 611                     "who provided you with this hardware.\n");
 612         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 613                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 614         if (diag) {
 615                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 616                 return -EIO;
 617         }
 618
 619         /* pick up the PCI bus settings for reporting later */
 620         ixgbe_get_bus_info(hw);
 621
 622         /* reset mappings for queue statistics hw counters*/
 623         ixgbe_reset_qstat_mappings(hw);
 624
 625         /* Allocate memory for storing MAC addresses */
 626         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 627                         hw->mac.num_rar_entries, 0);
 628         if (eth_dev->data->mac_addrs == NULL) {
 629                 PMD_INIT_LOG(ERR,
 630                         "Failed to allocate %d bytes needed to store MAC addresses",
 631                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 632                 return -ENOMEM;
 633         }
 634         /* Copy the permanent MAC address */
 635         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 636                         &eth_dev->data->mac_addrs[0]);
 637
 638         /* initialize the vfta */
 639         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 640
 641         /* initialize the hw strip bitmap*/
 642         memset(hwstrip, 0, sizeof(*hwstrip));
 643
 644         /* let hardware know driver is loaded */
 645         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 646         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 647         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 648
 649         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 650                 PMD_INIT_LOG(DEBUG,
 651                              "MAC: %d, PHY: %d, SFP+: %d<n",
 652                              (int) hw->mac.type, (int) hw->phy.type,
 653                              (int) hw->phy.sfp_type);
 654         else
 655                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 656                              (int) hw->mac.type, (int) hw->phy.type);
 657
 658         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 659                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 660                         pci_dev->id.device_id);
 661
 662         rte_intr_callback_register(&(pci_dev->intr_handle),
 663                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 664
 665         return 0;
 666 }
 667
 668 /*
 669  * Virtual Function device init
 670  */
 671 static int
 672 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 673                      struct rte_eth_dev *eth_dev)
 674 {
 675         struct rte_pci_device *pci_dev;
 676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 677         int diag;
 678         struct ixgbe_vfta * shadow_vfta =
 679                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 680         struct ixgbe_hwstrip *hwstrip =
 681                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 682
 683         PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
 684
 685         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 686         pci_dev = eth_dev->pci_dev;
 687
 688         hw->device_id = pci_dev->id.device_id;
 689         hw->vendor_id = pci_dev->id.vendor_id;
 690         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 691
 692         /* initialize the vfta */
 693         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 694
 695         /* initialize the hw strip bitmap*/
 696         memset(hwstrip, 0, sizeof(*hwstrip));
 697
 698         /* Initialize the shared code */
 699         diag = ixgbe_init_shared_code(hw);
 700         if (diag != IXGBE_SUCCESS) {
 701                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 702                 return -EIO;
 703         }
 704
 705         /* init_mailbox_params */
 706         hw->mbx.ops.init_params(hw);
 707
 708         /* Disable the interrupts for VF */
 709         ixgbevf_intr_disable(hw);
 710
 711         hw->mac.num_rar_entries = hw->mac.max_rx_queues;
 712         diag = hw->mac.ops.reset_hw(hw);
 713         if (diag != IXGBE_SUCCESS) {
 714                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 715                 return (diag);
 716         }
 717
 718         /* Allocate memory for storing MAC addresses */
 719         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 720                         hw->mac.num_rar_entries, 0);
 721         if (eth_dev->data->mac_addrs == NULL) {
 722                 PMD_INIT_LOG(ERR,
 723                         "Failed to allocate %d bytes needed to store MAC addresses",
 724                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 725                 return -ENOMEM;
 726         }
 727         /* Copy the permanent MAC address */
 728         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 729                         &eth_dev->data->mac_addrs[0]);
 730
 731         /* reset the hardware with the new settings */
 732         diag = hw->mac.ops.start_hw(hw);
 733         switch (diag) {
 734                 case  0:
 735                         break;
 736
 737                 default:
 738                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 739                         return (-EIO);
 740         }
 741
 742         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
 743                          eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
 744                          "ixgbe_mac_82599_vf");
 745
 746         return 0;
 747 }
 748
 749 static struct eth_driver rte_ixgbe_pmd = {
 750         {
 751                 .name = "rte_ixgbe_pmd",
 752                 .id_table = pci_id_ixgbe_map,
 753                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 754         },
 755         .eth_dev_init = eth_ixgbe_dev_init,
 756         .dev_private_size = sizeof(struct ixgbe_adapter),
 757 };
 758
 759 /*
 760  * virtual function driver struct
 761  */
 762 static struct eth_driver rte_ixgbevf_pmd = {
 763         {
 764                 .name = "rte_ixgbevf_pmd",
 765                 .id_table = pci_id_ixgbevf_map,
 766                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 767         },
 768         .eth_dev_init = eth_ixgbevf_dev_init,
 769         .dev_private_size = sizeof(struct ixgbe_adapter),
 770 };
 771
 772 /*
 773  * Driver initialization routine.
 774  * Invoked once at EAL init time.
 775  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 776  */
 777 int
 778 rte_ixgbe_pmd_init(void)
 779 {
 780         PMD_INIT_FUNC_TRACE();
 781
 782         rte_eth_driver_register(&rte_ixgbe_pmd);
 783         return 0;
 784 }
 785
 786 /*
 787  * VF Driver initialization routine.
 788  * Invoked one at EAL init time.
 789  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
 790  */
 791 int
 792 rte_ixgbevf_pmd_init(void)
 793 {
 794         DEBUGFUNC("rte_ixgbevf_pmd_init");
 795
 796         rte_eth_driver_register(&rte_ixgbevf_pmd);
 797         return (0);
 798 }
 799
 800 static int
 801 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 802 {
 803         struct ixgbe_hw *hw =
 804                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 805         struct ixgbe_vfta * shadow_vfta =
 806                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
 807         uint32_t vfta;
 808         uint32_t vid_idx;
 809         uint32_t vid_bit;
 810
 811         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
 812         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
 813         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
 814         if (on)
 815                 vfta |= vid_bit;
 816         else
 817                 vfta &= ~vid_bit;
 818         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
 819
 820         /* update local VFTA copy */
 821         shadow_vfta->vfta[vid_idx] = vfta;
 822
 823         return 0;
 824 }
 825
 826 static void
 827 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 828 {
 829         if (on)
 830                 ixgbe_vlan_hw_strip_enable(dev, queue);
 831         else
 832                 ixgbe_vlan_hw_strip_disable(dev, queue);
 833 }
 834
 835 static void
 836 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
 837 {
 838         struct ixgbe_hw *hw =
 839                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 840
 841         /* Only the high 16-bits is valid */
 842         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
 843 }
 844
 845 static void
 846 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
 847 {
 848         struct ixgbe_hw *hw =
 849                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 850         uint32_t vlnctrl;
 851
 852         PMD_INIT_FUNC_TRACE();
 853
 854         /* Filter Table Disable */
 855         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 856         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
 857
 858         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
 859 }
 860
 861 static void
 862 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 863 {
 864         struct ixgbe_hw *hw =
 865                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 866         struct ixgbe_vfta * shadow_vfta =
 867                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
 868         uint32_t vlnctrl;
 869         uint16_t i;
 870
 871         PMD_INIT_FUNC_TRACE();
 872
 873         /* Filter Table Enable */
 874         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 875         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
 876         vlnctrl |= IXGBE_VLNCTRL_VFE;
 877
 878         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
 879
 880         /* write whatever is in local vfta copy */
 881         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
 882                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
 883 }
 884
 885 static void
 886 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
 887 {
 888         struct ixgbe_hwstrip *hwstrip =
 889                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
 890
 891         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
 892                 return;
 893
 894         if (on)
 895                 IXGBE_SET_HWSTRIP(hwstrip, queue);
 896         else
 897                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
 898 }
 899
 900 static void
 901 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
 902 {
 903         struct ixgbe_hw *hw =
 904                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 905         uint32_t ctrl;
 906
 907         PMD_INIT_FUNC_TRACE();
 908
 909         if (hw->mac.type == ixgbe_mac_82598EB) {
 910                 /* No queue level support */
 911                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
 912                 return;
 913         }
 914         else {
 915                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
 916                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
 917                 ctrl &= ~IXGBE_RXDCTL_VME;
 918                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
 919         }
 920         /* record those setting for HW strip per queue */
 921         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
 922 }
 923
 924 static void
 925 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
 926 {
 927         struct ixgbe_hw *hw =
 928                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 929         uint32_t ctrl;
 930
 931         PMD_INIT_FUNC_TRACE();
 932
 933         if (hw->mac.type == ixgbe_mac_82598EB) {
 934                 /* No queue level supported */
 935                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
 936                 return;
 937         }
 938         else {
 939                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
 940                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
 941                 ctrl |= IXGBE_RXDCTL_VME;
 942                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
 943         }
 944         /* record those setting for HW strip per queue */
 945         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
 946 }
 947
 948 static void
 949 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
 950 {
 951         struct ixgbe_hw *hw =
 952                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 953         uint32_t ctrl;
 954         uint16_t i;
 955
 956         PMD_INIT_FUNC_TRACE();
 957
 958         if (hw->mac.type == ixgbe_mac_82598EB) {
 959                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 960                 ctrl &= ~IXGBE_VLNCTRL_VME;
 961                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
 962         }
 963         else {
 964                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
 965                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 966                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 967                         ctrl &= ~IXGBE_RXDCTL_VME;
 968                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
 969
 970                         /* record those setting for HW strip per queue */
 971                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
 972                 }
 973         }
 974 }
 975
 976 static void
 977 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
 978 {
 979         struct ixgbe_hw *hw =
 980                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 981         uint32_t ctrl;
 982         uint16_t i;
 983
 984         PMD_INIT_FUNC_TRACE();
 985
 986         if (hw->mac.type == ixgbe_mac_82598EB) {
 987                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 988                 ctrl |= IXGBE_VLNCTRL_VME;
 989                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
 990         }
 991         else {
 992                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
 993                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
 994                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 995                         ctrl |= IXGBE_RXDCTL_VME;
 996                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
 997
 998                         /* record those setting for HW strip per queue */
 999                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1000                 }
1001         }
1002 }
1003
1004 static void
1005 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1006 {
1007         struct ixgbe_hw *hw =
1008                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1009         uint32_t ctrl;
1010
1011         PMD_INIT_FUNC_TRACE();
1012
1013         /* DMATXCTRL: Geric Double VLAN Disable */
1014         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1015         ctrl &= ~IXGBE_DMATXCTL_GDV;
1016         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1017
1018         /* CTRL_EXT: Global Double VLAN Disable */
1019         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1020         ctrl &= ~IXGBE_EXTENDED_VLAN;
1021         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1022
1023 }
1024
1025 static void
1026 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1027 {
1028         struct ixgbe_hw *hw =
1029                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030         uint32_t ctrl;
1031
1032         PMD_INIT_FUNC_TRACE();
1033
1034         /* DMATXCTRL: Geric Double VLAN Enable */
1035         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1036         ctrl |= IXGBE_DMATXCTL_GDV;
1037         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1038
1039         /* CTRL_EXT: Global Double VLAN Enable */
1040         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1041         ctrl |= IXGBE_EXTENDED_VLAN;
1042         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1043
1044         /*
1045          * VET EXT field in the EXVET register = 0x8100 by default
1046          * So no need to change. Same to VT field of DMATXCTL register
1047          */
1048 }
1049
1050 static void
1051 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1052 {
1053         if(mask & ETH_VLAN_STRIP_MASK){
1054                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1055                         ixgbe_vlan_hw_strip_enable_all(dev);
1056                 else
1057                         ixgbe_vlan_hw_strip_disable_all(dev);
1058         }
1059
1060         if(mask & ETH_VLAN_FILTER_MASK){
1061                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1062                         ixgbe_vlan_hw_filter_enable(dev);
1063                 else
1064                         ixgbe_vlan_hw_filter_disable(dev);
1065         }
1066
1067         if(mask & ETH_VLAN_EXTEND_MASK){
1068                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1069                         ixgbe_vlan_hw_extend_enable(dev);
1070                 else
1071                         ixgbe_vlan_hw_extend_disable(dev);
1072         }
1073 }
1074
1075 static int
1076 ixgbe_dev_configure(struct rte_eth_dev *dev)
1077 {
1078         struct ixgbe_interrupt *intr =
1079                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1080
1081         PMD_INIT_FUNC_TRACE();
1082
1083         /* set flag to update link status after init */
1084         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1085
1086         return 0;
1087 }
1088
1089 /*
1090  * Configure device link speed and setup link.
1091  * It returns 0 on success.
1092  */
1093 static int
1094 ixgbe_dev_start(struct rte_eth_dev *dev)
1095 {
1096         struct ixgbe_hw *hw =
1097                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1098         int err, link_up = 0, negotiate = 0;
1099         uint32_t speed = 0;
1100         int mask = 0;
1101
1102         PMD_INIT_FUNC_TRACE();
1103
1104         /* IXGBE devices don't support half duplex */
1105         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1106                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1107                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%u) for port %u\n",
1108                                 dev->data->dev_conf.link_duplex,
1109                                 dev->data->port_id);
1110                 return -EINVAL;
1111         }
1112
1113         /* stop adapter */
1114         hw->adapter_stopped = FALSE;
1115         ixgbe_stop_adapter(hw);
1116
1117         /* reinitialize adapter
1118          * this calls reset and start */
1119         ixgbe_init_hw(hw);
1120
1121         /* initialize transmission unit */
1122         ixgbe_dev_tx_init(dev);
1123
1124         /* This can fail when allocating mbufs for descriptor rings */
1125         err = ixgbe_dev_rx_init(dev);
1126         if (err) {
1127                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1128                 goto error;
1129         }
1130
1131         ixgbe_dev_rxtx_start(dev);
1132
1133         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1134                 err = hw->mac.ops.setup_sfp(hw);
1135                 if (err)
1136                         goto error;
1137         }
1138
1139         /* Turn on the laser */
1140         if (hw->phy.multispeed_fiber)
1141                 ixgbe_enable_tx_laser(hw);
1142
1143         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1144         if (err)
1145                 goto error;
1146         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1147         if (err)
1148                 goto error;
1149
1150         switch(dev->data->dev_conf.link_speed) {
1151         case ETH_LINK_SPEED_AUTONEG:
1152                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1153                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1154                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1155                 break;
1156         case ETH_LINK_SPEED_100:
1157                 /*
1158                  * Invalid for 82598 but error will be detected by
1159                  * ixgbe_setup_link()
1160                  */
1161                 speed = IXGBE_LINK_SPEED_100_FULL;
1162                 break;
1163         case ETH_LINK_SPEED_1000:
1164                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1165                 break;
1166         case ETH_LINK_SPEED_10000:
1167                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1168                 break;
1169         default:
1170                 PMD_INIT_LOG(ERR, "Invalid link_speed (%u) for port %u\n",
1171                                 dev->data->dev_conf.link_speed, dev->data->port_id);
1172                 goto error;
1173         }
1174
1175         err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1176         if (err)
1177                 goto error;
1178
1179         /* check if lsc interrupt is enabled */
1180         if (dev->data->dev_conf.intr_conf.lsc != 0) {
1181                 err = ixgbe_dev_interrupt_setup(dev);
1182                 if (err)
1183                         goto error;
1184         }
1185
1186         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1187                 ETH_VLAN_EXTEND_MASK;
1188         ixgbe_vlan_offload_set(dev, mask);
1189
1190         /* Configure DCB hw */
1191         ixgbe_configure_dcb(dev);
1192
1193         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1194                 err = ixgbe_fdir_configure(dev);
1195                 if (err)
1196                         goto error;
1197         }
1198
1199         ixgbe_restore_statistics_mapping(dev);
1200
1201         return (0);
1202
1203 error:
1204         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1205         ixgbe_dev_clear_queues(dev);
1206         return -EIO;
1207 }
1208
1209 /*
1210  * Stop device: disable rx and tx functions to allow for reconfiguring.
1211  */
1212 static void
1213 ixgbe_dev_stop(struct rte_eth_dev *dev)
1214 {
1215         struct rte_eth_link link;
1216         struct ixgbe_hw *hw =
1217                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218
1219         PMD_INIT_FUNC_TRACE();
1220
1221         /* disable interrupts */
1222         ixgbe_disable_intr(hw);
1223
1224         /* reset the NIC */
1225         ixgbe_reset_hw(hw);
1226         hw->adapter_stopped = FALSE;
1227
1228         /* stop adapter */
1229         ixgbe_stop_adapter(hw);
1230
1231         /* Turn off the laser */
1232         if (hw->phy.multispeed_fiber)
1233                 ixgbe_disable_tx_laser(hw);
1234
1235         ixgbe_dev_clear_queues(dev);
1236
1237         /* Clear recorded link status */
1238         memset(&link, 0, sizeof(link));
1239         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1240 }
1241
1242 /*
1243  * Reest and stop device.
1244  */
1245 static void
1246 ixgbe_dev_close(struct rte_eth_dev *dev)
1247 {
1248         struct ixgbe_hw *hw =
1249                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1250
1251         PMD_INIT_FUNC_TRACE();
1252
1253         ixgbe_reset_hw(hw);
1254
1255
1256         ixgbe_dev_stop(dev);
1257         hw->adapter_stopped = 1;
1258
1259         ixgbe_disable_pcie_master(hw);
1260
1261         /* reprogram the RAR[0] in case user changed it. */
1262         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1263 }
1264
1265 /*
1266  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1267  */
1268 static void
1269 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1270 {
1271         struct ixgbe_hw *hw =
1272                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1273         struct ixgbe_hw_stats *hw_stats =
1274                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1275         uint32_t bprc, lxon, lxoff, total;
1276         uint64_t total_missed_rx, total_qbrc, total_qprc;
1277         unsigned i;
1278
1279         total_missed_rx = 0;
1280         total_qbrc = 0;
1281         total_qprc = 0;
1282
1283         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1284         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1285         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1286         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1287
1288         for (i = 0; i < 8; i++) {
1289                 uint32_t mp;
1290                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1291                 /* global total per queue */
1292                 hw_stats->mpc[i] += mp;
1293                 /* Running comprehensive total for stats display */
1294                 total_missed_rx += hw_stats->mpc[i];
1295                 if (hw->mac.type == ixgbe_mac_82598EB)
1296                         hw_stats->rnbc[i] +=
1297                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1298                 hw_stats->pxontxc[i] +=
1299                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1300                 hw_stats->pxonrxc[i] +=
1301                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1302                 hw_stats->pxofftxc[i] +=
1303                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1304                 hw_stats->pxoffrxc[i] +=
1305                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1306                 hw_stats->pxon2offc[i] +=
1307                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1308         }
1309         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1310                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1311                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1312                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1313                 hw_stats->qbrc[i] +=
1314                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1315                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1316                 hw_stats->qbtc[i] +=
1317                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1318                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1319
1320                 total_qprc += hw_stats->qprc[i];
1321                 total_qbrc += hw_stats->qbrc[i];
1322         }
1323         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1324         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1325         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1326
1327         /* Note that gprc counts missed packets */
1328         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1329
1330         if (hw->mac.type != ixgbe_mac_82598EB) {
1331                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1332                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1333                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1334                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1335                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1336                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1337                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1338                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1339         } else {
1340                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1341                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1342                 /* 82598 only has a counter in the high register */
1343                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1344                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1345                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1346         }
1347
1348         /*
1349          * Workaround: mprc hardware is incorrectly counting
1350          * broadcasts, so for now we subtract those.
1351          */
1352         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1353         hw_stats->bprc += bprc;
1354         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1355         if (hw->mac.type == ixgbe_mac_82598EB)
1356                 hw_stats->mprc -= bprc;
1357
1358         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1359         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1360         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1361         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1362         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1363         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1364
1365         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1366         hw_stats->lxontxc += lxon;
1367         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1368         hw_stats->lxofftxc += lxoff;
1369         total = lxon + lxoff;
1370
1371         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1372         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1373         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1374         hw_stats->gptc -= total;
1375         hw_stats->mptc -= total;
1376         hw_stats->ptc64 -= total;
1377         hw_stats->gotc -= total * ETHER_MIN_LEN;
1378
1379         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1380         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1381         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1382         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1383         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1384         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1385         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1386         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1387         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1388         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1389         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1390         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1391         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1392         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1393         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1394         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1395         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1396         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1397         /* Only read FCOE on 82599 */
1398         if (hw->mac.type != ixgbe_mac_82598EB) {
1399                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1400                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1401                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1402                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1403                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1404         }
1405
1406         if (stats == NULL)
1407                 return;
1408
1409         /* Fill out the rte_eth_stats statistics structure */
1410         stats->ipackets = total_qprc;
1411         stats->ibytes = total_qbrc;
1412         stats->opackets = hw_stats->gptc;
1413         stats->obytes = hw_stats->gotc;
1414         stats->imcasts = hw_stats->mprc;
1415
1416         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1417                 stats->q_ipackets[i] = hw_stats->qprc[i];
1418                 stats->q_opackets[i] = hw_stats->qptc[i];
1419                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1420                 stats->q_obytes[i] = hw_stats->qbtc[i];
1421                 stats->q_errors[i] = hw_stats->qprdc[i];
1422         }
1423
1424         /* Rx Errors */
1425         stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1426                 hw_stats->rlec;
1427
1428         stats->oerrors  = 0;
1429
1430         /* Flow Director Stats registers */
1431         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1432         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1433         stats->fdirmatch = hw_stats->fdirmatch;
1434         stats->fdirmiss = hw_stats->fdirmiss;
1435 }
1436
1437 static void
1438 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1439 {
1440         struct ixgbe_hw_stats *stats =
1441                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1442
1443         /* HW registers are cleared on read */
1444         ixgbe_dev_stats_get(dev, NULL);
1445
1446         /* Reset software totals */
1447         memset(stats, 0, sizeof(*stats));
1448 }
1449
1450 static void
1451 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1452 {
1453         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1454         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1455                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1456
1457         /* Good Rx packet, include VF loopback */
1458         UPDATE_VF_STAT(IXGBE_VFGPRC,
1459             hw_stats->last_vfgprc, hw_stats->vfgprc);
1460
1461         /* Good Rx octets, include VF loopback */
1462         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1463             hw_stats->last_vfgorc, hw_stats->vfgorc);
1464
1465         /* Good Tx packet, include VF loopback */
1466         UPDATE_VF_STAT(IXGBE_VFGPTC,
1467             hw_stats->last_vfgptc, hw_stats->vfgptc);
1468
1469         /* Good Tx octets, include VF loopback */
1470         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1471             hw_stats->last_vfgotc, hw_stats->vfgotc);
1472
1473         /* Rx Multicst Packet */
1474         UPDATE_VF_STAT(IXGBE_VFMPRC,
1475             hw_stats->last_vfmprc, hw_stats->vfmprc);
1476
1477         if (stats == NULL)
1478                 return;
1479
1480         memset(stats, 0, sizeof(*stats));
1481         stats->ipackets = hw_stats->vfgprc;
1482         stats->ibytes = hw_stats->vfgorc;
1483         stats->opackets = hw_stats->vfgptc;
1484         stats->obytes = hw_stats->vfgotc;
1485         stats->imcasts = hw_stats->vfmprc;
1486 }
1487
1488 static void
1489 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1490 {
1491         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1492                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1493
1494         /* Sync HW register to the last stats */
1495         ixgbevf_dev_stats_get(dev, NULL);
1496
1497         /* reset HW current stats*/
1498         hw_stats->vfgprc = 0;
1499         hw_stats->vfgorc = 0;
1500         hw_stats->vfgptc = 0;
1501         hw_stats->vfgotc = 0;
1502         hw_stats->vfmprc = 0;
1503
1504 }
1505
1506 static void
1507 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1508 {
1509         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1510
1511         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1512         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1513         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1514         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1515         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1516 }
1517
1518 /* return 0 means link status changed, -1 means not changed */
1519 static int
1520 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1521 {
1522         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1523         struct rte_eth_link link, old;
1524         ixgbe_link_speed link_speed;
1525         int link_up;
1526         int diag;
1527
1528         link.link_status = 0;
1529         link.link_speed = 0;
1530         link.link_duplex = 0;
1531         memset(&old, 0, sizeof(old));
1532         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1533
1534         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1535         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1536                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1537         else
1538                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1539         if (diag != 0) {
1540                 link.link_speed = ETH_LINK_SPEED_100;
1541                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1542                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1543                 if (link.link_status == old.link_status)
1544                         return -1;
1545                 return 0;
1546         }
1547
1548         if (link_up == 0) {
1549                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1550                 if (link.link_status == old.link_status)
1551                         return -1;
1552                 return 0;
1553         }
1554         link.link_status = 1;
1555         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1556
1557         switch (link_speed) {
1558         default:
1559         case IXGBE_LINK_SPEED_UNKNOWN:
1560                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1561                 link.link_speed = ETH_LINK_SPEED_100;
1562                 break;
1563
1564         case IXGBE_LINK_SPEED_100_FULL:
1565                 link.link_speed = ETH_LINK_SPEED_100;
1566                 break;
1567
1568         case IXGBE_LINK_SPEED_1GB_FULL:
1569                 link.link_speed = ETH_LINK_SPEED_1000;
1570                 break;
1571
1572         case IXGBE_LINK_SPEED_10GB_FULL:
1573                 link.link_speed = ETH_LINK_SPEED_10000;
1574                 break;
1575         }
1576         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1577
1578         if (link.link_status == old.link_status)
1579                 return -1;
1580
1581         return 0;
1582 }
1583
1584 static void
1585 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1586 {
1587         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1588         uint32_t fctrl;
1589
1590         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1591         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1592         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1593 }
1594
1595 static void
1596 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1597 {
1598         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599         uint32_t fctrl;
1600
1601         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1602         fctrl &= (~IXGBE_FCTRL_UPE);
1603         if (dev->data->all_multicast == 1)
1604                 fctrl |= IXGBE_FCTRL_MPE;
1605         else
1606                 fctrl &= (~IXGBE_FCTRL_MPE);
1607         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1608 }
1609
1610 static void
1611 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1612 {
1613         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614         uint32_t fctrl;
1615
1616         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1617         fctrl |= IXGBE_FCTRL_MPE;
1618         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1619 }
1620
1621 static void
1622 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1623 {
1624         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1625         uint32_t fctrl;
1626
1627         if (dev->data->promiscuous == 1)
1628                 return; /* must remain in all_multicast mode */
1629
1630         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1631         fctrl &= (~IXGBE_FCTRL_MPE);
1632         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1633 }
1634
1635 /**
1636  * It clears the interrupt causes and enables the interrupt.
1637  * It will be called once only during nic initialized.
1638  *
1639  * @param dev
1640  *  Pointer to struct rte_eth_dev.
1641  *
1642  * @return
1643  *  - On success, zero.
1644  *  - On failure, a negative value.
1645  */
1646 static int
1647 ixgbe_dev_interrupt_setup(struct rte_eth_dev *dev)
1648 {
1649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1650
1651         ixgbe_dev_link_status_print(dev);
1652         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EICR_LSC);
1653         IXGBE_WRITE_FLUSH(hw);
1654         rte_intr_enable(&(dev->pci_dev->intr_handle));
1655
1656         return 0;
1657 }
1658
1659 /*
1660  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1661  *
1662  * @param dev
1663  *  Pointer to struct rte_eth_dev.
1664  *
1665  * @return
1666  *  - On success, zero.
1667  *  - On failure, a negative value.
1668  */
1669 static int
1670 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1671 {
1672         uint32_t eicr;
1673         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674         struct ixgbe_interrupt *intr =
1675                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1676
1677         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EICR_LSC);
1678         IXGBE_WRITE_FLUSH(hw);
1679
1680         /* read-on-clear nic registers here */
1681         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1682         PMD_INIT_LOG(INFO, "eicr %x", eicr);
1683         if (eicr & IXGBE_EICR_LSC) {
1684                 /* set flag for async link update */
1685                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1686         }
1687
1688         return 0;
1689 }
1690
1691 /**
1692  * It gets and then prints the link status.
1693  *
1694  * @param dev
1695  *  Pointer to struct rte_eth_dev.
1696  *
1697  * @return
1698  *  - On success, zero.
1699  *  - On failure, a negative value.
1700  */
1701 static void
1702 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1703 {
1704         struct rte_eth_link link;
1705
1706         memset(&link, 0, sizeof(link));
1707         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1708         if (link.link_status) {
1709                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1710                                         (int)(dev->data->port_id),
1711                                         (unsigned)link.link_speed,
1712                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1713                                         "full-duplex" : "half-duplex");
1714         } else {
1715                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1716                                 (int)(dev->data->port_id));
1717         }
1718         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1719                                 dev->pci_dev->addr.domain,
1720                                 dev->pci_dev->addr.bus,
1721                                 dev->pci_dev->addr.devid,
1722                                 dev->pci_dev->addr.function);
1723 }
1724
1725 /*
1726  * It executes link_update after knowing an interrupt occured.
1727  *
1728  * @param dev
1729  *  Pointer to struct rte_eth_dev.
1730  *
1731  * @return
1732  *  - On success, zero.
1733  *  - On failure, a negative value.
1734  */
1735 static int
1736 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1737 {
1738         struct ixgbe_interrupt *intr =
1739                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1740
1741         if (!(intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
1742                 return -1;
1743         }
1744         ixgbe_dev_link_update(dev, 0);
1745
1746         return 0;
1747 }
1748
1749 /**
1750  * Interrupt handler which shall be registered for alarm callback for delayed
1751  * handling specific interrupt to wait for the stable nic state. As the
1752  * NIC interrupt state is not stable for ixgbe after link is just down,
1753  * it needs to wait 4 seconds to get the stable status.
1754  *
1755  * @param handle
1756  *  Pointer to interrupt handle.
1757  * @param param
1758  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1759  *
1760  * @return
1761  *  void
1762  */
1763 static void
1764 ixgbe_dev_interrupt_delayed_handler(void *param)
1765 {
1766         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1767         struct ixgbe_interrupt *intr =
1768                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1769         struct ixgbe_hw *hw =
1770                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771
1772         IXGBE_READ_REG(hw, IXGBE_EICR);
1773         ixgbe_dev_interrupt_action(dev);
1774         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1775                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
1776                 rte_intr_enable(&(dev->pci_dev->intr_handle));
1777                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EICR_LSC);
1778                 IXGBE_WRITE_FLUSH(hw);
1779                 ixgbe_dev_link_status_print(dev);
1780                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1781         }
1782 }
1783
1784 /**
1785  * Interrupt handler triggered by NIC  for handling
1786  * specific interrupt.
1787  *
1788  * @param handle
1789  *  Pointer to interrupt handle.
1790  * @param param
1791  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1792  *
1793  * @return
1794  *  void
1795  */
1796 static void
1797 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1798                                                         void *param)
1799 {
1800         int64_t timeout;
1801         struct rte_eth_link link;
1802         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1803         struct ixgbe_interrupt *intr =
1804                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1805
1806         /* get the link status before link update, for predicting later */
1807         memset(&link, 0, sizeof(link));
1808         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1809         ixgbe_dev_interrupt_get_status(dev);
1810         ixgbe_dev_interrupt_action(dev);
1811
1812         if (!(intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
1813                 return;
1814
1815         /* likely to up */
1816         if (!link.link_status)
1817                 /* handle it 1 sec later, wait it being stable */
1818                 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
1819         /* likely to down */
1820         else
1821                 /* handle it 4 sec later, wait it being stable */
1822                 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
1823
1824         ixgbe_dev_link_status_print(dev);
1825         if (rte_eal_alarm_set(timeout * 1000,
1826                 ixgbe_dev_interrupt_delayed_handler, param) < 0)
1827                 PMD_INIT_LOG(ERR, "Error setting alarm");
1828 }
1829
1830 static int
1831 ixgbe_dev_led_on(struct rte_eth_dev *dev)
1832 {
1833         struct ixgbe_hw *hw;
1834
1835         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
1837 }
1838
1839 static int
1840 ixgbe_dev_led_off(struct rte_eth_dev *dev)
1841 {
1842         struct ixgbe_hw *hw;
1843
1844         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
1846 }
1847
1848 static int
1849 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1850 {
1851         struct ixgbe_hw *hw;
1852         int err;
1853         uint32_t rx_buf_size;
1854         uint32_t max_high_water;
1855         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
1856                 ixgbe_fc_none,
1857                 ixgbe_fc_rx_pause,
1858                 ixgbe_fc_tx_pause,
1859                 ixgbe_fc_full
1860         };
1861
1862         PMD_INIT_FUNC_TRACE();
1863
1864         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1865         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
1866         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1867
1868         /*
1869          * At least reserve one Ethernet frame for watermark
1870          * high_water/low_water in kilo bytes for ixgbe
1871          */
1872         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
1873         if ((fc_conf->high_water > max_high_water) ||
1874                 (fc_conf->high_water < fc_conf->low_water)) {
1875                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
1876                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
1877                 return (-EINVAL);
1878         }
1879
1880         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
1881         hw->fc.pause_time     = fc_conf->pause_time;
1882         hw->fc.high_water[0]  = fc_conf->high_water;
1883         hw->fc.low_water[0]   = fc_conf->low_water;
1884         hw->fc.send_xon       = fc_conf->send_xon;
1885
1886         err = ixgbe_fc_enable(hw);
1887         /* Not negotiated is not an error case */
1888         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
1889                 return 0;
1890         }
1891
1892         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
1893         return -EIO;
1894 }
1895
1896 /**
1897  *  ixgbe_pfc_enable_generic - Enable flow control
1898  *  @hw: pointer to hardware structure
1899  *  @tc_num: traffic class number
1900  *  Enable flow control according to the current settings.
1901  */
1902 static int
1903 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
1904 {
1905         int ret_val = 0;
1906         uint32_t mflcn_reg, fccfg_reg;
1907         uint32_t reg;
1908         uint32_t fcrtl, fcrth;
1909         uint8_t i;
1910         uint8_t nb_rx_en;
1911
1912         /* Validate the water mark configuration */
1913         if (!hw->fc.pause_time) {
1914                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1915                 goto out;
1916         }
1917
1918         /* Low water mark of zero causes XOFF floods */
1919         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1920                  /* High/Low water can not be 0 */
1921                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
1922                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
1923                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1924                         goto out;
1925                 }
1926
1927                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
1928                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
1929                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1930                         goto out;
1931                 }
1932         }
1933         /* Negotiate the fc mode to use */
1934         ixgbe_fc_autoneg(hw);
1935
1936         /* Disable any previous flow control settings */
1937         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1938         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
1939
1940         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1941         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1942
1943         switch (hw->fc.current_mode) {
1944         case ixgbe_fc_none:
1945                 /*
1946                  * If the count of enabled RX Priority Flow control >1,
1947                  * and the TX pause can not be disabled
1948                  */
1949                 nb_rx_en = 0;
1950                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1951                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
1952                         if (reg & IXGBE_FCRTH_FCEN)
1953                                 nb_rx_en++;
1954                 }
1955                 if (nb_rx_en > 1)
1956                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
1957                 break;
1958         case ixgbe_fc_rx_pause:
1959                 /*
1960                  * Rx Flow control is enabled and Tx Flow control is
1961                  * disabled by software override. Since there really
1962                  * isn't a way to advertise that we are capable of RX
1963                  * Pause ONLY, we will advertise that we support both
1964                  * symmetric and asymmetric Rx PAUSE.  Later, we will
1965                  * disable the adapter's ability to send PAUSE frames.
1966                  */
1967                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
1968                 /*
1969                  * If the count of enabled RX Priority Flow control >1,
1970                  * and the TX pause can not be disabled
1971                  */
1972                 nb_rx_en = 0;
1973                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1974                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
1975                         if (reg & IXGBE_FCRTH_FCEN)
1976                                 nb_rx_en++;
1977                 }
1978                 if (nb_rx_en > 1)
1979                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
1980                 break;
1981         case ixgbe_fc_tx_pause:
1982                 /*
1983                  * Tx Flow control is enabled, and Rx Flow control is
1984                  * disabled by software override.
1985                  */
1986                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
1987                 break;
1988         case ixgbe_fc_full:
1989                 /* Flow control (both Rx and Tx) is enabled by SW override. */
1990                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
1991                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
1992                 break;
1993         default:
1994                 DEBUGOUT("Flow control param set incorrectly\n");
1995                 ret_val = IXGBE_ERR_CONFIG;
1996                 goto out;
1997                 break;
1998         }
1999
2000         /* Set 802.3x based flow control settings. */
2001         mflcn_reg |= IXGBE_MFLCN_DPF;
2002         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2003         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2004
2005         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2006         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2007                 hw->fc.high_water[tc_num]) {
2008                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2009                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2010                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2011         } else {
2012                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2013                 /*
2014                  * In order to prevent Tx hangs when the internal Tx
2015                  * switch is enabled we must set the high water mark
2016                  * to the maximum FCRTH value.  This allows the Tx
2017                  * switch to function even under heavy Rx workloads.
2018                  */
2019                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2020         }
2021         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2022
2023         /* Configure pause time (2 TCs per register) */
2024         reg = hw->fc.pause_time * 0x00010001;
2025         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2026                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2027
2028         /* Configure flow control refresh threshold value */
2029         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2030
2031 out:
2032         return ret_val;
2033 }
2034
2035 static int
2036 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2037 {
2038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2039         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2040
2041         if(hw->mac.type != ixgbe_mac_82598EB) {
2042                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2043         }
2044         return ret_val;
2045 }
2046
2047 static int
2048 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2049 {
2050         int err;
2051         uint32_t rx_buf_size;
2052         uint32_t max_high_water;
2053         uint8_t tc_num;
2054         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2055         struct ixgbe_hw *hw =
2056                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057         struct ixgbe_dcb_config *dcb_config =
2058                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2059
2060         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2061                 ixgbe_fc_none,
2062                 ixgbe_fc_rx_pause,
2063                 ixgbe_fc_tx_pause,
2064                 ixgbe_fc_full
2065         };
2066
2067         PMD_INIT_FUNC_TRACE();
2068
2069         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2070         tc_num = map[pfc_conf->priority];
2071         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2072         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2073         /*
2074          * At least reserve one Ethernet frame for watermark
2075          * high_water/low_water in kilo bytes for ixgbe
2076          */
2077         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2078         if ((pfc_conf->fc.high_water > max_high_water) ||
2079                 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2080                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2081                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2082                 return (-EINVAL);
2083         }
2084
2085         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2086         hw->fc.pause_time = pfc_conf->fc.pause_time;
2087         hw->fc.send_xon = pfc_conf->fc.send_xon;
2088         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2089         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2090
2091         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2092
2093         /* Not negotiated is not an error case */
2094         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2095                 return 0;
2096
2097         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2098         return -EIO;
2099 }
2100
2101 static void
2102 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2103                                 uint32_t index, uint32_t pool)
2104 {
2105         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106         uint32_t enable_addr = 1;
2107
2108         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2109 }
2110
2111 static void
2112 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2113 {
2114         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2115
2116         ixgbe_clear_rar(hw, index);
2117 }
2118
2119 /*
2120  * Virtual Function operations
2121  */
2122 static void
2123 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2124 {
2125         PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2126
2127         /* Clear interrupt mask to stop from interrupts being generated */
2128         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2129
2130         IXGBE_WRITE_FLUSH(hw);
2131 }
2132
2133 static int
2134 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2135 {
2136         struct rte_eth_conf* conf = &dev->data->dev_conf;
2137
2138         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2139                 dev->data->port_id);
2140
2141         /*
2142          * VF has no ability to enable/disable HW CRC
2143          * Keep the persistent behavior the same as Host PF
2144          */
2145 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2146         if (!conf->rxmode.hw_strip_crc) {
2147                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2148                 conf->rxmode.hw_strip_crc = 1;
2149         }
2150 #else
2151         if (conf->rxmode.hw_strip_crc) {
2152                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2153                 conf->rxmode.hw_strip_crc = 0;
2154         }
2155 #endif
2156
2157         return 0;
2158 }
2159
2160 static int
2161 ixgbevf_dev_start(struct rte_eth_dev *dev)
2162 {
2163         int err, mask = 0;
2164
2165         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2166
2167         ixgbevf_dev_tx_init(dev);
2168
2169         /* This can fail when allocating mbufs for descriptor rings */
2170         err = ixgbevf_dev_rx_init(dev);
2171         if (err) {
2172                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2173                 ixgbe_dev_clear_queues(dev);
2174                 return err;
2175         }
2176
2177         /* Set vfta */
2178         ixgbevf_set_vfta_all(dev,1);
2179
2180         /* Set HW strip */
2181         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2182                 ETH_VLAN_EXTEND_MASK;
2183         ixgbevf_vlan_offload_set(dev, mask);
2184
2185         ixgbevf_dev_rxtx_start(dev);
2186
2187         return 0;
2188 }
2189
2190 static void
2191 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2192 {
2193         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2194
2195         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2196
2197         hw->adapter_stopped = TRUE;
2198         ixgbe_stop_adapter(hw);
2199
2200         /*
2201           * Clear what we set, but we still keep shadow_vfta to
2202           * restore after device starts
2203           */
2204         ixgbevf_set_vfta_all(dev,0);
2205
2206         ixgbe_dev_clear_queues(dev);
2207 }
2208
2209 static void
2210 ixgbevf_dev_close(struct rte_eth_dev *dev)
2211 {
2212         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2213
2214         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2215
2216         ixgbe_reset_hw(hw);
2217
2218         ixgbevf_dev_stop(dev);
2219
2220         /* reprogram the RAR[0] in case user changed it. */
2221         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2222 }
2223
2224 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2225 {
2226         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227         struct ixgbe_vfta * shadow_vfta =
2228                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2229         int i = 0, j = 0, vfta = 0, mask = 1;
2230
2231         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2232                 vfta = shadow_vfta->vfta[i];
2233                 if(vfta){
2234                         mask = 1;
2235                         for (j = 0; j < 32; j++){
2236                                 if(vfta & mask)
2237                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2238                                 mask<<=1;
2239                         }
2240                 }
2241         }
2242
2243 }
2244
2245 static int
2246 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2247 {
2248         struct ixgbe_hw *hw =
2249                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250         struct ixgbe_vfta * shadow_vfta =
2251                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2252         uint32_t vid_idx = 0;
2253         uint32_t vid_bit = 0;
2254         int ret = 0;
2255
2256         PMD_INIT_FUNC_TRACE();
2257
2258         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2259         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2260         if(ret){
2261                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2262                 return ret;
2263         }
2264         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2265         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2266
2267         /* Save what we set and retore it after device reset */
2268         if (on)
2269                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2270         else
2271                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2272
2273         return 0;
2274 }
2275
2276 static void
2277 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2278 {
2279         struct ixgbe_hw *hw =
2280                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2281         uint32_t ctrl;
2282
2283         PMD_INIT_FUNC_TRACE();
2284
2285         if(queue >= hw->mac.max_rx_queues)
2286                 return;
2287
2288         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2289         if(on)
2290                 ctrl |= IXGBE_RXDCTL_VME;
2291         else
2292                 ctrl &= ~IXGBE_RXDCTL_VME;
2293         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2294
2295         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2296 }
2297
2298 static void
2299 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2300 {
2301         struct ixgbe_hw *hw =
2302                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2303         uint16_t i;
2304         int on = 0;
2305
2306         /* VF function only support hw strip feature, others are not support */
2307         if(mask & ETH_VLAN_STRIP_MASK){
2308                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2309
2310                 for(i=0; i < hw->mac.max_rx_queues; i++)
2311                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2312         }
2313 }