lib/librte_pmd_ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_tailq.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61
  62 #include "ixgbe_logs.h"
  63 #include "ixgbe/ixgbe_api.h"
  64 #include "ixgbe/ixgbe_vf.h"
  65 #include "ixgbe/ixgbe_common.h"
  66 #include "ixgbe_ethdev.h"
  67 #include "ixgbe_bypass.h"
  68
  69 /*
  70  * High threshold controlling when to start sending XOFF frames. Must be at
  71  * least 8 bytes less than receive packet buffer size. This value is in units
  72  * of 1024 bytes.
  73  */
  74 #define IXGBE_FC_HI    0x80
  75
  76 /*
  77  * Low threshold controlling when to start sending XON frames. This value is
  78  * in units of 1024 bytes.
  79  */
  80 #define IXGBE_FC_LO    0x40
  81
  82 /* Timer value included in XOFF frames. */
  83 #define IXGBE_FC_PAUSE 0x680
  84
  85 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  86 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  87 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  88
  89
  90 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  91
  92 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  93
  94 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
  95                 struct rte_eth_dev *eth_dev);
  96 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
  97 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
  98 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
  99 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 100 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 101 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 102 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 103 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 104 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 105                                 int wait_to_complete);
 106 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 107                                 struct rte_eth_stats *stats);
 108 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 109 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 110                                              uint16_t queue_id,
 111                                              uint8_t stat_idx,
 112                                              uint8_t is_rx);
 113 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 114                                 struct rte_eth_dev_info *dev_info);
 115 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 116                 uint16_t vlan_id, int on);
 117 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 118 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 119                 uint16_t queue, bool on);
 120 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 121                 int on);
 122 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 123 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 124 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 125 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 126 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 127
 128 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 129 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 130 static int  ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 131                 struct rte_eth_fc_conf *fc_conf);
 132 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 133                 struct rte_eth_pfc_conf *pfc_conf);
 134 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 135                 struct rte_eth_rss_reta *reta_conf);
 136 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 137                 struct rte_eth_rss_reta *reta_conf);
 138 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 139 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 140 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 141 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 143                 void *param);
 144 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 145 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 146                 uint32_t index, uint32_t pool);
 147 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 148 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 149
 150 /* For Virtual Function support */
 151 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
 152                 struct rte_eth_dev *eth_dev);
 153 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 154 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 155 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 156 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 157 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 158 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 159                 struct rte_eth_stats *stats);
 160 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 161 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 162                 uint16_t vlan_id, int on);
 163 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 164                 uint16_t queue, int on);
 165 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 166 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 167
 168 /* For Eth VMDQ APIs support */
 169 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 170                 ether_addr* mac_addr,uint8_t on);
 171 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 172 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 173                 uint16_t rx_mask, uint8_t on);
 174 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 175 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 176 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 177                 uint64_t pool_mask,uint8_t vlan_on);
 178 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 179                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 180                 uint8_t rule_id, uint8_t on);
 181 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 182                 uint8_t rule_id);
 183
 184 /*
 185  * Define VF Stats MACRO for Non "cleared on read" register
 186  */
 187 #define UPDATE_VF_STAT(reg, last, cur)                          \
 188 {                                                               \
 189         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 190         cur += latest - last;                                   \
 191         last = latest;                                          \
 192 }
 193
 194 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 195 {                                                                \
 196         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 197         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 198         u64 latest = ((new_msb << 32) | new_lsb);                \
 199         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 200         last = latest;                                           \
 201 }
 202
 203 #define IXGBE_SET_HWSTRIP(h, q) do{\
 204                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 205                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 206                 (h)->bitmap[idx] |= 1 << bit;\
 207         }while(0)
 208
 209 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 210                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 211                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 212                 (h)->bitmap[idx] &= ~(1 << bit);\
 213         }while(0)
 214
 215 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 216                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 217                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 218                 (r) = (h)->bitmap[idx] >> bit & 1;\
 219         }while(0)
 220
 221 /*
 222  * The set of PCI devices this driver supports
 223  */
 224 static struct rte_pci_id pci_id_ixgbe_map[] = {
 225
 226 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 227 #include "rte_pci_dev_ids.h"
 228
 229 { .vendor_id = 0, /* sentinel */ },
 230 };
 231
 232
 233 /*
 234  * The set of PCI devices this driver supports (for 82599 VF)
 235  */
 236 static struct rte_pci_id pci_id_ixgbevf_map[] = {
 237
 238 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 239 #include "rte_pci_dev_ids.h"
 240 { .vendor_id = 0, /* sentinel */ },
 241
 242 };
 243
 244 static struct eth_dev_ops ixgbe_eth_dev_ops = {
 245         .dev_configure        = ixgbe_dev_configure,
 246         .dev_start            = ixgbe_dev_start,
 247         .dev_stop             = ixgbe_dev_stop,
 248         .dev_close            = ixgbe_dev_close,
 249         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 250         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 251         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 252         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 253         .link_update          = ixgbe_dev_link_update,
 254         .stats_get            = ixgbe_dev_stats_get,
 255         .stats_reset          = ixgbe_dev_stats_reset,
 256         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 257         .dev_infos_get        = ixgbe_dev_info_get,
 258         .vlan_filter_set      = ixgbe_vlan_filter_set,
 259         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 260         .vlan_offload_set     = ixgbe_vlan_offload_set,
 261         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 262         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 263         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 264         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 265         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 266         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 267         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 268         .dev_led_on           = ixgbe_dev_led_on,
 269         .dev_led_off          = ixgbe_dev_led_off,
 270         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 271         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 272         .mac_addr_add         = ixgbe_add_rar,
 273         .mac_addr_remove      = ixgbe_remove_rar,
 274         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 275         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 276         .mirror_rule_set        = ixgbe_mirror_rule_set,
 277         .mirror_rule_reset      = ixgbe_mirror_rule_reset,
 278         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 279         .set_vf_rx            = ixgbe_set_pool_rx,
 280         .set_vf_tx            = ixgbe_set_pool_tx,
 281         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 282         .fdir_add_signature_filter    = ixgbe_fdir_add_signature_filter,
 283         .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
 284         .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
 285         .fdir_infos_get               = ixgbe_fdir_info_get,
 286         .fdir_add_perfect_filter      = ixgbe_fdir_add_perfect_filter,
 287         .fdir_update_perfect_filter   = ixgbe_fdir_update_perfect_filter,
 288         .fdir_remove_perfect_filter   = ixgbe_fdir_remove_perfect_filter,
 289         .fdir_set_masks               = ixgbe_fdir_set_masks,
 290         .reta_update          = ixgbe_dev_rss_reta_update,
 291         .reta_query           = ixgbe_dev_rss_reta_query,
 292 #ifdef RTE_NIC_BYPASS
 293         .bypass_init          = ixgbe_bypass_init,
 294         .bypass_state_set     = ixgbe_bypass_state_store,
 295         .bypass_state_show    = ixgbe_bypass_state_show,
 296         .bypass_event_set     = ixgbe_bypass_event_store,
 297         .bypass_event_show    = ixgbe_bypass_event_show,
 298         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 299         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 300         .bypass_ver_show      = ixgbe_bypass_ver_show,
 301         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 302 #endif /* RTE_NIC_BYPASS */
 303 };
 304
 305 /*
 306  * dev_ops for virtual function, bare necessities for basic vf
 307  * operation have been implemented
 308  */
 309 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
 310
 311         .dev_configure        = ixgbevf_dev_configure,
 312         .dev_start            = ixgbevf_dev_start,
 313         .dev_stop             = ixgbevf_dev_stop,
 314         .link_update          = ixgbe_dev_link_update,
 315         .stats_get            = ixgbevf_dev_stats_get,
 316         .stats_reset          = ixgbevf_dev_stats_reset,
 317         .dev_close            = ixgbevf_dev_close,
 318         .dev_infos_get        = ixgbe_dev_info_get,
 319         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 320         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 321         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 322         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 323         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 324         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 325         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 326 };
 327
 328 /**
 329  * Atomically reads the link status information from global
 330  * structure rte_eth_dev.
 331  *
 332  * @param dev
 333  *   - Pointer to the structure rte_eth_dev to read from.
 334  *   - Pointer to the buffer to be saved with the link status.
 335  *
 336  * @return
 337  *   - On success, zero.
 338  *   - On failure, negative value.
 339  */
 340 static inline int
 341 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 342                                 struct rte_eth_link *link)
 343 {
 344         struct rte_eth_link *dst = link;
 345         struct rte_eth_link *src = &(dev->data->dev_link);
 346
 347         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 348                                         *(uint64_t *)src) == 0)
 349                 return -1;
 350
 351         return 0;
 352 }
 353
 354 /**
 355  * Atomically writes the link status information into global
 356  * structure rte_eth_dev.
 357  *
 358  * @param dev
 359  *   - Pointer to the structure rte_eth_dev to read from.
 360  *   - Pointer to the buffer to be saved with the link status.
 361  *
 362  * @return
 363  *   - On success, zero.
 364  *   - On failure, negative value.
 365  */
 366 static inline int
 367 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 368                                 struct rte_eth_link *link)
 369 {
 370         struct rte_eth_link *dst = &(dev->data->dev_link);
 371         struct rte_eth_link *src = link;
 372
 373         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 374                                         *(uint64_t *)src) == 0)
 375                 return -1;
 376
 377         return 0;
 378 }
 379
 380 /*
 381  * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
 382  */
 383 static inline int
 384 ixgbe_is_sfp(struct ixgbe_hw *hw)
 385 {
 386         switch (hw->phy.type) {
 387         case ixgbe_phy_sfp_avago:
 388         case ixgbe_phy_sfp_ftl:
 389         case ixgbe_phy_sfp_intel:
 390         case ixgbe_phy_sfp_unknown:
 391         case ixgbe_phy_sfp_passive_tyco:
 392         case ixgbe_phy_sfp_passive_unknown:
 393                 return 1;
 394         default:
 395                 return 0;
 396         }
 397 }
 398
 399 static inline int32_t
 400 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 401 {
 402         uint32_t ctrl_ext;
 403         int32_t status;
 404
 405         status = ixgbe_reset_hw(hw);
 406
 407         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 408         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 409         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 410         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 411         IXGBE_WRITE_FLUSH(hw);
 412
 413         return status;
 414 }
 415
 416 static inline void
 417 ixgbe_enable_intr(struct rte_eth_dev *dev)
 418 {
 419         struct ixgbe_interrupt *intr =
 420                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 421         struct ixgbe_hw *hw =
 422                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 423
 424         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 425         IXGBE_WRITE_FLUSH(hw);
 426 }
 427
 428 /*
 429  * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
 430  */
 431 static void
 432 ixgbe_disable_intr(struct ixgbe_hw *hw)
 433 {
 434         PMD_INIT_FUNC_TRACE();
 435
 436         if (hw->mac.type == ixgbe_mac_82598EB) {
 437                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 438         } else {
 439                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 440                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 441                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 442         }
 443         IXGBE_WRITE_FLUSH(hw);
 444 }
 445
 446 /*
 447  * This function resets queue statistics mapping registers.
 448  * From Niantic datasheet, Initialization of Statistics section:
 449  * "...if software requires the queue counters, the RQSMR and TQSM registers
 450  * must be re-programmed following a device reset.
 451  */
 452 static void
 453 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 454 {
 455         uint32_t i;
 456
 457         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 458                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 459                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 460         }
 461 }
 462
 463
 464 static int
 465 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 466                                   uint16_t queue_id,
 467                                   uint8_t stat_idx,
 468                                   uint8_t is_rx)
 469 {
 470 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 471 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 472 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 473
 474         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 475         struct ixgbe_stat_mapping_registers *stat_mappings =
 476                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 477         uint32_t qsmr_mask = 0;
 478         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 479         uint32_t q_map;
 480         uint8_t n, offset;
 481
 482         if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
 483                 return -ENOSYS;
 484
 485         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
 486                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
 487
 488         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 489         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 490                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
 491                 return -EIO;
 492         }
 493         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 494
 495         /* Now clear any previous stat_idx set */
 496         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 497         if (!is_rx)
 498                 stat_mappings->tqsm[n] &= ~clearing_mask;
 499         else
 500                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 501
 502         q_map = (uint32_t)stat_idx;
 503         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 504         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 505         if (!is_rx)
 506                 stat_mappings->tqsm[n] |= qsmr_mask;
 507         else
 508                 stat_mappings->rqsmr[n] |= qsmr_mask;
 509
 510         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
 511                      "%s[%d] = 0x%08x\n",
 512                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
 513                      is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 514
 515         /* Now write the mapping in the appropriate register */
 516         if (is_rx) {
 517                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
 518                              stat_mappings->rqsmr[n], n);
 519                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 520         }
 521         else {
 522                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
 523                              stat_mappings->tqsm[n], n);
 524                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 525         }
 526         return 0;
 527 }
 528
 529 static void
 530 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 531 {
 532         struct ixgbe_stat_mapping_registers *stat_mappings =
 533                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 534         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 535         int i;
 536
 537         /* write whatever was in stat mapping table to the NIC */
 538         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 539                 /* rx */
 540                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 541
 542                 /* tx */
 543                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 544         }
 545 }
 546
 547 static void
 548 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 549 {
 550         uint8_t i;
 551         struct ixgbe_dcb_tc_config *tc;
 552         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 553
 554         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 555         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 556         for (i = 0; i < dcb_max_tc; i++) {
 557                 tc = &dcb_config->tc_config[i];
 558                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 559                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 560                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 561                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 562                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 563                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 564                 tc->pfc = ixgbe_dcb_pfc_disabled;
 565         }
 566
 567         /* Initialize default user to priority mapping, UPx->TC0 */
 568         tc = &dcb_config->tc_config[0];
 569         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 570         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 571         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 572                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 573                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 574         }
 575         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 576         dcb_config->pfc_mode_enable = false;
 577         dcb_config->vt_mode = true;
 578         dcb_config->round_robin_enable = false;
 579         /* support all DCB capabilities in 82599 */
 580         dcb_config->support.capabilities = 0xFF;
 581
 582         /*we only support 4 Tcs for X540*/
 583         if (hw->mac.type == ixgbe_mac_X540) {
 584                 dcb_config->num_tcs.pg_tcs = 4;
 585                 dcb_config->num_tcs.pfc_tcs = 4;
 586         }
 587 }
 588
 589 /*
 590  * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
 591  * It returns 0 on success.
 592  */
 593 static int
 594 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 595                      struct rte_eth_dev *eth_dev)
 596 {
 597         struct rte_pci_device *pci_dev;
 598         struct ixgbe_hw *hw =
 599                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 600         struct ixgbe_vfta * shadow_vfta =
 601                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 602         struct ixgbe_hwstrip *hwstrip =
 603                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 604         struct ixgbe_dcb_config *dcb_config =
 605                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 606         uint32_t ctrl_ext;
 607         uint16_t csum;
 608         int diag, i;
 609
 610         PMD_INIT_FUNC_TRACE();
 611
 612         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 613         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 614         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 615
 616         /* for secondary processes, we don't initialise any further as primary
 617          * has already done this work. Only check we don't need a different
 618          * RX function */
 619         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 620                 if (eth_dev->data->scattered_rx)
 621                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 622                 return 0;
 623         }
 624         pci_dev = eth_dev->pci_dev;
 625
 626         /* Vendor and Device ID need to be set before init of shared code */
 627         hw->device_id = pci_dev->id.device_id;
 628         hw->vendor_id = pci_dev->id.vendor_id;
 629         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 630 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
 631         hw->allow_unsupported_sfp = 1;
 632 #endif
 633
 634         /* Initialize the shared code */
 635 #ifdef RTE_NIC_BYPASS
 636         diag = ixgbe_bypass_init_shared_code(hw);
 637 #else
 638         diag = ixgbe_init_shared_code(hw);
 639 #endif /* RTE_NIC_BYPASS */
 640
 641         if (diag != IXGBE_SUCCESS) {
 642                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 643                 return -EIO;
 644         }
 645
 646         /* Initialize DCB configuration*/
 647         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 648         ixgbe_dcb_init(hw,dcb_config);
 649         /* Get Hardware Flow Control setting */
 650         hw->fc.requested_mode = ixgbe_fc_full;
 651         hw->fc.current_mode = ixgbe_fc_full;
 652         hw->fc.pause_time = IXGBE_FC_PAUSE;
 653         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 654                 hw->fc.low_water[i] = IXGBE_FC_LO;
 655                 hw->fc.high_water[i] = IXGBE_FC_HI;
 656         }
 657         hw->fc.send_xon = 1;
 658
 659         /* Make sure we have a good EEPROM before we read from it */
 660         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 661         if (diag != IXGBE_SUCCESS) {
 662                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 663                 return -EIO;
 664         }
 665
 666 #ifdef RTE_NIC_BYPASS
 667         diag = ixgbe_bypass_init_hw(hw);
 668 #else
 669         diag = ixgbe_init_hw(hw);
 670 #endif /* RTE_NIC_BYPASS */
 671
 672         /*
 673          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 674          * is called too soon after the kernel driver unbinding/binding occurs.
 675          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 676          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 677          * also called. See ixgbe_identify_phy_82599(). The reason for the
 678          * failure is not known, and only occuts when virtualisation features
 679          * are disabled in the bios. A delay of 100ms  was found to be enough by
 680          * trial-and-error, and is doubled to be safe.
 681          */
 682         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 683                 rte_delay_ms(200);
 684                 diag = ixgbe_init_hw(hw);
 685         }
 686
 687         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 688                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 689                     "LOM.  Please be aware there may be issues associated "
 690                     "with your hardware.\n If you are experiencing problems "
 691                     "please contact your Intel or hardware representative "
 692                     "who provided you with this hardware.\n");
 693         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 694                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
 695         if (diag) {
 696                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 697                 return -EIO;
 698         }
 699
 700         /* disable interrupt */
 701         ixgbe_disable_intr(hw);
 702
 703         /* pick up the PCI bus settings for reporting later */
 704         ixgbe_get_bus_info(hw);
 705
 706         /* reset mappings for queue statistics hw counters*/
 707         ixgbe_reset_qstat_mappings(hw);
 708
 709         /* Allocate memory for storing MAC addresses */
 710         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 711                         hw->mac.num_rar_entries, 0);
 712         if (eth_dev->data->mac_addrs == NULL) {
 713                 PMD_INIT_LOG(ERR,
 714                         "Failed to allocate %u bytes needed to store "
 715                         "MAC addresses",
 716                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 717                 return -ENOMEM;
 718         }
 719         /* Copy the permanent MAC address */
 720         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 721                         &eth_dev->data->mac_addrs[0]);
 722
 723         /* Allocate memory for storing hash filter MAC addresses */
 724         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 725                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 726         if (eth_dev->data->hash_mac_addrs == NULL) {
 727                 PMD_INIT_LOG(ERR,
 728                         "Failed to allocate %d bytes needed to store MAC addresses",
 729                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 730                 return -ENOMEM;
 731         }
 732
 733         /* initialize the vfta */
 734         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 735
 736         /* initialize the hw strip bitmap*/
 737         memset(hwstrip, 0, sizeof(*hwstrip));
 738
 739         /* initialize PF if max_vfs not zero */
 740         ixgbe_pf_host_init(eth_dev);
 741
 742         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 743         /* let hardware know driver is loaded */
 744         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 745         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 746         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 747         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 748         IXGBE_WRITE_FLUSH(hw);
 749
 750         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 751                 PMD_INIT_LOG(DEBUG,
 752                              "MAC: %d, PHY: %d, SFP+: %d<n",
 753                              (int) hw->mac.type, (int) hw->phy.type,
 754                              (int) hw->phy.sfp_type);
 755         else
 756                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
 757                              (int) hw->mac.type, (int) hw->phy.type);
 758
 759         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 760                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 761                         pci_dev->id.device_id);
 762
 763         rte_intr_callback_register(&(pci_dev->intr_handle),
 764                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 765
 766         /* enable uio intr after callback register */
 767         rte_intr_enable(&(pci_dev->intr_handle));
 768
 769         /* enable support intr */
 770         ixgbe_enable_intr(eth_dev);
 771
 772         return 0;
 773 }
 774
 775 static void ixgbevf_get_queue_num(struct ixgbe_hw *hw)
 776 {
 777         /* Traffic classes are not supported by now */
 778         unsigned int tcs, tc;
 779
 780         /*
 781          * Must let PF know we are at mailbox API version 1.1.
 782          * Otherwise PF won't answer properly.
 783          * In case that PF fails to provide Rx/Tx queue number,
 784          * max_tx_queues and max_rx_queues remain to be 1.
 785          */
 786         if (!ixgbevf_negotiate_api_version(hw, ixgbe_mbox_api_11))
 787                 ixgbevf_get_queues(hw, &tcs, &tc);
 788 }
 789
 790 /*
 791  * Virtual Function device init
 792  */
 793 static int
 794 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 795                      struct rte_eth_dev *eth_dev)
 796 {
 797         struct rte_pci_device *pci_dev;
 798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 799         int diag;
 800         struct ixgbe_vfta * shadow_vfta =
 801                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 802         struct ixgbe_hwstrip *hwstrip =
 803                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 804
 805         PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
 806
 807         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 808         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 809         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 810
 811         /* for secondary processes, we don't initialise any further as primary
 812          * has already done this work. Only check we don't need a different
 813          * RX function */
 814         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 815                 if (eth_dev->data->scattered_rx)
 816                         eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
 817                 return 0;
 818         }
 819
 820         pci_dev = eth_dev->pci_dev;
 821
 822         hw->device_id = pci_dev->id.device_id;
 823         hw->vendor_id = pci_dev->id.vendor_id;
 824         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 825
 826         /* initialize the vfta */
 827         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 828
 829         /* initialize the hw strip bitmap*/
 830         memset(hwstrip, 0, sizeof(*hwstrip));
 831
 832         /* Initialize the shared code */
 833         diag = ixgbe_init_shared_code(hw);
 834         if (diag != IXGBE_SUCCESS) {
 835                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
 836                 return -EIO;
 837         }
 838
 839         /* init_mailbox_params */
 840         hw->mbx.ops.init_params(hw);
 841
 842         /* Disable the interrupts for VF */
 843         ixgbevf_intr_disable(hw);
 844
 845         hw->mac.num_rar_entries = hw->mac.max_rx_queues;
 846         diag = hw->mac.ops.reset_hw(hw);
 847
 848         if (diag != IXGBE_SUCCESS) {
 849                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 850                         RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
 851                                         "\tThe most likely cause of this error is that the VM host\n"
 852                                         "\thas not assigned a valid MAC address to this VF device.\n"
 853                                         "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
 854                                         "\ta possible solution to this problem.\n");
 855                 return (diag);
 856         }
 857
 858         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
 859         ixgbevf_get_queue_num(hw);
 860
 861         /* Allocate memory for storing MAC addresses */
 862         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
 863                         hw->mac.num_rar_entries, 0);
 864         if (eth_dev->data->mac_addrs == NULL) {
 865                 PMD_INIT_LOG(ERR,
 866                         "Failed to allocate %u bytes needed to store "
 867                         "MAC addresses",
 868                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 869                 return -ENOMEM;
 870         }
 871
 872         /* Copy the permanent MAC address */
 873         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 874                         &eth_dev->data->mac_addrs[0]);
 875
 876         /* reset the hardware with the new settings */
 877         diag = hw->mac.ops.start_hw(hw);
 878         switch (diag) {
 879                 case  0:
 880                         break;
 881
 882                 default:
 883                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
 884                         return (-EIO);
 885         }
 886
 887         PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
 888                          eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
 889                          "ixgbe_mac_82599_vf");
 890
 891         return 0;
 892 }
 893
 894 static struct eth_driver rte_ixgbe_pmd = {
 895         {
 896                 .name = "rte_ixgbe_pmd",
 897                 .id_table = pci_id_ixgbe_map,
 898                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 899         },
 900         .eth_dev_init = eth_ixgbe_dev_init,
 901         .dev_private_size = sizeof(struct ixgbe_adapter),
 902 };
 903
 904 /*
 905  * virtual function driver struct
 906  */
 907 static struct eth_driver rte_ixgbevf_pmd = {
 908         {
 909                 .name = "rte_ixgbevf_pmd",
 910                 .id_table = pci_id_ixgbevf_map,
 911                 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
 912         },
 913         .eth_dev_init = eth_ixgbevf_dev_init,
 914         .dev_private_size = sizeof(struct ixgbe_adapter),
 915 };
 916
 917 /*
 918  * Driver initialization routine.
 919  * Invoked once at EAL init time.
 920  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 921  */
 922 int
 923 rte_ixgbe_pmd_init(void)
 924 {
 925         PMD_INIT_FUNC_TRACE();
 926
 927         rte_eth_driver_register(&rte_ixgbe_pmd);
 928         return 0;
 929 }
 930
 931 /*
 932  * VF Driver initialization routine.
 933  * Invoked one at EAL init time.
 934  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
 935  */
 936 int
 937 rte_ixgbevf_pmd_init(void)
 938 {
 939         DEBUGFUNC("rte_ixgbevf_pmd_init");
 940
 941         rte_eth_driver_register(&rte_ixgbevf_pmd);
 942         return (0);
 943 }
 944
 945 static int
 946 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 947 {
 948         struct ixgbe_hw *hw =
 949                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 950         struct ixgbe_vfta * shadow_vfta =
 951                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
 952         uint32_t vfta;
 953         uint32_t vid_idx;
 954         uint32_t vid_bit;
 955
 956         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
 957         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
 958         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
 959         if (on)
 960                 vfta |= vid_bit;
 961         else
 962                 vfta &= ~vid_bit;
 963         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
 964
 965         /* update local VFTA copy */
 966         shadow_vfta->vfta[vid_idx] = vfta;
 967
 968         return 0;
 969 }
 970
 971 static void
 972 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 973 {
 974         if (on)
 975                 ixgbe_vlan_hw_strip_enable(dev, queue);
 976         else
 977                 ixgbe_vlan_hw_strip_disable(dev, queue);
 978 }
 979
 980 static void
 981 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
 982 {
 983         struct ixgbe_hw *hw =
 984                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 985
 986         /* Only the high 16-bits is valid */
 987         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
 988 }
 989
 990 void
 991 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
 992 {
 993         struct ixgbe_hw *hw =
 994                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 995         uint32_t vlnctrl;
 996
 997         PMD_INIT_FUNC_TRACE();
 998
 999         /* Filter Table Disable */
1000         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1001         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1002
1003         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1004 }
1005
1006 void
1007 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1008 {
1009         struct ixgbe_hw *hw =
1010                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1011         struct ixgbe_vfta * shadow_vfta =
1012                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1013         uint32_t vlnctrl;
1014         uint16_t i;
1015
1016         PMD_INIT_FUNC_TRACE();
1017
1018         /* Filter Table Enable */
1019         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1020         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1021         vlnctrl |= IXGBE_VLNCTRL_VFE;
1022
1023         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1024
1025         /* write whatever is in local vfta copy */
1026         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1027                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1028 }
1029
1030 static void
1031 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1032 {
1033         struct ixgbe_hwstrip *hwstrip =
1034                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1035
1036         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1037                 return;
1038
1039         if (on)
1040                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1041         else
1042                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1043 }
1044
1045 static void
1046 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1047 {
1048         struct ixgbe_hw *hw =
1049                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1050         uint32_t ctrl;
1051
1052         PMD_INIT_FUNC_TRACE();
1053
1054         if (hw->mac.type == ixgbe_mac_82598EB) {
1055                 /* No queue level support */
1056                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1057                 return;
1058         }
1059         else {
1060                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1061                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1062                 ctrl &= ~IXGBE_RXDCTL_VME;
1063                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1064         }
1065         /* record those setting for HW strip per queue */
1066         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1067 }
1068
1069 static void
1070 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1071 {
1072         struct ixgbe_hw *hw =
1073                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1074         uint32_t ctrl;
1075
1076         PMD_INIT_FUNC_TRACE();
1077
1078         if (hw->mac.type == ixgbe_mac_82598EB) {
1079                 /* No queue level supported */
1080                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1081                 return;
1082         }
1083         else {
1084                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1085                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1086                 ctrl |= IXGBE_RXDCTL_VME;
1087                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1088         }
1089         /* record those setting for HW strip per queue */
1090         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1091 }
1092
1093 void
1094 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1095 {
1096         struct ixgbe_hw *hw =
1097                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1098         uint32_t ctrl;
1099         uint16_t i;
1100
1101         PMD_INIT_FUNC_TRACE();
1102
1103         if (hw->mac.type == ixgbe_mac_82598EB) {
1104                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1105                 ctrl &= ~IXGBE_VLNCTRL_VME;
1106                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1107         }
1108         else {
1109                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1110                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1111                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1112                         ctrl &= ~IXGBE_RXDCTL_VME;
1113                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1114
1115                         /* record those setting for HW strip per queue */
1116                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1117                 }
1118         }
1119 }
1120
1121 void
1122 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1123 {
1124         struct ixgbe_hw *hw =
1125                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1126         uint32_t ctrl;
1127         uint16_t i;
1128
1129         PMD_INIT_FUNC_TRACE();
1130
1131         if (hw->mac.type == ixgbe_mac_82598EB) {
1132                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1133                 ctrl |= IXGBE_VLNCTRL_VME;
1134                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1135         }
1136         else {
1137                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1138                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1139                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1140                         ctrl |= IXGBE_RXDCTL_VME;
1141                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1142
1143                         /* record those setting for HW strip per queue */
1144                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1145                 }
1146         }
1147 }
1148
1149 static void
1150 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1151 {
1152         struct ixgbe_hw *hw =
1153                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1154         uint32_t ctrl;
1155
1156         PMD_INIT_FUNC_TRACE();
1157
1158         /* DMATXCTRL: Geric Double VLAN Disable */
1159         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1160         ctrl &= ~IXGBE_DMATXCTL_GDV;
1161         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1162
1163         /* CTRL_EXT: Global Double VLAN Disable */
1164         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1165         ctrl &= ~IXGBE_EXTENDED_VLAN;
1166         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1167
1168 }
1169
1170 static void
1171 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1172 {
1173         struct ixgbe_hw *hw =
1174                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1175         uint32_t ctrl;
1176
1177         PMD_INIT_FUNC_TRACE();
1178
1179         /* DMATXCTRL: Geric Double VLAN Enable */
1180         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1181         ctrl |= IXGBE_DMATXCTL_GDV;
1182         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1183
1184         /* CTRL_EXT: Global Double VLAN Enable */
1185         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1186         ctrl |= IXGBE_EXTENDED_VLAN;
1187         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1188
1189         /*
1190          * VET EXT field in the EXVET register = 0x8100 by default
1191          * So no need to change. Same to VT field of DMATXCTL register
1192          */
1193 }
1194
1195 static void
1196 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1197 {
1198         if(mask & ETH_VLAN_STRIP_MASK){
1199                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1200                         ixgbe_vlan_hw_strip_enable_all(dev);
1201                 else
1202                         ixgbe_vlan_hw_strip_disable_all(dev);
1203         }
1204
1205         if(mask & ETH_VLAN_FILTER_MASK){
1206                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1207                         ixgbe_vlan_hw_filter_enable(dev);
1208                 else
1209                         ixgbe_vlan_hw_filter_disable(dev);
1210         }
1211
1212         if(mask & ETH_VLAN_EXTEND_MASK){
1213                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1214                         ixgbe_vlan_hw_extend_enable(dev);
1215                 else
1216                         ixgbe_vlan_hw_extend_disable(dev);
1217         }
1218 }
1219
1220 static void
1221 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1222 {
1223         struct ixgbe_hw *hw =
1224                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1225         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1226         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1227         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1228         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1229 }
1230
1231 static int
1232 ixgbe_dev_configure(struct rte_eth_dev *dev)
1233 {
1234         struct ixgbe_interrupt *intr =
1235                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1236
1237         PMD_INIT_FUNC_TRACE();
1238
1239         /* set flag to update link status after init */
1240         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1241
1242         return 0;
1243 }
1244
1245 /*
1246  * Configure device link speed and setup link.
1247  * It returns 0 on success.
1248  */
1249 static int
1250 ixgbe_dev_start(struct rte_eth_dev *dev)
1251 {
1252         struct ixgbe_hw *hw =
1253                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1254         int err, link_up = 0, negotiate = 0;
1255         uint32_t speed = 0;
1256         int mask = 0;
1257         int status;
1258
1259         PMD_INIT_FUNC_TRACE();
1260
1261         /* IXGBE devices don't support half duplex */
1262         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1263                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1264                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1265                                 dev->data->dev_conf.link_duplex,
1266                                 dev->data->port_id);
1267                 return -EINVAL;
1268         }
1269
1270         /* stop adapter */
1271         hw->adapter_stopped = FALSE;
1272         ixgbe_stop_adapter(hw);
1273
1274         /* reinitialize adapter
1275          * this calls reset and start */
1276         status = ixgbe_pf_reset_hw(hw);
1277         if (status != 0)
1278                 return -1;
1279         hw->mac.ops.start_hw(hw);
1280
1281         /* configure PF module if SRIOV enabled */
1282         ixgbe_pf_host_configure(dev);
1283
1284         /* initialize transmission unit */
1285         ixgbe_dev_tx_init(dev);
1286
1287         /* This can fail when allocating mbufs for descriptor rings */
1288         err = ixgbe_dev_rx_init(dev);
1289         if (err) {
1290                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1291                 goto error;
1292         }
1293
1294         ixgbe_dev_rxtx_start(dev);
1295
1296         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1297                 err = hw->mac.ops.setup_sfp(hw);
1298                 if (err)
1299                         goto error;
1300         }
1301
1302         /* Turn on the laser */
1303         ixgbe_enable_tx_laser(hw);
1304
1305         /* Skip link setup if loopback mode is enabled for 82599. */
1306         if (hw->mac.type == ixgbe_mac_82599EB &&
1307                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1308                 goto skip_link_setup;
1309
1310         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1311         if (err)
1312                 goto error;
1313         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1314         if (err)
1315                 goto error;
1316
1317         switch(dev->data->dev_conf.link_speed) {
1318         case ETH_LINK_SPEED_AUTONEG:
1319                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1320                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1321                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1322                 break;
1323         case ETH_LINK_SPEED_100:
1324                 /*
1325                  * Invalid for 82598 but error will be detected by
1326                  * ixgbe_setup_link()
1327                  */
1328                 speed = IXGBE_LINK_SPEED_100_FULL;
1329                 break;
1330         case ETH_LINK_SPEED_1000:
1331                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1332                 break;
1333         case ETH_LINK_SPEED_10000:
1334                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1335                 break;
1336         default:
1337                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1338                                 dev->data->dev_conf.link_speed,
1339                                 dev->data->port_id);
1340                 goto error;
1341         }
1342
1343         err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1344         if (err)
1345                 goto error;
1346
1347 skip_link_setup:
1348
1349         /* check if lsc interrupt is enabled */
1350         if (dev->data->dev_conf.intr_conf.lsc != 0)
1351                 ixgbe_dev_lsc_interrupt_setup(dev);
1352
1353         /* resume enabled intr since hw reset */
1354         ixgbe_enable_intr(dev);
1355
1356         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1357                 ETH_VLAN_EXTEND_MASK;
1358         ixgbe_vlan_offload_set(dev, mask);
1359
1360         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1361                 /* Enable vlan filtering for VMDq */
1362                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1363         }
1364
1365         /* Configure DCB hw */
1366         ixgbe_configure_dcb(dev);
1367
1368         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1369                 err = ixgbe_fdir_configure(dev);
1370                 if (err)
1371                         goto error;
1372         }
1373
1374         ixgbe_restore_statistics_mapping(dev);
1375
1376         return (0);
1377
1378 error:
1379         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1380         ixgbe_dev_clear_queues(dev);
1381         return -EIO;
1382 }
1383
1384 /*
1385  * Stop device: disable rx and tx functions to allow for reconfiguring.
1386  */
1387 static void
1388 ixgbe_dev_stop(struct rte_eth_dev *dev)
1389 {
1390         struct rte_eth_link link;
1391         struct ixgbe_hw *hw =
1392                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1393         struct ixgbe_vf_info *vfinfo =
1394                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1395         int vf;
1396
1397         PMD_INIT_FUNC_TRACE();
1398
1399         /* disable interrupts */
1400         ixgbe_disable_intr(hw);
1401
1402         /* reset the NIC */
1403         ixgbe_pf_reset_hw(hw);
1404         hw->adapter_stopped = FALSE;
1405
1406         /* stop adapter */
1407         ixgbe_stop_adapter(hw);
1408
1409         for (vf = 0; vfinfo != NULL &&
1410                      vf < dev->pci_dev->max_vfs; vf++)
1411                 vfinfo[vf].clear_to_send = false;
1412
1413         /* Turn off the laser */
1414         ixgbe_disable_tx_laser(hw);
1415
1416         ixgbe_dev_clear_queues(dev);
1417
1418         /* Clear recorded link status */
1419         memset(&link, 0, sizeof(link));
1420         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1421 }
1422
1423 /*
1424  * Reest and stop device.
1425  */
1426 static void
1427 ixgbe_dev_close(struct rte_eth_dev *dev)
1428 {
1429         struct ixgbe_hw *hw =
1430                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1431
1432         PMD_INIT_FUNC_TRACE();
1433
1434         ixgbe_pf_reset_hw(hw);
1435
1436         ixgbe_dev_stop(dev);
1437         hw->adapter_stopped = 1;
1438
1439         ixgbe_disable_pcie_master(hw);
1440
1441         /* reprogram the RAR[0] in case user changed it. */
1442         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1443 }
1444
1445 /*
1446  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1447  */
1448 static void
1449 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1450 {
1451         struct ixgbe_hw *hw =
1452                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1453         struct ixgbe_hw_stats *hw_stats =
1454                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1455         uint32_t bprc, lxon, lxoff, total;
1456         uint64_t total_missed_rx, total_qbrc, total_qprc;
1457         unsigned i;
1458
1459         total_missed_rx = 0;
1460         total_qbrc = 0;
1461         total_qprc = 0;
1462
1463         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1464         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1465         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1466         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1467
1468         for (i = 0; i < 8; i++) {
1469                 uint32_t mp;
1470                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1471                 /* global total per queue */
1472                 hw_stats->mpc[i] += mp;
1473                 /* Running comprehensive total for stats display */
1474                 total_missed_rx += hw_stats->mpc[i];
1475                 if (hw->mac.type == ixgbe_mac_82598EB)
1476                         hw_stats->rnbc[i] +=
1477                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1478                 hw_stats->pxontxc[i] +=
1479                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1480                 hw_stats->pxonrxc[i] +=
1481                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1482                 hw_stats->pxofftxc[i] +=
1483                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1484                 hw_stats->pxoffrxc[i] +=
1485                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1486                 hw_stats->pxon2offc[i] +=
1487                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1488         }
1489         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1490                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1491                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1492                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1493                 hw_stats->qbrc[i] +=
1494                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1495                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1496                 hw_stats->qbtc[i] +=
1497                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1498                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1499
1500                 total_qprc += hw_stats->qprc[i];
1501                 total_qbrc += hw_stats->qbrc[i];
1502         }
1503         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1504         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1505         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1506
1507         /* Note that gprc counts missed packets */
1508         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1509
1510         if (hw->mac.type != ixgbe_mac_82598EB) {
1511                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1512                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1513                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1514                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1515                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1516                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1517                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1518                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1519         } else {
1520                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1521                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1522                 /* 82598 only has a counter in the high register */
1523                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1524                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1525                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1526         }
1527
1528         /*
1529          * Workaround: mprc hardware is incorrectly counting
1530          * broadcasts, so for now we subtract those.
1531          */
1532         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1533         hw_stats->bprc += bprc;
1534         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1535         if (hw->mac.type == ixgbe_mac_82598EB)
1536                 hw_stats->mprc -= bprc;
1537
1538         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1539         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1540         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1541         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1542         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1543         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1544
1545         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1546         hw_stats->lxontxc += lxon;
1547         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1548         hw_stats->lxofftxc += lxoff;
1549         total = lxon + lxoff;
1550
1551         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1552         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1553         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1554         hw_stats->gptc -= total;
1555         hw_stats->mptc -= total;
1556         hw_stats->ptc64 -= total;
1557         hw_stats->gotc -= total * ETHER_MIN_LEN;
1558
1559         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1560         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1561         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1562         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1563         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1564         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1565         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1566         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1567         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1568         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1569         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1570         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1571         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1572         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1573         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1574         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1575         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1576         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1577         /* Only read FCOE on 82599 */
1578         if (hw->mac.type != ixgbe_mac_82598EB) {
1579                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1580                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1581                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1582                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1583                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1584         }
1585
1586         if (stats == NULL)
1587                 return;
1588
1589         /* Fill out the rte_eth_stats statistics structure */
1590         stats->ipackets = total_qprc;
1591         stats->ibytes = total_qbrc;
1592         stats->opackets = hw_stats->gptc;
1593         stats->obytes = hw_stats->gotc;
1594         stats->imcasts = hw_stats->mprc;
1595
1596         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1597                 stats->q_ipackets[i] = hw_stats->qprc[i];
1598                 stats->q_opackets[i] = hw_stats->qptc[i];
1599                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1600                 stats->q_obytes[i] = hw_stats->qbtc[i];
1601                 stats->q_errors[i] = hw_stats->qprdc[i];
1602         }
1603
1604         /* Rx Errors */
1605         stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1606                 hw_stats->rlec;
1607
1608         stats->oerrors  = 0;
1609
1610         /* XON/XOFF pause frames */
1611         stats->tx_pause_xon  = hw_stats->lxontxc;
1612         stats->rx_pause_xon  = hw_stats->lxonrxc;
1613         stats->tx_pause_xoff = hw_stats->lxofftxc;
1614         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1615
1616         /* Flow Director Stats registers */
1617         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1618         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1619         stats->fdirmatch = hw_stats->fdirmatch;
1620         stats->fdirmiss = hw_stats->fdirmiss;
1621 }
1622
1623 static void
1624 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1625 {
1626         struct ixgbe_hw_stats *stats =
1627                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1628
1629         /* HW registers are cleared on read */
1630         ixgbe_dev_stats_get(dev, NULL);
1631
1632         /* Reset software totals */
1633         memset(stats, 0, sizeof(*stats));
1634 }
1635
1636 static void
1637 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1638 {
1639         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1641                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1642
1643         /* Good Rx packet, include VF loopback */
1644         UPDATE_VF_STAT(IXGBE_VFGPRC,
1645             hw_stats->last_vfgprc, hw_stats->vfgprc);
1646
1647         /* Good Rx octets, include VF loopback */
1648         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1649             hw_stats->last_vfgorc, hw_stats->vfgorc);
1650
1651         /* Good Tx packet, include VF loopback */
1652         UPDATE_VF_STAT(IXGBE_VFGPTC,
1653             hw_stats->last_vfgptc, hw_stats->vfgptc);
1654
1655         /* Good Tx octets, include VF loopback */
1656         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1657             hw_stats->last_vfgotc, hw_stats->vfgotc);
1658
1659         /* Rx Multicst Packet */
1660         UPDATE_VF_STAT(IXGBE_VFMPRC,
1661             hw_stats->last_vfmprc, hw_stats->vfmprc);
1662
1663         if (stats == NULL)
1664                 return;
1665
1666         memset(stats, 0, sizeof(*stats));
1667         stats->ipackets = hw_stats->vfgprc;
1668         stats->ibytes = hw_stats->vfgorc;
1669         stats->opackets = hw_stats->vfgptc;
1670         stats->obytes = hw_stats->vfgotc;
1671         stats->imcasts = hw_stats->vfmprc;
1672 }
1673
1674 static void
1675 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1676 {
1677         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1678                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1679
1680         /* Sync HW register to the last stats */
1681         ixgbevf_dev_stats_get(dev, NULL);
1682
1683         /* reset HW current stats*/
1684         hw_stats->vfgprc = 0;
1685         hw_stats->vfgorc = 0;
1686         hw_stats->vfgptc = 0;
1687         hw_stats->vfgotc = 0;
1688         hw_stats->vfmprc = 0;
1689
1690 }
1691
1692 static void
1693 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1694 {
1695         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1696
1697         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1698         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1699         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1700         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1701         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1702         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1703         dev_info->max_vfs = dev->pci_dev->max_vfs;
1704         if (hw->mac.type == ixgbe_mac_82598EB)
1705                 dev_info->max_vmdq_pools = ETH_16_POOLS;
1706         else
1707                 dev_info->max_vmdq_pools = ETH_64_POOLS;
1708         dev_info->rx_offload_capa =
1709                 DEV_RX_OFFLOAD_VLAN_STRIP |
1710                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1711                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1712                 DEV_RX_OFFLOAD_TCP_CKSUM;
1713         dev_info->tx_offload_capa =
1714                 DEV_TX_OFFLOAD_VLAN_INSERT |
1715                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1716                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1717                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1718                 DEV_TX_OFFLOAD_SCTP_CKSUM;
1719 }
1720
1721 /* return 0 means link status changed, -1 means not changed */
1722 static int
1723 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1724 {
1725         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         struct rte_eth_link link, old;
1727         ixgbe_link_speed link_speed;
1728         int link_up;
1729         int diag;
1730
1731         link.link_status = 0;
1732         link.link_speed = 0;
1733         link.link_duplex = 0;
1734         memset(&old, 0, sizeof(old));
1735         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1736
1737         /* check if it needs to wait to complete, if lsc interrupt is enabled */
1738         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1739                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1740         else
1741                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1742         if (diag != 0) {
1743                 link.link_speed = ETH_LINK_SPEED_100;
1744                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1745                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1746                 if (link.link_status == old.link_status)
1747                         return -1;
1748                 return 0;
1749         }
1750
1751         if (link_up == 0) {
1752                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1753                 if (link.link_status == old.link_status)
1754                         return -1;
1755                 return 0;
1756         }
1757         link.link_status = 1;
1758         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1759
1760         switch (link_speed) {
1761         default:
1762         case IXGBE_LINK_SPEED_UNKNOWN:
1763                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1764                 link.link_speed = ETH_LINK_SPEED_100;
1765                 break;
1766
1767         case IXGBE_LINK_SPEED_100_FULL:
1768                 link.link_speed = ETH_LINK_SPEED_100;
1769                 break;
1770
1771         case IXGBE_LINK_SPEED_1GB_FULL:
1772                 link.link_speed = ETH_LINK_SPEED_1000;
1773                 break;
1774
1775         case IXGBE_LINK_SPEED_10GB_FULL:
1776                 link.link_speed = ETH_LINK_SPEED_10000;
1777                 break;
1778         }
1779         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1780
1781         if (link.link_status == old.link_status)
1782                 return -1;
1783
1784         return 0;
1785 }
1786
1787 static void
1788 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1789 {
1790         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1791         uint32_t fctrl;
1792
1793         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1794         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1795         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1796 }
1797
1798 static void
1799 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1800 {
1801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1802         uint32_t fctrl;
1803
1804         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1805         fctrl &= (~IXGBE_FCTRL_UPE);
1806         if (dev->data->all_multicast == 1)
1807                 fctrl |= IXGBE_FCTRL_MPE;
1808         else
1809                 fctrl &= (~IXGBE_FCTRL_MPE);
1810         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1811 }
1812
1813 static void
1814 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1815 {
1816         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1817         uint32_t fctrl;
1818
1819         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1820         fctrl |= IXGBE_FCTRL_MPE;
1821         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1822 }
1823
1824 static void
1825 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1826 {
1827         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1828         uint32_t fctrl;
1829
1830         if (dev->data->promiscuous == 1)
1831                 return; /* must remain in all_multicast mode */
1832
1833         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1834         fctrl &= (~IXGBE_FCTRL_MPE);
1835         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1836 }
1837
1838 /**
1839  * It clears the interrupt causes and enables the interrupt.
1840  * It will be called once only during nic initialized.
1841  *
1842  * @param dev
1843  *  Pointer to struct rte_eth_dev.
1844  *
1845  * @return
1846  *  - On success, zero.
1847  *  - On failure, a negative value.
1848  */
1849 static int
1850 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1851 {
1852         struct ixgbe_interrupt *intr =
1853                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1854
1855         ixgbe_dev_link_status_print(dev);
1856         intr->mask |= IXGBE_EICR_LSC;
1857
1858         return 0;
1859 }
1860
1861 /*
1862  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1863  *
1864  * @param dev
1865  *  Pointer to struct rte_eth_dev.
1866  *
1867  * @return
1868  *  - On success, zero.
1869  *  - On failure, a negative value.
1870  */
1871 static int
1872 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1873 {
1874         uint32_t eicr;
1875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1876         struct ixgbe_interrupt *intr =
1877                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1878
1879         /* clear all cause mask */
1880         ixgbe_disable_intr(hw);
1881
1882         /* read-on-clear nic registers here */
1883         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1884         PMD_DRV_LOG(INFO, "eicr %x", eicr);
1885
1886         intr->flags = 0;
1887         if (eicr & IXGBE_EICR_LSC) {
1888                 /* set flag for async link update */
1889                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1890         }
1891
1892         if (eicr & IXGBE_EICR_MAILBOX)
1893                 intr->flags |= IXGBE_FLAG_MAILBOX;
1894
1895         return 0;
1896 }
1897
1898 /**
1899  * It gets and then prints the link status.
1900  *
1901  * @param dev
1902  *  Pointer to struct rte_eth_dev.
1903  *
1904  * @return
1905  *  - On success, zero.
1906  *  - On failure, a negative value.
1907  */
1908 static void
1909 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1910 {
1911         struct rte_eth_link link;
1912
1913         memset(&link, 0, sizeof(link));
1914         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1915         if (link.link_status) {
1916                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1917                                         (int)(dev->data->port_id),
1918                                         (unsigned)link.link_speed,
1919                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1920                                         "full-duplex" : "half-duplex");
1921         } else {
1922                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1923                                 (int)(dev->data->port_id));
1924         }
1925         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1926                                 dev->pci_dev->addr.domain,
1927                                 dev->pci_dev->addr.bus,
1928                                 dev->pci_dev->addr.devid,
1929                                 dev->pci_dev->addr.function);
1930 }
1931
1932 /*
1933  * It executes link_update after knowing an interrupt occured.
1934  *
1935  * @param dev
1936  *  Pointer to struct rte_eth_dev.
1937  *
1938  * @return
1939  *  - On success, zero.
1940  *  - On failure, a negative value.
1941  */
1942 static int
1943 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1944 {
1945         struct ixgbe_interrupt *intr =
1946                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1947         int64_t timeout;
1948         struct rte_eth_link link;
1949         int intr_enable_delay = false;
1950
1951         PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
1952
1953         if (intr->flags & IXGBE_FLAG_MAILBOX) {
1954                 ixgbe_pf_mbx_process(dev);
1955                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
1956         }
1957
1958         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1959                 /* get the link status before link update, for predicting later */
1960                 memset(&link, 0, sizeof(link));
1961                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1962
1963                 ixgbe_dev_link_update(dev, 0);
1964
1965                 /* likely to up */
1966                 if (!link.link_status)
1967                         /* handle it 1 sec later, wait it being stable */
1968                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
1969                 /* likely to down */
1970                 else
1971                         /* handle it 4 sec later, wait it being stable */
1972                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
1973
1974                 ixgbe_dev_link_status_print(dev);
1975
1976                 intr_enable_delay = true;
1977         }
1978
1979         if (intr_enable_delay) {
1980                 if (rte_eal_alarm_set(timeout * 1000,
1981                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
1982                         PMD_DRV_LOG(ERR, "Error setting alarm");
1983         } else {
1984                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
1985                 ixgbe_enable_intr(dev);
1986                 rte_intr_enable(&(dev->pci_dev->intr_handle));
1987         }
1988
1989
1990         return 0;
1991 }
1992
1993 /**
1994  * Interrupt handler which shall be registered for alarm callback for delayed
1995  * handling specific interrupt to wait for the stable nic state. As the
1996  * NIC interrupt state is not stable for ixgbe after link is just down,
1997  * it needs to wait 4 seconds to get the stable status.
1998  *
1999  * @param handle
2000  *  Pointer to interrupt handle.
2001  * @param param
2002  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2003  *
2004  * @return
2005  *  void
2006  */
2007 static void
2008 ixgbe_dev_interrupt_delayed_handler(void *param)
2009 {
2010         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2011         struct ixgbe_interrupt *intr =
2012                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2013         struct ixgbe_hw *hw =
2014                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2015         uint32_t eicr;
2016
2017         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2018         if (eicr & IXGBE_EICR_MAILBOX)
2019                 ixgbe_pf_mbx_process(dev);
2020
2021         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2022                 ixgbe_dev_link_update(dev, 0);
2023                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2024                 ixgbe_dev_link_status_print(dev);
2025                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2026         }
2027
2028         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2029         ixgbe_enable_intr(dev);
2030         rte_intr_enable(&(dev->pci_dev->intr_handle));
2031 }
2032
2033 /**
2034  * Interrupt handler triggered by NIC  for handling
2035  * specific interrupt.
2036  *
2037  * @param handle
2038  *  Pointer to interrupt handle.
2039  * @param param
2040  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2041  *
2042  * @return
2043  *  void
2044  */
2045 static void
2046 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2047                                                         void *param)
2048 {
2049         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2050         ixgbe_dev_interrupt_get_status(dev);
2051         ixgbe_dev_interrupt_action(dev);
2052 }
2053
2054 static int
2055 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2056 {
2057         struct ixgbe_hw *hw;
2058
2059         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2061 }
2062
2063 static int
2064 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2065 {
2066         struct ixgbe_hw *hw;
2067
2068         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2069         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2070 }
2071
2072 static int
2073 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2074 {
2075         struct ixgbe_hw *hw;
2076         int err;
2077         uint32_t rx_buf_size;
2078         uint32_t max_high_water;
2079         uint32_t mflcn;
2080         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2081                 ixgbe_fc_none,
2082                 ixgbe_fc_rx_pause,
2083                 ixgbe_fc_tx_pause,
2084                 ixgbe_fc_full
2085         };
2086
2087         PMD_INIT_FUNC_TRACE();
2088
2089         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2090         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2091         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2092
2093         /*
2094          * At least reserve one Ethernet frame for watermark
2095          * high_water/low_water in kilo bytes for ixgbe
2096          */
2097         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2098         if ((fc_conf->high_water > max_high_water) ||
2099                 (fc_conf->high_water < fc_conf->low_water)) {
2100                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2101                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2102                 return (-EINVAL);
2103         }
2104
2105         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2106         hw->fc.pause_time     = fc_conf->pause_time;
2107         hw->fc.high_water[0]  = fc_conf->high_water;
2108         hw->fc.low_water[0]   = fc_conf->low_water;
2109         hw->fc.send_xon       = fc_conf->send_xon;
2110
2111         err = ixgbe_fc_enable(hw);
2112
2113         /* Not negotiated is not an error case */
2114         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2115
2116                 /* check if we want to forward MAC frames - driver doesn't have native
2117                  * capability to do that, so we'll write the registers ourselves */
2118
2119                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2120
2121                 /* set or clear MFLCN.PMCF bit depending on configuration */
2122                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2123                         mflcn |= IXGBE_MFLCN_PMCF;
2124                 else
2125                         mflcn &= ~IXGBE_MFLCN_PMCF;
2126
2127                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2128                 IXGBE_WRITE_FLUSH(hw);
2129
2130                 return 0;
2131         }
2132
2133         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2134         return -EIO;
2135 }
2136
2137 /**
2138  *  ixgbe_pfc_enable_generic - Enable flow control
2139  *  @hw: pointer to hardware structure
2140  *  @tc_num: traffic class number
2141  *  Enable flow control according to the current settings.
2142  */
2143 static int
2144 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2145 {
2146         int ret_val = 0;
2147         uint32_t mflcn_reg, fccfg_reg;
2148         uint32_t reg;
2149         uint32_t fcrtl, fcrth;
2150         uint8_t i;
2151         uint8_t nb_rx_en;
2152
2153         /* Validate the water mark configuration */
2154         if (!hw->fc.pause_time) {
2155                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2156                 goto out;
2157         }
2158
2159         /* Low water mark of zero causes XOFF floods */
2160         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2161                  /* High/Low water can not be 0 */
2162                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2163                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2164                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2165                         goto out;
2166                 }
2167
2168                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2169                         PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2170                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2171                         goto out;
2172                 }
2173         }
2174         /* Negotiate the fc mode to use */
2175         ixgbe_fc_autoneg(hw);
2176
2177         /* Disable any previous flow control settings */
2178         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2179         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2180
2181         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2182         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2183
2184         switch (hw->fc.current_mode) {
2185         case ixgbe_fc_none:
2186                 /*
2187                  * If the count of enabled RX Priority Flow control >1,
2188                  * and the TX pause can not be disabled
2189                  */
2190                 nb_rx_en = 0;
2191                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2192                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2193                         if (reg & IXGBE_FCRTH_FCEN)
2194                                 nb_rx_en++;
2195                 }
2196                 if (nb_rx_en > 1)
2197                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2198                 break;
2199         case ixgbe_fc_rx_pause:
2200                 /*
2201                  * Rx Flow control is enabled and Tx Flow control is
2202                  * disabled by software override. Since there really
2203                  * isn't a way to advertise that we are capable of RX
2204                  * Pause ONLY, we will advertise that we support both
2205                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2206                  * disable the adapter's ability to send PAUSE frames.
2207                  */
2208                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2209                 /*
2210                  * If the count of enabled RX Priority Flow control >1,
2211                  * and the TX pause can not be disabled
2212                  */
2213                 nb_rx_en = 0;
2214                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2215                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2216                         if (reg & IXGBE_FCRTH_FCEN)
2217                                 nb_rx_en++;
2218                 }
2219                 if (nb_rx_en > 1)
2220                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2221                 break;
2222         case ixgbe_fc_tx_pause:
2223                 /*
2224                  * Tx Flow control is enabled, and Rx Flow control is
2225                  * disabled by software override.
2226                  */
2227                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2228                 break;
2229         case ixgbe_fc_full:
2230                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2231                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2232                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2233                 break;
2234         default:
2235                 DEBUGOUT("Flow control param set incorrectly\n");
2236                 ret_val = IXGBE_ERR_CONFIG;
2237                 goto out;
2238                 break;
2239         }
2240
2241         /* Set 802.3x based flow control settings. */
2242         mflcn_reg |= IXGBE_MFLCN_DPF;
2243         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2244         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2245
2246         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2247         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2248                 hw->fc.high_water[tc_num]) {
2249                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2250                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2251                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2252         } else {
2253                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2254                 /*
2255                  * In order to prevent Tx hangs when the internal Tx
2256                  * switch is enabled we must set the high water mark
2257                  * to the maximum FCRTH value.  This allows the Tx
2258                  * switch to function even under heavy Rx workloads.
2259                  */
2260                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2261         }
2262         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2263
2264         /* Configure pause time (2 TCs per register) */
2265         reg = hw->fc.pause_time * 0x00010001;
2266         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2267                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2268
2269         /* Configure flow control refresh threshold value */
2270         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2271
2272 out:
2273         return ret_val;
2274 }
2275
2276 static int
2277 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2278 {
2279         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2280         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2281
2282         if(hw->mac.type != ixgbe_mac_82598EB) {
2283                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2284         }
2285         return ret_val;
2286 }
2287
2288 static int
2289 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2290 {
2291         int err;
2292         uint32_t rx_buf_size;
2293         uint32_t max_high_water;
2294         uint8_t tc_num;
2295         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2296         struct ixgbe_hw *hw =
2297                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2298         struct ixgbe_dcb_config *dcb_config =
2299                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2300
2301         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2302                 ixgbe_fc_none,
2303                 ixgbe_fc_rx_pause,
2304                 ixgbe_fc_tx_pause,
2305                 ixgbe_fc_full
2306         };
2307
2308         PMD_INIT_FUNC_TRACE();
2309
2310         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2311         tc_num = map[pfc_conf->priority];
2312         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2313         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2314         /*
2315          * At least reserve one Ethernet frame for watermark
2316          * high_water/low_water in kilo bytes for ixgbe
2317          */
2318         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2319         if ((pfc_conf->fc.high_water > max_high_water) ||
2320                 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2321                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2322                 PMD_INIT_LOG(ERR, "High_water must <=  0x%x\n", max_high_water);
2323                 return (-EINVAL);
2324         }
2325
2326         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2327         hw->fc.pause_time = pfc_conf->fc.pause_time;
2328         hw->fc.send_xon = pfc_conf->fc.send_xon;
2329         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2330         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2331
2332         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2333
2334         /* Not negotiated is not an error case */
2335         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2336                 return 0;
2337
2338         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2339         return -EIO;
2340 }
2341
2342 static int
2343 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2344                                 struct rte_eth_rss_reta *reta_conf)
2345 {
2346         uint8_t i,j,mask;
2347         uint32_t reta;
2348         struct ixgbe_hw *hw =
2349                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2350
2351         PMD_INIT_FUNC_TRACE();
2352         /*
2353         * Update Redirection Table RETA[n],n=0...31,The redirection table has
2354         * 128-entries in 32 registers
2355          */
2356         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2357                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2358                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2359                 else
2360                         mask = (uint8_t)((reta_conf->mask_hi >>
2361                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2362                 if (mask != 0) {
2363                         reta = 0;
2364                         if (mask != 0xF)
2365                                 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2366
2367                         for (j = 0; j < 4; j++) {
2368                                 if (mask & (0x1 << j)) {
2369                                         if (mask != 0xF)
2370                                                 reta &= ~(0xFF << 8 * j);
2371                                         reta |= reta_conf->reta[i + j] << 8*j;
2372                                 }
2373                         }
2374                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2375                 }
2376         }
2377
2378         return 0;
2379 }
2380
2381 static int
2382 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2383                                 struct rte_eth_rss_reta *reta_conf)
2384 {
2385         uint8_t i,j,mask;
2386         uint32_t reta;
2387         struct ixgbe_hw *hw =
2388                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389
2390         PMD_INIT_FUNC_TRACE();
2391         /*
2392          * Read Redirection Table RETA[n],n=0...31,The redirection table has
2393          * 128-entries in 32 registers
2394          */
2395         for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2396                 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2397                         mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2398                 else
2399                         mask = (uint8_t)((reta_conf->mask_hi >>
2400                                 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2401
2402                 if (mask != 0) {
2403                         reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2404                         for (j = 0; j < 4; j++) {
2405                                 if (mask & (0x1 << j))
2406                                         reta_conf->reta[i + j] =
2407                                                 (uint8_t)((reta >> 8 * j) & 0xFF);
2408                         }
2409                 }
2410         }
2411
2412         return 0;
2413 }
2414
2415 static void
2416 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2417                                 uint32_t index, uint32_t pool)
2418 {
2419         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2420         uint32_t enable_addr = 1;
2421
2422         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2423 }
2424
2425 static void
2426 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2427 {
2428         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2429
2430         ixgbe_clear_rar(hw, index);
2431 }
2432
2433 /*
2434  * Virtual Function operations
2435  */
2436 static void
2437 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2438 {
2439         PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2440
2441         /* Clear interrupt mask to stop from interrupts being generated */
2442         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2443
2444         IXGBE_WRITE_FLUSH(hw);
2445 }
2446
2447 static int
2448 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2449 {
2450         struct rte_eth_conf* conf = &dev->data->dev_conf;
2451
2452         PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2453                 dev->data->port_id);
2454
2455         /*
2456          * VF has no ability to enable/disable HW CRC
2457          * Keep the persistent behavior the same as Host PF
2458          */
2459 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2460         if (!conf->rxmode.hw_strip_crc) {
2461                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2462                 conf->rxmode.hw_strip_crc = 1;
2463         }
2464 #else
2465         if (conf->rxmode.hw_strip_crc) {
2466                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2467                 conf->rxmode.hw_strip_crc = 0;
2468         }
2469 #endif
2470
2471         return 0;
2472 }
2473
2474 static int
2475 ixgbevf_dev_start(struct rte_eth_dev *dev)
2476 {
2477         struct ixgbe_hw *hw =
2478                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2479         int err, mask = 0;
2480
2481         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2482
2483         hw->mac.ops.reset_hw(hw);
2484
2485         ixgbevf_dev_tx_init(dev);
2486
2487         /* This can fail when allocating mbufs for descriptor rings */
2488         err = ixgbevf_dev_rx_init(dev);
2489         if (err) {
2490                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2491                 ixgbe_dev_clear_queues(dev);
2492                 return err;
2493         }
2494
2495         /* Set vfta */
2496         ixgbevf_set_vfta_all(dev,1);
2497
2498         /* Set HW strip */
2499         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2500                 ETH_VLAN_EXTEND_MASK;
2501         ixgbevf_vlan_offload_set(dev, mask);
2502
2503         ixgbevf_dev_rxtx_start(dev);
2504
2505         return 0;
2506 }
2507
2508 static void
2509 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2510 {
2511         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2512
2513         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2514
2515         hw->adapter_stopped = TRUE;
2516         ixgbe_stop_adapter(hw);
2517
2518         /*
2519           * Clear what we set, but we still keep shadow_vfta to
2520           * restore after device starts
2521           */
2522         ixgbevf_set_vfta_all(dev,0);
2523
2524         ixgbe_dev_clear_queues(dev);
2525 }
2526
2527 static void
2528 ixgbevf_dev_close(struct rte_eth_dev *dev)
2529 {
2530         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531
2532         PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2533
2534         ixgbe_reset_hw(hw);
2535
2536         ixgbevf_dev_stop(dev);
2537
2538         /* reprogram the RAR[0] in case user changed it. */
2539         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2540 }
2541
2542 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2543 {
2544         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2545         struct ixgbe_vfta * shadow_vfta =
2546                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2547         int i = 0, j = 0, vfta = 0, mask = 1;
2548
2549         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2550                 vfta = shadow_vfta->vfta[i];
2551                 if(vfta){
2552                         mask = 1;
2553                         for (j = 0; j < 32; j++){
2554                                 if(vfta & mask)
2555                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2556                                 mask<<=1;
2557                         }
2558                 }
2559         }
2560
2561 }
2562
2563 static int
2564 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2565 {
2566         struct ixgbe_hw *hw =
2567                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2568         struct ixgbe_vfta * shadow_vfta =
2569                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2570         uint32_t vid_idx = 0;
2571         uint32_t vid_bit = 0;
2572         int ret = 0;
2573
2574         PMD_INIT_FUNC_TRACE();
2575
2576         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2577         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2578         if(ret){
2579                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2580                 return ret;
2581         }
2582         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2583         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2584
2585         /* Save what we set and retore it after device reset */
2586         if (on)
2587                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2588         else
2589                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2590
2591         return 0;
2592 }
2593
2594 static void
2595 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2596 {
2597         struct ixgbe_hw *hw =
2598                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2599         uint32_t ctrl;
2600
2601         PMD_INIT_FUNC_TRACE();
2602
2603         if(queue >= hw->mac.max_rx_queues)
2604                 return;
2605
2606         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2607         if(on)
2608                 ctrl |= IXGBE_RXDCTL_VME;
2609         else
2610                 ctrl &= ~IXGBE_RXDCTL_VME;
2611         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2612
2613         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2614 }
2615
2616 static void
2617 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2618 {
2619         struct ixgbe_hw *hw =
2620                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2621         uint16_t i;
2622         int on = 0;
2623
2624         /* VF function only support hw strip feature, others are not support */
2625         if(mask & ETH_VLAN_STRIP_MASK){
2626                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2627
2628                 for(i=0; i < hw->mac.max_rx_queues; i++)
2629                         ixgbevf_vlan_strip_queue_set(dev,i,on);
2630         }
2631 }
2632
2633 static int
2634 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2635 {
2636         uint32_t reg_val;
2637
2638         /* we only need to do this if VMDq is enabled */
2639         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2640         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2641                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2642                 return (-1);
2643         }
2644
2645         return 0;
2646 }
2647
2648 static uint32_t
2649 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2650 {
2651         uint32_t vector = 0;
2652         switch (hw->mac.mc_filter_type) {
2653         case 0:   /* use bits [47:36] of the address */
2654                 vector = ((uc_addr->addr_bytes[4] >> 4) |
2655                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2656                 break;
2657         case 1:   /* use bits [46:35] of the address */
2658                 vector = ((uc_addr->addr_bytes[4] >> 3) |
2659                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2660                 break;
2661         case 2:   /* use bits [45:34] of the address */
2662                 vector = ((uc_addr->addr_bytes[4] >> 2) |
2663                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2664                 break;
2665         case 3:   /* use bits [43:32] of the address */
2666                 vector = ((uc_addr->addr_bytes[4]) |
2667                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2668                 break;
2669         default:  /* Invalid mc_filter_type */
2670                 break;
2671         }
2672
2673         /* vector can only be 12-bits or boundary will be exceeded */
2674         vector &= 0xFFF;
2675         return vector;
2676 }
2677
2678 static int
2679 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2680                                uint8_t on)
2681 {
2682         uint32_t vector;
2683         uint32_t uta_idx;
2684         uint32_t reg_val;
2685         uint32_t uta_shift;
2686         uint32_t rc;
2687         const uint32_t ixgbe_uta_idx_mask = 0x7F;
2688         const uint32_t ixgbe_uta_bit_shift = 5;
2689         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2690         const uint32_t bit1 = 0x1;
2691
2692         struct ixgbe_hw *hw =
2693                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2694         struct ixgbe_uta_info *uta_info =
2695                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2696
2697         /* The UTA table only exists on 82599 hardware and newer */
2698         if (hw->mac.type < ixgbe_mac_82599EB)
2699                 return (-ENOTSUP);
2700
2701         vector = ixgbe_uta_vector(hw,mac_addr);
2702         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2703         uta_shift = vector & ixgbe_uta_bit_mask;
2704
2705         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2706         if(rc == on)
2707                 return 0;
2708
2709         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2710         if (on) {
2711                 uta_info->uta_in_use++;
2712                 reg_val |= (bit1 << uta_shift);
2713                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2714         } else {
2715                 uta_info->uta_in_use--;
2716                 reg_val &= ~(bit1 << uta_shift);
2717                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2718         }
2719
2720         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2721
2722         if (uta_info->uta_in_use > 0)
2723                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2724                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2725         else
2726                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2727
2728         return 0;
2729 }
2730
2731 static int
2732 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2733 {
2734         int i;
2735         struct ixgbe_hw *hw =
2736                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2737         struct ixgbe_uta_info *uta_info =
2738                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2739
2740         /* The UTA table only exists on 82599 hardware and newer */
2741         if (hw->mac.type < ixgbe_mac_82599EB)
2742                 return (-ENOTSUP);
2743
2744         if(on) {
2745                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2746                         uta_info->uta_shadow[i] = ~0;
2747                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2748                 }
2749         } else {
2750                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2751                         uta_info->uta_shadow[i] = 0;
2752                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2753                 }
2754         }
2755         return 0;
2756
2757 }
2758 static int
2759 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2760                                uint16_t rx_mask, uint8_t on)
2761 {
2762         int val = 0;
2763
2764         struct ixgbe_hw *hw =
2765                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2766         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2767
2768         if (hw->mac.type == ixgbe_mac_82598EB) {
2769                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2770                         " on 82599 hardware and newer\n");
2771                 return (-ENOTSUP);
2772         }
2773         if (ixgbe_vmdq_mode_check(hw) < 0)
2774                 return (-ENOTSUP);
2775
2776         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
2777                 val |= IXGBE_VMOLR_AUPE;
2778         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
2779                 val |= IXGBE_VMOLR_ROMPE;
2780         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
2781                 val |= IXGBE_VMOLR_ROPE;
2782         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
2783                 val |= IXGBE_VMOLR_BAM;
2784         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
2785                 val |= IXGBE_VMOLR_MPE;
2786
2787         if (on)
2788                 vmolr |= val;
2789         else
2790                 vmolr &= ~val;
2791
2792         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
2793
2794         return 0;
2795 }
2796
2797 static int
2798 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2799 {
2800         uint32_t reg,addr;
2801         uint32_t val;
2802         const uint8_t bit1 = 0x1;
2803
2804         struct ixgbe_hw *hw =
2805                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2806
2807         if (ixgbe_vmdq_mode_check(hw) < 0)
2808                 return (-ENOTSUP);
2809
2810         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
2811         reg = IXGBE_READ_REG(hw, addr);
2812         val = bit1 << pool;
2813
2814         if (on)
2815                 reg |= val;
2816         else
2817                 reg &= ~val;
2818
2819         IXGBE_WRITE_REG(hw, addr,reg);
2820
2821         return 0;
2822 }
2823
2824 static int
2825 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2826 {
2827         uint32_t reg,addr;
2828         uint32_t val;
2829         const uint8_t bit1 = 0x1;
2830
2831         struct ixgbe_hw *hw =
2832                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2833
2834         if (ixgbe_vmdq_mode_check(hw) < 0)
2835                 return (-ENOTSUP);
2836
2837         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
2838         reg = IXGBE_READ_REG(hw, addr);
2839         val = bit1 << pool;
2840
2841         if (on)
2842                 reg |= val;
2843         else
2844                 reg &= ~val;
2845
2846         IXGBE_WRITE_REG(hw, addr,reg);
2847
2848         return 0;
2849 }
2850
2851 static int
2852 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
2853                         uint64_t pool_mask, uint8_t vlan_on)
2854 {
2855         int ret = 0;
2856         uint16_t pool_idx;
2857         struct ixgbe_hw *hw =
2858                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859
2860         if (ixgbe_vmdq_mode_check(hw) < 0)
2861                 return (-ENOTSUP);
2862         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
2863                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
2864                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
2865                         if (ret < 0)
2866                                 return ret;
2867         }
2868
2869         return ret;
2870 }
2871
2872 static int
2873 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
2874                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
2875                         uint8_t rule_id, uint8_t on)
2876 {
2877         uint32_t mr_ctl,vlvf;
2878         uint32_t mp_lsb = 0;
2879         uint32_t mv_msb = 0;
2880         uint32_t mv_lsb = 0;
2881         uint32_t mp_msb = 0;
2882         uint8_t i = 0;
2883         int reg_index = 0;
2884         uint64_t vlan_mask = 0;
2885
2886         const uint8_t pool_mask_offset = 32;
2887         const uint8_t vlan_mask_offset = 32;
2888         const uint8_t dst_pool_offset = 8;
2889         const uint8_t rule_mr_offset  = 4;
2890         const uint8_t mirror_rule_mask= 0x0F;
2891
2892         struct ixgbe_mirror_info *mr_info =
2893                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2894         struct ixgbe_hw *hw =
2895                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896
2897         if (ixgbe_vmdq_mode_check(hw) < 0)
2898                 return (-ENOTSUP);
2899
2900         /* Check if vlan mask is valid */
2901         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
2902                 if (mirror_conf->vlan.vlan_mask == 0)
2903                         return (-EINVAL);
2904         }
2905
2906         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
2907         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2908                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
2909                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
2910                                 /* search vlan id related pool vlan filter index */
2911                                 reg_index = ixgbe_find_vlvf_slot(hw,
2912                                                 mirror_conf->vlan.vlan_id[i]);
2913                                 if(reg_index < 0)
2914                                         return (-EINVAL);
2915                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
2916                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
2917                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
2918                                                 == mirror_conf->vlan.vlan_id[i]))
2919                                         vlan_mask |= (1ULL << reg_index);
2920                                 else
2921                                         return (-EINVAL);
2922                         }
2923                 }
2924
2925                 if (on) {
2926                         mv_lsb = vlan_mask & 0xFFFFFFFF;
2927                         mv_msb = vlan_mask >> vlan_mask_offset;
2928
2929                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
2930                                                 mirror_conf->vlan.vlan_mask;
2931                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
2932                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
2933                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
2934                                                 mirror_conf->vlan.vlan_id[i];
2935                         }
2936                 } else {
2937                         mv_lsb = 0;
2938                         mv_msb = 0;
2939                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
2940                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
2941                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
2942                 }
2943         }
2944
2945         /*
2946          * if enable pool mirror, write related pool mask register,if disable
2947          * pool mirror, clear PFMRVM register
2948          */
2949         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2950                 if (on) {
2951                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
2952                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
2953                         mr_info->mr_conf[rule_id].pool_mask =
2954                                         mirror_conf->pool_mask;
2955
2956                 } else {
2957                         mp_lsb = 0;
2958                         mp_msb = 0;
2959                         mr_info->mr_conf[rule_id].pool_mask = 0;
2960                 }
2961         }
2962
2963         /* read  mirror control register and recalculate it */
2964         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
2965
2966         if (on) {
2967                 mr_ctl |= mirror_conf->rule_type_mask;
2968                 mr_ctl &= mirror_rule_mask;
2969                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
2970         } else
2971                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
2972
2973         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
2974         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
2975
2976         /* write mirrror control  register */
2977         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
2978
2979         /* write pool mirrror control  register */
2980         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2981                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
2982                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
2983                                 mp_msb);
2984         }
2985         /* write VLAN mirrror control  register */
2986         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2987                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
2988                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
2989                                 mv_msb);
2990         }
2991
2992         return 0;
2993 }
2994
2995 static int
2996 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
2997 {
2998         int mr_ctl = 0;
2999         uint32_t lsb_val = 0;
3000         uint32_t msb_val = 0;
3001         const uint8_t rule_mr_offset = 4;
3002
3003         struct ixgbe_hw *hw =
3004                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3005         struct ixgbe_mirror_info *mr_info =
3006                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3007
3008         if (ixgbe_vmdq_mode_check(hw) < 0)
3009                 return (-ENOTSUP);
3010
3011         memset(&mr_info->mr_conf[rule_id], 0,
3012                 sizeof(struct rte_eth_vmdq_mirror_conf));
3013
3014         /* clear PFVMCTL register */
3015         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3016
3017         /* clear pool mask register */
3018         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3019         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3020
3021         /* clear vlan mask register */
3022         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3023         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3024
3025         return 0;
3026 }