4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "ixgbe/ixgbe_dcb.h"
37 #include "ixgbe/ixgbe_dcb_82599.h"
38 #include "ixgbe/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
41 /* need update link, bit flag */
42 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
43 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
46 * Defines that were not part of ixgbe_type.h as they are not used by the
49 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
50 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
51 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
52 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
53 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
54 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
55 #define IXGBE_NB_STAT_MAPPING_REGS 32
56 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
57 #define IXGBE_VFTA_SIZE 128
58 #define IXGBE_VLAN_TAG_SIZE 4
59 #define IXGBE_MAX_RX_QUEUE_NUM 128
61 #define NBBY 8 /* number of bits in a byte */
63 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
65 /* Loopback operation modes */
66 /* 82599 specific loopback operation types */
67 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
68 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
70 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
72 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
73 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
74 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
76 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
78 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
79 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
80 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
81 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
83 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
84 #define IXGBE_ETQF_SHIFT 16
85 #define IXGBE_ETQF_UP_EN 0x00080000
86 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
87 #define IXGBE_ETQF_MAX_PRI 7
89 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
90 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
91 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
93 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
94 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
95 #define IXGBE_L34T_IMIR_LLI 0x00100000
96 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
97 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
98 #define IXGBE_5TUPLE_MAX_PRI 7
99 #define IXGBE_5TUPLE_MIN_PRI 1
102 * Information about the fdir mode.
105 struct ixgbe_hw_fdir_mask {
106 uint16_t vlan_tci_mask;
107 uint32_t src_ipv4_mask;
108 uint32_t dst_ipv4_mask;
109 uint16_t src_ipv6_mask;
110 uint16_t dst_ipv6_mask;
111 uint16_t src_port_mask;
112 uint16_t dst_port_mask;
113 uint16_t flex_bytes_mask;
116 struct ixgbe_hw_fdir_info {
117 struct ixgbe_hw_fdir_mask mask;
118 uint8_t flex_bytes_offset;
129 /* structure for interrupt relative data */
130 struct ixgbe_interrupt {
135 struct ixgbe_stat_mapping_registers {
136 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
137 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
141 uint32_t vfta[IXGBE_VFTA_SIZE];
144 struct ixgbe_hwstrip {
145 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
149 * VF data which used by PF host only
151 #define IXGBE_MAX_VF_MC_ENTRIES 30
152 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
153 #define IXGBE_MAX_UTA 128
155 struct ixgbe_uta_info {
156 uint8_t uc_filter_type;
158 uint32_t uta_shadow[IXGBE_MAX_UTA];
161 struct ixgbe_mirror_info {
162 struct rte_eth_vmdq_mirror_conf mr_conf[ETH_VMDQ_NUM_MIRROR_RULE];
163 /**< store PF mirror rules configuration*/
166 struct ixgbe_vf_info {
167 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
168 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
169 uint16_t num_vf_mc_hashes;
170 uint16_t default_vf_vlan_id;
171 uint16_t vlans_enabled;
173 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
175 uint8_t spoofchk_enabled;
180 * Possible l4type of 5tuple filters.
182 enum ixgbe_5tuple_protocol {
183 IXGBE_FILTER_PROTOCOL_TCP = 0,
184 IXGBE_FILTER_PROTOCOL_UDP,
185 IXGBE_FILTER_PROTOCOL_SCTP,
186 IXGBE_FILTER_PROTOCOL_NONE,
189 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
191 struct ixgbe_5tuple_filter_info {
196 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
197 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
198 used when more than one filter matches. */
199 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
200 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
201 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
202 src_port_mask:1, /* if mask is 1b, do not compare src port. */
203 proto_mask:1; /* if mask is 1b, do not compare protocol. */
206 /* 5tuple filter structure */
207 struct ixgbe_5tuple_filter {
208 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
209 uint16_t index; /* the index of 5tuple filter */
210 struct ixgbe_5tuple_filter_info filter_info;
211 uint16_t queue; /* rx queue assigned to */
214 #define IXGBE_5TUPLE_ARRAY_SIZE \
215 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
216 (sizeof(uint32_t) * NBBY))
219 * Structure to store filters' info.
221 struct ixgbe_filter_info {
222 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
223 /* store used ethertype filters*/
224 uint16_t ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
225 /* Bit mask for every used 5tuple filter */
226 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
227 struct ixgbe_5tuple_filter_list fivetuple_list;
231 * Structure to store private data for each driver instance (for each port).
233 struct ixgbe_adapter {
235 struct ixgbe_hw_stats stats;
236 struct ixgbe_hw_fdir_info fdir;
237 struct ixgbe_interrupt intr;
238 struct ixgbe_stat_mapping_registers stat_mappings;
239 struct ixgbe_vfta shadow_vfta;
240 struct ixgbe_hwstrip hwstrip;
241 struct ixgbe_dcb_config dcb_config;
242 struct ixgbe_mirror_info mr_data;
243 struct ixgbe_vf_info *vfdata;
244 struct ixgbe_uta_info uta_info;
245 #ifdef RTE_NIC_BYPASS
246 struct ixgbe_bypass_info bps;
247 #endif /* RTE_NIC_BYPASS */
248 struct ixgbe_filter_info filter;
251 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
252 (&((struct ixgbe_adapter *)adapter)->hw)
254 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
255 (&((struct ixgbe_adapter *)adapter)->stats)
257 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
258 (&((struct ixgbe_adapter *)adapter)->intr)
260 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
261 (&((struct ixgbe_adapter *)adapter)->fdir)
263 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
264 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
266 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
267 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
269 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
270 (&((struct ixgbe_adapter *)adapter)->hwstrip)
272 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
273 (&((struct ixgbe_adapter *)adapter)->dcb_config)
275 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
276 (&((struct ixgbe_adapter *)adapter)->vfdata)
278 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
279 (&((struct ixgbe_adapter *)adapter)->mr_data)
281 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
282 (&((struct ixgbe_adapter *)adapter)->uta_info)
284 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
285 (&((struct ixgbe_adapter *)adapter)->filter)
288 * RX/TX function prototypes
290 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
292 void ixgbe_dev_rx_queue_release(void *rxq);
294 void ixgbe_dev_tx_queue_release(void *txq);
296 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
297 uint16_t nb_rx_desc, unsigned int socket_id,
298 const struct rte_eth_rxconf *rx_conf,
299 struct rte_mempool *mb_pool);
301 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
302 uint16_t nb_tx_desc, unsigned int socket_id,
303 const struct rte_eth_txconf *tx_conf);
305 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
306 uint16_t rx_queue_id);
308 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
310 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
312 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
314 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
316 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
318 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
320 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
322 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
324 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
326 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
328 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
330 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
333 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
334 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
338 uint16_t ixgbe_recv_scattered_pkts(void *rx_queue,
339 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
341 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
344 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
347 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
348 struct rte_eth_rss_conf *rss_conf);
350 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
351 struct rte_eth_rss_conf *rss_conf);
354 * Flow director function prototypes
356 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
358 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
361 * misc function prototypes
363 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
365 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
367 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
369 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
371 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
373 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
375 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
377 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
379 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
380 enum rte_filter_op filter_op, void *arg);
381 #endif /* _IXGBE_ETHDEV_H_ */