4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
55 #include <rte_tailq.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
80 #include "ixgbe_rxtx.h"
82 #define IXGBE_RSS_OFFLOAD_ALL ( \
88 ETH_RSS_IPV6_TCP_EX | \
93 /* Bit Mask to indicate what bits required for building TX context */
94 #define IXGBE_TX_OFFLOAD_MASK ( \
99 static inline struct rte_mbuf *
100 rte_rxmbuf_alloc(struct rte_mempool *mp)
104 m = __rte_mbuf_raw_alloc(mp);
105 __rte_mbuf_sanity_check_raw(m, 0);
111 #define RTE_PMD_USE_PREFETCH
114 #ifdef RTE_PMD_USE_PREFETCH
116 * Prefetch a cache line into all cache levels.
118 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
120 #define rte_ixgbe_prefetch(p) do {} while(0)
123 /*********************************************************************
127 **********************************************************************/
130 * Check for descriptors with their DD bit set and free mbufs.
131 * Return the total number of buffers freed.
133 static inline int __attribute__((always_inline))
134 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
136 struct igb_tx_entry *txep;
140 /* check DD bit on threshold descriptor */
141 status = txq->tx_ring[txq->tx_next_dd].wb.status;
142 if (! (status & IXGBE_ADVTXD_STAT_DD))
146 * first buffer to free from S/W ring is at index
147 * tx_next_dd - (tx_rs_thresh-1)
149 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
151 /* free buffers one at a time */
152 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
153 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
154 txep->mbuf->next = NULL;
155 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
159 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
160 rte_pktmbuf_free_seg(txep->mbuf);
165 /* buffers were freed, update counters */
166 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
167 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
168 if (txq->tx_next_dd >= txq->nb_tx_desc)
169 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
171 return txq->tx_rs_thresh;
174 /* Populate 4 descriptors with data from 4 mbufs */
176 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
178 uint64_t buf_dma_addr;
182 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
183 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
184 pkt_len = (*pkts)->data_len;
186 /* write data to descriptor */
187 txdp->read.buffer_addr = buf_dma_addr;
188 txdp->read.cmd_type_len =
189 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
190 txdp->read.olinfo_status =
191 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
192 rte_prefetch0(&(*pkts)->pool);
196 /* Populate 1 descriptor with data from 1 mbuf */
198 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
200 uint64_t buf_dma_addr;
203 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
204 pkt_len = (*pkts)->data_len;
206 /* write data to descriptor */
207 txdp->read.buffer_addr = buf_dma_addr;
208 txdp->read.cmd_type_len =
209 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
210 txdp->read.olinfo_status =
211 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
212 rte_prefetch0(&(*pkts)->pool);
216 * Fill H/W descriptor ring with mbuf data.
217 * Copy mbuf pointers to the S/W ring.
220 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
223 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
224 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
225 const int N_PER_LOOP = 4;
226 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
227 int mainpart, leftover;
231 * Process most of the packets in chunks of N pkts. Any
232 * leftover packets will get processed one at a time.
234 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
235 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
236 for (i = 0; i < mainpart; i += N_PER_LOOP) {
237 /* Copy N mbuf pointers to the S/W ring */
238 for (j = 0; j < N_PER_LOOP; ++j) {
239 (txep + i + j)->mbuf = *(pkts + i + j);
241 tx4(txdp + i, pkts + i);
244 if (unlikely(leftover > 0)) {
245 for (i = 0; i < leftover; ++i) {
246 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
247 tx1(txdp + mainpart + i, pkts + mainpart + i);
252 static inline uint16_t
253 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
256 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
257 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
261 * Begin scanning the H/W ring for done descriptors when the
262 * number of available descriptors drops below tx_free_thresh. For
263 * each done descriptor, free the associated buffer.
265 if (txq->nb_tx_free < txq->tx_free_thresh)
266 ixgbe_tx_free_bufs(txq);
268 /* Only use descriptors that are available */
269 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
270 if (unlikely(nb_pkts == 0))
273 /* Use exactly nb_pkts descriptors */
274 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
277 * At this point, we know there are enough descriptors in the
278 * ring to transmit all the packets. This assumes that each
279 * mbuf contains a single segment, and that no new offloads
280 * are expected, which would require a new context descriptor.
284 * See if we're going to wrap-around. If so, handle the top
285 * of the descriptor ring first, then do the bottom. If not,
286 * the processing looks just like the "bottom" part anyway...
288 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
289 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
290 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
293 * We know that the last descriptor in the ring will need to
294 * have its RS bit set because tx_rs_thresh has to be
295 * a divisor of the ring size
297 tx_r[txq->tx_next_rs].read.cmd_type_len |=
298 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
299 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
304 /* Fill H/W descriptor ring with mbuf data */
305 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
306 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
309 * Determine if RS bit should be set
310 * This is what we actually want:
311 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
312 * but instead of subtracting 1 and doing >=, we can just do
313 * greater than without subtracting.
315 if (txq->tx_tail > txq->tx_next_rs) {
316 tx_r[txq->tx_next_rs].read.cmd_type_len |=
317 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
318 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
320 if (txq->tx_next_rs >= txq->nb_tx_desc)
321 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
325 * Check for wrap-around. This would only happen if we used
326 * up to the last descriptor in the ring, no more, no less.
328 if (txq->tx_tail >= txq->nb_tx_desc)
331 /* update tail pointer */
333 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
339 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
344 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
345 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
346 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
348 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
352 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
353 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
354 nb_tx = (uint16_t)(nb_tx + ret);
355 nb_pkts = (uint16_t)(nb_pkts - ret);
364 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
365 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
366 uint64_t ol_flags, uint32_t vlan_macip_lens)
368 uint32_t type_tucmd_mlhl;
369 uint32_t mss_l4len_idx;
373 ctx_idx = txq->ctx_curr;
377 if (ol_flags & PKT_TX_VLAN_PKT) {
378 cmp_mask |= TX_VLAN_CMP_MASK;
381 if (ol_flags & PKT_TX_IP_CKSUM) {
382 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
383 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
386 /* Specify which HW CTX to upload. */
387 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
388 switch (ol_flags & PKT_TX_L4_MASK) {
389 case PKT_TX_UDP_CKSUM:
390 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
391 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
392 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
393 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
395 case PKT_TX_TCP_CKSUM:
396 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
397 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
398 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
399 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
401 case PKT_TX_SCTP_CKSUM:
402 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
403 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
404 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
405 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
408 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
409 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
413 txq->ctx_cache[ctx_idx].flags = ol_flags;
414 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
415 txq->ctx_cache[ctx_idx].vlan_macip_lens.data =
416 vlan_macip_lens & cmp_mask;
418 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
419 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
420 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
421 ctx_txd->seqnum_seed = 0;
425 * Check which hardware context can be used. Use the existing match
426 * or create a new context descriptor.
428 static inline uint32_t
429 what_advctx_update(struct igb_tx_queue *txq, uint64_t flags,
430 uint32_t vlan_macip_lens)
432 /* If match with the current used context */
433 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
434 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
435 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
436 return txq->ctx_curr;
439 /* What if match with the next context */
441 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
442 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==
443 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
444 return txq->ctx_curr;
447 /* Mismatch, use the previous context */
448 return (IXGBE_CTX_NUM);
451 static inline uint32_t
452 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
454 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
455 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
458 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
459 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
463 static inline uint32_t
464 tx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags)
466 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
467 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
470 /* Default RS bit threshold values */
471 #ifndef DEFAULT_TX_RS_THRESH
472 #define DEFAULT_TX_RS_THRESH 32
474 #ifndef DEFAULT_TX_FREE_THRESH
475 #define DEFAULT_TX_FREE_THRESH 32
478 /* Reset transmit descriptors after they have been used */
480 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
482 struct igb_tx_entry *sw_ring = txq->sw_ring;
483 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
484 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
485 uint16_t nb_tx_desc = txq->nb_tx_desc;
486 uint16_t desc_to_clean_to;
487 uint16_t nb_tx_to_clean;
489 /* Determine the last descriptor needing to be cleaned */
490 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
491 if (desc_to_clean_to >= nb_tx_desc)
492 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
494 /* Check to make sure the last descriptor to clean is done */
495 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
496 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
498 PMD_TX_FREE_LOG(DEBUG,
499 "TX descriptor %4u is not done"
500 "(port=%d queue=%d)",
502 txq->port_id, txq->queue_id);
503 /* Failed to clean any descriptors, better luck next time */
507 /* Figure out how many descriptors will be cleaned */
508 if (last_desc_cleaned > desc_to_clean_to)
509 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
512 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
515 PMD_TX_FREE_LOG(DEBUG,
516 "Cleaning %4u TX descriptors: %4u to %4u "
517 "(port=%d queue=%d)",
518 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
519 txq->port_id, txq->queue_id);
522 * The last descriptor to clean is done, so that means all the
523 * descriptors from the last descriptor that was cleaned
524 * up to the last descriptor with the RS bit set
525 * are done. Only reset the threshold descriptor.
527 txr[desc_to_clean_to].wb.status = 0;
529 /* Update the txq to reflect the last descriptor that was cleaned */
530 txq->last_desc_cleaned = desc_to_clean_to;
531 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
538 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
541 struct igb_tx_queue *txq;
542 struct igb_tx_entry *sw_ring;
543 struct igb_tx_entry *txe, *txn;
544 volatile union ixgbe_adv_tx_desc *txr;
545 volatile union ixgbe_adv_tx_desc *txd;
546 struct rte_mbuf *tx_pkt;
547 struct rte_mbuf *m_seg;
548 union ixgbe_vlan_macip vlan_macip_lens;
549 uint64_t buf_dma_addr;
550 uint32_t olinfo_status;
551 uint32_t cmd_type_len;
564 sw_ring = txq->sw_ring;
566 tx_id = txq->tx_tail;
567 txe = &sw_ring[tx_id];
569 /* Determine if the descriptor ring needs to be cleaned. */
570 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
571 ixgbe_xmit_cleanup(txq);
574 rte_prefetch0(&txe->mbuf->pool);
577 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
580 pkt_len = tx_pkt->pkt_len;
583 * Determine how many (if any) context descriptors
584 * are needed for offload functionality.
586 ol_flags = tx_pkt->ol_flags;
588 /* If hardware offload required */
589 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
591 vlan_macip_lens.f.vlan_tci = tx_pkt->vlan_tci;
592 vlan_macip_lens.f.l2_l3_len = tx_pkt->l2_l3_len;
594 /* If new context need be built or reuse the exist ctx. */
595 ctx = what_advctx_update(txq, tx_ol_req,
596 vlan_macip_lens.data);
597 /* Only allocate context descriptor if required*/
598 new_ctx = (ctx == IXGBE_CTX_NUM);
603 * Keep track of how many descriptors are used this loop
604 * This will always be the number of segments + the number of
605 * Context descriptors required to transmit the packet
607 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
610 * The number of descriptors that must be allocated for a
611 * packet is the number of segments of that packet, plus 1
612 * Context Descriptor for the hardware offload, if any.
613 * Determine the last TX descriptor to allocate in the TX ring
614 * for the packet, starting from the current position (tx_id)
617 tx_last = (uint16_t) (tx_id + nb_used - 1);
620 if (tx_last >= txq->nb_tx_desc)
621 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
623 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
624 " tx_first=%u tx_last=%u",
625 (unsigned) txq->port_id,
626 (unsigned) txq->queue_id,
632 * Make sure there are enough TX descriptors available to
633 * transmit the entire packet.
634 * nb_used better be less than or equal to txq->tx_rs_thresh
636 if (nb_used > txq->nb_tx_free) {
637 PMD_TX_FREE_LOG(DEBUG,
638 "Not enough free TX descriptors "
639 "nb_used=%4u nb_free=%4u "
640 "(port=%d queue=%d)",
641 nb_used, txq->nb_tx_free,
642 txq->port_id, txq->queue_id);
644 if (ixgbe_xmit_cleanup(txq) != 0) {
645 /* Could not clean any descriptors */
651 /* nb_used better be <= txq->tx_rs_thresh */
652 if (unlikely(nb_used > txq->tx_rs_thresh)) {
653 PMD_TX_FREE_LOG(DEBUG,
654 "The number of descriptors needed to "
655 "transmit the packet exceeds the "
656 "RS bit threshold. This will impact "
658 "nb_used=%4u nb_free=%4u "
660 "(port=%d queue=%d)",
661 nb_used, txq->nb_tx_free,
663 txq->port_id, txq->queue_id);
665 * Loop here until there are enough TX
666 * descriptors or until the ring cannot be
669 while (nb_used > txq->nb_tx_free) {
670 if (ixgbe_xmit_cleanup(txq) != 0) {
672 * Could not clean any
684 * By now there are enough free TX descriptors to transmit
689 * Set common flags of all TX Data Descriptors.
691 * The following bits must be set in all Data Descriptors:
692 * - IXGBE_ADVTXD_DTYP_DATA
693 * - IXGBE_ADVTXD_DCMD_DEXT
695 * The following bits must be set in the first Data Descriptor
696 * and are ignored in the other ones:
697 * - IXGBE_ADVTXD_DCMD_IFCS
698 * - IXGBE_ADVTXD_MAC_1588
699 * - IXGBE_ADVTXD_DCMD_VLE
701 * The following bits must only be set in the last Data
703 * - IXGBE_TXD_CMD_EOP
705 * The following bits can be set in any Data Descriptor, but
706 * are only set in the last Data Descriptor:
709 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
710 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
711 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
712 #ifdef RTE_LIBRTE_IEEE1588
713 if (ol_flags & PKT_TX_IEEE1588_TMST)
714 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
719 * Setup the TX Advanced Context Descriptor if required
722 volatile struct ixgbe_adv_tx_context_desc *
725 ctx_txd = (volatile struct
726 ixgbe_adv_tx_context_desc *)
729 txn = &sw_ring[txe->next_id];
730 rte_prefetch0(&txn->mbuf->pool);
732 if (txe->mbuf != NULL) {
733 rte_pktmbuf_free_seg(txe->mbuf);
737 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
738 vlan_macip_lens.data);
740 txe->last_id = tx_last;
741 tx_id = txe->next_id;
746 * Setup the TX Advanced Data Descriptor,
747 * This path will go through
748 * whatever new/reuse the context descriptor
750 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
751 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
752 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
758 txn = &sw_ring[txe->next_id];
759 rte_prefetch0(&txn->mbuf->pool);
761 if (txe->mbuf != NULL)
762 rte_pktmbuf_free_seg(txe->mbuf);
766 * Set up Transmit Data Descriptor.
768 slen = m_seg->data_len;
769 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
770 txd->read.buffer_addr =
771 rte_cpu_to_le_64(buf_dma_addr);
772 txd->read.cmd_type_len =
773 rte_cpu_to_le_32(cmd_type_len | slen);
774 txd->read.olinfo_status =
775 rte_cpu_to_le_32(olinfo_status);
776 txe->last_id = tx_last;
777 tx_id = txe->next_id;
780 } while (m_seg != NULL);
783 * The last packet data descriptor needs End Of Packet (EOP)
785 cmd_type_len |= IXGBE_TXD_CMD_EOP;
786 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
787 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
789 /* Set RS bit only on threshold packets' last descriptor */
790 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
791 PMD_TX_FREE_LOG(DEBUG,
792 "Setting RS bit on TXD id="
793 "%4u (port=%d queue=%d)",
794 tx_last, txq->port_id, txq->queue_id);
796 cmd_type_len |= IXGBE_TXD_CMD_RS;
798 /* Update txq RS bit counters */
801 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
807 * Set the Transmit Descriptor Tail (TDT)
809 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
810 (unsigned) txq->port_id, (unsigned) txq->queue_id,
811 (unsigned) tx_id, (unsigned) nb_tx);
812 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
813 txq->tx_tail = tx_id;
818 /*********************************************************************
822 **********************************************************************/
823 static inline uint64_t
824 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
828 static uint64_t ip_pkt_types_map[16] = {
829 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
830 PKT_RX_IPV6_HDR, 0, 0, 0,
831 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
832 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
835 static uint64_t ip_rss_types_map[16] = {
836 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
837 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
838 PKT_RX_RSS_HASH, 0, 0, 0,
839 0, 0, 0, PKT_RX_FDIR,
842 #ifdef RTE_LIBRTE_IEEE1588
843 static uint64_t ip_pkt_etqf_map[8] = {
844 0, 0, 0, PKT_RX_IEEE1588_PTP,
848 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
849 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
850 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
852 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
853 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
856 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
859 static inline uint64_t
860 rx_desc_status_to_pkt_flags(uint32_t rx_status)
865 * Check if VLAN present only.
866 * Do not check whether L3/L4 rx checksum done by NIC or not,
867 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
869 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
871 #ifdef RTE_LIBRTE_IEEE1588
872 if (rx_status & IXGBE_RXD_STAT_TMST)
873 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
878 static inline uint64_t
879 rx_desc_error_to_pkt_flags(uint32_t rx_status)
882 * Bit 31: IPE, IPv4 checksum error
883 * Bit 30: L4I, L4I integrity error
885 static uint64_t error_to_pkt_flags_map[4] = {
886 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
887 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
889 return error_to_pkt_flags_map[(rx_status >>
890 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
893 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
895 * LOOK_AHEAD defines how many desc statuses to check beyond the
896 * current descriptor.
897 * It must be a pound define for optimal performance.
898 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
899 * function only works with LOOK_AHEAD=8.
902 #if (LOOK_AHEAD != 8)
903 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
906 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
908 volatile union ixgbe_adv_rx_desc *rxdp;
909 struct igb_rx_entry *rxep;
913 int s[LOOK_AHEAD], nb_dd;
917 /* get references to current descriptor and S/W ring entry */
918 rxdp = &rxq->rx_ring[rxq->rx_tail];
919 rxep = &rxq->sw_ring[rxq->rx_tail];
921 /* check to make sure there is at least 1 packet to receive */
922 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
926 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
927 * reference packets that are ready to be received.
929 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
930 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
932 /* Read desc statuses backwards to avoid race condition */
933 for (j = LOOK_AHEAD-1; j >= 0; --j)
934 s[j] = rxdp[j].wb.upper.status_error;
936 /* Compute how many status bits were set */
938 for (j = 0; j < LOOK_AHEAD; ++j)
939 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
943 /* Translate descriptor info to mbuf format */
944 for (j = 0; j < nb_dd; ++j) {
946 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
947 mb->data_len = pkt_len;
948 mb->pkt_len = pkt_len;
949 mb->vlan_tci = rxdp[j].wb.upper.vlan;
950 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
952 /* convert descriptor fields to rte mbuf flags */
953 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
954 rxdp[j].wb.lower.lo_dword.data);
955 /* reuse status field from scan list */
956 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
957 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
958 mb->ol_flags = pkt_flags;
960 if (likely(pkt_flags & PKT_RX_RSS_HASH))
961 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
962 else if (pkt_flags & PKT_RX_FDIR) {
964 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
965 & IXGBE_ATR_HASH_MASK);
966 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
970 /* Move mbuf pointers from the S/W ring to the stage */
971 for (j = 0; j < LOOK_AHEAD; ++j) {
972 rxq->rx_stage[i + j] = rxep[j].mbuf;
975 /* stop if all requested packets could not be received */
976 if (nb_dd != LOOK_AHEAD)
980 /* clear software ring entries so we can cleanup correctly */
981 for (i = 0; i < nb_rx; ++i) {
982 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
990 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
992 volatile union ixgbe_adv_rx_desc *rxdp;
993 struct igb_rx_entry *rxep;
999 /* allocate buffers in bulk directly into the S/W ring */
1000 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1001 (rxq->rx_free_thresh - 1));
1002 rxep = &rxq->sw_ring[alloc_idx];
1003 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1004 rxq->rx_free_thresh);
1005 if (unlikely(diag != 0))
1008 rxdp = &rxq->rx_ring[alloc_idx];
1009 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1010 /* populate the static rte mbuf fields */
1012 rte_mbuf_refcnt_set(mb, 1);
1014 mb->data_off = RTE_PKTMBUF_HEADROOM;
1016 mb->port = rxq->port_id;
1018 /* populate the descriptors */
1019 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1020 rxdp[i].read.hdr_addr = dma_addr;
1021 rxdp[i].read.pkt_addr = dma_addr;
1024 /* update tail pointer */
1026 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1028 /* update state of internal queue structure */
1029 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1030 rxq->rx_free_thresh);
1031 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1032 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1038 static inline uint16_t
1039 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1042 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1045 /* how many packets are ready to return? */
1046 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1048 /* copy mbuf pointers to the application's packet list */
1049 for (i = 0; i < nb_pkts; ++i)
1050 rx_pkts[i] = stage[i];
1052 /* update internal queue state */
1053 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1054 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1059 static inline uint16_t
1060 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1063 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1066 /* Any previously recv'd pkts will be returned from the Rx stage */
1067 if (rxq->rx_nb_avail)
1068 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1070 /* Scan the H/W ring for packets to receive */
1071 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1073 /* update internal queue state */
1074 rxq->rx_next_avail = 0;
1075 rxq->rx_nb_avail = nb_rx;
1076 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1078 /* if required, allocate new buffers to replenish descriptors */
1079 if (rxq->rx_tail > rxq->rx_free_trigger) {
1080 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1082 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1083 "queue_id=%u", (unsigned) rxq->port_id,
1084 (unsigned) rxq->queue_id);
1086 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1087 rxq->rx_free_thresh;
1090 * Need to rewind any previous receives if we cannot
1091 * allocate new buffers to replenish the old ones.
1093 rxq->rx_nb_avail = 0;
1094 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1095 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1096 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1102 if (rxq->rx_tail >= rxq->nb_rx_desc)
1105 /* received any packets this loop? */
1106 if (rxq->rx_nb_avail)
1107 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1112 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1114 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1119 if (unlikely(nb_pkts == 0))
1122 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1123 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1125 /* request is relatively large, chunk it up */
1129 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1130 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1131 nb_rx = (uint16_t)(nb_rx + ret);
1132 nb_pkts = (uint16_t)(nb_pkts - ret);
1139 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1142 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1145 struct igb_rx_queue *rxq;
1146 volatile union ixgbe_adv_rx_desc *rx_ring;
1147 volatile union ixgbe_adv_rx_desc *rxdp;
1148 struct igb_rx_entry *sw_ring;
1149 struct igb_rx_entry *rxe;
1150 struct rte_mbuf *rxm;
1151 struct rte_mbuf *nmb;
1152 union ixgbe_adv_rx_desc rxd;
1155 uint32_t hlen_type_rss;
1165 rx_id = rxq->rx_tail;
1166 rx_ring = rxq->rx_ring;
1167 sw_ring = rxq->sw_ring;
1168 while (nb_rx < nb_pkts) {
1170 * The order of operations here is important as the DD status
1171 * bit must not be read after any other descriptor fields.
1172 * rx_ring and rxdp are pointing to volatile data so the order
1173 * of accesses cannot be reordered by the compiler. If they were
1174 * not volatile, they could be reordered which could lead to
1175 * using invalid descriptor fields when read from rxd.
1177 rxdp = &rx_ring[rx_id];
1178 staterr = rxdp->wb.upper.status_error;
1179 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1186 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1187 * is likely to be invalid and to be dropped by the various
1188 * validation checks performed by the network stack.
1190 * Allocate a new mbuf to replenish the RX ring descriptor.
1191 * If the allocation fails:
1192 * - arrange for that RX descriptor to be the first one
1193 * being parsed the next time the receive function is
1194 * invoked [on the same queue].
1196 * - Stop parsing the RX ring and return immediately.
1198 * This policy do not drop the packet received in the RX
1199 * descriptor for which the allocation of a new mbuf failed.
1200 * Thus, it allows that packet to be later retrieved if
1201 * mbuf have been freed in the mean time.
1202 * As a side effect, holding RX descriptors instead of
1203 * systematically giving them back to the NIC may lead to
1204 * RX ring exhaustion situations.
1205 * However, the NIC can gracefully prevent such situations
1206 * to happen by sending specific "back-pressure" flow control
1207 * frames to its peer(s).
1209 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1210 "ext_err_stat=0x%08x pkt_len=%u",
1211 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1212 (unsigned) rx_id, (unsigned) staterr,
1213 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1215 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1217 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1218 "queue_id=%u", (unsigned) rxq->port_id,
1219 (unsigned) rxq->queue_id);
1220 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1225 rxe = &sw_ring[rx_id];
1227 if (rx_id == rxq->nb_rx_desc)
1230 /* Prefetch next mbuf while processing current one. */
1231 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1234 * When next RX descriptor is on a cache-line boundary,
1235 * prefetch the next 4 RX descriptors and the next 8 pointers
1238 if ((rx_id & 0x3) == 0) {
1239 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1240 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1246 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1247 rxdp->read.hdr_addr = dma_addr;
1248 rxdp->read.pkt_addr = dma_addr;
1251 * Initialize the returned mbuf.
1252 * 1) setup generic mbuf fields:
1253 * - number of segments,
1256 * - RX port identifier.
1257 * 2) integrate hardware offload data, if any:
1258 * - RSS flag & hash,
1259 * - IP checksum flag,
1260 * - VLAN TCI, if any,
1263 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1265 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1266 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1269 rxm->pkt_len = pkt_len;
1270 rxm->data_len = pkt_len;
1271 rxm->port = rxq->port_id;
1273 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1274 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1275 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1277 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1278 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1279 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1280 rxm->ol_flags = pkt_flags;
1282 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1283 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1284 else if (pkt_flags & PKT_RX_FDIR) {
1285 rxm->hash.fdir.hash =
1286 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1287 & IXGBE_ATR_HASH_MASK);
1288 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1291 * Store the mbuf address into the next entry of the array
1292 * of returned packets.
1294 rx_pkts[nb_rx++] = rxm;
1296 rxq->rx_tail = rx_id;
1299 * If the number of free RX descriptors is greater than the RX free
1300 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1302 * Update the RDT with the value of the last processed RX descriptor
1303 * minus 1, to guarantee that the RDT register is never equal to the
1304 * RDH register, which creates a "full" ring situtation from the
1305 * hardware point of view...
1307 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1308 if (nb_hold > rxq->rx_free_thresh) {
1309 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1310 "nb_hold=%u nb_rx=%u",
1311 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1312 (unsigned) rx_id, (unsigned) nb_hold,
1314 rx_id = (uint16_t) ((rx_id == 0) ?
1315 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1316 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1319 rxq->nb_rx_hold = nb_hold;
1324 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1327 struct igb_rx_queue *rxq;
1328 volatile union ixgbe_adv_rx_desc *rx_ring;
1329 volatile union ixgbe_adv_rx_desc *rxdp;
1330 struct igb_rx_entry *sw_ring;
1331 struct igb_rx_entry *rxe;
1332 struct rte_mbuf *first_seg;
1333 struct rte_mbuf *last_seg;
1334 struct rte_mbuf *rxm;
1335 struct rte_mbuf *nmb;
1336 union ixgbe_adv_rx_desc rxd;
1337 uint64_t dma; /* Physical address of mbuf data buffer */
1339 uint32_t hlen_type_rss;
1349 rx_id = rxq->rx_tail;
1350 rx_ring = rxq->rx_ring;
1351 sw_ring = rxq->sw_ring;
1354 * Retrieve RX context of current packet, if any.
1356 first_seg = rxq->pkt_first_seg;
1357 last_seg = rxq->pkt_last_seg;
1359 while (nb_rx < nb_pkts) {
1362 * The order of operations here is important as the DD status
1363 * bit must not be read after any other descriptor fields.
1364 * rx_ring and rxdp are pointing to volatile data so the order
1365 * of accesses cannot be reordered by the compiler. If they were
1366 * not volatile, they could be reordered which could lead to
1367 * using invalid descriptor fields when read from rxd.
1369 rxdp = &rx_ring[rx_id];
1370 staterr = rxdp->wb.upper.status_error;
1371 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1378 * Allocate a new mbuf to replenish the RX ring descriptor.
1379 * If the allocation fails:
1380 * - arrange for that RX descriptor to be the first one
1381 * being parsed the next time the receive function is
1382 * invoked [on the same queue].
1384 * - Stop parsing the RX ring and return immediately.
1386 * This policy does not drop the packet received in the RX
1387 * descriptor for which the allocation of a new mbuf failed.
1388 * Thus, it allows that packet to be later retrieved if
1389 * mbuf have been freed in the mean time.
1390 * As a side effect, holding RX descriptors instead of
1391 * systematically giving them back to the NIC may lead to
1392 * RX ring exhaustion situations.
1393 * However, the NIC can gracefully prevent such situations
1394 * to happen by sending specific "back-pressure" flow control
1395 * frames to its peer(s).
1397 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1398 "staterr=0x%x data_len=%u",
1399 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1400 (unsigned) rx_id, (unsigned) staterr,
1401 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1403 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1405 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1406 "queue_id=%u", (unsigned) rxq->port_id,
1407 (unsigned) rxq->queue_id);
1408 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1413 rxe = &sw_ring[rx_id];
1415 if (rx_id == rxq->nb_rx_desc)
1418 /* Prefetch next mbuf while processing current one. */
1419 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1422 * When next RX descriptor is on a cache-line boundary,
1423 * prefetch the next 4 RX descriptors and the next 8 pointers
1426 if ((rx_id & 0x3) == 0) {
1427 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1428 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1432 * Update RX descriptor with the physical address of the new
1433 * data buffer of the new allocated mbuf.
1437 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1438 rxdp->read.hdr_addr = dma;
1439 rxdp->read.pkt_addr = dma;
1442 * Set data length & data buffer address of mbuf.
1444 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1445 rxm->data_len = data_len;
1446 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1449 * If this is the first buffer of the received packet,
1450 * set the pointer to the first mbuf of the packet and
1451 * initialize its context.
1452 * Otherwise, update the total length and the number of segments
1453 * of the current scattered packet, and update the pointer to
1454 * the last mbuf of the current packet.
1456 if (first_seg == NULL) {
1458 first_seg->pkt_len = data_len;
1459 first_seg->nb_segs = 1;
1461 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1463 first_seg->nb_segs++;
1464 last_seg->next = rxm;
1468 * If this is not the last buffer of the received packet,
1469 * update the pointer to the last mbuf of the current scattered
1470 * packet and continue to parse the RX ring.
1472 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1478 * This is the last buffer of the received packet.
1479 * If the CRC is not stripped by the hardware:
1480 * - Subtract the CRC length from the total packet length.
1481 * - If the last buffer only contains the whole CRC or a part
1482 * of it, free the mbuf associated to the last buffer.
1483 * If part of the CRC is also contained in the previous
1484 * mbuf, subtract the length of that CRC part from the
1485 * data length of the previous mbuf.
1488 if (unlikely(rxq->crc_len > 0)) {
1489 first_seg->pkt_len -= ETHER_CRC_LEN;
1490 if (data_len <= ETHER_CRC_LEN) {
1491 rte_pktmbuf_free_seg(rxm);
1492 first_seg->nb_segs--;
1493 last_seg->data_len = (uint16_t)
1494 (last_seg->data_len -
1495 (ETHER_CRC_LEN - data_len));
1496 last_seg->next = NULL;
1499 (uint16_t) (data_len - ETHER_CRC_LEN);
1503 * Initialize the first mbuf of the returned packet:
1504 * - RX port identifier,
1505 * - hardware offload data, if any:
1506 * - RSS flag & hash,
1507 * - IP checksum flag,
1508 * - VLAN TCI, if any,
1511 first_seg->port = rxq->port_id;
1514 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1515 * set in the pkt_flags field.
1517 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1518 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1519 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1520 pkt_flags = (pkt_flags |
1521 rx_desc_status_to_pkt_flags(staterr));
1522 pkt_flags = (pkt_flags |
1523 rx_desc_error_to_pkt_flags(staterr));
1524 first_seg->ol_flags = pkt_flags;
1526 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1527 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1528 else if (pkt_flags & PKT_RX_FDIR) {
1529 first_seg->hash.fdir.hash =
1530 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1531 & IXGBE_ATR_HASH_MASK);
1532 first_seg->hash.fdir.id =
1533 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1536 /* Prefetch data of first segment, if configured to do so. */
1537 rte_packet_prefetch((char *)first_seg->buf_addr +
1538 first_seg->data_off);
1541 * Store the mbuf address into the next entry of the array
1542 * of returned packets.
1544 rx_pkts[nb_rx++] = first_seg;
1547 * Setup receipt context for a new packet.
1553 * Record index of the next RX descriptor to probe.
1555 rxq->rx_tail = rx_id;
1558 * Save receive context.
1560 rxq->pkt_first_seg = first_seg;
1561 rxq->pkt_last_seg = last_seg;
1564 * If the number of free RX descriptors is greater than the RX free
1565 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1567 * Update the RDT with the value of the last processed RX descriptor
1568 * minus 1, to guarantee that the RDT register is never equal to the
1569 * RDH register, which creates a "full" ring situtation from the
1570 * hardware point of view...
1572 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1573 if (nb_hold > rxq->rx_free_thresh) {
1574 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1575 "nb_hold=%u nb_rx=%u",
1576 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1577 (unsigned) rx_id, (unsigned) nb_hold,
1579 rx_id = (uint16_t) ((rx_id == 0) ?
1580 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1581 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1584 rxq->nb_rx_hold = nb_hold;
1588 /*********************************************************************
1590 * Queue management functions
1592 **********************************************************************/
1595 * Rings setup and release.
1597 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1598 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1599 * also optimize cache line size effect. H/W supports up to cache line size 128.
1601 #define IXGBE_ALIGN 128
1604 * Maximum number of Ring Descriptors.
1606 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1607 * descriptors should meet the following condition:
1608 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1610 #define IXGBE_MIN_RING_DESC 32
1611 #define IXGBE_MAX_RING_DESC 4096
1614 * Create memzone for HW rings. malloc can't be used as the physical address is
1615 * needed. If the memzone is already created, then this function returns a ptr
1618 static const struct rte_memzone *
1619 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1620 uint16_t queue_id, uint32_t ring_size, int socket_id)
1622 char z_name[RTE_MEMZONE_NAMESIZE];
1623 const struct rte_memzone *mz;
1625 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1626 dev->driver->pci_drv.name, ring_name,
1627 dev->data->port_id, queue_id);
1629 mz = rte_memzone_lookup(z_name);
1633 #ifdef RTE_LIBRTE_XEN_DOM0
1634 return rte_memzone_reserve_bounded(z_name, ring_size,
1635 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1637 return rte_memzone_reserve_aligned(z_name, ring_size,
1638 socket_id, 0, IXGBE_ALIGN);
1643 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1647 if (txq->sw_ring != NULL) {
1648 for (i = 0; i < txq->nb_tx_desc; i++) {
1649 if (txq->sw_ring[i].mbuf != NULL) {
1650 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1651 txq->sw_ring[i].mbuf = NULL;
1658 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
1661 txq->sw_ring != NULL)
1662 rte_free(txq->sw_ring);
1666 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1668 if (txq != NULL && txq->ops != NULL) {
1669 txq->ops->release_mbufs(txq);
1670 txq->ops->free_swring(txq);
1676 ixgbe_dev_tx_queue_release(void *txq)
1678 ixgbe_tx_queue_release(txq);
1681 /* (Re)set dynamic igb_tx_queue fields to defaults */
1683 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1685 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1687 struct igb_tx_entry *txe = txq->sw_ring;
1690 /* Zero out HW ring memory */
1691 for (i = 0; i < txq->nb_tx_desc; i++) {
1692 txq->tx_ring[i] = zeroed_desc;
1695 /* Initialize SW ring entries */
1696 prev = (uint16_t) (txq->nb_tx_desc - 1);
1697 for (i = 0; i < txq->nb_tx_desc; i++) {
1698 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1699 txd->wb.status = IXGBE_TXD_STAT_DD;
1702 txe[prev].next_id = i;
1706 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1707 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1710 txq->nb_tx_used = 0;
1712 * Always allow 1 descriptor to be un-allocated to avoid
1713 * a H/W race condition
1715 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1716 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1718 memset((void*)&txq->ctx_cache, 0,
1719 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1722 static struct ixgbe_txq_ops def_txq_ops = {
1723 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1724 .free_swring = ixgbe_tx_free_swring,
1725 .reset = ixgbe_reset_tx_queue,
1729 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1732 unsigned int socket_id,
1733 const struct rte_eth_txconf *tx_conf)
1735 const struct rte_memzone *tz;
1736 struct igb_tx_queue *txq;
1737 struct ixgbe_hw *hw;
1738 uint16_t tx_rs_thresh, tx_free_thresh;
1740 PMD_INIT_FUNC_TRACE();
1741 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1744 * Validate number of transmit descriptors.
1745 * It must not exceed hardware maximum, and must be multiple
1748 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1749 (nb_desc > IXGBE_MAX_RING_DESC) ||
1750 (nb_desc < IXGBE_MIN_RING_DESC)) {
1755 * The following two parameters control the setting of the RS bit on
1756 * transmit descriptors.
1757 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1758 * descriptors have been used.
1759 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1760 * descriptors are used or if the number of descriptors required
1761 * to transmit a packet is greater than the number of free TX
1763 * The following constraints must be satisfied:
1764 * tx_rs_thresh must be greater than 0.
1765 * tx_rs_thresh must be less than the size of the ring minus 2.
1766 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1767 * tx_rs_thresh must be a divisor of the ring size.
1768 * tx_free_thresh must be greater than 0.
1769 * tx_free_thresh must be less than the size of the ring minus 3.
1770 * One descriptor in the TX ring is used as a sentinel to avoid a
1771 * H/W race condition, hence the maximum threshold constraints.
1772 * When set to zero use default values.
1774 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1775 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1776 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1777 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1778 if (tx_rs_thresh >= (nb_desc - 2)) {
1779 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
1780 "of TX descriptors minus 2. (tx_rs_thresh=%u "
1781 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1782 (int)dev->data->port_id, (int)queue_idx);
1785 if (tx_free_thresh >= (nb_desc - 3)) {
1786 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1787 "tx_free_thresh must be less than the number of "
1788 "TX descriptors minus 3. (tx_free_thresh=%u "
1789 "port=%d queue=%d)",
1790 (unsigned int)tx_free_thresh,
1791 (int)dev->data->port_id, (int)queue_idx);
1794 if (tx_rs_thresh > tx_free_thresh) {
1795 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1796 "tx_free_thresh. (tx_free_thresh=%u "
1797 "tx_rs_thresh=%u port=%d queue=%d)",
1798 (unsigned int)tx_free_thresh,
1799 (unsigned int)tx_rs_thresh,
1800 (int)dev->data->port_id,
1804 if ((nb_desc % tx_rs_thresh) != 0) {
1805 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1806 "number of TX descriptors. (tx_rs_thresh=%u "
1807 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1808 (int)dev->data->port_id, (int)queue_idx);
1813 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1814 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1815 * by the NIC and all descriptors are written back after the NIC
1816 * accumulates WTHRESH descriptors.
1818 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1819 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1820 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1821 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1822 (int)dev->data->port_id, (int)queue_idx);
1826 /* Free memory prior to re-allocation if needed... */
1827 if (dev->data->tx_queues[queue_idx] != NULL) {
1828 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1829 dev->data->tx_queues[queue_idx] = NULL;
1832 /* First allocate the tx queue data structure */
1833 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct igb_tx_queue),
1834 CACHE_LINE_SIZE, socket_id);
1839 * Allocate TX ring hardware descriptors. A memzone large enough to
1840 * handle the maximum ring size is allocated in order to allow for
1841 * resizing in later calls to the queue setup function.
1843 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1844 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1847 ixgbe_tx_queue_release(txq);
1851 txq->nb_tx_desc = nb_desc;
1852 txq->tx_rs_thresh = tx_rs_thresh;
1853 txq->tx_free_thresh = tx_free_thresh;
1854 txq->pthresh = tx_conf->tx_thresh.pthresh;
1855 txq->hthresh = tx_conf->tx_thresh.hthresh;
1856 txq->wthresh = tx_conf->tx_thresh.wthresh;
1857 txq->queue_id = queue_idx;
1858 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1859 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1860 txq->port_id = dev->data->port_id;
1861 txq->txq_flags = tx_conf->txq_flags;
1862 txq->ops = &def_txq_ops;
1863 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1866 * Modification to set VFTDT for virtual function if vf is detected
1868 if (hw->mac.type == ixgbe_mac_82599_vf)
1869 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1871 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1872 #ifndef RTE_LIBRTE_XEN_DOM0
1873 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1875 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1877 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1879 /* Allocate software ring */
1880 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1881 sizeof(struct igb_tx_entry) * nb_desc,
1882 CACHE_LINE_SIZE, socket_id);
1883 if (txq->sw_ring == NULL) {
1884 ixgbe_tx_queue_release(txq);
1887 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1888 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1890 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1891 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1892 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1893 PMD_INIT_LOG(INFO, "Using simple tx code path");
1894 #ifdef RTE_IXGBE_INC_VECTOR
1895 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1896 ixgbe_txq_vec_setup(txq) == 0) {
1897 PMD_INIT_LOG(INFO, "Vector tx enabled.");
1898 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1902 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1904 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
1905 PMD_INIT_LOG(INFO, " - txq_flags = %lx "
1906 "[IXGBE_SIMPLE_FLAGS=%lx]",
1907 (long unsigned)txq->txq_flags,
1908 (long unsigned)IXGBE_SIMPLE_FLAGS);
1909 PMD_INIT_LOG(INFO, " - tx_rs_thresh = %lu "
1910 "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
1911 (long unsigned)txq->tx_rs_thresh,
1912 (long unsigned)RTE_PMD_IXGBE_TX_MAX_BURST);
1913 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1916 txq->ops->reset(txq);
1918 dev->data->tx_queues[queue_idx] = txq;
1925 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1929 if (rxq->sw_ring != NULL) {
1930 for (i = 0; i < rxq->nb_rx_desc; i++) {
1931 if (rxq->sw_ring[i].mbuf != NULL) {
1932 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1933 rxq->sw_ring[i].mbuf = NULL;
1936 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1937 if (rxq->rx_nb_avail) {
1938 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1939 struct rte_mbuf *mb;
1940 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1941 rte_pktmbuf_free_seg(mb);
1943 rxq->rx_nb_avail = 0;
1950 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
1953 ixgbe_rx_queue_release_mbufs(rxq);
1954 rte_free(rxq->sw_ring);
1960 ixgbe_dev_rx_queue_release(void *rxq)
1962 ixgbe_rx_queue_release(rxq);
1966 * Check if Rx Burst Bulk Alloc function can be used.
1968 * 0: the preconditions are satisfied and the bulk allocation function
1970 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
1971 * function must be used.
1974 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1975 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
1977 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct igb_rx_queue *rxq)
1983 * Make sure the following pre-conditions are satisfied:
1984 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
1985 * rxq->rx_free_thresh < rxq->nb_rx_desc
1986 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
1987 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
1988 * Scattered packets are not supported. This should be checked
1989 * outside of this function.
1991 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1992 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
1993 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
1994 "rxq->rx_free_thresh=%d, "
1995 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
1996 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
1998 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
1999 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2000 "rxq->rx_free_thresh=%d, "
2001 "rxq->nb_rx_desc=%d",
2002 rxq->rx_free_thresh, rxq->nb_rx_desc);
2004 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2005 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2006 "rxq->nb_rx_desc=%d, "
2007 "rxq->rx_free_thresh=%d",
2008 rxq->nb_rx_desc, rxq->rx_free_thresh);
2010 } else if (!(rxq->nb_rx_desc <
2011 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2012 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2013 "rxq->nb_rx_desc=%d, "
2014 "IXGBE_MAX_RING_DESC=%d, "
2015 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2016 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2017 RTE_PMD_IXGBE_RX_MAX_BURST);
2027 /* Reset dynamic igb_rx_queue fields back to defaults */
2029 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
2031 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2037 * By default, the Rx queue setup function allocates enough memory for
2038 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2039 * extra memory at the end of the descriptor ring to be zero'd out. A
2040 * pre-condition for using the Rx burst bulk alloc function is that the
2041 * number of descriptors is less than or equal to
2042 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2043 * constraints here to see if we need to zero out memory after the end
2044 * of the H/W descriptor ring.
2046 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2047 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2048 /* zero out extra memory */
2049 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2052 /* do not zero out extra memory */
2053 len = rxq->nb_rx_desc;
2056 * Zero out HW ring memory. Zero out extra memory at the end of
2057 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2058 * reads extra memory as zeros.
2060 for (i = 0; i < len; i++) {
2061 rxq->rx_ring[i] = zeroed_desc;
2064 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2066 * initialize extra software ring entries. Space for these extra
2067 * entries is always allocated
2069 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2070 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2071 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2074 rxq->rx_nb_avail = 0;
2075 rxq->rx_next_avail = 0;
2076 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2077 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2079 rxq->nb_rx_hold = 0;
2080 rxq->pkt_first_seg = NULL;
2081 rxq->pkt_last_seg = NULL;
2085 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2088 unsigned int socket_id,
2089 const struct rte_eth_rxconf *rx_conf,
2090 struct rte_mempool *mp)
2092 const struct rte_memzone *rz;
2093 struct igb_rx_queue *rxq;
2094 struct ixgbe_hw *hw;
2095 int use_def_burst_func = 1;
2098 PMD_INIT_FUNC_TRACE();
2099 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102 * Validate number of receive descriptors.
2103 * It must not exceed hardware maximum, and must be multiple
2106 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2107 (nb_desc > IXGBE_MAX_RING_DESC) ||
2108 (nb_desc < IXGBE_MIN_RING_DESC)) {
2112 /* Free memory prior to re-allocation if needed... */
2113 if (dev->data->rx_queues[queue_idx] != NULL) {
2114 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2115 dev->data->rx_queues[queue_idx] = NULL;
2118 /* First allocate the rx queue data structure */
2119 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct igb_rx_queue),
2120 CACHE_LINE_SIZE, socket_id);
2124 rxq->nb_rx_desc = nb_desc;
2125 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2126 rxq->queue_id = queue_idx;
2127 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2128 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2129 rxq->port_id = dev->data->port_id;
2130 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2132 rxq->drop_en = rx_conf->rx_drop_en;
2133 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2136 * Allocate RX ring hardware descriptors. A memzone large enough to
2137 * handle the maximum ring size is allocated in order to allow for
2138 * resizing in later calls to the queue setup function.
2140 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2141 RX_RING_SZ, socket_id);
2143 ixgbe_rx_queue_release(rxq);
2148 * Zero init all the descriptors in the ring.
2150 memset (rz->addr, 0, RX_RING_SZ);
2153 * Modified to setup VFRDT for Virtual Function
2155 if (hw->mac.type == ixgbe_mac_82599_vf) {
2157 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2159 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2163 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2165 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2167 #ifndef RTE_LIBRTE_XEN_DOM0
2168 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2170 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2172 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2175 * Allocate software ring. Allow for space at the end of the
2176 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2177 * function does not access an invalid memory region.
2179 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2180 len = (uint16_t)(nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST);
2184 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2185 sizeof(struct igb_rx_entry) * len,
2186 CACHE_LINE_SIZE, socket_id);
2187 if (rxq->sw_ring == NULL) {
2188 ixgbe_rx_queue_release(rxq);
2191 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2192 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2195 * Certain constraints must be met in order to use the bulk buffer
2196 * allocation Rx burst function.
2198 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2200 #ifdef RTE_IXGBE_INC_VECTOR
2201 ixgbe_rxq_vec_setup(rxq);
2203 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2204 if (!use_def_burst_func && !dev->data->scattered_rx) {
2205 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2206 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2207 "satisfied. Rx Burst Bulk Alloc function will be "
2208 "used on port=%d, queue=%d.",
2209 rxq->port_id, rxq->queue_id);
2210 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2211 #ifdef RTE_IXGBE_INC_VECTOR
2212 if (!ixgbe_rx_vec_condition_check(dev)) {
2213 PMD_INIT_LOG(INFO, "Vector rx enabled, please make "
2214 "sure RX burst size no less than 32.");
2215 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
2220 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2221 "are not satisfied, Scattered Rx is requested, "
2222 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2223 "enabled (port=%d, queue=%d).",
2224 rxq->port_id, rxq->queue_id);
2226 dev->data->rx_queues[queue_idx] = rxq;
2228 ixgbe_reset_rx_queue(rxq);
2234 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2236 #define IXGBE_RXQ_SCAN_INTERVAL 4
2237 volatile union ixgbe_adv_rx_desc *rxdp;
2238 struct igb_rx_queue *rxq;
2241 if (rx_queue_id >= dev->data->nb_rx_queues) {
2242 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2246 rxq = dev->data->rx_queues[rx_queue_id];
2247 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2249 while ((desc < rxq->nb_rx_desc) &&
2250 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2251 desc += IXGBE_RXQ_SCAN_INTERVAL;
2252 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2253 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2254 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2255 desc - rxq->nb_rx_desc]);
2262 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2264 volatile union ixgbe_adv_rx_desc *rxdp;
2265 struct igb_rx_queue *rxq = rx_queue;
2268 if (unlikely(offset >= rxq->nb_rx_desc))
2270 desc = rxq->rx_tail + offset;
2271 if (desc >= rxq->nb_rx_desc)
2272 desc -= rxq->nb_rx_desc;
2274 rxdp = &rxq->rx_ring[desc];
2275 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2279 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2283 PMD_INIT_FUNC_TRACE();
2285 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2286 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2288 txq->ops->release_mbufs(txq);
2289 txq->ops->reset(txq);
2293 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2294 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2296 ixgbe_rx_queue_release_mbufs(rxq);
2297 ixgbe_reset_rx_queue(rxq);
2302 /*********************************************************************
2304 * Device RX/TX init functions
2306 **********************************************************************/
2309 * Receive Side Scaling (RSS)
2310 * See section 7.1.2.8 in the following document:
2311 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2314 * The source and destination IP addresses of the IP header and the source
2315 * and destination ports of TCP/UDP headers, if any, of received packets are
2316 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2317 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2318 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2319 * RSS output index which is used as the RX queue index where to store the
2321 * The following output is supplied in the RX write-back descriptor:
2322 * - 32-bit result of the Microsoft RSS hash function,
2323 * - 4-bit RSS type field.
2327 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2328 * Used as the default key.
2330 static uint8_t rss_intel_key[40] = {
2331 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2332 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2333 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2334 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2335 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2339 ixgbe_rss_disable(struct rte_eth_dev *dev)
2341 struct ixgbe_hw *hw;
2344 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2345 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2346 mrqc &= ~IXGBE_MRQC_RSSEN;
2347 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2351 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2359 hash_key = rss_conf->rss_key;
2360 if (hash_key != NULL) {
2361 /* Fill in RSS hash key */
2362 for (i = 0; i < 10; i++) {
2363 rss_key = hash_key[(i * 4)];
2364 rss_key |= hash_key[(i * 4) + 1] << 8;
2365 rss_key |= hash_key[(i * 4) + 2] << 16;
2366 rss_key |= hash_key[(i * 4) + 3] << 24;
2367 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2371 /* Set configured hashing protocols in MRQC register */
2372 rss_hf = rss_conf->rss_hf;
2373 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2374 if (rss_hf & ETH_RSS_IPV4)
2375 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2376 if (rss_hf & ETH_RSS_IPV4_TCP)
2377 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2378 if (rss_hf & ETH_RSS_IPV6)
2379 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2380 if (rss_hf & ETH_RSS_IPV6_EX)
2381 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2382 if (rss_hf & ETH_RSS_IPV6_TCP)
2383 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2384 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2385 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2386 if (rss_hf & ETH_RSS_IPV4_UDP)
2387 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2388 if (rss_hf & ETH_RSS_IPV6_UDP)
2389 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2390 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2391 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2392 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2396 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2397 struct rte_eth_rss_conf *rss_conf)
2399 struct ixgbe_hw *hw;
2403 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2406 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2407 * "RSS enabling cannot be done dynamically while it must be
2408 * preceded by a software reset"
2409 * Before changing anything, first check that the update RSS operation
2410 * does not attempt to disable RSS, if RSS was enabled at
2411 * initialization time, or does not attempt to enable RSS, if RSS was
2412 * disabled at initialization time.
2414 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2415 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2416 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2417 if (rss_hf != 0) /* Enable RSS */
2419 return 0; /* Nothing to do */
2422 if (rss_hf == 0) /* Disable RSS */
2424 ixgbe_hw_rss_hash_set(hw, rss_conf);
2429 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2430 struct rte_eth_rss_conf *rss_conf)
2432 struct ixgbe_hw *hw;
2439 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2440 hash_key = rss_conf->rss_key;
2441 if (hash_key != NULL) {
2442 /* Return RSS hash key */
2443 for (i = 0; i < 10; i++) {
2444 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2445 hash_key[(i * 4)] = rss_key & 0x000000FF;
2446 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2447 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2448 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2452 /* Get RSS functions configured in MRQC register */
2453 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2454 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2455 rss_conf->rss_hf = 0;
2459 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2460 rss_hf |= ETH_RSS_IPV4;
2461 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2462 rss_hf |= ETH_RSS_IPV4_TCP;
2463 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2464 rss_hf |= ETH_RSS_IPV6;
2465 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2466 rss_hf |= ETH_RSS_IPV6_EX;
2467 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2468 rss_hf |= ETH_RSS_IPV6_TCP;
2469 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2470 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2471 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2472 rss_hf |= ETH_RSS_IPV4_UDP;
2473 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2474 rss_hf |= ETH_RSS_IPV6_UDP;
2475 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2476 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2477 rss_conf->rss_hf = rss_hf;
2482 ixgbe_rss_configure(struct rte_eth_dev *dev)
2484 struct rte_eth_rss_conf rss_conf;
2485 struct ixgbe_hw *hw;
2490 PMD_INIT_FUNC_TRACE();
2491 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2494 * Fill in redirection table
2495 * The byte-swap is needed because NIC registers are in
2496 * little-endian order.
2499 for (i = 0, j = 0; i < 128; i++, j++) {
2500 if (j == dev->data->nb_rx_queues)
2502 reta = (reta << 8) | j;
2504 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2509 * Configure the RSS key and the RSS protocols used to compute
2510 * the RSS hash of input packets.
2512 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2513 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2514 ixgbe_rss_disable(dev);
2517 if (rss_conf.rss_key == NULL)
2518 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2519 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2522 #define NUM_VFTA_REGISTERS 128
2523 #define NIC_RX_BUFFER_SIZE 0x200
2526 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2528 struct rte_eth_vmdq_dcb_conf *cfg;
2529 struct ixgbe_hw *hw;
2530 enum rte_eth_nb_pools num_pools;
2531 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2533 uint8_t nb_tcs; /* number of traffic classes */
2536 PMD_INIT_FUNC_TRACE();
2537 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2539 num_pools = cfg->nb_queue_pools;
2540 /* Check we have a valid number of pools */
2541 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2542 ixgbe_rss_disable(dev);
2545 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2546 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2550 * split rx buffer up into sections, each for 1 traffic class
2552 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2553 for (i = 0 ; i < nb_tcs; i++) {
2554 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2555 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2556 /* clear 10 bits. */
2557 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2558 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2560 /* zero alloc all unused TCs */
2561 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2562 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2563 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2564 /* clear 10 bits. */
2565 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2568 /* MRQC: enable vmdq and dcb */
2569 mrqc = ((num_pools == ETH_16_POOLS) ? \
2570 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2571 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2573 /* PFVTCTL: turn on virtualisation and set the default pool */
2574 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2575 if (cfg->enable_default_pool) {
2576 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2578 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2581 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2583 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2585 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2587 * mapping is done with 3 bits per priority,
2588 * so shift by i*3 each time
2590 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2592 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2594 /* RTRPCS: DCB related */
2595 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2597 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2598 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2599 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2600 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2602 /* VFTA - enable all vlan filters */
2603 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2604 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2607 /* VFRE: pool enabling for receive - 16 or 32 */
2608 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2609 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2612 * MPSAR - allow pools to read specific mac addresses
2613 * In this case, all pools should be able to read from mac addr 0
2615 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2616 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2618 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2619 for (i = 0; i < cfg->nb_pool_maps; i++) {
2620 /* set vlan id in VF register and set the valid bit */
2621 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2622 (cfg->pool_map[i].vlan_id & 0xFFF)));
2624 * Put the allowed pools in VFB reg. As we only have 16 or 32
2625 * pools, we only need to use the first half of the register
2628 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2633 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2634 * @hw: pointer to hardware structure
2635 * @dcb_config: pointer to ixgbe_dcb_config structure
2638 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2639 struct ixgbe_dcb_config *dcb_config)
2644 PMD_INIT_FUNC_TRACE();
2645 if (hw->mac.type != ixgbe_mac_82598EB) {
2646 /* Disable the Tx desc arbiter so that MTQC can be changed */
2647 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2648 reg |= IXGBE_RTTDCS_ARBDIS;
2649 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2651 /* Enable DCB for Tx with 8 TCs */
2652 if (dcb_config->num_tcs.pg_tcs == 8) {
2653 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2656 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2658 if (dcb_config->vt_mode)
2659 reg |= IXGBE_MTQC_VT_ENA;
2660 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2662 /* Disable drop for all queues */
2663 for (q = 0; q < 128; q++)
2664 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2665 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2667 /* Enable the Tx desc arbiter */
2668 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2669 reg &= ~IXGBE_RTTDCS_ARBDIS;
2670 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2672 /* Enable Security TX Buffer IFG for DCB */
2673 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2674 reg |= IXGBE_SECTX_DCB;
2675 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2681 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2682 * @dev: pointer to rte_eth_dev structure
2683 * @dcb_config: pointer to ixgbe_dcb_config structure
2686 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2687 struct ixgbe_dcb_config *dcb_config)
2689 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2690 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2691 struct ixgbe_hw *hw =
2692 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2694 PMD_INIT_FUNC_TRACE();
2695 if (hw->mac.type != ixgbe_mac_82598EB)
2696 /*PF VF Transmit Enable*/
2697 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2698 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2700 /*Configure general DCB TX parameters*/
2701 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2706 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2707 struct ixgbe_dcb_config *dcb_config)
2709 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2710 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2711 struct ixgbe_dcb_tc_config *tc;
2714 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2715 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2716 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2717 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2720 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2721 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2723 /* User Priority to Traffic Class mapping */
2724 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2725 j = vmdq_rx_conf->dcb_queue[i];
2726 tc = &dcb_config->tc_config[j];
2727 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2733 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2734 struct ixgbe_dcb_config *dcb_config)
2736 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2737 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2738 struct ixgbe_dcb_tc_config *tc;
2741 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2742 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2743 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2744 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2747 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2748 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2751 /* User Priority to Traffic Class mapping */
2752 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2753 j = vmdq_tx_conf->dcb_queue[i];
2754 tc = &dcb_config->tc_config[j];
2755 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2762 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2763 struct ixgbe_dcb_config *dcb_config)
2765 struct rte_eth_dcb_rx_conf *rx_conf =
2766 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2767 struct ixgbe_dcb_tc_config *tc;
2770 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2771 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2773 /* User Priority to Traffic Class mapping */
2774 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2775 j = rx_conf->dcb_queue[i];
2776 tc = &dcb_config->tc_config[j];
2777 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2783 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2784 struct ixgbe_dcb_config *dcb_config)
2786 struct rte_eth_dcb_tx_conf *tx_conf =
2787 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2788 struct ixgbe_dcb_tc_config *tc;
2791 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2792 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2794 /* User Priority to Traffic Class mapping */
2795 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2796 j = tx_conf->dcb_queue[i];
2797 tc = &dcb_config->tc_config[j];
2798 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2804 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2805 * @hw: pointer to hardware structure
2806 * @dcb_config: pointer to ixgbe_dcb_config structure
2809 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2810 struct ixgbe_dcb_config *dcb_config)
2816 PMD_INIT_FUNC_TRACE();
2818 * Disable the arbiter before changing parameters
2819 * (always enable recycle mode; WSP)
2821 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2822 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2824 if (hw->mac.type != ixgbe_mac_82598EB) {
2825 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2826 if (dcb_config->num_tcs.pg_tcs == 4) {
2827 if (dcb_config->vt_mode)
2828 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2829 IXGBE_MRQC_VMDQRT4TCEN;
2831 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2832 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2836 if (dcb_config->num_tcs.pg_tcs == 8) {
2837 if (dcb_config->vt_mode)
2838 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2839 IXGBE_MRQC_VMDQRT8TCEN;
2841 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2842 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2847 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2850 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2851 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2852 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2853 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2855 /* VFTA - enable all vlan filters */
2856 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2857 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2861 * Configure Rx packet plane (recycle mode; WSP) and
2864 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2865 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2871 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2872 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2874 switch (hw->mac.type) {
2875 case ixgbe_mac_82598EB:
2876 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2878 case ixgbe_mac_82599EB:
2879 case ixgbe_mac_X540:
2880 case ixgbe_mac_X550:
2881 case ixgbe_mac_X550EM_x:
2882 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2891 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2892 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2894 switch (hw->mac.type) {
2895 case ixgbe_mac_82598EB:
2896 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2897 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2899 case ixgbe_mac_82599EB:
2900 case ixgbe_mac_X540:
2901 case ixgbe_mac_X550:
2902 case ixgbe_mac_X550EM_x:
2903 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2904 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2911 #define DCB_RX_CONFIG 1
2912 #define DCB_TX_CONFIG 1
2913 #define DCB_TX_PB 1024
2915 * ixgbe_dcb_hw_configure - Enable DCB and configure
2916 * general DCB in VT mode and non-VT mode parameters
2917 * @dev: pointer to rte_eth_dev structure
2918 * @dcb_config: pointer to ixgbe_dcb_config structure
2921 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2922 struct ixgbe_dcb_config *dcb_config)
2925 uint8_t i,pfc_en,nb_tcs;
2927 uint8_t config_dcb_rx = 0;
2928 uint8_t config_dcb_tx = 0;
2929 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2930 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2931 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2932 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2933 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2934 struct ixgbe_dcb_tc_config *tc;
2935 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2936 struct ixgbe_hw *hw =
2937 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2939 switch(dev->data->dev_conf.rxmode.mq_mode){
2940 case ETH_MQ_RX_VMDQ_DCB:
2941 dcb_config->vt_mode = true;
2942 if (hw->mac.type != ixgbe_mac_82598EB) {
2943 config_dcb_rx = DCB_RX_CONFIG;
2945 *get dcb and VT rx configuration parameters
2948 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2949 /*Configure general VMDQ and DCB RX parameters*/
2950 ixgbe_vmdq_dcb_configure(dev);
2954 dcb_config->vt_mode = false;
2955 config_dcb_rx = DCB_RX_CONFIG;
2956 /* Get dcb TX configuration parameters from rte_eth_conf */
2957 ixgbe_dcb_rx_config(dev,dcb_config);
2958 /*Configure general DCB RX parameters*/
2959 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2962 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
2965 switch (dev->data->dev_conf.txmode.mq_mode) {
2966 case ETH_MQ_TX_VMDQ_DCB:
2967 dcb_config->vt_mode = true;
2968 config_dcb_tx = DCB_TX_CONFIG;
2969 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2970 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2971 /*Configure general VMDQ and DCB TX parameters*/
2972 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2976 dcb_config->vt_mode = false;
2977 config_dcb_tx = DCB_TX_CONFIG;
2978 /*get DCB TX configuration parameters from rte_eth_conf*/
2979 ixgbe_dcb_tx_config(dev,dcb_config);
2980 /*Configure general DCB TX parameters*/
2981 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2984 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
2988 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2990 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2991 if(nb_tcs == ETH_4_TCS) {
2992 /* Avoid un-configured priority mapping to TC0 */
2994 uint8_t mask = 0xFF;
2995 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2996 mask = (uint8_t)(mask & (~ (1 << map[i])));
2997 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2998 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3002 /* Re-configure 4 TCs BW */
3003 for (i = 0; i < nb_tcs; i++) {
3004 tc = &dcb_config->tc_config[i];
3005 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3006 (uint8_t)(100 / nb_tcs);
3007 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3008 (uint8_t)(100 / nb_tcs);
3010 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3011 tc = &dcb_config->tc_config[i];
3012 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3013 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3018 /* Set RX buffer size */
3019 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3020 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3021 for (i = 0 ; i < nb_tcs; i++) {
3022 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3024 /* zero alloc all unused TCs */
3025 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3026 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3030 /* Only support an equally distributed Tx packet buffer strategy. */
3031 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3032 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3033 for (i = 0; i < nb_tcs; i++) {
3034 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3035 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3037 /* Clear unused TCs, if any, to zero buffer size*/
3038 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3039 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3040 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3044 /*Calculates traffic class credits*/
3045 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3046 IXGBE_DCB_TX_CONFIG);
3047 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3048 IXGBE_DCB_RX_CONFIG);
3051 /* Unpack CEE standard containers */
3052 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3053 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3054 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3055 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3056 /* Configure PG(ETS) RX */
3057 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3061 /* Unpack CEE standard containers */
3062 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3063 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3064 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3065 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3066 /* Configure PG(ETS) TX */
3067 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3070 /*Configure queue statistics registers*/
3071 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3073 /* Check if the PFC is supported */
3074 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3075 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3076 for (i = 0; i < nb_tcs; i++) {
3078 * If the TC count is 8,and the default high_water is 48,
3079 * the low_water is 16 as default.
3081 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3082 hw->fc.low_water[i] = pbsize / 4;
3083 /* Enable pfc for this TC */
3084 tc = &dcb_config->tc_config[i];
3085 tc->pfc = ixgbe_dcb_pfc_enabled;
3087 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3088 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3090 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3097 * ixgbe_configure_dcb - Configure DCB Hardware
3098 * @dev: pointer to rte_eth_dev
3100 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3102 struct ixgbe_dcb_config *dcb_cfg =
3103 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3104 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3106 PMD_INIT_FUNC_TRACE();
3108 /* check support mq_mode for DCB */
3109 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3110 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3113 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3116 /** Configure DCB hardware **/
3117 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3123 * VMDq only support for 10 GbE NIC.
3126 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3128 struct rte_eth_vmdq_rx_conf *cfg;
3129 struct ixgbe_hw *hw;
3130 enum rte_eth_nb_pools num_pools;
3131 uint32_t mrqc, vt_ctl, vlanctrl;
3135 PMD_INIT_FUNC_TRACE();
3136 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3137 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3138 num_pools = cfg->nb_queue_pools;
3140 ixgbe_rss_disable(dev);
3142 /* MRQC: enable vmdq */
3143 mrqc = IXGBE_MRQC_VMDQEN;
3144 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3146 /* PFVTCTL: turn on virtualisation and set the default pool */
3147 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3148 if (cfg->enable_default_pool)
3149 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3151 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3153 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3155 for (i = 0; i < (int)num_pools; i++) {
3156 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3157 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3160 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3161 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3162 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3163 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3165 /* VFTA - enable all vlan filters */
3166 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3167 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3169 /* VFRE: pool enabling for receive - 64 */
3170 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3171 if (num_pools == ETH_64_POOLS)
3172 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3175 * MPSAR - allow pools to read specific mac addresses
3176 * In this case, all pools should be able to read from mac addr 0
3178 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3179 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3181 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3182 for (i = 0; i < cfg->nb_pool_maps; i++) {
3183 /* set vlan id in VF register and set the valid bit */
3184 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3185 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3187 * Put the allowed pools in VFB reg. As we only have 16 or 64
3188 * pools, we only need to use the first half of the register
3191 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3192 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3193 (cfg->pool_map[i].pools & UINT32_MAX));
3195 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3196 ((cfg->pool_map[i].pools >> 32) \
3201 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3202 if (cfg->enable_loop_back) {
3203 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3204 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3205 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3208 IXGBE_WRITE_FLUSH(hw);
3212 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3213 * @hw: pointer to hardware structure
3216 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3221 PMD_INIT_FUNC_TRACE();
3222 /*PF VF Transmit Enable*/
3223 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3224 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3226 /* Disable the Tx desc arbiter so that MTQC can be changed */
3227 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3228 reg |= IXGBE_RTTDCS_ARBDIS;
3229 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3231 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3232 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3234 /* Disable drop for all queues */
3235 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3236 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3237 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3239 /* Enable the Tx desc arbiter */
3240 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3241 reg &= ~IXGBE_RTTDCS_ARBDIS;
3242 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3244 IXGBE_WRITE_FLUSH(hw);
3250 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
3252 struct igb_rx_entry *rxe = rxq->sw_ring;
3256 /* Initialize software ring entries */
3257 for (i = 0; i < rxq->nb_rx_desc; i++) {
3258 volatile union ixgbe_adv_rx_desc *rxd;
3259 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3261 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3262 (unsigned) rxq->queue_id);
3266 rte_mbuf_refcnt_set(mbuf, 1);
3268 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3270 mbuf->port = rxq->port_id;
3273 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3274 rxd = &rxq->rx_ring[i];
3275 rxd->read.hdr_addr = dma_addr;
3276 rxd->read.pkt_addr = dma_addr;
3284 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3286 struct ixgbe_hw *hw =
3287 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3289 if (hw->mac.type == ixgbe_mac_82598EB)
3292 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3294 * SRIOV inactive scheme
3295 * any DCB/RSS w/o VMDq multi-queue setting
3297 switch (dev->data->dev_conf.rxmode.mq_mode) {
3299 ixgbe_rss_configure(dev);
3302 case ETH_MQ_RX_VMDQ_DCB:
3303 ixgbe_vmdq_dcb_configure(dev);
3306 case ETH_MQ_RX_VMDQ_ONLY:
3307 ixgbe_vmdq_rx_hw_configure(dev);
3310 case ETH_MQ_RX_NONE:
3311 /* if mq_mode is none, disable rss mode.*/
3312 default: ixgbe_rss_disable(dev);
3315 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3317 * SRIOV active scheme
3318 * FIXME if support DCB/RSS together with VMDq & SRIOV
3321 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN);
3325 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN);
3329 IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN);
3332 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3340 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3342 struct ixgbe_hw *hw =
3343 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3347 if (hw->mac.type == ixgbe_mac_82598EB)
3350 /* disable arbiter before setting MTQC */
3351 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3352 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3353 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3355 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3357 * SRIOV inactive scheme
3358 * any DCB w/o VMDq multi-queue setting
3360 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3361 ixgbe_vmdq_tx_hw_configure(hw);
3363 mtqc = IXGBE_MTQC_64Q_1PB;
3364 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3367 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3370 * SRIOV active scheme
3371 * FIXME if support DCB together with VMDq & SRIOV
3374 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3377 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3380 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3384 mtqc = IXGBE_MTQC_64Q_1PB;
3385 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3387 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3390 /* re-enable arbiter */
3391 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3392 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3398 * Initializes Receive Unit.
3401 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3403 struct ixgbe_hw *hw;
3404 struct igb_rx_queue *rxq;
3405 struct rte_pktmbuf_pool_private *mbp_priv;
3417 PMD_INIT_FUNC_TRACE();
3418 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3421 * Make sure receives are disabled while setting
3422 * up the RX context (registers, descriptor rings, etc.).
3424 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3425 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3427 /* Enable receipt of broadcasted frames */
3428 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3429 fctrl |= IXGBE_FCTRL_BAM;
3430 fctrl |= IXGBE_FCTRL_DPF;
3431 fctrl |= IXGBE_FCTRL_PMCF;
3432 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3435 * Configure CRC stripping, if any.
3437 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3438 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3439 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3441 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3444 * Configure jumbo frame support, if any.
3446 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3447 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3448 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3449 maxfrs &= 0x0000FFFF;
3450 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3451 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3453 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3456 * If loopback mode is configured for 82599, set LPBK bit.
3458 if (hw->mac.type == ixgbe_mac_82599EB &&
3459 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3460 hlreg0 |= IXGBE_HLREG0_LPBK;
3462 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3464 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3466 /* Setup RX queues */
3467 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3468 rxq = dev->data->rx_queues[i];
3471 * Reset crc_len in case it was changed after queue setup by a
3472 * call to configure.
3474 rxq->crc_len = (uint8_t)
3475 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3478 /* Setup the Base and Length of the Rx Descriptor Rings */
3479 bus_addr = rxq->rx_ring_phys_addr;
3480 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3481 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3482 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3483 (uint32_t)(bus_addr >> 32));
3484 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3485 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3486 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3487 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3489 /* Configure the SRRCTL register */
3490 #ifdef RTE_HEADER_SPLIT_ENABLE
3492 * Configure Header Split
3494 if (dev->data->dev_conf.rxmode.header_split) {
3495 if (hw->mac.type == ixgbe_mac_82599EB) {
3496 /* Must setup the PSRTYPE register */
3498 psrtype = IXGBE_PSRTYPE_TCPHDR |
3499 IXGBE_PSRTYPE_UDPHDR |
3500 IXGBE_PSRTYPE_IPV4HDR |
3501 IXGBE_PSRTYPE_IPV6HDR;
3502 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3504 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3505 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3506 IXGBE_SRRCTL_BSIZEHDR_MASK);
3507 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3510 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3512 /* Set if packets are dropped when no descriptors available */
3514 srrctl |= IXGBE_SRRCTL_DROP_EN;
3517 * Configure the RX buffer size in the BSIZEPACKET field of
3518 * the SRRCTL register of the queue.
3519 * The value is in 1 KB resolution. Valid values can be from
3522 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3523 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3524 RTE_PKTMBUF_HEADROOM);
3525 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3526 IXGBE_SRRCTL_BSIZEPKT_MASK);
3527 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3529 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3530 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3532 /* It adds dual VLAN length for supporting dual VLAN */
3533 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
3534 2 * IXGBE_VLAN_TAG_SIZE) > buf_size){
3535 if (!dev->data->scattered_rx)
3536 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
3537 dev->data->scattered_rx = 1;
3538 #ifdef RTE_IXGBE_INC_VECTOR
3539 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3541 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3546 if (dev->data->dev_conf.rxmode.enable_scatter) {
3547 if (!dev->data->scattered_rx)
3548 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
3549 #ifdef RTE_IXGBE_INC_VECTOR
3550 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3552 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3554 dev->data->scattered_rx = 1;
3558 * Device configured with multiple RX queues.
3560 ixgbe_dev_mq_rx_configure(dev);
3563 * Setup the Checksum Register.
3564 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3565 * Enable IP/L4 checkum computation by hardware if requested to do so.
3567 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3568 rxcsum |= IXGBE_RXCSUM_PCSD;
3569 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3570 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3572 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3574 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3576 if (hw->mac.type == ixgbe_mac_82599EB) {
3577 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3578 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3579 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3581 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3582 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3583 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3590 * Initializes Transmit Unit.
3593 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3595 struct ixgbe_hw *hw;
3596 struct igb_tx_queue *txq;
3602 PMD_INIT_FUNC_TRACE();
3603 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3605 /* Enable TX CRC (checksum offload requirement) */
3606 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3607 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3608 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3610 /* Setup the Base and Length of the Tx Descriptor Rings */
3611 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3612 txq = dev->data->tx_queues[i];
3614 bus_addr = txq->tx_ring_phys_addr;
3615 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3616 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3617 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3618 (uint32_t)(bus_addr >> 32));
3619 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3620 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3621 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3622 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3623 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3626 * Disable Tx Head Writeback RO bit, since this hoses
3627 * bookkeeping if things aren't delivered in order.
3629 switch (hw->mac.type) {
3630 case ixgbe_mac_82598EB:
3631 txctrl = IXGBE_READ_REG(hw,
3632 IXGBE_DCA_TXCTRL(txq->reg_idx));
3633 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3634 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3638 case ixgbe_mac_82599EB:
3639 case ixgbe_mac_X540:
3640 case ixgbe_mac_X550:
3641 case ixgbe_mac_X550EM_x:
3643 txctrl = IXGBE_READ_REG(hw,
3644 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3645 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3646 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3652 /* Device configured with multiple TX queues. */
3653 ixgbe_dev_mq_tx_configure(dev);
3657 * Set up link for 82599 loopback mode Tx->Rx.
3660 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3662 PMD_INIT_FUNC_TRACE();
3664 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3665 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3667 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
3676 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3677 ixgbe_reset_pipeline_82599(hw);
3679 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3685 * Start Transmit and Receive Units.
3688 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3690 struct ixgbe_hw *hw;
3691 struct igb_tx_queue *txq;
3692 struct igb_rx_queue *rxq;
3698 PMD_INIT_FUNC_TRACE();
3699 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3701 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3702 txq = dev->data->tx_queues[i];
3703 /* Setup Transmit Threshold Registers */
3704 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3705 txdctl |= txq->pthresh & 0x7F;
3706 txdctl |= ((txq->hthresh & 0x7F) << 8);
3707 txdctl |= ((txq->wthresh & 0x7F) << 16);
3708 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3711 if (hw->mac.type != ixgbe_mac_82598EB) {
3712 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3713 dmatxctl |= IXGBE_DMATXCTL_TE;
3714 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3717 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3718 txq = dev->data->tx_queues[i];
3719 if (!txq->tx_deferred_start)
3720 ixgbe_dev_tx_queue_start(dev, i);
3723 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3724 rxq = dev->data->rx_queues[i];
3725 if (!rxq->rx_deferred_start)
3726 ixgbe_dev_rx_queue_start(dev, i);
3729 /* Enable Receive engine */
3730 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3731 if (hw->mac.type == ixgbe_mac_82598EB)
3732 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3733 rxctrl |= IXGBE_RXCTRL_RXEN;
3734 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3736 /* If loopback mode is enabled for 82599, set up the link accordingly */
3737 if (hw->mac.type == ixgbe_mac_82599EB &&
3738 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3739 ixgbe_setup_loopback_link_82599(hw);
3744 * Start Receive Units for specified queue.
3747 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3749 struct ixgbe_hw *hw;
3750 struct igb_rx_queue *rxq;
3754 PMD_INIT_FUNC_TRACE();
3755 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3757 if (rx_queue_id < dev->data->nb_rx_queues) {
3758 rxq = dev->data->rx_queues[rx_queue_id];
3760 /* Allocate buffers for descriptor rings */
3761 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3762 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
3766 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3767 rxdctl |= IXGBE_RXDCTL_ENABLE;
3768 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3770 /* Wait until RX Enable ready */
3771 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3774 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3775 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3777 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
3780 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3781 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3789 * Stop Receive Units for specified queue.
3792 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3794 struct ixgbe_hw *hw;
3795 struct igb_rx_queue *rxq;
3799 PMD_INIT_FUNC_TRACE();
3800 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3802 if (rx_queue_id < dev->data->nb_rx_queues) {
3803 rxq = dev->data->rx_queues[rx_queue_id];
3805 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3806 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3807 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3809 /* Wait until RX Enable ready */
3810 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3813 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3814 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3816 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
3819 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3821 ixgbe_rx_queue_release_mbufs(rxq);
3822 ixgbe_reset_rx_queue(rxq);
3831 * Start Transmit Units for specified queue.
3834 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3836 struct ixgbe_hw *hw;
3837 struct igb_tx_queue *txq;
3841 PMD_INIT_FUNC_TRACE();
3842 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3844 if (tx_queue_id < dev->data->nb_tx_queues) {
3845 txq = dev->data->tx_queues[tx_queue_id];
3846 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3847 txdctl |= IXGBE_TXDCTL_ENABLE;
3848 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3850 /* Wait until TX Enable ready */
3851 if (hw->mac.type == ixgbe_mac_82599EB) {
3852 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3855 txdctl = IXGBE_READ_REG(hw,
3856 IXGBE_TXDCTL(txq->reg_idx));
3857 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3859 PMD_INIT_LOG(ERR, "Could not enable "
3860 "Tx Queue %d", tx_queue_id);
3863 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3864 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3872 * Stop Transmit Units for specified queue.
3875 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
3877 struct ixgbe_hw *hw;
3878 struct igb_tx_queue *txq;
3880 uint32_t txtdh, txtdt;
3883 PMD_INIT_FUNC_TRACE();
3884 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3886 if (tx_queue_id < dev->data->nb_tx_queues) {
3887 txq = dev->data->tx_queues[tx_queue_id];
3889 /* Wait until TX queue is empty */
3890 if (hw->mac.type == ixgbe_mac_82599EB) {
3891 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3893 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3894 txtdh = IXGBE_READ_REG(hw,
3895 IXGBE_TDH(txq->reg_idx));
3896 txtdt = IXGBE_READ_REG(hw,
3897 IXGBE_TDT(txq->reg_idx));
3898 } while (--poll_ms && (txtdh != txtdt));
3900 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
3901 "when stopping.", tx_queue_id);
3904 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3905 txdctl &= ~IXGBE_TXDCTL_ENABLE;
3906 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3908 /* Wait until TX Enable ready */
3909 if (hw->mac.type == ixgbe_mac_82599EB) {
3910 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3913 txdctl = IXGBE_READ_REG(hw,
3914 IXGBE_TXDCTL(txq->reg_idx));
3915 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
3917 PMD_INIT_LOG(ERR, "Could not disable "
3918 "Tx Queue %d", tx_queue_id);
3921 if (txq->ops != NULL) {
3922 txq->ops->release_mbufs(txq);
3923 txq->ops->reset(txq);
3932 * [VF] Initializes Receive Unit.
3935 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3937 struct ixgbe_hw *hw;
3938 struct igb_rx_queue *rxq;
3939 struct rte_pktmbuf_pool_private *mbp_priv;
3946 PMD_INIT_FUNC_TRACE();
3947 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3950 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
3951 * disables the VF receipt of packets if the PF MTU is > 1500.
3952 * This is done to deal with 82599 limitations that imposes
3953 * the PF and all VFs to share the same MTU.
3954 * Then, the PF driver enables again the VF receipt of packet when
3955 * the VF driver issues a IXGBE_VF_SET_LPE request.
3956 * In the meantime, the VF device cannot be used, even if the VF driver
3957 * and the Guest VM network stack are ready to accept packets with a
3958 * size up to the PF MTU.
3959 * As a work-around to this PF behaviour, force the call to
3960 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
3961 * VF packets received can work in all cases.
3963 ixgbevf_rlpml_set_vf(hw,
3964 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
3966 /* Setup RX queues */
3967 dev->rx_pkt_burst = ixgbe_recv_pkts;
3968 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3969 rxq = dev->data->rx_queues[i];
3971 /* Allocate buffers for descriptor rings */
3972 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3976 /* Setup the Base and Length of the Rx Descriptor Rings */
3977 bus_addr = rxq->rx_ring_phys_addr;
3979 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3980 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3981 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3982 (uint32_t)(bus_addr >> 32));
3983 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3984 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3985 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3986 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3989 /* Configure the SRRCTL register */
3990 #ifdef RTE_HEADER_SPLIT_ENABLE
3992 * Configure Header Split
3994 if (dev->data->dev_conf.rxmode.header_split) {
3996 /* Must setup the PSRTYPE register */
3998 psrtype = IXGBE_PSRTYPE_TCPHDR |
3999 IXGBE_PSRTYPE_UDPHDR |
4000 IXGBE_PSRTYPE_IPV4HDR |
4001 IXGBE_PSRTYPE_IPV6HDR;
4003 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
4005 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4006 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4007 IXGBE_SRRCTL_BSIZEHDR_MASK);
4008 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4011 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4013 /* Set if packets are dropped when no descriptors available */
4015 srrctl |= IXGBE_SRRCTL_DROP_EN;
4018 * Configure the RX buffer size in the BSIZEPACKET field of
4019 * the SRRCTL register of the queue.
4020 * The value is in 1 KB resolution. Valid values can be from
4023 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
4024 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
4025 RTE_PKTMBUF_HEADROOM);
4026 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4027 IXGBE_SRRCTL_BSIZEPKT_MASK);
4030 * VF modification to write virtual function SRRCTL register
4032 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4034 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4035 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4037 /* It adds dual VLAN length for supporting dual VLAN */
4038 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
4039 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4040 if (!dev->data->scattered_rx)
4041 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4042 dev->data->scattered_rx = 1;
4043 #ifdef RTE_IXGBE_INC_VECTOR
4044 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4046 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4051 if (dev->data->dev_conf.rxmode.enable_scatter) {
4052 if (!dev->data->scattered_rx)
4053 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4054 #ifdef RTE_IXGBE_INC_VECTOR
4055 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
4057 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4059 dev->data->scattered_rx = 1;
4066 * [VF] Initializes Transmit Unit.
4069 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4071 struct ixgbe_hw *hw;
4072 struct igb_tx_queue *txq;
4077 PMD_INIT_FUNC_TRACE();
4078 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4080 /* Setup the Base and Length of the Tx Descriptor Rings */
4081 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4082 txq = dev->data->tx_queues[i];
4083 bus_addr = txq->tx_ring_phys_addr;
4084 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4085 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4086 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4087 (uint32_t)(bus_addr >> 32));
4088 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4089 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4090 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4091 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4092 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4095 * Disable Tx Head Writeback RO bit, since this hoses
4096 * bookkeeping if things aren't delivered in order.
4098 txctrl = IXGBE_READ_REG(hw,
4099 IXGBE_VFDCA_TXCTRL(i));
4100 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4101 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4107 * [VF] Start Transmit and Receive Units.
4110 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4112 struct ixgbe_hw *hw;
4113 struct igb_tx_queue *txq;
4114 struct igb_rx_queue *rxq;
4120 PMD_INIT_FUNC_TRACE();
4121 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4123 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4124 txq = dev->data->tx_queues[i];
4125 /* Setup Transmit Threshold Registers */
4126 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4127 txdctl |= txq->pthresh & 0x7F;
4128 txdctl |= ((txq->hthresh & 0x7F) << 8);
4129 txdctl |= ((txq->wthresh & 0x7F) << 16);
4130 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4133 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4135 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4136 txdctl |= IXGBE_TXDCTL_ENABLE;
4137 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4140 /* Wait until TX Enable ready */
4143 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4144 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4146 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4148 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4150 rxq = dev->data->rx_queues[i];
4152 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4153 rxdctl |= IXGBE_RXDCTL_ENABLE;
4154 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4156 /* Wait until RX Enable ready */
4160 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4161 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4163 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4165 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);