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35 #include <sys/queue.h>
47 #include <rte_byteorder.h>
48 #include <rte_common.h>
49 #include <rte_cycles.h>
51 #include <rte_debug.h>
52 #include <rte_interrupts.h>
54 #include <rte_memory.h>
55 #include <rte_memzone.h>
56 #include <rte_launch.h>
57 #include <rte_tailq.h>
59 #include <rte_per_lcore.h>
60 #include <rte_lcore.h>
61 #include <rte_atomic.h>
62 #include <rte_branch_prediction.h>
64 #include <rte_mempool.h>
65 #include <rte_malloc.h>
67 #include <rte_ether.h>
68 #include <rte_ethdev.h>
69 #include <rte_prefetch.h>
73 #include <rte_string_fns.h>
74 #include <rte_errno.h>
76 #include "ixgbe_logs.h"
77 #include "ixgbe/ixgbe_api.h"
78 #include "ixgbe/ixgbe_vf.h"
79 #include "ixgbe_ethdev.h"
80 #include "ixgbe/ixgbe_dcb.h"
82 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
83 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
86 static inline struct rte_mbuf *
87 rte_rxmbuf_alloc(struct rte_mempool *mp)
91 m = __rte_mbuf_raw_alloc(mp);
92 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
96 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
97 (uint64_t) ((mb)->buf_physaddr + (uint64_t)((char *)((mb)->pkt.data) - \
98 (char *)(mb)->buf_addr))
100 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
101 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
104 * Structure associated with each descriptor of the RX ring of a RX queue.
106 struct igb_rx_entry {
107 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
111 * Structure associated with each descriptor of the TX ring of a TX queue.
113 struct igb_tx_entry {
114 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
115 uint16_t next_id; /**< Index of next descriptor in ring. */
116 uint16_t last_id; /**< Index of last scattered descriptor. */
120 * Structure associated with each RX queue.
122 struct igb_rx_queue {
123 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
124 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
125 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
126 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
127 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
128 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
129 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
130 uint16_t nb_rx_desc; /**< number of RX descriptors. */
131 uint16_t rx_tail; /**< current value of RDT register. */
132 uint16_t nb_rx_hold; /**< number of held free RX desc. */
133 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
134 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
135 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
136 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
138 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
139 uint16_t queue_id; /**< RX queue index. */
140 uint8_t port_id; /**< Device port identifier. */
141 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
142 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
143 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
144 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
145 struct rte_mbuf fake_mbuf;
146 /** hold packets to return to application */
147 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
152 * IXGBE CTX Constants
154 enum ixgbe_advctx_num {
155 IXGBE_CTX_0 = 0, /**< CTX0 */
156 IXGBE_CTX_1 = 1, /**< CTX1 */
157 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
161 * Structure to check if new context need be built
163 struct ixgbe_advctx_info {
164 uint16_t flags; /**< ol_flags for context build. */
165 uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
166 uint32_t vlan_macip_lens; /**< vlan, mac ip length. */
170 * Structure associated with each TX queue.
172 struct igb_tx_queue {
173 /** TX ring virtual address. */
174 volatile union ixgbe_adv_tx_desc *tx_ring;
175 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
176 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
177 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
178 uint16_t nb_tx_desc; /**< number of TX descriptors. */
179 uint16_t tx_tail; /**< current value of TDT reg. */
180 uint16_t tx_free_thresh;/**< minimum TX before freeing. */
181 /** Number of TX descriptors to use before RS bit is set. */
182 uint16_t tx_rs_thresh;
183 /** Number of TX descriptors used since RS bit was set. */
185 /** Index to last TX descriptor to have been cleaned. */
186 uint16_t last_desc_cleaned;
187 /** Total number of TX descriptors ready to be allocated. */
189 uint16_t queue_id; /**< TX queue index. */
190 uint8_t port_id; /**< Device port identifier. */
191 uint8_t pthresh; /**< Prefetch threshold register. */
192 uint8_t hthresh; /**< Host threshold register. */
193 uint8_t wthresh; /**< Write-back threshold reg. */
194 uint32_t ctx_curr; /**< Hardware context states. */
195 /** Hardware context0 history. */
196 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
201 #define RTE_PMD_USE_PREFETCH
204 #ifdef RTE_PMD_USE_PREFETCH
206 * Prefetch a cache line into all cache levels.
208 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
210 #define rte_ixgbe_prefetch(p) do {} while(0)
213 #ifdef RTE_PMD_PACKET_PREFETCH
214 #define rte_packet_prefetch(p) rte_prefetch1(p)
216 #define rte_packet_prefetch(p) do {} while(0)
219 /*********************************************************************
223 **********************************************************************/
225 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
226 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
227 uint16_t ol_flags, uint32_t vlan_macip_lens)
229 uint32_t type_tucmd_mlhl;
230 uint32_t mss_l4len_idx;
234 ctx_idx = txq->ctx_curr;
238 if (ol_flags & PKT_TX_VLAN_PKT) {
239 cmp_mask |= TX_VLAN_CMP_MASK;
242 if (ol_flags & PKT_TX_IP_CKSUM) {
243 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
244 cmp_mask |= TX_MAC_LEN_CMP_MASK;
247 /* Specify which HW CTX to upload. */
248 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
249 switch (ol_flags & PKT_TX_L4_MASK) {
250 case PKT_TX_UDP_CKSUM:
251 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
252 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
253 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
254 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
256 case PKT_TX_TCP_CKSUM:
257 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
258 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
259 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
260 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
262 case PKT_TX_SCTP_CKSUM:
263 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
264 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
265 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
266 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
269 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
270 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
274 txq->ctx_cache[ctx_idx].flags = ol_flags;
275 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
276 txq->ctx_cache[ctx_idx].vlan_macip_lens = vlan_macip_lens & cmp_mask;
278 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
279 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
280 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
281 ctx_txd->seqnum_seed = 0;
285 * Check which hardware context can be used. Use the existing match
286 * or create a new context descriptor.
288 static inline uint32_t
289 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
290 uint32_t vlan_macip_lens)
292 /* If match with the current used context */
293 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
294 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens ==
295 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
296 return txq->ctx_curr;
299 /* What if match with the next context */
301 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
302 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens ==
303 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
304 return txq->ctx_curr;
307 /* Mismatch, use the previous context */
308 return (IXGBE_CTX_NUM);
311 static inline uint32_t
312 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
314 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
315 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
318 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
319 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
323 static inline uint32_t
324 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
326 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
327 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
330 /* Default RS bit threshold values */
331 #ifndef DEFAULT_TX_RS_THRESH
332 #define DEFAULT_TX_RS_THRESH 32
334 #ifndef DEFAULT_TX_FREE_THRESH
335 #define DEFAULT_TX_FREE_THRESH 32
338 /* Reset transmit descriptors after they have been used */
340 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
342 struct igb_tx_entry *sw_ring = txq->sw_ring;
343 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
344 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
345 uint16_t nb_tx_desc = txq->nb_tx_desc;
346 uint16_t desc_to_clean_to;
347 uint16_t nb_tx_to_clean;
349 /* Determine the last descriptor needing to be cleaned */
350 desc_to_clean_to = last_desc_cleaned + txq->tx_rs_thresh;
351 if (desc_to_clean_to >= nb_tx_desc)
352 desc_to_clean_to = desc_to_clean_to - nb_tx_desc;
354 /* Check to make sure the last descriptor to clean is done */
355 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
356 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
358 PMD_TX_FREE_LOG(DEBUG,
359 "TX descriptor %4u is not done"
360 "(port=%d queue=%d)",
362 txq->port_id, txq->queue_id);
363 /* Failed to clean any descriptors, better luck next time */
367 /* Figure out how many descriptors will be cleaned */
368 if (last_desc_cleaned > desc_to_clean_to)
369 nb_tx_to_clean = ((nb_tx_desc - last_desc_cleaned) +
372 nb_tx_to_clean = desc_to_clean_to - last_desc_cleaned;
374 PMD_TX_FREE_LOG(DEBUG,
375 "Cleaning %4u TX descriptors: %4u to %4u "
376 "(port=%d queue=%d)",
377 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
378 txq->port_id, txq->queue_id);
381 * The last descriptor to clean is done, so that means all the
382 * descriptors from the last descriptor that was cleaned
383 * up to the last descriptor with the RS bit set
384 * are done. Only reset the threshold descriptor.
386 txr[desc_to_clean_to].wb.status = 0;
388 /* Update the txq to reflect the last descriptor that was cleaned */
389 txq->last_desc_cleaned = desc_to_clean_to;
390 txq->nb_tx_free += nb_tx_to_clean;
397 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
400 struct igb_tx_queue *txq;
401 struct igb_tx_entry *sw_ring;
402 struct igb_tx_entry *txe, *txn;
403 volatile union ixgbe_adv_tx_desc *txr;
404 volatile union ixgbe_adv_tx_desc *txd;
405 struct rte_mbuf *tx_pkt;
406 struct rte_mbuf *m_seg;
407 uint64_t buf_dma_addr;
408 uint32_t olinfo_status;
409 uint32_t cmd_type_len;
418 uint32_t vlan_macip_lens;
423 sw_ring = txq->sw_ring;
425 tx_id = txq->tx_tail;
426 txe = &sw_ring[tx_id];
428 /* Determine if the descriptor ring needs to be cleaned. */
429 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
430 ixgbe_xmit_cleanup(txq);
434 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
437 pkt_len = tx_pkt->pkt.pkt_len;
439 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
442 * Determine how many (if any) context descriptors
443 * are needed for offload functionality.
445 ol_flags = tx_pkt->ol_flags;
446 vlan_macip_lens = tx_pkt->pkt.vlan_tci << 16 |
447 tx_pkt->pkt.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT |
450 /* If hardware offload required */
451 tx_ol_req = ol_flags & PKT_TX_OFFLOAD_MASK;
453 /* If new context need be built or reuse the exist ctx. */
454 ctx = what_advctx_update(txq, tx_ol_req, vlan_macip_lens);
455 /* Only allocate context descriptor if required*/
456 new_ctx = (ctx == IXGBE_CTX_NUM);
461 * Keep track of how many descriptors are used this loop
462 * This will always be the number of segments + the number of
463 * Context descriptors required to transmit the packet
465 nb_used = tx_pkt->pkt.nb_segs + new_ctx;
468 * The number of descriptors that must be allocated for a
469 * packet is the number of segments of that packet, plus 1
470 * Context Descriptor for the hardware offload, if any.
471 * Determine the last TX descriptor to allocate in the TX ring
472 * for the packet, starting from the current position (tx_id)
475 tx_last = (uint16_t) (tx_id + nb_used - 1);
478 if (tx_last >= txq->nb_tx_desc)
479 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
481 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
482 " tx_first=%u tx_last=%u\n",
483 (unsigned) txq->port_id,
484 (unsigned) txq->queue_id,
490 * Make sure there are enough TX descriptors available to
491 * transmit the entire packet.
492 * nb_used better be less than or equal to txq->tx_rs_thresh
494 if (nb_used > txq->nb_tx_free) {
495 PMD_TX_FREE_LOG(DEBUG,
496 "Not enough free TX descriptors "
497 "nb_used=%4u nb_free=%4u "
498 "(port=%d queue=%d)",
499 nb_used, txq->nb_tx_free,
500 txq->port_id, txq->queue_id);
502 if (ixgbe_xmit_cleanup(txq) != 0) {
503 /* Could not clean any descriptors */
509 /* nb_used better be <= txq->tx_rs_thresh */
510 if (unlikely(nb_used > txq->tx_rs_thresh)) {
511 PMD_TX_FREE_LOG(DEBUG,
512 "The number of descriptors needed to "
513 "transmit the packet exceeds the "
514 "RS bit threshold. This will impact "
516 "nb_used=%4u nb_free=%4u "
518 "(port=%d queue=%d)",
519 nb_used, txq->nb_tx_free,
521 txq->port_id, txq->queue_id);
523 * Loop here until there are enough TX
524 * descriptors or until the ring cannot be
527 while (nb_used > txq->nb_tx_free) {
528 if (ixgbe_xmit_cleanup(txq) != 0) {
530 * Could not clean any
542 * By now there are enough free TX descriptors to transmit
547 * Set common flags of all TX Data Descriptors.
549 * The following bits must be set in all Data Descriptors:
550 * - IXGBE_ADVTXD_DTYP_DATA
551 * - IXGBE_ADVTXD_DCMD_DEXT
553 * The following bits must be set in the first Data Descriptor
554 * and are ignored in the other ones:
555 * - IXGBE_ADVTXD_DCMD_IFCS
556 * - IXGBE_ADVTXD_MAC_1588
557 * - IXGBE_ADVTXD_DCMD_VLE
559 * The following bits must only be set in the last Data
561 * - IXGBE_TXD_CMD_EOP
563 * The following bits can be set in any Data Descriptor, but
564 * are only set in the last Data Descriptor:
567 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
568 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
569 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
570 #ifdef RTE_LIBRTE_IEEE1588
571 if (ol_flags & PKT_TX_IEEE1588_TMST)
572 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
577 * Setup the TX Advanced Context Descriptor if required
580 volatile struct ixgbe_adv_tx_context_desc *
583 ctx_txd = (volatile struct
584 ixgbe_adv_tx_context_desc *)
587 txn = &sw_ring[txe->next_id];
588 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
590 if (txe->mbuf != NULL) {
591 rte_pktmbuf_free_seg(txe->mbuf);
595 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
598 txe->last_id = tx_last;
599 tx_id = txe->next_id;
604 * Setup the TX Advanced Data Descriptor,
605 * This path will go through
606 * whatever new/reuse the context descriptor
608 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
609 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
610 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
616 txn = &sw_ring[txe->next_id];
618 if (txe->mbuf != NULL)
619 rte_pktmbuf_free_seg(txe->mbuf);
623 * Set up Transmit Data Descriptor.
625 slen = m_seg->pkt.data_len;
626 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
627 txd->read.buffer_addr =
628 rte_cpu_to_le_64(buf_dma_addr);
629 txd->read.cmd_type_len =
630 rte_cpu_to_le_32(cmd_type_len | slen);
631 txd->read.olinfo_status =
632 rte_cpu_to_le_32(olinfo_status);
633 txe->last_id = tx_last;
634 tx_id = txe->next_id;
636 m_seg = m_seg->pkt.next;
637 } while (m_seg != NULL);
640 * The last packet data descriptor needs End Of Packet (EOP)
642 cmd_type_len |= IXGBE_TXD_CMD_EOP;
643 txq->nb_tx_used += nb_used;
644 txq->nb_tx_free -= nb_used;
646 /* Set RS bit only on threshold packets' last descriptor */
647 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
648 PMD_TX_FREE_LOG(DEBUG,
649 "Setting RS bit on TXD id="
650 "%4u (port=%d queue=%d)",
651 tx_last, txq->port_id, txq->queue_id);
653 cmd_type_len |= IXGBE_TXD_CMD_RS;
655 /* Update txq RS bit counters */
658 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
664 * Set the Transmit Descriptor Tail (TDT)
666 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
667 (unsigned) txq->port_id, (unsigned) txq->queue_id,
668 (unsigned) tx_id, (unsigned) nb_tx);
669 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
670 txq->tx_tail = tx_id;
675 /*********************************************************************
679 **********************************************************************/
680 static inline uint16_t
681 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
685 static uint16_t ip_pkt_types_map[16] = {
686 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
687 PKT_RX_IPV6_HDR, 0, 0, 0,
688 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
689 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
692 static uint16_t ip_rss_types_map[16] = {
693 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
694 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
695 PKT_RX_RSS_HASH, 0, 0, 0,
696 0, 0, 0, PKT_RX_FDIR,
699 #ifdef RTE_LIBRTE_IEEE1588
700 static uint32_t ip_pkt_etqf_map[8] = {
701 0, 0, 0, PKT_RX_IEEE1588_PTP,
705 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
706 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
707 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
709 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
710 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
713 return (pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF]);
716 static inline uint16_t
717 rx_desc_status_to_pkt_flags(uint32_t rx_status)
722 * Check if VLAN present only.
723 * Do not check whether L3/L4 rx checksum done by NIC or not,
724 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
726 pkt_flags = (uint16_t) (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
728 #ifdef RTE_LIBRTE_IEEE1588
729 if (rx_status & IXGBE_RXD_STAT_TMST)
730 pkt_flags = (pkt_flags | PKT_RX_IEEE1588_TMST);
735 static inline uint16_t
736 rx_desc_error_to_pkt_flags(uint32_t rx_status)
739 * Bit 31: IPE, IPv4 checksum error
740 * Bit 30: L4I, L4I integrity error
742 static uint16_t error_to_pkt_flags_map[4] = {
743 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
744 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
746 return error_to_pkt_flags_map[(rx_status >>
747 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
750 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
752 * LOOK_AHEAD defines how many desc statuses to check beyond the
753 * current descriptor.
754 * It must be a pound define for optimal performance.
755 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
756 * function only works with LOOK_AHEAD=8.
759 #if (LOOK_AHEAD != 8)
760 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
763 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
765 volatile union ixgbe_adv_rx_desc *rxdp;
766 struct igb_rx_entry *rxep;
769 int s[LOOK_AHEAD], nb_dd;
773 /* get references to current descriptor and S/W ring entry */
774 rxdp = &rxq->rx_ring[rxq->rx_tail];
775 rxep = &rxq->sw_ring[rxq->rx_tail];
777 /* check to make sure there is at least 1 packet to receive */
778 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
782 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
783 * reference packets that are ready to be received.
785 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
786 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
788 /* Read desc statuses backwards to avoid race condition */
789 for (j = LOOK_AHEAD-1; j >= 0; --j)
790 s[j] = rxdp[j].wb.upper.status_error;
792 /* Clear everything but the status bits (LSB) */
793 for (j = 0; j < LOOK_AHEAD; ++j)
794 s[j] &= IXGBE_RXDADV_STAT_DD;
796 /* Compute how many status bits were set */
797 nb_dd = s[0]+s[1]+s[2]+s[3]+s[4]+s[5]+s[6]+s[7];
800 /* Translate descriptor info to mbuf format */
801 for (j = 0; j < nb_dd; ++j) {
803 pkt_len = rxdp[j].wb.upper.length - rxq->crc_len;
804 mb->pkt.data_len = pkt_len;
805 mb->pkt.pkt_len = pkt_len;
806 mb->pkt.vlan_macip.f.vlan_tci = rxdp[j].wb.upper.vlan;
807 mb->pkt.hash.rss = rxdp[j].wb.lower.hi_dword.rss;
809 /* convert descriptor fields to rte mbuf flags */
810 mb->ol_flags = rx_desc_hlen_type_rss_to_pkt_flags(
811 rxdp[j].wb.lower.lo_dword.data);
812 /* reuse status field from scan list */
813 mb->ol_flags |= rx_desc_status_to_pkt_flags(s[j]);
814 mb->ol_flags |= rx_desc_error_to_pkt_flags(s[j]);
817 /* Move mbuf pointers from the S/W ring to the stage */
818 for (j = 0; j < LOOK_AHEAD; ++j) {
819 rxq->rx_stage[i + j] = rxep[j].mbuf;
822 /* stop if all requested packets could not be received */
823 if (nb_dd != LOOK_AHEAD)
827 /* clear software ring entries so we can cleanup correctly */
828 for (i = 0; i < nb_rx; ++i)
829 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
835 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
837 volatile union ixgbe_adv_rx_desc *rxdp;
838 struct igb_rx_entry *rxep;
844 /* allocate buffers in bulk directly into the S/W ring */
845 alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
846 rxep = &rxq->sw_ring[alloc_idx];
847 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
848 rxq->rx_free_thresh);
849 if (unlikely(diag != 0))
852 rxdp = &rxq->rx_ring[alloc_idx];
853 for (i = 0; i < rxq->rx_free_thresh; ++i) {
854 /* populate the static rte mbuf fields */
856 rte_mbuf_refcnt_set(mb, 1);
857 mb->type = RTE_MBUF_PKT;
859 mb->pkt.data = (char *)mb->buf_addr + RTE_PKTMBUF_HEADROOM;
861 mb->pkt.in_port = rxq->port_id;
863 /* populate the descriptors */
864 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
865 rxdp[i].read.hdr_addr = dma_addr;
866 rxdp[i].read.pkt_addr = dma_addr;
869 /* update tail pointer */
871 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
873 /* update state of internal queue structure */
874 rxq->rx_free_trigger += rxq->rx_free_thresh;
875 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
876 rxq->rx_free_trigger = (rxq->rx_free_thresh - 1);
882 static inline uint16_t
883 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
886 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
889 /* how many packets are ready to return? */
890 nb_pkts = RTE_MIN(nb_pkts, rxq->rx_nb_avail);
892 /* copy mbuf pointers to the application's packet list */
893 for (i = 0; i < nb_pkts; ++i)
894 rx_pkts[i] = stage[i];
896 /* update internal queue state */
897 rxq->rx_nb_avail -= nb_pkts;
898 rxq->rx_next_avail += nb_pkts;
903 static inline uint16_t
904 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
907 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
910 /* Any previously recv'd pkts will be returned from the Rx stage */
911 if (rxq->rx_nb_avail)
912 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
914 /* Scan the H/W ring for packets to receive */
915 nb_rx = ixgbe_rx_scan_hw_ring(rxq);
917 /* update internal queue state */
918 rxq->rx_next_avail = 0;
919 rxq->rx_nb_avail = nb_rx;
920 rxq->rx_tail += nb_rx;
922 /* if required, allocate new buffers to replenish descriptors */
923 if (rxq->rx_tail > rxq->rx_free_trigger) {
924 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
926 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
927 "queue_id=%u\n", (unsigned) rxq->port_id,
928 (unsigned) rxq->queue_id);
930 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
934 * Need to rewind any previous receives if we cannot
935 * allocate new buffers to replenish the old ones.
937 rxq->rx_nb_avail = 0;
938 rxq->rx_tail -= nb_rx;
939 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
940 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
946 if (rxq->rx_tail >= rxq->nb_rx_desc)
949 /* received any packets this loop? */
950 if (rxq->rx_nb_avail)
951 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
956 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
958 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
963 if (unlikely(nb_pkts == 0))
966 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
967 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
969 /* request is relatively large, chunk it up */
973 n = RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
974 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
983 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
986 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
989 struct igb_rx_queue *rxq;
990 volatile union ixgbe_adv_rx_desc *rx_ring;
991 volatile union ixgbe_adv_rx_desc *rxdp;
992 struct igb_rx_entry *sw_ring;
993 struct igb_rx_entry *rxe;
994 struct rte_mbuf *rxm;
995 struct rte_mbuf *nmb;
996 union ixgbe_adv_rx_desc rxd;
999 uint32_t hlen_type_rss;
1009 rx_id = rxq->rx_tail;
1010 rx_ring = rxq->rx_ring;
1011 sw_ring = rxq->sw_ring;
1012 while (nb_rx < nb_pkts) {
1014 * The order of operations here is important as the DD status
1015 * bit must not be read after any other descriptor fields.
1016 * rx_ring and rxdp are pointing to volatile data so the order
1017 * of accesses cannot be reordered by the compiler. If they were
1018 * not volatile, they could be reordered which could lead to
1019 * using invalid descriptor fields when read from rxd.
1021 rxdp = &rx_ring[rx_id];
1022 staterr = rxdp->wb.upper.status_error;
1023 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1030 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1031 * is likely to be invalid and to be dropped by the various
1032 * validation checks performed by the network stack.
1034 * Allocate a new mbuf to replenish the RX ring descriptor.
1035 * If the allocation fails:
1036 * - arrange for that RX descriptor to be the first one
1037 * being parsed the next time the receive function is
1038 * invoked [on the same queue].
1040 * - Stop parsing the RX ring and return immediately.
1042 * This policy do not drop the packet received in the RX
1043 * descriptor for which the allocation of a new mbuf failed.
1044 * Thus, it allows that packet to be later retrieved if
1045 * mbuf have been freed in the mean time.
1046 * As a side effect, holding RX descriptors instead of
1047 * systematically giving them back to the NIC may lead to
1048 * RX ring exhaustion situations.
1049 * However, the NIC can gracefully prevent such situations
1050 * to happen by sending specific "back-pressure" flow control
1051 * frames to its peer(s).
1053 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1054 "ext_err_stat=0x%08x pkt_len=%u\n",
1055 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1056 (unsigned) rx_id, (unsigned) staterr,
1057 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1059 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1061 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1062 "queue_id=%u\n", (unsigned) rxq->port_id,
1063 (unsigned) rxq->queue_id);
1064 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1069 rxe = &sw_ring[rx_id];
1071 if (rx_id == rxq->nb_rx_desc)
1074 /* Prefetch next mbuf while processing current one. */
1075 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1078 * When next RX descriptor is on a cache-line boundary,
1079 * prefetch the next 4 RX descriptors and the next 8 pointers
1082 if ((rx_id & 0x3) == 0) {
1083 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1084 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1090 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1091 rxdp->read.hdr_addr = dma_addr;
1092 rxdp->read.pkt_addr = dma_addr;
1095 * Initialize the returned mbuf.
1096 * 1) setup generic mbuf fields:
1097 * - number of segments,
1100 * - RX port identifier.
1101 * 2) integrate hardware offload data, if any:
1102 * - RSS flag & hash,
1103 * - IP checksum flag,
1104 * - VLAN TCI, if any,
1107 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1109 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1110 rte_packet_prefetch(rxm->pkt.data);
1111 rxm->pkt.nb_segs = 1;
1112 rxm->pkt.next = NULL;
1113 rxm->pkt.pkt_len = pkt_len;
1114 rxm->pkt.data_len = pkt_len;
1115 rxm->pkt.in_port = rxq->port_id;
1117 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1118 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1119 rxm->pkt.vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1121 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1122 pkt_flags = (pkt_flags | rx_desc_status_to_pkt_flags(staterr));
1123 pkt_flags = (pkt_flags | rx_desc_error_to_pkt_flags(staterr));
1124 rxm->ol_flags = pkt_flags;
1126 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1127 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1128 else if (pkt_flags & PKT_RX_FDIR) {
1129 rxm->pkt.hash.fdir.hash =
1130 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1131 & IXGBE_ATR_HASH_MASK);
1132 rxm->pkt.hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1135 * Store the mbuf address into the next entry of the array
1136 * of returned packets.
1138 rx_pkts[nb_rx++] = rxm;
1140 rxq->rx_tail = rx_id;
1143 * If the number of free RX descriptors is greater than the RX free
1144 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1146 * Update the RDT with the value of the last processed RX descriptor
1147 * minus 1, to guarantee that the RDT register is never equal to the
1148 * RDH register, which creates a "full" ring situtation from the
1149 * hardware point of view...
1151 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1152 if (nb_hold > rxq->rx_free_thresh) {
1153 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1154 "nb_hold=%u nb_rx=%u\n",
1155 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1156 (unsigned) rx_id, (unsigned) nb_hold,
1158 rx_id = (uint16_t) ((rx_id == 0) ?
1159 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1160 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1163 rxq->nb_rx_hold = nb_hold;
1168 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1171 struct igb_rx_queue *rxq;
1172 volatile union ixgbe_adv_rx_desc *rx_ring;
1173 volatile union ixgbe_adv_rx_desc *rxdp;
1174 struct igb_rx_entry *sw_ring;
1175 struct igb_rx_entry *rxe;
1176 struct rte_mbuf *first_seg;
1177 struct rte_mbuf *last_seg;
1178 struct rte_mbuf *rxm;
1179 struct rte_mbuf *nmb;
1180 union ixgbe_adv_rx_desc rxd;
1181 uint64_t dma; /* Physical address of mbuf data buffer */
1183 uint32_t hlen_type_rss;
1193 rx_id = rxq->rx_tail;
1194 rx_ring = rxq->rx_ring;
1195 sw_ring = rxq->sw_ring;
1198 * Retrieve RX context of current packet, if any.
1200 first_seg = rxq->pkt_first_seg;
1201 last_seg = rxq->pkt_last_seg;
1203 while (nb_rx < nb_pkts) {
1206 * The order of operations here is important as the DD status
1207 * bit must not be read after any other descriptor fields.
1208 * rx_ring and rxdp are pointing to volatile data so the order
1209 * of accesses cannot be reordered by the compiler. If they were
1210 * not volatile, they could be reordered which could lead to
1211 * using invalid descriptor fields when read from rxd.
1213 rxdp = &rx_ring[rx_id];
1214 staterr = rxdp->wb.upper.status_error;
1215 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1222 * Allocate a new mbuf to replenish the RX ring descriptor.
1223 * If the allocation fails:
1224 * - arrange for that RX descriptor to be the first one
1225 * being parsed the next time the receive function is
1226 * invoked [on the same queue].
1228 * - Stop parsing the RX ring and return immediately.
1230 * This policy does not drop the packet received in the RX
1231 * descriptor for which the allocation of a new mbuf failed.
1232 * Thus, it allows that packet to be later retrieved if
1233 * mbuf have been freed in the mean time.
1234 * As a side effect, holding RX descriptors instead of
1235 * systematically giving them back to the NIC may lead to
1236 * RX ring exhaustion situations.
1237 * However, the NIC can gracefully prevent such situations
1238 * to happen by sending specific "back-pressure" flow control
1239 * frames to its peer(s).
1241 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
1242 "staterr=0x%x data_len=%u\n",
1243 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1244 (unsigned) rx_id, (unsigned) staterr,
1245 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1247 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1249 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1250 "queue_id=%u\n", (unsigned) rxq->port_id,
1251 (unsigned) rxq->queue_id);
1252 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1257 rxe = &sw_ring[rx_id];
1259 if (rx_id == rxq->nb_rx_desc)
1262 /* Prefetch next mbuf while processing current one. */
1263 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1266 * When next RX descriptor is on a cache-line boundary,
1267 * prefetch the next 4 RX descriptors and the next 8 pointers
1270 if ((rx_id & 0x3) == 0) {
1271 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1272 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1276 * Update RX descriptor with the physical address of the new
1277 * data buffer of the new allocated mbuf.
1281 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1282 rxdp->read.hdr_addr = dma;
1283 rxdp->read.pkt_addr = dma;
1286 * Set data length & data buffer address of mbuf.
1288 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1289 rxm->pkt.data_len = data_len;
1290 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1293 * If this is the first buffer of the received packet,
1294 * set the pointer to the first mbuf of the packet and
1295 * initialize its context.
1296 * Otherwise, update the total length and the number of segments
1297 * of the current scattered packet, and update the pointer to
1298 * the last mbuf of the current packet.
1300 if (first_seg == NULL) {
1302 first_seg->pkt.pkt_len = data_len;
1303 first_seg->pkt.nb_segs = 1;
1305 first_seg->pkt.pkt_len = (uint16_t)(first_seg->pkt.pkt_len
1307 first_seg->pkt.nb_segs++;
1308 last_seg->pkt.next = rxm;
1312 * If this is not the last buffer of the received packet,
1313 * update the pointer to the last mbuf of the current scattered
1314 * packet and continue to parse the RX ring.
1316 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1322 * This is the last buffer of the received packet.
1323 * If the CRC is not stripped by the hardware:
1324 * - Subtract the CRC length from the total packet length.
1325 * - If the last buffer only contains the whole CRC or a part
1326 * of it, free the mbuf associated to the last buffer.
1327 * If part of the CRC is also contained in the previous
1328 * mbuf, subtract the length of that CRC part from the
1329 * data length of the previous mbuf.
1331 rxm->pkt.next = NULL;
1332 if (unlikely(rxq->crc_len > 0)) {
1333 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
1334 if (data_len <= ETHER_CRC_LEN) {
1335 rte_pktmbuf_free_seg(rxm);
1336 first_seg->pkt.nb_segs--;
1337 last_seg->pkt.data_len = (uint16_t)
1338 (last_seg->pkt.data_len -
1339 (ETHER_CRC_LEN - data_len));
1340 last_seg->pkt.next = NULL;
1343 (uint16_t) (data_len - ETHER_CRC_LEN);
1347 * Initialize the first mbuf of the returned packet:
1348 * - RX port identifier,
1349 * - hardware offload data, if any:
1350 * - RSS flag & hash,
1351 * - IP checksum flag,
1352 * - VLAN TCI, if any,
1355 first_seg->pkt.in_port = rxq->port_id;
1358 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1359 * set in the pkt_flags field.
1361 first_seg->pkt.vlan_tci =
1362 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1363 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1364 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1365 pkt_flags = (pkt_flags |
1366 rx_desc_status_to_pkt_flags(staterr));
1367 pkt_flags = (pkt_flags |
1368 rx_desc_error_to_pkt_flags(staterr));
1369 first_seg->ol_flags = pkt_flags;
1371 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1372 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1373 else if (pkt_flags & PKT_RX_FDIR) {
1374 first_seg->pkt.hash.fdir.hash =
1375 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1376 & IXGBE_ATR_HASH_MASK);
1377 first_seg->pkt.hash.fdir.id =
1378 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1381 /* Prefetch data of first segment, if configured to do so. */
1382 rte_packet_prefetch(first_seg->pkt.data);
1385 * Store the mbuf address into the next entry of the array
1386 * of returned packets.
1388 rx_pkts[nb_rx++] = first_seg;
1391 * Setup receipt context for a new packet.
1397 * Record index of the next RX descriptor to probe.
1399 rxq->rx_tail = rx_id;
1402 * Save receive context.
1404 rxq->pkt_first_seg = first_seg;
1405 rxq->pkt_last_seg = last_seg;
1408 * If the number of free RX descriptors is greater than the RX free
1409 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1411 * Update the RDT with the value of the last processed RX descriptor
1412 * minus 1, to guarantee that the RDT register is never equal to the
1413 * RDH register, which creates a "full" ring situtation from the
1414 * hardware point of view...
1416 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1417 if (nb_hold > rxq->rx_free_thresh) {
1418 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1419 "nb_hold=%u nb_rx=%u\n",
1420 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1421 (unsigned) rx_id, (unsigned) nb_hold,
1423 rx_id = (uint16_t) ((rx_id == 0) ?
1424 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1425 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1428 rxq->nb_rx_hold = nb_hold;
1432 /*********************************************************************
1434 * Queue management functions
1436 **********************************************************************/
1439 * Rings setup and release.
1441 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1442 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1443 * also optimize cache line size effect. H/W supports up to cache line size 128.
1445 #define IXGBE_ALIGN 128
1448 * Maximum number of Ring Descriptors.
1450 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1451 * descriptors should meet the following condition:
1452 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1454 #define IXGBE_MIN_RING_DESC 64
1455 #define IXGBE_MAX_RING_DESC 4096
1458 * Create memzone for HW rings. malloc can't be used as the physical address is
1459 * needed. If the memzone is already created, then this function returns a ptr
1462 static const struct rte_memzone *
1463 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1464 uint16_t queue_id, uint32_t ring_size, int socket_id)
1466 char z_name[RTE_MEMZONE_NAMESIZE];
1467 const struct rte_memzone *mz;
1469 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1470 dev->driver->pci_drv.name, ring_name,
1471 dev->data->port_id, queue_id);
1473 mz = rte_memzone_lookup(z_name);
1477 return rte_memzone_reserve_aligned(z_name, (uint64_t) ring_size,
1478 socket_id, 0, IXGBE_ALIGN);
1482 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1486 if (txq->sw_ring != NULL) {
1487 for (i = 0; i < txq->nb_tx_desc; i++) {
1488 if (txq->sw_ring[i].mbuf != NULL) {
1489 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1490 txq->sw_ring[i].mbuf = NULL;
1497 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1500 ixgbe_tx_queue_release_mbufs(txq);
1501 rte_free(txq->sw_ring);
1507 ixgbe_dev_tx_queue_release(void *txq)
1509 ixgbe_tx_queue_release(txq);
1512 /* (Re)set dynamic igb_tx_queue fields to defaults */
1514 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1516 struct igb_tx_entry *txe = txq->sw_ring;
1519 /* Zero out HW ring memory */
1520 for (i = 0; i < sizeof(union ixgbe_adv_tx_desc) * txq->nb_tx_desc; i++) {
1521 ((volatile char *)txq->tx_ring)[i] = 0;
1524 /* Initialize SW ring entries */
1525 prev = (uint16_t) (txq->nb_tx_desc - 1);
1526 for (i = 0; i < txq->nb_tx_desc; i++) {
1527 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1528 txd->wb.status = IXGBE_TXD_STAT_DD;
1531 txe[prev].next_id = i;
1536 txq->nb_tx_used = 0;
1538 * Always allow 1 descriptor to be un-allocated to avoid
1539 * a H/W race condition
1541 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1542 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1544 memset((void*)&txq->ctx_cache, 0,
1545 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1549 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1552 unsigned int socket_id,
1553 const struct rte_eth_txconf *tx_conf)
1555 const struct rte_memzone *tz;
1556 struct igb_tx_queue *txq;
1557 struct ixgbe_hw *hw;
1558 uint16_t tx_rs_thresh, tx_free_thresh;
1560 PMD_INIT_FUNC_TRACE();
1561 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1564 * Validate number of transmit descriptors.
1565 * It must not exceed hardware maximum, and must be multiple
1568 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1569 (nb_desc > IXGBE_MAX_RING_DESC) ||
1570 (nb_desc < IXGBE_MIN_RING_DESC)) {
1575 * The following two parameters control the setting of the RS bit on
1576 * transmit descriptors.
1577 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1578 * descriptors have been used.
1579 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1580 * descriptors are used or if the number of descriptors required
1581 * to transmit a packet is greater than the number of free TX
1583 * The following constraints must be satisfied:
1584 * tx_rs_thresh must be greater than 0.
1585 * tx_rs_thresh must be less than the size of the ring minus 2.
1586 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1587 * tx_free_thresh must be greater than 0.
1588 * tx_free_thresh must be less than the size of the ring minus 3.
1589 * One descriptor in the TX ring is used as a sentinel to avoid a
1590 * H/W race condition, hence the maximum threshold constraints.
1591 * When set to zero use default values.
1593 tx_rs_thresh = (tx_conf->tx_rs_thresh) ?
1594 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH;
1595 tx_free_thresh = (tx_conf->tx_free_thresh) ?
1596 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH;
1597 if (tx_rs_thresh >= (nb_desc - 2)) {
1599 "tx_rs_thresh must be less than the "
1600 "number of TX descriptors minus 2. "
1601 "(tx_rs_thresh=%u port=%d queue=%d)",
1602 tx_rs_thresh, dev->data->port_id, queue_idx);
1605 if (tx_free_thresh >= (nb_desc - 3)) {
1607 "tx_rs_thresh must be less than the "
1608 "tx_free_thresh must be less than the "
1609 "number of TX descriptors minus 3. "
1610 "(tx_free_thresh=%u port=%d queue=%d)",
1611 tx_free_thresh, dev->data->port_id, queue_idx);
1614 if (tx_rs_thresh > tx_free_thresh) {
1616 "tx_rs_thresh must be less than or equal to "
1618 "(tx_free_thresh=%u tx_rs_thresh=%u "
1619 "port=%d queue=%d)",
1620 tx_free_thresh, tx_rs_thresh,
1621 dev->data->port_id, queue_idx);
1626 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1627 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1628 * by the NIC and all descriptors are written back after the NIC
1629 * accumulates WTHRESH descriptors.
1631 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1633 "TX WTHRESH should be set to 0 if "
1634 "tx_rs_thresh is greater than 1. "
1635 "TX WTHRESH will be set to 0. "
1636 "(tx_rs_thresh=%u port=%d queue=%d)",
1638 dev->data->port_id, queue_idx);
1642 /* Free memory prior to re-allocation if needed... */
1643 if (dev->data->tx_queues[queue_idx] != NULL)
1644 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1646 /* First allocate the tx queue data structure */
1647 txq = rte_zmalloc("ethdev TX queue", sizeof(struct igb_tx_queue),
1653 * Allocate TX ring hardware descriptors. A memzone large enough to
1654 * handle the maximum ring size is allocated in order to allow for
1655 * resizing in later calls to the queue setup function.
1657 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1658 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1661 ixgbe_tx_queue_release(txq);
1665 txq->nb_tx_desc = nb_desc;
1666 txq->tx_rs_thresh = tx_rs_thresh;
1667 txq->tx_free_thresh = tx_free_thresh;
1668 txq->pthresh = tx_conf->tx_thresh.pthresh;
1669 txq->hthresh = tx_conf->tx_thresh.hthresh;
1670 txq->wthresh = tx_conf->tx_thresh.wthresh;
1671 txq->queue_id = queue_idx;
1672 txq->port_id = dev->data->port_id;
1675 * Modification to set VFTDT for virtual function if vf is detected
1677 if (hw->mac.type == ixgbe_mac_82599_vf)
1678 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1680 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(queue_idx));
1682 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1683 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1685 /* Allocate software ring */
1686 txq->sw_ring = rte_zmalloc("txq->sw_ring",
1687 sizeof(struct igb_tx_entry) * nb_desc,
1689 if (txq->sw_ring == NULL) {
1690 ixgbe_tx_queue_release(txq);
1693 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1694 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1696 ixgbe_reset_tx_queue(txq);
1698 dev->data->tx_queues[queue_idx] = txq;
1700 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1706 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1710 if (rxq->sw_ring != NULL) {
1711 for (i = 0; i < rxq->nb_rx_desc; i++) {
1712 if (rxq->sw_ring[i].mbuf != NULL) {
1713 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1714 rxq->sw_ring[i].mbuf = NULL;
1717 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1718 if (rxq->rx_nb_avail) {
1719 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1720 struct rte_mbuf *mb;
1721 mb = rxq->rx_stage[rxq->rx_next_avail + i];
1722 rte_pktmbuf_free_seg(mb);
1724 rxq->rx_nb_avail = 0;
1731 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
1733 ixgbe_rx_queue_release_mbufs(rxq);
1734 rte_free(rxq->sw_ring);
1739 ixgbe_dev_rx_queue_release(void *rxq)
1741 ixgbe_rx_queue_release(rxq);
1745 * Check if Rx Burst Bulk Alloc function can be used.
1747 * 0: the preconditions are satisfied and the bulk allocation function
1749 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
1750 * function must be used.
1753 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
1758 * Make sure the following pre-conditions are satisfied:
1759 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
1760 * rxq->rx_free_thresh < rxq->nb_rx_desc
1761 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
1762 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
1763 * Scattered packets are not supported. This should be checked
1764 * outside of this function.
1766 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1767 if (! (rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST))
1769 else if (! (rxq->rx_free_thresh < rxq->nb_rx_desc))
1771 else if (! ((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0))
1773 else if (! (rxq->nb_rx_desc <
1774 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)))
1783 /* (Re)set dynamic igb_rx_queue fields to defaults */
1785 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
1790 * By default, the Rx queue setup function allocates enough memory for
1791 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
1792 * extra memory at the end of the descriptor ring to be zero'd out. A
1793 * pre-condition for using the Rx burst bulk alloc function is that the
1794 * number of descriptors is less than or equal to
1795 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
1796 * constraints here to see if we need to zero out memory after the end
1797 * of the H/W descriptor ring.
1799 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1800 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
1801 /* zero out extra memory */
1802 len = rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST;
1805 /* do not zero out extra memory */
1806 len = rxq->nb_rx_desc;
1809 * Zero out HW ring memory. Zero out extra memory at the end of
1810 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
1811 * reads extra memory as zeros.
1813 for (i = 0; i < len * sizeof(union ixgbe_adv_rx_desc); i++) {
1814 ((volatile char *)rxq->rx_ring)[i] = 0;
1817 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1819 * initialize extra software ring entries. Space for these extra
1820 * entries is always allocated
1822 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
1823 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
1824 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
1827 rxq->rx_nb_avail = 0;
1828 rxq->rx_next_avail = 0;
1829 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1830 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1832 rxq->nb_rx_hold = 0;
1833 rxq->pkt_first_seg = NULL;
1834 rxq->pkt_last_seg = NULL;
1838 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
1841 unsigned int socket_id,
1842 const struct rte_eth_rxconf *rx_conf,
1843 struct rte_mempool *mp)
1845 const struct rte_memzone *rz;
1846 struct igb_rx_queue *rxq;
1847 struct ixgbe_hw *hw;
1849 PMD_INIT_FUNC_TRACE();
1850 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853 * Validate number of receive descriptors.
1854 * It must not exceed hardware maximum, and must be multiple
1857 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
1858 (nb_desc > IXGBE_MAX_RING_DESC) ||
1859 (nb_desc < IXGBE_MIN_RING_DESC)) {
1863 /* Free memory prior to re-allocation if needed... */
1864 if (dev->data->rx_queues[queue_idx] != NULL)
1865 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
1867 /* First allocate the rx queue data structure */
1868 rxq = rte_zmalloc("ethdev RX queue", sizeof(struct igb_rx_queue),
1873 rxq->nb_rx_desc = nb_desc;
1874 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1875 rxq->queue_id = queue_idx;
1876 rxq->port_id = dev->data->port_id;
1877 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
1881 * Allocate TX ring hardware descriptors. A memzone large enough to
1882 * handle the maximum ring size is allocated in order to allow for
1883 * resizing in later calls to the queue setup function.
1885 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
1886 IXGBE_MAX_RING_DESC * sizeof(union ixgbe_adv_rx_desc),
1889 ixgbe_rx_queue_release(rxq);
1893 * Modified to setup VFRDT for Virtual Function
1895 if (hw->mac.type == ixgbe_mac_82599_vf)
1896 rxq->rdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
1898 rxq->rdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(queue_idx));
1900 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
1901 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
1904 * Allocate software ring. Allow for space at the end of the
1905 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
1906 * function does not access an invalid memory region.
1908 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1909 len = nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST;
1913 rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1914 sizeof(struct igb_rx_entry) * nb_desc,
1916 if (rxq->sw_ring == NULL) {
1917 ixgbe_rx_queue_release(rxq);
1920 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1921 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1924 * Certain constaints must be met in order to use the bulk buffer
1925 * allocation Rx burst function.
1927 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1929 /* Check if pre-conditions are satisfied, and no Scattered Rx */
1930 if (!use_def_burst_func && !dev->data->scattered_rx) {
1931 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1932 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1933 "satisfied. Rx Burst Bulk Alloc function will be "
1934 "used on port=%d, queue=%d.\n",
1935 rxq->port_id, rxq->queue_id);
1936 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
1939 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
1940 "are not satisfied, Scattered Rx is requested, "
1941 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
1942 "enabled (port=%d, queue=%d).\n",
1943 rxq->port_id, rxq->queue_id);
1945 dev->data->rx_queues[queue_idx] = rxq;
1947 ixgbe_reset_rx_queue(rxq);
1953 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
1958 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1959 struct igb_tx_queue *txq = dev->data->tx_queues[i];
1960 ixgbe_tx_queue_release_mbufs(txq);
1961 ixgbe_reset_tx_queue(txq);
1964 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1965 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
1966 ixgbe_rx_queue_release_mbufs(rxq);
1967 ixgbe_reset_rx_queue(rxq);
1971 /*********************************************************************
1973 * Device RX/TX init functions
1975 **********************************************************************/
1978 * Receive Side Scaling (RSS)
1979 * See section 7.1.2.8 in the following document:
1980 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
1983 * The source and destination IP addresses of the IP header and the source
1984 * and destination ports of TCP/UDP headers, if any, of received packets are
1985 * hashed against a configurable random key to compute a 32-bit RSS hash result.
1986 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
1987 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
1988 * RSS output index which is used as the RX queue index where to store the
1990 * The following output is supplied in the RX write-back descriptor:
1991 * - 32-bit result of the Microsoft RSS hash function,
1992 * - 4-bit RSS type field.
1996 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
1997 * Used as the default key.
1999 static uint8_t rss_intel_key[40] = {
2000 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2001 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2002 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2003 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2004 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2008 ixgbe_rss_disable(struct rte_eth_dev *dev)
2010 struct ixgbe_hw *hw;
2013 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2014 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2015 mrqc &= ~IXGBE_MRQC_RSSEN;
2016 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2020 ixgbe_rss_configure(struct rte_eth_dev *dev)
2022 struct ixgbe_hw *hw;
2031 PMD_INIT_FUNC_TRACE();
2032 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2034 rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
2035 if (rss_hf == 0) { /* Disable RSS */
2036 ixgbe_rss_disable(dev);
2039 hash_key = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
2040 if (hash_key == NULL)
2041 hash_key = rss_intel_key; /* Default hash key */
2043 /* Fill in RSS hash key */
2044 for (i = 0; i < 10; i++) {
2045 rss_key = hash_key[(i * 4)];
2046 rss_key |= hash_key[(i * 4) + 1] << 8;
2047 rss_key |= hash_key[(i * 4) + 2] << 16;
2048 rss_key |= hash_key[(i * 4) + 3] << 24;
2049 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2052 /* Fill in redirection table */
2054 for (i = 0, j = 0; i < 128; i++, j++) {
2055 if (j == dev->data->nb_rx_queues) j = 0;
2056 reta = (reta << 8) | j;
2058 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), rte_bswap32(reta));
2061 /* Set configured hashing functions in MRQC register */
2062 mrqc = IXGBE_MRQC_RSSEN; /* RSS enable */
2063 if (rss_hf & ETH_RSS_IPV4)
2064 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2065 if (rss_hf & ETH_RSS_IPV4_TCP)
2066 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2067 if (rss_hf & ETH_RSS_IPV6)
2068 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2069 if (rss_hf & ETH_RSS_IPV6_EX)
2070 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2071 if (rss_hf & ETH_RSS_IPV6_TCP)
2072 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2073 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2074 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2075 if (rss_hf & ETH_RSS_IPV4_UDP)
2076 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2077 if (rss_hf & ETH_RSS_IPV6_UDP)
2078 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2079 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2080 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2081 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2084 #define NUM_VFTA_REGISTERS 128
2085 #define NIC_RX_BUFFER_SIZE 0x200
2088 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2090 struct rte_eth_vmdq_dcb_conf *cfg;
2091 struct ixgbe_hw *hw;
2092 enum rte_eth_nb_pools num_pools;
2093 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2095 uint8_t nb_tcs; /* number of traffic classes */
2098 PMD_INIT_FUNC_TRACE();
2099 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2101 num_pools = cfg->nb_queue_pools;
2102 /* Check we have a valid number of pools */
2103 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2104 ixgbe_rss_disable(dev);
2107 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2108 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2112 * split rx buffer up into sections, each for 1 traffic class
2114 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2115 for (i = 0 ; i < nb_tcs; i++) {
2116 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2117 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2118 /* clear 10 bits. */
2119 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2120 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2122 /* zero alloc all unused TCs */
2123 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2124 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2125 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2126 /* clear 10 bits. */
2127 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2130 /* MRQC: enable vmdq and dcb */
2131 mrqc = ((num_pools == ETH_16_POOLS) ? \
2132 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2133 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2135 /* PFVTCTL: turn on virtualisation and set the default pool */
2136 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2137 if (cfg->enable_default_pool) {
2138 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2140 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2142 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2144 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2146 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2148 * mapping is done with 3 bits per priority,
2149 * so shift by i*3 each time
2151 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2153 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2155 /* RTRPCS: DCB related */
2156 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2158 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2159 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2160 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2161 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2163 /* VFTA - enable all vlan filters */
2164 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2165 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2168 /* VFRE: pool enabling for receive - 16 or 32 */
2169 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2170 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2173 * MPSAR - allow pools to read specific mac addresses
2174 * In this case, all pools should be able to read from mac addr 0
2176 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2177 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2179 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2180 for (i = 0; i < cfg->nb_pool_maps; i++) {
2181 /* set vlan id in VF register and set the valid bit */
2182 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2183 (cfg->pool_map[i].vlan_id & 0xFFF)));
2185 * Put the allowed pools in VFB reg. As we only have 16 or 32
2186 * pools, we only need to use the first half of the register
2189 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2194 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2195 * @hw: pointer to hardware structure
2196 * @dcb_config: pointer to ixgbe_dcb_config structure
2199 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2200 struct ixgbe_dcb_config *dcb_config)
2205 PMD_INIT_FUNC_TRACE();
2206 if (hw->mac.type != ixgbe_mac_82598EB) {
2207 /* Disable the Tx desc arbiter so that MTQC can be changed */
2208 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2209 reg |= IXGBE_RTTDCS_ARBDIS;
2210 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2212 /* Enable DCB for Tx with 8 TCs */
2213 if (dcb_config->num_tcs.pg_tcs == 8) {
2214 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2217 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2219 if (dcb_config->vt_mode)
2220 reg |= IXGBE_MTQC_VT_ENA;
2221 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2223 /* Disable drop for all queues */
2224 for (q = 0; q < 128; q++)
2225 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2226 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2228 /* Enable the Tx desc arbiter */
2229 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2230 reg &= ~IXGBE_RTTDCS_ARBDIS;
2231 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2233 /* Enable Security TX Buffer IFG for DCB */
2234 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2235 reg |= IXGBE_SECTX_DCB;
2236 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2242 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2243 * @dev: pointer to rte_eth_dev structure
2244 * @dcb_config: pointer to ixgbe_dcb_config structure
2247 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2248 struct ixgbe_dcb_config *dcb_config)
2250 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2251 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2252 struct ixgbe_hw *hw =
2253 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2255 PMD_INIT_FUNC_TRACE();
2256 if (hw->mac.type != ixgbe_mac_82598EB)
2257 /*PF VF Transmit Enable*/
2258 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2259 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2261 /*Configure general DCB TX parameters*/
2262 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2267 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2268 struct ixgbe_dcb_config *dcb_config)
2270 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2271 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2272 struct ixgbe_dcb_tc_config *tc;
2275 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2276 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2277 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2278 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2281 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2282 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2284 /* User Priority to Traffic Class mapping */
2285 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2286 j = vmdq_rx_conf->dcb_queue[i];
2287 tc = &dcb_config->tc_config[j];
2288 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = (1 << j);
2293 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2294 struct ixgbe_dcb_config *dcb_config)
2296 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2297 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2298 struct ixgbe_dcb_tc_config *tc;
2301 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2302 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2303 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2304 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2307 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2308 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2311 /* User Priority to Traffic Class mapping */
2312 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2313 j = vmdq_tx_conf->dcb_queue[i];
2314 tc = &dcb_config->tc_config[j];
2315 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = (1 << j);
2321 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,struct ixgbe_dcb_config *dcb_config)
2323 struct rte_eth_dcb_rx_conf *rx_conf =
2324 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2325 struct ixgbe_dcb_tc_config *tc;
2328 dcb_config->num_tcs.pg_tcs = rx_conf->nb_tcs;
2329 dcb_config->num_tcs.pfc_tcs = rx_conf->nb_tcs;
2331 /* User Priority to Traffic Class mapping */
2332 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2333 j = rx_conf->dcb_queue[i];
2334 tc = &dcb_config->tc_config[j];
2335 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = (1 << j);
2340 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,struct ixgbe_dcb_config *dcb_config)
2342 struct rte_eth_dcb_tx_conf *tx_conf =
2343 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2344 struct ixgbe_dcb_tc_config *tc;
2347 dcb_config->num_tcs.pg_tcs = tx_conf->nb_tcs;
2348 dcb_config->num_tcs.pfc_tcs = tx_conf->nb_tcs;
2350 /* User Priority to Traffic Class mapping */
2351 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2352 j = tx_conf->dcb_queue[i];
2353 tc = &dcb_config->tc_config[j];
2354 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = (1 << j);
2359 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2360 * @hw: pointer to hardware structure
2361 * @dcb_config: pointer to ixgbe_dcb_config structure
2364 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2365 struct ixgbe_dcb_config *dcb_config)
2371 PMD_INIT_FUNC_TRACE();
2373 * Disable the arbiter before changing parameters
2374 * (always enable recycle mode; WSP)
2376 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2377 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2379 if (hw->mac.type != ixgbe_mac_82598EB) {
2380 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2381 if (dcb_config->num_tcs.pg_tcs == 4) {
2382 if (dcb_config->vt_mode)
2383 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2384 IXGBE_MRQC_VMDQRT4TCEN;
2386 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2387 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2391 if (dcb_config->num_tcs.pg_tcs == 8) {
2392 if (dcb_config->vt_mode)
2393 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2394 IXGBE_MRQC_VMDQRT8TCEN;
2396 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2397 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2402 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2405 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2406 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2407 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2408 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2410 /* VFTA - enable all vlan filters */
2411 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2412 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2416 * Configure Rx packet plane (recycle mode; WSP) and
2419 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2420 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2426 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2427 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2429 switch (hw->mac.type) {
2430 case ixgbe_mac_82598EB:
2431 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2433 case ixgbe_mac_82599EB:
2434 case ixgbe_mac_X540:
2435 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2444 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2445 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2447 switch (hw->mac.type) {
2448 case ixgbe_mac_82598EB:
2449 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2450 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2452 case ixgbe_mac_82599EB:
2453 case ixgbe_mac_X540:
2454 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2455 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2462 #define DCB_RX_CONFIG 1
2463 #define DCB_TX_CONFIG 1
2464 #define DCB_TX_PB 1024
2466 * ixgbe_dcb_hw_configure - Enable DCB and configure
2467 * general DCB in VT mode and non-VT mode parameters
2468 * @dev: pointer to rte_eth_dev structure
2469 * @dcb_config: pointer to ixgbe_dcb_config structure
2472 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2473 struct ixgbe_dcb_config *dcb_config)
2476 uint8_t i,pfc_en,nb_tcs;
2478 uint8_t config_dcb_rx = 0;
2479 uint8_t config_dcb_tx = 0;
2480 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2481 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2482 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2483 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2484 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2485 struct ixgbe_dcb_tc_config *tc;
2486 uint32_t max_frame = dev->data->max_frame_size;
2487 struct ixgbe_hw *hw =
2488 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490 switch(dev->data->dev_conf.rxmode.mq_mode){
2492 dcb_config->vt_mode = true;
2493 if (hw->mac.type != ixgbe_mac_82598EB) {
2494 config_dcb_rx = DCB_RX_CONFIG;
2496 *get dcb and VT rx configuration parameters
2499 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2500 /*Configure general VMDQ and DCB RX parameters*/
2501 ixgbe_vmdq_dcb_configure(dev);
2505 dcb_config->vt_mode = false;
2506 config_dcb_rx = DCB_RX_CONFIG;
2507 /* Get dcb TX configuration parameters from rte_eth_conf */
2508 ixgbe_dcb_rx_config(dev,dcb_config);
2509 /*Configure general DCB RX parameters*/
2510 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2513 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration\n");
2516 switch (dev->data->dev_conf.txmode.mq_mode) {
2517 case ETH_VMDQ_DCB_TX:
2518 dcb_config->vt_mode = true;
2519 config_dcb_tx = DCB_TX_CONFIG;
2520 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2521 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2522 /*Configure general VMDQ and DCB TX parameters*/
2523 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2527 dcb_config->vt_mode = false;
2528 config_dcb_tx = DCB_RX_CONFIG;
2529 /*get DCB TX configuration parameters from rte_eth_conf*/
2530 ixgbe_dcb_tx_config(dev,dcb_config);
2531 /*Configure general DCB TX parameters*/
2532 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2535 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration\n");
2539 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2541 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2542 if(nb_tcs == ETH_4_TCS) {
2543 /* Avoid un-configured priority mapping to TC0 */
2545 uint8_t mask = 0xFF;
2546 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2547 mask &= ~ (1 << map[i]);
2548 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2549 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2553 /* Re-configure 4 TCs BW */
2554 for (i = 0; i < nb_tcs; i++) {
2555 tc = &dcb_config->tc_config[i];
2556 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 100 / nb_tcs;
2557 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 100 / nb_tcs;
2559 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2560 tc = &dcb_config->tc_config[i];
2561 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
2562 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
2567 /* Set RX buffer size */
2568 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2569 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
2570 for (i = 0 ; i < nb_tcs; i++) {
2571 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2573 /* zero alloc all unused TCs */
2574 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2575 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
2579 /* Only support an equally distributed Tx packet buffer strategy. */
2580 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
2581 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
2582 for (i = 0; i < nb_tcs; i++) {
2583 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
2584 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
2586 /* Clear unused TCs, if any, to zero buffer size*/
2587 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2588 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
2589 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
2593 /*Calculates traffic class credits*/
2594 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2595 IXGBE_DCB_TX_CONFIG);
2596 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2597 IXGBE_DCB_RX_CONFIG);
2600 /* Unpack CEE standard containers */
2601 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
2602 ixgbe_dcb_unpack_max_cee(dcb_config, max);
2603 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
2604 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
2605 /* Configure PG(ETS) RX */
2606 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
2610 /* Unpack CEE standard containers */
2611 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
2612 ixgbe_dcb_unpack_max_cee(dcb_config, max);
2613 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
2614 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
2615 /* Configure PG(ETS) TX */
2616 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
2619 /*Configure queue statistics registers*/
2620 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
2622 /* Check if the PFC is supported */
2623 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
2624 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
2625 for (i = 0; i < nb_tcs; i++) {
2627 * If the TC count is 8,and the default high_water is 48,
2628 * the low_water is 16 as default.
2630 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
2631 hw->fc.low_water[i] = pbsize / 4;
2632 /* Enable pfc for this TC */
2633 tc = &dcb_config->tc_config[i];
2634 tc->pfc = ixgbe_dcb_pfc_enabled;
2636 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
2637 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
2639 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
2646 * ixgbe_configure_dcb - Configure DCB Hardware
2647 * @dev: pointer to rte_eth_dev
2649 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
2651 struct ixgbe_dcb_config *dcb_cfg =
2652 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2654 PMD_INIT_FUNC_TRACE();
2655 /** Configure DCB hardware **/
2656 if(((dev->data->dev_conf.rxmode.mq_mode != ETH_RSS) &&
2657 (dev->data->nb_rx_queues == ETH_DCB_NUM_QUEUES))||
2658 ((dev->data->dev_conf.txmode.mq_mode != ETH_DCB_NONE) &&
2659 (dev->data->nb_tx_queues == ETH_DCB_NUM_QUEUES))) {
2660 ixgbe_dcb_hw_configure(dev,dcb_cfg);
2666 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
2668 struct igb_rx_entry *rxe = rxq->sw_ring;
2672 /* Initialize software ring entries */
2673 for (i = 0; i < rxq->nb_rx_desc; i++) {
2674 volatile union ixgbe_adv_rx_desc *rxd;
2675 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
2677 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u\n",
2678 (unsigned) rxq->queue_id);
2682 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2683 rxd = &rxq->rx_ring[i];
2684 rxd->read.hdr_addr = dma_addr;
2685 rxd->read.pkt_addr = dma_addr;
2693 * Initializes Receive Unit.
2696 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
2698 struct ixgbe_hw *hw;
2699 struct igb_rx_queue *rxq;
2700 struct rte_pktmbuf_pool_private *mbp_priv;
2713 PMD_INIT_FUNC_TRACE();
2714 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2717 * Make sure receives are disabled while setting
2718 * up the RX context (registers, descriptor rings, etc.).
2720 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2721 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2723 /* Enable receipt of broadcasted frames */
2724 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2725 fctrl |= IXGBE_FCTRL_BAM;
2726 fctrl |= IXGBE_FCTRL_DPF;
2727 fctrl |= IXGBE_FCTRL_PMCF;
2728 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2731 * Configure CRC stripping, if any.
2733 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2734 if (dev->data->dev_conf.rxmode.hw_strip_crc)
2735 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
2737 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
2740 * Configure jumbo frame support, if any.
2742 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
2743 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2744 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2745 maxfrs &= 0x0000FFFF;
2746 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2747 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2749 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2751 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2753 /* Setup RX queues */
2754 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2755 rxq = dev->data->rx_queues[i];
2757 /* Allocate buffers for descriptor rings */
2758 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
2763 * Reset crc_len in case it was changed after queue setup by a
2764 * call to configure.
2766 rxq->crc_len = (uint8_t)
2767 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
2770 /* Setup the Base and Length of the Rx Descriptor Rings */
2771 bus_addr = rxq->rx_ring_phys_addr;
2772 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(i),
2773 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
2774 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(i),
2775 (uint32_t)(bus_addr >> 32));
2776 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(i),
2777 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
2778 IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
2779 IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
2781 /* Configure the SRRCTL register */
2782 #ifdef RTE_HEADER_SPLIT_ENABLE
2784 * Configure Header Split
2786 if (dev->data->dev_conf.rxmode.header_split) {
2787 if (hw->mac.type == ixgbe_mac_82599EB) {
2788 /* Must setup the PSRTYPE register */
2790 psrtype = IXGBE_PSRTYPE_TCPHDR |
2791 IXGBE_PSRTYPE_UDPHDR |
2792 IXGBE_PSRTYPE_IPV4HDR |
2793 IXGBE_PSRTYPE_IPV6HDR;
2794 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(i), psrtype);
2796 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
2797 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2798 IXGBE_SRRCTL_BSIZEHDR_MASK);
2799 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2802 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2805 * Configure the RX buffer size in the BSIZEPACKET field of
2806 * the SRRCTL register of the queue.
2807 * The value is in 1 KB resolution. Valid values can be from
2810 mbp_priv = (struct rte_pktmbuf_pool_private *)
2811 ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
2812 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
2813 RTE_PKTMBUF_HEADROOM);
2814 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
2815 IXGBE_SRRCTL_BSIZEPKT_MASK);
2816 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(i), srrctl);
2818 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
2819 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
2820 if (dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size){
2821 dev->data->scattered_rx = 1;
2822 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
2827 * Configure RSS if device configured with multiple RX queues.
2829 if (hw->mac.type == ixgbe_mac_82599EB) {
2830 if (dev->data->nb_rx_queues > 1)
2831 switch (dev->data->dev_conf.rxmode.mq_mode) {
2833 ixgbe_rss_configure(dev);
2837 ixgbe_vmdq_dcb_configure(dev);
2840 default: ixgbe_rss_disable(dev);
2843 ixgbe_rss_disable(dev);
2847 * Setup the Checksum Register.
2848 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
2849 * Enable IP/L4 checkum computation by hardware if requested to do so.
2851 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2852 rxcsum |= IXGBE_RXCSUM_PCSD;
2853 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
2854 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2856 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
2858 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2860 if (hw->mac.type == ixgbe_mac_82599EB) {
2861 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2862 if (dev->data->dev_conf.rxmode.hw_strip_crc)
2863 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2865 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
2866 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2867 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2874 * Initializes Transmit Unit.
2877 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
2879 struct ixgbe_hw *hw;
2880 struct igb_tx_queue *txq;
2887 PMD_INIT_FUNC_TRACE();
2888 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890 /* Enable TX CRC (checksum offload requirement) */
2891 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2892 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
2893 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2895 /* Setup the Base and Length of the Tx Descriptor Rings */
2896 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2897 txq = dev->data->tx_queues[i];
2899 bus_addr = txq->tx_ring_phys_addr;
2900 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(i),
2901 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
2902 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(i),
2903 (uint32_t)(bus_addr >> 32));
2904 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(i),
2905 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
2906 /* Setup the HW Tx Head and TX Tail descriptor pointers */
2907 IXGBE_WRITE_REG(hw, IXGBE_TDH(i), 0);
2908 IXGBE_WRITE_REG(hw, IXGBE_TDT(i), 0);
2911 * Disable Tx Head Writeback RO bit, since this hoses
2912 * bookkeeping if things aren't delivered in order.
2914 switch (hw->mac.type) {
2915 case ixgbe_mac_82598EB:
2916 txctrl = IXGBE_READ_REG(hw,
2917 IXGBE_DCA_TXCTRL(i));
2918 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2919 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i),
2923 case ixgbe_mac_82599EB:
2924 case ixgbe_mac_X540:
2926 txctrl = IXGBE_READ_REG(hw,
2927 IXGBE_DCA_TXCTRL_82599(i));
2928 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2929 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i),
2935 if (hw->mac.type != ixgbe_mac_82598EB) {
2936 /* disable arbiter before setting MTQC */
2937 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2938 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2939 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2941 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2943 /* re-enable arbiter */
2944 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2945 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2950 * Start Transmit and Receive Units.
2953 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
2955 struct ixgbe_hw *hw;
2956 struct igb_tx_queue *txq;
2957 struct igb_rx_queue *rxq;
2965 PMD_INIT_FUNC_TRACE();
2966 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2968 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2969 txq = dev->data->tx_queues[i];
2970 /* Setup Transmit Threshold Registers */
2971 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
2972 txdctl |= txq->pthresh & 0x7F;
2973 txdctl |= ((txq->hthresh & 0x7F) << 8);
2974 txdctl |= ((txq->wthresh & 0x7F) << 16);
2975 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), txdctl);
2978 if (hw->mac.type != ixgbe_mac_82598EB) {
2979 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2980 dmatxctl |= IXGBE_DMATXCTL_TE;
2981 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2984 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2985 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
2986 txdctl |= IXGBE_TXDCTL_ENABLE;
2987 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), txdctl);
2989 /* Wait until TX Enable ready */
2990 if (hw->mac.type == ixgbe_mac_82599EB) {
2994 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
2995 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
2997 PMD_INIT_LOG(ERR, "Could not enable "
2998 "Tx Queue %d\n", i);
3001 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3002 rxq = dev->data->rx_queues[i];
3003 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
3004 rxdctl |= IXGBE_RXDCTL_ENABLE;
3005 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), rxdctl);
3007 /* Wait until RX Enable ready */
3011 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
3012 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3014 PMD_INIT_LOG(ERR, "Could not enable "
3015 "Rx Queue %d\n", i);
3017 IXGBE_WRITE_REG(hw, IXGBE_RDT(i), rxq->nb_rx_desc - 1);
3020 /* Enable Receive engine */
3021 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3022 if (hw->mac.type == ixgbe_mac_82598EB)
3023 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3024 rxctrl |= IXGBE_RXCTRL_RXEN;
3025 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3030 * [VF] Initializes Receive Unit.
3033 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3035 struct ixgbe_hw *hw;
3036 struct igb_rx_queue *rxq;
3037 struct rte_pktmbuf_pool_private *mbp_priv;
3044 PMD_INIT_FUNC_TRACE();
3045 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3047 /* Setup RX queues */
3048 dev->rx_pkt_burst = ixgbe_recv_pkts;
3049 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3050 rxq = dev->data->rx_queues[i];
3052 /* Allocate buffers for descriptor rings */
3053 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3057 /* Setup the Base and Length of the Rx Descriptor Rings */
3058 bus_addr = rxq->rx_ring_phys_addr;
3060 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3061 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3062 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3063 (uint32_t)(bus_addr >> 32));
3064 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3065 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3066 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3067 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3070 /* Configure the SRRCTL register */
3071 #ifdef RTE_HEADER_SPLIT_ENABLE
3073 * Configure Header Split
3075 if (dev->data->dev_conf.rxmode.header_split) {
3077 /* Must setup the PSRTYPE register */
3079 psrtype = IXGBE_PSRTYPE_TCPHDR |
3080 IXGBE_PSRTYPE_UDPHDR |
3081 IXGBE_PSRTYPE_IPV4HDR |
3082 IXGBE_PSRTYPE_IPV6HDR;
3084 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3086 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3087 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3088 IXGBE_SRRCTL_BSIZEHDR_MASK);
3089 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3092 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3095 * Configure the RX buffer size in the BSIZEPACKET field of
3096 * the SRRCTL register of the queue.
3097 * The value is in 1 KB resolution. Valid values can be from
3100 mbp_priv = (struct rte_pktmbuf_pool_private *)
3101 ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
3102 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3103 RTE_PKTMBUF_HEADROOM);
3104 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3105 IXGBE_SRRCTL_BSIZEPKT_MASK);
3108 * VF modification to write virtual function SRRCTL register
3110 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
3112 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3113 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3114 if (dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size){
3115 dev->data->scattered_rx = 1;
3116 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3123 * [VF] Initializes Transmit Unit.
3126 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
3128 struct ixgbe_hw *hw;
3129 struct igb_tx_queue *txq;
3134 PMD_INIT_FUNC_TRACE();
3135 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3137 /* Setup the Base and Length of the Tx Descriptor Rings */
3138 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3139 txq = dev->data->tx_queues[i];
3140 bus_addr = txq->tx_ring_phys_addr;
3141 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
3142 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3143 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
3144 (uint32_t)(bus_addr >> 32));
3145 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
3146 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3147 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3148 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
3149 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
3152 * Disable Tx Head Writeback RO bit, since this hoses
3153 * bookkeeping if things aren't delivered in order.
3155 txctrl = IXGBE_READ_REG(hw,
3156 IXGBE_VFDCA_TXCTRL(i));
3157 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
3158 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
3164 * [VF] Start Transmit and Receive Units.
3167 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
3169 struct ixgbe_hw *hw;
3170 struct igb_tx_queue *txq;
3171 struct igb_rx_queue *rxq;
3177 PMD_INIT_FUNC_TRACE();
3178 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3180 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3181 txq = dev->data->tx_queues[i];
3182 /* Setup Transmit Threshold Registers */
3183 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3184 txdctl |= txq->pthresh & 0x7F;
3185 txdctl |= ((txq->hthresh & 0x7F) << 8);
3186 txdctl |= ((txq->wthresh & 0x7F) << 16);
3187 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3190 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3192 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3193 txdctl |= IXGBE_TXDCTL_ENABLE;
3194 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3197 /* Wait until TX Enable ready */
3200 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3201 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3203 PMD_INIT_LOG(ERR, "Could not enable "
3204 "Tx Queue %d\n", i);
3206 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3208 rxq = dev->data->rx_queues[i];
3210 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3211 rxdctl |= IXGBE_RXDCTL_ENABLE;
3212 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
3214 /* Wait until RX Enable ready */
3218 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3219 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3221 PMD_INIT_LOG(ERR, "Could not enable "
3222 "Rx Queue %d\n", i);
3224 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);