4 * Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
47 #include <rte_byteorder.h>
48 #include <rte_common.h>
49 #include <rte_cycles.h>
51 #include <rte_debug.h>
52 #include <rte_interrupts.h>
54 #include <rte_memory.h>
55 #include <rte_memzone.h>
56 #include <rte_launch.h>
57 #include <rte_tailq.h>
59 #include <rte_per_lcore.h>
60 #include <rte_lcore.h>
61 #include <rte_atomic.h>
62 #include <rte_branch_prediction.h>
64 #include <rte_mempool.h>
65 #include <rte_malloc.h>
67 #include <rte_ether.h>
68 #include <rte_ethdev.h>
69 #include <rte_prefetch.h>
73 #include <rte_string_fns.h>
74 #include <rte_errno.h>
76 #include "ixgbe_logs.h"
77 #include "ixgbe/ixgbe_api.h"
78 #include "ixgbe/ixgbe_vf.h"
79 #include "ixgbe_ethdev.h"
80 #include "ixgbe/ixgbe_dcb.h"
83 #define RTE_PMD_IXGBE_TX_MAX_BURST 32
85 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
86 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
89 static inline struct rte_mbuf *
90 rte_rxmbuf_alloc(struct rte_mempool *mp)
94 m = __rte_mbuf_raw_alloc(mp);
95 __rte_mbuf_sanity_check_raw(m, RTE_MBUF_PKT, 0);
99 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
100 (uint64_t) ((mb)->buf_physaddr + (uint64_t)((char *)((mb)->pkt.data) - \
101 (char *)(mb)->buf_addr))
103 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
104 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
107 * Structure associated with each descriptor of the RX ring of a RX queue.
109 struct igb_rx_entry {
110 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
114 * Structure associated with each descriptor of the TX ring of a TX queue.
116 struct igb_tx_entry {
117 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
118 uint16_t next_id; /**< Index of next descriptor in ring. */
119 uint16_t last_id; /**< Index of last scattered descriptor. */
123 * Structure associated with each RX queue.
125 struct igb_rx_queue {
126 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
127 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
128 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
129 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
130 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
131 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
132 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
133 uint16_t nb_rx_desc; /**< number of RX descriptors. */
134 uint16_t rx_tail; /**< current value of RDT register. */
135 uint16_t nb_rx_hold; /**< number of held free RX desc. */
136 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
137 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
138 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
139 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
141 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
142 uint16_t queue_id; /**< RX queue index. */
143 uint8_t port_id; /**< Device port identifier. */
144 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
145 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
146 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
147 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
148 struct rte_mbuf fake_mbuf;
149 /** hold packets to return to application */
150 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
155 * IXGBE CTX Constants
157 enum ixgbe_advctx_num {
158 IXGBE_CTX_0 = 0, /**< CTX0 */
159 IXGBE_CTX_1 = 1, /**< CTX1 */
160 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
164 * Structure to check if new context need be built
166 struct ixgbe_advctx_info {
167 uint16_t flags; /**< ol_flags for context build. */
168 uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
169 uint32_t vlan_macip_lens; /**< vlan, mac ip length. */
173 * Structure associated with each TX queue.
175 struct igb_tx_queue {
176 /** TX ring virtual address. */
177 volatile union ixgbe_adv_tx_desc *tx_ring;
178 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
179 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
180 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
181 uint16_t nb_tx_desc; /**< number of TX descriptors. */
182 uint16_t tx_tail; /**< current value of TDT reg. */
183 uint16_t tx_free_thresh;/**< minimum TX before freeing. */
184 /** Number of TX descriptors to use before RS bit is set. */
185 uint16_t tx_rs_thresh;
186 /** Number of TX descriptors used since RS bit was set. */
188 /** Index to last TX descriptor to have been cleaned. */
189 uint16_t last_desc_cleaned;
190 /** Total number of TX descriptors ready to be allocated. */
192 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
193 uint16_t tx_next_rs; /**< next desc to set RS bit */
194 uint16_t queue_id; /**< TX queue index. */
195 uint8_t port_id; /**< Device port identifier. */
196 uint8_t pthresh; /**< Prefetch threshold register. */
197 uint8_t hthresh; /**< Host threshold register. */
198 uint8_t wthresh; /**< Write-back threshold reg. */
199 uint32_t txq_flags; /**< Holds flags for this TXq */
200 uint32_t ctx_curr; /**< Hardware context states. */
201 /** Hardware context0 history. */
202 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
207 #define RTE_PMD_USE_PREFETCH
210 #ifdef RTE_PMD_USE_PREFETCH
212 * Prefetch a cache line into all cache levels.
214 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
216 #define rte_ixgbe_prefetch(p) do {} while(0)
219 #ifdef RTE_PMD_PACKET_PREFETCH
220 #define rte_packet_prefetch(p) rte_prefetch1(p)
222 #define rte_packet_prefetch(p) do {} while(0)
225 /*********************************************************************
229 **********************************************************************/
232 * The "simple" TX queue functions require that the following
233 * flags are set when the TX queue is configured:
234 * - ETH_TXQ_FLAGS_NOMULTSEGS
235 * - ETH_TXQ_FLAGS_NOVLANOFFL
236 * - ETH_TXQ_FLAGS_NOXSUMSCTP
237 * - ETH_TXQ_FLAGS_NOXSUMUDP
238 * - ETH_TXQ_FLAGS_NOXSUMTCP
239 * and that the RS bit threshold (tx_rs_thresh) is at least equal to
240 * RTE_PMD_IXGBE_TX_MAX_BURST.
242 #define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
243 ETH_TXQ_FLAGS_NOOFFLOADS)
246 * Check for descriptors with their DD bit set and free mbufs.
247 * Return the total number of buffers freed.
250 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
252 struct igb_tx_entry *txep;
256 /* check DD bit on threshold descriptor */
257 status = txq->tx_ring[txq->tx_next_dd].wb.status;
258 if (! (status & IXGBE_ADVTXD_STAT_DD))
262 * first buffer to free from S/W ring is at index
263 * tx_next_dd - (tx_rs_thresh-1)
265 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
267 /* prefetch the mbufs that are about to be freed */
268 for (i = 0; i < txq->tx_rs_thresh; ++i)
269 rte_prefetch0((txep + i)->mbuf);
271 /* free buffers one at a time */
272 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
273 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
274 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
278 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
279 rte_pktmbuf_free_seg(txep->mbuf);
284 /* buffers were freed, update counters */
285 txq->nb_tx_free += txq->tx_rs_thresh;
286 txq->tx_next_dd += txq->tx_rs_thresh;
287 if (txq->tx_next_dd >= txq->nb_tx_desc)
288 txq->tx_next_dd = txq->tx_rs_thresh - 1;
290 return txq->tx_rs_thresh;
294 * Populate descriptors with the following info:
295 * 1.) buffer_addr = phys_addr + headroom
296 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
297 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
300 /* Defines for Tx descriptor */
301 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
302 IXGBE_ADVTXD_DCMD_IFCS |\
303 IXGBE_ADVTXD_DCMD_DEXT |\
304 IXGBE_ADVTXD_DCMD_EOP)
306 /* Populate 4 descriptors with data from 4 mbufs */
308 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
310 uint64_t buf_dma_addr;
314 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
315 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
316 pkt_len = (*pkts)->pkt.data_len;
318 /* write data to descriptor */
319 txdp->read.buffer_addr = buf_dma_addr;
320 txdp->read.cmd_type_len =
321 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
322 txdp->read.olinfo_status =
323 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
327 /* Populate 1 descriptor with data from 1 mbuf */
329 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
331 uint64_t buf_dma_addr;
334 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
335 pkt_len = (*pkts)->pkt.data_len;
337 /* write data to descriptor */
338 txdp->read.buffer_addr = buf_dma_addr;
339 txdp->read.cmd_type_len =
340 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
341 txdp->read.olinfo_status =
342 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
346 * Fill H/W descriptor ring with mbuf data.
347 * Copy mbuf pointers to the S/W ring.
350 ixgbe_tx_fill_hw_ring(struct igb_tx_queue *txq, struct rte_mbuf **pkts,
353 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
354 struct igb_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
355 const int N_PER_LOOP = 4;
356 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
357 int mainpart, leftover;
361 * Process most of the packets in chunks of N pkts. Any
362 * leftover packets will get processed one at a time.
364 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
365 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
366 for (i = 0; i < mainpart; i += N_PER_LOOP) {
367 /* Copy N mbuf pointers to the S/W ring */
368 for (j = 0; j < N_PER_LOOP; ++j) {
369 (txep + i + j)->mbuf = *(pkts + i + j);
371 tx4(txdp + i, pkts + i);
374 if (unlikely(leftover > 0)) {
375 for (i = 0; i < leftover; ++i) {
376 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
377 tx1(txdp + mainpart + i, pkts + mainpart + i);
382 static inline uint16_t
383 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
386 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
387 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
391 * Begin scanning the H/W ring for done descriptors when the
392 * number of available descriptors drops below tx_free_thresh. For
393 * each done descriptor, free the associated buffer.
395 if (txq->nb_tx_free < txq->tx_free_thresh)
396 ixgbe_tx_free_bufs(txq);
398 /* Only use descriptors that are available */
399 nb_pkts = RTE_MIN(txq->nb_tx_free, nb_pkts);
400 if (unlikely(nb_pkts == 0))
403 /* Use exactly nb_pkts descriptors */
404 txq->nb_tx_free -= nb_pkts;
407 * At this point, we know there are enough descriptors in the
408 * ring to transmit all the packets. This assumes that each
409 * mbuf contains a single segment, and that no new offloads
410 * are expected, which would require a new context descriptor.
414 * See if we're going to wrap-around. If so, handle the top
415 * of the descriptor ring first, then do the bottom. If not,
416 * the processing looks just like the "bottom" part anyway...
418 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
419 n = txq->nb_tx_desc - txq->tx_tail;
420 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
423 * We know that the last descriptor in the ring will need to
424 * have its RS bit set because tx_rs_thresh has to be
425 * a divisor of the ring size
427 tx_r[txq->tx_next_rs].read.cmd_type_len |=
428 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
429 txq->tx_next_rs = txq->tx_rs_thresh - 1;
434 /* Fill H/W descriptor ring with mbuf data */
435 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, nb_pkts - n);
436 txq->tx_tail += (nb_pkts - n);
439 * Determine if RS bit should be set
440 * This is what we actually want:
441 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
442 * but instead of subtracting 1 and doing >=, we can just do
443 * greater than without subtracting.
445 if (txq->tx_tail > txq->tx_next_rs) {
446 tx_r[txq->tx_next_rs].read.cmd_type_len |=
447 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
448 txq->tx_next_rs += txq->tx_rs_thresh;
449 if (txq->tx_next_rs >= txq->nb_tx_desc)
450 txq->tx_next_rs = txq->tx_rs_thresh - 1;
454 * Check for wrap-around. This would only happen if we used
455 * up to the last descriptor in the ring, no more, no less.
457 if (txq->tx_tail >= txq->nb_tx_desc)
460 /* update tail pointer */
462 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
468 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
473 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
474 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
475 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
477 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
481 n = RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
482 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
493 ixgbe_set_xmit_ctx(struct igb_tx_queue* txq,
494 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
495 uint16_t ol_flags, uint32_t vlan_macip_lens)
497 uint32_t type_tucmd_mlhl;
498 uint32_t mss_l4len_idx;
502 ctx_idx = txq->ctx_curr;
506 if (ol_flags & PKT_TX_VLAN_PKT) {
507 cmp_mask |= TX_VLAN_CMP_MASK;
510 if (ol_flags & PKT_TX_IP_CKSUM) {
511 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
512 cmp_mask |= TX_MAC_LEN_CMP_MASK;
515 /* Specify which HW CTX to upload. */
516 mss_l4len_idx = (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
517 switch (ol_flags & PKT_TX_L4_MASK) {
518 case PKT_TX_UDP_CKSUM:
519 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
520 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
521 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
522 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
524 case PKT_TX_TCP_CKSUM:
525 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
526 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
527 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
528 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
530 case PKT_TX_SCTP_CKSUM:
531 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
532 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
533 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
534 cmp_mask |= TX_MACIP_LEN_CMP_MASK;
537 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
538 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
542 txq->ctx_cache[ctx_idx].flags = ol_flags;
543 txq->ctx_cache[ctx_idx].cmp_mask = cmp_mask;
544 txq->ctx_cache[ctx_idx].vlan_macip_lens = vlan_macip_lens & cmp_mask;
546 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
547 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
548 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
549 ctx_txd->seqnum_seed = 0;
553 * Check which hardware context can be used. Use the existing match
554 * or create a new context descriptor.
556 static inline uint32_t
557 what_advctx_update(struct igb_tx_queue *txq, uint16_t flags,
558 uint32_t vlan_macip_lens)
560 /* If match with the current used context */
561 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
562 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens ==
563 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
564 return txq->ctx_curr;
567 /* What if match with the next context */
569 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
570 (txq->ctx_cache[txq->ctx_curr].vlan_macip_lens ==
571 (txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {
572 return txq->ctx_curr;
575 /* Mismatch, use the previous context */
576 return (IXGBE_CTX_NUM);
579 static inline uint32_t
580 tx_desc_cksum_flags_to_olinfo(uint16_t ol_flags)
582 static const uint32_t l4_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_TXSM};
583 static const uint32_t l3_olinfo[2] = {0, IXGBE_ADVTXD_POPTS_IXSM};
586 tmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];
587 tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
591 static inline uint32_t
592 tx_desc_vlan_flags_to_cmdtype(uint16_t ol_flags)
594 static const uint32_t vlan_cmd[2] = {0, IXGBE_ADVTXD_DCMD_VLE};
595 return vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
598 /* Default RS bit threshold values */
599 #ifndef DEFAULT_TX_RS_THRESH
600 #define DEFAULT_TX_RS_THRESH 32
602 #ifndef DEFAULT_TX_FREE_THRESH
603 #define DEFAULT_TX_FREE_THRESH 32
606 /* Reset transmit descriptors after they have been used */
608 ixgbe_xmit_cleanup(struct igb_tx_queue *txq)
610 struct igb_tx_entry *sw_ring = txq->sw_ring;
611 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
612 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
613 uint16_t nb_tx_desc = txq->nb_tx_desc;
614 uint16_t desc_to_clean_to;
615 uint16_t nb_tx_to_clean;
617 /* Determine the last descriptor needing to be cleaned */
618 desc_to_clean_to = last_desc_cleaned + txq->tx_rs_thresh;
619 if (desc_to_clean_to >= nb_tx_desc)
620 desc_to_clean_to = desc_to_clean_to - nb_tx_desc;
622 /* Check to make sure the last descriptor to clean is done */
623 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
624 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
626 PMD_TX_FREE_LOG(DEBUG,
627 "TX descriptor %4u is not done"
628 "(port=%d queue=%d)",
630 txq->port_id, txq->queue_id);
631 /* Failed to clean any descriptors, better luck next time */
635 /* Figure out how many descriptors will be cleaned */
636 if (last_desc_cleaned > desc_to_clean_to)
637 nb_tx_to_clean = ((nb_tx_desc - last_desc_cleaned) +
640 nb_tx_to_clean = desc_to_clean_to - last_desc_cleaned;
642 PMD_TX_FREE_LOG(DEBUG,
643 "Cleaning %4u TX descriptors: %4u to %4u "
644 "(port=%d queue=%d)",
645 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
646 txq->port_id, txq->queue_id);
649 * The last descriptor to clean is done, so that means all the
650 * descriptors from the last descriptor that was cleaned
651 * up to the last descriptor with the RS bit set
652 * are done. Only reset the threshold descriptor.
654 txr[desc_to_clean_to].wb.status = 0;
656 /* Update the txq to reflect the last descriptor that was cleaned */
657 txq->last_desc_cleaned = desc_to_clean_to;
658 txq->nb_tx_free += nb_tx_to_clean;
665 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
668 struct igb_tx_queue *txq;
669 struct igb_tx_entry *sw_ring;
670 struct igb_tx_entry *txe, *txn;
671 volatile union ixgbe_adv_tx_desc *txr;
672 volatile union ixgbe_adv_tx_desc *txd;
673 struct rte_mbuf *tx_pkt;
674 struct rte_mbuf *m_seg;
675 uint64_t buf_dma_addr;
676 uint32_t olinfo_status;
677 uint32_t cmd_type_len;
686 uint32_t vlan_macip_lens;
691 sw_ring = txq->sw_ring;
693 tx_id = txq->tx_tail;
694 txe = &sw_ring[tx_id];
696 /* Determine if the descriptor ring needs to be cleaned. */
697 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
698 ixgbe_xmit_cleanup(txq);
702 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
705 pkt_len = tx_pkt->pkt.pkt_len;
707 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
710 * Determine how many (if any) context descriptors
711 * are needed for offload functionality.
713 ol_flags = tx_pkt->ol_flags;
714 vlan_macip_lens = tx_pkt->pkt.vlan_tci << 16 |
715 tx_pkt->pkt.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT |
718 /* If hardware offload required */
719 tx_ol_req = ol_flags & PKT_TX_OFFLOAD_MASK;
721 /* If new context need be built or reuse the exist ctx. */
722 ctx = what_advctx_update(txq, tx_ol_req, vlan_macip_lens);
723 /* Only allocate context descriptor if required*/
724 new_ctx = (ctx == IXGBE_CTX_NUM);
729 * Keep track of how many descriptors are used this loop
730 * This will always be the number of segments + the number of
731 * Context descriptors required to transmit the packet
733 nb_used = tx_pkt->pkt.nb_segs + new_ctx;
736 * The number of descriptors that must be allocated for a
737 * packet is the number of segments of that packet, plus 1
738 * Context Descriptor for the hardware offload, if any.
739 * Determine the last TX descriptor to allocate in the TX ring
740 * for the packet, starting from the current position (tx_id)
743 tx_last = (uint16_t) (tx_id + nb_used - 1);
746 if (tx_last >= txq->nb_tx_desc)
747 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
749 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
750 " tx_first=%u tx_last=%u\n",
751 (unsigned) txq->port_id,
752 (unsigned) txq->queue_id,
758 * Make sure there are enough TX descriptors available to
759 * transmit the entire packet.
760 * nb_used better be less than or equal to txq->tx_rs_thresh
762 if (nb_used > txq->nb_tx_free) {
763 PMD_TX_FREE_LOG(DEBUG,
764 "Not enough free TX descriptors "
765 "nb_used=%4u nb_free=%4u "
766 "(port=%d queue=%d)",
767 nb_used, txq->nb_tx_free,
768 txq->port_id, txq->queue_id);
770 if (ixgbe_xmit_cleanup(txq) != 0) {
771 /* Could not clean any descriptors */
777 /* nb_used better be <= txq->tx_rs_thresh */
778 if (unlikely(nb_used > txq->tx_rs_thresh)) {
779 PMD_TX_FREE_LOG(DEBUG,
780 "The number of descriptors needed to "
781 "transmit the packet exceeds the "
782 "RS bit threshold. This will impact "
784 "nb_used=%4u nb_free=%4u "
786 "(port=%d queue=%d)",
787 nb_used, txq->nb_tx_free,
789 txq->port_id, txq->queue_id);
791 * Loop here until there are enough TX
792 * descriptors or until the ring cannot be
795 while (nb_used > txq->nb_tx_free) {
796 if (ixgbe_xmit_cleanup(txq) != 0) {
798 * Could not clean any
810 * By now there are enough free TX descriptors to transmit
815 * Set common flags of all TX Data Descriptors.
817 * The following bits must be set in all Data Descriptors:
818 * - IXGBE_ADVTXD_DTYP_DATA
819 * - IXGBE_ADVTXD_DCMD_DEXT
821 * The following bits must be set in the first Data Descriptor
822 * and are ignored in the other ones:
823 * - IXGBE_ADVTXD_DCMD_IFCS
824 * - IXGBE_ADVTXD_MAC_1588
825 * - IXGBE_ADVTXD_DCMD_VLE
827 * The following bits must only be set in the last Data
829 * - IXGBE_TXD_CMD_EOP
831 * The following bits can be set in any Data Descriptor, but
832 * are only set in the last Data Descriptor:
835 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
836 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
837 olinfo_status = (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
838 #ifdef RTE_LIBRTE_IEEE1588
839 if (ol_flags & PKT_TX_IEEE1588_TMST)
840 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
845 * Setup the TX Advanced Context Descriptor if required
848 volatile struct ixgbe_adv_tx_context_desc *
851 ctx_txd = (volatile struct
852 ixgbe_adv_tx_context_desc *)
855 txn = &sw_ring[txe->next_id];
856 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
858 if (txe->mbuf != NULL) {
859 rte_pktmbuf_free_seg(txe->mbuf);
863 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
866 txe->last_id = tx_last;
867 tx_id = txe->next_id;
872 * Setup the TX Advanced Data Descriptor,
873 * This path will go through
874 * whatever new/reuse the context descriptor
876 cmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);
877 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
878 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
884 txn = &sw_ring[txe->next_id];
886 if (txe->mbuf != NULL)
887 rte_pktmbuf_free_seg(txe->mbuf);
891 * Set up Transmit Data Descriptor.
893 slen = m_seg->pkt.data_len;
894 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
895 txd->read.buffer_addr =
896 rte_cpu_to_le_64(buf_dma_addr);
897 txd->read.cmd_type_len =
898 rte_cpu_to_le_32(cmd_type_len | slen);
899 txd->read.olinfo_status =
900 rte_cpu_to_le_32(olinfo_status);
901 txe->last_id = tx_last;
902 tx_id = txe->next_id;
904 m_seg = m_seg->pkt.next;
905 } while (m_seg != NULL);
908 * The last packet data descriptor needs End Of Packet (EOP)
910 cmd_type_len |= IXGBE_TXD_CMD_EOP;
911 txq->nb_tx_used += nb_used;
912 txq->nb_tx_free -= nb_used;
914 /* Set RS bit only on threshold packets' last descriptor */
915 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
916 PMD_TX_FREE_LOG(DEBUG,
917 "Setting RS bit on TXD id="
918 "%4u (port=%d queue=%d)",
919 tx_last, txq->port_id, txq->queue_id);
921 cmd_type_len |= IXGBE_TXD_CMD_RS;
923 /* Update txq RS bit counters */
926 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
932 * Set the Transmit Descriptor Tail (TDT)
934 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
935 (unsigned) txq->port_id, (unsigned) txq->queue_id,
936 (unsigned) tx_id, (unsigned) nb_tx);
937 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
938 txq->tx_tail = tx_id;
943 /*********************************************************************
947 **********************************************************************/
948 static inline uint16_t
949 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
953 static uint16_t ip_pkt_types_map[16] = {
954 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
955 PKT_RX_IPV6_HDR, 0, 0, 0,
956 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
957 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
960 static uint16_t ip_rss_types_map[16] = {
961 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
962 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
963 PKT_RX_RSS_HASH, 0, 0, 0,
964 0, 0, 0, PKT_RX_FDIR,
967 #ifdef RTE_LIBRTE_IEEE1588
968 static uint32_t ip_pkt_etqf_map[8] = {
969 0, 0, 0, PKT_RX_IEEE1588_PTP,
973 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
974 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
975 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
977 pkt_flags = (uint16_t) ((hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
978 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F]);
981 return (pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF]);
984 static inline uint16_t
985 rx_desc_status_to_pkt_flags(uint32_t rx_status)
990 * Check if VLAN present only.
991 * Do not check whether L3/L4 rx checksum done by NIC or not,
992 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
994 pkt_flags = (uint16_t) (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
996 #ifdef RTE_LIBRTE_IEEE1588
997 if (rx_status & IXGBE_RXD_STAT_TMST)
998 pkt_flags = (pkt_flags | PKT_RX_IEEE1588_TMST);
1003 static inline uint16_t
1004 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1007 * Bit 31: IPE, IPv4 checksum error
1008 * Bit 30: L4I, L4I integrity error
1010 static uint16_t error_to_pkt_flags_map[4] = {
1011 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
1012 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1014 return error_to_pkt_flags_map[(rx_status >>
1015 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1018 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1020 * LOOK_AHEAD defines how many desc statuses to check beyond the
1021 * current descriptor.
1022 * It must be a pound define for optimal performance.
1023 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1024 * function only works with LOOK_AHEAD=8.
1026 #define LOOK_AHEAD 8
1027 #if (LOOK_AHEAD != 8)
1028 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1031 ixgbe_rx_scan_hw_ring(struct igb_rx_queue *rxq)
1033 volatile union ixgbe_adv_rx_desc *rxdp;
1034 struct igb_rx_entry *rxep;
1035 struct rte_mbuf *mb;
1037 int s[LOOK_AHEAD], nb_dd;
1038 int i, j, nb_rx = 0;
1041 /* get references to current descriptor and S/W ring entry */
1042 rxdp = &rxq->rx_ring[rxq->rx_tail];
1043 rxep = &rxq->sw_ring[rxq->rx_tail];
1045 /* check to make sure there is at least 1 packet to receive */
1046 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
1050 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1051 * reference packets that are ready to be received.
1053 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1054 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
1056 /* Read desc statuses backwards to avoid race condition */
1057 for (j = LOOK_AHEAD-1; j >= 0; --j)
1058 s[j] = rxdp[j].wb.upper.status_error;
1060 /* Clear everything but the status bits (LSB) */
1061 for (j = 0; j < LOOK_AHEAD; ++j)
1062 s[j] &= IXGBE_RXDADV_STAT_DD;
1064 /* Compute how many status bits were set */
1065 nb_dd = s[0]+s[1]+s[2]+s[3]+s[4]+s[5]+s[6]+s[7];
1068 /* Translate descriptor info to mbuf format */
1069 for (j = 0; j < nb_dd; ++j) {
1071 pkt_len = rxdp[j].wb.upper.length - rxq->crc_len;
1072 mb->pkt.data_len = pkt_len;
1073 mb->pkt.pkt_len = pkt_len;
1074 mb->pkt.vlan_macip.f.vlan_tci = rxdp[j].wb.upper.vlan;
1075 mb->pkt.hash.rss = rxdp[j].wb.lower.hi_dword.rss;
1077 /* convert descriptor fields to rte mbuf flags */
1078 mb->ol_flags = rx_desc_hlen_type_rss_to_pkt_flags(
1079 rxdp[j].wb.lower.lo_dword.data);
1080 /* reuse status field from scan list */
1081 mb->ol_flags |= rx_desc_status_to_pkt_flags(s[j]);
1082 mb->ol_flags |= rx_desc_error_to_pkt_flags(s[j]);
1085 /* Move mbuf pointers from the S/W ring to the stage */
1086 for (j = 0; j < LOOK_AHEAD; ++j) {
1087 rxq->rx_stage[i + j] = rxep[j].mbuf;
1090 /* stop if all requested packets could not be received */
1091 if (nb_dd != LOOK_AHEAD)
1095 /* clear software ring entries so we can cleanup correctly */
1096 for (i = 0; i < nb_rx; ++i)
1097 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1103 ixgbe_rx_alloc_bufs(struct igb_rx_queue *rxq)
1105 volatile union ixgbe_adv_rx_desc *rxdp;
1106 struct igb_rx_entry *rxep;
1107 struct rte_mbuf *mb;
1112 /* allocate buffers in bulk directly into the S/W ring */
1113 alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1114 rxep = &rxq->sw_ring[alloc_idx];
1115 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1116 rxq->rx_free_thresh);
1117 if (unlikely(diag != 0))
1120 rxdp = &rxq->rx_ring[alloc_idx];
1121 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1122 /* populate the static rte mbuf fields */
1124 rte_mbuf_refcnt_set(mb, 1);
1125 mb->type = RTE_MBUF_PKT;
1126 mb->pkt.next = NULL;
1127 mb->pkt.data = (char *)mb->buf_addr + RTE_PKTMBUF_HEADROOM;
1128 mb->pkt.nb_segs = 1;
1129 mb->pkt.in_port = rxq->port_id;
1131 /* populate the descriptors */
1132 dma_addr = (uint64_t)mb->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1133 rxdp[i].read.hdr_addr = dma_addr;
1134 rxdp[i].read.pkt_addr = dma_addr;
1137 /* update tail pointer */
1139 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1141 /* update state of internal queue structure */
1142 rxq->rx_free_trigger += rxq->rx_free_thresh;
1143 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1144 rxq->rx_free_trigger = (rxq->rx_free_thresh - 1);
1150 static inline uint16_t
1151 ixgbe_rx_fill_from_stage(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1154 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1157 /* how many packets are ready to return? */
1158 nb_pkts = RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1160 /* copy mbuf pointers to the application's packet list */
1161 for (i = 0; i < nb_pkts; ++i)
1162 rx_pkts[i] = stage[i];
1164 /* update internal queue state */
1165 rxq->rx_nb_avail -= nb_pkts;
1166 rxq->rx_next_avail += nb_pkts;
1171 static inline uint16_t
1172 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1175 struct igb_rx_queue *rxq = (struct igb_rx_queue *)rx_queue;
1178 /* Any previously recv'd pkts will be returned from the Rx stage */
1179 if (rxq->rx_nb_avail)
1180 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1182 /* Scan the H/W ring for packets to receive */
1183 nb_rx = ixgbe_rx_scan_hw_ring(rxq);
1185 /* update internal queue state */
1186 rxq->rx_next_avail = 0;
1187 rxq->rx_nb_avail = nb_rx;
1188 rxq->rx_tail += nb_rx;
1190 /* if required, allocate new buffers to replenish descriptors */
1191 if (rxq->rx_tail > rxq->rx_free_trigger) {
1192 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1194 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1195 "queue_id=%u\n", (unsigned) rxq->port_id,
1196 (unsigned) rxq->queue_id);
1198 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1199 rxq->rx_free_thresh;
1202 * Need to rewind any previous receives if we cannot
1203 * allocate new buffers to replenish the old ones.
1205 rxq->rx_nb_avail = 0;
1206 rxq->rx_tail -= nb_rx;
1207 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1208 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1214 if (rxq->rx_tail >= rxq->nb_rx_desc)
1217 /* received any packets this loop? */
1218 if (rxq->rx_nb_avail)
1219 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1224 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1226 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1231 if (unlikely(nb_pkts == 0))
1234 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1235 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1237 /* request is relatively large, chunk it up */
1241 n = RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1242 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1251 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1254 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1257 struct igb_rx_queue *rxq;
1258 volatile union ixgbe_adv_rx_desc *rx_ring;
1259 volatile union ixgbe_adv_rx_desc *rxdp;
1260 struct igb_rx_entry *sw_ring;
1261 struct igb_rx_entry *rxe;
1262 struct rte_mbuf *rxm;
1263 struct rte_mbuf *nmb;
1264 union ixgbe_adv_rx_desc rxd;
1267 uint32_t hlen_type_rss;
1277 rx_id = rxq->rx_tail;
1278 rx_ring = rxq->rx_ring;
1279 sw_ring = rxq->sw_ring;
1280 while (nb_rx < nb_pkts) {
1282 * The order of operations here is important as the DD status
1283 * bit must not be read after any other descriptor fields.
1284 * rx_ring and rxdp are pointing to volatile data so the order
1285 * of accesses cannot be reordered by the compiler. If they were
1286 * not volatile, they could be reordered which could lead to
1287 * using invalid descriptor fields when read from rxd.
1289 rxdp = &rx_ring[rx_id];
1290 staterr = rxdp->wb.upper.status_error;
1291 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1298 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1299 * is likely to be invalid and to be dropped by the various
1300 * validation checks performed by the network stack.
1302 * Allocate a new mbuf to replenish the RX ring descriptor.
1303 * If the allocation fails:
1304 * - arrange for that RX descriptor to be the first one
1305 * being parsed the next time the receive function is
1306 * invoked [on the same queue].
1308 * - Stop parsing the RX ring and return immediately.
1310 * This policy do not drop the packet received in the RX
1311 * descriptor for which the allocation of a new mbuf failed.
1312 * Thus, it allows that packet to be later retrieved if
1313 * mbuf have been freed in the mean time.
1314 * As a side effect, holding RX descriptors instead of
1315 * systematically giving them back to the NIC may lead to
1316 * RX ring exhaustion situations.
1317 * However, the NIC can gracefully prevent such situations
1318 * to happen by sending specific "back-pressure" flow control
1319 * frames to its peer(s).
1321 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1322 "ext_err_stat=0x%08x pkt_len=%u\n",
1323 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1324 (unsigned) rx_id, (unsigned) staterr,
1325 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1327 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1329 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1330 "queue_id=%u\n", (unsigned) rxq->port_id,
1331 (unsigned) rxq->queue_id);
1332 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1337 rxe = &sw_ring[rx_id];
1339 if (rx_id == rxq->nb_rx_desc)
1342 /* Prefetch next mbuf while processing current one. */
1343 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1346 * When next RX descriptor is on a cache-line boundary,
1347 * prefetch the next 4 RX descriptors and the next 8 pointers
1350 if ((rx_id & 0x3) == 0) {
1351 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1352 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1358 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1359 rxdp->read.hdr_addr = dma_addr;
1360 rxdp->read.pkt_addr = dma_addr;
1363 * Initialize the returned mbuf.
1364 * 1) setup generic mbuf fields:
1365 * - number of segments,
1368 * - RX port identifier.
1369 * 2) integrate hardware offload data, if any:
1370 * - RSS flag & hash,
1371 * - IP checksum flag,
1372 * - VLAN TCI, if any,
1375 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1377 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1378 rte_packet_prefetch(rxm->pkt.data);
1379 rxm->pkt.nb_segs = 1;
1380 rxm->pkt.next = NULL;
1381 rxm->pkt.pkt_len = pkt_len;
1382 rxm->pkt.data_len = pkt_len;
1383 rxm->pkt.in_port = rxq->port_id;
1385 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1386 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1387 rxm->pkt.vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1389 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1390 pkt_flags = (pkt_flags | rx_desc_status_to_pkt_flags(staterr));
1391 pkt_flags = (pkt_flags | rx_desc_error_to_pkt_flags(staterr));
1392 rxm->ol_flags = pkt_flags;
1394 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1395 rxm->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1396 else if (pkt_flags & PKT_RX_FDIR) {
1397 rxm->pkt.hash.fdir.hash =
1398 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1399 & IXGBE_ATR_HASH_MASK);
1400 rxm->pkt.hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1403 * Store the mbuf address into the next entry of the array
1404 * of returned packets.
1406 rx_pkts[nb_rx++] = rxm;
1408 rxq->rx_tail = rx_id;
1411 * If the number of free RX descriptors is greater than the RX free
1412 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1414 * Update the RDT with the value of the last processed RX descriptor
1415 * minus 1, to guarantee that the RDT register is never equal to the
1416 * RDH register, which creates a "full" ring situtation from the
1417 * hardware point of view...
1419 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1420 if (nb_hold > rxq->rx_free_thresh) {
1421 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1422 "nb_hold=%u nb_rx=%u\n",
1423 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1424 (unsigned) rx_id, (unsigned) nb_hold,
1426 rx_id = (uint16_t) ((rx_id == 0) ?
1427 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1428 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1431 rxq->nb_rx_hold = nb_hold;
1436 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1439 struct igb_rx_queue *rxq;
1440 volatile union ixgbe_adv_rx_desc *rx_ring;
1441 volatile union ixgbe_adv_rx_desc *rxdp;
1442 struct igb_rx_entry *sw_ring;
1443 struct igb_rx_entry *rxe;
1444 struct rte_mbuf *first_seg;
1445 struct rte_mbuf *last_seg;
1446 struct rte_mbuf *rxm;
1447 struct rte_mbuf *nmb;
1448 union ixgbe_adv_rx_desc rxd;
1449 uint64_t dma; /* Physical address of mbuf data buffer */
1451 uint32_t hlen_type_rss;
1461 rx_id = rxq->rx_tail;
1462 rx_ring = rxq->rx_ring;
1463 sw_ring = rxq->sw_ring;
1466 * Retrieve RX context of current packet, if any.
1468 first_seg = rxq->pkt_first_seg;
1469 last_seg = rxq->pkt_last_seg;
1471 while (nb_rx < nb_pkts) {
1474 * The order of operations here is important as the DD status
1475 * bit must not be read after any other descriptor fields.
1476 * rx_ring and rxdp are pointing to volatile data so the order
1477 * of accesses cannot be reordered by the compiler. If they were
1478 * not volatile, they could be reordered which could lead to
1479 * using invalid descriptor fields when read from rxd.
1481 rxdp = &rx_ring[rx_id];
1482 staterr = rxdp->wb.upper.status_error;
1483 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1490 * Allocate a new mbuf to replenish the RX ring descriptor.
1491 * If the allocation fails:
1492 * - arrange for that RX descriptor to be the first one
1493 * being parsed the next time the receive function is
1494 * invoked [on the same queue].
1496 * - Stop parsing the RX ring and return immediately.
1498 * This policy does not drop the packet received in the RX
1499 * descriptor for which the allocation of a new mbuf failed.
1500 * Thus, it allows that packet to be later retrieved if
1501 * mbuf have been freed in the mean time.
1502 * As a side effect, holding RX descriptors instead of
1503 * systematically giving them back to the NIC may lead to
1504 * RX ring exhaustion situations.
1505 * However, the NIC can gracefully prevent such situations
1506 * to happen by sending specific "back-pressure" flow control
1507 * frames to its peer(s).
1509 PMD_RX_LOG(DEBUG, "\nport_id=%u queue_id=%u rx_id=%u "
1510 "staterr=0x%x data_len=%u\n",
1511 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1512 (unsigned) rx_id, (unsigned) staterr,
1513 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1515 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1517 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1518 "queue_id=%u\n", (unsigned) rxq->port_id,
1519 (unsigned) rxq->queue_id);
1520 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1525 rxe = &sw_ring[rx_id];
1527 if (rx_id == rxq->nb_rx_desc)
1530 /* Prefetch next mbuf while processing current one. */
1531 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1534 * When next RX descriptor is on a cache-line boundary,
1535 * prefetch the next 4 RX descriptors and the next 8 pointers
1538 if ((rx_id & 0x3) == 0) {
1539 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1540 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1544 * Update RX descriptor with the physical address of the new
1545 * data buffer of the new allocated mbuf.
1549 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1550 rxdp->read.hdr_addr = dma;
1551 rxdp->read.pkt_addr = dma;
1554 * Set data length & data buffer address of mbuf.
1556 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1557 rxm->pkt.data_len = data_len;
1558 rxm->pkt.data = (char*) rxm->buf_addr + RTE_PKTMBUF_HEADROOM;
1561 * If this is the first buffer of the received packet,
1562 * set the pointer to the first mbuf of the packet and
1563 * initialize its context.
1564 * Otherwise, update the total length and the number of segments
1565 * of the current scattered packet, and update the pointer to
1566 * the last mbuf of the current packet.
1568 if (first_seg == NULL) {
1570 first_seg->pkt.pkt_len = data_len;
1571 first_seg->pkt.nb_segs = 1;
1573 first_seg->pkt.pkt_len = (uint16_t)(first_seg->pkt.pkt_len
1575 first_seg->pkt.nb_segs++;
1576 last_seg->pkt.next = rxm;
1580 * If this is not the last buffer of the received packet,
1581 * update the pointer to the last mbuf of the current scattered
1582 * packet and continue to parse the RX ring.
1584 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1590 * This is the last buffer of the received packet.
1591 * If the CRC is not stripped by the hardware:
1592 * - Subtract the CRC length from the total packet length.
1593 * - If the last buffer only contains the whole CRC or a part
1594 * of it, free the mbuf associated to the last buffer.
1595 * If part of the CRC is also contained in the previous
1596 * mbuf, subtract the length of that CRC part from the
1597 * data length of the previous mbuf.
1599 rxm->pkt.next = NULL;
1600 if (unlikely(rxq->crc_len > 0)) {
1601 first_seg->pkt.pkt_len -= ETHER_CRC_LEN;
1602 if (data_len <= ETHER_CRC_LEN) {
1603 rte_pktmbuf_free_seg(rxm);
1604 first_seg->pkt.nb_segs--;
1605 last_seg->pkt.data_len = (uint16_t)
1606 (last_seg->pkt.data_len -
1607 (ETHER_CRC_LEN - data_len));
1608 last_seg->pkt.next = NULL;
1611 (uint16_t) (data_len - ETHER_CRC_LEN);
1615 * Initialize the first mbuf of the returned packet:
1616 * - RX port identifier,
1617 * - hardware offload data, if any:
1618 * - RSS flag & hash,
1619 * - IP checksum flag,
1620 * - VLAN TCI, if any,
1623 first_seg->pkt.in_port = rxq->port_id;
1626 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1627 * set in the pkt_flags field.
1629 first_seg->pkt.vlan_tci =
1630 rte_le_to_cpu_16(rxd.wb.upper.vlan);
1631 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1632 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1633 pkt_flags = (pkt_flags |
1634 rx_desc_status_to_pkt_flags(staterr));
1635 pkt_flags = (pkt_flags |
1636 rx_desc_error_to_pkt_flags(staterr));
1637 first_seg->ol_flags = pkt_flags;
1639 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1640 first_seg->pkt.hash.rss = rxd.wb.lower.hi_dword.rss;
1641 else if (pkt_flags & PKT_RX_FDIR) {
1642 first_seg->pkt.hash.fdir.hash =
1643 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1644 & IXGBE_ATR_HASH_MASK);
1645 first_seg->pkt.hash.fdir.id =
1646 rxd.wb.lower.hi_dword.csum_ip.ip_id;
1649 /* Prefetch data of first segment, if configured to do so. */
1650 rte_packet_prefetch(first_seg->pkt.data);
1653 * Store the mbuf address into the next entry of the array
1654 * of returned packets.
1656 rx_pkts[nb_rx++] = first_seg;
1659 * Setup receipt context for a new packet.
1665 * Record index of the next RX descriptor to probe.
1667 rxq->rx_tail = rx_id;
1670 * Save receive context.
1672 rxq->pkt_first_seg = first_seg;
1673 rxq->pkt_last_seg = last_seg;
1676 * If the number of free RX descriptors is greater than the RX free
1677 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1679 * Update the RDT with the value of the last processed RX descriptor
1680 * minus 1, to guarantee that the RDT register is never equal to the
1681 * RDH register, which creates a "full" ring situtation from the
1682 * hardware point of view...
1684 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1685 if (nb_hold > rxq->rx_free_thresh) {
1686 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1687 "nb_hold=%u nb_rx=%u\n",
1688 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1689 (unsigned) rx_id, (unsigned) nb_hold,
1691 rx_id = (uint16_t) ((rx_id == 0) ?
1692 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1693 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1696 rxq->nb_rx_hold = nb_hold;
1700 /*********************************************************************
1702 * Queue management functions
1704 **********************************************************************/
1707 * Rings setup and release.
1709 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1710 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1711 * also optimize cache line size effect. H/W supports up to cache line size 128.
1713 #define IXGBE_ALIGN 128
1716 * Maximum number of Ring Descriptors.
1718 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1719 * descriptors should meet the following condition:
1720 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1722 #define IXGBE_MIN_RING_DESC 64
1723 #define IXGBE_MAX_RING_DESC 4096
1726 * Create memzone for HW rings. malloc can't be used as the physical address is
1727 * needed. If the memzone is already created, then this function returns a ptr
1730 static const struct rte_memzone *
1731 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1732 uint16_t queue_id, uint32_t ring_size, int socket_id)
1734 char z_name[RTE_MEMZONE_NAMESIZE];
1735 const struct rte_memzone *mz;
1737 rte_snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1738 dev->driver->pci_drv.name, ring_name,
1739 dev->data->port_id, queue_id);
1741 mz = rte_memzone_lookup(z_name);
1745 return rte_memzone_reserve_aligned(z_name, (uint64_t) ring_size,
1746 socket_id, 0, IXGBE_ALIGN);
1750 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1754 if (txq->sw_ring != NULL) {
1755 for (i = 0; i < txq->nb_tx_desc; i++) {
1756 if (txq->sw_ring[i].mbuf != NULL) {
1757 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1758 txq->sw_ring[i].mbuf = NULL;
1765 ixgbe_tx_queue_release(struct igb_tx_queue *txq)
1768 ixgbe_tx_queue_release_mbufs(txq);
1769 rte_free(txq->sw_ring);
1775 ixgbe_dev_tx_queue_release(void *txq)
1777 ixgbe_tx_queue_release(txq);
1780 /* (Re)set dynamic igb_tx_queue fields to defaults */
1782 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
1784 struct igb_tx_entry *txe = txq->sw_ring;
1787 /* Zero out HW ring memory */
1788 for (i = 0; i < sizeof(union ixgbe_adv_tx_desc) * txq->nb_tx_desc; i++) {
1789 ((volatile char *)txq->tx_ring)[i] = 0;
1792 /* Initialize SW ring entries */
1793 prev = (uint16_t) (txq->nb_tx_desc - 1);
1794 for (i = 0; i < txq->nb_tx_desc; i++) {
1795 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1796 txd->wb.status = IXGBE_TXD_STAT_DD;
1799 txe[prev].next_id = i;
1803 txq->tx_next_dd = txq->tx_rs_thresh - 1;
1804 txq->tx_next_rs = txq->tx_rs_thresh - 1;
1807 txq->nb_tx_used = 0;
1809 * Always allow 1 descriptor to be un-allocated to avoid
1810 * a H/W race condition
1812 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1813 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1815 memset((void*)&txq->ctx_cache, 0,
1816 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1820 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1823 unsigned int socket_id,
1824 const struct rte_eth_txconf *tx_conf)
1826 const struct rte_memzone *tz;
1827 struct igb_tx_queue *txq;
1828 struct ixgbe_hw *hw;
1829 uint16_t tx_rs_thresh, tx_free_thresh;
1831 PMD_INIT_FUNC_TRACE();
1832 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835 * Validate number of transmit descriptors.
1836 * It must not exceed hardware maximum, and must be multiple
1839 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1840 (nb_desc > IXGBE_MAX_RING_DESC) ||
1841 (nb_desc < IXGBE_MIN_RING_DESC)) {
1846 * The following two parameters control the setting of the RS bit on
1847 * transmit descriptors.
1848 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1849 * descriptors have been used.
1850 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1851 * descriptors are used or if the number of descriptors required
1852 * to transmit a packet is greater than the number of free TX
1854 * The following constraints must be satisfied:
1855 * tx_rs_thresh must be greater than 0.
1856 * tx_rs_thresh must be less than the size of the ring minus 2.
1857 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1858 * tx_rs_thresh must be a divisor of the ring size.
1859 * tx_free_thresh must be greater than 0.
1860 * tx_free_thresh must be less than the size of the ring minus 3.
1861 * One descriptor in the TX ring is used as a sentinel to avoid a
1862 * H/W race condition, hence the maximum threshold constraints.
1863 * When set to zero use default values.
1865 tx_rs_thresh = (tx_conf->tx_rs_thresh) ?
1866 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH;
1867 tx_free_thresh = (tx_conf->tx_free_thresh) ?
1868 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH;
1869 if (tx_rs_thresh >= (nb_desc - 2)) {
1871 "tx_rs_thresh must be less than the "
1872 "number of TX descriptors minus 2. "
1873 "(tx_rs_thresh=%u port=%d queue=%d)",
1874 tx_rs_thresh, dev->data->port_id, queue_idx);
1877 if (tx_free_thresh >= (nb_desc - 3)) {
1879 "tx_rs_thresh must be less than the "
1880 "tx_free_thresh must be less than the "
1881 "number of TX descriptors minus 3. "
1882 "(tx_free_thresh=%u port=%d queue=%d)",
1883 tx_free_thresh, dev->data->port_id, queue_idx);
1886 if (tx_rs_thresh > tx_free_thresh) {
1888 "tx_rs_thresh must be less than or equal to "
1890 "(tx_free_thresh=%u tx_rs_thresh=%u "
1891 "port=%d queue=%d)\n",
1892 tx_free_thresh, tx_rs_thresh,
1893 dev->data->port_id, queue_idx);
1896 if ((nb_desc % tx_rs_thresh) != 0) {
1898 "tx_rs_thresh must be a divisor of the"
1899 "number of TX descriptors. "
1900 "(tx_rs_thresh=%u port=%d queue=%d)\n",
1901 tx_rs_thresh, dev->data->port_id, queue_idx);
1906 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1907 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1908 * by the NIC and all descriptors are written back after the NIC
1909 * accumulates WTHRESH descriptors.
1911 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1913 "TX WTHRESH should be set to 0 if "
1914 "tx_rs_thresh is greater than 1. "
1915 "TX WTHRESH will be set to 0. "
1916 "(tx_rs_thresh=%u port=%d queue=%d)",
1918 dev->data->port_id, queue_idx);
1922 /* Free memory prior to re-allocation if needed... */
1923 if (dev->data->tx_queues[queue_idx] != NULL)
1924 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1926 /* First allocate the tx queue data structure */
1927 txq = rte_zmalloc("ethdev TX queue", sizeof(struct igb_tx_queue),
1933 * Allocate TX ring hardware descriptors. A memzone large enough to
1934 * handle the maximum ring size is allocated in order to allow for
1935 * resizing in later calls to the queue setup function.
1937 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1938 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1941 ixgbe_tx_queue_release(txq);
1945 txq->nb_tx_desc = nb_desc;
1946 txq->tx_rs_thresh = tx_rs_thresh;
1947 txq->tx_free_thresh = tx_free_thresh;
1948 txq->pthresh = tx_conf->tx_thresh.pthresh;
1949 txq->hthresh = tx_conf->tx_thresh.hthresh;
1950 txq->wthresh = tx_conf->tx_thresh.wthresh;
1951 txq->queue_id = queue_idx;
1952 txq->port_id = dev->data->port_id;
1953 txq->txq_flags = tx_conf->txq_flags;
1956 * Modification to set VFTDT for virtual function if vf is detected
1958 if (hw->mac.type == ixgbe_mac_82599_vf)
1959 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1961 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(queue_idx));
1963 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1964 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1966 /* Allocate software ring */
1967 txq->sw_ring = rte_zmalloc("txq->sw_ring",
1968 sizeof(struct igb_tx_entry) * nb_desc,
1970 if (txq->sw_ring == NULL) {
1971 ixgbe_tx_queue_release(txq);
1974 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
1975 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1977 ixgbe_reset_tx_queue(txq);
1979 dev->data->tx_queues[queue_idx] = txq;
1981 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1982 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS) &&
1983 (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST))
1984 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1986 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1992 ixgbe_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1996 if (rxq->sw_ring != NULL) {
1997 for (i = 0; i < rxq->nb_rx_desc; i++) {
1998 if (rxq->sw_ring[i].mbuf != NULL) {
1999 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2000 rxq->sw_ring[i].mbuf = NULL;
2003 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2004 if (rxq->rx_nb_avail) {
2005 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2006 struct rte_mbuf *mb;
2007 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2008 rte_pktmbuf_free_seg(mb);
2010 rxq->rx_nb_avail = 0;
2017 ixgbe_rx_queue_release(struct igb_rx_queue *rxq)
2019 ixgbe_rx_queue_release_mbufs(rxq);
2020 rte_free(rxq->sw_ring);
2025 ixgbe_dev_rx_queue_release(void *rxq)
2027 ixgbe_rx_queue_release(rxq);
2031 * Check if Rx Burst Bulk Alloc function can be used.
2033 * 0: the preconditions are satisfied and the bulk allocation function
2035 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2036 * function must be used.
2039 check_rx_burst_bulk_alloc_preconditions(struct igb_rx_queue *rxq)
2044 * Make sure the following pre-conditions are satisfied:
2045 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2046 * rxq->rx_free_thresh < rxq->nb_rx_desc
2047 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2048 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2049 * Scattered packets are not supported. This should be checked
2050 * outside of this function.
2052 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2053 if (! (rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST))
2055 else if (! (rxq->rx_free_thresh < rxq->nb_rx_desc))
2057 else if (! ((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0))
2059 else if (! (rxq->nb_rx_desc <
2060 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)))
2069 /* (Re)set dynamic igb_rx_queue fields to defaults */
2071 ixgbe_reset_rx_queue(struct igb_rx_queue *rxq)
2076 * By default, the Rx queue setup function allocates enough memory for
2077 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2078 * extra memory at the end of the descriptor ring to be zero'd out. A
2079 * pre-condition for using the Rx burst bulk alloc function is that the
2080 * number of descriptors is less than or equal to
2081 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2082 * constraints here to see if we need to zero out memory after the end
2083 * of the H/W descriptor ring.
2085 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2086 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2087 /* zero out extra memory */
2088 len = rxq->nb_rx_desc + RTE_PMD_IXGBE_RX_MAX_BURST;
2091 /* do not zero out extra memory */
2092 len = rxq->nb_rx_desc;
2095 * Zero out HW ring memory. Zero out extra memory at the end of
2096 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2097 * reads extra memory as zeros.
2099 for (i = 0; i < len * sizeof(union ixgbe_adv_rx_desc); i++) {
2100 ((volatile char *)rxq->rx_ring)[i] = 0;
2103 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2105 * initialize extra software ring entries. Space for these extra
2106 * entries is always allocated
2108 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2109 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST; ++i) {
2110 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2113 rxq->rx_nb_avail = 0;
2114 rxq->rx_next_avail = 0;
2115 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
2116 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2118 rxq->nb_rx_hold = 0;
2119 rxq->pkt_first_seg = NULL;
2120 rxq->pkt_last_seg = NULL;
2124 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2127 unsigned int socket_id,
2128 const struct rte_eth_rxconf *rx_conf,
2129 struct rte_mempool *mp)
2131 const struct rte_memzone *rz;
2132 struct igb_rx_queue *rxq;
2133 struct ixgbe_hw *hw;
2135 PMD_INIT_FUNC_TRACE();
2136 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2139 * Validate number of receive descriptors.
2140 * It must not exceed hardware maximum, and must be multiple
2143 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2144 (nb_desc > IXGBE_MAX_RING_DESC) ||
2145 (nb_desc < IXGBE_MIN_RING_DESC)) {
2149 /* Free memory prior to re-allocation if needed... */
2150 if (dev->data->rx_queues[queue_idx] != NULL)
2151 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2153 /* First allocate the rx queue data structure */
2154 rxq = rte_zmalloc("ethdev RX queue", sizeof(struct igb_rx_queue),
2159 rxq->nb_rx_desc = nb_desc;
2160 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2161 rxq->queue_id = queue_idx;
2162 rxq->port_id = dev->data->port_id;
2163 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
2167 * Allocate TX ring hardware descriptors. A memzone large enough to
2168 * handle the maximum ring size is allocated in order to allow for
2169 * resizing in later calls to the queue setup function.
2171 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2172 IXGBE_MAX_RING_DESC * sizeof(union ixgbe_adv_rx_desc),
2175 ixgbe_rx_queue_release(rxq);
2179 * Modified to setup VFRDT for Virtual Function
2181 if (hw->mac.type == ixgbe_mac_82599_vf)
2182 rxq->rdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2184 rxq->rdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(queue_idx));
2186 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2187 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2190 * Allocate software ring. Allow for space at the end of the
2191 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2192 * function does not access an invalid memory region.
2194 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2195 len = nb_desc + RTE_PMD_IXGBE_RX_MAX_BURST;
2199 rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
2200 sizeof(struct igb_rx_entry) * nb_desc,
2202 if (rxq->sw_ring == NULL) {
2203 ixgbe_rx_queue_release(rxq);
2206 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64"\n",
2207 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2210 * Certain constaints must be met in order to use the bulk buffer
2211 * allocation Rx burst function.
2213 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2215 /* Check if pre-conditions are satisfied, and no Scattered Rx */
2216 if (!use_def_burst_func && !dev->data->scattered_rx) {
2217 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2218 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2219 "satisfied. Rx Burst Bulk Alloc function will be "
2220 "used on port=%d, queue=%d.\n",
2221 rxq->port_id, rxq->queue_id);
2222 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
2225 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions "
2226 "are not satisfied, Scattered Rx is requested, "
2227 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC is not "
2228 "enabled (port=%d, queue=%d).\n",
2229 rxq->port_id, rxq->queue_id);
2231 dev->data->rx_queues[queue_idx] = rxq;
2233 ixgbe_reset_rx_queue(rxq);
2239 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2244 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2245 struct igb_tx_queue *txq = dev->data->tx_queues[i];
2246 ixgbe_tx_queue_release_mbufs(txq);
2247 ixgbe_reset_tx_queue(txq);
2250 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2251 struct igb_rx_queue *rxq = dev->data->rx_queues[i];
2252 ixgbe_rx_queue_release_mbufs(rxq);
2253 ixgbe_reset_rx_queue(rxq);
2257 /*********************************************************************
2259 * Device RX/TX init functions
2261 **********************************************************************/
2264 * Receive Side Scaling (RSS)
2265 * See section 7.1.2.8 in the following document:
2266 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2269 * The source and destination IP addresses of the IP header and the source
2270 * and destination ports of TCP/UDP headers, if any, of received packets are
2271 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2272 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2273 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2274 * RSS output index which is used as the RX queue index where to store the
2276 * The following output is supplied in the RX write-back descriptor:
2277 * - 32-bit result of the Microsoft RSS hash function,
2278 * - 4-bit RSS type field.
2282 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2283 * Used as the default key.
2285 static uint8_t rss_intel_key[40] = {
2286 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2287 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2288 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2289 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2290 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2294 ixgbe_rss_disable(struct rte_eth_dev *dev)
2296 struct ixgbe_hw *hw;
2299 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2301 mrqc &= ~IXGBE_MRQC_RSSEN;
2302 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2306 ixgbe_rss_configure(struct rte_eth_dev *dev)
2308 struct ixgbe_hw *hw;
2317 PMD_INIT_FUNC_TRACE();
2318 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2320 rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
2321 if (rss_hf == 0) { /* Disable RSS */
2322 ixgbe_rss_disable(dev);
2325 hash_key = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
2326 if (hash_key == NULL)
2327 hash_key = rss_intel_key; /* Default hash key */
2329 /* Fill in RSS hash key */
2330 for (i = 0; i < 10; i++) {
2331 rss_key = hash_key[(i * 4)];
2332 rss_key |= hash_key[(i * 4) + 1] << 8;
2333 rss_key |= hash_key[(i * 4) + 2] << 16;
2334 rss_key |= hash_key[(i * 4) + 3] << 24;
2335 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2338 /* Fill in redirection table */
2340 for (i = 0, j = 0; i < 128; i++, j++) {
2341 if (j == dev->data->nb_rx_queues) j = 0;
2342 reta = (reta << 8) | j;
2344 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), rte_bswap32(reta));
2347 /* Set configured hashing functions in MRQC register */
2348 mrqc = IXGBE_MRQC_RSSEN; /* RSS enable */
2349 if (rss_hf & ETH_RSS_IPV4)
2350 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2351 if (rss_hf & ETH_RSS_IPV4_TCP)
2352 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2353 if (rss_hf & ETH_RSS_IPV6)
2354 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2355 if (rss_hf & ETH_RSS_IPV6_EX)
2356 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2357 if (rss_hf & ETH_RSS_IPV6_TCP)
2358 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2359 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2360 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2361 if (rss_hf & ETH_RSS_IPV4_UDP)
2362 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2363 if (rss_hf & ETH_RSS_IPV6_UDP)
2364 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2365 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2366 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2367 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2370 #define NUM_VFTA_REGISTERS 128
2371 #define NIC_RX_BUFFER_SIZE 0x200
2374 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2376 struct rte_eth_vmdq_dcb_conf *cfg;
2377 struct ixgbe_hw *hw;
2378 enum rte_eth_nb_pools num_pools;
2379 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2381 uint8_t nb_tcs; /* number of traffic classes */
2384 PMD_INIT_FUNC_TRACE();
2385 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2386 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2387 num_pools = cfg->nb_queue_pools;
2388 /* Check we have a valid number of pools */
2389 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2390 ixgbe_rss_disable(dev);
2393 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2394 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2398 * split rx buffer up into sections, each for 1 traffic class
2400 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2401 for (i = 0 ; i < nb_tcs; i++) {
2402 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2403 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2404 /* clear 10 bits. */
2405 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2406 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2408 /* zero alloc all unused TCs */
2409 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2410 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2411 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2412 /* clear 10 bits. */
2413 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2416 /* MRQC: enable vmdq and dcb */
2417 mrqc = ((num_pools == ETH_16_POOLS) ? \
2418 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2419 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2421 /* PFVTCTL: turn on virtualisation and set the default pool */
2422 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2423 if (cfg->enable_default_pool) {
2424 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2426 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2428 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2430 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2432 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2434 * mapping is done with 3 bits per priority,
2435 * so shift by i*3 each time
2437 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2439 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2441 /* RTRPCS: DCB related */
2442 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2444 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2445 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2446 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2447 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2449 /* VFTA - enable all vlan filters */
2450 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2451 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2454 /* VFRE: pool enabling for receive - 16 or 32 */
2455 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2456 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2459 * MPSAR - allow pools to read specific mac addresses
2460 * In this case, all pools should be able to read from mac addr 0
2462 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2463 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2465 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2466 for (i = 0; i < cfg->nb_pool_maps; i++) {
2467 /* set vlan id in VF register and set the valid bit */
2468 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2469 (cfg->pool_map[i].vlan_id & 0xFFF)));
2471 * Put the allowed pools in VFB reg. As we only have 16 or 32
2472 * pools, we only need to use the first half of the register
2475 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2480 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2481 * @hw: pointer to hardware structure
2482 * @dcb_config: pointer to ixgbe_dcb_config structure
2485 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2486 struct ixgbe_dcb_config *dcb_config)
2491 PMD_INIT_FUNC_TRACE();
2492 if (hw->mac.type != ixgbe_mac_82598EB) {
2493 /* Disable the Tx desc arbiter so that MTQC can be changed */
2494 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2495 reg |= IXGBE_RTTDCS_ARBDIS;
2496 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2498 /* Enable DCB for Tx with 8 TCs */
2499 if (dcb_config->num_tcs.pg_tcs == 8) {
2500 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2503 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2505 if (dcb_config->vt_mode)
2506 reg |= IXGBE_MTQC_VT_ENA;
2507 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2509 /* Disable drop for all queues */
2510 for (q = 0; q < 128; q++)
2511 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2512 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2514 /* Enable the Tx desc arbiter */
2515 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2516 reg &= ~IXGBE_RTTDCS_ARBDIS;
2517 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2519 /* Enable Security TX Buffer IFG for DCB */
2520 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2521 reg |= IXGBE_SECTX_DCB;
2522 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2528 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2529 * @dev: pointer to rte_eth_dev structure
2530 * @dcb_config: pointer to ixgbe_dcb_config structure
2533 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2534 struct ixgbe_dcb_config *dcb_config)
2536 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2537 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2538 struct ixgbe_hw *hw =
2539 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541 PMD_INIT_FUNC_TRACE();
2542 if (hw->mac.type != ixgbe_mac_82598EB)
2543 /*PF VF Transmit Enable*/
2544 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2545 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2547 /*Configure general DCB TX parameters*/
2548 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2553 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2554 struct ixgbe_dcb_config *dcb_config)
2556 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2557 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2558 struct ixgbe_dcb_tc_config *tc;
2561 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2562 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2563 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2564 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2567 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2568 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2570 /* User Priority to Traffic Class mapping */
2571 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2572 j = vmdq_rx_conf->dcb_queue[i];
2573 tc = &dcb_config->tc_config[j];
2574 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = (1 << j);
2579 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2580 struct ixgbe_dcb_config *dcb_config)
2582 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2583 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2584 struct ixgbe_dcb_tc_config *tc;
2587 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2588 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2589 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2590 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2593 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2594 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2597 /* User Priority to Traffic Class mapping */
2598 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2599 j = vmdq_tx_conf->dcb_queue[i];
2600 tc = &dcb_config->tc_config[j];
2601 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = (1 << j);
2607 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,struct ixgbe_dcb_config *dcb_config)
2609 struct rte_eth_dcb_rx_conf *rx_conf =
2610 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2611 struct ixgbe_dcb_tc_config *tc;
2614 dcb_config->num_tcs.pg_tcs = rx_conf->nb_tcs;
2615 dcb_config->num_tcs.pfc_tcs = rx_conf->nb_tcs;
2617 /* User Priority to Traffic Class mapping */
2618 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2619 j = rx_conf->dcb_queue[i];
2620 tc = &dcb_config->tc_config[j];
2621 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = (1 << j);
2626 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,struct ixgbe_dcb_config *dcb_config)
2628 struct rte_eth_dcb_tx_conf *tx_conf =
2629 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2630 struct ixgbe_dcb_tc_config *tc;
2633 dcb_config->num_tcs.pg_tcs = tx_conf->nb_tcs;
2634 dcb_config->num_tcs.pfc_tcs = tx_conf->nb_tcs;
2636 /* User Priority to Traffic Class mapping */
2637 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2638 j = tx_conf->dcb_queue[i];
2639 tc = &dcb_config->tc_config[j];
2640 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = (1 << j);
2645 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2646 * @hw: pointer to hardware structure
2647 * @dcb_config: pointer to ixgbe_dcb_config structure
2650 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2651 struct ixgbe_dcb_config *dcb_config)
2657 PMD_INIT_FUNC_TRACE();
2659 * Disable the arbiter before changing parameters
2660 * (always enable recycle mode; WSP)
2662 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2663 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2665 if (hw->mac.type != ixgbe_mac_82598EB) {
2666 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2667 if (dcb_config->num_tcs.pg_tcs == 4) {
2668 if (dcb_config->vt_mode)
2669 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2670 IXGBE_MRQC_VMDQRT4TCEN;
2672 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2673 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2677 if (dcb_config->num_tcs.pg_tcs == 8) {
2678 if (dcb_config->vt_mode)
2679 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2680 IXGBE_MRQC_VMDQRT8TCEN;
2682 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2683 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2688 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2691 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2692 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2693 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2694 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2696 /* VFTA - enable all vlan filters */
2697 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2698 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2702 * Configure Rx packet plane (recycle mode; WSP) and
2705 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2706 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2712 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2713 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2715 switch (hw->mac.type) {
2716 case ixgbe_mac_82598EB:
2717 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2719 case ixgbe_mac_82599EB:
2720 case ixgbe_mac_X540:
2721 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2730 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2731 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2733 switch (hw->mac.type) {
2734 case ixgbe_mac_82598EB:
2735 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2736 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2738 case ixgbe_mac_82599EB:
2739 case ixgbe_mac_X540:
2740 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2741 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2748 #define DCB_RX_CONFIG 1
2749 #define DCB_TX_CONFIG 1
2750 #define DCB_TX_PB 1024
2752 * ixgbe_dcb_hw_configure - Enable DCB and configure
2753 * general DCB in VT mode and non-VT mode parameters
2754 * @dev: pointer to rte_eth_dev structure
2755 * @dcb_config: pointer to ixgbe_dcb_config structure
2758 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2759 struct ixgbe_dcb_config *dcb_config)
2762 uint8_t i,pfc_en,nb_tcs;
2764 uint8_t config_dcb_rx = 0;
2765 uint8_t config_dcb_tx = 0;
2766 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2767 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2768 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2769 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2770 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2771 struct ixgbe_dcb_tc_config *tc;
2772 uint32_t max_frame = dev->data->max_frame_size;
2773 struct ixgbe_hw *hw =
2774 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2776 switch(dev->data->dev_conf.rxmode.mq_mode){
2778 dcb_config->vt_mode = true;
2779 if (hw->mac.type != ixgbe_mac_82598EB) {
2780 config_dcb_rx = DCB_RX_CONFIG;
2782 *get dcb and VT rx configuration parameters
2785 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2786 /*Configure general VMDQ and DCB RX parameters*/
2787 ixgbe_vmdq_dcb_configure(dev);
2791 dcb_config->vt_mode = false;
2792 config_dcb_rx = DCB_RX_CONFIG;
2793 /* Get dcb TX configuration parameters from rte_eth_conf */
2794 ixgbe_dcb_rx_config(dev,dcb_config);
2795 /*Configure general DCB RX parameters*/
2796 ixgbe_dcb_rx_hw_config(hw, dcb_config);
2799 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration\n");
2802 switch (dev->data->dev_conf.txmode.mq_mode) {
2803 case ETH_VMDQ_DCB_TX:
2804 dcb_config->vt_mode = true;
2805 config_dcb_tx = DCB_TX_CONFIG;
2806 /* get DCB and VT TX configuration parameters from rte_eth_conf */
2807 ixgbe_dcb_vt_tx_config(dev,dcb_config);
2808 /*Configure general VMDQ and DCB TX parameters*/
2809 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
2813 dcb_config->vt_mode = false;
2814 config_dcb_tx = DCB_RX_CONFIG;
2815 /*get DCB TX configuration parameters from rte_eth_conf*/
2816 ixgbe_dcb_tx_config(dev,dcb_config);
2817 /*Configure general DCB TX parameters*/
2818 ixgbe_dcb_tx_hw_config(hw, dcb_config);
2821 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration\n");
2825 nb_tcs = dcb_config->num_tcs.pfc_tcs;
2827 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2828 if(nb_tcs == ETH_4_TCS) {
2829 /* Avoid un-configured priority mapping to TC0 */
2831 uint8_t mask = 0xFF;
2832 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
2833 mask &= ~ (1 << map[i]);
2834 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
2835 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
2839 /* Re-configure 4 TCs BW */
2840 for (i = 0; i < nb_tcs; i++) {
2841 tc = &dcb_config->tc_config[i];
2842 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 100 / nb_tcs;
2843 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 100 / nb_tcs;
2845 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2846 tc = &dcb_config->tc_config[i];
2847 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
2848 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
2853 /* Set RX buffer size */
2854 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2855 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
2856 for (i = 0 ; i < nb_tcs; i++) {
2857 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2859 /* zero alloc all unused TCs */
2860 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2861 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
2865 /* Only support an equally distributed Tx packet buffer strategy. */
2866 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
2867 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
2868 for (i = 0; i < nb_tcs; i++) {
2869 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
2870 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
2872 /* Clear unused TCs, if any, to zero buffer size*/
2873 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2874 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
2875 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
2879 /*Calculates traffic class credits*/
2880 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2881 IXGBE_DCB_TX_CONFIG);
2882 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
2883 IXGBE_DCB_RX_CONFIG);
2886 /* Unpack CEE standard containers */
2887 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
2888 ixgbe_dcb_unpack_max_cee(dcb_config, max);
2889 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
2890 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
2891 /* Configure PG(ETS) RX */
2892 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
2896 /* Unpack CEE standard containers */
2897 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
2898 ixgbe_dcb_unpack_max_cee(dcb_config, max);
2899 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
2900 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
2901 /* Configure PG(ETS) TX */
2902 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
2905 /*Configure queue statistics registers*/
2906 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
2908 /* Check if the PFC is supported */
2909 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
2910 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
2911 for (i = 0; i < nb_tcs; i++) {
2913 * If the TC count is 8,and the default high_water is 48,
2914 * the low_water is 16 as default.
2916 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
2917 hw->fc.low_water[i] = pbsize / 4;
2918 /* Enable pfc for this TC */
2919 tc = &dcb_config->tc_config[i];
2920 tc->pfc = ixgbe_dcb_pfc_enabled;
2922 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
2923 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
2925 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
2932 * ixgbe_configure_dcb - Configure DCB Hardware
2933 * @dev: pointer to rte_eth_dev
2935 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
2937 struct ixgbe_dcb_config *dcb_cfg =
2938 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2940 PMD_INIT_FUNC_TRACE();
2941 /** Configure DCB hardware **/
2942 if(((dev->data->dev_conf.rxmode.mq_mode != ETH_RSS) &&
2943 (dev->data->nb_rx_queues == ETH_DCB_NUM_QUEUES))||
2944 ((dev->data->dev_conf.txmode.mq_mode != ETH_DCB_NONE) &&
2945 (dev->data->nb_tx_queues == ETH_DCB_NUM_QUEUES))) {
2946 ixgbe_dcb_hw_configure(dev,dcb_cfg);
2952 ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
2954 struct igb_rx_entry *rxe = rxq->sw_ring;
2958 /* Initialize software ring entries */
2959 for (i = 0; i < rxq->nb_rx_desc; i++) {
2960 volatile union ixgbe_adv_rx_desc *rxd;
2961 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
2963 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u\n",
2964 (unsigned) rxq->queue_id);
2968 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2969 rxd = &rxq->rx_ring[i];
2970 rxd->read.hdr_addr = dma_addr;
2971 rxd->read.pkt_addr = dma_addr;
2979 * Initializes Receive Unit.
2982 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
2984 struct ixgbe_hw *hw;
2985 struct igb_rx_queue *rxq;
2986 struct rte_pktmbuf_pool_private *mbp_priv;
2999 PMD_INIT_FUNC_TRACE();
3000 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3003 * Make sure receives are disabled while setting
3004 * up the RX context (registers, descriptor rings, etc.).
3006 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3007 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3009 /* Enable receipt of broadcasted frames */
3010 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3011 fctrl |= IXGBE_FCTRL_BAM;
3012 fctrl |= IXGBE_FCTRL_DPF;
3013 fctrl |= IXGBE_FCTRL_PMCF;
3014 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3017 * Configure CRC stripping, if any.
3019 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3020 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3021 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3023 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3026 * Configure jumbo frame support, if any.
3028 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3029 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3030 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3031 maxfrs &= 0x0000FFFF;
3032 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3033 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3035 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3037 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3039 /* Setup RX queues */
3040 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3041 rxq = dev->data->rx_queues[i];
3043 /* Allocate buffers for descriptor rings */
3044 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3049 * Reset crc_len in case it was changed after queue setup by a
3050 * call to configure.
3052 rxq->crc_len = (uint8_t)
3053 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3056 /* Setup the Base and Length of the Rx Descriptor Rings */
3057 bus_addr = rxq->rx_ring_phys_addr;
3058 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(i),
3059 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3060 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(i),
3061 (uint32_t)(bus_addr >> 32));
3062 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(i),
3063 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3064 IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
3065 IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
3067 /* Configure the SRRCTL register */
3068 #ifdef RTE_HEADER_SPLIT_ENABLE
3070 * Configure Header Split
3072 if (dev->data->dev_conf.rxmode.header_split) {
3073 if (hw->mac.type == ixgbe_mac_82599EB) {
3074 /* Must setup the PSRTYPE register */
3076 psrtype = IXGBE_PSRTYPE_TCPHDR |
3077 IXGBE_PSRTYPE_UDPHDR |
3078 IXGBE_PSRTYPE_IPV4HDR |
3079 IXGBE_PSRTYPE_IPV6HDR;
3080 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(i), psrtype);
3082 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3083 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3084 IXGBE_SRRCTL_BSIZEHDR_MASK);
3085 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3088 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3091 * Configure the RX buffer size in the BSIZEPACKET field of
3092 * the SRRCTL register of the queue.
3093 * The value is in 1 KB resolution. Valid values can be from
3096 mbp_priv = (struct rte_pktmbuf_pool_private *)
3097 ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
3098 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3099 RTE_PKTMBUF_HEADROOM);
3100 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3101 IXGBE_SRRCTL_BSIZEPKT_MASK);
3102 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(i), srrctl);
3104 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3105 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3106 if (dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size){
3107 dev->data->scattered_rx = 1;
3108 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3113 * Configure RSS if device configured with multiple RX queues.
3115 if (hw->mac.type == ixgbe_mac_82599EB) {
3116 if (dev->data->nb_rx_queues > 1)
3117 switch (dev->data->dev_conf.rxmode.mq_mode) {
3119 ixgbe_rss_configure(dev);
3123 ixgbe_vmdq_dcb_configure(dev);
3126 default: ixgbe_rss_disable(dev);
3129 ixgbe_rss_disable(dev);
3133 * Setup the Checksum Register.
3134 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3135 * Enable IP/L4 checkum computation by hardware if requested to do so.
3137 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3138 rxcsum |= IXGBE_RXCSUM_PCSD;
3139 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3140 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3142 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3144 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3146 if (hw->mac.type == ixgbe_mac_82599EB) {
3147 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3148 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3149 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3151 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3152 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3153 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3160 * Initializes Transmit Unit.
3163 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3165 struct ixgbe_hw *hw;
3166 struct igb_tx_queue *txq;
3173 PMD_INIT_FUNC_TRACE();
3174 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3176 /* Enable TX CRC (checksum offload requirement) */
3177 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3178 hlreg0 |= IXGBE_HLREG0_TXCRCEN;
3179 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3181 /* Setup the Base and Length of the Tx Descriptor Rings */
3182 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3183 txq = dev->data->tx_queues[i];
3185 bus_addr = txq->tx_ring_phys_addr;
3186 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(i),
3187 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3188 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(i),
3189 (uint32_t)(bus_addr >> 32));
3190 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(i),
3191 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3192 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3193 IXGBE_WRITE_REG(hw, IXGBE_TDH(i), 0);
3194 IXGBE_WRITE_REG(hw, IXGBE_TDT(i), 0);
3197 * Disable Tx Head Writeback RO bit, since this hoses
3198 * bookkeeping if things aren't delivered in order.
3200 switch (hw->mac.type) {
3201 case ixgbe_mac_82598EB:
3202 txctrl = IXGBE_READ_REG(hw,
3203 IXGBE_DCA_TXCTRL(i));
3204 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
3205 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i),
3209 case ixgbe_mac_82599EB:
3210 case ixgbe_mac_X540:
3212 txctrl = IXGBE_READ_REG(hw,
3213 IXGBE_DCA_TXCTRL_82599(i));
3214 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
3215 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i),
3221 if (hw->mac.type != ixgbe_mac_82598EB) {
3222 /* disable arbiter before setting MTQC */
3223 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3224 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3225 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3227 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
3229 /* re-enable arbiter */
3230 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3231 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3236 * Start Transmit and Receive Units.
3239 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3241 struct ixgbe_hw *hw;
3242 struct igb_tx_queue *txq;
3243 struct igb_rx_queue *rxq;
3251 PMD_INIT_FUNC_TRACE();
3252 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3254 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3255 txq = dev->data->tx_queues[i];
3256 /* Setup Transmit Threshold Registers */
3257 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
3258 txdctl |= txq->pthresh & 0x7F;
3259 txdctl |= ((txq->hthresh & 0x7F) << 8);
3260 txdctl |= ((txq->wthresh & 0x7F) << 16);
3261 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), txdctl);
3264 if (hw->mac.type != ixgbe_mac_82598EB) {
3265 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3266 dmatxctl |= IXGBE_DMATXCTL_TE;
3267 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3270 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3271 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
3272 txdctl |= IXGBE_TXDCTL_ENABLE;
3273 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), txdctl);
3275 /* Wait until TX Enable ready */
3276 if (hw->mac.type == ixgbe_mac_82599EB) {
3280 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
3281 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3283 PMD_INIT_LOG(ERR, "Could not enable "
3284 "Tx Queue %d\n", i);
3287 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3288 rxq = dev->data->rx_queues[i];
3289 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
3290 rxdctl |= IXGBE_RXDCTL_ENABLE;
3291 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), rxdctl);
3293 /* Wait until RX Enable ready */
3297 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
3298 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3300 PMD_INIT_LOG(ERR, "Could not enable "
3301 "Rx Queue %d\n", i);
3303 IXGBE_WRITE_REG(hw, IXGBE_RDT(i), rxq->nb_rx_desc - 1);
3306 /* Enable Receive engine */
3307 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3308 if (hw->mac.type == ixgbe_mac_82598EB)
3309 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3310 rxctrl |= IXGBE_RXCTRL_RXEN;
3311 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3316 * [VF] Initializes Receive Unit.
3319 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
3321 struct ixgbe_hw *hw;
3322 struct igb_rx_queue *rxq;
3323 struct rte_pktmbuf_pool_private *mbp_priv;
3330 PMD_INIT_FUNC_TRACE();
3331 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3333 /* Setup RX queues */
3334 dev->rx_pkt_burst = ixgbe_recv_pkts;
3335 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3336 rxq = dev->data->rx_queues[i];
3338 /* Allocate buffers for descriptor rings */
3339 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
3343 /* Setup the Base and Length of the Rx Descriptor Rings */
3344 bus_addr = rxq->rx_ring_phys_addr;
3346 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
3347 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3348 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
3349 (uint32_t)(bus_addr >> 32));
3350 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
3351 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3352 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
3353 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
3356 /* Configure the SRRCTL register */
3357 #ifdef RTE_HEADER_SPLIT_ENABLE
3359 * Configure Header Split
3361 if (dev->data->dev_conf.rxmode.header_split) {
3363 /* Must setup the PSRTYPE register */
3365 psrtype = IXGBE_PSRTYPE_TCPHDR |
3366 IXGBE_PSRTYPE_UDPHDR |
3367 IXGBE_PSRTYPE_IPV4HDR |
3368 IXGBE_PSRTYPE_IPV6HDR;
3370 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype);
3372 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3373 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3374 IXGBE_SRRCTL_BSIZEHDR_MASK);
3375 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3378 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3381 * Configure the RX buffer size in the BSIZEPACKET field of
3382 * the SRRCTL register of the queue.
3383 * The value is in 1 KB resolution. Valid values can be from
3386 mbp_priv = (struct rte_pktmbuf_pool_private *)
3387 ((char *)rxq->mb_pool + sizeof(struct rte_mempool));
3388 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3389 RTE_PKTMBUF_HEADROOM);
3390 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3391 IXGBE_SRRCTL_BSIZEPKT_MASK);
3394 * VF modification to write virtual function SRRCTL register
3396 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
3398 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3399 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3400 if (dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size){
3401 dev->data->scattered_rx = 1;
3402 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3409 * [VF] Initializes Transmit Unit.
3412 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
3414 struct ixgbe_hw *hw;
3415 struct igb_tx_queue *txq;
3420 PMD_INIT_FUNC_TRACE();
3421 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3423 /* Setup the Base and Length of the Tx Descriptor Rings */
3424 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3425 txq = dev->data->tx_queues[i];
3426 bus_addr = txq->tx_ring_phys_addr;
3427 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
3428 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3429 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
3430 (uint32_t)(bus_addr >> 32));
3431 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
3432 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3433 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3434 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
3435 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
3438 * Disable Tx Head Writeback RO bit, since this hoses
3439 * bookkeeping if things aren't delivered in order.
3441 txctrl = IXGBE_READ_REG(hw,
3442 IXGBE_VFDCA_TXCTRL(i));
3443 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
3444 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
3450 * [VF] Start Transmit and Receive Units.
3453 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
3455 struct ixgbe_hw *hw;
3456 struct igb_tx_queue *txq;
3457 struct igb_rx_queue *rxq;
3463 PMD_INIT_FUNC_TRACE();
3464 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3466 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3467 txq = dev->data->tx_queues[i];
3468 /* Setup Transmit Threshold Registers */
3469 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3470 txdctl |= txq->pthresh & 0x7F;
3471 txdctl |= ((txq->hthresh & 0x7F) << 8);
3472 txdctl |= ((txq->wthresh & 0x7F) << 16);
3473 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3476 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3478 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3479 txdctl |= IXGBE_TXDCTL_ENABLE;
3480 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
3483 /* Wait until TX Enable ready */
3486 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
3487 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
3489 PMD_INIT_LOG(ERR, "Could not enable "
3490 "Tx Queue %d\n", i);
3492 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3494 rxq = dev->data->rx_queues[i];
3496 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3497 rxdctl |= IXGBE_RXDCTL_ENABLE;
3498 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
3500 /* Wait until RX Enable ready */
3504 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
3505 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3507 PMD_INIT_LOG(ERR, "Could not enable "
3508 "Rx Queue %d\n", i);
3510 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);