4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 #include <rte_common.h>
39 #include <rte_memory.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
42 #include <rte_prefetch.h>
43 #include <rte_branch_prediction.h>
46 #include "rte_sched.h"
47 #include "rte_bitmap.h"
48 #include "rte_sched_common.h"
49 #include "rte_approx.h"
51 #ifdef __INTEL_COMPILER
52 #pragma warning(disable:2259) /* conversion may lose significant bits */
55 #ifndef RTE_SCHED_DEBUG
56 #define RTE_SCHED_DEBUG 0
59 #ifndef RTE_SCHED_OPTIMIZATIONS
60 #define RTE_SCHED_OPTIMIZATIONS 0
63 #if RTE_SCHED_OPTIMIZATIONS
64 #include <immintrin.h>
67 #define RTE_SCHED_ENQUEUE 1
69 #define RTE_SCHED_TS 1
71 #if RTE_SCHED_TS == 0 /* Infinite credits. Traffic shaping disabled. */
72 #define RTE_SCHED_TS_CREDITS_UPDATE 0
73 #define RTE_SCHED_TS_CREDITS_CHECK 0
74 #else /* Real Credits. Full traffic shaping implemented. */
75 #define RTE_SCHED_TS_CREDITS_UPDATE 1
76 #define RTE_SCHED_TS_CREDITS_CHECK 1
79 #ifndef RTE_SCHED_TB_RATE_CONFIG_ERR
80 #define RTE_SCHED_TB_RATE_CONFIG_ERR (1e-7)
83 #define RTE_SCHED_WRR 1
85 #ifndef RTE_SCHED_WRR_SHIFT
86 #define RTE_SCHED_WRR_SHIFT 3
89 #ifndef RTE_SCHED_PORT_N_GRINDERS
90 #define RTE_SCHED_PORT_N_GRINDERS 8
92 #if (RTE_SCHED_PORT_N_GRINDERS == 0) || (RTE_SCHED_PORT_N_GRINDERS & (RTE_SCHED_PORT_N_GRINDERS - 1))
93 #error Number of grinders must be non-zero and a power of 2
95 #if (RTE_SCHED_OPTIMIZATIONS && (RTE_SCHED_PORT_N_GRINDERS != 8))
96 #error Number of grinders must be 8 when RTE_SCHED_OPTIMIZATIONS is set
99 #define RTE_SCHED_GRINDER_PCACHE_SIZE (64 / RTE_SCHED_QUEUES_PER_PIPE)
101 #define RTE_SCHED_PIPE_INVALID UINT32_MAX
103 #define RTE_SCHED_BMP_POS_INVALID UINT32_MAX
105 struct rte_sched_subport {
106 /* Token bucket (TB) */
107 uint64_t tb_time; /* time of last update */
109 uint32_t tb_credits_per_period;
113 /* Traffic classes (TCs) */
114 uint64_t tc_time; /* time of next update */
115 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
116 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
119 /* TC oversubscription */
121 uint32_t tc_ov_wm_min;
122 uint32_t tc_ov_wm_max;
123 uint8_t tc_ov_period_id;
129 struct rte_sched_subport_stats stats;
132 struct rte_sched_pipe_profile {
133 /* Token bucket (TB) */
135 uint32_t tb_credits_per_period;
138 /* Pipe traffic classes */
140 uint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
141 uint8_t tc_ov_weight;
144 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_PIPE];
147 struct rte_sched_pipe {
148 /* Token bucket (TB) */
149 uint64_t tb_time; /* time of last update */
152 /* Pipe profile and flags */
155 /* Traffic classes (TCs) */
156 uint64_t tc_time; /* time of next update */
157 uint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
159 /* Weighted Round Robin (WRR) */
160 uint8_t wrr_tokens[RTE_SCHED_QUEUES_PER_PIPE];
162 /* TC oversubscription */
163 uint32_t tc_ov_credits;
164 uint8_t tc_ov_period_id;
166 } __rte_cache_aligned;
168 struct rte_sched_queue {
173 struct rte_sched_queue_extra {
174 struct rte_sched_queue_stats stats;
181 e_GRINDER_PREFETCH_PIPE = 0,
182 e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS,
183 e_GRINDER_PREFETCH_MBUF,
188 * Path through the scheduler hierarchy used by the scheduler enqueue
189 * operation to identify the destination queue for the current
190 * packet. Stored in the field pkt.hash.sched of struct rte_mbuf of
191 * each packet, typically written by the classification stage and read
192 * by scheduler enqueue.
194 struct rte_sched_port_hierarchy {
195 uint32_t queue:2; /**< Queue ID (0 .. 3) */
196 uint32_t traffic_class:2; /**< Traffic class ID (0 .. 3)*/
197 uint32_t pipe:20; /**< Pipe ID */
198 uint32_t subport:6; /**< Subport ID */
199 uint32_t color:2; /**< Color */
202 struct rte_sched_grinder {
204 uint16_t pcache_qmask[RTE_SCHED_GRINDER_PCACHE_SIZE];
205 uint32_t pcache_qindex[RTE_SCHED_GRINDER_PCACHE_SIZE];
210 enum grinder_state state;
213 struct rte_sched_subport *subport;
214 struct rte_sched_pipe *pipe;
215 struct rte_sched_pipe_profile *pipe_params;
218 uint8_t tccache_qmask[4];
219 uint32_t tccache_qindex[4];
225 struct rte_sched_queue *queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
226 struct rte_mbuf **qbase[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
227 uint32_t qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
231 struct rte_mbuf *pkt;
234 uint16_t wrr_tokens[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
235 uint16_t wrr_mask[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
236 uint8_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
239 struct rte_sched_port {
240 /* User parameters */
241 uint32_t n_subports_per_port;
242 uint32_t n_pipes_per_subport;
245 uint32_t frame_overhead;
246 uint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
247 uint32_t n_pipe_profiles;
248 uint32_t pipe_tc3_rate_max;
250 struct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][e_RTE_METER_COLORS];
254 uint64_t time_cpu_cycles; /* Current CPU time measured in CPU cyles */
255 uint64_t time_cpu_bytes; /* Current CPU time measured in bytes */
256 uint64_t time; /* Current NIC TX time measured in bytes */
257 double cycles_per_byte; /* CPU cycles per byte */
259 /* Scheduling loop detection */
261 uint32_t pipe_exhaustion;
264 struct rte_bitmap *bmp;
265 uint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] __rte_aligned_16;
268 struct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];
269 uint32_t busy_grinders;
270 struct rte_mbuf **pkts_out;
273 /* Queue base calculation */
274 uint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];
277 /* Large data structures */
278 struct rte_sched_subport *subport;
279 struct rte_sched_pipe *pipe;
280 struct rte_sched_queue *queue;
281 struct rte_sched_queue_extra *queue_extra;
282 struct rte_sched_pipe_profile *pipe_profiles;
284 struct rte_mbuf **queue_array;
285 uint8_t memory[0] __rte_cache_aligned;
286 } __rte_cache_aligned;
288 enum rte_sched_port_array {
289 e_RTE_SCHED_PORT_ARRAY_SUBPORT = 0,
290 e_RTE_SCHED_PORT_ARRAY_PIPE,
291 e_RTE_SCHED_PORT_ARRAY_QUEUE,
292 e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA,
293 e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES,
294 e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY,
295 e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY,
296 e_RTE_SCHED_PORT_ARRAY_TOTAL,
299 #ifdef RTE_SCHED_COLLECT_STATS
301 static inline uint32_t
302 rte_sched_port_queues_per_subport(struct rte_sched_port *port)
304 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport;
309 static inline uint32_t
310 rte_sched_port_queues_per_port(struct rte_sched_port *port)
312 return RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport * port->n_subports_per_port;
316 rte_sched_port_check_params(struct rte_sched_port_params *params)
320 if (params == NULL) {
325 if ((params->socket < 0) || (params->socket >= RTE_MAX_NUMA_NODES)) {
330 if (params->rate == 0) {
335 if (params->mtu == 0) {
339 /* n_subports_per_port: non-zero, power of 2 */
340 if ((params->n_subports_per_port == 0) || (!rte_is_power_of_2(params->n_subports_per_port))) {
344 /* n_pipes_per_subport: non-zero, power of 2 */
345 if ((params->n_pipes_per_subport == 0) || (!rte_is_power_of_2(params->n_pipes_per_subport))) {
349 /* qsize: non-zero, power of 2,
350 * no bigger than 32K (due to 16-bit read/write pointers) */
351 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
352 uint16_t qsize = params->qsize[i];
354 if ((qsize == 0) || (!rte_is_power_of_2(qsize))) {
359 /* pipe_profiles and n_pipe_profiles */
360 if ((params->pipe_profiles == NULL) ||
361 (params->n_pipe_profiles == 0) ||
362 (params->n_pipe_profiles > RTE_SCHED_PIPE_PROFILES_PER_PORT)) {
366 for (i = 0; i < params->n_pipe_profiles; i ++) {
367 struct rte_sched_pipe_params *p = params->pipe_profiles + i;
369 /* TB rate: non-zero, not greater than port rate */
370 if ((p->tb_rate == 0) || (p->tb_rate > params->rate)) {
374 /* TB size: non-zero */
375 if (p->tb_size == 0) {
379 /* TC rate: non-zero, less than pipe rate */
380 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
381 if ((p->tc_rate[j] == 0) || (p->tc_rate[j] > p->tb_rate)) {
386 /* TC period: non-zero */
387 if (p->tc_period == 0) {
391 #ifdef RTE_SCHED_SUBPORT_TC_OV
392 /* TC3 oversubscription weight: non-zero */
393 if (p->tc_ov_weight == 0) {
398 /* Queue WRR weights: non-zero */
399 for (j = 0; j < RTE_SCHED_QUEUES_PER_PIPE; j ++) {
400 if (p->wrr_weights[j] == 0) {
410 rte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sched_port_array array)
412 uint32_t n_subports_per_port = params->n_subports_per_port;
413 uint32_t n_pipes_per_subport = params->n_pipes_per_subport;
414 uint32_t n_pipes_per_port = n_pipes_per_subport * n_subports_per_port;
415 uint32_t n_queues_per_port = RTE_SCHED_QUEUES_PER_PIPE * n_pipes_per_subport * n_subports_per_port;
417 uint32_t size_subport = n_subports_per_port * sizeof(struct rte_sched_subport);
418 uint32_t size_pipe = n_pipes_per_port * sizeof(struct rte_sched_pipe);
419 uint32_t size_queue = n_queues_per_port * sizeof(struct rte_sched_queue);
420 uint32_t size_queue_extra = n_queues_per_port * sizeof(struct rte_sched_queue_extra);
421 uint32_t size_pipe_profiles = RTE_SCHED_PIPE_PROFILES_PER_PORT * sizeof(struct rte_sched_pipe_profile);
422 uint32_t size_bmp_array = rte_bitmap_get_memory_footprint(n_queues_per_port);
423 uint32_t size_per_pipe_queue_array, size_queue_array;
427 size_per_pipe_queue_array = 0;
428 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
429 size_per_pipe_queue_array += RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS * params->qsize[i] * sizeof(struct rte_mbuf *);
431 size_queue_array = n_pipes_per_port * size_per_pipe_queue_array;
435 if (array == e_RTE_SCHED_PORT_ARRAY_SUBPORT) return base;
436 base += RTE_CACHE_LINE_ROUNDUP(size_subport);
438 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE) return base;
439 base += RTE_CACHE_LINE_ROUNDUP(size_pipe);
441 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE) return base;
442 base += RTE_CACHE_LINE_ROUNDUP(size_queue);
444 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA) return base;
445 base += RTE_CACHE_LINE_ROUNDUP(size_queue_extra);
447 if (array == e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES) return base;
448 base += RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles);
450 if (array == e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY) return base;
451 base += RTE_CACHE_LINE_ROUNDUP(size_bmp_array);
453 if (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY) return base;
454 base += RTE_CACHE_LINE_ROUNDUP(size_queue_array);
460 rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)
462 uint32_t size0, size1;
465 status = rte_sched_port_check_params(params);
467 RTE_LOG(NOTICE, SCHED,
468 "Port scheduler params check failed (%d)\n", status);
473 size0 = sizeof(struct rte_sched_port);
474 size1 = rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_TOTAL);
476 return (size0 + size1);
480 rte_sched_port_config_qsize(struct rte_sched_port *port)
483 port->qsize_add[0] = 0;
484 port->qsize_add[1] = port->qsize_add[0] + port->qsize[0];
485 port->qsize_add[2] = port->qsize_add[1] + port->qsize[0];
486 port->qsize_add[3] = port->qsize_add[2] + port->qsize[0];
489 port->qsize_add[4] = port->qsize_add[3] + port->qsize[0];
490 port->qsize_add[5] = port->qsize_add[4] + port->qsize[1];
491 port->qsize_add[6] = port->qsize_add[5] + port->qsize[1];
492 port->qsize_add[7] = port->qsize_add[6] + port->qsize[1];
495 port->qsize_add[8] = port->qsize_add[7] + port->qsize[1];
496 port->qsize_add[9] = port->qsize_add[8] + port->qsize[2];
497 port->qsize_add[10] = port->qsize_add[9] + port->qsize[2];
498 port->qsize_add[11] = port->qsize_add[10] + port->qsize[2];
501 port->qsize_add[12] = port->qsize_add[11] + port->qsize[2];
502 port->qsize_add[13] = port->qsize_add[12] + port->qsize[3];
503 port->qsize_add[14] = port->qsize_add[13] + port->qsize[3];
504 port->qsize_add[15] = port->qsize_add[14] + port->qsize[3];
506 port->qsize_sum = port->qsize_add[15] + port->qsize[3];
510 rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)
512 struct rte_sched_pipe_profile *p = port->pipe_profiles + i;
514 RTE_LOG(DEBUG, SCHED, "Low level config for pipe profile %u:\n"
515 " Token bucket: period = %u, credits per period = %u, size = %u\n"
516 " Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
517 " Traffic class 3 oversubscription: weight = %hhu\n"
518 " WRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu]\n",
523 p->tb_credits_per_period,
526 /* Traffic classes */
528 p->tc_credits_per_period[0],
529 p->tc_credits_per_period[1],
530 p->tc_credits_per_period[2],
531 p->tc_credits_per_period[3],
533 /* Traffic class 3 oversubscription */
537 p->wrr_cost[ 0], p->wrr_cost[ 1], p->wrr_cost[ 2], p->wrr_cost[ 3],
538 p->wrr_cost[ 4], p->wrr_cost[ 5], p->wrr_cost[ 6], p->wrr_cost[ 7],
539 p->wrr_cost[ 8], p->wrr_cost[ 9], p->wrr_cost[10], p->wrr_cost[11],
540 p->wrr_cost[12], p->wrr_cost[13], p->wrr_cost[14], p->wrr_cost[15]);
543 static inline uint64_t
544 rte_sched_time_ms_to_bytes(uint32_t time_ms, uint32_t rate)
546 uint64_t time = time_ms;
547 time = (time * rate) / 1000;
553 rte_sched_port_config_pipe_profile_table(struct rte_sched_port *port, struct rte_sched_port_params *params)
557 for (i = 0; i < port->n_pipe_profiles; i ++) {
558 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
559 struct rte_sched_pipe_profile *dst = port->pipe_profiles + i;
562 if (src->tb_rate == params->rate) {
563 dst->tb_credits_per_period = 1;
566 double tb_rate = ((double) src->tb_rate) / ((double) params->rate);
567 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
569 rte_approx(tb_rate, d, &dst->tb_credits_per_period, &dst->tb_period);
571 dst->tb_size = src->tb_size;
573 /* Traffic Classes */
574 dst->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, params->rate);
575 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
576 dst->tc_credits_per_period[j] = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, src->tc_rate[j]);
578 #ifdef RTE_SCHED_SUBPORT_TC_OV
579 dst->tc_ov_weight = src->tc_ov_weight;
583 for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {
584 uint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];
585 uint32_t lcd, lcd1, lcd2;
588 qindex = j * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;
590 wrr_cost[0] = src->wrr_weights[qindex];
591 wrr_cost[1] = src->wrr_weights[qindex + 1];
592 wrr_cost[2] = src->wrr_weights[qindex + 2];
593 wrr_cost[3] = src->wrr_weights[qindex + 3];
595 lcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);
596 lcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);
597 lcd = rte_get_lcd(lcd1, lcd2);
599 wrr_cost[0] = lcd / wrr_cost[0];
600 wrr_cost[1] = lcd / wrr_cost[1];
601 wrr_cost[2] = lcd / wrr_cost[2];
602 wrr_cost[3] = lcd / wrr_cost[3];
604 dst->wrr_cost[qindex] = (uint8_t) wrr_cost[0];
605 dst->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1];
606 dst->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2];
607 dst->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3];
610 rte_sched_port_log_pipe_profile(port, i);
613 port->pipe_tc3_rate_max = 0;
614 for (i = 0; i < port->n_pipe_profiles; i ++) {
615 struct rte_sched_pipe_params *src = params->pipe_profiles + i;
616 uint32_t pipe_tc3_rate = src->tc_rate[3];
618 if (port->pipe_tc3_rate_max < pipe_tc3_rate) {
619 port->pipe_tc3_rate_max = pipe_tc3_rate;
624 struct rte_sched_port *
625 rte_sched_port_config(struct rte_sched_port_params *params)
627 struct rte_sched_port *port = NULL;
628 uint32_t mem_size, bmp_mem_size, n_queues_per_port, i;
630 /* Check user parameters. Determine the amount of memory to allocate */
631 mem_size = rte_sched_port_get_memory_footprint(params);
636 /* Allocate memory to store the data structures */
637 port = rte_zmalloc("qos_params", mem_size, RTE_CACHE_LINE_SIZE);
642 /* User parameters */
643 port->n_subports_per_port = params->n_subports_per_port;
644 port->n_pipes_per_subport = params->n_pipes_per_subport;
645 port->rate = params->rate;
646 port->mtu = params->mtu + params->frame_overhead;
647 port->frame_overhead = params->frame_overhead;
648 memcpy(port->qsize, params->qsize, sizeof(params->qsize));
649 port->n_pipe_profiles = params->n_pipe_profiles;
652 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
655 for (j = 0; j < e_RTE_METER_COLORS; j++) {
656 /* if min/max are both zero, then RED is disabled */
657 if ((params->red_params[i][j].min_th |
658 params->red_params[i][j].max_th) == 0) {
662 if (rte_red_config_init(&port->red_config[i][j],
663 params->red_params[i][j].wq_log2,
664 params->red_params[i][j].min_th,
665 params->red_params[i][j].max_th,
666 params->red_params[i][j].maxp_inv) != 0) {
674 port->time_cpu_cycles = rte_get_tsc_cycles();
675 port->time_cpu_bytes = 0;
677 port->cycles_per_byte = ((double) rte_get_tsc_hz()) / ((double) params->rate);
679 /* Scheduling loop detection */
680 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
681 port->pipe_exhaustion = 0;
684 port->busy_grinders = 0;
685 port->pkts_out = NULL;
686 port->n_pkts_out = 0;
688 /* Queue base calculation */
689 rte_sched_port_config_qsize(port);
691 /* Large data structures */
692 port->subport = (struct rte_sched_subport *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_SUBPORT));
693 port->pipe = (struct rte_sched_pipe *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE));
694 port->queue = (struct rte_sched_queue *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE));
695 port->queue_extra = (struct rte_sched_queue_extra *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA));
696 port->pipe_profiles = (struct rte_sched_pipe_profile *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES));
697 port->bmp_array = port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY);
698 port->queue_array = (struct rte_mbuf **) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY));
700 /* Pipe profile table */
701 rte_sched_port_config_pipe_profile_table(port, params);
704 n_queues_per_port = rte_sched_port_queues_per_port(port);
705 bmp_mem_size = rte_bitmap_get_memory_footprint(n_queues_per_port);
706 port->bmp = rte_bitmap_init(n_queues_per_port, port->bmp_array, bmp_mem_size);
707 if (port->bmp == NULL) {
708 RTE_LOG(ERR, SCHED, "Bitmap init error\n");
711 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {
712 port->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;
719 rte_sched_port_free(struct rte_sched_port *port)
721 /* Check user parameters */
726 rte_bitmap_free(port->bmp);
731 rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)
733 struct rte_sched_subport *s = port->subport + i;
735 RTE_LOG(DEBUG, SCHED, "Low level config for subport %u:\n"
736 " Token bucket: period = %u, credits per period = %u, size = %u\n"
737 " Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\n"
738 " Traffic class 3 oversubscription: wm min = %u, wm max = %u\n",
743 s->tb_credits_per_period,
746 /* Traffic classes */
748 s->tc_credits_per_period[0],
749 s->tc_credits_per_period[1],
750 s->tc_credits_per_period[2],
751 s->tc_credits_per_period[3],
753 /* Traffic class 3 oversubscription */
759 rte_sched_subport_config(struct rte_sched_port *port,
761 struct rte_sched_subport_params *params)
763 struct rte_sched_subport *s;
766 /* Check user parameters */
767 if ((port == NULL) ||
768 (subport_id >= port->n_subports_per_port) ||
773 if ((params->tb_rate == 0) || (params->tb_rate > port->rate)) {
777 if (params->tb_size == 0) {
781 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
782 if ((params->tc_rate[i] == 0) || (params->tc_rate[i] > params->tb_rate)) {
787 if (params->tc_period == 0) {
791 s = port->subport + subport_id;
793 /* Token Bucket (TB) */
794 if (params->tb_rate == port->rate) {
795 s->tb_credits_per_period = 1;
798 double tb_rate = ((double) params->tb_rate) / ((double) port->rate);
799 double d = RTE_SCHED_TB_RATE_CONFIG_ERR;
801 rte_approx(tb_rate, d, &s->tb_credits_per_period, &s->tb_period);
803 s->tb_size = params->tb_size;
804 s->tb_time = port->time;
805 s->tb_credits = s->tb_size / 2;
807 /* Traffic Classes (TCs) */
808 s->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, port->rate);
809 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
810 s->tc_credits_per_period[i] = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, params->tc_rate[i]);
812 s->tc_time = port->time + s->tc_period;
813 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
814 s->tc_credits[i] = s->tc_credits_per_period[i];
817 #ifdef RTE_SCHED_SUBPORT_TC_OV
818 /* TC oversubscription */
819 s->tc_ov_wm_min = port->mtu;
820 s->tc_ov_wm_max = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, port->pipe_tc3_rate_max);
821 s->tc_ov_wm = s->tc_ov_wm_max;
822 s->tc_ov_period_id = 0;
828 rte_sched_port_log_subport_config(port, subport_id);
834 rte_sched_pipe_config(struct rte_sched_port *port,
837 int32_t pipe_profile)
839 struct rte_sched_subport *s;
840 struct rte_sched_pipe *p;
841 struct rte_sched_pipe_profile *params;
842 uint32_t deactivate, profile, i;
844 /* Check user parameters */
845 profile = (uint32_t) pipe_profile;
846 deactivate = (pipe_profile < 0);
847 if ((port == NULL) ||
848 (subport_id >= port->n_subports_per_port) ||
849 (pipe_id >= port->n_pipes_per_subport) ||
850 ((!deactivate) && (profile >= port->n_pipe_profiles))) {
854 /* Check that subport configuration is valid */
855 s = port->subport + subport_id;
856 if (s->tb_period == 0) {
860 p = port->pipe + (subport_id * port->n_pipes_per_subport + pipe_id);
862 /* Handle the case when pipe already has a valid configuration */
864 params = port->pipe_profiles + p->profile;
866 #ifdef RTE_SCHED_SUBPORT_TC_OV
867 double subport_tc3_rate = ((double) s->tc_credits_per_period[3]) / ((double) s->tc_period);
868 double pipe_tc3_rate = ((double) params->tc_credits_per_period[3]) / ((double) params->tc_period);
869 uint32_t tc3_ov = s->tc_ov;
871 /* Unplug pipe from its subport */
872 s->tc_ov_n -= params->tc_ov_weight;
873 s->tc_ov_rate -= pipe_tc3_rate;
874 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
876 if (s->tc_ov != tc3_ov) {
877 RTE_LOG(DEBUG, SCHED,
878 "Subport %u TC3 oversubscription is OFF (%.4lf >= %.4lf)\n",
879 subport_id, subport_tc3_rate, s->tc_ov_rate);
884 memset(p, 0, sizeof(struct rte_sched_pipe));
891 /* Apply the new pipe configuration */
892 p->profile = profile;
893 params = port->pipe_profiles + p->profile;
895 /* Token Bucket (TB) */
896 p->tb_time = port->time;
897 p->tb_credits = params->tb_size / 2;
899 /* Traffic Classes (TCs) */
900 p->tc_time = port->time + params->tc_period;
901 for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {
902 p->tc_credits[i] = params->tc_credits_per_period[i];
905 #ifdef RTE_SCHED_SUBPORT_TC_OV
907 /* Subport TC3 oversubscription */
908 double subport_tc3_rate = ((double) s->tc_credits_per_period[3]) / ((double) s->tc_period);
909 double pipe_tc3_rate = ((double) params->tc_credits_per_period[3]) / ((double) params->tc_period);
910 uint32_t tc3_ov = s->tc_ov;
912 s->tc_ov_n += params->tc_ov_weight;
913 s->tc_ov_rate += pipe_tc3_rate;
914 s->tc_ov = s->tc_ov_rate > subport_tc3_rate;
916 if (s->tc_ov != tc3_ov) {
917 RTE_LOG(DEBUG, SCHED,
918 "Subport %u TC3 oversubscription is ON (%.4lf < %.4lf)\n",
919 subport_id, subport_tc3_rate, s->tc_ov_rate);
921 p->tc_ov_period_id = s->tc_ov_period_id;
922 p->tc_ov_credits = s->tc_ov_wm;
930 rte_sched_port_pkt_write(struct rte_mbuf *pkt,
931 uint32_t subport, uint32_t pipe, uint32_t traffic_class,
932 uint32_t queue, enum rte_meter_color color)
934 struct rte_sched_port_hierarchy *sched
935 = (struct rte_sched_port_hierarchy *) &pkt->hash.sched;
937 sched->color = (uint32_t) color;
938 sched->subport = subport;
940 sched->traffic_class = traffic_class;
941 sched->queue = queue;
945 rte_sched_port_pkt_read_tree_path(const struct rte_mbuf *pkt,
946 uint32_t *subport, uint32_t *pipe,
947 uint32_t *traffic_class, uint32_t *queue)
949 const struct rte_sched_port_hierarchy *sched
950 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
952 *subport = sched->subport;
954 *traffic_class = sched->traffic_class;
955 *queue = sched->queue;
960 rte_sched_port_pkt_read_color(const struct rte_mbuf *pkt)
962 const struct rte_sched_port_hierarchy *sched
963 = (const struct rte_sched_port_hierarchy *) &pkt->hash.sched;
965 return (enum rte_meter_color) sched->color;
969 rte_sched_subport_read_stats(struct rte_sched_port *port,
971 struct rte_sched_subport_stats *stats,
974 struct rte_sched_subport *s;
976 /* Check user parameters */
977 if ((port == NULL) ||
978 (subport_id >= port->n_subports_per_port) ||
983 s = port->subport + subport_id;
985 /* Copy subport stats and clear */
986 memcpy(stats, &s->stats, sizeof(struct rte_sched_subport_stats));
987 memset(&s->stats, 0, sizeof(struct rte_sched_subport_stats));
989 /* Subport TC ovesubscription status */
996 rte_sched_queue_read_stats(struct rte_sched_port *port,
998 struct rte_sched_queue_stats *stats,
1001 struct rte_sched_queue *q;
1002 struct rte_sched_queue_extra *qe;
1004 /* Check user parameters */
1005 if ((port == NULL) ||
1006 (queue_id >= rte_sched_port_queues_per_port(port)) ||
1011 q = port->queue + queue_id;
1012 qe = port->queue_extra + queue_id;
1014 /* Copy queue stats and clear */
1015 memcpy(stats, &qe->stats, sizeof(struct rte_sched_queue_stats));
1016 memset(&qe->stats, 0, sizeof(struct rte_sched_queue_stats));
1019 *qlen = q->qw - q->qr;
1024 static inline uint32_t
1025 rte_sched_port_qindex(struct rte_sched_port *port, uint32_t subport, uint32_t pipe, uint32_t traffic_class, uint32_t queue)
1029 result = subport * port->n_pipes_per_subport + pipe;
1030 result = result * RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE + traffic_class;
1031 result = result * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + queue;
1036 static inline struct rte_mbuf **
1037 rte_sched_port_qbase(struct rte_sched_port *port, uint32_t qindex)
1039 uint32_t pindex = qindex >> 4;
1040 uint32_t qpos = qindex & 0xF;
1042 return (port->queue_array + pindex * port->qsize_sum + port->qsize_add[qpos]);
1045 static inline uint16_t
1046 rte_sched_port_qsize(struct rte_sched_port *port, uint32_t qindex)
1048 uint32_t tc = (qindex >> 2) & 0x3;
1050 return port->qsize[tc];
1056 rte_sched_port_queue_is_empty(struct rte_sched_port *port, uint32_t qindex)
1058 struct rte_sched_queue *queue = port->queue + qindex;
1060 return (queue->qr == queue->qw);
1064 rte_sched_port_queue_is_full(struct rte_sched_port *port, uint32_t qindex)
1066 struct rte_sched_queue *queue = port->queue + qindex;
1067 uint16_t qsize = rte_sched_port_qsize(port, qindex);
1068 uint16_t qlen = queue->qw - queue->qr;
1070 return (qlen >= qsize);
1073 #endif /* RTE_SCHED_DEBUG */
1075 #ifdef RTE_SCHED_COLLECT_STATS
1078 rte_sched_port_update_subport_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1080 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1081 uint32_t tc_index = (qindex >> 2) & 0x3;
1082 uint32_t pkt_len = pkt->pkt_len;
1084 s->stats.n_pkts_tc[tc_index] += 1;
1085 s->stats.n_bytes_tc[tc_index] += pkt_len;
1089 rte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1091 struct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));
1092 uint32_t tc_index = (qindex >> 2) & 0x3;
1093 uint32_t pkt_len = pkt->pkt_len;
1095 s->stats.n_pkts_tc_dropped[tc_index] += 1;
1096 s->stats.n_bytes_tc_dropped[tc_index] += pkt_len;
1100 rte_sched_port_update_queue_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1102 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1103 uint32_t pkt_len = pkt->pkt_len;
1105 qe->stats.n_pkts += 1;
1106 qe->stats.n_bytes += pkt_len;
1110 rte_sched_port_update_queue_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)
1112 struct rte_sched_queue_extra *qe = port->queue_extra + qindex;
1113 uint32_t pkt_len = pkt->pkt_len;
1115 qe->stats.n_pkts_dropped += 1;
1116 qe->stats.n_bytes_dropped += pkt_len;
1119 #endif /* RTE_SCHED_COLLECT_STATS */
1121 #ifdef RTE_SCHED_RED
1124 rte_sched_port_red_drop(struct rte_sched_port *port, struct rte_mbuf *pkt, uint32_t qindex, uint16_t qlen)
1126 struct rte_sched_queue_extra *qe;
1127 struct rte_red_config *red_cfg;
1128 struct rte_red *red;
1130 enum rte_meter_color color;
1132 tc_index = (qindex >> 2) & 0x3;
1133 color = rte_sched_port_pkt_read_color(pkt);
1134 red_cfg = &port->red_config[tc_index][color];
1136 if ((red_cfg->min_th | red_cfg->max_th) == 0)
1139 qe = port->queue_extra + qindex;
1142 return rte_red_enqueue(red_cfg, red, qlen, port->time);
1146 rte_sched_port_set_queue_empty_timestamp(struct rte_sched_port *port, uint32_t qindex)
1148 struct rte_sched_queue_extra *qe;
1149 struct rte_red *red;
1151 qe = port->queue_extra + qindex;
1154 rte_red_mark_queue_empty(red, port->time);
1159 #define rte_sched_port_red_drop(port, pkt, qindex, qlen) 0
1161 #define rte_sched_port_set_queue_empty_timestamp(port, qindex)
1163 #endif /* RTE_SCHED_RED */
1168 debug_pipe_is_empty(struct rte_sched_port *port, uint32_t pindex)
1172 qindex = pindex << 4;
1174 for (i = 0; i < 16; i ++){
1175 uint32_t queue_empty = rte_sched_port_queue_is_empty(port, qindex + i);
1176 uint32_t bmp_bit_clear = (rte_bitmap_get(port->bmp, qindex + i) == 0);
1178 if (queue_empty != bmp_bit_clear){
1179 rte_panic("Queue status mismatch for queue %u of pipe %u\n", i, pindex);
1191 debug_check_queue_slab(struct rte_sched_port *port, uint32_t bmp_pos, uint64_t bmp_slab)
1197 rte_panic("Empty slab at position %u\n", bmp_pos);
1201 for (i = 0, mask = 1; i < 64; i ++, mask <<= 1) {
1202 if (mask & bmp_slab){
1203 if (rte_sched_port_queue_is_empty(port, bmp_pos + i)) {
1204 printf("Queue %u (slab offset %u) is empty\n", bmp_pos + i, i);
1211 rte_panic("Empty queues in slab 0x%" PRIx64 "starting at position %u\n",
1216 #endif /* RTE_SCHED_DEBUG */
1218 static inline uint32_t
1219 rte_sched_port_enqueue_qptrs_prefetch0(struct rte_sched_port *port, struct rte_mbuf *pkt)
1221 struct rte_sched_queue *q;
1222 #ifdef RTE_SCHED_COLLECT_STATS
1223 struct rte_sched_queue_extra *qe;
1225 uint32_t subport, pipe, traffic_class, queue, qindex;
1227 rte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);
1229 qindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);
1230 q = port->queue + qindex;
1232 #ifdef RTE_SCHED_COLLECT_STATS
1233 qe = port->queue_extra + qindex;
1241 rte_sched_port_enqueue_qwa_prefetch0(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase)
1243 struct rte_sched_queue *q;
1244 struct rte_mbuf **q_qw;
1247 q = port->queue + qindex;
1248 qsize = rte_sched_port_qsize(port, qindex);
1249 q_qw = qbase + (q->qw & (qsize - 1));
1251 rte_prefetch0(q_qw);
1252 rte_bitmap_prefetch0(port->bmp, qindex);
1256 rte_sched_port_enqueue_qwa(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase, struct rte_mbuf *pkt)
1258 struct rte_sched_queue *q;
1262 q = port->queue + qindex;
1263 qsize = rte_sched_port_qsize(port, qindex);
1264 qlen = q->qw - q->qr;
1266 /* Drop the packet (and update drop stats) when queue is full */
1267 if (unlikely(rte_sched_port_red_drop(port, pkt, qindex, qlen) || (qlen >= qsize))) {
1268 rte_pktmbuf_free(pkt);
1269 #ifdef RTE_SCHED_COLLECT_STATS
1270 rte_sched_port_update_subport_stats_on_drop(port, qindex, pkt);
1271 rte_sched_port_update_queue_stats_on_drop(port, qindex, pkt);
1276 /* Enqueue packet */
1277 qbase[q->qw & (qsize - 1)] = pkt;
1280 /* Activate queue in the port bitmap */
1281 rte_bitmap_set(port->bmp, qindex);
1284 #ifdef RTE_SCHED_COLLECT_STATS
1285 rte_sched_port_update_subport_stats(port, qindex, pkt);
1286 rte_sched_port_update_queue_stats(port, qindex, pkt);
1292 #if RTE_SCHED_ENQUEUE == 0
1295 rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
1301 for (i = 0; i < n_pkts; i ++) {
1302 struct rte_mbuf *pkt;
1303 struct rte_mbuf **q_base;
1304 uint32_t subport, pipe, traffic_class, queue, qindex;
1308 rte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);
1310 qindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);
1312 q_base = rte_sched_port_qbase(port, qindex);
1314 result += rte_sched_port_enqueue_qwa(port, qindex, q_base, pkt);
1323 * The enqueue function implements a 4-level pipeline with each stage processing
1324 * two different packets. The purpose of using a pipeline is to hide the latency
1325 * of prefetching the data structures. The naming convention is presented in the
1328 * p00 _______ p10 _______ p20 _______ p30 _______
1329 * ----->| |----->| |----->| |----->| |----->
1330 * | 0 | | 1 | | 2 | | 3 |
1331 * ----->|_______|----->|_______|----->|_______|----->|_______|----->
1336 rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
1338 struct rte_mbuf *pkt00, *pkt01, *pkt10, *pkt11, *pkt20, *pkt21, *pkt30, *pkt31, *pkt_last;
1339 struct rte_mbuf **q00_base, **q01_base, **q10_base, **q11_base, **q20_base, **q21_base, **q30_base, **q31_base, **q_last_base;
1340 uint32_t q00, q01, q10, q11, q20, q21, q30, q31, q_last;
1341 uint32_t r00, r01, r10, r11, r20, r21, r30, r31, r_last;
1346 /* Less then 6 input packets available, which is not enough to feed the pipeline */
1347 if (unlikely(n_pkts < 6)) {
1348 struct rte_mbuf **q_base[5];
1351 /* Prefetch the mbuf structure of each packet */
1352 for (i = 0; i < n_pkts; i ++) {
1353 rte_prefetch0(pkts[i]);
1356 /* Prefetch the queue structure for each queue */
1357 for (i = 0; i < n_pkts; i ++) {
1358 q[i] = rte_sched_port_enqueue_qptrs_prefetch0(port, pkts[i]);
1361 /* Prefetch the write pointer location of each queue */
1362 for (i = 0; i < n_pkts; i ++) {
1363 q_base[i] = rte_sched_port_qbase(port, q[i]);
1364 rte_sched_port_enqueue_qwa_prefetch0(port, q[i], q_base[i]);
1367 /* Write each packet to its queue */
1368 for (i = 0; i < n_pkts; i ++) {
1369 result += rte_sched_port_enqueue_qwa(port, q[i], q_base[i], pkts[i]);
1375 /* Feed the first 3 stages of the pipeline (6 packets needed) */
1378 rte_prefetch0(pkt20);
1379 rte_prefetch0(pkt21);
1383 rte_prefetch0(pkt10);
1384 rte_prefetch0(pkt11);
1386 q20 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt20);
1387 q21 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt21);
1391 rte_prefetch0(pkt00);
1392 rte_prefetch0(pkt01);
1394 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1395 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1397 q20_base = rte_sched_port_qbase(port, q20);
1398 q21_base = rte_sched_port_qbase(port, q21);
1399 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1400 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1402 /* Run the pipeline */
1403 for (i = 6; i < (n_pkts & (~1)); i += 2) {
1404 /* Propagate stage inputs */
1415 q30_base = q20_base;
1416 q31_base = q21_base;
1418 /* Stage 0: Get packets in */
1420 pkt01 = pkts[i + 1];
1421 rte_prefetch0(pkt00);
1422 rte_prefetch0(pkt01);
1424 /* Stage 1: Prefetch queue structure storing queue pointers */
1425 q10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);
1426 q11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);
1428 /* Stage 2: Prefetch queue write location */
1429 q20_base = rte_sched_port_qbase(port, q20);
1430 q21_base = rte_sched_port_qbase(port, q21);
1431 rte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);
1432 rte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);
1434 /* Stage 3: Write packet to queue and activate queue */
1435 r30 = rte_sched_port_enqueue_qwa(port, q30, q30_base, pkt30);
1436 r31 = rte_sched_port_enqueue_qwa(port, q31, q31_base, pkt31);
1437 result += r30 + r31;
1440 /* Drain the pipeline (exactly 6 packets). Handle the last packet in the case
1441 of an odd number of input packets. */
1442 pkt_last = pkts[n_pkts - 1];
1443 rte_prefetch0(pkt_last);
1445 q00 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt00);
1446 q01 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt01);
1448 q10_base = rte_sched_port_qbase(port, q10);
1449 q11_base = rte_sched_port_qbase(port, q11);
1450 rte_sched_port_enqueue_qwa_prefetch0(port, q10, q10_base);
1451 rte_sched_port_enqueue_qwa_prefetch0(port, q11, q11_base);
1453 r20 = rte_sched_port_enqueue_qwa(port, q20, q20_base, pkt20);
1454 r21 = rte_sched_port_enqueue_qwa(port, q21, q21_base, pkt21);
1455 result += r20 + r21;
1457 q_last = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt_last);
1459 q00_base = rte_sched_port_qbase(port, q00);
1460 q01_base = rte_sched_port_qbase(port, q01);
1461 rte_sched_port_enqueue_qwa_prefetch0(port, q00, q00_base);
1462 rte_sched_port_enqueue_qwa_prefetch0(port, q01, q01_base);
1464 r10 = rte_sched_port_enqueue_qwa(port, q10, q10_base, pkt10);
1465 r11 = rte_sched_port_enqueue_qwa(port, q11, q11_base, pkt11);
1466 result += r10 + r11;
1468 q_last_base = rte_sched_port_qbase(port, q_last);
1469 rte_sched_port_enqueue_qwa_prefetch0(port, q_last, q_last_base);
1471 r00 = rte_sched_port_enqueue_qwa(port, q00, q00_base, pkt00);
1472 r01 = rte_sched_port_enqueue_qwa(port, q01, q01_base, pkt01);
1473 result += r00 + r01;
1476 r_last = rte_sched_port_enqueue_qwa(port, q_last, q_last_base, pkt_last);
1483 #endif /* RTE_SCHED_ENQUEUE */
1485 #if RTE_SCHED_TS_CREDITS_UPDATE == 0
1487 #define grinder_credits_update(port, pos)
1489 #elif !defined(RTE_SCHED_SUBPORT_TC_OV)
1492 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1494 struct rte_sched_grinder *grinder = port->grinder + pos;
1495 struct rte_sched_subport *subport = grinder->subport;
1496 struct rte_sched_pipe *pipe = grinder->pipe;
1497 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1501 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1502 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1503 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1504 subport->tb_time += n_periods * subport->tb_period;
1507 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1508 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1509 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1510 pipe->tb_time += n_periods * params->tb_period;
1513 if (unlikely(port->time >= subport->tc_time)) {
1514 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1515 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1516 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1517 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1518 subport->tc_time = port->time + subport->tc_period;
1522 if (unlikely(port->time >= pipe->tc_time)) {
1523 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1524 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1525 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1526 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1527 pipe->tc_time = port->time + params->tc_period;
1533 static inline uint32_t
1534 grinder_tc_ov_credits_update(struct rte_sched_port *port, uint32_t pos)
1536 struct rte_sched_grinder *grinder = port->grinder + pos;
1537 struct rte_sched_subport *subport = grinder->subport;
1538 uint32_t tc_ov_consumption[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
1539 uint32_t tc_ov_consumption_max;
1540 uint32_t tc_ov_wm = subport->tc_ov_wm;
1542 if (subport->tc_ov == 0) {
1543 return subport->tc_ov_wm_max;
1546 tc_ov_consumption[0] = subport->tc_credits_per_period[0] - subport->tc_credits[0];
1547 tc_ov_consumption[1] = subport->tc_credits_per_period[1] - subport->tc_credits[1];
1548 tc_ov_consumption[2] = subport->tc_credits_per_period[2] - subport->tc_credits[2];
1549 tc_ov_consumption[3] = subport->tc_credits_per_period[3] - subport->tc_credits[3];
1551 tc_ov_consumption_max = subport->tc_credits_per_period[3] -
1552 (tc_ov_consumption[0] + tc_ov_consumption[1] + tc_ov_consumption[2]);
1554 if (tc_ov_consumption[3] > (tc_ov_consumption_max - port->mtu)) {
1555 tc_ov_wm -= tc_ov_wm >> 7;
1556 if (tc_ov_wm < subport->tc_ov_wm_min) {
1557 tc_ov_wm = subport->tc_ov_wm_min;
1562 tc_ov_wm += (tc_ov_wm >> 7) + 1;
1563 if (tc_ov_wm > subport->tc_ov_wm_max) {
1564 tc_ov_wm = subport->tc_ov_wm_max;
1570 grinder_credits_update(struct rte_sched_port *port, uint32_t pos)
1572 struct rte_sched_grinder *grinder = port->grinder + pos;
1573 struct rte_sched_subport *subport = grinder->subport;
1574 struct rte_sched_pipe *pipe = grinder->pipe;
1575 struct rte_sched_pipe_profile *params = grinder->pipe_params;
1579 n_periods = (port->time - subport->tb_time) / subport->tb_period;
1580 subport->tb_credits += n_periods * subport->tb_credits_per_period;
1581 subport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);
1582 subport->tb_time += n_periods * subport->tb_period;
1585 n_periods = (port->time - pipe->tb_time) / params->tb_period;
1586 pipe->tb_credits += n_periods * params->tb_credits_per_period;
1587 pipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);
1588 pipe->tb_time += n_periods * params->tb_period;
1591 if (unlikely(port->time >= subport->tc_time)) {
1592 subport->tc_ov_wm = grinder_tc_ov_credits_update(port, pos);
1594 subport->tc_credits[0] = subport->tc_credits_per_period[0];
1595 subport->tc_credits[1] = subport->tc_credits_per_period[1];
1596 subport->tc_credits[2] = subport->tc_credits_per_period[2];
1597 subport->tc_credits[3] = subport->tc_credits_per_period[3];
1599 subport->tc_time = port->time + subport->tc_period;
1600 subport->tc_ov_period_id ++;
1604 if (unlikely(port->time >= pipe->tc_time)) {
1605 pipe->tc_credits[0] = params->tc_credits_per_period[0];
1606 pipe->tc_credits[1] = params->tc_credits_per_period[1];
1607 pipe->tc_credits[2] = params->tc_credits_per_period[2];
1608 pipe->tc_credits[3] = params->tc_credits_per_period[3];
1609 pipe->tc_time = port->time + params->tc_period;
1612 /* Pipe TCs - Oversubscription */
1613 if (unlikely(pipe->tc_ov_period_id != subport->tc_ov_period_id)) {
1614 pipe->tc_ov_credits = subport->tc_ov_wm * params->tc_ov_weight;
1616 pipe->tc_ov_period_id = subport->tc_ov_period_id;
1620 #endif /* RTE_SCHED_TS_CREDITS_UPDATE, RTE_SCHED_SUBPORT_TC_OV */
1622 #if RTE_SCHED_TS_CREDITS_CHECK
1624 #ifndef RTE_SCHED_SUBPORT_TC_OV
1627 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1629 struct rte_sched_grinder *grinder = port->grinder + pos;
1630 struct rte_sched_subport *subport = grinder->subport;
1631 struct rte_sched_pipe *pipe = grinder->pipe;
1632 struct rte_mbuf *pkt = grinder->pkt;
1633 uint32_t tc_index = grinder->tc_index;
1634 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1635 uint32_t subport_tb_credits = subport->tb_credits;
1636 uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1637 uint32_t pipe_tb_credits = pipe->tb_credits;
1638 uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1641 /* Check queue credits */
1642 enough_credits = (pkt_len <= subport_tb_credits) &&
1643 (pkt_len <= subport_tc_credits) &&
1644 (pkt_len <= pipe_tb_credits) &&
1645 (pkt_len <= pipe_tc_credits);
1647 if (!enough_credits) {
1651 /* Update port credits */
1652 subport->tb_credits -= pkt_len;
1653 subport->tc_credits[tc_index] -= pkt_len;
1654 pipe->tb_credits -= pkt_len;
1655 pipe->tc_credits[tc_index] -= pkt_len;
1663 grinder_credits_check(struct rte_sched_port *port, uint32_t pos)
1665 struct rte_sched_grinder *grinder = port->grinder + pos;
1666 struct rte_sched_subport *subport = grinder->subport;
1667 struct rte_sched_pipe *pipe = grinder->pipe;
1668 struct rte_mbuf *pkt = grinder->pkt;
1669 uint32_t tc_index = grinder->tc_index;
1670 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1671 uint32_t subport_tb_credits = subport->tb_credits;
1672 uint32_t subport_tc_credits = subport->tc_credits[tc_index];
1673 uint32_t pipe_tb_credits = pipe->tb_credits;
1674 uint32_t pipe_tc_credits = pipe->tc_credits[tc_index];
1675 uint32_t pipe_tc_ov_mask1[] = {UINT32_MAX, UINT32_MAX, UINT32_MAX, pipe->tc_ov_credits};
1676 uint32_t pipe_tc_ov_mask2[] = {0, 0, 0, UINT32_MAX};
1677 uint32_t pipe_tc_ov_credits = pipe_tc_ov_mask1[tc_index];
1680 /* Check pipe and subport credits */
1681 enough_credits = (pkt_len <= subport_tb_credits) &&
1682 (pkt_len <= subport_tc_credits) &&
1683 (pkt_len <= pipe_tb_credits) &&
1684 (pkt_len <= pipe_tc_credits) &&
1685 (pkt_len <= pipe_tc_ov_credits);
1687 if (!enough_credits) {
1691 /* Update pipe and subport credits */
1692 subport->tb_credits -= pkt_len;
1693 subport->tc_credits[tc_index] -= pkt_len;
1694 pipe->tb_credits -= pkt_len;
1695 pipe->tc_credits[tc_index] -= pkt_len;
1696 pipe->tc_ov_credits -= pipe_tc_ov_mask2[tc_index] & pkt_len;
1701 #endif /* RTE_SCHED_SUBPORT_TC_OV */
1703 #endif /* RTE_SCHED_TS_CREDITS_CHECK */
1706 grinder_schedule(struct rte_sched_port *port, uint32_t pos)
1708 struct rte_sched_grinder *grinder = port->grinder + pos;
1709 struct rte_sched_queue *queue = grinder->queue[grinder->qpos];
1710 struct rte_mbuf *pkt = grinder->pkt;
1711 uint32_t pkt_len = pkt->pkt_len + port->frame_overhead;
1713 #if RTE_SCHED_TS_CREDITS_CHECK
1714 if (!grinder_credits_check(port, pos)) {
1719 /* Advance port time */
1720 port->time += pkt_len;
1723 port->pkts_out[port->n_pkts_out ++] = pkt;
1725 grinder->wrr_tokens[grinder->qpos] += pkt_len * grinder->wrr_cost[grinder->qpos];
1726 if (queue->qr == queue->qw) {
1727 uint32_t qindex = grinder->qindex[grinder->qpos];
1729 rte_bitmap_clear(port->bmp, qindex);
1730 grinder->qmask &= ~(1 << grinder->qpos);
1731 grinder->wrr_mask[grinder->qpos] = 0;
1732 rte_sched_port_set_queue_empty_timestamp(port, qindex);
1735 /* Reset pipe loop detection */
1736 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1737 grinder->productive = 1;
1742 #if RTE_SCHED_OPTIMIZATIONS
1745 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1747 __m128i index = _mm_set1_epi32 (base_pipe);
1748 __m128i pipes = _mm_load_si128((__m128i *)port->grinder_base_bmp_pos);
1749 __m128i res = _mm_cmpeq_epi32(pipes, index);
1750 pipes = _mm_load_si128((__m128i *)(port->grinder_base_bmp_pos + 4));
1751 pipes = _mm_cmpeq_epi32(pipes, index);
1752 res = _mm_or_si128(res, pipes);
1754 if (_mm_testz_si128(res, res))
1763 grinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)
1767 for (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {
1768 if (port->grinder_base_bmp_pos[i] == base_pipe) {
1776 #endif /* RTE_SCHED_OPTIMIZATIONS */
1779 grinder_pcache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t bmp_pos, uint64_t bmp_slab)
1781 struct rte_sched_grinder *grinder = port->grinder + pos;
1784 grinder->pcache_w = 0;
1785 grinder->pcache_r = 0;
1787 w[0] = (uint16_t) bmp_slab;
1788 w[1] = (uint16_t) (bmp_slab >> 16);
1789 w[2] = (uint16_t) (bmp_slab >> 32);
1790 w[3] = (uint16_t) (bmp_slab >> 48);
1792 grinder->pcache_qmask[grinder->pcache_w] = w[0];
1793 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos;
1794 grinder->pcache_w += (w[0] != 0);
1796 grinder->pcache_qmask[grinder->pcache_w] = w[1];
1797 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 16;
1798 grinder->pcache_w += (w[1] != 0);
1800 grinder->pcache_qmask[grinder->pcache_w] = w[2];
1801 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 32;
1802 grinder->pcache_w += (w[2] != 0);
1804 grinder->pcache_qmask[grinder->pcache_w] = w[3];
1805 grinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 48;
1806 grinder->pcache_w += (w[3] != 0);
1810 grinder_tccache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t qindex, uint16_t qmask)
1812 struct rte_sched_grinder *grinder = port->grinder + pos;
1815 grinder->tccache_w = 0;
1816 grinder->tccache_r = 0;
1818 b[0] = (uint8_t) (qmask & 0xF);
1819 b[1] = (uint8_t) ((qmask >> 4) & 0xF);
1820 b[2] = (uint8_t) ((qmask >> 8) & 0xF);
1821 b[3] = (uint8_t) ((qmask >> 12) & 0xF);
1823 grinder->tccache_qmask[grinder->tccache_w] = b[0];
1824 grinder->tccache_qindex[grinder->tccache_w] = qindex;
1825 grinder->tccache_w += (b[0] != 0);
1827 grinder->tccache_qmask[grinder->tccache_w] = b[1];
1828 grinder->tccache_qindex[grinder->tccache_w] = qindex + 4;
1829 grinder->tccache_w += (b[1] != 0);
1831 grinder->tccache_qmask[grinder->tccache_w] = b[2];
1832 grinder->tccache_qindex[grinder->tccache_w] = qindex + 8;
1833 grinder->tccache_w += (b[2] != 0);
1835 grinder->tccache_qmask[grinder->tccache_w] = b[3];
1836 grinder->tccache_qindex[grinder->tccache_w] = qindex + 12;
1837 grinder->tccache_w += (b[3] != 0);
1841 grinder_next_tc(struct rte_sched_port *port, uint32_t pos)
1843 struct rte_sched_grinder *grinder = port->grinder + pos;
1844 struct rte_mbuf **qbase;
1848 if (grinder->tccache_r == grinder->tccache_w) {
1852 qindex = grinder->tccache_qindex[grinder->tccache_r];
1853 qbase = rte_sched_port_qbase(port, qindex);
1854 qsize = rte_sched_port_qsize(port, qindex);
1856 grinder->tc_index = (qindex >> 2) & 0x3;
1857 grinder->qmask = grinder->tccache_qmask[grinder->tccache_r];
1858 grinder->qsize = qsize;
1860 grinder->qindex[0] = qindex;
1861 grinder->qindex[1] = qindex + 1;
1862 grinder->qindex[2] = qindex + 2;
1863 grinder->qindex[3] = qindex + 3;
1865 grinder->queue[0] = port->queue + qindex;
1866 grinder->queue[1] = port->queue + qindex + 1;
1867 grinder->queue[2] = port->queue + qindex + 2;
1868 grinder->queue[3] = port->queue + qindex + 3;
1870 grinder->qbase[0] = qbase;
1871 grinder->qbase[1] = qbase + qsize;
1872 grinder->qbase[2] = qbase + 2 * qsize;
1873 grinder->qbase[3] = qbase + 3 * qsize;
1875 grinder->tccache_r ++;
1880 grinder_next_pipe(struct rte_sched_port *port, uint32_t pos)
1882 struct rte_sched_grinder *grinder = port->grinder + pos;
1883 uint32_t pipe_qindex;
1884 uint16_t pipe_qmask;
1886 if (grinder->pcache_r < grinder->pcache_w) {
1887 pipe_qmask = grinder->pcache_qmask[grinder->pcache_r];
1888 pipe_qindex = grinder->pcache_qindex[grinder->pcache_r];
1889 grinder->pcache_r ++;
1891 uint64_t bmp_slab = 0;
1892 uint32_t bmp_pos = 0;
1894 /* Get another non-empty pipe group */
1895 if (unlikely(rte_bitmap_scan(port->bmp, &bmp_pos, &bmp_slab) <= 0)) {
1900 debug_check_queue_slab(port, bmp_pos, bmp_slab);
1903 /* Return if pipe group already in one of the other grinders */
1904 port->grinder_base_bmp_pos[pos] = RTE_SCHED_BMP_POS_INVALID;
1905 if (unlikely(grinder_pipe_exists(port, bmp_pos))) {
1908 port->grinder_base_bmp_pos[pos] = bmp_pos;
1910 /* Install new pipe group into grinder's pipe cache */
1911 grinder_pcache_populate(port, pos, bmp_pos, bmp_slab);
1913 pipe_qmask = grinder->pcache_qmask[0];
1914 pipe_qindex = grinder->pcache_qindex[0];
1915 grinder->pcache_r = 1;
1918 /* Install new pipe in the grinder */
1919 grinder->pindex = pipe_qindex >> 4;
1920 grinder->subport = port->subport + (grinder->pindex / port->n_pipes_per_subport);
1921 grinder->pipe = port->pipe + grinder->pindex;
1922 grinder->pipe_params = NULL; /* to be set after the pipe structure is prefetched */
1923 grinder->productive = 0;
1925 grinder_tccache_populate(port, pos, pipe_qindex, pipe_qmask);
1926 grinder_next_tc(port, pos);
1928 /* Check for pipe exhaustion */
1929 if (grinder->pindex == port->pipe_loop) {
1930 port->pipe_exhaustion = 1;
1931 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
1937 #if RTE_SCHED_WRR == 0
1939 #define grinder_wrr_load(a,b)
1941 #define grinder_wrr_store(a,b)
1944 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
1946 struct rte_sched_grinder *grinder = port->grinder + pos;
1947 uint64_t slab = grinder->qmask;
1949 if (rte_bsf64(slab, &grinder->qpos) == 0) {
1950 rte_panic("grinder wrr\n");
1954 #elif RTE_SCHED_WRR == 1
1957 grinder_wrr_load(struct rte_sched_port *port, uint32_t pos)
1959 struct rte_sched_grinder *grinder = port->grinder + pos;
1960 struct rte_sched_pipe *pipe = grinder->pipe;
1961 struct rte_sched_pipe_profile *pipe_params = grinder->pipe_params;
1962 uint32_t tc_index = grinder->tc_index;
1963 uint32_t qmask = grinder->qmask;
1966 qindex = tc_index * 4;
1968 grinder->wrr_tokens[0] = ((uint16_t) pipe->wrr_tokens[qindex]) << RTE_SCHED_WRR_SHIFT;
1969 grinder->wrr_tokens[1] = ((uint16_t) pipe->wrr_tokens[qindex + 1]) << RTE_SCHED_WRR_SHIFT;
1970 grinder->wrr_tokens[2] = ((uint16_t) pipe->wrr_tokens[qindex + 2]) << RTE_SCHED_WRR_SHIFT;
1971 grinder->wrr_tokens[3] = ((uint16_t) pipe->wrr_tokens[qindex + 3]) << RTE_SCHED_WRR_SHIFT;
1973 grinder->wrr_mask[0] = (qmask & 0x1) * 0xFFFF;
1974 grinder->wrr_mask[1] = ((qmask >> 1) & 0x1) * 0xFFFF;
1975 grinder->wrr_mask[2] = ((qmask >> 2) & 0x1) * 0xFFFF;
1976 grinder->wrr_mask[3] = ((qmask >> 3) & 0x1) * 0xFFFF;
1978 grinder->wrr_cost[0] = pipe_params->wrr_cost[qindex];
1979 grinder->wrr_cost[1] = pipe_params->wrr_cost[qindex + 1];
1980 grinder->wrr_cost[2] = pipe_params->wrr_cost[qindex + 2];
1981 grinder->wrr_cost[3] = pipe_params->wrr_cost[qindex + 3];
1985 grinder_wrr_store(struct rte_sched_port *port, uint32_t pos)
1987 struct rte_sched_grinder *grinder = port->grinder + pos;
1988 struct rte_sched_pipe *pipe = grinder->pipe;
1989 uint32_t tc_index = grinder->tc_index;
1992 qindex = tc_index * 4;
1994 pipe->wrr_tokens[qindex] = (uint8_t) ((grinder->wrr_tokens[0] & grinder->wrr_mask[0]) >> RTE_SCHED_WRR_SHIFT);
1995 pipe->wrr_tokens[qindex + 1] = (uint8_t) ((grinder->wrr_tokens[1] & grinder->wrr_mask[1]) >> RTE_SCHED_WRR_SHIFT);
1996 pipe->wrr_tokens[qindex + 2] = (uint8_t) ((grinder->wrr_tokens[2] & grinder->wrr_mask[2]) >> RTE_SCHED_WRR_SHIFT);
1997 pipe->wrr_tokens[qindex + 3] = (uint8_t) ((grinder->wrr_tokens[3] & grinder->wrr_mask[3]) >> RTE_SCHED_WRR_SHIFT);
2001 grinder_wrr(struct rte_sched_port *port, uint32_t pos)
2003 struct rte_sched_grinder *grinder = port->grinder + pos;
2004 uint16_t wrr_tokens_min;
2006 grinder->wrr_tokens[0] |= ~grinder->wrr_mask[0];
2007 grinder->wrr_tokens[1] |= ~grinder->wrr_mask[1];
2008 grinder->wrr_tokens[2] |= ~grinder->wrr_mask[2];
2009 grinder->wrr_tokens[3] |= ~grinder->wrr_mask[3];
2011 grinder->qpos = rte_min_pos_4_u16(grinder->wrr_tokens);
2012 wrr_tokens_min = grinder->wrr_tokens[grinder->qpos];
2014 grinder->wrr_tokens[0] -= wrr_tokens_min;
2015 grinder->wrr_tokens[1] -= wrr_tokens_min;
2016 grinder->wrr_tokens[2] -= wrr_tokens_min;
2017 grinder->wrr_tokens[3] -= wrr_tokens_min;
2022 #error Invalid value for RTE_SCHED_WRR
2024 #endif /* RTE_SCHED_WRR */
2026 #define grinder_evict(port, pos)
2029 grinder_prefetch_pipe(struct rte_sched_port *port, uint32_t pos)
2031 struct rte_sched_grinder *grinder = port->grinder + pos;
2033 rte_prefetch0(grinder->pipe);
2034 rte_prefetch0(grinder->queue[0]);
2038 grinder_prefetch_tc_queue_arrays(struct rte_sched_port *port, uint32_t pos)
2040 struct rte_sched_grinder *grinder = port->grinder + pos;
2041 uint16_t qsize, qr[4];
2043 qsize = grinder->qsize;
2044 qr[0] = grinder->queue[0]->qr & (qsize - 1);
2045 qr[1] = grinder->queue[1]->qr & (qsize - 1);
2046 qr[2] = grinder->queue[2]->qr & (qsize - 1);
2047 qr[3] = grinder->queue[3]->qr & (qsize - 1);
2049 rte_prefetch0(grinder->qbase[0] + qr[0]);
2050 rte_prefetch0(grinder->qbase[1] + qr[1]);
2052 grinder_wrr_load(port, pos);
2053 grinder_wrr(port, pos);
2055 rte_prefetch0(grinder->qbase[2] + qr[2]);
2056 rte_prefetch0(grinder->qbase[3] + qr[3]);
2060 grinder_prefetch_mbuf(struct rte_sched_port *port, uint32_t pos)
2062 struct rte_sched_grinder *grinder = port->grinder + pos;
2063 uint32_t qpos = grinder->qpos;
2064 struct rte_mbuf **qbase = grinder->qbase[qpos];
2065 uint16_t qsize = grinder->qsize;
2066 uint16_t qr = grinder->queue[qpos]->qr & (qsize - 1);
2068 grinder->pkt = qbase[qr];
2069 rte_prefetch0(grinder->pkt);
2071 if (unlikely((qr & 0x7) == 7)) {
2072 uint16_t qr_next = (grinder->queue[qpos]->qr + 1) & (qsize - 1);
2074 rte_prefetch0(qbase + qr_next);
2078 static inline uint32_t
2079 grinder_handle(struct rte_sched_port *port, uint32_t pos)
2081 struct rte_sched_grinder *grinder = port->grinder + pos;
2083 switch (grinder->state) {
2084 case e_GRINDER_PREFETCH_PIPE:
2086 if (grinder_next_pipe(port, pos)) {
2087 grinder_prefetch_pipe(port, pos);
2088 port->busy_grinders ++;
2090 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2097 case e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS:
2099 struct rte_sched_pipe *pipe = grinder->pipe;
2101 grinder->pipe_params = port->pipe_profiles + pipe->profile;
2102 grinder_prefetch_tc_queue_arrays(port, pos);
2103 grinder_credits_update(port, pos);
2105 grinder->state = e_GRINDER_PREFETCH_MBUF;
2109 case e_GRINDER_PREFETCH_MBUF:
2111 grinder_prefetch_mbuf(port, pos);
2113 grinder->state = e_GRINDER_READ_MBUF;
2117 case e_GRINDER_READ_MBUF:
2119 uint32_t result = 0;
2121 result = grinder_schedule(port, pos);
2123 /* Look for next packet within the same TC */
2124 if (result && grinder->qmask) {
2125 grinder_wrr(port, pos);
2126 grinder_prefetch_mbuf(port, pos);
2130 grinder_wrr_store(port, pos);
2132 /* Look for another active TC within same pipe */
2133 if (grinder_next_tc(port, pos)) {
2134 grinder_prefetch_tc_queue_arrays(port, pos);
2136 grinder->state = e_GRINDER_PREFETCH_MBUF;
2139 if ((grinder->productive == 0) && (port->pipe_loop == RTE_SCHED_PIPE_INVALID)) {
2140 port->pipe_loop = grinder->pindex;
2142 grinder_evict(port, pos);
2144 /* Look for another active pipe */
2145 if (grinder_next_pipe(port, pos)) {
2146 grinder_prefetch_pipe(port, pos);
2148 grinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;
2152 /* No active pipe found */
2153 port->busy_grinders --;
2155 grinder->state = e_GRINDER_PREFETCH_PIPE;
2160 rte_panic("Algorithmic error (invalid state)\n");
2166 rte_sched_port_time_resync(struct rte_sched_port *port)
2168 uint64_t cycles = rte_get_tsc_cycles();
2169 uint64_t cycles_diff = cycles - port->time_cpu_cycles;
2170 double bytes_diff = ((double) cycles_diff) / port->cycles_per_byte;
2172 /* Advance port time */
2173 port->time_cpu_cycles = cycles;
2174 port->time_cpu_bytes += (uint64_t) bytes_diff;
2175 if (port->time < port->time_cpu_bytes) {
2176 port->time = port->time_cpu_bytes;
2179 /* Reset pipe loop detection */
2180 port->pipe_loop = RTE_SCHED_PIPE_INVALID;
2184 rte_sched_port_exceptions(struct rte_sched_port *port, int second_pass)
2188 /* Check if any exception flag is set */
2189 exceptions = (second_pass && port->busy_grinders == 0) ||
2190 (port->pipe_exhaustion == 1);
2192 /* Clear exception flags */
2193 port->pipe_exhaustion = 0;
2199 rte_sched_port_dequeue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)
2203 port->pkts_out = pkts;
2204 port->n_pkts_out = 0;
2206 rte_sched_port_time_resync(port);
2208 /* Take each queue in the grinder one step further */
2209 for (i = 0, count = 0; ; i ++) {
2210 count += grinder_handle(port, i & (RTE_SCHED_PORT_N_GRINDERS - 1));
2211 if ((count == n_pkts) ||
2212 rte_sched_port_exceptions(port, i >= RTE_SCHED_PORT_N_GRINDERS)) {