e1000/base: fix K1 beacon for 82579
authorJijiang Liu <jijiang.liu@intel.com>
Wed, 18 Jun 2014 11:57:39 +0000 (13:57 +0200)
committerThomas Monjalon <thomas.monjalon@6wind.com>
Wed, 18 Jun 2014 21:30:29 +0000 (23:30 +0200)
Signed-off-by: Jijiang Liu <jijiang.liu@intel.com>
Acked-by: Helin Zhang <helin.zhang@intel.com>
Tested-by: Waterman Cao <waterman.cao@intel.com>
[Thomas: split code drop]

lib/librte_pmd_e1000/e1000/e1000_ich8lan.c
lib/librte_pmd_e1000/e1000/e1000_ich8lan.h
lib/librte_pmd_e1000/e1000/e1000_phy.h

index caa7f8e..22cc01d 100644 (file)
@@ -2696,55 +2696,47 @@ release:
  *  e1000_k1_gig_workaround_lv - K1 Si workaround
  *  @hw:   pointer to the HW structure
  *
- *  Workaround to set the K1 beacon duration for 82579 parts
+ *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
+ *  Disable K1 for 1000 and 100 speeds
  **/
 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
 {
        s32 ret_val = E1000_SUCCESS;
        u16 status_reg = 0;
-       u32 mac_reg;
-       u16 phy_reg;
 
        DEBUGFUNC("e1000_k1_workaround_lv");
 
        if (hw->mac.type != e1000_pch2lan)
                return E1000_SUCCESS;
 
-       /* Set K1 beacon duration based on 1Gbps speed or otherwise */
+       /* Set K1 beacon duration based on 10Mbs speed */
        ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
        if (ret_val)
                return ret_val;
 
        if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
            == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
-               mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
-               mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
-
-               ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
-               if (ret_val)
-                       return ret_val;
-
-               if (status_reg & HV_M_STATUS_SPEED_1000) {
+               if (status_reg &
+                   (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
                        u16 pm_phy_reg;
 
-                       mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
-                       phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
-                       /* LV 1G Packet drop issue wa  */
+                       /* LV 1G/100 Packet drop issue wa  */
                        ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
                                                       &pm_phy_reg);
                        if (ret_val)
                                return ret_val;
-                       pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
+                       pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
                        ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
                                                        pm_phy_reg);
                        if (ret_val)
                                return ret_val;
                } else {
+                       u32 mac_reg;
+                       mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
+                       mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
                        mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
-                       phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
+                       E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
                }
-               E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
-               ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
        }
 
        return ret_val;
index 6b6e1c6..44c2cd2 100644 (file)
@@ -249,7 +249,6 @@ POSSIBILITY OF SUCH DAMAGE.
 #define I82579_LPI_CTRL_100_ENABLE             0x2000
 #define I82579_LPI_CTRL_1000_ENABLE            0x4000
 #define I82579_LPI_CTRL_ENABLE_MASK            0x6000
-#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT   0x80
 
 /* 82579 DFT Control */
 #define I82579_DFT_CTRL                        PHY_REG(769, 20)
index 43a3d5d..072d559 100644 (file)
@@ -225,6 +225,7 @@ bool e1000_is_mphy_ready(struct e1000_hw *hw);
 #define HV_M_STATUS_AUTONEG_COMPLETE   0x1000
 #define HV_M_STATUS_SPEED_MASK         0x0300
 #define HV_M_STATUS_SPEED_1000         0x0200
+#define HV_M_STATUS_SPEED_100          0x0100
 #define HV_M_STATUS_LINK_UP            0x0040
 
 #define IGP01E1000_PHY_PCS_INIT_REG    0x00B4