net/mlx5: don't map doorbell register to write combining
authorShahaf Shuler <shahafs@mellanox.com>
Sun, 27 Aug 2017 06:47:09 +0000 (09:47 +0300)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 6 Oct 2017 00:49:47 +0000 (02:49 +0200)
By default, Verbs maps the doorbell register to write combining.
Working with write combining is useful for drivers which use blue flame
for the doorbell write.

Since mlx5 PMD uses only doorbells and write combining mapping requires
an extra memory barrier to flush the doorbell after its write, setting
the mapping to un-cached by default.

Such change is expected to reduce the max and average round trip latency.

Signed-off-by: Shahaf Shuler <shahafs@mellanox.com>
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Signed-off-by: Alexander Solganik <solganik@gmail.com>
Signed-off-by: Sagi Grimberg <sagi@grimberg.me>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
drivers/net/mlx5/mlx5.c

index bd66a7c..50f4ba7 100644 (file)
@@ -884,6 +884,8 @@ rte_mlx5_pmd_init(void)
         * using this PMD, which is not supported in forked processes.
         */
        setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
+       /* Don't map UAR to WC if BlueFlame is not used.*/
+       setenv("MLX5_SHUT_UP_BF", "1", 1);
        ibv_fork_init();
        rte_pci_register(&mlx5_driver);
 }