net/i40e/base: add error state for NVM update state machine
authorJingjing Wu <jingjing.wu@intel.com>
Sat, 10 Dec 2016 11:24:48 +0000 (19:24 +0800)
committerFerruh Yigit <ferruh.yigit@intel.com>
Tue, 17 Jan 2017 18:39:27 +0000 (19:39 +0100)
This patch adds I40E_NVMUPD_STATE_ERROR state for NVM update.
Without this patch driver has no possibility to return NVM image write
failure.This state is being set when ARQ rises error.
arq_last_status is also updated every time when ARQ event comes,
not only on error cases.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
drivers/net/i40e/base/i40e_adminq.c
drivers/net/i40e/base/i40e_nvm.c
drivers/net/i40e/base/i40e_type.h

index 0d3a83f..5bdf3f7 100644 (file)
@@ -1077,11 +1077,11 @@ enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
        desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
        desc_idx = ntc;
 
+       hw->aq.arq_last_status =
+               (enum i40e_admin_queue_err)LE16_TO_CPU(desc->retval);
        flags = LE16_TO_CPU(desc->flags);
        if (flags & I40E_AQ_FLAG_ERR) {
                ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
-               hw->aq.arq_last_status =
-                       (enum i40e_admin_queue_err)LE16_TO_CPU(desc->retval);
                i40e_debug(hw,
                           I40E_DEBUG_AQ_MESSAGE,
                           "AQRX: Event received with error 0x%X.\n",
index 1f345a5..4f4a645 100644 (file)
@@ -901,9 +901,20 @@ enum i40e_status_code i40e_nvmupd_command(struct i40e_hw *hw,
                        *((u16 *)&bytes[2]) = hw->nvm_wait_opcode;
                }
 
+               /* Clear error status on read */
+               if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR)
+                       hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
+
                return I40E_SUCCESS;
        }
 
+       /* Clear status even it is not read and log */
+       if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) {
+               i40e_debug(hw, I40E_DEBUG_NVM,
+                          "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n");
+               hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
+       }
+
        switch (hw->nvmupd_state) {
        case I40E_NVMUPD_STATE_INIT:
                status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
@@ -1253,6 +1264,7 @@ retry:
 void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode)
 {
        if (opcode == hw->nvm_wait_opcode) {
+
                i40e_debug(hw, I40E_DEBUG_NVM,
                           "NVMUPD: clearing wait on opcode 0x%04x\n", opcode);
                if (hw->nvm_release_on_done) {
@@ -1261,6 +1273,11 @@ void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode)
                }
                hw->nvm_wait_opcode = 0;
 
+               if (hw->aq.arq_last_status) {
+                       hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR;
+                       return;
+               }
+
                switch (hw->nvmupd_state) {
                case I40E_NVMUPD_STATE_INIT_WAIT:
                        hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
index 3784c8f..56e47ea 100644 (file)
@@ -499,6 +499,7 @@ enum i40e_nvmupd_state {
        I40E_NVMUPD_STATE_WRITING,
        I40E_NVMUPD_STATE_INIT_WAIT,
        I40E_NVMUPD_STATE_WRITE_WAIT,
+       I40E_NVMUPD_STATE_ERROR
 };
 
 /* nvm_access definition and its masks/shifts need to be accessible to
@@ -1526,6 +1527,7 @@ struct i40e_hw_port_stats {
 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR                0x3A
 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR       0x3B
 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR       0x3C
+#define I40E_SR_PHY_ACTIVITY_LIST_PTR          0x3D
 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR         0x3E
 #define I40E_SR_SW_CHECKSUM_WORD               0x3F
 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR    0x40