net/ixgbe/base: support 2.5G KX physical layer
authorWei Dai <wei.dai@intel.com>
Tue, 18 Apr 2017 06:57:01 +0000 (14:57 +0800)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 28 Apr 2017 12:46:17 +0000 (14:46 +0200)
Add another define for the 2.5G KX physical layer. This requires all
variables and support functions that deal with "physical_layer" to be
bumped to u64 as this is the 33rd define.

Signed-off-by: Wei Dai <wei.dai@intel.com>
Tested-by: Yuan Peng <yuan.peng@intel.com>
13 files changed:
drivers/net/ixgbe/base/ixgbe_82598.c
drivers/net/ixgbe/base/ixgbe_82598.h
drivers/net/ixgbe/base/ixgbe_82599.c
drivers/net/ixgbe/base/ixgbe_82599.h
drivers/net/ixgbe/base/ixgbe_api.c
drivers/net/ixgbe/base/ixgbe_api.h
drivers/net/ixgbe/base/ixgbe_phy.c
drivers/net/ixgbe/base/ixgbe_phy.h
drivers/net/ixgbe/base/ixgbe_type.h
drivers/net/ixgbe/base/ixgbe_x540.c
drivers/net/ixgbe/base/ixgbe_x540.h
drivers/net/ixgbe/base/ixgbe_x550.c
drivers/net/ixgbe/base/ixgbe_x550.h

index 724dcbb..d64abb2 100644 (file)
@@ -1222,9 +1222,9 @@ STATIC s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
  *
  *  Determines physical layer capabilities of the current configuration.
  **/
-u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
+u64 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
 {
-       u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
+       u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
        u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
        u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
        u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
index 0326e70..20aab9f 100644 (file)
@@ -45,7 +45,7 @@ s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
                                u8 *eeprom_data);
-u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
+u64 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);
index 832242e..d9d11a8 100644 (file)
@@ -2169,9 +2169,9 @@ s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
  *
  *  Determines physical layer capabilities of the current configuration.
  **/
-u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
+u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
 {
-       u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
+       u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
        u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
        u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
        u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
index c034d3d..d555dbc 100644 (file)
@@ -57,7 +57,7 @@ s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
-u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
+u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val);
 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 reg_val, bool locked);
index 270a97d..4117fb0 100644 (file)
@@ -1579,7 +1579,7 @@ s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
  *
  *  Determines physical layer capabilities of the current configuration.
  **/
-u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
+u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
 {
        return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
                               (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
index af85d4e..2f532aa 100644 (file)
@@ -143,7 +143,7 @@ s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw);
 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data);
-u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);
+u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);
 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);
 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw);
 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw);
index f44a11e..62c3080 100644 (file)
@@ -1575,9 +1575,9 @@ err_read_i2c_eeprom:
  *
  *  Determines physical layer capabilities of the current SFP.
  */
-s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
+u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
 {
-       u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
+       u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
        u8 comp_codes_10g = 0;
        u8 comp_codes_1g = 0;
 
index 820d471..cf8cadd 100644 (file)
@@ -192,7 +192,7 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);
 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
-s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw);
+u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw);
 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
                                        u16 *list_offset,
index 6acd966..bda8558 100644 (file)
@@ -3410,24 +3410,25 @@ typedef u32 ixgbe_link_speed;
                                         IXGBE_LINK_SPEED_10GB_FULL)
 
 /* Physical layer type */
-typedef u32 ixgbe_physical_layer;
+typedef u64 ixgbe_physical_layer;
 #define IXGBE_PHYSICAL_LAYER_UNKNOWN           0
-#define IXGBE_PHYSICAL_LAYER_10GBASE_T         0x0001
-#define IXGBE_PHYSICAL_LAYER_1000BASE_T                0x0002
-#define IXGBE_PHYSICAL_LAYER_100BASE_TX                0x0004
-#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU       0x0008
-#define IXGBE_PHYSICAL_LAYER_10GBASE_LR                0x0010
-#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM       0x0020
-#define IXGBE_PHYSICAL_LAYER_10GBASE_SR                0x0040
-#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4       0x0080
-#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4       0x0100
-#define IXGBE_PHYSICAL_LAYER_1000BASE_KX       0x0200
-#define IXGBE_PHYSICAL_LAYER_1000BASE_BX       0x0400
-#define IXGBE_PHYSICAL_LAYER_10GBASE_KR                0x0800
-#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI      0x1000
-#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA     0x2000
-#define IXGBE_PHYSICAL_LAYER_1000BASE_SX       0x4000
-#define IXGBE_PHYSICAL_LAYER_10BASE_T          0x8000
+#define IXGBE_PHYSICAL_LAYER_10GBASE_T         0x00001
+#define IXGBE_PHYSICAL_LAYER_1000BASE_T                0x00002
+#define IXGBE_PHYSICAL_LAYER_100BASE_TX                0x00004
+#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU       0x00008
+#define IXGBE_PHYSICAL_LAYER_10GBASE_LR                0x00010
+#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM       0x00020
+#define IXGBE_PHYSICAL_LAYER_10GBASE_SR                0x00040
+#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4       0x00080
+#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4       0x00100
+#define IXGBE_PHYSICAL_LAYER_1000BASE_KX       0x00200
+#define IXGBE_PHYSICAL_LAYER_1000BASE_BX       0x00400
+#define IXGBE_PHYSICAL_LAYER_10GBASE_KR                0x00800
+#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI      0x01000
+#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA     0x02000
+#define IXGBE_PHYSICAL_LAYER_1000BASE_SX       0x04000
+#define IXGBE_PHYSICAL_LAYER_10BASE_T          0x08000
+#define IXGBE_PHYSICAL_LAYER_2500BASE_KX       0x10000
 
 /* Flow Control Data Sheet defined values
  * Calculation and defines taken from 802.1bb Annex O
@@ -3906,7 +3907,7 @@ struct ixgbe_mac_operations {
        s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
        void (*enable_relaxed_ordering)(struct ixgbe_hw *);
        enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
-       u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
+       u64 (*get_supported_physical_layer)(struct ixgbe_hw *);
        s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
        s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
        s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);
index f624d55..0e51813 100644 (file)
@@ -329,9 +329,9 @@ out:
  *
  *  Determines physical layer capabilities of the current configuration.
  **/
-u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
+u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
 {
-       u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
+       u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
        u16 ext_ability = 0;
 
        DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
index e4baf6f..8a19ae2 100644 (file)
@@ -43,7 +43,7 @@ s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
                              bool link_up_wait_to_complete);
 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw);
 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw);
-u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw);
+u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw);
 
 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw);
 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data);
index a48155c..32786f8 100644 (file)
@@ -3673,9 +3673,9 @@ s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
  *
  *  Determines physical layer capabilities of the current configuration.
  **/
-u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
+u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
 {
-       u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
+       u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
        u16 ext_ability = 0;
 
        DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em");
@@ -3684,6 +3684,20 @@ u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)
 
        switch (hw->phy.type) {
        case ixgbe_phy_x550em_kr:
+               if (hw->mac.type == ixgbe_mac_X550EM_a) {
+                       if (hw->phy.nw_mng_if_sel &
+                           IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
+                               physical_layer =
+                                       IXGBE_PHYSICAL_LAYER_2500BASE_KX;
+                               break;
+                       } else if (hw->device_id ==
+                                  IXGBE_DEV_ID_X550EM_A_KR_L) {
+                               physical_layer =
+                                       IXGBE_PHYSICAL_LAYER_1000BASE_KX;
+                               break;
+                       }
+               }
+               /* fall through */
        case ixgbe_phy_x550em_xfi:
                physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |
                                 IXGBE_PHYSICAL_LAYER_1000BASE_KX;
index 30ca5df..6d18874 100644 (file)
@@ -88,7 +88,7 @@ s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw);
 s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw);
 s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw);
 s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw);
-u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw);
+u64 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw);
 void ixgbe_disable_rx_x550(struct ixgbe_hw *hw);
 s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed);
 s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw);