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net/ice/base: add helper function for boost TCAM match
2021-09-21 Qi Zhangnet/ice/base: add helper function for boost TCAM match
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: add parser runtime skeleton
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: init XLT key builder for parser
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: init flag redirect table for parser
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: init protocol group table for parser
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: init marker group table for parser
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: init ptype marker TCAM table for parser
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: init boost TCAM table for parser
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: init parse graph CAM table for parser
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: init metainit table for parser
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: init IMEM table for parser
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: add parser create and destroy skeleton
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: update auto-generated hardware register
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: support SMA controller
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: add get/set functions for shared parameters
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: add GCO defines and GCO flex descriptor
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: add helper to check for 100M speed support
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: add package segment ID
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: allow tool access to manageability register
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: change address parameter to 16-bit
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: allow to enable LAN and loopback in switch
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: use macro instead of open-coded division
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: include more E810T adapters
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-21 Qi Zhangnet/ice/base: calculate logical PF ID
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-09-06 Qi Zhangnet/ice: fix performance with writeback policy
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-29 Qi Zhangnet/ice: fix RXDID default value in DCF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: increase maximum TCAM/PTG per profile
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: fix typo in comment
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: rename and add setter for unicast MAC...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support flow director for GTPU UL/DL...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: enable jumbo frame during HW init
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support RSS for IPv4/L4 checksum
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support flow director for GTPoGRE
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: enable NVM update reset capabilities
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support RSS for GTPoGRE
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support flow director for GTPU EH inner...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support RSS for GRE tunnel
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support flow director for GRE tunnel
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support TC nodes PIR configuration
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: refine MAC rule adding
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add new AQ description
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: implement firmware debug dump
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add E810T check function
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: support starting PHY in bypass mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: clarify comments on checking PFC mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: implement Vernier calibration for E822
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: print human-friendly PHY types
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add accessors to get/set time reference
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add clock initialization function
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add timestamp masks
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: change dummy packets with VLAN
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add ethertype IPv6 check for dummy packet
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add functions for device clock control
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add IEEE 1588 capability probing
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-02 Qi Zhangdoc: update matching versions in ice guide
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/ice: fix data path in secondary process
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/ice: fix data path selection in secondary process
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/ice/base: remove unncessary code
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/ice/base: remove VSI info from previous aggregator
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/ice/base: remove firmware log
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/ice/base: add function for DSCP configure
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/iavf: fix handling of unsupported promiscuous
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-05-10 Qi Zhangnet/ice/base: remove dead code in capabilities parsing
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-30 Qi Zhangnet/ice/base: support IP fragment RSS and FDIR
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-30 Qi Zhangnet/ice/base: sign external device package programming
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-30 Qi Zhangnet/ice/base: support L3 DSCP QoS
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-30 Qi Zhangnet/ice/base: log if DDP/FW do not support QinQ
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-30 Qi Zhangnet/ice/base: refactor post DDP download VLAN mode...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-30 Qi Zhangnet/ice/base: add IP fragment flags
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-26 Qi Zhangcommon/iavf: use macro to define offload/capability
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-26 Qi Zhangcommon/iavf: refine comment in virtual channel
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-26 Qi Zhangcommon/iavf: add enumeration for Rx descriptor ID
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-26 Qi Zhangcommon/iavf: fix duplicated offload bit
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-19 Qi Zhangdoc: update matching versions in ice guide
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-19 Qi Zhangdoc: fix matching versions in ice guide
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: allow GTP-U filter using only inner protocols
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: add packet type for PPPoL2TPv2oUDP
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: fix QinQ PPPoE dummy packet selection
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: add inner VLAN protocol type for QinQ...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: add set/get GPIO helper functions
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: enable I2C read/write commands
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: add priority check of matching recipe
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: change protocol ID for VLAN in DVM
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: support PPPoL2TPv2oUDP RSS hash
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: set MAC type for E823C device
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: remove unused ptype field in PTT definition
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: print link configure error
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: support removing VSI from flow profile
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: cleanup code
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/igc: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/ixgbe: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/ice: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/iavf: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/i40e: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/e1000: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/fm10k: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangethdev: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-30 Qi Zhangnet/ice: refine RSS configure
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-29 Qi Zhangnet/iavf: fix TSO max segment size
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-24 Qi Zhangnet/ice/base: fix memory allocation for MAC addresses
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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