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net/ice/base: support starting PHY in bypass mode
2021-08-11 Qi Zhangnet/ice/base: support starting PHY in bypass mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: clarify comments on checking PFC mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: implement Vernier calibration for E822
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: print human-friendly PHY types
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add accessors to get/set time reference
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add clock initialization function
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add timestamp masks
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: change dummy packets with VLAN
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add ethertype IPv6 check for dummy packet
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add functions for device clock control
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-11 Qi Zhangnet/ice/base: add IEEE 1588 capability probing
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-08-02 Qi Zhangdoc: update matching versions in ice guide
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/ice: fix data path in secondary process
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/ice: fix data path selection in secondary process
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/ice/base: remove unncessary code
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/ice/base: remove VSI info from previous aggregator
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/ice/base: remove firmware log
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/ice/base: add function for DSCP configure
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-06-10 Qi Zhangnet/iavf: fix handling of unsupported promiscuous
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-05-10 Qi Zhangnet/ice/base: remove dead code in capabilities parsing
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-30 Qi Zhangnet/ice/base: support IP fragment RSS and FDIR
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-30 Qi Zhangnet/ice/base: sign external device package programming
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-30 Qi Zhangnet/ice/base: support L3 DSCP QoS
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-30 Qi Zhangnet/ice/base: log if DDP/FW do not support QinQ
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-30 Qi Zhangnet/ice/base: refactor post DDP download VLAN mode...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-30 Qi Zhangnet/ice/base: add IP fragment flags
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-26 Qi Zhangcommon/iavf: use macro to define offload/capability
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-26 Qi Zhangcommon/iavf: refine comment in virtual channel
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-26 Qi Zhangcommon/iavf: add enumeration for Rx descriptor ID
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-26 Qi Zhangcommon/iavf: fix duplicated offload bit
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-19 Qi Zhangdoc: update matching versions in ice guide
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-19 Qi Zhangdoc: fix matching versions in ice guide
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: allow GTP-U filter using only inner protocols
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: add packet type for PPPoL2TPv2oUDP
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: fix QinQ PPPoE dummy packet selection
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: add inner VLAN protocol type for QinQ...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: add set/get GPIO helper functions
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: enable I2C read/write commands
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: add priority check of matching recipe
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: change protocol ID for VLAN in DVM
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: support PPPoL2TPv2oUDP RSS hash
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: set MAC type for E823C device
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: remove unused ptype field in PTT definition
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: print link configure error
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: support removing VSI from flow profile
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-13 Qi Zhangnet/ice/base: cleanup code
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/igc: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/ixgbe: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/ice: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/iavf: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/i40e: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/e1000: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangnet/fm10k: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-04-01 Qi Zhangethdev: refine debug build option
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-30 Qi Zhangnet/ice: refine RSS configure
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-29 Qi Zhangnet/iavf: fix TSO max segment size
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-24 Qi Zhangnet/ice/base: fix memory allocation for MAC addresses
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: cleanup filter list on error
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: fix uninitialized struct
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: update GTPU EH dummy packets for FDIR
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: update boost TCAM for DVM
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: mark ptype 2 as reserved
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: fix payload indicator on ptype
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: support GTPU IP inner IPv6 for flow director
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: support switch filter (GTP tunnel+IP...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: enable more GTPU inner L3 fields for...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: expose link configuration error
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: enable GTPU inner L3/L4 for flow director
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: indicate double reset solution restriction
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: support external device secure programming
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-03-05 Qi Zhangnet/ice/base: support firmware log
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-02-10 Qi Zhangethdev: refine doxygen comment of UDP tunnel API
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-29 Qi Zhangnet/ice: support E823C family devices
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-29 Qi Zhangnet/ice/base: support configuring device in double...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-29 Qi Zhangnet/ice/base: add VLAN TPID for VLAN filters
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-29 Qi Zhangnet/ice/base: fix outer VLAN related macro
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-13 Qi Zhangcommon/iavf: update copyright date
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-13 Qi Zhangcommon/iavf: support VLAN offload by DCF
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-13 Qi Zhangcommon/iavf: support new VLAN capabilities
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: update copyright date
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: update add scheduler node counter
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: cleanup style
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: support GTPU inner for AVF flow director
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: limit forced overrides based on FW version
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: fix memory handling
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: add package ptype enable information
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: remove deprecated field
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: align add VSI and update VSI AQ command...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: refactor structure field
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: remove unused struct member
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: support eCPRI over UDP type 0 flow
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: support eCPRI over MAC type 0 flow
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: align macro names to specification
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: use report default config to get PHY...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: fix null pointer dereference
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: modify recursive way of adding nodes
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: change get PHY capability log level
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: resend some AQ commands when EBUSY
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: support checking double VLAN mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: fix tunnel destroy
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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